ISE project file can be created by executing "make project" command.
All configurations are in "config.tcl" script file.
# Targets desctiption:
+# - project : Creates ISE project file, which can be opened in ISE IDE. HDL
+# source files are added according to the $PRJ variable content.
+# Configuration of project is moved to the config.tcl script file.
+# All parameters which can be configured in IDE are accessible
+# from this TCL script file. For more information execute 'xtclsh'
+# and type 'help'.
# - synthesize : Synthesize all VHDL and Verilog source files, libraries, etc.
# defined in PRJ files and produces NGC file.
# - translate : Translate all netlist files (.ngc, ...) into the NGD file,
BMM_LOCAL = $(notdir $(BMM))
BMM_LOCAL_BD = $(basename $(BMM_LOCAL))_bd$(suffix $(BMM))
+ISE = $(TOP).ise
NGC = $(TOP).ngc
NGD = $(TOP).ngd
PCF = $(TOP).pcf
NCD_MAP = $(TOP)_map.ncd
NCD = $(TOP).ncd
+SRCPRJ = $(addprefix $(SRC),/$(PRJ))
+
#===============================================================================
.PHONY: all synthesize translate map par implement download download-only clean
#===============================================================================
+project: $(ISE)
+$(ISE): $(SRCPRJ) config.tcl
+ifneq ($(strip $(BMM)),)
+ ln -sf $(SRC)/$(BMM) $(BMM_LOCAL)
+endif
+ rm -f *.ise* *.restore
+ xtclsh create.tcl $(ISE) $(SRCPRJ)
+ xtclsh config.tcl $(ISE)
+
+
synthesize: $(NGC)
re-synthesize $(NGC): $(addprefix $(SRC)/,$(PRJ))
echo " \
#===============================================================================
clean:
- ls | grep -v ^Makefile$$ | xargs rm -rf
- rm -f $(addprefix $(SRC)/,$(PRJ:.prj=.d))
+ ls | grep -v ^Makefile$$ | grep -v .tcl$$ | xargs rm -rf
+ rm -f $(SRCPRJ:.prj=.d)
make -C $(SRC)/$(SW_SRC) distclean
#===============================================================================
--- /dev/null
+# xtclsh config.tcl <project.ise>
+#===============================================================================
+
+if {$argc != 1} {
+ puts "ERROR: there is wrong number of arguments, see source file..."
+ exit 1
+}
+
+
+project open [lindex $argv 0]
+
+
+# Device
+project set "family" virtex2
+project set "device" xc2v1000
+project set "package" fg456
+project set "speed" -6
+
+# Top.level entity
+project set "top" /msp_motion
+
+# BLock memory map file
+xfile add memory.bmm
+
+# User constraints file
+xfile add ../msp_motion.ucf
+
+# Verilog Include directory
+project set "Verilog Include Directories" "../openmsp430/top/top_8_32_mul_dbus/"
+
+# Partitions
+partition new /msp_motion/openMSP430_1
+partition new /msp_motion/openMSP430_1/uart_0
+partition new /msp_motion/mcc_1
+
+# Keep Hierarchy
+project set "Keep Hierarchy" "Soft"
+
+
+project close
--- /dev/null
+# xtclsh create.tcl <project.ise> <sources1.prj> <sources2.prj> ...
+#===============================================================================
+
+proc xfile_add_prj prj {
+ set f [open $prj]
+ set dir [file dirname $prj]
+
+ while {[gets $f line] >= 0} {
+ set l [string trim $line]
+ regsub "#.*" $l "" l
+ regsub -all "\t" $l " " l
+ regsub -all " +" $l " " l
+
+ if {[string length $l] > 5} {
+ set list [split $l " "]
+ set lib [lindex $list 1]
+ set src $dir/[lindex $list 2]
+
+ puts [format "Adding (%s) %s" $lib $src]
+
+ xfile add $src
+ }
+ }
+
+ close $f
+}
+
+#===============================================================================
+
+if {$argc < 2} {
+ puts "ERROR: there are missing arguments, see source file..."
+ exit 1
+}
+
+
+project new [lindex $argv 0]
+
+for {set i 1} {$i < $argc} {incr i} {
+ xfile_add_prj [lindex $argv $i]
+}
+
+project close
+