]> rtime.felk.cvut.cz Git - fpga/virtex2/msp_motion.git/commit
projects / fpga / virtex2 / msp_motion.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 5003c3b) | patch
PWM output polarity inverted.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 21:48:36 +0000 (23:48 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 21:48:36 +0000 (23:48 +0200)
commitdea7f319282d48c6279e4764ce66bcf0318f2cb7
tree6a73dee5d16944b014a0b8ce9f8567d0ca69c5dctree | snapshot
parent5003c3b6cc021dc3377b51c8c21f439a46b072aacommit | diff
PWM output polarity inverted.

Inverted to correspond with power electronic board LP_MPW1 where
PWM input signals are inverted too.
msp_motion.vhd diff | blob | history
MSP430 BLDC control HW and PXMC SW - top level design for Virtex 2 V2MB1000 board