Keeping hierarchy during hardware synthesis.

Does not propagate to place & route stage, so optimization is still
working. But we can see in  floorplan which part of FPGA implements
which entity.

diff --git a/build/Makefile b/build/Makefile
index 6eb12ffc927c1b52bc5cccd02530a68862ff80b5..fa08461a8802bebadb368308621100d7ca095b20 100644 (file)
--- a/build/Makefile
+++ b/build/Makefile
@@ -105,6 +105,7 @@ re-synthesize $(NGC): $(addrefix $(SRC)/,$(PRJ))
          -top $(TOP) \
          -p $(DEVICE) \
          -opt_mode Speed \
+          -keep_hierarchy soft \
          -opt_level 1" | xst | tee xst.log