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(parent: bd1e41d) | patch
Keeping hierarchy during hardware synthesis.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Fri, 27 May 2011 06:11:04 +0000 (08:11 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Fri, 27 May 2011 06:11:04 +0000 (08:11 +0200)
commitbb6b940d288b29282f2429b4cdb9c92effd7ac94
tree1287b66de930a3d0c793c85face8a55dac6cfa5ctree | snapshot
parentbd1e41d6e288374d780132b9ebdccb2c785ec9d1commit | diff
Keeping hierarchy during hardware synthesis.

Does not propagate to place & route stage, so optimization is still
working. But we can see in  floorplan which part of FPGA implements
which entity.
build/Makefile diff | blob | history
MSP430 BLDC control HW and PXMC SW - top level design for Virtex 2 V2MB1000 board