2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.STD_LOGIC_ARITH.ALL;
4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
6 entity omsp_quadcount is
8 ADDR : std_logic_vector (15 downto 0) := X"0150");
11 per_addr : in std_logic_vector (7 downto 0);
12 per_din : in std_logic_vector (15 downto 0); -- unused
13 per_en : in std_logic;
14 per_wen : in std_logic_vector (1 downto 0); -- unused
15 puc : in std_logic; -- unused
16 per_irq_acc : in std_logic; -- unused
17 per_irq : out std_logic;
18 per_dout : out std_logic_vector (15 downto 0);
20 qcount : in std_logic_vector (31 downto 0)
24 --------------------------------------------------------------------------------
26 architecture behavioral of omsp_quadcount is
28 -- When reading whole 32-bit qcount input, first QCNTL has to be loaded, because
29 -- this event causes QCNTH to latch appropriate value of qcount. This procedure
30 -- ensures that correct value is readed.
32 -- qcount lower word logic address
33 constant QCNTL : std_logic_vector (15 downto 0) := ADDR;
34 -- qcount higher word logic address
35 constant QCNTH : std_logic_vector (15 downto 0) := ADDR + 2;
37 signal qcntl_sel : boolean;
38 signal qcnth_sel : boolean;
40 signal qcnth_latch : std_logic_vector (15 downto 0) := (others => '0');
42 signal qcount_prev : std_logic_vector (31 downto 0) := (others => '0');
44 --------------------------------------------------------------------------------
48 qcntl_sel <= (per_addr = QCNTL(8 downto 1)) and (per_en = '1');
49 qcnth_sel <= (per_addr = QCNTH(8 downto 1)) and (per_en = '1');
51 per_dout <= qcount (15 downto 0) when qcntl_sel else
52 qcnth_latch when qcnth_sel else
58 if (rising_edge(mclk) and qcntl_sel) then
59 qcnth_latch <= qcount (31 downto 16);
63 -- Generation of IRQ signal. (changes in lower 2 bits are suppresed)
66 if (rising_edge(mclk)) then
67 qcount_prev <= qcount;
71 elsif (qcount_prev (31 downto 2) /= qcount (31 downto 2)) then