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RX modul synchronization changed to falling edges.
[fpga/uart.git] / baud_gen.vhd
2011-02-04 Vladimir BurianBaud generator ClockEnable added. blob | commitdiff | raw
2011-01-28 Vladimir BurianSome comments added. blob | commitdiff | raw | diff to current
2011-01-22 Vladimir BurianBaud_gen scale input width redefined as generic. Defaul... blob | commitdiff | raw | diff to current
2011-01-22 Vladimir BurianFirst working prototype of HW UART - TX part. blob | commitdiff | raw | diff to current
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