library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity baud_gen is
  generic (
    SCALE_WIDTH : integer := 16
  );
  port (
    clk      : in  std_logic;
    reset    : in  std_logic;
    scale    : in  std_logic_vector (SCALE_WIDTH-1 downto 0);
    clk_baud : out std_logic
  );
end baud_gen;

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architecture behavioral of baud_gen is

  signal counter    : std_logic_vector (SCALE_WIDTH-1 downto 0);
  signal clk_baud_s : std_logic;

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begin

  process (clk, reset)
  begin
    if (reset = '1') then
      counter <= (others => '0');
      clk_baud_s <= '0';
      
    elsif (rising_edge(clk)) then
      if (counter = 0) then
        counter <= scale;
        clk_baud_s <= not clk_baud_s;
        
      else
        counter <= counter - 1;

      end if;
    end if;
  end process;

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  clk_baud <= clk_baud_s;
  
end behavioral;