rtime.felk.cvut.cz Git - sojka/nv-tegra/linux-3.10.git/log

ARM64: DT: tegra210: disable KSO mode dump

Disable SDMMC register dump after errors
like command index error in KSO sleep mode
for Jetson-cv board

bug 200138403

Change-Id: Iad087a16de2caa270c1fc30dbd0fe76da99c2792
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/824721
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

mmc: host: tegra: disable kso mode reg dump

On platforms with Broadcom Wifi over SDIO
support register dump in KSO sleep is disabled

bug 200138403

Change-Id: I49bded4df12fd0ce83be5bd791f4a9bd2e98b5b7
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/824720
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

bindings: mmc: tegra: disable SDIO register dump

Platforms with Broadcom Wifi over SDIO support
may use attribute
nvidia,bcm-sdio-supress-kso-dump to suppress
register dump in KSO sleep mode.

bug 200138403

Change-Id: Ib7258be0023df53cdf0f3910f947b5e56b5e2f82
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/824719
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

p2360: Add support for max20024-rtc

bug 200138527
bug 1687264

Change-Id: I8dc4c84e1e62aa11d87b1f874add89f37651ec40
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/833904
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshagiri Holi <sholi@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>

media: v4l2-core: Migration from upstream

Adds required upstream files to support
unified VI driver
Add minimal changes in existing files without
breaking the current interface

Bug 1617777

Change-Id: Iaa2b63aed4ac028fd3b3a7920a3781d7186ca03f
Signed-off-by: Bhanu Murthy V <bmurthyv@nvidia.com>
Reviewed-on: http://git-master/r/786823
(cherry picked from commit 230d024056fb256a741ac4da94624f463cad6574)
Reviewed-on: http://git-master/r/832143
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

drivers: Restructure GRHOST_VI

Remove GRHOST_VI. VI code moved from
drivers/video/tegra/host/ to
drivers/media/platform/tegra/vi/

Bug 1617777

Change-Id: I54350ddf178229c9975419a77d2fe0d9836e844f
Signed-off-by: Bhanu Murthy V <bmurthyv@nvidia.com>
Reviewed-on: http://git-master/r/825018
(cherry picked from commit 9bf60d57e2ddbc273e25ce7cb022ebaacedaac3a)
Reviewed-on: http://git-master/r/832137
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arch: arm64: configs: Moving VI config

Remove GRHOST_VI as part of defconfig
Add TEGRA_VI for l4t to compile as module

Bug 1617777

Change-Id: Ia48be53d8529ab35a438a8abc16a94e7e38d83db
Signed-off-by: Bhanu Murthy V <bmurthyv@nvidia.com>
Reviewed-on: http://git-master/r/825017
(cherry picked from commit d9aed46d431443740cd82b15fccbface2d8d2dc0)
Reviewed-on: http://git-master/r/832136
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

iio: proximity: IQS2x3 SAR v.20

- Add device tree options for the loop variables that checks for the RDY GPIO
signal.
- Update the documentation for this.

Bug 200137195

Change-Id: Ie2b482ef7e71d5932ceea40072dd086624f18017
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/831117
(cherry picked from commit 9fb5f2d04cef94818977e7ec2412ac09a118bad5)
Reviewed-on: http://git-master/r/833377
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>

drivers: usb: gadget: Add release fn for snd_uac2

Introducing a blank release fucntion to fix the warning issue
faced while unloading g_audio module.

Bug 200149372

Change-Id: Ia1fdd73ed2b1aa80f9d1bb2aed497ade6ed26608
Signed-off-by: Gaurav Singh <gaursingh@nvidia.com>
Reviewed-on: http://git-master/r/828208
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arm64: mm: dma-mapping: fix the overflow issue

Fix the overflow of variable "start" holding the start bit number.
It should be of same type mapping->bits, which is size_t, to avoid
overflow for IOVA range beyond 4GB boundary.

Bug 200150063

Change-Id: Ie2ab3ce12293beadac4a1a21d26ed6d1fef41176
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/834822
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

platform: tegra: pmc: silent debug print

pcm prod list not found list is made a
debug print as its not a mandatory error

Bug 200137939

Change-Id: I8b5523e015325ad940ff29b2b7ba1cad69d2d845
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/825874
(cherry picked from commit 5c9397de732d50acaf879ca1a77823a16410ac6e)
Reviewed-on: http://git-master/r/826864
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: disable ELPG while accessing gr_gpcs_tpcs_sm_sch_macro_sched_r

bug 200139995

Any GR register access should disable ELPG and clock gating before
access and enable it back after it is done. Disable ELPG while tweaking
perf parameters in gk20a_alloc_obj_ctx.

Also output NV_PBUS_INTR_0 in case of interrupt.

Change-Id: Ic9ddc514207ff91631dbd96c5ab0c70ebae0b6d1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/826272
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm64: tegra210: fix DT for node xusb_padctl

DT node xusb_padctl contains info to initialize PLLE and UPHY PLLs.

If pcie is enabled, xusb_padctl needs the following property copied
from pcie node:
nvidia,lane-map

If sata is enabled, xusb_padctl needs the following property copied
from sata node:
nvidia,enable-sata-port

XUSB uses the following property to assign lanes:
nvidia,lane_owner

To initialize PLLE and UPHY PLLs, xusb_padctl needs to know power
rails below:
avdd_pll_uerefe-supply
hvdd_pex_pll_e-supply
dvdd_pex_pll-supply
hvddio_pex-supply
dvddio_pex-supply
hvdd_sata-supply
dvdd_sata_pll-supply
hvddio_sata-supply
dvddio_sata-supply

Bug 1685150

DEPENDS ON: < None >

Change-Id: I5d3d227883d8c3f2148c9ea218f1312a2b54c20a
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/815639
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit

arm64: max77620: jetson-cv: update fps-time-period

Fix fps-time-period for Jetson-CV board as provided by syseng

Bug 200149755

Change-Id: Ia1be5dc98143b6b25821235381dbd191b3803893
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/829392
(cherry picked from commit cdddc523aafea574cd2d83d6f3455ae403b27354)
Reviewed-on: http://git-master/r/833318
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>

arm64: t210: config: enable Intel 82576 NIC driver

Bug 200144579

Change-Id: Ibadbd0418914844a1d6613cdf3a6bdb5c5eee785
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/832155
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arm64: t210: ksavedefconfig formatted output

Bug 200144579

Change-Id: I95b3636fd2786a5c144445cc16e687031d769880
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/832154
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arm: dts: p2360: HDMI: Golden register update

Update golden register fields as per latest QUAL for HDMI on p2360

bug 200104478

Change-Id: I8fbe6a01088b058d40ccb37614ab8a4147c84822
Reviewed-on: http://git-master/r/789476
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: http://git-master/r/826960
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers: video: tegra: sor: Updated sor GR's

Bug 200104480

Change-Id: I8d581b384b339675e761ccf7bf87cffad4efa2db
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: http://git-master/r/819544
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>

resource: Coverity fixes

Coverity fixes
Initializing counter 'l' to 0 in 'r_next', which is
incremented to keep track of the resource position during
resource tree traversal.

Coverit ID 13503

Bug 200083369

Change-Id: Iea3d1390686b4c418a9bf40571921dbd9ca8d2fa
Signed-off-by: Pavitrakumar <pavitrak@nvidia.com>
Reviewed-on: http://git-master/r/759698
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

tegra: pm: Coverity fixes

Coverity fixes
Initialized pps.affinity_level field to 0; this was left
un-initialized and coverity complained about this.

Coverity ID 18088

Bug 200083369

Change-Id: I1b297b57e69c879e437b606b1c04694605146dd2
Signed-off-by: Pavitrakumar <pavitrak@nvidia.com>
Reviewed-on: http://git-master/r/759603
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

arm64: tegra210: add device node xusb_padctl

Rename the node from padctl to xusb_padctl and add properties:

nvidia,lane-map: assign lanes for PCIE driver
nvidia,enable-sata-port: specify if SATA driver will use lane or not

Add power rails necessary for UPHY.

Bug 200068549
Bug 1682515

Change-Id: Iae2708211267ccb564dad32be90561827350608d
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/831714
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Carl Dong <carld@nvidia.com>
Reviewed-by: Hayden Du <haydend@nvidia.com>

drivers: media: soc_camera: IMX230 driver to gain

Updating IMX230 driver to have it's own to gain function.

Bug 1654210

Change-Id: Iedd8303a3cce61c5de9a272343248bc86b4bca7d
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/831854
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bhanu Murthy V <bmurthyv@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

drivers: media: platform: tegra: get gpio pwr info

Add support to get power status (on/off) of a GPIO used by isc-mgr to
turn on/off isc devices

Bug 1698463

Change-Id: I6a01c610a2bd41027eb04158514887ae5ed67234
Signed-off-by: Anurag Dosapati <adosapati@nvidia.com>
Reviewed-on: http://git-master/r/830964
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Songhee Baek <sbaek@nvidia.com>
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>

iio: proximity: IQS2x3 SAR v.19

- Add generic external status function for WARs.
  When called by an external driver an ATI redo is done.
- Add the ability to spew just the SAR GPIO status to the kernel log.
- Add ability to spew just the external state to the kernel log when the call
  is made.
- Add a DT option to make visible and hide the SAR sensors from the OS by
  changing the case ("SAR" vs. "sar") in the sensor name.  If os_options is > 0
  then the lower case name is used allowing the NVS HAL to find the sensors.
  Otherwise the sensor names use "SAR" and is hidden from the OS.

Bug 200137195

Change-Id: I4163f3ab30fc9e3292f3171dd98f88c8896a079e
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/826194
(cherry picked from commit 740de03f84ae5f7fd4d95f6ede3099876306ea2f)
Reviewed-on: http://git-master/r/831999
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>

iio: light: Add WAKE_ON capability

- Add ability to wake AP from proximity (WAKE_ON) sensors.
- Add proximity debug dump.
- Add NVS light and proximity module versioning.
- Fix light enable initial poll delay.
- Add CM32180 ARA WAR device tree configuration option.  If enabled, the WAR
  does an ARA before every I2C transaction regardless of the interrupt GPIO
  status.  The DT option: ARA_WAR = <1>;
  This is an extension to the current WAR that tests the interrupt GPIO to
  determine if an ARA is needed.

Bug 200122255
Bug 200121777

Change-Id: Id334d165cd7f6962c47592392089c55e70b50d22
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/821953
(cherry picked from commit 51087b9001d2c851d620aa02de0098add7df998b)
Reviewed-on: http://git-master/r/831346
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>

ARM64: jetson: provide commands for power off from bootrom

Add support to power off system via bootrom. Add required commands
for bootrom from DT so that bootrom can issue the I2C commands.

Bug 200146310

Change-Id: Ib128af7f0982a154fc4068005169c58b7fa93fda
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/831324
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM64: t210: hawkeye: provide commands for power off from bootrom

Add support to power off system via bootrom. Add required commands
for bootrom from DT so that bootrom can issue the I2C commands.

bug 200146310

Change-Id: I8bba75d25a748ef2bd43031880d761965de1f2c9
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/829086

power: reset: max77620: add support to ignore final power off commands

Add support to not issue final power off commands for PMIC if there
is soc specific power off sequence is available.

This is required to do the power off sequence by SoC per their system
requirements.

bug 200146310

Change-Id: I932c2044d4f2942dd7e234185b88720ebcd676ee
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/829085

power: reset: system-pmic: add support to power off via soc specific

Add support to call the SoC specific power off calls when registerd
pm_power_off is not able to power off the system.

On this case, SoC provides the power off handler to do system power
off.

bug 200146310

Change-Id: I8a98825c33e05631c879028a651f510a895b6c3d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/829084

platform: tegra: pmc: add API to do system reset

Add APIs to do system reset through PMC.

bug 200146310

Change-Id: If89a68f29f85140e1d046c3f8a39da2293a3f0c7
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/829083

platform: tegra: bootrom: add support for power off commands

Add support for power off commands fro bootrom. The commands
are provided from DT as follows:
pmc {
bootrom-commands {
reset-commands {
};
power-off-commands {
};
};
};

If power off and reset commands are not available from child node
then properties and command in node bootrom-commands are used. This
is done to support backward compatibility.

The commands properties are same as earlier.

bug 200146310

Change-Id: I3a2102a20424c81310a7c96041884b24ce6e9e15
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/829082

platform: tegra: bootrom: fix pmc register config for commands

The number of PMC commands provided from DT is not fully written
into PMC register due to mishandling of index pointer.

Fix the index pointer handling to properly increment it.

bug 200146310

Change-Id: I6d300a050923052ebd356b62dc756dd6cf197beb
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/829081

drivers: soc_camera: sensor drivers update

Adding OV5693 V4L2 driver with timing, OTP, and
EEPROM controls. Updating IMX214 V4L2 driver group
hold control. Updating IMX214 and OV23850 dpd
control.

Bug 200143026.

Change-Id: I91d73ee3f54ca5a1df8ae38abf71d4f33331b664
Signed-off-by: David Wang <davidw@nvidia.com>
(cherry picked from commit e6415ba6abeca5e284a7560f9fcd260faf3d7c3f)
Reviewed-on: http://git-master/r/815427
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

drivers: soc_camera: add ov23850 OTP controls

enabling ov23850 driver with OTP and fuse id controls.

bug 1651635.

Change-Id: I0e9b4a72135730a5a55e986d1f3a2e064f3cc834
Signed-off-by: David Wang <davidw@nvidia.com>
(cherry picked from commit 6d3d3aa222a273bec33d630b18e1e30efda16882)
Reviewed-on: http://git-master/r/825097
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

ARM64: updating OV23850 boundary values

Updating OV23850 DT entry with correct boundary values
including pixel clock, min/max exposure and frame rate

bug 1651635.

Change-Id: Iacce0d94ae1e9ec0dfada7fd2bff6826fea4bf22
Signed-off-by: David Wang <davidw@nvidia.com>
(cherry picked from commit 7337b5d93b65c1b82317635392415547fced85ef)
Reviewed-on: http://git-master/r/825096
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

Revert "iio: proximity: SAR Stable Setting V1.2.3"

This reverts commit 7706a9b9170491e2c39fc3d54f60eeb011579fa2.

Change-Id: I02ca3757a469275b8a61c19dcfcc8fae36f025fb
Signed-off-by: Steve Rogers <srogers@nvidia.com>
Reviewed-on: http://git-master/r/829254
(cherry picked from commit 886e933e846f7139caee2432e36c40a8bde35ca2)
Reviewed-on: http://git-master/r/829413
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

gpu: nvgpu: rework private command buffer free path

We currently allocate private command buffers (wait_cmd
and incr_cmd) before submitting the job but we never
free them explicitly.
When private command queue of the channel is full, we
then try to recycle/remove free command buffers.
But this recycling happens during submit path, and
hence that particular submit path takes much longer

Rework this as below :
- add reference of command buffers to job structure
- when job completes, free the command buffers
explicitly
- remove the code to recycle buffers since it should
not be needed now

Note that command buffers need to be freed in order of
their allocation. Ensure this with error print before
freeing the command buffer entry

Bug 200141116
Bug 1698667

Change-Id: Id4b69429d7ad966307e0d122a71ad55076684307
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/827638
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

dt: otg: update doc with nvidia,enable-host-peripheral-transitions

Update the doc with dt node field enable-host-peripheral-transitions.
Enabling this will allow otg driver to allow host to peripheral
transitions and vice versa. And remove nvidia,enable-event-serialization.

Bug 1653886

Change-Id: Ifac1c1c46567f9c0a0164f85d4ecebc5b8a98532
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/827402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

usb: phy: tegra: allow host peripheral transitions

Allow otg state machine transitions from host to
pheripheral and vice-versa.

Bug 1653886

Change-Id: I55c6b6bcf7c5cc33ecfd8e9063faed88aa54ccc2
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/826937
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Haribabu Narayanan <hnarayanan@nvidia.com>
Tested-by: Haribabu Narayanan <hnarayanan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

xhci: tegra: fix for usb2 utmi pad power saving

USB2 pad PD bits can be set to save power when device is disconnected
or suspended. When device is connected or in resume state, we need to
clear these PD bits.

During boot, there is a case that CSC bit is cleared by hub init
function. This causes PD bits set and failures in port reset and set
address.

Bug 200146188

Change-Id: Id12deb97689ef08b3e9236124c2fc4775b039c3c
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/826136
GVS: Gerrit_Virtual_Submit
Reviewed-by: Henry Lin <henryl@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

tegra124: p2360: Use clock port 0 for PCI root port 1

bug 1657220

Change-Id: I647c029649c6be08635f79b6ae61acfc111b6290
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/801254
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

pci: tegra: Make clkport independent of root port

PCI driver assumes that PCI0 is bound to clock port 0 and PCI1 is bound
to clock port 1. This patch adds a DT property to make use of the below
combinations as well
PCI0 <--> Clock Port 1
PCI1 <--> Clock Port 0

bug 1657220

Change-Id: I01ff0285d1b1403f1ea15202119318fb489fbe8b
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/801253
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

p2360: Add support for C-sample

bug 200150801

Change-Id: I5c1a86afef20bfb17199d9a543ebf1684eefda5c
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/826900
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>

media: tegra_camera: fix potential race condition

Make sure increase sync point max value for arming the single shot.

Bug 1700868

Change-Id: I9a429150dad0851a3da34ee8ad75339728f3ed81
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/826439
(cherry picked from commit d20b72061fa57331fe16d311bfac035227e206ae)
Reviewed-on: http://git-master/r/827967
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

media: tegra_camera: introduce 2 kthreads for capture

Use one kthread to start capture a frame and wait for next frame start.
Before waiting, it will move the current buffer to another queue which
will be handled another kthread.

The second kthread (capture_done) will wait for memory output done sync
point event and handle the buffer to videobuffer2 framework as capture
done.

Bug 1686911

Change-Id: I6805e47ab5252aa75ba70f62747c845c7dd2ba71
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/824954
(cherry picked from commit 7f9af08d6e1e710c0444d0986b6324f884a3d688)
Reviewed-on: http://git-master/r/824965
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

media: tegra_camera: replace workqueue with kthread

Use kthread instead of workqueue, which will create a dedicated kernel
thread for capture.

Remove useless mutex and convert spin_lock_irq() to normal spin_lock().

Bug 1686911

Change-Id: Ie90320ccff9b46a53719bf8924afe38b24dda64c
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/824953
(cherry picked from commit d184f7a5ad79419a169c01e453af2c5ac41b5865)
Reviewed-on: http://git-master/r/824964
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

gpu: nvgpu: restart timer instead of cancel

In gk20a_fifo_handle_sched_error(), we currently cancel
the timeout on all the channels
But this could cause us to miss one of stuck channel

hence, instead of cancelling, restart the timeout of channel
on which it is already active

Bug 200133289

Change-Id: I40e7e0e5394911fc110ab6fde39592b885dfaf7d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/816133
(cherry picked from commit 7d249416f79e708f4825c9a7265becec0b8c6100)
Reviewed-on: http://git-master/r/820161
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/825508
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: fix deadlock on timeout lock

In gk20a_channel_timeout_stop(), we take the channel's
timeout lock and then cancel the timeout worker thread

Timeout worker thread also tries to acquire same timeout
lock.

Hence, while cancelling the timeout in gk20a_channel_timeout_stop()
if the timeout_handler is already scheduled, we will have a deadlock

Fix this by moving cancel_delayed_work_sync() out of the locks

Bug 200133289
Bug 1695481

Change-Id: Iea78770180b483a63e5e176efba27831174e9dde
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/815922
(cherry picked from commit a02bd3855ccc840daff3cbb34e379c7865501283)
Reviewed-on: http://git-master/r/820160
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/825507
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: cancel all wdt timeouts while handling SCHED errors

A SCHED error might cause multiple channels' watchdogs to trigger
simultaneously

Hence, to avoid this conflict cancel watchdog timeout on all
channels before recovering from SCHED errors

Also, define API gk20a_channel_timeout_stop_all_channels()
to cancel wdt timeout on all channels

Bug 200133289

Change-Id: I8324c397891f0a711327b77d0677cd6718af6d01
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/810959
(cherry picked from commit 1501d972d4ab1546737472d0469faacb6ed9eb18)
Reviewed-on: http://git-master/r/814255
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/825506
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

p2360: Add ina220 device

bug 200141952

Change-Id: I39d886c97d9cc378c994683a479658176baf996d
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/818630
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: set default channel timeout to 3s

We have another constant timeout of 5s for channel watchdog.
Hence drop default channel timeout (used for SCHED errors)
to 3s so that they both don't conflict with each other

Bug 200133289

Change-Id: Ieed675cad462119ff2f1a155a955c8a22cb6c6f8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/810958
(cherry picked from commit 1adc13570f5771f74d1acb621c7cde266f4612fc)
Reviewed-on: http://git-master/r/814254
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Change-Id: I78ac8f0fcd71190f5ca09a65983d031cff3347f0
Reviewed-on: http://git-master/r/815984
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

gpu: nvgpu: debugfs for ch_wdt timeout

export debugfs /d/gpu.0/ch_wdt_timeout_ms to modify
all channels' watchdog timeout

this is needed for testing purpose only

Bug 200133289

Change-Id: I8776b567d5d5a1c304334835b0bcab7b242cf0ab
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/810957
(cherry picked from commit 03739db3d28cf64b4065f9a7abca3ba77d5ced8f)
Reviewed-on: http://git-master/r/814253
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/815932
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

gpu: nvgpu: make wdt timeout per-platform

Channel watchdog timeout is set to a costant value of 5s
as of now

Make this timeout platform specific and set it to 5s for gm20b
and 7s for gk20a

Bug 200133289

Change-Id: I6e7f0fed93a8d5b197ae46807131311196c6636f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/810956
(cherry picked from commit f015c3db9aecf7756375a0529dad8cdbca964377)
Reviewed-on: http://git-master/r/814252
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Change-Id: If5cce458e28574bf1eaf7134bc3f123f5a632d4e
Reviewed-on: http://git-master/r/815983
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: implement per-channel watchdog

Implement per-channel watchdog/timer as per below rules :
- start the timer while submitting first job on channel or if
  no timer is already running
- cancel the timer when job completes
- re-start the timer if there is any incomplete job left
  in the channel's queue
- trigger appropriate recovery method as part of timeout
  handling mechanism

Handle the timeout as per below :
- get timed out channel, and job data
- disable activity on all engines
- check if fence is really pending
- get information on failing engine
- if no engine is failing, just abort the channel
- if engine is failing, trigger the recovery

Also, add flag "ch_wdt_enabled" to enable/disable channel
watchdog mechanism. Watchdog can also be disabled using
global flag "timeouts_enabled"

Set the watchdog time to be 5s using macro
NVGPU_CHANNEL_WATCHDOG_DEFAULT_TIMEOUT_MS

Bug 200133289

Change-Id: I401cf14dd34a210bc429f31bd5216a361edf1237
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797072
(cherry picked from commit 2d4bcbae629bfdee6b7886c9c2bf2932c3ef8245)
Reviewed-on: http://git-master/r/793638
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/815931
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: APIs to disable/enable all engines' activity

Add below APIs to disable/re-enable activity on all
engines
gk20a_fifo_disable_all_engine_activity()
gk20a_fifo_enable_all_engine_activity()

Bug 200133289

Change-Id: Ie01a260d587807a3c1712ee32fe870fbcb08f9cd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/798747
(cherry picked from commit b16ef2d4763b899dc632dbdbe8c48ea04f709da0)
Reviewed-on: http://git-master/r/805928
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/815930
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: disable channel before adjusting syncpoints

As per current sequence in gk20a_channel_abort(),
we first balance the syncpoint values associated with
failing channel, and then abort it

Reverse this sequence so that we first disable the channel
and then only balance the syncpoints

Bug 200133289

Change-Id: I5a748afce437e728a5ff6c8a030a75d0f627c622
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797071
(cherry picked from commit d797ddb230ed94ac565fc42377f6653fb94610a8)
Reviewed-on: http://git-master/r/806565
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/815929
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: separate API to get failing engine data

In gk20a_fifo_handle_sched_error(), we currently have a sequence
to identify failing engine (stuck on context switch) and
corresponding failing channel with its type

Separate out this sequence in new API
gk20a_fifo_get_failing_engine_data() so that it can be
reused from else where too

Bug 200133289

Change-Id: I3cef395170cf8990c014c7505c798fd6f2e37921
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797070
(cherry picked from commit d642f1244638bbdf265e6f81ffa2614a419cbd7f)
Reviewed-on: http://git-master/r/806564
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Change-Id: I8780a2d135c3ff6bfbf9755b7c27978458b673fd
Reviewed-on: http://git-master/r/815982
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

gpu: nvgpu: Use gradual slowdown

Program clock slowdown to happen using gradual slowdown. It is
significantly faster than the default slowdown.

Change-Id: I9e5259889637fce2c0b083a424b54af12bb45c25
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/819792
(cherry picked from commit aee586151e6a353483397eca6a3e8fd968acd3e0)
Reviewed-on: http://git-master/r/821582
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>

arm: tegra: p2360: Enable spidev driver

bug 200147979

Change-Id: I8058a4a4daf6635cb57dd39de48880e639c527e6
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/820895
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm: tegra: p2360: Reduce PCI timeout to ZERO

bug 1669370

Change-Id: I20be3a5b35e618c7af970a85c3c1c1960388c771
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/818736
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bhavesh Parekh <bparekh@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>

gpu: nvgpu: support skipping buffer refcounting in submit

In job submission path, we always take refcount on all
the mapped buffers to safeguard against case where user
space releases the buffer early

But in case user space itself is doing proper buffer
management, kernel need not take refcounts on all the
buffers - which is also a overhead in submit path

Hence, provide a new submit flag
NVGPU_SUBMIT_GPFIFO_FLAGS_SKIP_BUFFER_REFCOUNTING to
optionally skip taking refcounts on all the buffers

Also, if we do not take refcounts, then no need to drop
any refcounts in gk20a_channel_update() as well

Bug 1698667
Bug 200141116

Change-Id: I81bb7a03240300b691c70bcec04ea1badd5934f4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/824718
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

power: tegra12: Hot reset GPU MC client

Hot reset GPU MC client interface when GPU is powered ON
after boot or SC7 or rail-gate.

Bug 1642920

Change-Id: I421d535af4e9d627bf272814594ac3c7a50aaae7
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/740730
(cherry-picked from commit 8131500ef8b7cfc880a58141f7c964f06d7677c7)
Reviewed-on: http://git-master/r/757964
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

video: tegra: nvmap: fix divide by zero.

This change avoid unneccessary calculation
of compression when there is no compression.

Bug 200138578

Change-Id: Ie3ad3697f15d87f0347c00cf437de68df1ed76bd
Signed-off-by: puneet saini <psaini@nvidia.com>
Reviewed-on: http://git-master/r/821849
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>

arm: tegra: vcm30t124: Init clocks for LP CPU

Init clocks for LP CPU.
LP CPU is used during entering/exiting LP0.
But in automotive, LP CPU is not initialized since there is
no use case for LP CPU.
So LP CPU could operate with unexpected setting during
entering/exiting LP0 in automotive.

Bug 200143779

Change-Id: I4892d0a217cafe45baad3320d5c615ff92b802ba
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/824000
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

gpu: nvgpu: set aggressive_sync_destroy at runtime

We currently set "aggressive_destroy" flag to destroy
sync object statically and for each sync object

Move this flag to per-platform structure so that it
can be set per-platform for all the sync objects

Also, set the default value of this flag as "false"
and set it to "true" once we have more than 64
channels in use

Bug 200141116

Change-Id: I1bc271df4f468a4087a06a27c7289ee0ec3ef29c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/822041
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

net: wireless: bcmdhd: fix alignment fault

[   23.704327] Unhandled fault: alignment fault (0x96000021) at 0xffffff800c05f03c
[   23.711641] Internal error: : 96000021 [#1] PREEMPT SMP
[   23.738781] Modules linked in:
[   23.741849] CPU: 2 PID: 975 Comm: wpa_supplicant Not tainted 3.10.67-tegra #15
[   23.749062] task: ffffffc08bb0c840 ti: ffffffc087990000 task.ti: ffffffc087990000
[   23.756540] PC is at dhdpcie_bus_membytes+0x68/0xb4
[   23.761414] LR is at dhdpcie_readshared+0x130/0x6c4
[   23.766285] pc : [<ffffffc0005eb1ac>] lr : [<ffffffc0005ebd14>] pstate: 20000145

Bug 1642069

Change-Id: Id74018f3aa234bb0de39752179d830afa6f4e196
Signed-off-by: David Yu <davyu@nvidia.com>
Reviewed-on: http://git-master/r/782783
(cherry picked from commit dba8f5d738fad2d4f46bdd7fed981df2f30f2004)
Reviewed-on: http://git-master/r/825148
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kamal Balagopalan <kbalagopalan@nvidia.com>

tegra21: dvfs: Add 0x87 SKU

Add sku for Darcy that is capable of CPU 2Ghz at 1.15V

Bug 1669968

Change-Id: Ie6eac1a744760d0bf8afc1d2dd76c270aaf73ba1
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/824333
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

iio: common: NVS v209 common timestamps

- Create a common timestamp function for NVS sensor drivers.
- Timestamp changed from ktime_get_ts to get_monotonic_boottime to address
  the timestamp change through suspend.

- Removed the dependency of the NVI driver on NVS drivers supporting the NVI
  auxiliary bus.  If NVI_MPU is not enabled then these drivers build without
  NVI auxiliary bus API support.

Bug 200142073

Change-Id: I53b16bfb39b53015f3ee1e5418755f9b3f0cd132
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/821141
(cherry picked from commit 7c5801f839a493f17fa81993cc6b2315716c737a)
Reviewed-on: http://git-master/r/823563
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>

iio: light: CM3217 index fix.

- Fix possible table index out-of-bounds.
- Change default threshold values to something in reality.
- Add CM3217 debug light dump.
NVS_IIO v208:
- Add ability to read debug dump from HW driver without a write.
- Add sensor name to debug prints.
- Add functionality to returned calls from HW driver allowing simplification
of HW driver code, specifically for multi-sensor drivers.

Bug 200145232

Change-Id: I79d014569e236c70d8a3cdec2945fc0f22e43c07
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/818914
(cherry picked from commit 2821e9f1d517169d21ac8b18b648afd27bf438a1)
Reviewed-on: http://git-master/r/823562
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>

gpu: nvgpu: remove temporary gpfifo allocation in submit path

In GPU job submit path gk20a_ioctl_channel_submit_gpfifo(),
we currently allocate a temporary gpfifo, copy user space
gpfifo content into this temporary buffer, and then copy
temp buffer content into channel's gpfifo.

Allocation/copy/free of temporary buffer adds additional
overhead

Rewrite this sequence such that gk20a_submit_channel_gpfifo()
can receive either a pre-filled gpfifo or pointer to
user provided args.
And then we can direclty copy the user provided gpfifo
into the channel's gpfifo

Also, if command buffer tracing is enabled, we still need
to copy user provided gpfifo into temporaty buffer for reading
But that should not cause overhead in real world use case

Bug 200141116

Change-Id: I7166c9271da2694059da9853ab8839e98457b941
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/823386
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: fb: intimate fbcon to blank/unblank

Upon a hotplug/unplug, intimate fbcon to unblank or
blank accordingly. This helps in keeping dc and fbcon
in sync.

bug 1693204

Change-Id: I96b83bd8420e68ebb6048d50d9d9a422cd1fb706
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/820409
(cherry picked from commit 3a5c4678905a299e6ffadfaa8fab56bf4b29255d)
Reviewed-on: http://git-master/r/820822
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

video: fb: update VC before fbcon during hotplug

fbcon depends on the modes known to virtual console while updating
its own mode. Hence during a hotplug event, update virtual consoles
with new modes before updating fbcon mode.

bug 1693204

Change-Id: I6430ef27d186b8ac529a7e2c2929e383b0c2806e
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/815661
(cherry picked from commit c7d1081f7601957b17eab7a41562c77614503bf0)
Reviewed-on: http://git-master/r/820819
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

drivers: video: tegra: dc: Added nvdcR5G6B5 support

Bug 1691158

Change-Id: I429f4498e080b9b2c81a774e1e18e6bc0103e9d5
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: http://git-master/r/812625
GVS: Gerrit_Virtual_Submit
Tested-by: Vishal Agrawal (SW) <visagrawal@nvidia.com>
Reviewed-by: Raghavendra V K <rvk@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

arm64: jetson-cv: disable ldo6

Since ldo6 is not used on Jetson-CV, to disable it for safe. Although the ldo6
will not be enabled by any driver in Jetson-CV, but it has been set as
"regulator-always-on" and "regulator-boot-on" in
tegra210-jetson-e-pmic-p2530-0930-e03.dtsi.

Bug 1688673

Change-Id: I1fd17a6dc222d23069f03318ef4b30a67b2cec0f
Signed-off-by: Neil Chen <neilc@nvidia.com>
Reviewed-on: http://git-master/r/822584
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

clock: tegra21: fix a warning message

Fix the warning message below in tegra21_plle_clk_enable():
"pll_e hw sequencer is already on"

This message is printed when PLLE is under HW control and there is a
request to enable PLLE. When PLLE is under HW control, SW need to
ignore requests to enable or disable PLLE. This message is for
information only.

Bug 1691314

Change-Id: I45585d3b5d6e32320ac2e1dd6511fcf9e63dd504
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/820865
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

media: tegra: p2360: dtv: disable for zfas

Bug 200138574

Change-Id: Id0743973404af9503998b81a0e949d6ffd0d0c4b
Signed-off-by: puneet saini <psaini@nvidia.com>
Reviewed-on: http://git-master/r/821901
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>

media: platform: tegra: add multi offset len read

+ Add support for multi offset length read

Bug 1690851
Bug 1695405

Change-Id: I6e5a01a779765c3b742272141ab082970a00fb11
Signed-off-by: Vishal Agrawal <visagrawal@nvidia.com>
(cherry picked from commit 2c65a7015ae42c22b951677e3cbb0de2d3efc42d)
Reviewed-on: http://git-master/r/817864
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laszlo Weber <lweber@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>

power: bq2419x: update JEITA_VSET bit based on cable status

Update JEITA_VSET bit of charger chip in following cases
- set if charger cable connected to device
- clear when input cable disconnected from device
- clear if cable connected to device while powering off.

Bug 1647341
Bug 200143946

Change-Id: I25100859288eb7602c0434bd3abf581df65218ac
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/812010
(cherry picked from commit 13fac6e79b3efe8430bce41d06563105b49dc471)
Reviewed-on: http://git-master/r/814906
(cherry picked from commit 952a5edc8c649c75fc0055a6cf4c8e37986a2f97)
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/812066
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

power: bq27441: add low battery shutdown sysfs node

Adding low battery shutdown sysfs node to enable/disable
device shutdown based on battery soc value.

Bug 1674449

Change-Id: I6c8847e17060ffe6af0e59621bc06ff4b5f578ec
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/793766
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm64: context-switch user tls register tpidr_el0 for compat tasks

Since commit a4780adeefd0 ("ARM: 7735/2: Preserve the user r/w register
TPIDRURW on context switch and fork"), arch/arm/ has context switched
the user-writable TLS register, so do the same for compat tasks running
under the arm64 kernel.

Reported-by: André Hentschel <nerv@dawncrow.de>
Tested-by: André Hentschel <nerv@dawncrow.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: I6badb27e7c4db282fbf8d5b416f155947afbc8f9
Reviewed-on: http://git-master/r/776455
(cherry picked from commit 32e3a38f7a0b24d77f128971c5f646a4c05f7695)
Reviewed-on: http://git-master/r/787409
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

usb: gadget: composite: Fix cdev null after rmmod

Avoid to disconnect gadget again after unbinding

bug 200141741
bug 200143079

Change-Id: I6fadcb4c5b5262d861a865f24ba2d8666e126923
Signed-off-by: Peter Chiang <pchiang@nvidia.com>
Reviewed-on: http://git-master/r/805175
Reviewed-on: http://git-master/r/819566
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

gpu: nvgpu: fix pbdma intr handling

To handle any of the pbdma interrupt, we currently write zero
to pbdma_method0 and then clear the interrupt

But this is insufficient since we cannot use same intr clear
method for all the interrupts

Hence, add intr specific routines to handle those interrupts

NV_PPBDMA_INTR_0_PBENTRY:
- fix the pb_header to have a null opcode
- fix the pbdma_method to have a valid nop

NV_PPBDMA_INTR_0_METHOD:
- fix the pbdma_method to have a valid nop

NV_PPBDMA_INTR_0_DEVICE:
- fix the pb_header to have a null opcode
- go through all pbdma_method0/1/2/3
-- if they contain host s/w methods, replace those
methods with a valid NOP

Bug 200134238

Change-Id: I10c284a6cdc1441f9d437cea65aae00d3c33a8c8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/814561
(cherry picked from commit 5e2cfdee1171cc46d3a78465409b2df7372bf0e6)
Reviewed-on: http://git-master/r/819393
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

ASoC: Codec: fix headset-mic issue

LDO2 and MICBIAS power supplies are turned ON during
jack detection to detect headset-mic. The micbias voltage
turned OFF if there is no headset-mic.
This should be tried on E2614 with FSA rework

Bug 1686170
Bug 200135470

Reviewed-on: http://git-master/r/805033
(cherry picked from commit b05badedae5c0445949c25ebf5b4d44adb638a00)

Change-Id: I88b4901e00b88fae7b7fb1ceacb738dd2fc488df
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: http://git-master/r/807875
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>

iio: proximity: SAR Stable Setting V1.2.3

- improved target and base value setting for DVT1.
- hw configuration:1.5K+2pf , DNP+2pf , DNP+DNP.

Bug 1696152

Signed-off-by: Shylender Gaddamwar <sgaddamwar@nvidia.com>
Change-Id: I50870a56752f60df55751760ae3bb84e9cf23ebe
Reviewed-on: http://git-master/r/818484
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>

net: wireless: bcmdhd: Fix country code map mem leak

Free country code map buffer when adapter is removed.

Bug 200143482

Change-Id: Iab82b3b56ec07a99a3d3012b2931c51ddecbc502
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: http://git-master/r/817916
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

wireless: bcmdhd: Set/get dhd_msg_level using module param

Android utility tools to configure the msg_level in the DHD are
not available for platforms like L4T. Allow the msg_level variable
as a module param so that it can be configured at runtime via sysfs

Bug 1686560

Change-Id: Ibc480bd6eebea446ba453e2e58c37d1744cfb2a9
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: http://git-master/r/817239
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

media: tegra_v4l2_camera: update v4l2_imx230

Add support for 2 more modes
2672x1600 (2-binned mode of 5344x3200) and
5344x4016 (full-res)

Bug 1682934

Change-Id: I0c2d9fb9343757ea9b87e32fbce0d2cecfed750c
Signed-off-by: Arun Kannan <akannan@nvidia.com>
Reviewed-on: http://git-master/r/812401
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hu He <hhe@nvidia.com>
Reviewed-by: Kamal Balagopalan <kbalagopalan@nvidia.com>

platform: tegra: mc: handle dec and sec mc err combo

Hanlde DECERR_EMEM and SECURTY_VIOLATION error combination.

Bug 1675932

Change-Id: I762b3bfa153ea41af35881fad2c7c9306b0fc8d5
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/804003
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
GVS: Gerrit_Virtual_Submit

arm: tegra: p2360: Add SPI NOR partitions

Create 2 partitions for SPI NOR
Persistency: 65280KiB@0
Dataset: 256KiB@65280KiB(ro)

bug 200136941

Change-Id: I3b5ca9a0a0a0bea8dcd5f5e85d3f980cd5c7a5c2
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/806645
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

p2360: Add dtb's for 480p resolution

* Modified default hdmi resolution as 1080p@30fps
* Added tegra124-p2360-480p-*.dtb

bug 200133460

Change-Id: I66bf44e936e177ac896dafbe12ca1a544646e9c6
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: http://git-master/r/791765
(cherry picked from commit 9cb5adc7e4969aefa1655787b0c69e89298ac053)
Reviewed-on: http://git-master/r/794348
Reviewed-by: Vipin Kumar <vipink@nvidia.com>
Tested-by: Vipin Kumar <vipink@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>

pcie: host: tegra: adds pad powerdown programming

adds missing pad powerdown programming which is present
in pcie IAS doc

Bug 200069084
Bug 200044687

Change-Id: I3c69be6da8d849e9c203d3af0fb84b2ade4f09fe
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: http://git-master/r/778016
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

mmc: tegra: Disable SD_CLK before calibration start

Disabled SD_CLK before auto-calibration start and
enabled it after completion of auto-calibration

Bug 1670647

Change-Id: I3e0d2dd757430cb6f29c1dfeabcf55c96f0a29f5
Reviewed-on: http://git-master/r/781006
(cherry picked from commit fea4877b2bd8e63a3de1e40fb5507933e4d7455a)

Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Change-Id: Ia4fdfd3e446b1d61410cd41814c996d292d697f5
Reviewed-on: http://git-master/r/814445
GVS: Gerrit_Virtual_Submit
Tested-by: Anubhav Jain <anubhavj@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>

arm64: boot: dts: update HS_SQUELCH_LEVEL for A02

From A02, HS_SQUELCH_LEVEL in XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0 is
set to 0.

Bug 200074796

Change-Id: I96ae8ffbecdf7ed839f3e393d2781ed9e207b6e4
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Signed-off-by: Henry Lin <henryl@nvidia.com>
Reviewed-on: http://git-master/r/737763
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: ChihMin Cheng <ccheng@nvidia.com>
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-on: http://git-master/r/811673
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

platform: t210: padctl: sata idle detector

Power down SATA idle detector to save power.

If there is no drive found during boot, SATA driver will be unloaded.
Since SATA driver is unloaded, there is no chance for it to program
registers to save power after LP0 cycle.

In this change, we power down SATA idle detector from PADCTL driver
as part of UPHY PLL initialization during early boot and resume.
Later, SATA driver can power up idle detector when necessary.

Bug 200126755

Change-Id: I26e74c7cccb0ac8d6d9a84ecbaad15ec23ba38c0
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/779675
(cherry picked from commit e9f60a963783b09b6a2543af0cd6540b5c532f1a)
Reviewed-on: http://git-master/r/811595
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Tested-by: Ajay Gupta <ajayg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

Revert "ata: ahci: WAR for SATA power issues"

This reverts commit 9558cecc16eb3e0c8b966800fc7cd6a8a476546d.

Change-Id: I9bddc92db0ee629c151a22ec502f9eb75888c11b
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/811591
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Tested-by: Ajay Gupta <ajayg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

ARM: tegra21: ERS: rails LDO1 and LDO8

Make LDO1 and LDO8 always ON with LP0 OFF.

Make these rails to be OFF in LP0 by connecting these rails with FPS1.

These rails are necessary for UPHY PAD and PLL. UPHY needs to be in
operating state in LP1. We can only turn these rails OFF in LP0.

Bug 200068549
Bug 1653521

Change-Id: If08dd287ec466bc36e8db0f5b13fe1c81f29be6a
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/756449
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-on: http://git-master/r/810580
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

arm64: tegra210: add device node xusb_padctl

Rename the node from padctl to xusb_padctl and add properties:

nvidia,lane-map: assign lanes for PCIE driver
nvidia,enable-sata-port: specify if SATA driver will use lane or not

Add power rails necessary for UPHY.

Bug 200068549

Change-Id: Ib02b5551840c33ba853949477e5e3c8333d41e34
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/746213
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-on: http://git-master/r/810579
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

ata: ahci: t210 uphy pad and pll

Move T210 PADCTL register access to padctl driver.

Bug 200068549

Change-Id: I504bf5264ed029d8736ea2c51677278e0f9eed99
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/752543
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-on: http://git-master/r/810578
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Tested-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Preetham Chandru <pchandru@nvidia.com>
GVS: Gerrit_Virtual_Submit

platform: t210: padctl: enable plle hw sequencer

Make PADCTL driver as a module to program UPHY PAD and PLL and enable
PLLE HW sequencer early during boot and system resume. This ensures
correct sequence that we only enable PLLE HW sequencer after both
PEX and SATA UPHY PLL HW sequencers are enabled.
PADCTL driver enables all power rails for UPHY PAD and PLL. It will
keep these rails ON during suspend also as we decided to keep UPHY
operating in LP1/SC4. Power tree may turn off these reails in LP0/SC7.

Add checks for UPHY PLL HW sequencers. If HW sequencer is enabled,
there is no need to assert UPHY reset or initialize UPHY PLL.

Export functions below for SATA driver to program UPHY PAD and PLL:
tegra_padctl_init_sata_pad()
tegra_padctl_enable_sata_pad()

Controller drivers still call functions from PADCTL driver to program
UPHY PAD and PLL, but PADCTL driver will ensure UPHY PLLs are only
initialized once when necessary.

Add code to release always on PAD muxing logic state latching after
bringing all specific lanes of UPHY out of IDDQ.

Define a new spinlock for PADCTL register access to avoid dead lock.

There are two main parts for the change:
The 1st part is for SATA UPHY PAD. The programming sequence is mostly
copied from current SATA driver. The entry points are two exported
functions mentioned above.
The 2nd part is for PADCTL driver to program UPHY PAD and PLL. The entry
functions are tegra_padctl_uphy_init() and tegra_padctl_uphy_deinit().

Bug 200068549

Change-Id: Ic16a18e35b8290daadccb402fc1c3f85b13121dd
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/752541
Reviewed-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-on: http://git-master/r/810577
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Tested-by: Ajay Gupta <ajayg@nvidia.com>
GVS: Gerrit_Virtual_Submit