#define NV_PCIE2_RP_VEND_XP_BIST 0x00000F4C
#define PCIE2_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE (1 << 28)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN 0x00000F50
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_L1_EN (1 << 0)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC_EN (1 << 1)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED_EN (1 << 2)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_L1_CLKREQ_EN (1 << 15)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP (3 << 5)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1P (2 << 3)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1PP (3 << 3)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_CLKREQ_L1P (2 << 16)
+#define NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_CLKREQ_L1PP (3 << 16)
+
#define NV_PCIE2_RP_PRIV_XP_RX_L0S_ENTRY_COUNT 0x00000F8C
#define NV_PCIE2_RP_PRIV_XP_TX_L0S_ENTRY_COUNT 0x00000F90
#define NV_PCIE2_RP_PRIV_XP_TX_L1_ENTRY_COUNT 0x00000F94
data |= PCIE2_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH;
rp_writel(port, data, NV_PCIE2_RP_VEND_CTL0);
+ data = rp_readl(port, NV_PCIE2_RP_VEND_XP_PAD_PWRDN);
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED_EN;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC_EN;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_L1_EN;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_L1_CLKREQ_EN;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1PP;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_CLKREQ_L1PP;
+ rp_writel(port, data, NV_PCIE2_RP_VEND_XP_PAD_PWRDN);
+
/* Do timer settings only if clk25m freq equal to 19.2 MHz */
if (clk_get_rate(clk_get_sys(NULL, "clk_m")) != 19200000)
return;
data = rp_readl(port, RP_VEND_XP);
data |= RP_VEND_XP_UPDATE_FC_THRESHOLD;
rp_writel(port, data, RP_VEND_XP);
+
+ data = rp_readl(port, NV_PCIE2_RP_VEND_XP_PAD_PWRDN);
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED_EN;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC_EN;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_L1_EN;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_L1_CLKREQ_EN;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1P;
+ data |= NV_PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_CLKREQ_L1P;
+ rp_writel(port, data, NV_PCIE2_RP_VEND_XP_PAD_PWRDN);
#endif
}
}