arm64: tegra210: fix DT for node xusb_padctl

arm64: tegra210: fix DT for node xusb_padctl

DT node xusb_padctl contains info to initialize PLLE and UPHY PLLs.

If pcie is enabled, xusb_padctl needs the following property copied
from pcie node:
	nvidia,lane-map

If sata is enabled, xusb_padctl needs the following property copied
from sata node:
	nvidia,enable-sata-port

XUSB uses the following property to assign lanes:
	nvidia,lane_owner

To initialize PLLE and UPHY PLLs, xusb_padctl needs to know power
rails below:
	avdd_pll_uerefe-supply
	hvdd_pex_pll_e-supply
	dvdd_pex_pll-supply
	hvddio_pex-supply
	dvddio_pex-supply
	hvdd_sata-supply
	dvdd_sata_pll-supply
	hvddio_sata-supply
	dvddio_sata-supply

Bug 1685150

DEPENDS ON: < None >

Change-Id: I5d3d227883d8c3f2148c9ea218f1312a2b54c20a
Signed-off-by: TW Chiu <twchiu@nvidia.com>
Reviewed-on: http://git-master/r/815639
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit