drivers: video: tegra: sor: Updated sor GR's

Bug 200104480

Change-Id: I8d581b384b339675e761ccf7bf87cffad4efa2db
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: http://git-master/r/819544
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>

diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c
index c93123b939c1080877b437adefecaffcb91f01af..8656c653eac60584deabedaf01ae4b6d17c699fe 100644 (file)
--- a/drivers/video/tegra/dc/sor.c
+++ b/drivers/video/tegra/dc/sor.c
@@ -201,7 +201,9 @@ static int dbg_sor_show(struct seq_file *s, void *unused)
        DUMP_REG(NV_SOR_DC(0));
        DUMP_REG(NV_SOR_DC(1));
        DUMP_REG(NV_SOR_LANE_DRIVE_CURRENT(0));
+       DUMP_REG(NV_SOR_LANE4_DRIVE_CURRENT(0));
        DUMP_REG(NV_SOR_PR(0));
+       DUMP_REG(NV_SOR_LANE_PREEMPHASIS(0));
        DUMP_REG(NV_SOR_LANE4_PREEMPHASIS(0));
        DUMP_REG(NV_SOR_POSTCURSOR(0));
        DUMP_REG(NV_SOR_DP_CONFIG(0));
@@ -1756,8 +1758,10 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
                NV_SOR_PLL3_PLLVDD_MODE_MASK,
                NV_SOR_PLL3_PLLVDD_MODE_V1_8);
 
-       tegra_sor_writel(sor, NV_SOR_PLL1,
-               NV_SOR_PLL1_TERM_COMPOUT_HIGH | NV_SOR_PLL1_TMDS_TERM_ENABLE);
+       tegra_sor_writel(sor, NV_SOR_PLL1, 
+                        (NV_SOR_PLL1_TMDS_TERMADJ_OHM500 |
+                         (2 << NV_SOR_PLL1_LVDSCM_SHIFT) |
+                         (2 << NV_SOR_PLL1_LOADADJ_SHIFT)));
        tegra_sor_write_field(sor, NV_SOR_PLL2,
                NV_SOR_PLL2_AUX1_SEQ_MASK |
                NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK,
@@ -1781,7 +1785,26 @@ void tegra_dc_sor_enable_lvds(struct tegra_dc_sor_data *sor,
 
        tegra_sor_writel(sor, NV_SOR_LVDS, reg_val);
        tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
-               0x40404040);
+               (NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0 |
+                NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0 |
+                NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0 |
+                NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0));
+       reg_val = tegra_sor_readl(sor,
+                                 NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum));
+       reg_val &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK;
+       tegra_sor_writel(sor, NV_SOR_LANE4_DRIVE_CURRENT(sor->portnum),
+                reg_val | NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0);
+
+       tegra_sor_writel(sor, NV_SOR_LANE_PREEMPHASIS(sor->portnum),
+                        (NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL4 |
+                         NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL4 |
+                         NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL4 |
+                         NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL4));
+       reg_val = tegra_sor_readl(sor,
+                NV_SOR_LANE4_PREEMPHASIS(sor->portnum));
+       reg_val &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK;
+       tegra_sor_writel(sor, NV_SOR_LANE4_PREEMPHASIS(sor->portnum),
+                        reg_val | NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL4);
 
 #if 0
        tegra_sor_write_field(sor, NV_SOR_LVDS,

diff --git a/drivers/video/tegra/dc/sor_regs.h b/drivers/video/tegra/dc/sor_regs.h
index 18a69b7a2472a04bc9f97443ee072889b0ed5e32..bb7b43c152396b25c23119121302bf2fc18b73d3 100644 (file)
--- a/drivers/video/tegra/dc/sor_regs.h
+++ b/drivers/video/tegra/dc/sor_regs.h
@@ -686,6 +686,7 @@
 #define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2                     (34 << 24)
 #define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2                     (43 << 24)
 #define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3                     (51 << 24)
+#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL4                     (3 << 24)
 #define NV_SOR_DC_LANE2_DP_LANE0_SHIFT                         (16)
 #define NV_SOR_DC_LANE2_DP_LANE0_MASK                          (0xff << 16)
 #define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0                     (17 << 16)
@@ -698,6 +699,7 @@
 #define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2                     (34 << 16)
 #define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2                     (43 << 16)
 #define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3                     (51 << 16)
+#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL4                     (3 << 16)
 #define NV_SOR_DC_LANE1_DP_LANE1_SHIFT                         (8)
 #define NV_SOR_DC_LANE1_DP_LANE1_MASK                          (0xff << 8)
 #define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0                     (17 << 8)
@@ -710,6 +712,7 @@
 #define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2                     (34 << 8)
 #define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2                     (43 << 8)
 #define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3                     (51 << 8)
+#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL4                     (3 << 8)
 #define NV_SOR_DC_LANE0_DP_LANE2_SHIFT                         (0)
 #define NV_SOR_DC_LANE0_DP_LANE2_MASK                          (0xff)
 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0                     (17)
@@ -722,7 +725,9 @@
 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2                     (34)
 #define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2                     (43)
 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3                     (51)
+#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL4                     (3)
 #define NV_SOR_LANE_DRIVE_CURRENT(i)                           (0x4e + (i))
+#define NV_SOR_LANE4_DRIVE_CURRENT(i)                          (0x50 + (i))
 #define NV_SOR_PR(i)                                           (0x52 + (i))
 #define NV_SOR_PR_LANE3_DP_LANE3_SHIFT                         (24)
 #define NV_SOR_PR_LANE3_DP_LANE3_MASK                          (0xff << 24)
@@ -772,6 +777,7 @@
 #define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2                     (8)
 #define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2                     (13)
 #define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3                     (17)
+#define NV_SOR_LANE_PREEMPHASIS(i)                             (0x52 + (i))
 #define NV_SOR_LANE4_PREEMPHASIS(i)                            (0x54 + (i))
 #define NV_SOR_POSTCURSOR(i)                                   (0x56 + (i))
 #define NV_SOR_DP_CONFIG(i)                                    (0x58 + (i))