[submodule "submodule/ulan-drv"]
path = submodule/ulan-drv
url = git://git.code.sf.net/p/ulan/ulan-drv
+[submodule "submodule/tumbl"]
+ path = submodule/tumbl
+ url = ssh://git@rtime.felk.cvut.cz/fpga/lx-cpu1/tumbl.git
# - gen : Transfer placed and routed NCD file into the bin file, which can
# be then used to configure particular FPGA (this is further packaged
# for SelectMap interface via the ARM CPU)
+# - firmware : Builds the firmware for Tumbl core
# Dependicies are handled, so in most cases only 'download' target is called.
REQ_PKG := $(REQB).pkg
REQ_SRC := .
+REQ_FIRMWARE := $(OUT)/imem.bin $(OUT)/imem.asm $(OUT)/dmem.bin $(OUT)/firmware.lst
+
+#===============================================================================
+
+MB_CROSS_COMPILE ?= mb-
+TARGET_CC := $(MB_CROSS_COMPILE)gcc
+TARGET_LD := $(MB_CROSS_COMPILE)ld
+TARGET_OBJCOPY := $(MB_CROSS_COMPILE)objcopy
+TARGET_OBJDUMP := $(MB_CROSS_COMPILE)objdump
+
+C_OBJS := $(OUT)/firmware.o
+A_OBJS :=
+CFLAGS := -mxl-soft-div -msoft-float -mno-xl-soft-mul -mxl-barrel-shift -Wno-main -Wl,-no-check-sections -fno-zero-initialized-in-bss -g -O2 -Wall
+AFLAGS := -D__ASSEMBLY__ $(CFLAGS)
+LDFLAGS := -static -nostdlib -defsym _STACK_SIZE=0x0200
+
+OBJS := $(OUT)/start.o $(C_OBJS) $(A_OBJS)
+
+FIRMWARE_DIR := ./lx-rocon_firmware
+
#===============================================================================
# Attempt to create a output directory.
#===============================================================================
.PHONY: all
-all: pkg
+all: pkg firmware
.PHONY: re-synthesize
re-synthesize $(REQ_NGC): $(addprefix $(REQ_SRC)/,$(PRJ))
cd $(OUT); \
./packager le $(BIN) $(PKG)
+$(OUT)/%.o: $(FIRMWARE_DIR)/%.c
+ $(TARGET_CC) $(CFLAGS) -c $< -o $@
+
+$(OUT)/%.o: $(FIRMWARE_DIR)/%.S
+ $(TARGET_CC) $(AFLAGS) -c $< -o $@
+
+$(OUT)/firmware.elf: $(OBJS)
+ $(TARGET_LD) $(LDFLAGS) -T $(FIRMWARE_DIR)/utils/tumbl.ld-script -o $@ $(OBJS)
+
+$(OUT)/mb-dasm: $(FIRMWARE_DIR)/utils/mb-dasm.cpp
+ g++ $< -o $@
+
+$(OUT)/bin2mem: $(FIRMWARE_DIR)/utils/bin2mem.c
+ gcc $< -o $@
+
+.PHONY: re-firmware
+re-firmware $(REQ_FIRMWARE): $(REQ_PKG) $(OUT)/mb-dasm $(OUT)/bin2mem $(OUT)/firmware.elf
+ $(TARGET_OBJCOPY) -O binary $(OUT)/firmware.elf -j .text -S $(OUT)/imem.bin
+ $(TARGET_OBJCOPY) -O binary $(OUT)/firmware.elf -j .data -S $(OUT)/dmem.bin
+ $(TARGET_OBJDUMP) -DSCz $(OUT)/firmware.elf > $@
+ cd $(OUT); \
+ ./mb-dasm imem.bin > imem.asm
+
#===============================================================================
.PHONY: clean
.PHONY: pkg
pkg: $(OUT)/packager $(REQ_PKG)
+
+.PHONY: firmware
+firmware: $(OUT)/mb-dasm $(OUT)/bin2mem $(REQ_FIRMWARE)
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
--- Bcd for clock debugging purposes
-
-entity bcd is
- generic
- (
- width : integer := 32
- );
- port
- (
- -- Reset
- reset : in std_logic;
-
- -- Enabled
- en : in std_logic;
-
- -- Clock
- clk : in std_logic;
-
- -- Value
- value : out std_logic_vector((width-1) downto 0)
- );
-end bcd;
-
-architecture Behavioral of bcd is
- signal counter : std_logic_vector((width-1) downto 0);
-begin
-
- value <= counter;
-
- update: process (clk, reset)
- begin
-
- if reset = '1' then
- counter <= (others => '0');
- elsif clk = '1' and clk'event then
- if en = '1' then
- counter <= counter + 1;
- end if;
- end if;
-
- end process;
-
-end Behavioral;
-
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
--- BCD interconnection
-
-entity bus_bcd is
- port
- (
- -- Reset
- reset : in std_logic;
-
- -- Enable
- en : in std_logic;
-
- -- Clock
- clk : in std_logic;
-
- -- Chip enable
- ce : in std_logic;
-
- -- Data bus (read only)
- data_out : out std_logic_vector(31 downto 0);
-
- -- Bus signals
- rd : in std_logic;
- ta : out std_logic
- );
-end bus_bcd;
-
-architecture Behavioral of bus_bcd is
-
- signal value : std_logic_vector(31 downto 0);
-
- component bcd
- generic
- (
- width : integer
- );
- port
- (
- reset : in std_logic;
- en : in std_logic;
- clk : in std_logic;
- value : out std_logic_vector((width-1) downto 0)
- );
- end component;
-
-begin
-
- my_bcd: bcd
- generic map
- (
- width => 32
- )
- port map
- (
- reset => reset,
- en => en,
- clk => clk,
- value => value
- );
-
- memory_bus: process(ce, rd, value)
- begin
-
- -- Init defaults
- ta <= '1';
- data_out <= (others => 'X');
-
- if ce = '0' and rd = '0' then
- ta <= '0';
- -- ID in big endian
- data_out <= value;
- end if;
-
- end process;
-
-
-end Behavioral;
-
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
+use work.lx_rocon_pkg.all;
-- Memory bus calibration
-- Holds the signal for one clock to simulate longest route
-- Wiring
signal read1_out : std_logic_vector(31 downto 0);
signal read1_ta : std_logic;
- signal read1_ce : std_logic;
signal read2_out : std_logic_vector(31 downto 0);
signal read2_ta : std_logic;
- signal read2_ce : std_logic;
signal write1_out : std_logic_vector(31 downto 0);
signal write1_ta : std_logic;
signal write2_ta : std_logic;
signal write2_ce : std_logic;
- component calibration_read_register
- generic
- (
- id : std_logic_vector(31 downto 0)
- );
- port
- (
- ce : in std_logic;
- data_out : out std_logic_vector(31 downto 0);
- rd : in std_logic;
- ta : out std_logic
- );
- end component;
-
- component calibration_write_register
- port
- (
- clk : in std_logic;
- reset : in std_logic;
- ce : in std_logic;
- data_in : in std_logic_vector(31 downto 0);
- data_out : out std_logic_vector(31 downto 0);
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- ta : out std_logic
- );
- end component;
-
begin
-- First read calibration register (0xAAAAAAAA)
)
port map
(
- ce => read1_ce,
rd => rd,
ta => read1_ta,
data_out => read1_out
)
port map
(
- ce => read2_ce,
rd => rd,
ta => read2_ta,
data_out => read2_out
if clk = '1' and clk'event then
-- Defaults
- read1_ce <= '1';
- read2_ce <= '1';
write1_ce <= '1';
write2_ce <= '1';
if ce = '0' then
case address is
when "00" => -- Read1
- read1_ce <= '0';
ta <= read1_ta;
data_out <= read1_out;
when "01" => -- Read2
- read2_ce <= '0';
ta <= read2_ta;
data_out <= read2_out;
when "10" => -- Write1
+++ /dev/null
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Wrapper for the memory bus for CPU and the BRAM
-
-entity bus_control_bram is
- port
- (
- -- Clock
- clk : in std_logic;
-
- -- This is wired to CPU memory bus
- ena : in std_logic;
- wea : in std_logic_vector(3 downto 0);
- addra : in std_logic_vector(8 downto 0);
- dina : in std_logic_vector(31 downto 0);
- douta : out std_logic_vector(31 downto 0);
- taa : out std_logic;
-
- -- This is wired to control unit bus
- enb : in std_logic;
- web : in std_logic_vector(3 downto 0);
- addrb : in std_logic_vector(8 downto 0);
- dinb : in std_logic_vector(31 downto 0);
- doutb : out std_logic_vector(31 downto 0)
- );
-end bus_control_bram;
-
-architecture Behavioral of bus_control_bram is
-
- signal neg_ena : std_logic;
- signal neg_wea : std_logic_vector(3 downto 0);
-
- component control_bram
- port
- (
- clka : in std_logic;
- ena : in std_logic;
- wea : in std_logic_vector(3 downto 0);
- addra : in std_logic_vector(8 downto 0);
- dina : in std_logic_vector(31 downto 0);
- douta : out std_logic_vector(31 downto 0);
-
- clkb : in std_logic;
- enb : in std_logic;
- web : in std_logic_vector(3 downto 0);
- addrb : in std_logic_vector(8 downto 0);
- dinb : in std_logic_vector(31 downto 0);
- doutb : out std_logic_vector(31 downto 0)
- );
- end component;
-
-begin
-
- -- Wire it to the actual BRAM
- my_bram: control_bram
- port map
- (
- clka => clk,
- ena => neg_ena,
- wea => neg_wea,
- addra => addra,
- dina => dina,
- douta => douta,
-
- clkb => clk,
- enb => enb,
- web => web,
- addrb => addrb,
- dinb => dinb,
- doutb => doutb
- );
-
- -- Transaction acknowledge
- my_bram_ta: process(clk)
- begin
-
- -- It puts there data synchronously with clock, so make the same for ack
- if clk = '1' and clk'event then
- taa <= ena;
- end if;
-
- end process;
-
- -- Wire negated inputs
- my_bream_neg: process(ena, wea)
- begin
-
- neg_ena <= not ena;
- neg_wea <= not wea;
-
- end process;
-
-end Behavioral;
-
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
+use work.lx_rocon_pkg.all;
-- IRC bus interconnect: memory region for IRC
signal irc4_ta : std_logic;
signal irc4_ce : std_logic_vector(1 downto 0);
- -- IRC register
- component irc_register
- port
- (
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
- mark0 : in std_logic;
- data_in : in std_logic;
- data_out : out std_logic_vector(31 downto 0);
- ce : in std_logic_vector(1 downto 0);
- rd : in std_logic;
- ta : out std_logic;
- wr : in std_logic
- );
- end component;
-
begin
-- IRC for first axis
data_out <= irc4_out;
ta <= irc4_ta;
- when others =>
- data_out <= (others => 'X');
+ when others => NULL;
end case;
--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.mbl_Pkg.all;
+use work.lx_rocon_pkg.all;
+
+-- Connects tumbl to the Master CPU
+
+entity bus_tumbl is
+ port
+ (
+ -- Clock
+ clk_100m : in std_logic;
+ clk_50m : in std_logic;
+
+ -- Chip enable
+ ce : in std_logic;
+
+ -- Global Reset
+ reset : in std_logic;
+
+ -- Master CPU bus for the memory
+ rd : in std_logic;
+ bls : in std_logic_vector(3 downto 0);
+ address : in std_logic_vector(11 downto 0);
+ data_in : in std_logic_vector(31 downto 0);
+ data_out : out std_logic_vector(31 downto 0);
+ ta : out std_logic;
+
+ -- Tumbl extrenal memory bus
+ XMEMB_sel_o : out std_logic;
+ XMEMB_i : in DMEMB2CORE_Type;
+ XMEMB_o : out CORE2DMEMB_Type
+ );
+end bus_tumbl;
+
+architecture Behavioral of bus_tumbl is
+
+ -- Internal state
+ signal tumbl_reset : std_logic;
+ signal tumbl_halt : std_logic;
+ signal tumbl_int : std_logic;
+ signal tumbl_trace : std_logic;
+ signal tumbl_trace_kick : std_logic; -- driven by 50M clock
+ signal tumbl_trace_kick_ack : std_logic; -- driven by 50M clock
+ signal tumbl_trace_kick_req : std_logic; -- driven by 100M clock
+ signal tumbl_done : std_logic; -- driven by 50M clock
+ signal tumbl_bad_op : std_logic; -- driven by 50M clock
+
+ -- Tumbl PC (copy it with cpu clock and then wire further)
+ signal tumbl_pc : std_logic_vector(31 downto 0); -- driven by 50M clock
+
+ -- Internal memory signals
+ signal imem_en : std_logic;
+ signal dmem_en : std_logic;
+
+ signal imem_we : std_logic_vector(3 downto 0);
+ signal dmem_we : std_logic_vector(3 downto 0);
+
+ signal imem_dout : std_logic_vector(31 downto 0);
+ signal dmem_dout : std_logic_vector(31 downto 0);
+
+ -- Internal bus structure
+ -- 12 address bits: 2 bits for selection, 10 bits for address
+ --
+ -- Selection:
+ -- 00 - imem
+ -- 01 - dmem
+ -- 10 - reserved
+ -- 11 - registers
+
+ -- Registers
+ -- 0x000
+ --
+ -- Bit 0: R/W - Reset
+ -- Bit 1: R/W - Interrupt
+ -- Bit 2: R/W - Halt
+ -- Bit 3: R/W - Trace
+ -- Bit 3: R - Done
+ -- Bit 4: R - Bad Op (halts the core until reset)
+
+ -- 0x001
+ -- Bit 0: W - Write 1 for trace kick, R - Read internal signals
+
+ -- 0x002
+ -- Tumbl program counter (R)
+
+begin
+
+ -- Wire it to the tumbl
+ I_TUMBL: lx_rocon_tumbl
+ generic map
+ (
+ IMEM_ABITS_g => 11,
+ DMEM_ABITS_g => 12,
+ --
+ USE_HW_MUL_g => true,
+ USE_BARREL_g => true
+ )
+ port map
+ (
+ clk_i => clk_50m,
+ rst_i => tumbl_reset,
+ halt_i => tumbl_halt,
+ int_i => tumbl_int,
+ trace_i => tumbl_trace,
+ trace_kick_i => tumbl_trace_kick,
+
+ pc_o => tumbl_pc,
+
+ -- Internal memory (instruction)
+ imem_clk => clk_100m,
+ imem_en => imem_en,
+ imem_we => imem_we,
+ imem_addr => address(8 downto 0),
+ imem_din => data_in,
+ imem_dout => imem_dout,
+
+ -- Internal memory (data)
+ dmem_clk => clk_100m,
+ dmem_en => dmem_en,
+ dmem_we => dmem_we,
+ dmem_addr => address(9 downto 0),
+ dmem_din => data_in,
+ dmem_dout => dmem_dout,
+
+ -- External memory bus
+ XMEMB_sel_o => XMEMB_sel_o,
+ XMEMB_i => XMEMB_i,
+ XMEMB_o => XMEMB_o,
+ --
+ done_o => tumbl_done,
+ bad_op_o => tumbl_bad_op
+ );
+
+ -- Wiring
+ wiring: process(ce, rd, bls, address, imem_en, imem_dout, dmem_en, dmem_dout,
+ tumbl_reset, tumbl_int, tumbl_halt, tumbl_trace, tumbl_done, tumbl_bad_op, tumbl_pc)
+ begin
+
+ if ce = '0' and address(11 downto 10) = "00" then
+ imem_en <= '1';
+ else
+ imem_en <= '0';
+ end if;
+
+ if ce = '0' and address(11 downto 10) = "01" then
+ dmem_en <= '1';
+ else
+ dmem_en <= '0';
+ end if;
+
+ if imem_en = '1' and tumbl_reset = '1' then
+ imem_we <= not bls;
+ else
+ imem_we <= "0000";
+ end if;
+
+ if dmem_en = '1' and tumbl_reset = '1' then
+ dmem_we <= not bls;
+ else
+ dmem_we <= "0000";
+ end if;
+
+ if imem_en = '1' then
+ data_out <= imem_dout;
+ elsif dmem_en = '1' then
+ data_out <= dmem_dout;
+ elsif ce = '0' and rd = '0' and address(11 downto 10) = "11" then
+ if address(9 downto 0) = "0000000000" then
+ data_out(0) <= tumbl_reset;
+ data_out(1) <= tumbl_int;
+ data_out(2) <= tumbl_halt;
+ data_out(3) <= tumbl_trace;
+ data_out(4) <= tumbl_done;
+ data_out(5) <= tumbl_bad_op;
+ data_out(31 downto 5) <= (others => '0');
+ elsif address(9 downto 0) = "0000000010" then
+ data_out <= tumbl_pc;
+ else
+ data_out <= (others => 'X');
+ end if;
+ else
+ data_out <= (others => 'X');
+ end if;
+
+ end process;
+
+ -- Transaction acknowledge and writing to registers
+ -- The clock are synchronous!
+ update: process(clk_100m)
+ begin
+
+ -- Update on the 100 MHz clock
+ if clk_100m = '1' and clk_100m'event then
+ ta <= '1';
+
+ if imem_en = '1' or dmem_en = '1' then
+ ta <= '0';
+ end if;
+
+ if reset = '1' then
+ tumbl_reset <= '1';
+ tumbl_int <= '0';
+ tumbl_halt <= '0';
+ tumbl_trace <= '0';
+ tumbl_trace_kick_req <= '0';
+ else
+
+ if tumbl_trace_kick_ack = '1' then
+ tumbl_trace_kick_req <= '0';
+ end if;
+
+ if ce = '0' and address(11 downto 10) = "11" then
+ if bls(0) = '0' then
+ if address(9 downto 0) = "0000000000" then
+ tumbl_reset <= data_in(0);
+ tumbl_int <= data_in(1);
+ tumbl_halt <= data_in(2);
+ tumbl_trace <= data_in(3);
+ elsif address(9 downto 0) = "0000000001" then
+ if data_in(0) = '1' and tumbl_trace_kick = '0' then
+ tumbl_trace_kick_req <= '1';
+ end if;
+ end if;
+ end if;
+
+ if rd = '0' then
+ ta <= '0';
+ end if;
+ end if;
+ end if;
+
+ end if;
+ end process;
+
+ -- Update tracing
+ tumbl: process(clk_50m)
+ begin
+
+ -- Update on the 50 MHz clock
+ if clk_50m = '1' and clk_50m'event then
+
+ if reset = '1' then
+ tumbl_trace_kick <= '0';
+ tumbl_trace_kick_ack <= '0';
+ else
+ if tumbl_trace_kick = '0' and tumbl_trace_kick_req = '1' then
+ tumbl_trace_kick <= '1';
+ tumbl_trace_kick_ack <= '1';
+ else
+ tumbl_trace_kick <= '0';
+ end if;
+ end if;
+
+ if tumbl_trace_kick_req <= '0' then
+ tumbl_trace_kick_ack <= '0';
+ end if;
+
+ end if;
+
+ end process;
+
+end Behavioral;
+
);
port
(
- -- Chip enable
- ce : in std_logic;
-
-- Data bus (read only)
data_out : out std_logic_vector(31 downto 0);
architecture Behavioral of calibration_read_register is
begin
- memory_bus: process(ce, rd)
+ memory_bus: process(rd)
begin
- -- Init defaults
- ta <= '1';
- data_out <= (others => 'X');
-
- if ce = '0' and rd = '0' then
- ta <= '0';
- data_out <= id;
- end if;
+ ta <= rd;
+ data_out <= id;
end process;
begin
-- Read is immideate
- memory_bus_read: process(ce, rd, value)
+ memory_bus_read: process(rd, value)
begin
- -- Init defaults
- ta <= '1';
- data_out <= (others => 'X');
-
- if ce = '0' and rd = '0' then
- ta <= '0';
- data_out <= value;
- end if;
+ ta <= rd;
+ data_out <= value;
end process;
-- Write waits for clock
- memory_bus_write: process(clk, reset)
+ memory_bus_write: process(clk)
begin
- if reset = '1' then
- value <= (others => '0');
- end if;
-
if clk = '1' and clk'event then
+ if reset = '1' then
+ value <= (others => '0');
+ end if;
+
if ce = '0' then
if reset = '0' and bls /= "1111" then
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+-- D circuit (filtered)
+
+entity dff2 is
+ port
+ (
+ clk : in std_logic;
+ reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+ );
+end dff2;
+
+architecture behavioral of dff2 is
+ signal last_d : std_logic;
+ signal data: std_logic;
+begin
+ q <= data;
+
+ seq: process(clk)
+ begin
+ if clk = '1' and clk'event then
+ if reset = '1' then
+ last_d <= '0';
+ data <= '0';
+ else
+ if d = last_d then
+ data <= d;
+ end if;
+ end if;
+
+ last_d <= d;
+ end if;
+ end process;
+
+end behavioral;
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$0a6
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\7fM`13twvqMNL{2c6>a7al:;9<pNOBz2~DEV|uIJ
\ No newline at end of file
+++ /dev/null
---------------------------------------------------------------------------------
--- This file is owned and controlled by Xilinx and must be used solely --
--- for design, simulation, implementation and creation of design files --
--- limited to Xilinx devices or technologies. Use with non-Xilinx --
--- devices or technologies is expressly prohibited and immediately --
--- terminates your license. --
--- --
--- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
--- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
--- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
--- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
--- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
--- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
--- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
--- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
--- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
--- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
--- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
--- PARTICULAR PURPOSE. --
--- --
--- Xilinx products are not intended for use in life support appliances, --
--- devices, or systems. Use in such applications are expressly --
--- prohibited. --
--- --
--- (c) Copyright 1995-2013 Xilinx, Inc. --
--- All rights reserved. --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- You must compile the wrapper file control_bram.vhd when simulating
--- the core, control_bram. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-LIBRARY XilinxCoreLib;
--- synthesis translate_on
-ENTITY control_bram IS
- PORT (
- clka : IN STD_LOGIC;
- ena : IN STD_LOGIC;
- wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
- dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- clkb : IN STD_LOGIC;
- enb : IN STD_LOGIC;
- web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
- dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
-END control_bram;
-
-ARCHITECTURE control_bram_a OF control_bram IS
--- synthesis translate_off
-COMPONENT wrapped_control_bram
- PORT (
- clka : IN STD_LOGIC;
- ena : IN STD_LOGIC;
- wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
- dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- clkb : IN STD_LOGIC;
- enb : IN STD_LOGIC;
- web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
- dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
- );
-END COMPONENT;
-
--- Configuration specification
- FOR ALL : wrapped_control_bram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
- GENERIC MAP (
- c_addra_width => 9,
- c_addrb_width => 9,
- c_algorithm => 0,
- c_axi_id_width => 4,
- c_axi_slave_type => 0,
- c_axi_type => 1,
- c_byte_size => 8,
- c_common_clk => 0,
- c_default_data => "0",
- c_disable_warn_bhv_coll => 0,
- c_disable_warn_bhv_range => 0,
- c_enable_32bit_address => 0,
- c_family => "spartan6",
- c_has_axi_id => 0,
- c_has_ena => 1,
- c_has_enb => 1,
- c_has_injecterr => 0,
- c_has_mem_output_regs_a => 0,
- c_has_mem_output_regs_b => 0,
- c_has_mux_output_regs_a => 0,
- c_has_mux_output_regs_b => 0,
- c_has_regcea => 0,
- c_has_regceb => 0,
- c_has_rsta => 0,
- c_has_rstb => 0,
- c_has_softecc_input_regs_a => 0,
- c_has_softecc_output_regs_b => 0,
- c_init_file => "BlankString",
- c_init_file_name => "no_coe_file_loaded",
- c_inita_val => "0",
- c_initb_val => "0",
- c_interface_type => 0,
- c_load_init_file => 0,
- c_mem_type => 2,
- c_mux_pipeline_stages => 0,
- c_prim_type => 3,
- c_read_depth_a => 288,
- c_read_depth_b => 288,
- c_read_width_a => 32,
- c_read_width_b => 32,
- c_rst_priority_a => "CE",
- c_rst_priority_b => "CE",
- c_rst_type => "SYNC",
- c_rstram_a => 0,
- c_rstram_b => 0,
- c_sim_collision_check => "ALL",
- c_use_bram_block => 0,
- c_use_byte_wea => 1,
- c_use_byte_web => 1,
- c_use_default_data => 1,
- c_use_ecc => 0,
- c_use_softecc => 0,
- c_wea_width => 4,
- c_web_width => 4,
- c_write_depth_a => 288,
- c_write_depth_b => 288,
- c_write_mode_a => "WRITE_FIRST",
- c_write_mode_b => "WRITE_FIRST",
- c_write_width_a => 32,
- c_write_width_b => 32,
- c_xdevicefamily => "spartan6"
- );
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_control_bram
- PORT MAP (
- clka => clka,
- ena => ena,
- wea => wea,
- addra => addra,
- dina => dina,
- douta => douta,
- clkb => clkb,
- enb => enb,
- web => web,
- addrb => addrb,
- dinb => dinb,
- doutb => doutb
- );
--- synthesis translate_on
-
-END control_bram_a;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
+use work.lx_rocon_pkg.all;
-- IRC reader module
entity irc_reader is
port
(
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
- mark0 : in std_logic;
-
- qcount : out std_logic_vector (31 downto 0);
- ab_event : out std_logic;
- ab_error : out std_logic;
- out_index : out std_logic;
- out_mark : out std_logic
+ clk : in std_logic;
+ reset : in std_logic;
+ a0, b0 : in std_logic;
+ index0 : in std_logic;
+ mark0 : in std_logic;
+
+ qcount : out std_logic_vector (31 downto 0);
+ qcount_index : out std_logic_vector (31 downto 0);
+ ab_event : out std_logic;
+ ab_error : out std_logic;
+ out_mark : out std_logic
);
end irc_reader;
-architecture Behavioral of irc_reader is
- component qcounter
- port
- (
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
-
- a_rise : out std_logic;
- a_fall : out std_logic;
- b_rise : out std_logic;
- b_fall : out std_logic;
-
- qcount : out std_logic_vector (31 downto 0);
- ab_event : out std_logic;
- ab_error : out std_logic
- );
- end component;
-
- component dff
- port
- (
- clk : in std_logic;
- reset : in std_logic;
- d : in std_logic;
- q : out std_logic
- );
- end component;
+architecture rtl of irc_reader is
begin
- dff_index: dff
+ dff_mark: dff2
port map
(
clk => clk,
- reset => reset,
- d => index0,
- q => out_index
- );
-
- dff_mark: dff
- port map
- (
- clk => clk,
- reset => reset,
+ reset => '0',
d => mark0,
q => out_mark
);
reset => reset,
a0 => a0,
b0 => b0,
+ index0 => index0,
qcount => qcount,
+ qcount_index => qcount_index,
ab_event => ab_event,
ab_error => ab_error,
a_rise => open,
b_fall => open
);
-end Behavioral;
-
+end rtl;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
+use work.lx_rocon_pkg.all;
-- IRC register: connects IRC output to memory bus
index0 : in std_logic;
mark0 : in std_logic;
- -- Data bus
+ -- Data bus for Master CPU
data_in : in std_logic; -- 1 bit input
data_out : out std_logic_vector(31 downto 0);
signal qcount_error : std_logic;
signal qcount : std_logic_vector (31 downto 0);
signal qcount_index : std_logic_vector (31 downto 0);
- signal qcount_index_prev : std_logic_vector (31 downto 0);
signal ab_event : std_logic;
signal ab_error : std_logic;
- signal old_index : std_logic;
- signal out_index : std_logic;
signal out_mark : std_logic;
component irc_reader
port
(
- clk : in std_logic;
- reset : in std_logic;
- a0, b0 : in std_logic;
- index0 : in std_logic;
- mark0 : in std_logic;
-
- qcount : out std_logic_vector (31 downto 0);
- ab_event : out std_logic;
- ab_error : out std_logic;
- out_index : out std_logic;
- out_mark : out std_logic
+ clk : in std_logic;
+ reset : in std_logic;
+ a0, b0 : in std_logic;
+ index0 : in std_logic;
+ mark0 : in std_logic;
+
+ qcount : out std_logic_vector (31 downto 0);
+ qcount_index : out std_logic_vector (31 downto 0);
+ ab_event : out std_logic;
+ ab_error : out std_logic;
+ out_mark : out std_logic
);
end component;
index0 => index0,
mark0 => mark0,
qcount => qcount,
+ qcount_index => qcount_index,
ab_event => ab_event,
ab_error => ab_error,
- out_index => out_index,
out_mark => out_mark
);
else
qcount_error <= qcount_error or ab_error;
end if;
-
- old_index <= out_index;
- qcount_index_prev <= qcount_index;
end if;
end process;
- signals: process(reset, old_index, out_index, qcount, qcount_index_prev)
- begin
-
- if reset = '0' and old_index = '0' and out_index = '1' then
- qcount_index <= qcount;
- elsif reset = '1' then
- qcount_index <= (others => '0');
- else
- qcount_index <= qcount_index_prev;
- end if;
-
- end process;
memory_bus: process(ce, rd, qcount, qcount_index, qcount_error, ab_event, ab_error, out_mark)
begin
-- Reset signals
- ta <= '1';
+ ta <= rd;
data_out <= (others => 'X');
-- Check chip enable
case ce is
when "00" =>
- if rd = '0' then
- data_out <= qcount;
- ta <= '0';
- end if;
+ data_out <= qcount;
when "01" =>
- if rd = '0' then
- data_out <= qcount_index;
- ta <= '0';
- end if;
+ data_out <= qcount_index;
when "10" =>
- if rd = '0' then
- data_out(0) <= ab_event;
- data_out(1) <= ab_error;
- data_out(2) <= qcount_error;
- data_out(3) <= out_mark;
- data_out(31 downto 4) <= (others => '0');
- ta <= '0';
- end if;
-
- when others =>
- data_out <= (others => 'X');
+ data_out(0) <= ab_event;
+ data_out(1) <= ab_error;
+ data_out(2) <= qcount_error;
+ data_out(3) <= out_mark;
+ data_out(31 downto 4) <= (others => '0');
+
+ when others => NULL;
end case;
# ====================================================================
# Clock
-NET CLK_CPU PERIOD = 13.8ns HIGH 50%;
-NET CLK_CPU LOC = P15 | IOSTANDARD = LVCMOS33;
-#NET CLK_50M PERIOD = 20.0ns HIGH 50%;
-#NET CLK_50M LOC = P14 | IOSTANDARD = LVCMOS33;
+#NET CLK_CPU PERIOD = 13.8ns HIGH 50%;
+#NET CLK_CPU LOC = P15 | IOSTANDARD = LVCMOS33;
+NET CLK_50M PERIOD = 20.0ns HIGH 50%;
+NET CLK_50M LOC = P14 | IOSTANDARD = LVCMOS33;
# Reset (active LOW)
NET INIT LOC = P39 | IOSTANDARD = LVCMOS33;
--- /dev/null
+/* Firmware file for lx-rocon tumbl coprocessor */
+
+#include <stdint.h>
+
+typedef struct
+{
+ int16_t p;
+ int16_t i;
+ int32_t irc_period;
+ int16_t req_current;
+ int16_t acc_dev;
+ int16_t max_acc;
+} axis_settings;
+
+typedef struct
+{
+ /* Input */
+ int16_t current;
+ int32_t irc;
+ int32_t irc_last;
+ int32_t irc_norm;
+
+ /* Output */
+ uint16_t pwm[3];
+} axis_io;
+
+axis_settings a_settings;
+
+axis_io a_io;
+int32_t irc_a_reg;
+int16_t current_a_reg;
+uint32_t count;
+int16_t phase_table[1][1];
+
+void init_defvals()
+{
+ a_settings.p = 20;
+ a_settings.i = 2;
+ a_settings.irc_period = 7000;
+ a_settings.req_current = 500;
+ a_settings.acc_dev = 0;
+}
+
+void update_axis(axis_settings *settings, axis_io* io)
+{
+ int i;
+ int16_t dev;
+ int32_t mag, irc_diff;
+
+ dev = settings->req_current - io->current;
+ settings->acc_dev += dev;
+
+ if (settings->acc_dev > settings->max_acc)
+ settings->acc_dev = settings->max_acc;
+ else if (-(settings->acc_dev) <= -(settings->max_acc))
+ settings->acc_dev = -(settings->max_acc);
+
+ mag = settings->acc_dev * settings->i + dev * settings->p;
+
+ irc_diff = io->irc - io->irc_last;
+ io->irc_last = io->irc;
+ io->irc_norm += irc_diff;
+
+ if (io->irc_norm > settings->irc_period)
+ io->irc_norm -= settings->irc_period;
+ else if (io->irc_norm < 0)
+ io->irc_norm += settings->irc_period;
+
+ for (i = 0; i < 3; i++)
+ io->pwm[i] = (uint16_t)((mag * phase_table[/*i*/ 0][/*irc_norm*/ 0]) >> 16);
+}
+
+void main()
+{
+ while (1)
+ {
+ update_axis(&a_settings, &a_io);
+ a_io.irc = irc_a_reg;
+ a_io.current = current_a_reg;
+ count++;
+ }
+}
+
--- /dev/null
+/* LX ROCON firmware startup file */
+
+.globl _main
+.align 2
+
+_main:
+
+ /* Stack pointer */
+ addi r1, r0, 0xFFC
+
+ /* Other register values are not initialized to 0 */
+ addi r2, r0, 0
+ addi r3, r0, 0
+ addi r4, r0, 0
+ addi r5, r0, 0
+ addi r6, r0, 0
+ addi r7, r0, 0
+ addi r8, r0, 0
+ addi r9, r0, 0
+ addi r10, r0, 0
+ addi r11, r0, 0
+ addi r12, r0, 0
+ addi r13, r0, 0
+ addi r14, r0, 0
+ addi r15, r0, 0
+ addi r16, r0, 0
+ addi r17, r0, 0
+ addi r18, r0, 0
+ addi r19, r0, 0
+ addi r20, r0, 0
+ addi r21, r0, 0
+ addi r22, r0, 0
+ addi r23, r0, 0
+ addi r24, r0, 0
+ addi r25, r0, 0
+ addi r26, r0, 0
+ addi r27, r0, 0
+ addi r28, r0, 0
+ addi r29, r0, 0
+ addi r30, r0, 0
+ addi r31, r0, 0
+
+ /* reset data */
+ addi r6, r0, _sdata
+ addi r7, r0, _edata
+ rsub r18, r6, r7
+ blei r18, .Lenddata
+.Lloopdata:
+ swi r0, r6, 0
+ addi r6, r6, 4
+ rsub r18, r6, r7
+ bgti r18, .Lloopdata
+ or r0, r0, r0
+.Lenddata:
+ /* Init default values */
+ brlid r15, init_defvals
+ addi r31, r0, 20
+ or r0, r0, r0
+
+ /* Run program */
+ brlid r15, main
+ or r0, r0, r0
+
+ /* End of program */
+ bri 0x00
+ or r0, r0, r0
--- /dev/null
+../../submodule/tumbl/utils
\ No newline at end of file
--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.mbl_Pkg.all;
+use work.lx_rocon_pkg.all;
+
+-- 4 kB data memory for Thumbl core
+-- To be flashed from the Master CPU
+
+entity lx_rocon_dmem is
+ port
+ (
+ -- Memory wiring for Tumbl
+ clk_i : in std_logic;
+ ce_i : in std_logic;
+ adr_i : in std_logic_vector(11 downto 2);
+ wre_i : in std_logic;
+ bsel_i : in std_logic_vector(3 downto 0);
+ dat_i : in std_logic_vector(31 downto 0);
+ dat_o : out std_logic_vector(31 downto 0);
+
+ -- Memory wiring for Master CPU
+ clk_m : in std_logic;
+ en_m : in std_logic;
+ we_m : in std_logic_vector(3 downto 0);
+ addr_m : in std_logic_vector(9 downto 0);
+ din_m : in std_logic_vector(31 downto 0);
+ dout_m : out std_logic_vector(31 downto 0)
+
+ );
+end lx_rocon_dmem;
+
+architecture rtl of lx_rocon_dmem is
+
+ signal wre_i_s : std_logic_vector(3 downto 0);
+
+begin
+
+ wre_i_s <= bsel_i when (wre_i = '1') else "0000";
+
+ I_RAMB: xilinx_dualport_bram
+ generic map
+ (
+ we_width => 4,
+ byte_width => 8,
+ address_width => 10
+ )
+ port map
+ (
+ -- Tumblr port
+ clka => clk_i,
+ rsta => '0',
+ ena => ce_i,
+ wea => wre_i_s,
+ addra => adr_i(11 downto 2),
+ dina => dat_i,
+ douta => dat_o,
+
+ -- Master CPU port
+ clkb => clk_m,
+ rstb => '0',
+ enb => en_m,
+ web => we_m,
+ addrb => addr_m,
+ dinb => din_m,
+ doutb => dout_m
+ );
+
+end rtl;
--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.mbl_Pkg.all;
+use work.lx_rocon_pkg.all;
+
+-- 32x32b General Puprose Registers for Tumbl Core
+-- Uses 3 BRAMs
+
+entity lx_rocon_gprf_abd is
+ port
+ (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ clken_i : in std_logic;
+
+ ID2GPRF_i : in ID2GPRF_Type;
+ MEM_WRB_i : in WRB_Type;
+ GPRF2EX_o : out GPRF2EX_Type
+ );
+end entity lx_rocon_gprf_abd;
+
+architecture rtl of lx_rocon_gprf_abd is
+
+ signal rdix_rA_s : std_logic_vector(4 downto 0);
+ signal rdix_rB_s : std_logic_vector(4 downto 0);
+ signal rdix_rD_s : std_logic_vector(4 downto 0);
+
+ signal wre_rD_s : std_logic;
+ signal ena_rA_s : std_logic;
+ signal ena_rB_s : std_logic;
+ signal ena_rD_s : std_logic;
+
+ signal clken_s : std_logic;
+
+ signal wthru_rA_r : std_logic;
+ signal rA_DOA_s : std_logic_vector(31 downto 0);
+ signal rA_DOB_s : std_logic_vector(31 downto 0);
+ signal wthru_rB_r : std_logic;
+ signal rB_DOA_s : std_logic_vector(31 downto 0);
+ signal rB_DOB_s : std_logic_vector(31 downto 0);
+ signal wthru_rD_r : std_logic;
+ signal rD_DOA_s : std_logic_vector(31 downto 0);
+ signal rD_DOB_s : std_logic_vector(31 downto 0);
+
+begin
+
+ -- writeback if WRB_EX or WRB_MEM, but not when r0 involved
+ wre_rD_s <= '1' when ((MEM_WRB_i.wrb_Action /= NO_WRB) and
+ (MEM_WRB_i.wrix_rD /= "00000")) else '0';
+
+ -- ports A should remain unchanged when clken_i is low, while also
+ -- reading from the same address as will be written to should be disabled
+ -- (setup for writeThru of data_rD)
+ ena_rA_s <= '1' when rst_i = '1' else clken_i when ((ID2GPRF_i.rdix_rA /= MEM_WRB_i.wrix_rD)) else '0';
+ ena_rB_s <= '1' when rst_i = '1' else clken_i when ((ID2GPRF_i.rdix_rB /= MEM_WRB_i.wrix_rD)) else '0';
+ ena_rD_s <= '1' when rst_i = '1' else clken_i when ((ID2GPRF_i.rdix_rD /= MEM_WRB_i.wrix_rD)) else '0';
+
+ -- make sure reset does it's job (writes 0 to R0 and resets the ports)
+ clken_s <= rst_i or clken_i;
+ rdix_rA_s <= (others => '0') when rst_i = '1' else ID2GPRF_i.rdix_rA;
+ rdix_rB_s <= (others => '0') when rst_i = '1' else ID2GPRF_i.rdix_rB;
+ rdix_rD_s <= (others => '0') when rst_i = '1' else ID2GPRF_i.rdix_rD;
+
+ GPRF2EX_o.data_rA <= rA_DOA_s when (wthru_rA_r = '0') else rA_DOB_s;
+ GPRF2EX_o.data_rB <= rB_DOA_s when (wthru_rB_r = '0') else rB_DOB_s;
+ GPRF2EX_o.data_rD <= rD_DOA_s when (wthru_rD_r = '0') else rD_DOB_s; -- also for rD ???
+
+ I_rA: xilinx_dualport_bram
+ generic map
+ (
+ byte_width => 32,
+ we_width => 1,
+ address_width => 5
+ )
+ port map
+ (
+ clka => clk_i,
+ rsta => rst_i,
+ ena => ena_rA_s,
+ wea(0) => rst_i,
+ addra => rdix_rA_s,
+ dina => C_32_ZEROS,
+ douta => rA_DOA_s,
+ -- Write-back
+ clkb => clk_i,
+ rstb => rst_i,
+ enb => clken_s,
+ web(0) => wre_rD_s,
+ addrb => MEM_WRB_i.wrix_rD,
+ dinb => MEM_WRB_i.data_rD,
+ doutb => rA_DOB_s
+ );
+
+ I_rB: xilinx_dualport_bram
+ generic map
+ (
+ byte_width => 32,
+ we_width => 1,
+ address_width => 5
+ )
+ port map
+ (
+ clka => clk_i,
+ rsta => rst_i,
+ ena => ena_rB_s,
+ wea(0) => rst_i,
+ addra => rdix_rB_s,
+ dina => C_32_ZEROS,
+ douta => rB_DOA_s,
+ -- Write-back
+ clkb => clk_i,
+ rstb => rst_i,
+ enb => clken_s,
+ web(0) => wre_rD_s,
+ addrb => MEM_WRB_i.wrix_rD,
+ dinb => MEM_WRB_i.data_rD,
+ doutb => rB_DOB_s
+ );
+
+ I_rD: xilinx_dualport_bram
+ generic map
+ (
+ byte_width => 32,
+ we_width => 1,
+ address_width => 5
+ )
+ port map
+ (
+ clka => clk_i,
+ rsta => rst_i,
+ ena => ena_rD_s,
+ wea(0) => rst_i,
+ addra => rdix_rD_s,
+ dina => C_32_ZEROS,
+ douta => rD_DOA_s,
+ -- Write-back
+ clkb => clk_i,
+ rstb => rst_i,
+ enb => clken_s,
+ web(0) => wre_rD_s,
+ addrb => MEM_WRB_i.wrix_rD,
+ dinb => MEM_WRB_i.data_rD,
+ doutb => rD_DOB_s
+ );
+
+ p_regd: process(clk_i)
+ begin
+ if clk_i = '1' and clk_i'event then
+ if (clken_i = '1') then
+ wthru_rA_r <= not ena_rA_s;
+ wthru_rB_r <= not ena_rB_s;
+ wthru_rD_r <= not ena_rD_s;
+ end if;
+ end if;
+ end process;
+
+end architecture rtl;
--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.mbl_Pkg.all;
+use work.lx_rocon_pkg.all;
+
+-- 2 kB instruction memory for Thumbl core
+-- To be flashed from the Master CPU
+
+entity lx_rocon_imem is
+ port
+ (
+ -- Memory wiring for Tumbl
+ clk_i : in std_logic;
+ cs_i : in std_logic;
+ adr_i : in std_logic_vector(10 downto 2);
+ dat_o : out std_logic_vector(31 downto 0);
+
+ -- Memory wiring for Master CPU
+ clk_m : in std_logic;
+ en_m : in std_logic;
+ we_m : in std_logic_vector(3 downto 0);
+ addr_m : in std_logic_vector(8 downto 0);
+ din_m : in std_logic_vector(31 downto 0);
+ dout_m : out std_logic_vector(31 downto 0)
+
+ );
+end lx_rocon_imem;
+
+architecture rtl of lx_rocon_imem is
+begin
+
+ I_RAMB: xilinx_dualport_bram
+ generic map
+ (
+ we_width => 4,
+ byte_width => 8,
+ address_width => 9
+ )
+ port map
+ (
+ -- Tumblr port
+ clka => clk_i,
+ rsta => '0',
+ ena => cs_i,
+ wea => "0000",
+ addra => adr_i(10 downto 2),
+ dina => C_32_ZEROS,
+ douta => dat_o,
+
+ -- Master CPU port
+ clkb => clk_m,
+ rstb => '0',
+ enb => en_m,
+ web => we_m,
+ addrb => addr_m,
+ dinb => din_m,
+ doutb => dout_m
+ );
+
+end rtl;
--- /dev/null
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.mbl_Pkg.all;
+use work.lx_rocon_pkg.all;
+
+-- Tumbl configured as a coprocessor for lx_rocon
+-- Uses 10 bits width address bus with HW barrel and multiplier
+
+entity lx_rocon_tumbl is
+ generic
+ (
+ IMEM_ABITS_g : positive := 11;
+ DMEM_ABITS_g : positive := 12;
+ --
+ USE_HW_MUL_g : boolean := true;
+ USE_BARREL_g : boolean := true
+ );
+ port
+ (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ halt_i : in std_logic;
+ int_i : in std_logic;
+ trace_i : in std_logic;
+ trace_kick_i : in std_logic;
+
+ -- Program counter
+ pc_o : out std_logic_vector(31 downto 0);
+
+ -- Internal memory (instruction)
+ imem_clk : in std_logic;
+ imem_en : in std_logic;
+ imem_we : in std_logic_vector(3 downto 0);
+ imem_addr : in std_logic_vector(8 downto 0);
+ imem_din : in std_logic_vector(31 downto 0);
+ imem_dout : out std_logic_vector(31 downto 0);
+
+ -- Internal memory (data)
+ dmem_clk : in std_logic;
+ dmem_en : in std_logic;
+ dmem_we : in std_logic_vector(3 downto 0);
+ dmem_addr : in std_logic_vector(9 downto 0);
+ dmem_din : in std_logic_vector(31 downto 0);
+ dmem_dout : out std_logic_vector(31 downto 0);
+
+ -- External memory bus
+ XMEMB_sel_o : out std_logic;
+ XMEMB_i : in DMEMB2CORE_Type;
+ XMEMB_o : out CORE2DMEMB_Type;
+ --
+ bad_op_o : out std_logic;
+ done_o : out std_logic
+ );
+end entity lx_rocon_tumbl;
+
+architecture rtl of lx_rocon_tumbl is
+
+ constant DMEM_TEST_c : std_logic_vector((31-DMEM_ABITS_g) downto 0) := (others => '0');
+
+ signal imem_clken_s : std_logic;
+ signal imem_addr_s : std_logic_vector(31 downto 0);
+ signal imem_data_s : std_logic_vector(31 downto 0);
+ signal gprf_clken_s : std_logic;
+ signal core_clk_en_s : std_logic;
+ signal pc_ctrl_s : std_logic;
+ signal c2dmemb_s : CORE2DMEMB_Type;
+ signal dmem_data_s : std_logic_vector(31 downto 0);
+ signal DMEMB_i_s : DMEMB2CORE_Type;
+
+ signal MEM2CTRL_s : MEM2CTRL_Type;
+ signal INT_CTRL_s : INT_CTRL_Type;
+ signal ID2CTRL_s : ID2CTRL_Type;
+
+ signal IF2ID_s, IF2ID_r : IF2ID_Type;
+ signal ID2EX_s, ID2EX_r : ID2EX_Type;
+ signal ID2GPRF_s : ID2GPRF_Type;
+ signal GPRF2EX_s : GPRF2EX_Type;
+ signal EX2IF_s, EX2IF_r : EX2IF_Type;
+ signal EX2MEM_s, EX2MEM_r : EX2MEM_Type;
+ signal EX_WRB_s, EX_WRB_r : WRB_Type;
+ signal MEM_WRB_s : WRB_Type;
+ signal IMM_LOCK_s, IMM_LOCK_r : IMM_LOCK_Type;
+ signal HAZARD_WRB_s, HAZARD_WRB_r : HAZARD_WRB_Type;
+ signal EX2MSR_s : MSR_Type;
+ signal MSR2EX_s : MSR_Type;
+ signal MEM_REG_s, MEM_REG_r : MEM_REG_Type;
+ signal dmem_sel_s, dmem_sel_r : std_logic;
+ signal BAD_OP_s : std_logic;
+ signal BAD_OP_up_s : std_logic;
+ signal halt_s : std_logic;
+
+ signal imem_really_clken_s : std_logic;
+ signal dmem_really_sel_s : std_logic;
+ signal gprf_really_clken_s : std_logic;
+
+begin
+
+ -- select internal data memory when all address bits above DMEM_ABITS_g are zero
+ dmem_sel_s <= '1' when (c2dmemb_s.addr(31 downto DMEM_ABITS_g) = DMEM_TEST_c)
+ else '0';
+ XMEMB_sel_o <= not dmem_sel_s;
+ XMEMB_o <= c2dmemb_s;
+ pc_o <= ID2EX_r.program_counter; -- Program counter for EXEQ
+ bad_op_o <= BAD_OP_s;
+ halt_s <= halt_i or BAD_OP_up_s;
+
+ imem_really_clken_s <= imem_clken_s and core_clk_en_s;
+ dmem_really_sel_s <= dmem_sel_s and core_clk_en_s;
+ gprf_really_clken_s <= gprf_clken_s and core_clk_en_s;
+
+ I_IMEM: lx_rocon_imem
+ port map
+ (
+ clk_i => clk_i,
+ cs_i => imem_really_clken_s,
+ adr_i => imem_addr_s((IMEM_ABITS_g-1) downto 2),
+ dat_o => imem_data_s,
+
+ clk_m => imem_clk,
+ en_m => imem_en,
+ we_m => imem_we,
+ addr_m => imem_addr,
+ din_m => imem_din,
+ dout_m => imem_dout
+ );
+
+ I_DMEM: lx_rocon_dmem
+ port map
+ (
+ clk_i => clk_i,
+ ce_i => dmem_really_sel_s,
+ adr_i => c2dmemb_s.addr((DMEM_ABITS_g-1) downto 2),
+ wre_i => c2dmemb_s.wre,
+ bsel_i => c2dmemb_s.bSel,
+ dat_i => c2dmemb_s.data,
+ dat_o => dmem_data_s,
+
+ clk_m => dmem_clk,
+ en_m => dmem_en,
+ we_m => dmem_we,
+ addr_m => dmem_addr,
+ din_m => dmem_din,
+ dout_m => dmem_dout
+ );
+
+ I_FETCH: fetch
+ port map
+ (
+ prog_cntr_i => IF2ID_r.program_counter,
+ inc_pc_i => pc_ctrl_s,
+ EX2IF_i => EX2IF_r,
+ IF2ID_o => IF2ID_s
+ );
+
+ I_DECODE: decode
+ generic map(USE_HW_MUL_g, USE_BARREL_g)
+ port map
+ (
+ IF2ID_i => IF2ID_r,
+ imem_data_i => imem_data_s,
+ --
+ ID2GPRF_o => ID2GPRF_s,
+ ID2EX_o => ID2EX_s,
+ --
+ INT_CTRL_i => INT_CTRL_s,
+ ID2CTRL_o => ID2CTRL_s,
+ --
+ noLiteOpc_o => BAD_OP_s
+ );
+
+ I_GPRF: lx_rocon_gprf_abd
+ port map
+ (
+ clk_i => clk_i,
+ rst_i => rst_i,
+ clken_i => gprf_really_clken_s,
+ --
+ ID2GPRF_i => ID2GPRF_s,
+ MEM_WRB_i => MEM_WRB_s,
+ GPRF2EX_o => GPRF2EX_s
+ );
+
+ I_EXEQ: exeq
+ generic map(USE_HW_MUL_g, USE_BARREL_g)
+ port map
+ (
+ ID2EX_i => ID2EX_r,
+ GPRF2EX_i => GPRF2EX_s,
+ EX2IF_o => EX2IF_s,
+ --
+ EX_WRB_i => EX_WRB_r,
+ EX_WRB_o => EX_WRB_s,
+ MEM_WRB_i => MEM_WRB_s,
+ --
+ HAZARD_WRB_i => HAZARD_WRB_r,
+ HAZARD_WRB_o => HAZARD_WRB_s,
+ --
+ IMM_LOCK_i => IMM_LOCK_r,
+ IMM_LOCK_o => IMM_LOCK_s,
+ --
+ MSR_i => MSR2EX_s,
+ MSR_o => EX2MSR_s,
+ --
+ EX2MEM_o => EX2MEM_s
+ );
+
+ -- this is a very simple address block decoder, just "internal" dmem or "external"
+ -- clken and int hardwired for fast internal data-memory
+ DMEMB_i_s.clken <= '1' when (dmem_sel_s = '1') else XMEMB_i.clken;
+ DMEMB_i_s.data <= dmem_data_s when (dmem_sel_r = '1') else XMEMB_i.data;
+ DMEMB_i_s.int <= XMEMB_i.int;
+
+ I_MEM: mem
+ port map
+ (
+ EX2MEM_i => EX2MEM_r,
+ MEM_WRB_o => MEM_WRB_s,
+ --
+ DMEMB_i => DMEMB_i_s,
+ DMEMB_o => c2dmemb_s,
+ --
+ MEM_REG_i => MEM_REG_r,
+ MEM_REG_o => MEM_REG_s,
+ --
+ MEM2CTRL_o => MEM2CTRL_s
+ );
+
+ I_CTRL: core_ctrl
+ port map
+ (
+ clk_i => clk_i,
+ rst_i => rst_i,
+ halt_i => halt_s,
+ int_i => int_i,
+ trace_i => trace_i,
+ trace_kick_i => trace_kick_i,
+ core_clk_en_o => core_clk_en_s,
+ -- specific fetch i/o
+ imem_addr_o => imem_addr_s,
+ imem_clken_o => imem_clken_s,
+ pc_ctrl_o => pc_ctrl_s,
+ -- fetch to decode pipeline registers
+ IF2ID_REG_i => IF2ID_s,
+ IF2ID_REG_o => IF2ID_r,
+ -- decode to exeq pipeline registers
+ ID2EX_REG_i => ID2EX_s,
+ ID2EX_REG_o => ID2EX_r,
+ -- GPRF control
+ gprf_clken_o => gprf_clken_s,
+ -- exeq to fetch feedback registers
+ EX2IF_REG_i => EX2IF_s,
+ EX2IF_REG_o => EX2IF_r,
+ -- exeq to mem pipeline registers
+ EX2MEM_REG_i => EX2MEM_s,
+ EX2MEM_REG_o => EX2MEM_r,
+ -- mem pipeline register
+ MEM_REG_i => MEM_REG_s,
+ MEM_REG_o => MEM_REG_r,
+ -- decode control i/o
+ ID2CTRL_i => ID2CTRL_s,
+ INT_CTRL_o => INT_CTRL_s,
+ -- exeq control i/o
+ EX_WRB_i => EX_WRB_s,
+ EX_WRB_o => EX_WRB_r,
+ -- data hazard i/o
+ HAZARD_WRB_i => HAZARD_WRB_s,
+ HAZARD_WRB_o => HAZARD_WRB_r,
+ -- for handling the 'IMM' instruction
+ IMM_LOCK_i => IMM_LOCK_s,
+ IMM_LOCK_o => IMM_LOCK_r,
+ -- for handling the Machine Status Register
+ MSR_i => EX2MSR_s,
+ MSR_o => MSR2EX_s,
+ -- miscellaneous
+ MEM2CTRL_i => MEM2CTRL_s,
+ done_o => done_o
+ );
+
+ regd_proc: process(clk_i, rst_i)
+ begin
+ if clk_i = '1' and clk_i'event then
+ if (rst_i = '1') then -- synchronous reset ...
+ dmem_sel_r <= '1';
+ BAD_OP_up_s <= '0';
+ else -- delay select_external_mem (needed for reading ...)
+ if (DMEMB_i_s.clken = '1') then
+ dmem_sel_r <= dmem_sel_s; -- OR c2dmemb_s.wre; ??
+ end if;
+ BAD_OP_up_s <= BAD_OP_up_s or BAD_OP_s;
+ end if;
+ end if;
+ end process regd_proc;
+
+end architecture rtl;
--- /dev/null
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.mbl_Pkg.ALL;
+USE work.lx_rocon_pkg.ALL;
+
+-- Tumbl core testbench
+
+ENTITY lx_rocon_tumbl_tb IS
+END lx_rocon_tumbl_tb;
+
+ARCHITECTURE behavior OF lx_rocon_tumbl_tb IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT lx_rocon_tumbl
+ PORT(
+ clk_i : IN std_logic;
+ rst_i : IN std_logic;
+ halt_i : IN std_logic;
+ int_i : IN std_logic;
+ trace_i : IN std_logic;
+ trace_kick_i : IN std_logic;
+ pc_o : OUT std_logic_vector(31 downto 0);
+ imem_clk : IN std_logic;
+ imem_en : IN std_logic;
+ imem_we : IN std_logic_vector(3 downto 0);
+ imem_addr : IN std_logic_vector(8 downto 0);
+ imem_din : IN std_logic_vector(31 downto 0);
+ imem_dout : OUT std_logic_vector(31 downto 0);
+ dmem_clk : IN std_logic;
+ dmem_en : IN std_logic;
+ dmem_we : IN std_logic_vector(3 downto 0);
+ dmem_addr : IN std_logic_vector(9 downto 0);
+ dmem_din : IN std_logic_vector(31 downto 0);
+ dmem_dout : OUT std_logic_vector(31 downto 0);
+ XMEMB_sel_o : OUT std_logic;
+ XMEMB_i : IN DMEMB2CORE_Type;
+ XMEMB_o : OUT CORE2DMEMB_Type;
+ bad_op_o : OUT std_logic;
+ done_o : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal clk_i : std_logic := '0';
+ signal rst_i : std_logic := '0';
+ signal halt_i : std_logic := '0';
+ signal int_i : std_logic := '0';
+ signal trace_i : std_logic := '0';
+ signal trace_kick_i : std_logic := '0';
+ signal imem_clk : std_logic := '0';
+ signal imem_en : std_logic := '0';
+ signal imem_we : std_logic_vector(3 downto 0) := (others => '0');
+ signal imem_addr : std_logic_vector(8 downto 0) := (others => '0');
+ signal imem_din : std_logic_vector(31 downto 0) := (others => '0');
+ signal dmem_clk : std_logic := '0';
+ signal dmem_en : std_logic := '0';
+ signal dmem_we : std_logic_vector(3 downto 0) := (others => '0');
+ signal dmem_addr : std_logic_vector(9 downto 0) := (others => '0');
+ signal dmem_din : std_logic_vector(31 downto 0) := (others => '0');
+ signal XMEMB_i : DMEMB2CORE_Type := (clken => '0', data => (others => '0'), int => '0');
+
+ --Outputs
+ signal pc_o : std_logic_vector(31 downto 0);
+ signal imem_dout : std_logic_vector(31 downto 0);
+ signal dmem_dout : std_logic_vector(31 downto 0);
+ signal XMEMB_sel_o : std_logic;
+ signal XMEMB_o : CORE2DMEMB_Type;
+ signal bad_op_o : std_logic;
+ signal done_o : std_logic;
+
+ -- Clock period definitions
+ constant clk_i_period : time := 20 ns; -- 50 MHz
+ constant imem_clk_period : time := 13.8 ns; -- 72 MHz
+ constant dmem_clk_period : time := 13.8 ns; -- 72 MHz
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: lx_rocon_tumbl PORT MAP (
+ clk_i => clk_i,
+ rst_i => rst_i,
+ halt_i => halt_i,
+ int_i => int_i,
+ trace_i => trace_i,
+ trace_kick_i => trace_kick_i,
+ pc_o => pc_o,
+ imem_clk => imem_clk,
+ imem_en => imem_en,
+ imem_we => imem_we,
+ imem_addr => imem_addr,
+ imem_din => imem_din,
+ imem_dout => imem_dout,
+ dmem_clk => dmem_clk,
+ dmem_en => dmem_en,
+ dmem_we => dmem_we,
+ dmem_addr => dmem_addr,
+ dmem_din => dmem_din,
+ dmem_dout => dmem_dout,
+ XMEMB_sel_o => XMEMB_sel_o,
+ XMEMB_i => XMEMB_i,
+ XMEMB_o => XMEMB_o,
+ bad_op_o => bad_op_o,
+ done_o => done_o
+ );
+
+ -- Clock process definitions
+ clk_i_process :process
+ begin
+ clk_i <= '0';
+ wait for clk_i_period/2;
+ clk_i <= '1';
+ wait for clk_i_period/2;
+ end process;
+
+ imem_clk_process :process
+ begin
+ imem_clk <= '0';
+ wait for imem_clk_period/2;
+ imem_clk <= '1';
+ wait for imem_clk_period/2;
+ end process;
+
+ dmem_clk_process :process
+ begin
+ dmem_clk <= '0';
+ wait for dmem_clk_period/2;
+ dmem_clk <= '1';
+ wait for dmem_clk_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- External ModelSim script
+
+ wait;
+ end process;
+
+END;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use work.mbl_Pkg.all;
+
+-- Entities within lx_rocon
+
+package lx_rocon_pkg is
+
+ -- IRC register
+ component irc_register
+ port
+ (
+ clk : in std_logic;
+ reset : in std_logic;
+ a0, b0 : in std_logic;
+ index0 : in std_logic;
+ mark0 : in std_logic;
+ data_in : in std_logic;
+ data_out : out std_logic_vector(31 downto 0);
+ ce : in std_logic_vector(1 downto 0);
+ rd : in std_logic;
+ ta : out std_logic;
+ wr : in std_logic
+ );
+ end component;
+
+ -- BCD counter
+ component bcd
+ generic
+ (
+ width : integer
+ );
+ port
+ (
+ reset : in std_logic;
+ en : in std_logic;
+ clk : in std_logic;
+ value : out std_logic_vector((width-1) downto 0)
+ );
+ end component;
+
+ -- Quadcount
+ component qcounter
+ port
+ (
+ clk : in std_logic;
+ reset : in std_logic;
+ a0, b0 : in std_logic;
+ index0 : in std_logic;
+
+ a_rise : out std_logic;
+ a_fall : out std_logic;
+ b_rise : out std_logic;
+ b_fall : out std_logic;
+
+ qcount : out std_logic_vector (31 downto 0);
+ qcount_index : out std_logic_vector (31 downto 0);
+ ab_event : out std_logic;
+ ab_error : out std_logic
+ );
+ end component;
+
+ -- D sampler
+ component dff
+ port
+ (
+ clk : in std_logic;
+ reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+ );
+ end component;
+
+ -- D sampler (filtered)
+ component dff2
+ port
+ (
+ clk : in std_logic;
+ reset : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+ );
+ end component;
+
+ --------------------------------------------------------------------------------
+ -- TUMBL
+ --------------------------------------------------------------------------------
+
+ component lx_rocon_tumbl
+ generic
+ (
+ IMEM_ABITS_g : positive := 12;
+ DMEM_ABITS_g : positive := 12;
+ --
+ USE_HW_MUL_g : boolean := true;
+ USE_BARREL_g : boolean := true
+ );
+ port
+ (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ halt_i : in std_logic;
+ int_i : in std_logic;
+ trace_i : in std_logic;
+ trace_kick_i : in std_logic;
+ pc_o : out std_logic_vector(31 downto 0);
+ imem_clk : in std_logic;
+ imem_en : in std_logic;
+ imem_we : in std_logic_vector(3 downto 0);
+ imem_addr : in std_logic_vector(8 downto 0);
+ imem_din : in std_logic_vector(31 downto 0);
+ imem_dout : out std_logic_vector(31 downto 0);
+ dmem_clk : in std_logic;
+ dmem_en : in std_logic;
+ dmem_we : in std_logic_vector(3 downto 0);
+ dmem_addr : in std_logic_vector(9 downto 0);
+ dmem_din : in std_logic_vector(31 downto 0);
+ dmem_dout : out std_logic_vector(31 downto 0);
+ XMEMB_sel_o : out std_logic;
+ XMEMB_i : in DMEMB2CORE_Type;
+ XMEMB_o : out CORE2DMEMB_Type;
+ bad_op_o : out std_logic;
+ done_o : out std_logic
+ );
+ end component;
+
+ component lx_rocon_imem
+ port
+ (
+ clk_i : in std_logic;
+ cs_i : in std_logic;
+ adr_i : in std_logic_vector(10 downto 2);
+ dat_o : out std_logic_vector(31 downto 0);
+ clk_m : in std_logic;
+ en_m : in std_logic;
+ we_m : in std_logic_vector(3 downto 0);
+ addr_m : in std_logic_vector(8 downto 0);
+ din_m : in std_logic_vector(31 downto 0);
+ dout_m : out std_logic_vector(31 downto 0)
+
+ );
+ end component;
+
+ component lx_rocon_dmem
+ port
+ (
+ clk_i : in std_logic;
+ ce_i : in std_logic;
+ adr_i : in std_logic_vector(11 downto 2);
+ wre_i : in std_logic;
+ bsel_i : in std_logic_vector(3 downto 0);
+ dat_i : in std_logic_vector(31 downto 0);
+ dat_o : out std_logic_vector(31 downto 0);
+ clk_m : in std_logic;
+ en_m : in std_logic;
+ we_m : in std_logic_vector(3 downto 0);
+ addr_m : in std_logic_vector(9 downto 0);
+ din_m : in std_logic_vector(31 downto 0);
+ dout_m : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component lx_rocon_gprf_abd
+ port
+ (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ clken_i : in std_logic;
+ ID2GPRF_i : in ID2GPRF_Type;
+ MEM_WRB_i : in WRB_Type;
+ GPRF2EX_o : out GPRF2EX_Type
+ );
+ end component;
+
+ --------------------------------------------------------------------------------
+ -- MEMORY BUS
+ --------------------------------------------------------------------------------
+
+ -- Calibration read register
+ component calibration_read_register
+ generic
+ (
+ id : std_logic_vector(31 downto 0)
+ );
+ port
+ (
+ data_out : out std_logic_vector(31 downto 0);
+ rd : in std_logic;
+ ta : out std_logic
+ );
+ end component;
+
+ -- Calibration write register
+ component calibration_write_register
+ port
+ (
+ clk : in std_logic;
+ reset : in std_logic;
+ ce : in std_logic;
+ data_in : in std_logic_vector(31 downto 0);
+ data_out : out std_logic_vector(31 downto 0);
+ rd : in std_logic;
+ bls : in std_logic_vector(3 downto 0);
+ ta : out std_logic
+ );
+ end component;
+
+ -- Calibration interconnect
+ component bus_calibration
+ port
+ (
+ clk : in std_logic;
+ reset : in std_logic;
+ ce : in std_logic;
+ address : in std_logic_vector(1 downto 0);
+ data_in : in std_logic_vector(31 downto 0);
+ data_out : out std_logic_vector(31 downto 0);
+ rd : in std_logic;
+ bls : in std_logic_vector(3 downto 0);
+ ta : out std_logic
+ );
+ end component;
+
+ -- IRC interconnect
+ component bus_irc
+ port
+ (
+ clk : in std_logic;
+ reset : in std_logic;
+
+ address : in std_logic_vector(3 downto 0);
+ ce : in std_logic;
+
+ data_in : in std_logic;
+ data_out : out std_logic_vector(31 downto 0);
+
+ rd : in std_logic;
+ wr : in std_logic;
+ ta : out std_logic;
+
+ irc1_a : in std_logic;
+ irc1_b : in std_logic;
+ irc1_index : in std_logic;
+ irc1_mark : in std_logic;
+
+ irc2_a : in std_logic;
+ irc2_b : in std_logic;
+ irc2_index : in std_logic;
+ irc2_mark : in std_logic;
+
+ irc3_a : in std_logic;
+ irc3_b : in std_logic;
+ irc3_index : in std_logic;
+ irc3_mark : in std_logic;
+
+ irc4_a : in std_logic;
+ irc4_b : in std_logic;
+ irc4_index : in std_logic;
+ irc4_mark : in std_logic
+ );
+ end component;
+
+ -- BCD interconnect
+ component bus_bcd
+ port
+ (
+ reset : in std_logic;
+ en : in std_logic;
+ clk : in std_logic;
+ data_out : out std_logic_vector(31 downto 0);
+ rd : in std_logic;
+ ta : out std_logic
+ );
+ end component;
+
+ -- Tumbl interconnect
+ component bus_tumbl
+ port
+ (
+ clk_100m : in std_logic;
+ clk_50m : in std_logic;
+ ce : in std_logic;
+ reset : in std_logic;
+ rd : in std_logic;
+ bls : in std_logic_vector(3 downto 0);
+ address : in std_logic_vector(11 downto 0);
+ data_in : in std_logic_vector(31 downto 0);
+ data_out : out std_logic_vector(31 downto 0);
+ ta : out std_logic;
+ XMEMB_sel_o : out std_logic;
+ XMEMB_i : in DMEMB2CORE_Type;
+ XMEMB_o : out CORE2DMEMB_Type
+ );
+ end component;
+
+ --------------------------------------------------------------------------------
+ -- BRAM
+ --------------------------------------------------------------------------------
+
+ component xilinx_dualport_bram
+ generic
+ (
+ byte_width : positive := 8;
+ address_width : positive := 8;
+ we_width : positive := 4
+ );
+ port
+ (
+ clka : in std_logic;
+ rsta : in std_logic;
+ ena : in std_logic;
+ wea : in std_logic_vector((we_width-1) downto 0);
+ addra : in std_logic_vector((address_width-1) downto 0);
+ dina : in std_logic_vector(((byte_width*we_width)-1) downto 0);
+ douta : out std_logic_vector(((byte_width*we_width)-1) downto 0);
+ clkb : in std_logic;
+ rstb : in std_logic;
+ enb : in std_logic;
+ web : in std_logic_vector((we_width-1) downto 0);
+ addrb : in std_logic_vector((address_width-1) downto 0);
+ dinb : in std_logic_vector(((byte_width*we_width)-1) downto 0);
+ doutb : out std_logic_vector(((byte_width*we_width)-1) downto 0)
+ );
+ end component;
+
+end lx_rocon_pkg;
+
+package body lx_rocon_pkg is
+
+
+end lx_rocon_pkg;
-vhdl work "dff.vhd"
+vhdl work "tumbl/mbl_Pkg.vhd"
+vhdl work "lx_rocon_pkg.vhd"
+vhdl work "dff2.vhd"
+vhdl work "xilinx_dualport_bram.vhd"
vhdl work "qcounter.vhd"
+vhdl work "tumbl/mem.vhd"
+vhdl work "tumbl/fetch.vhd"
+vhdl work "tumbl/exeq.vhd"
+vhdl work "tumbl/decode.vhd"
+vhdl work "tumbl/core_ctrl.vhd"
+vhdl work "lx-rocon_tumbl/lx_rocon_imem.vhd"
+vhdl work "lx-rocon_tumbl/lx_rocon_gprf_abd.vhd"
+vhdl work "lx-rocon_tumbl/lx_rocon_dmem.vhd"
vhdl work "irc_reader.vhd"
+vhdl work "lx-rocon_tumbl/lx_rocon_tumbl.vhd"
vhdl work "irc_register.vhd"
-vhdl work "ipcore_dir/control_bram.vhd"
vhdl work "calibration_write_register.vhd"
vhdl work "calibration_read_register.vhd"
-vhdl work "bcd.vhd"
+vhdl work "bus_tumbl.vhd"
vhdl work "bus_irc.vhd"
-vhdl work "bus_control_bram.vhd"
vhdl work "bus_calibration.vhd"
-vhdl work "bus_bcd.vhd"
vhdl work "lx_rocon_top.vhd"
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--- lx_rocon_top - wires the modules with outside world
+library unisim;
+use unisim.vcomponents.all;
+
+use work.mbl_Pkg.all;
+use work.lx_rocon_pkg.all;
+
+-- lx_rocon_top - wires the modules with the outside world
-- ======================================================
--- INTERNAL MEMORY BUS
+-- MASTER CPU EXTERNAL MEMORY BUS
-- ======================================================
--
--- Internal memory bus has the following wires:
+-- Master cpu memory bus has the following wires:
--
-- - address[15..0] The address
-- - data_in[31..0] The data coming to bus
-- - bls[3..0] Write enable for respective bytes, active LOW
-- In some cases, only WR is used
-- - ta Transaction acknowledge (latches data out), active LOW, multiplexed
+--
+-- ======================================================
+-- TUMBL EXTERNAL MEMORY BUS
+-- ======================================================
entity lx_rocon_top is
port
(
-- External
- clk_cpu : in std_logic;
+ --clk_cpu : in std_logic;
+ clk_50m : in std_logic;
cs0_xc : in std_logic;
-- Reset signal
signal reset : std_logic;
+ signal neg_init : std_logic;
+
+ -- 100 MHz clock
+ signal clk_100m : std_logic;
+ signal clk_100m_fb : std_logic;
+ signal clk_100m_locked : std_logic;
-- Peripherals on the memory bus
- signal bram_out : std_logic_vector(31 downto 0);
- signal bram_ta : std_logic;
- signal bram_ce : std_logic;
+ signal tumbl_out : std_logic_vector(31 downto 0);
+ signal tumbl_ta : std_logic;
+ signal tumbl_ce : std_logic;
signal irc_reg_out : std_logic_vector(31 downto 0);
signal irc_reg_ta : std_logic;
signal irc_reg_ce : std_logic;
- signal bcd_out : std_logic_vector(31 downto 0);
- signal bcd_ta : std_logic;
- signal bcd_ce : std_logic;
-
signal calib_out : std_logic_vector(31 downto 0);
signal calib_ta : std_logic;
signal calib_ce : std_logic;
-- Data latching is synchronous - it's purpose is to
-- provide stable data for CPU on the bus on high rise
-- of trans. ack signal
+ signal rd_f : std_logic;
+ signal rd_d : std_logic;
+
+ signal data_read : std_logic_vector(31 downto 0);
+
signal i_ta : std_logic;
signal i_rd : std_logic;
- signal data_read : std_logic_vector(31 downto 0);
signal acked : std_logic;
-- Writing logic:
- signal i_bls : std_logic_vector(3 downto 0);
+ signal bls_f : std_logic_vector(3 downto 0);
+ signal bls_d : std_logic_vector(3 downto 0);
+
signal data_write : std_logic_vector(31 downto 0);
- component bus_irc
- port
- (
- clk : in std_logic;
- reset : in std_logic;
-
- address : in std_logic_vector(3 downto 0);
- ce : in std_logic;
-
- data_in : in std_logic;
- data_out : out std_logic_vector(31 downto 0);
-
- rd : in std_logic;
- wr : in std_logic;
- ta : out std_logic;
-
- irc1_a : in std_logic;
- irc1_b : in std_logic;
- irc1_index : in std_logic;
- irc1_mark : in std_logic;
-
- irc2_a : in std_logic;
- irc2_b : in std_logic;
- irc2_index : in std_logic;
- irc2_mark : in std_logic;
-
- irc3_a : in std_logic;
- irc3_b : in std_logic;
- irc3_index : in std_logic;
- irc3_mark : in std_logic;
-
- irc4_a : in std_logic;
- irc4_b : in std_logic;
- irc4_index : in std_logic;
- irc4_mark : in std_logic
- );
- end component;
+ signal i_bls : std_logic_vector(3 downto 0);
- component bus_control_bram
- port
- (
- clk : in std_logic;
-
- ena : in std_logic;
- wea : in std_logic_vector(3 downto 0);
- addra : in std_logic_vector(8 downto 0);
- dina : in std_logic_vector(31 downto 0);
- douta : out std_logic_vector(31 downto 0);
- taa : out std_logic;
-
- enb : in std_logic;
- web : in std_logic_vector(3 downto 0);
- addrb : in std_logic_vector(8 downto 0);
- dinb : in std_logic_vector(31 downto 0);
- doutb : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component bus_bcd
- port
- (
- reset : in std_logic;
- en : in std_logic;
- clk : in std_logic;
- ce : in std_logic;
- data_out : out std_logic_vector(31 downto 0);
- rd : in std_logic;
- ta : out std_logic
- );
- end component;
+begin
- component bus_calibration
- port
+ -- Clocking
+ clk_100m_dcm_sp : DCM_SP
+ generic map
(
- clk : in std_logic;
- reset : in std_logic;
- ce : in std_logic;
- address : in std_logic_vector(1 downto 0);
- data_in : in std_logic_vector(31 downto 0);
- data_out : out std_logic_vector(31 downto 0);
- rd : in std_logic;
- bls : in std_logic_vector(3 downto 0);
- ta : out std_logic
+ clkdv_divide => 2.0,
+ clkfx_divide => 1,
+ clkfx_multiply => 2,
+ clkin_divide_by_2 => false,
+ clkin_period => 20.0, -- 50 MHz
+ clkout_phase_shift => "NONE",
+ clk_feedback => "1X",
+ deskew_adjust => "SYSTEM_SYNCHRONOUS",
+ dfs_frequency_mode => "LOW",
+ dll_frequency_mode => "LOW",
+ dss_mode => "NONE",
+ duty_cycle_correction => true,
+ factory_jf => X"c080",
+ phase_shift => 0,
+ startup_wait => false
+ )
+ port map
+ (
+ clk0 => clk_100m_fb,
+ clk180 => open,
+ clk270 => open,
+ clk2x => clk_100m,
+ clk2x180 => open,
+ clk90 => open,
+ clkdv => open,
+ clkfx => open,
+ clkfx180 => open,
+ locked => clk_100m_locked,
+ psdone => open,
+ status => open,
+ clkfb => clk_100m_fb,
+ clkin => clk_50m,
+ dssen => '0',
+ psclk => '0',
+ psen => '0',
+ psincdec => '0',
+ rst => neg_init
);
- end component;
-
-begin
-- IRC interconnect
memory_bus_irc: bus_irc
port map
(
- clk => clk_cpu,
+ clk => clk_100m,
reset => reset,
address => address(3 downto 0),
ce => irc_reg_ce,
data_in => data_in_bus(0),
data_out => irc_reg_out,
rd => i_rd,
- wr => bls(0),
+ wr => i_bls(0),
ta => irc_reg_ta,
irc1_a => irc1_a,
irc4_mark => irc4_mark
);
- -- Control BRAM interconnect (9 kib)
- memory_bus_control_bram: bus_control_bram
+ -- Tumbl coprocessor
+ memory_bus_tumbl: bus_tumbl
port map
(
- clk => clk_cpu,
- ena => bram_ce,
- taa => bram_ta,
- wea => i_bls,
- addra => address(8 downto 0),
- dina => data_in_bus,
- douta => bram_out,
-
- enb => '0',
- web => (others => '0'),
- addrb => (others => '0'),
- dinb => (others => '0'),
- doutb => open
- );
-
- -- BCD
- memory_bus_bcd: bus_bcd
- port map
- (
- clk => clk_cpu,
+ clk_100m => clk_100m,
+ clk_50m => clk_50m,
reset => reset,
- en => '1',
- ce => bcd_ce,
+ ce => tumbl_ce,
+ ta => tumbl_ta,
rd => i_rd,
- ta => bcd_ta,
- data_out => bcd_out
+ bls => i_bls,
+ address => address(11 downto 0),
+ data_in => data_in_bus,
+ data_out => tumbl_out,
+
+ XMEMB_o => open,
+ XMEMB_i.clken => '1',
+ XMEMB_i.data => (others => '1'),
+ XMEMB_i.int => '0',
+ XMEMB_sel_o => open
);
-- Calibration
memory_bus_calibration: bus_calibration
port map
(
- clk => clk_cpu,
+ clk => clk_100m,
reset => reset,
ce => calib_ce,
address => address(1 downto 0),
data_out => calib_out
);
+ -- Filters
+ bls_f <= bls when bls = bls_d else "1111";
+ rd_f <= rd when rd = rd_d else '1';
+
-- Bus update
- memory_bus_update: process(clk_cpu)
+ memory_bus_update: process(clk_100m)
begin
- if clk_cpu = '1' and clk_cpu'event then
+ if clk_100m = '1' and clk_100m'event then
-- Set every signal to inactive state here
irc_reg_ce <= '1';
- bram_ce <= '1';
- bcd_ce <= '1';
+ tumbl_ce <= '1';
calib_ce <= '1';
i_rd <= '1';
i_bls <= (others => '1');
-- Memory Map (16-bit address @ 32-bit each)
-- Each address is seen as 32-bit entry now
- -- 0x0000 - 0x011F: Control dual-port BRAM
+ -- 0x0000 - 0x0FFF: Tumbl
-- 0x8000 - 0x800F: IRC registers
- -- 0xFFFB: 32-bit BCD
-- 0xFFFC - 0xFFFF: Calibration
- if address < "0000000100100000" then -- Control BRAM
- bram_ce <= '0';
- i_ta <= bram_ta;
- data_out_bus <= bram_out;
+ if address < "0001000000000000" then -- Tumbl
+ tumbl_ce <= '0';
+ i_ta <= tumbl_ta;
+ data_out_bus <= tumbl_out;
elsif address(15 downto 4) = "100000000000" then -- IRC
irc_reg_ce <= '0';
i_ta <= irc_reg_ta;
data_out_bus <= irc_reg_out;
- elsif address = "1111111111111011" then -- BCD
- bcd_ce <= '0';
- i_ta <= bcd_ta;
- data_out_bus <= bcd_out;
elsif address(15 downto 2) = "11111111111111" then -- Calibration
calib_ce <= '0';
i_ta <= calib_ta;
end if;
-- Reading
- if rd = '0' then
+ if rd_f = '0' then
if last_rd = '1' or last_address /= address then
-- Getting something new
-- Set internal RD to active and reset ack and latched data
data_read <= (others => 'X');
end if;
- last_rd <= rd;
+ last_rd <= rd_f;
- -- Writing
- if bls /= "1111" then
- if last_bls /= bls or last_address /= address then
- -- Data are valid when BLS is active, broadcast it for one cycle
- i_bls <= bls;
+ -- Writing (BLS is filtered due to bus error otherwise)
+ if bls_f /= "1111" then
+
+ if last_bls /= bls_f or last_address /= address then
+ -- Broadcast BLS for once cycle to write the data
+ i_bls <= bls_f;
data_in_bus <= data_write;
end if;
last_address <= address;
end if;
- last_bls <= bls;
+ last_bls <= bls_f;
else
end if;
+ -- Filters
+ bls_d <= bls;
+ rd_d <= rd;
+
end if;
end process;
end process;
-- Reset
- initialization: process(init)
+ initialization: process(init, clk_100m_locked)
begin
- reset <= not init;
+ neg_init <= not init;
+ reset <= (not init) or (not clk_100m_locked);
end process;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
+use work.lx_rocon_pkg.all;
-- Quadcounter (for IRC)
clk : in std_logic;
reset : in std_logic;
a0, b0 : in std_logic;
+ index0 : in std_logic;
qcount : out std_logic_vector (31 downto 0);
+ qcount_index : out std_logic_vector (31 downto 0);
a_rise, a_fall, b_rise, b_fall, ab_event: out std_logic;
ab_error : out std_logic
);
end qcounter;
architecture behavioral of qcounter is
- component dff
- port
- (
- clk : in std_logic;
- reset : in std_logic;
- d : in std_logic;
- q : out std_logic
- );
- end component;
-subtype std_logic4 is std_logic_vector (3 downto 0);
signal last_reset: std_logic;
signal a, b, a_prev, b_prev: std_logic;
+ signal index: std_logic;
signal count_prev: std_logic_vector (29 downto 0);
signal count: std_logic_vector (29 downto 0);
+ signal count_index_prev: std_logic_vector (31 downto 0);
+ signal count_index: std_logic_vector (31 downto 0);
+
begin
- dff_a: dff
+ dff_a: dff2
port map
(
clk => clk,
q => a
);
- dff_b: dff
+ dff_b: dff2
port map
(
clk => clk,
q => b
);
+ dff_index: dff2
+ port map
+ (
+ clk => clk,
+ reset => '0',
+ d => index0,
+ q => index
+ );
+
qcount(0) <= a xor b;
qcount(1) <= b;
qcount(31 downto 2) <= count;
+ qcount_index <= count_index;
+
comb_event: process (reset, last_reset, a_prev, b_prev, a, b)
begin
a_rise <= '0';
end if;
end process;
- comb_count: process (reset, last_reset, a_prev, b_prev, a, b, count_prev)
+ comb_count: process (reset, last_reset, a_prev, b_prev, a, b, index, count_prev, count_index_prev)
begin
if reset = '1' or last_reset = '1' then
count <= count_prev;
+ count_index <= count_index_prev;
+
elsif (a_prev = '0') and (b_prev = '1') and (a = '0') and (b = '0') then
count <= count_prev + 1;
+
+ if index = '1' then
+ count_index(0) <= a xor b;
+ count_index(1) <= b;
+ count_index(31 downto 2) <= count_prev + 1;
+ else
+ count_index <= count_index_prev;
+ end if;
+
elsif (a_prev = '0') and (b_prev = '0') and (a = '0') and (b = '1') then
count <= count_prev - 1;
+
+ if index = '1' then
+ count_index(0) <= a xor b;
+ count_index(1) <= b;
+ count_index(31 downto 2) <= count_prev - 1;
+ else
+ count_index <= count_index_prev;
+ end if;
+
else
count <= count_prev;
+
+ if index = '1' then
+ count_index(0) <= a xor b;
+ count_index(1) <= b;
+ count_index(31 downto 2) <= count_prev;
+ else
+ count_index <= count_index_prev;
+ end if;
+
end if;
+
end process;
seq: process (clk)
if clk = '1' and clk'event then
if reset = '0' then
count_prev <= count;
+ count_index_prev <= count_index;
else
count_prev <= (others => '0');
+ count_index_prev <= (others => '0');
end if;
a_prev <= a;
b_prev <= b;
COMPONENT lx_rocon_top
PORT(
- clk_cpu : IN std_logic;
+ --clk_cpu : IN std_logic;
+ clk_50m : IN std_logic;
cs0_xc : IN std_logic;
rd : IN std_logic;
bls : IN std_logic_vector(3 downto 0);
--Inputs
- signal clk_cpu : std_logic := '0';
+ --signal clk_cpu : std_logic := '0';
+ signal clk_50m : std_logic := '0';
signal cs0_xc : std_logic := '1';
signal rd : std_logic := '1';
signal bls : std_logic_vector(3 downto 0) := (others => '1');
signal data : std_logic_vector(31 downto 0);
-- Clock period definitions
- constant clk_period : time := 20 ns;
+ constant clk_period_cpu : time := 13.8 ns;
+ constant clk_period_50m : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lx_rocon_top PORT MAP (
- clk_cpu => clk_cpu,
+ --clk_cpu => clk_cpu,
+ clk_50m => clk_50m,
cs0_xc => cs0_xc,
rd => rd,
bls => bls,
);
-- Clock process definitions
- clk_process :process
+-- clk_cpu_process :process
+-- begin
+-- clk_cpu <= '0';
+-- wait for clk_period_cpu/2;
+-- clk_cpu <= '1';
+-- wait for clk_period_cpu/2;
+-- end process;
+
+ clk_50m_process :process
begin
- clk_cpu <= '0';
- wait for clk_period/2;
- clk_cpu <= '1';
- wait for clk_period/2;
+ clk_50m <= '0';
+ wait for clk_period_50m/2;
+ clk_50m <= '1';
+ wait for clk_period_50m/2;
end process;
-- Stimulus process
stim_proc: process
begin
- -- hold reset state for 100 ns.
- init <= '0';
- data <= (others => 'Z');
- wait for 100 ns;
- init <= '1';
-
- wait for clk_period*10;
-
- -- insert stimulus here
-
- -- Increment IRC1
- irc1_a <= '1';
- wait for clk_period*2;
-
- irc1_b <= '1';
- wait for clk_period*2;
-
- irc1_a <= '0';
- wait for clk_period*2;
-
- irc1_b <= '0';
- wait for clk_period*2;
-
- irc1_a <= '1';
- wait for clk_period*2;
-
- irc1_b <= '1';
- wait for clk_period*2;
-
- irc1_a <= '0';
- wait for clk_period*2;
-
- -- Read IRC1 value (bus has 72 MHz, but signals are set to stay longer)
- cs0_xc <= '0';
- wait for clk_period;
-
- address <= "1000000000000000";
- wait for clk_period;
-
- rd <= '0';
- wait for 5*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- rd <= '1';
- wait for clk_period*3;
-
- -- Test BRAM: Write something and then read it back
- cs0_xc <= '0';
- wait for clk_period;
-
- address <= "0000000000011000";
- data <= "10101010101010101010101010101010";
- wait for clk_period;
-
- bls <= "0000";
- wait for 5*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- bls <= "1111";
- wait for clk_period;
-
- -- Now read it back
- cs0_xc <= '0';
- wait for clk_period;
-
- rd <= '0';
- wait for 5*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- rd <= '1';
- wait for clk_period*3;
-
- -- Now try writing to above address but with only some bytes active
- cs0_xc <= '0';
- wait for clk_period;
-
- address <= "0000000000011100";
- data <= "10101010101010101010101010101010";
- wait for clk_period;
-
- bls <= "0011";
- wait for 5*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- bls <= "1111";
- wait for clk_period;
-
- data <= (others => 'Z');
- wait for clk_period;
-
- -- Now read it back
- cs0_xc <= '0';
- wait for clk_period;
-
- rd <= '0';
- wait for 5*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- rd <= '1';
- wait for clk_period;
-
- -- Poke the bcd a few times
- cs0_xc <= '0';
- address <= "1111111111111011";
- wait for clk_period;
-
- rd <= '0';
- wait for 5*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- rd <= '1';
- wait for clk_period*5;
-
- cs0_xc <= '0';
- wait for clk_period;
-
- rd <= '0';
- wait for 5*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- rd <= '1';
- wait for clk_period;
-
- -- Read calibration register
- cs0_xc <= '0';
- address <= "1111111111111100";
- wait for clk_period;
-
- rd <= '0';
- wait for 8*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- rd <= '1';
- wait for clk_period*5;
-
- -- Write & Read calibration register
- cs0_xc <= '0';
- address <= "1111111111111110";
- data <= "10101010101010101010101010101010";
- wait for clk_period;
-
- bls <= "0000";
- wait for 8*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- rd <= '1';
- wait for clk_period*5;
-
- cs0_xc <= '0';
- address <= "1111111111111110";
- data <= (others => 'Z');
- wait for clk_period;
-
- rd <= '0';
- wait for 8*clk_period;
-
- cs0_xc <= '1';
- wait for clk_period;
-
- rd <= '1';
- wait for clk_period*5;
+ -- External ModelSim script
wait;
end process;
--- /dev/null
+../submodule/tumbl/hw
\ No newline at end of file
--- /dev/null
+-- Xilinx dualport BRAM template, write-first mode, no delay
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.lx_rocon_pkg.all;
+
+entity xilinx_dualport_bram is
+ generic
+ (
+ -- Not all combinations are plausible for BRAMs
+ -- byte width: 8, 9, 32, 36
+ -- we_width: 1, 2, 3, 4
+ byte_width : positive := 8;
+ address_width : positive := 8;
+ we_width : positive := 4
+ );
+ port
+ (
+ clka : in std_logic;
+ rsta : in std_logic;
+ ena : in std_logic;
+ wea : in std_logic_vector((we_width-1) downto 0);
+ addra : in std_logic_vector((address_width-1) downto 0);
+ dina : in std_logic_vector(((byte_width*we_width)-1) downto 0);
+ douta : out std_logic_vector(((byte_width*we_width)-1) downto 0);
+ clkb : in std_logic;
+ rstb : in std_logic;
+ enb : in std_logic;
+ web : in std_logic_vector((we_width-1) downto 0);
+ addrb : in std_logic_vector((address_width-1) downto 0);
+ dinb : in std_logic_vector(((byte_width*we_width)-1) downto 0);
+ doutb : out std_logic_vector(((byte_width*we_width)-1) downto 0)
+ );
+end xilinx_dualport_bram;
+
+architecture Behavioral of xilinx_dualport_bram is
+ type ram is array (0 to ((2**address_width) - 1)) of std_logic_vector(((byte_width*we_width)-1) downto 0);
+ shared variable ram_block : ram := (others => (others => '0'));
+
+begin
+
+ -- CLKA process
+ ram_process_a : process(clka)
+ begin
+
+ if clka = '1' and clka'event then
+
+ if ena = '1' then
+
+ for i in 0 to (we_width-1) loop
+ if wea(i) = '1' then
+ ram_block(to_integer(unsigned(addra)))(((i+1)*byte_width-1) downto (i*byte_width))
+ := dina(((i+1)*byte_width-1) downto (i*byte_width));
+ end if;
+ end loop;
+
+ if rsta = '1' then
+ douta <= (others => '0');
+ else
+ douta <= ram_block(to_integer(unsigned(addra)));
+ end if;
+
+ end if;
+
+ end if;
+
+ end process;
+
+ -- CLKB process
+ ram_process_b : process(clkb)
+ begin
+
+ if clkb = '1' and clkb'event then
+
+ if enb = '1' then
+
+ for i in 0 to (we_width-1) loop
+ if web(i) = '1' then
+ ram_block(to_integer(unsigned(addrb)))(((i+1)*byte_width-1) downto (i*byte_width))
+ := dinb(((i+1)*byte_width-1) downto (i*byte_width));
+ end if;
+ end loop;
+
+ if rstb = '1' then
+ doutb <= (others => '0');
+ else
+ doutb <= ram_block(to_integer(unsigned(addrb)));
+ end if;
+
+ end if;
+
+ end if;
+
+ end process;
+
+end Behavioral;
--- /dev/null
+Subproject commit 342b65f43eca19d8169829aa8d342d1424c6d323
projects / fpga / lx-cpu1 / lx-rocon.git / commitdiff