hw/dff2.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6
   7 -- D circuit (filtered)
   8
   9 entity dff2 is
  10   port
  11         (
  12     clk   : in std_logic;
  13                 reset : in std_logic;
  14     d     : in std_logic;
  15     q     : out std_logic
  16   );
  17 end dff2;
  18
  19 architecture behavioral of dff2 is
  20         signal last_d : std_logic;
  21   signal data: std_logic;
  22 begin
  23   q <= data;
  24
  25   seq: process(clk)
  26   begin
  27     if clk = '1' and clk'event then
  28                         if reset = '1' then
  29                                 last_d <= '0';
  30                                 data <= '0';
  31                         else
  32                                 if d = last_d then
  33                                         data <= d;
  34                                 end if;
  35                         end if;
  36
  37                         last_d <= d;
  38                 end if;
  39   end process;
  40
  41 end behavioral;