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25 -- (c) Copyright 1995-2013 Xilinx, Inc. --
26 -- All rights reserved. --
27 --------------------------------------------------------------------------------
28 --------------------------------------------------------------------------------
29 -- You must compile the wrapper file control_bram.vhd when simulating
30 -- the core, control_bram. When compiling the wrapper file, be sure to
31 -- reference the XilinxCoreLib VHDL simulation library. For detailed
32 -- instructions, please refer to the "CORE Generator Help".
34 -- The synthesis directives "translate_off/translate_on" specified
35 -- below are supported by Xilinx, Mentor Graphics and Synplicity
36 -- synthesis tools. Ensure they are correct for your synthesis tool(s).
39 USE ieee.std_logic_1164.ALL;
40 -- synthesis translate_off
41 LIBRARY XilinxCoreLib;
42 -- synthesis translate_on
43 ENTITY control_bram IS
47 wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
48 addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
49 dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
54 addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
55 dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
60 ARCHITECTURE control_bram_a OF control_bram IS
61 -- synthesis translate_off
62 COMPONENT wrapped_control_bram
66 wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
67 addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
68 dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
73 addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
74 dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
79 -- Configuration specification
80 FOR ALL : wrapped_control_bram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
86 c_axi_slave_type => 0,
90 c_default_data => "0",
91 c_disable_warn_bhv_coll => 0,
92 c_disable_warn_bhv_range => 0,
93 c_enable_32bit_address => 0,
94 c_family => "spartan6",
99 c_has_mem_output_regs_a => 0,
100 c_has_mem_output_regs_b => 0,
101 c_has_mux_output_regs_a => 0,
102 c_has_mux_output_regs_b => 0,
107 c_has_softecc_input_regs_a => 0,
108 c_has_softecc_output_regs_b => 0,
109 c_init_file => "BlankString",
110 c_init_file_name => "no_coe_file_loaded",
113 c_interface_type => 0,
114 c_load_init_file => 0,
116 c_mux_pipeline_stages => 0,
118 c_read_depth_a => 288,
119 c_read_depth_b => 288,
120 c_read_width_a => 32,
121 c_read_width_b => 32,
122 c_rst_priority_a => "CE",
123 c_rst_priority_b => "CE",
124 c_rst_type => "SYNC",
127 c_sim_collision_check => "ALL",
128 c_use_bram_block => 0,
131 c_use_default_data => 1,
136 c_write_depth_a => 288,
137 c_write_depth_b => 288,
138 c_write_mode_a => "WRITE_FIRST",
139 c_write_mode_b => "WRITE_FIRST",
140 c_write_width_a => 32,
141 c_write_width_b => 32,
142 c_xdevicefamily => "spartan6"
144 -- synthesis translate_on
146 -- synthesis translate_off
147 U0 : wrapped_control_bram
162 -- synthesis translate_on