hw/bus_irc.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.std_logic_arith.all;
   4 use ieee.std_logic_unsigned.all;
   5 use ieee.numeric_std.all;
   6 use work.lx_rocon_pkg.all;
   7
   8 -- IRC bus interconnect: memory region for IRC
   9
  10 entity bus_irc is
  11         port
  12         (
  13                 clk         : in std_logic;
  14                 reset       : in std_logic;
  15
  16                 -- Address (needs just last 4 bits, rest is wired to CE)
  17                 address     : in std_logic_vector(3 downto 0);
  18                 ce          : in std_logic;
  19
  20                 -- Data bus
  21                 data_in     : in std_logic; -- 1 bit input
  22                 data_out    : out std_logic_vector(31 downto 0);
  23
  24                 -- Bus signals
  25                 rd          : in std_logic;
  26                 ta          : out std_logic;
  27                 wr          : in std_logic;
  28
  29                 -- Signals for IRC
  30                 irc1_a      : in std_logic;
  31                 irc1_b      : in std_logic;
  32                 irc1_index  : in std_logic;
  33                 irc1_mark   : in std_logic;
  34
  35                 irc2_a      : in std_logic;
  36                 irc2_b      : in std_logic;
  37                 irc2_index  : in std_logic;
  38                 irc2_mark   : in std_logic;
  39
  40                 irc3_a      : in std_logic;
  41                 irc3_b      : in std_logic;
  42                 irc3_index  : in std_logic;
  43                 irc3_mark   : in std_logic;
  44
  45                 irc4_a      : in std_logic;
  46                 irc4_b      : in std_logic;
  47                 irc4_index  : in std_logic;
  48                 irc4_mark   : in std_logic
  49
  50         );
  51 end bus_irc;
  52
  53 architecture Behavioral of bus_irc is
  54
  55         -- Multiplexer signals
  56         signal irc1_out : std_logic_vector(31 downto 0);
  57         signal irc1_ta : std_logic;
  58         signal irc1_ce : std_logic_vector(1 downto 0);
  59
  60         signal irc2_out : std_logic_vector(31 downto 0);
  61         signal irc2_ta : std_logic;
  62         signal irc2_ce : std_logic_vector(1 downto 0);
  63
  64         signal irc3_out : std_logic_vector(31 downto 0);
  65         signal irc3_ta : std_logic;
  66         signal irc3_ce : std_logic_vector(1 downto 0);
  67
  68         signal irc4_out : std_logic_vector(31 downto 0);
  69         signal irc4_ta : std_logic;
  70         signal irc4_ce : std_logic_vector(1 downto 0);
  71
  72 begin
  73
  74         -- IRC for first axis
  75         irc1: irc_register
  76         port map
  77         (
  78                 clk => clk,
  79                 reset => reset,
  80                 a0 => irc1_a,
  81                 b0 => irc1_b,
  82                 index0 => irc1_index,
  83                 mark0 => irc1_mark,
  84                 data_in => data_in,
  85                 data_out => irc1_out,
  86                 ce => irc1_ce,
  87                 rd => rd,
  88                 ta => irc1_ta,
  89                 wr => wr
  90         );
  91
  92         -- IRC for second axis
  93         irc2: irc_register
  94         port map
  95         (
  96                 clk => clk,
  97                 reset => reset,
  98                 a0 => irc2_a,
  99                 b0 => irc2_b,
 100                 index0 => irc2_index,
 101                 mark0 => irc2_mark,
 102                 data_in => data_in,
 103                 data_out => irc2_out,
 104                 ce => irc2_ce,
 105                 rd => rd,
 106                 ta => irc2_ta,
 107                 wr => wr
 108         );
 109
 110         -- IRC for thrid axis
 111         irc3: irc_register
 112         port map
 113         (
 114                 clk => clk,
 115                 reset => reset,
 116                 a0 => irc3_a,
 117                 b0 => irc3_b,
 118                 index0 => irc3_index,
 119                 mark0 => irc3_mark,
 120                 data_in => data_in,
 121                 data_out => irc3_out,
 122                 ce => irc3_ce,
 123                 rd => rd,
 124                 ta => irc3_ta,
 125                 wr => wr
 126         );
 127
 128         -- IRC for fourth axis
 129         irc4: irc_register
 130         port map
 131         (
 132                 clk => clk,
 133                 reset => reset,
 134                 a0 => irc4_a,
 135                 b0 => irc4_b,
 136                 index0 => irc4_index,
 137                 mark0 => irc4_mark,
 138                 data_in => data_in,
 139                 data_out => irc4_out,
 140                 ce => irc4_ce,
 141                 rd => rd,
 142                 ta => irc4_ta,
 143                 wr => wr
 144         );
 145
 146         -- Bus update
 147         memory_bus_update: process(ce, address, irc1_out, irc1_ta, irc2_out, irc2_ta,
 148                                    irc3_out, irc3_ta, irc4_out, irc4_ta)
 149         begin
 150
 151                 -- Reset signals
 152                 irc1_ce <= "11";
 153                 irc2_ce <= "11";
 154                 irc3_ce <= "11";
 155                 irc4_ce <= "11";
 156
 157                 ta <= '1';
 158                 data_out <= (others => 'X');
 159
 160                 if ce = '0' then
 161
 162                         -- We have 4-bit address, and IRC module has 3 registers
 163                         -- Higher bits choose which IRC module, lower bits are for registers of the module
 164                         case address(3 downto 2) is
 165                                 when "00" =>
 166                                         irc1_ce <= address(1 downto 0);
 167                                         data_out <= irc1_out;
 168                                         ta <= irc1_ta;
 169
 170                                 when "01" =>
 171                                         irc2_ce <= address(1 downto 0);
 172                                         data_out <= irc2_out;
 173                                         ta <= irc2_ta;
 174
 175                                 when "10" =>
 176                                         irc3_ce <= address(1 downto 0);
 177                                         data_out <= irc3_out;
 178                                         ta <= irc3_ta;
 179
 180                                 when "11" =>
 181                                         irc4_ce <= address(1 downto 0);
 182                                         data_out <= irc4_out;
 183                                         ta <= irc4_ta;
 184
 185                                 when others => NULL;
 186
 187                         end case;
 188
 189                 end if;
 190
 191         end process;
 192
 193 end Behavioral;
 194