]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/lx-dad.git/shortlog
fpga/lx-cpu1/lx-dad.git
2015-02-15 Pavel PisaInclude testbed for simulation in GHDL.
2015-02-15 Pavel PisaDisable use of unisim library to allow simulation by...
2015-02-15 Pavel PisaInclude example of mapping dualported RAM mapping to...
2015-02-15 Pavel PisaInclude hardware design of FPGA peripherals to external...
2015-02-13 Pavel PisaSwitch LX_DAD default link variant to SDRAM.
2015-02-12 Pavel PisaInclude host tool to send code and FPGA configuration...
2015-02-12 Pavel PisaPrepare build-able skeleton for LX_DAD application.
2015-02-12 Pavel PisaLX_DAD project started.