--- /dev/null
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+<templateProperties value="id=com.ti.common.project.core.emptyProjectTemplate,"/>
+</projectOptions>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+ <externalSettings/>
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+ <extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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--- /dev/null
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--- /dev/null
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--- /dev/null
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--- /dev/null
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+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/source/subdir_rules.mk=UTF-8
+encoding//Debug/source/subdir_vars.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
--- /dev/null
+# TMS570LS3137ZWT 07/31/12 11:20:55\r
+# \r
+ARCH=TMS570LS3137ZWT\r
+# \r
+DRIVER.TOOLS.VAR.ARM.VALUE=0\r
+DRIVER.TOOLS.VAR.IAR.VALUE=0\r
+DRIVER.TOOLS.VAR.TI.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DIVIDER.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE.VALUE=NORMAL_OINC_NONSHARED\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION_VALUE.VALUE=0x0300\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_NAME.VALUE=het2LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_NAME.VALUE=adc2Group2Interrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_NAME.VALUE=spi4HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_MAPPING.VALUE=2\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MEMINIT_SELECTED.VALUE=1\r
+DRIVER.SYSTEM.VAR.FLASH_DATA_3_WAIT_STATE_FREQ.VALUE=200.0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_MAPPING.VALUE=96\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_MAPPING.VALUE=88\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0xFCFFFFFF\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_SELFCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_BYPASS_ON_SLIP.VALUE=0x20000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE_VALUE.VALUE=0x0008\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=256_KB\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_RAMPARITYCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=160.000\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=160.00\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_MAPPING.VALUE=65\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_MAPPING.VALUE=57\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_MAPPING.VALUE=49\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_NAME.VALUE=het1LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CCM_SELFCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE_VALUE.VALUE=0x0008\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_OUTPUT_DIV.VALUE=2\r
+DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x63FFFFFF\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_DP_PBISTCHECK_ENA.VALUE=0x00040000\r
+DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_MAPPING.VALUE=50\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_MAPPING.VALUE=42\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_MAPPING.VALUE=34\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_MAPPING.VALUE=26\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18\r
+DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=_isrStub\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0600\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_MAPPING.VALUE=11\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC\r
+DRIVER.SYSTEM.VAR.LBIST_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OINC_NONSHARED\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x003FFFFF\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=100.0\r
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08001200\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_NAME.VALUE=dcc1DoneInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_NAME.VALUE=sciLowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_NAME.VALUE=i2cInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_PMU_GLOBAL_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0xFF000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_DP_SELECTED.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=vPreemptiveTick\r
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER0_EVENT.VALUE=0x11\r
+DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENTRY.VALUE=_c_int00\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x0A\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_MAPPING.VALUE=102\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER.VALUE=1\r
+DRIVER.SYSTEM.VAR.RAM_LENGTH.VALUE=0x00040000\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=64_MB\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=spi2HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x203FFFFF\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_DP_PBISTCHECK_ENA.VALUE=0x00008000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE_VALUE.VALUE=0x0000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_MAPPING.VALUE=95\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_MAPPING.VALUE=87\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_MAPPING.VALUE=79\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_DP_PBISTCHECK_ENA.VALUE=0x00000040\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1\r
+DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_RAMPARITYCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.SCI_ALL_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0\r
+DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=24\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16\r
+DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=160.000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x1000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_MAPPING.VALUE=64\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_MAPPING.VALUE=56\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_MAPPING.VALUE=48\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_REF_CLOCK_DIV.VALUE=6\r
+DRIVER.SYSTEM.VAR.FLASHW_BASE_ADDRESS.VALUE=0xFFF87000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_FIQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]"\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_DP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001\r
+DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE.VALUE=NORMAL_OINC_NONSHARED\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_FREQ.VALUE=16.0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_NAME.VALUE=dcc2DoneInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_MAPPING.VALUE=41\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_MAPPING.VALUE=33\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_MAPPING.VALUE=25\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0008\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=2\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_FM_ENABLE.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0x08400000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_CPUSELFTEST_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.HET1_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_RTI1_PRE_SOURCE.VALUE=PLL1\r
+DRIVER.SYSTEM.VAR.FLASH_MODE_VALUE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE_VALUE.VALUE=0x19\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_MAPPING.VALUE=10\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE.VALUE=128_MB\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_DP_PBISTCHECK_ENA.VALUE=0x00001000\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_MAPPING.VALUE=124\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_MAPPING.VALUE=116\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_MAPPING.VALUE=108\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_NAME.VALUE=adc2Group0Interrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_NAME.VALUE=can2LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_NAME.VALUE=mibspi1LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC\r
+DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100\r
+DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3\r
+DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_RAMPARITYCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_SP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_MAPPING.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_DIV.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.RAM_BASE_ADDRESS.VALUE=0x08000000\r
+DRIVER.SYSTEM.VAR.CORE_PMU_EVENT_EXPORT_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x17\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_MAPPING.VALUE=94\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_MAPPING.VALUE=86\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_MAPPING.VALUE=78\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE.VALUE=STRONGLYORDERED_SHAREABLE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0\r
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08001300\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EFUSE_SELFCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_GHV_WAKUP_SOURCE.VALUE=PLL1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE_VALUE.VALUE=0x0000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_MAPPING.VALUE=71\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_MAPPING.VALUE=63\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_MAPPING.VALUE=55\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_MAPPING.VALUE=47\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_MAPPING.VALUE=39\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11\r
+DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08001500\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DIVIDER.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE.VALUE=8_MB\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK\r
+DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=100.0\r
+DRIVER.SYSTEM.VAR.RAM_STACK_BASE.VALUE=0x08000000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_NAME.VALUE=adc2Group1Interrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_MAPPING.VALUE=40\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_NAME.VALUE=can2HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_MAPPING.VALUE=32\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_NAME.VALUE=linLowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_MAPPING.VALUE=24\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_NAME.VALUE=crcInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xF07FFFFF\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_DP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.LBIST_STT.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE_VALUE.VALUE=0x0010\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_MAPPING.VALUE=123\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_MAPPING.VALUE=115\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_MAPPING.VALUE=107\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00001000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0x0843FFFF\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_SP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SELFCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x11\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x08001000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=STRONGLYORDERED_SHAREABLE\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_DP_PBISTCHECK_ENA.VALUE=0x00000100\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=10.000\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00001500\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0xFFFFFFFF\r
+DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=PLL2_ODCLK_8\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=80.0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_MAPPING.VALUE=69\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ2.VALUE=80.0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE.VALUE=16_MB\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_BASE_ADDRESS.VALUE=0xFC000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_2_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=120\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_NAME.VALUE=adc1Group2Interrupt\r
+DRIVER.SYSTEM.VAR.CLKT_OSC_ENABLE.VALUE=TRUE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE.VALUE=16_MB\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_MAPPING.VALUE=70\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_MAPPING.VALUE=62\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_MAPPING.VALUE=54\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_MAPPING.VALUE=46\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_MAPPING.VALUE=38\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_SOURCE_ENABLE.VALUE=0x00000080\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_DP_PBISTCHECK_ENA.VALUE=0x00080000\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_DP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1\r
+DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x00026B00\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x080017FF\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0008\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_MAPPING.VALUE=31\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_MAPPING.VALUE=23\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_MAPPING.VALUE=15\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_5_6.VALUE=0\r
+DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=120\r
+DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE.VALUE=NORMAL_OINC_NONSHARED\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENTRY.VALUE=_prefetch\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK2_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION_VALUE.VALUE=0x1300\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION_VALUE.VALUE=0x1300\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_SOURCE_ENABLE.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_BASE_ADDRESS.VALUE=0x60000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_7_8.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_0.VALUE=0x00000020\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_1.VALUE=0x00180000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE_VALUE.VALUE=0x08\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_MAPPING.VALUE=122\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_MAPPING.VALUE=114\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_MAPPING.VALUE=106\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER2_EVENT.VALUE=0x11\r
+DRIVER.SYSTEM.VAR.FLASH_DATA_WAIT_STATES.VALUE=3\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_6_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=150.0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5\r
+DRIVER.SYSTEM.VAR.VIM_PARITY_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.VIM_CHANNELS.VALUE=96\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_7.VALUE=0xF0200000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE.VALUE=512_BYTES\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_7_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_DP_PBISTCHECK_ENA.VALUE=0x00000010\r
+DRIVER.SYSTEM.VAR.ESM_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_MAPPING.VALUE=99\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_NAME.VALUE=mibspi5HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_NAME.VALUE=can3HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_NAME.VALUE=mibspi3HighInterruptLevel\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_NAME.VALUE=can1LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=2_KB\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_FREQ.VALUE=10.000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE_VALUE.VALUE=0x11\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]"\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=PLL1\r
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_MAPPING.VALUE=92\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_MAPPING.VALUE=84\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_MAPPING.VALUE=76\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_MAPPING.VALUE=68\r
+DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_DP_PBISTCHECK_ENA.VALUE=0x00020000\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_DP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_DP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.SYSTEM_INIT.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_NAME.VALUE=esmLowInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_NAME.VALUE=mibspi1HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION.VALUE=PRIV_NA_USER_NA_NOEXEC\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_BASE_ADDRESS.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_TYPE.VALUE=FIQ\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION_VALUE.VALUE=0x1100\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION_VALUE.VALUE=0x1200\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_MAPPING.VALUE=61\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_MAPPING.VALUE=53\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_MAPPING.VALUE=45\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_MAPPING.VALUE=37\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29\r
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1\r
+DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00200000\r
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100\r
+DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0010\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK1_DIVIDER.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE.VALUE=DEVICE_NONSHAREABLE\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0\r
+DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=50.0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_MAPPING.VALUE=30\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_MAPPING.VALUE=22\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_MAPPING.VALUE=14\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_2.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_RTI1_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_ESRAM_SELECTED.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=80.0\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0xFE0001FF\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00002000\r
+DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x0008\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_NAME.VALUE=spi4LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_NAME.VALUE=mibspi3LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.FEE_FLASH_ECC_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE.VALUE=4_MB\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87FFFFFF\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_GB\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION_VALUE.VALUE=0x1300\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE_VALUE.VALUE=0x17\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION_VALUE.VALUE=0x0300\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_MAPPING.VALUE=98\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_NAME.VALUE=linHighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_FUN.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_BASE_ADDRESS.VALUE=0x20000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_7_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_RAMPARITYCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000800\r
+DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0\r
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08001400\r
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08001000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=80.000\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_MAPPING.VALUE=83\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_MAPPING.VALUE=75\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_MAPPING.VALUE=67\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_MAPPING.VALUE=59\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_2.VALUE=SLEEP\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OINC_NONSHARED\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803FFFF\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_DP_PBISTCHECK_ENA.VALUE=0x00000008\r
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_4.VALUE=SLEEP\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_5.VALUE=SLEEP\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE_VALUE.VALUE=0x15\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.ECLK_PRESCALER.VALUE=8\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_6.VALUE=SLEEP\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0xFE000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=80.0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_MAPPING.VALUE=36\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_MAPPING.VALUE=28\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_BAND_WIDTH_ADJUSTMENT.VALUE=7\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_SOURCE_ENABLE.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_6_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_DP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CLKT_RTI1_POST_SOURCE.VALUE=VCLK\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_NAME.VALUE=het2HighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_NAME.VALUE=can3LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_DP_PBISTCHECK_ENA.VALUE=0x00000400\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_DP_PBISTCHECK_ENA.VALUE=0x00000080\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_MAPPING.VALUE=13\r
+DRIVER.SYSTEM.VAR.CLKT_PLL2_REF_CLOCK_DIV.VALUE=6\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_RATE.VALUE=255\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_RAMPARITYCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_SLIP.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE_VALUE.VALUE=0x0010\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION_VALUE.VALUE=0x0300\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_MAPPING.VALUE=127\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_MAPPING.VALUE=119\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION.VALUE=PRIV_RW_USER_NA_NOEXEC\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_FM_ENABLE.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_6_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE.VALUE=4_MB\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_NAME.VALUE=spi2LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_NAME.VALUE=adc1Group0Interrupt\r
+DRIVER.SYSTEM.VAR.CLKT_LPOLO_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0xFFFFFFFF\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=vPortYieldProcessor\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_RAMPARITYCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FLASHECC_SELFCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0008\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_MAPPING.VALUE=3\r
+DRIVER.SYSTEM.VAR.CLKT_LPOHI_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE.VALUE=NORMAL_OINC_NONSHARED\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RTP_DP_PBISTCHECK_ENA.VALUE=0x00004000\r
+DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIV_FREQ.VALUE=80.0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_MAPPING.VALUE=97\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_MAPPING.VALUE=89\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_NAME.VALUE=gioHighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_ENABLE.VALUE=TRUE\r
+DRIVER.SYSTEM.VAR.FLASH_BASE_ADDRESS.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_6_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_ENA.VALUE=0x08300020\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OINC_NONSHARED\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_DP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x0017FFE0\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00180000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_MAPPING.VALUE=90\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_MAPPING.VALUE=82\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_MAPPING.VALUE=74\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_MAPPING.VALUE=66\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_NAME.VALUE=sciHighLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_MAPPING.VALUE=58\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_NAME.VALUE=mibspi5LowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_7_DISABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_1_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00\r
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08001100\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt\r
+DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM_VALUE.VALUE=8\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_MAPPING.VALUE=51\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_MAPPING.VALUE=43\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_MAPPING.VALUE=35\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_MAPPING.VALUE=27\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_MAPPING.VALUE=19\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC\r
+DRIVER.SYSTEM.VAR.CCM_MENU.VALUE=NONE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=256_KB\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_RAMPARITYCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=160.00\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x1F\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt\r
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100\r
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_DP_PBISTCHECK_ENA.VALUE=0x00000004\r
+DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_SP_PBISTCHECK_ENA.VALUE=0x00010000\r
+DRIVER.SYSTEM.VAR.OS_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE_VALUE.VALUE=0x15\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_MAPPING.VALUE=126\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_MAPPING.VALUE=118\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_NAME.VALUE=phantomInterrupt\r
+DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.SYSTEM.VAR.ECLK_SUSPEND.VALUE=0\r
+DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_AMOUNT.VALUE=61\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_5_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.CORE_VFP_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_DP_PBISTCHECK_ENA.VALUE=0x00000200\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_FMCBUS2_SELFCHECK_ENA.VALUE=1\r
+DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.ECLK_OSCILLATOR_FREQ.VALUE=16.000\r
+DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM.VALUE=100.00\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9\r
+DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_ENABLE.VALUE=FALSE\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_0_DISABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=1\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_ENABLE.VALUE=0\r
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_TYPE.VALUE=IRQ\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM2_RAMPARITYCHECK_ENA.VALUE=0\r
+DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_DP_PBISTCHECK_ENA.VALUE=0x00000000\r
+DRIVER.SYSTEM.VAR.CLKT_CRYSTAL_FREQ.VALUE=16.0\r
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE_VALUE.VALUE=0x0008\r
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+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_BASE_PORTA.VALUE=0xFFF7BC34\r
+DRIVER.GIO.VAR.GIO_BASE_PORTB.VALUE=0xFFF7BC54\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_BASE.VALUE=0xFFF7BC00\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT4_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORTB_ENABLE.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT3_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT7_PULL.VALUE=1\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT5_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT4_DIR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULDIS.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_DOUT.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT6_PSL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_PDR.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_LVL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT5_ENA.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT1_BIT7_POL.VALUE=0\r
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_PSL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_TIMMINGMODE.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DIR.VALUE=0\r
+DRIVER.SCI.VAR.SCI_TIMMINGMODE.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_WAKEINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PEINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PULL.VALUE=2\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DIR.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT0_DIR.VALUE=0\r
+DRIVER.SCI.VAR.SCI_ACTUALBAUDRATE.VALUE=9597\r
+DRIVER.SCI.VAR.SCI_EVENPARITY.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_FUN.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DIR.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_RXINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT1_DIR.VALUE=0\r
+DRIVER.SCI.VAR.SCI_BASE_PORT.VALUE=0xFFF7E540\r
+DRIVER.SCI.VAR.SCILIN_PRESCALE.VALUE=520\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_FUN.VALUE=1\r
+DRIVER.SCI.VAR.SCI_PORT_BIT0_FUN.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT2_DIR.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PDR.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_FUN.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_PEINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT1_FUN.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.SCI.VAR.SCI_OEINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PDR.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PDR.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT2_FUN.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PSL.VALUE=1\r
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PDR.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PSL.VALUE=1\r
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PSL.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_BREAKINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCI_WAKEINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCI_BREAKINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PSL.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULDIS.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PULDIS.VALUE=0\r
+DRIVER.SCI.VAR.SCI_FEINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.SCI.VAR.SCI_OEINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCI_TXINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PARITYENA.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DOUT.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.SCI.VAR.SCI_BAUDRATE.VALUE=9600\r
+DRIVER.SCI.VAR.SCILIN_BREAKINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCI_WAKEINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.SCI.VAR.SCI_BREAKINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCI_STOPBITS.VALUE=2\r
+DRIVER.SCI.VAR.SCI_RXINTENA.VALUE=1\r
+DRIVER.SCI.VAR.SCI_FEINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_EVENPARITY.VALUE=0\r
+DRIVER.SCI.VAR.SCI_TXINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_OEINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DOUT.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT1_DOUT.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PEINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCI_CLKMODE.VALUE=1\r
+DRIVER.SCI.VAR.SCI_PARITYENA.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.SCI.VAR.SCI_PORT_BIT2_DOUT.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_BASE.VALUE=0xFFF7E400\r
+DRIVER.SCI.VAR.SCI_RXINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_FEINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PRESCALE.VALUE=520\r
+DRIVER.SCI.VAR.SCILIN_OEINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_TXINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT2_PULDIS.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULL.VALUE=2\r
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.SCI.VAR.SCI_PEINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_WAKEINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCI_LENGTH.VALUE=8\r
+DRIVER.SCI.VAR.SCILIN_CLKMODE.VALUE=1\r
+DRIVER.SCI.VAR.SCILIN_BASE_PORT.VALUE=0xFFF7E440\r
+DRIVER.SCI.VAR.SCILIN_BAUDRATE.VALUE=9600\r
+DRIVER.SCI.VAR.SCILIN_STOPBITS.VALUE=2\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULL.VALUE=2\r
+DRIVER.SCI.VAR.SCI_PORT_BIT1_PULL.VALUE=2\r
+DRIVER.SCI.VAR.SCILIN_RXINTENA.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_LENGTH.VALUE=8\r
+DRIVER.SCI.VAR.SCILIN_FEINTLVL.VALUE=0\r
+DRIVER.SCI.VAR.SCILIN_ACTUALBAUDRATE.VALUE=9597\r
+DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULDIS.VALUE=0\r
+DRIVER.SCI.VAR.SCI_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.SCI.VAR.SCI_BASE.VALUE=0xFFF7E500\r
+DRIVER.SCI.VAR.SCILIN_TXINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BITERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_CLKMOD.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PHASE3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSNR.VALUE=CS_2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=25.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_LENGTH.VALUE=8\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE3.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSNR.VALUE=CS_1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=12.500\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE.VALUE=0xFFF7FC00\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSNR.VALUE=CS_5\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE0.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE1.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BITERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=12.500\r
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_ENABLEHIGHZ.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSNR.VALUE=CS_4\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_RXINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI5_RXINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSNR.VALUE=CS_1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE0.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSNR.VALUE=CS_7\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE1.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE2.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TXINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE3.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BITERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSNR.VALUE=CS_0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_LENGTH.VALUE=8\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_BASE_RAM.VALUE=0xFF0A0000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN0.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN1.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSNR.VALUE=CS_4\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_RXINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=25.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE0.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5\r
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BITERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSNR.VALUE=CS_7\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE_RAM.VALUE=0xFF0E0000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN0.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN1.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN2.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE_PORT.VALUE=0xFFF7F418\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSNR.VALUE=CS_0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PARERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=12.500\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE0.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE1.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE2.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE3.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_BASE.VALUE=0xFFF7F400\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI3_RXINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PHASE3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_ENABLE.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_MASTER.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG4_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSNR.VALUE=CS_2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSNR.VALUE=CS_6\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG6_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_RXINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSNR.VALUE=CS_5\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE.VALUE=0xFFF7F800\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_MASTER.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG0_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG2_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_LOCK.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=25.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTLVL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_MODE.VALUE=4\r
+DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAY.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGEVT.VALUE=TRG_ALWAYS\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TXINTENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULDIS.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_WDEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=79\r
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0\r
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16\r
+DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGSRC.VALUE=TRG_DISABLED\r
+DRIVER.SPI.VAR.SPI2_TIMEOUTLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=12.500\r
+DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_POLARITY3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618\r
+DRIVER.SPI.VAR.SPI4_OVRNINTENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_WAITENA1.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_WAITENA2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI4_WAITENA3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI2_PARERRLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PARITYENA0.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_ENABLEHIGHZ.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARITYENA1.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARITYENA2.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_DLENERRLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_RXINTLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARITYENA3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_BAUDRATE0.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_BAUDRATE1.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_BAUDRATE2.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_BAUDRATE3.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_RAM_PARITY_ENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_POLARITY0.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_POLARITY1.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_POLARITY2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_POLARITY3.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_T2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.SPI.VAR.SPI4_T2CDELAY.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF0E0000\r
+DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16\r
+DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16\r
+DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16\r
+DRIVER.SPI.VAR.SPI4_SHIFTDIR0.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_OVRNINTLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_SHIFTDIR1.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_SHIFTDIR2.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_SHIFTDIR3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_DLENERRENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_WDELAY0.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_WDELAY1.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_WDELAY2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_BASE.VALUE=0xFFF7F600\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_C2TDELAY.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=25.000\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARPOL0.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARPOL1.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARPOL2.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARPOL3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_OVRNINTENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PHASE0.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_T2EDELAY.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PHASE1.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI4_PHASE2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_SHIFTDIR0.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PHASE3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_SHIFTDIR1.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_SHIFTDIR2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI4_C2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=79\r
+DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=79\r
+DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=79\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=79\r
+DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PARITYENA0.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PARITYENA1.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI2_PARITYENA2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_DLENERRLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_MASTER.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PARITYENA3.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=12.500\r
+DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_CLKMOD.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PHASE0.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PHASE1.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI2_PHASE2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_TXINTLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PHASE3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT3_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI2_OVRNINTLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_DEYSNCENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_WDELAY0.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_WDELAY1.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=79\r
+DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=79\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=79\r
+DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=79\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_TIMEOUTLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_BITERRENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_T2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_WAITENA0.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_WAITENA1.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_WAITENA2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_WAITENA3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PARPOL0.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PARPOL1.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PARPOL2.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PARPOL3.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_CLKMOD.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_RXINTLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_RAM_PARITY_ENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_C2EDELAY.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARERRENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_C2TDELAY.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_DEYSNCENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_DEYSNCLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE0.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE1.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_T2CDELAY.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE2.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE3.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI4_TXINTENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_BASE_RAM.VALUE=0xFF0E0000\r
+DRIVER.SPI.VAR.SPI2_CHARLEN0.VALUE=16\r
+DRIVER.SPI.VAR.SPI2_CHARLEN1.VALUE=16\r
+DRIVER.SPI.VAR.SPI2_TIMEOUTENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_CHARLEN2.VALUE=16\r
+DRIVER.SPI.VAR.SPI2_ENABLEHIGHZ.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_CHARLEN3.VALUE=16\r
+DRIVER.SPI.VAR.SPI2_BITERRENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_BITERRLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=25.000\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE0.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE1.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI4_BASE_PORT.VALUE=0xFFF7FA18\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE2.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE3.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PSL.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT1_DOUT.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_DIR.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_PARERRENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PARERRLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT11_DIR.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_DLENERRENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_RXINTENA.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULL.VALUE=2\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_BAUDRATE0.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI4_BAUDRATE1.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI4_BAUDRATE2.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI4_TXINTLVL.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT10_FUN.VALUE=1\r
+DRIVER.SPI.VAR.SPI4_BAUDRATE3.VALUE=1000.000\r
+DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULDIS.VALUE=0\r
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_PDR.VALUE=0\r
+DRIVER.SPI.VAR.SPI2_C2EDELAYACTUAL.VALUE=0.000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_SYNC.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=500\r
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ID.VALUE=30\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ID.VALUE=22\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ID.VALUE=14\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ID.VALUE=9\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_RAMBASE.VALUE=0xFF1C0000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_RATE.VALUE=500.000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=2\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ID.VALUE=31\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ID.VALUE=23\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ID.VALUE=15\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ID.VALUE=40\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DIN.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PSL.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ID.VALUE=41\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ID.VALUE=33\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17\r
+DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=4.000\r
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=3\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_RATE.VALUE=500.000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ID.VALUE=50\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ID.VALUE=42\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ID.VALUE=34\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ID.VALUE=26\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ID.VALUE=18\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_PROPAGATION_DELAY.VALUE=700\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=75.000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ID.VALUE=35\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ID.VALUE=27\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ID.VALUE=19\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ID.VALUE=3\r
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DOUT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_BASE.VALUE=0xFFF7DE00\r
+DRIVER.CAN.VAR.CAN_1_RAMBASE.VALUE=0xFF1E0000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PULL.VALUE=2\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_IDENTIFIER_MODE.VALUE=0x40000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ID.VALUE=60\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ID.VALUE=52\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ID.VALUE=44\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ID.VALUE=36\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ID.VALUE=28\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ID.VALUE=4\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ID.VALUE=61\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ID.VALUE=53\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ID.VALUE=45\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ID.VALUE=37\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ID.VALUE=29\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PULL.VALUE=2\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=500.000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=4.000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DIN.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DIR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_TQ.VALUE=250.000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ID.VALUE=6\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ID.VALUE=63\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ID.VALUE=55\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ID.VALUE=47\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ID.VALUE=39\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_TQ.VALUE=250.000\r
+DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7\r
+DRIVER.CAN.VAR.CAN_3_BASE.VALUE=0xFFF7E000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PULDIS.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ID.VALUE=48\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DOUT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_TQ.VALUE=250.000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ID.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=10\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PSL.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ID.VALUE=57\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ID.VALUE=49\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75\r
+DRIVER.CAN.VAR.CAN_1_PROPAGATION_DELAY.VALUE=700\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ID.VALUE=9\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=11\r
+DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_RX_FUN.VALUE=1\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58\r
+DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PULDIS.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=12\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ID.VALUE=59\r
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PDR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT_REFERENCE.VALUE=75\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=4.000\r
+DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=4.000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=14\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_BAUDRATE.VALUE=500\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=15\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DIN.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=75.000\r
+DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=2\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=16\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DOUT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PULL.VALUE=2\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_BRPE.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MASK.VALUE=0x1FFFFFFF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ID.VALUE=41\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=1\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ID.VALUE=50\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ID.VALUE=42\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ID.VALUE=34\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ID.VALUE=26\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ID.VALUE=18\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_BRP.VALUE=19\r
+DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=3\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ID.VALUE=10\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=2\r
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DIN.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ID.VALUE=51\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ID.VALUE=43\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ID.VALUE=35\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ID.VALUE=27\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=3\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ID.VALUE=60\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ID.VALUE=52\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ID.VALUE=44\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ID.VALUE=36\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ID.VALUE=28\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_BRP.VALUE=19\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ID.VALUE=20\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ID.VALUE=12\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PDR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=4\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000\r
+DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MASK.VALUE=0x1FFFFFFF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ID.VALUE=61\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ID.VALUE=53\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ID.VALUE=45\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ID.VALUE=37\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ID.VALUE=29\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PULL.VALUE=2\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=5\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ID.VALUE=62\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ID.VALUE=54\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ID.VALUE=46\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ID.VALUE=38\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_BRP.VALUE=19\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_IDENTIFIER_MODE.VALUE=0x40000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=2\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=6\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=1\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ID.VALUE=63\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ID.VALUE=55\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ID.VALUE=15\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=7\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PDR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ID.VALUE=64\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ID.VALUE=56\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ID.VALUE=48\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ID.VALUE=16\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_AUTO_RETRANSMISSION.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ID.VALUE=57\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ID.VALUE=49\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_40_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ID.VALUE=17\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=9\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_SJW.VALUE=2\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_BAUDRATE.VALUE=500\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ID.VALUE=26\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ID.VALUE=18\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DIN.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PSL.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ID.VALUE=59\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DIR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ID.VALUE=51\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ID.VALUE=43\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ID.VALUE=35\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ID.VALUE=27\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19\r
+DRIVER.CAN.VAR.CAN_2_SJW.VALUE=2\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=1\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ID.VALUE=60\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ID.VALUE=52\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ID.VALUE=44\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ID.VALUE=36\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ID.VALUE=28\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000\r
+DRIVER.CAN.VAR.CAN_1_SYNC.VALUE=1\r
+DRIVER.CAN.VAR.CAN_3_SHIFT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_PORT_RX_PULDIS.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_62_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_54_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_46_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_38_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=4.000\r
+DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=4.000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=3\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_17_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ID.VALUE=61\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ID.VALUE=53\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ID.VALUE=45\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ID.VALUE=37\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ID.VALUE=29\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_SJW.VALUE=2\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_50_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_42_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_34_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_26_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_18_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=75.000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ID.VALUE=46\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ID.VALUE=38\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ID.VALUE=3\r
+DRIVER.CAN.VAR.CAN_1_PORT_RX_DOUT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ID.VALUE=63\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ID.VALUE=55\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ID.VALUE=47\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ID.VALUE=39\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_RAMBASE.VALUE=0xFF1A0000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DIN.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_59_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PDR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ID.VALUE=4\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_PORT_TX_DOUT.VALUE=0\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ID.VALUE=64\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ID.VALUE=56\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ID.VALUE=48\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_SYNC.VALUE=1\r
+DRIVER.CAN.VAR.CAN_2_PORT_TX_PULL.VALUE=2\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_63_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_55_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_47_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_39_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ID.VALUE=10\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ID.VALUE=5\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_50_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_42_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_34_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_26_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_18_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ID.VALUE=57\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ID.VALUE=49\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_51_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_43_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_35_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_27_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_19_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ID.VALUE=11\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ID.VALUE=6\r
+DRIVER.CAN.VAR.CAN_3_PROPAGATION_DELAY.VALUE=700\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_9_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ID.VALUE=58\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_7_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_PORT_TX_PSL.VALUE=1\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59\r
+DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TR.VALUE=0\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DLC.VALUE=8\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000\r
+DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=1\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ID.VALUE=13\r
+DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8\r
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_PARITY_ENABLE.VALUE=0x00000005\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN17_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC1_GROUP2_RESOLUTION.VALUE=12_BIT\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN7_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN10_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_RAM_PARITY_ENA.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16\r
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16\r
+DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN7_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_ALT_TRIG.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN15_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN0_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_CONVERSION_TIME.VALUE=1.300\r
+DRIVER.ADC.VAR.ADC2_GROUP2_LENGTH.VALUE=32\r
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_BND.VALUE=2\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300\r
+DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT\r
+DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300\r
+DRIVER.ADC.VAR.ADC2_BND.VALUE=2\r
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=100.00\r
+DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_MODE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN5_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN13_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN9_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN19_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.ADC.VAR.ADC2_GROUP1_SCAN_TIME.VALUE=0.000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16\r
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC2_LENGTH.VALUE=64\r
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN21_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8\r
+DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT\r
+DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN14_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC2_GROUP1_BND.VALUE=8\r
+DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN0_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN3_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_ALT_TRIG_COMP.VALUE=1\r
+DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005\r
+DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=100.00\r
+DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000\r
+DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000\r
+DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32\r
+DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8\r
+DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN12_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN8_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PINS.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN1_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_MODE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_FIFO_SIZE.VALUE=16\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00\r
+DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=7\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN2_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_RAM_PARITY_ENA.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN24_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN16_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_ID_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN6_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN9_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300\r
+DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16\r
+DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16\r
+DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16\r
+DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN21_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN13_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00\r
+DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1\r
+DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP1_RAM_PARITY_ENA.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN1_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_RAM_PARITY_ENA.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN4_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_PRESCALER.VALUE=0\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN12_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN8_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN18_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_RESOLUTION.VALUE=12_BIT\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=7\r
+DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0\r
+DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN9_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN20_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN12_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN9_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_TIME.VALUE=200.00\r
+DRIVER.ADC.VAR.ADC2_GROUP1_FIFO_SIZE.VALUE=16\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN2_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000\r
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00\r
+DRIVER.LIN.VAR.LIN_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.LIN.VAR.LIN_PEINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_TOAWUSINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_BEINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_TOA3WUSINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT1_DOUT.VALUE=0\r
+DRIVER.LIN.VAR.LIN_MAXPRESCALE.VALUE=3600\r
+DRIVER.LIN.VAR.LIN_LENGTH.VALUE=8\r
+DRIVER.LIN.VAR.LIN_PARITYENA.VALUE=0\r
+DRIVER.LIN.VAR.LIN_BREAKINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_TX_MASK.VALUE=0xFF\r
+DRIVER.LIN.VAR.LIN_MSTMOD.VALUE=1\r
+DRIVER.LIN.VAR.LIN_SDEL.VALUE=1\r
+DRIVER.LIN.VAR.LIN_PORT_BIT2_DOUT.VALUE=0\r
+DRIVER.LIN.VAR.LIN_TOAWUSINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_WAKEINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_HGENCTRL.VALUE=1\r
+DRIVER.LIN.VAR.LIN_TOA3WUSINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT0_DIR.VALUE=0\r
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.LIN.VAR.LIN_CEINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_BREAKINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PBEINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT1_DIR.VALUE=0\r
+DRIVER.LIN.VAR.LIN_PORT_BIT0_FUN.VALUE=0\r
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PULDIS.VALUE=0\r
+DRIVER.LIN.VAR.LIN_PORT_BIT2_DIR.VALUE=0\r
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PULL.VALUE=2\r
+DRIVER.LIN.VAR.LIN_WAKEINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.LIN.VAR.LIN_OEINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT1_FUN.VALUE=2\r
+DRIVER.LIN.VAR.LIN_NREINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PDR.VALUE=0\r
+DRIVER.LIN.VAR.LIN_PORT_BIT2_FUN.VALUE=4\r
+DRIVER.LIN.VAR.LIN_CEINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PULL.VALUE=2\r
+DRIVER.LIN.VAR.LIN_PBEINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PDR.VALUE=0\r
+DRIVER.LIN.VAR.LIN_BASE_PORT.VALUE=0xFFF7E440\r
+DRIVER.LIN.VAR.LIN_ACTUALBAUDRATE.VALUE=20.000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT1_PSL.VALUE=2\r
+DRIVER.LIN.VAR.LIN_ISFEINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_FEINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PSL.VALUE=4\r
+DRIVER.LIN.VAR.LIN_OEINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_TXINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_NREINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_IDINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_SBREAK.VALUE=13\r
+DRIVER.LIN.VAR.LIN_TOINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_BAUDRATE.VALUE=20.000\r
+DRIVER.LIN.VAR.LIN_RX_MASK.VALUE=0xFF\r
+DRIVER.LIN.VAR.LIN_ISFEINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_RXINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_BASE.VALUE=0xFFF7E400\r
+DRIVER.LIN.VAR.LIN_FEINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_TXINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PORT_BIT2_PULDIS.VALUE=0\r
+DRIVER.LIN.VAR.LIN_IDINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PEINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_TOINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_MAXBAUDRATE.VALUE=22.222\r
+DRIVER.LIN.VAR.LIN_BEINTENA.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_RXINTLVL.VALUE=0x00000000\r
+DRIVER.LIN.VAR.LIN_PRESCALE.VALUE=249\r
+DRIVER.LIN.VAR.LIN_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT6_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X1.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_BIT29_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT0_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM3_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_PWM1_PIN_SELECT.VALUE=10\r
+DRIVER.HET.VAR.HET2_BIT12_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT3_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_INT_X2.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X3.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_INT_X4.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM6_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET1_PWM0_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT4_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM3_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT4_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X5.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT30_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT26_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT22_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT18_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT14_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT3_PSL.VALUE=0x00000008\r
+DRIVER.HET.VAR.HET2_INT_X6.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=9\r
+DRIVER.HET.VAR.HET1_BIT28_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT7_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_INT_X7.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT7_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X8.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT18_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT10_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X9.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT11_PSL.VALUE=0x00000800\r
+DRIVER.HET.VAR.HET2_BIT11_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM4_PIN_SELECT.VALUE=16\r
+DRIVER.HET.VAR.HET2_PWM4_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET1_RAM_BASE.VALUE=0xFF460000\r
+DRIVER.HET.VAR.HET2_EDGE6_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM2_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT15_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE2_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET2_BIT11_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP3_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT24_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT16_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT5_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT27_PSL.VALUE=0x08000000\r
+DRIVER.HET.VAR.HET1_BIT19_PSL.VALUE=0x00080000\r
+DRIVER.HET.VAR.HET2_EDGE6_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT24_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT16_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT2_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE3_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_EDGE5_PIN_SELECT.VALUE=21\r
+DRIVER.HET.VAR.HET2_BIT13_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM7_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT27_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT19_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_CAP5_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM4_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT8_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM1_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET2_CAP2_PIN_SELECT.VALUE=4\r
+DRIVER.HET.VAR.HET2_BIT4_PSL.VALUE=0x00000010\r
+DRIVER.HET.VAR.HET1_PWM0_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT29_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT0_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT8_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET2_BIT1_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT12_PSL.VALUE=0x00001000\r
+DRIVER.HET.VAR.HET2_PWM7_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET2_BIT18_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_BIT16_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM3_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM3_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET1_BIT0_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM1_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT6_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP5_PIN_SELECT.VALUE=26\r
+DRIVER.HET.VAR.HET1_BIT28_PSL.VALUE=0x10000000\r
+DRIVER.HET.VAR.HET1_BIT10_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_EDGE7_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM0_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT1_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE7_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE5_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM5_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_BIT3_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE7_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_EDGE1_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM3_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT14_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT4_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_EDGE4_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT5_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_EDGE5_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM5_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT2_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT5_PSL.VALUE=0x00000020\r
+DRIVER.HET.VAR.HET1_PWM7_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT8_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT1_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_LR_ACTUALTIME.VALUE=800.000\r
+DRIVER.HET.VAR.HET1_PWM5_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM4_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET2_BIT9_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM3_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM0_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT5_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_PIN_SELECT.VALUE=18\r
+DRIVER.HET.VAR.HET2_BIT13_PSL.VALUE=0x00002000\r
+DRIVER.HET.VAR.HET2_BIT12_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_EDGE7_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT17_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM6_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM0_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT30_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT27_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT22_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT19_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT14_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM1_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT7_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE5_PIN_SELECT.VALUE=21\r
+DRIVER.HET.VAR.HET1_BIT29_PSL.VALUE=0x20000000\r
+DRIVER.HET.VAR.HET1_BIT0_PSL.VALUE=0x00000001\r
+DRIVER.HET.VAR.HET_DIS_BLACKBOX.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM7_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_HR_ACTUALFREQUENCY.VALUE=80.000\r
+DRIVER.HET.VAR.HET2_PWM5_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET1_BIT25_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT17_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT4_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE0_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_CAP6_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT20_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT12_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT15_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X10.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT28_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_INT_X11.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X20.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X12.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET2_PWM6_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT16_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X21.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X13.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_HR_PRESCALE.VALUE=0\r
+DRIVER.HET.VAR.HET1_EDGE6_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM6_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_LR_PRESCALE.VALUE=6\r
+DRIVER.HET.VAR.HET2_PWM0_PIN_SELECT.VALUE=8\r
+DRIVER.HET.VAR.HET2_BIT6_PSL.VALUE=0x00000040\r
+DRIVER.HET.VAR.HET2_INT_X30.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X22.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X14.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT2_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X31.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X23.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X15.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM3_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET2_INT_X24.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X16.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BASE_PORT.VALUE=0xFFF7B84C\r
+DRIVER.HET.VAR.HET2_PWM5_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT0_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X25.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X17.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET1_PWM3_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT10_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT14_PSL.VALUE=0x00004000\r
+DRIVER.HET.VAR.HET2_INT_X26.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X18.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X27.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X19.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT18_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X28.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM1_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET2_PWM0_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET2_BIT18_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_INT_X29.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM1_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET2_CAP7_PIN_SELECT.VALUE=30\r
+DRIVER.HET.VAR.HET2_BIT8_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM5_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_PWM4_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_PWM3_PIN_SELECT.VALUE=14\r
+DRIVER.HET.VAR.HET1_BIT11_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT1_PSL.VALUE=0x00000002\r
+DRIVER.HET.VAR.HET2_PWM0_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_BIT2_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE6_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT5_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT14_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT6_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_BIT20_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT12_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT16_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT5_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM0_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_BIT6_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM7_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM0_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT8_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE4_PIN_SELECT.VALUE=20\r
+DRIVER.HET.VAR.HET2_BIT7_PSL.VALUE=0x00000080\r
+DRIVER.HET.VAR.HET1_BIT9_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT3_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM5_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT10_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_CAP1_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_EDGE6_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP1_PIN_SELECT.VALUE=2\r
+DRIVER.HET.VAR.HET2_BIT15_PSL.VALUE=0x00008000\r
+DRIVER.HET.VAR.HET2_BIT13_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_EDGE3_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_PWM6_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT9_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT2_PSL.VALUE=0x00000004\r
+DRIVER.HET.VAR.HET2_EDGE0_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET1_BIT26_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT18_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT6_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE3_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT16_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT17_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP4_PIN_SELECT.VALUE=24\r
+DRIVER.HET.VAR.HET1_BIT29_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT0_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM2_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET2_EDGE3_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT3_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT2_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT8_PSL.VALUE=0x00000100\r
+DRIVER.HET.VAR.HET1_PWM1_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT4_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT4_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT25_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT17_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT16_PSL.VALUE=0x00010000\r
+DRIVER.HET.VAR.HET1_PWM1_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_PWM1_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_PWM7_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET1_PWM3_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT24_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT16_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT10_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM5_PIN_SELECT.VALUE=17\r
+DRIVER.HET.VAR.HET1_BIT20_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT12_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT3_PSL.VALUE=0x00000008\r
+DRIVER.HET.VAR.HET1_INT_X10.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X11.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT3_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE7_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_EDGE0_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT7_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X20.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X12.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT14_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM5_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_BIT10_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X21.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X13.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM5_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT18_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT6_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_EDGE4_PIN_SELECT.VALUE=20\r
+DRIVER.HET.VAR.HET1_INT_X30.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X22.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X14.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM3_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET1_INT_X31.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X23.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X15.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE5_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM1_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM7_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM6_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_BIT7_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_INT_X24.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X16.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP2_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM3_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT6_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X25.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X17.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT9_PSL.VALUE=0x00000200\r
+DRIVER.HET.VAR.HET1_BIT5_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X26.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X18.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X27.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X19.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT11_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_INT_X28.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM2_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_RAM_SIZE.VALUE=160\r
+DRIVER.HET.VAR.HET1_EDGE2_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_INT_X29.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT17_PSL.VALUE=0x00020000\r
+DRIVER.HET.VAR.HET2_BIT14_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM3_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_PWM5_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET1_BIT10_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP4_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT8_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT4_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM0_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET1_BIT4_PSL.VALUE=0x00000010\r
+DRIVER.HET.VAR.HET2_PWM1_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET1_EDGE1_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM1_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT27_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT19_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT8_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT14_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP6_PIN_SELECT.VALUE=28\r
+DRIVER.HET.VAR.HET1_PWM2_PIN_SELECT.VALUE=12\r
+DRIVER.HET.VAR.HET1_BIT1_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM3_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_PWM2_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET1_EDGE4_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT28_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT6_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE0_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET2_EDGE6_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM5_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT8_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT4_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE3_PIN_SELECT.VALUE=15\r
+DRIVER.HET.VAR.HET2_PWM2_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT18_PSL.VALUE=0x00040000\r
+DRIVER.HET.VAR.HET1_BIT11_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT10_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_EDGE1_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM7_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM2_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_PWM5_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT8_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP0_PIN_SELECT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT21_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT13_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT5_PSL.VALUE=0x00000020\r
+DRIVER.HET.VAR.HET1_PWM4_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_BIT4_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE2_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_BIT9_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT6_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM6_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_BIT1_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM4_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT7_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM7_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET1_BIT8_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM2_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT12_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT31_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT23_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT15_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP3_PIN_SELECT.VALUE=6\r
+DRIVER.HET.VAR.HET1_BIT7_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_PWM4_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM1_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET2_BIT12_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET1_PWM0_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET1_CAP5_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT26_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT18_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT15_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM0_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET1_EDGE4_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT20_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT12_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT12_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE5_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM6_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT6_PSL.VALUE=0x00000040\r
+DRIVER.HET.VAR.HET2_EDGE1_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM3_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE3_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT28_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_CAP7_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM3_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET2_PWM4_PIN_SELECT.VALUE=16\r
+DRIVER.HET.VAR.HET1_BIT10_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT2_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT9_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM5_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE3_PIN_SELECT.VALUE=15\r
+DRIVER.HET.VAR.HET1_PWM1_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT8_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BASE.VALUE=0xFFF7B800\r
+DRIVER.HET.VAR.HET2_EDGE1_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM6_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM5_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT12_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT2_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT2_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM7_PIN_SELECT.VALUE=19\r
+DRIVER.HET.VAR.HET1_PWM5_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_LR_ACTUALTIME.VALUE=800.000\r
+DRIVER.HET.VAR.HET1_BIT21_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT13_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT11_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM3_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_PWM7_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET1_HR_PRESCALE.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT30_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT22_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT14_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT7_PSL.VALUE=0x00000080\r
+DRIVER.HET.VAR.HET1_HR_ACTUALFREQUENCY.VALUE=80.000\r
+DRIVER.HET.VAR.HET2_PWM1_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT5_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE4_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP0_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT4_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE2_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM7_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_PWM2_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT8_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT11_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM7_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_EDGE6_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_PWM5_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM0_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT9_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_EDGE6_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT10_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP5_PIN_SELECT.VALUE=26\r
+DRIVER.HET.VAR.HET1_PWM1_PIN_SELECT.VALUE=10\r
+DRIVER.HET.VAR.HET1_BIT9_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT13_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_PWM7_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_PWM5_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT24_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT16_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT6_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.HET.VAR.HET2_BIT16_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT10_PSL.VALUE=0x00000400\r
+DRIVER.HET.VAR.HET2_PWM7_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE0_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT30_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT22_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT14_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X0.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE2_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM4_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT28_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT0_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT0_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X1.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE2_PIN_SELECT.VALUE=13\r
+DRIVER.HET.VAR.HET2_PWM2_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT8_PSL.VALUE=0x00000100\r
+DRIVER.HET.VAR.HET1_INT_X2.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_DIS_BLACKBOX.VALUE=0\r
+DRIVER.HET.VAR.HET2_LR_TIME.VALUE=800.000\r
+DRIVER.HET.VAR.HET1_INT_X3.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_EDGE5_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM5_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET1_BIT29_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT0_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_INT_X4.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT2_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT21_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT13_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X5.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT20_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT12_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT3_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_INT_X6.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM0_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET1_INT_X7.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BASE_PORT.VALUE=0xFFF7B94C\r
+DRIVER.HET.VAR.HET1_INT_X8.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT17_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT2_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM6_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET1_BIT30_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT22_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT14_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_INT_X9.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BASE.VALUE=0xFFF7B900\r
+DRIVER.HET.VAR.HET2_EDGE2_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_EDGE0_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET2_BIT10_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP2_PIN_SELECT.VALUE=4\r
+DRIVER.HET.VAR.HET1_BIT11_PSL.VALUE=0x00000800\r
+DRIVER.HET.VAR.HET2_PWM2_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_PWM0_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT31_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT23_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT20_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT15_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT12_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM4_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET2_BIT18_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP1_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT30_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT22_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT14_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_PWM6_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT31_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT23_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT15_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT9_PSL.VALUE=0x00000200\r
+DRIVER.HET.VAR.HET2_BIT6_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE6_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT7_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE1_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_RAM_SIZE.VALUE=160\r
+DRIVER.HET.VAR.HET2_BIT9_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT21_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT13_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM2_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT0_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM3_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET2_CAP3_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT0_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM3_PIN_SELECT.VALUE=14\r
+DRIVER.HET.VAR.HET2_PWM6_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT14_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE7_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT17_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_EDGE2_PIN_SELECT.VALUE=13\r
+DRIVER.HET.VAR.HET1_BIT20_PSL.VALUE=0x00100000\r
+DRIVER.HET.VAR.HET1_BIT12_PSL.VALUE=0x00001000\r
+DRIVER.HET.VAR.HET1_HR_FREQUENCY.VALUE=80.000\r
+DRIVER.HET.VAR.HET2_PWM2_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_EDGE5_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE1_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM5_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT24_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT16_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM1_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT18_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE0_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT0_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM6_PIN_SELECT.VALUE=18\r
+DRIVER.HET.VAR.HET2_EDGE2_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE7_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT1_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_EDGE5_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_EDGE4_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT6_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT30_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT22_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT14_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT4_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT1_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM7_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT8_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT0_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT4_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE7_PIN_SELECT.VALUE=23\r
+DRIVER.HET.VAR.HET2_PWM7_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_PWM3_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_PWM3_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_EDGE3_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM1_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM2_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT28_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT26_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT18_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP4_PIN_SELECT.VALUE=24\r
+DRIVER.HET.VAR.HET2_PWM0_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_PWM0_PIN_SELECT.VALUE=8\r
+DRIVER.HET.VAR.HET1_BIT21_PSL.VALUE=0x00200000\r
+DRIVER.HET.VAR.HET1_BIT13_PSL.VALUE=0x00002000\r
+DRIVER.HET.VAR.HET1_LR_TIME.VALUE=800.000\r
+DRIVER.HET.VAR.HET2_EDGE0_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM3_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET1_BIT25_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT21_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT17_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT13_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM5_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET2_PWM1_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT20_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT12_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT11_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT24_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT16_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM5_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_RAM_BASE.VALUE=0xFF440000\r
+DRIVER.HET.VAR.HET2_PWM3_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT7_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM4_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT15_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP4_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT8_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE1_PIN_SELECT.VALUE=11\r
+DRIVER.HET.VAR.HET1_CAP7_PIN_SELECT.VALUE=30\r
+DRIVER.HET.VAR.HET1_BIT31_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT23_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT15_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE7_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET2_BIT2_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE4_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT15_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_BIT10_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP6_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM2_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT18_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT0_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET1_BIT30_PSL.VALUE=0x40000000\r
+DRIVER.HET.VAR.HET1_BIT22_PSL.VALUE=0x00400000\r
+DRIVER.HET.VAR.HET1_BIT14_PSL.VALUE=0x00004000\r
+DRIVER.HET.VAR.HET2_EDGE1_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM7_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE2_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT26_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT18_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM1_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT16_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT5_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_RAM_PARITY_ENA.VALUE=0x00000005\r
+DRIVER.HET.VAR.HET1_PWM7_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM0_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET2_PWM0_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT1_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_CAP1_PIN_SELECT.VALUE=2\r
+DRIVER.HET.VAR.HET1_PWM7_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET1_BIT2_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM6_PERIOD_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM4_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT10_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM7_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT10_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE7_PIN_SELECT.VALUE=23\r
+DRIVER.HET.VAR.HET1_BIT24_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT16_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT5_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM7_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET2_PWM7_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET2_PWM4_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT3_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE5_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT6_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM6_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_EDGE4_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM1_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT11_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE1_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET2_LR_PRESCALE.VALUE=6\r
+DRIVER.HET.VAR.HET2_PWM2_PIN_SELECT.VALUE=12\r
+DRIVER.HET.VAR.HET2_BIT1_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT31_PSL.VALUE=0x80000000\r
+DRIVER.HET.VAR.HET1_BIT23_PSL.VALUE=0x00800000\r
+DRIVER.HET.VAR.HET1_BIT15_PSL.VALUE=0x00008000\r
+DRIVER.HET.VAR.HET1_PWM6_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_EDGE2_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT30_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT27_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT22_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT19_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT14_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_EDGE2_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET2_BIT8_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT9_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE1_PIN_SELECT.VALUE=11\r
+DRIVER.HET.VAR.HET1_BIT25_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT17_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT8_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_PWM4_PERIOD_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM0_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT14_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT2_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM5_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT0_PSL.VALUE=0x00000001\r
+DRIVER.HET.VAR.HET1_PWM5_PIN_SELECT.VALUE=17\r
+DRIVER.HET.VAR.HET1_BIT25_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT17_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM6_DUTY_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT4_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE1_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_CAP7_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT28_ANDSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT24_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT16_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT16_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_BIT12_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM4_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_PWM1_ACTION.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT0_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE7_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM1_DUTY_INTENA.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE6_PIN_SELECT.VALUE=22\r
+DRIVER.HET.VAR.HET2_BIT2_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_DIS_BLACKBOX.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT24_PSL.VALUE=0x01000000\r
+DRIVER.HET.VAR.HET1_BIT16_PSL.VALUE=0x00010000\r
+DRIVER.HET.VAR.HET2_EDGE3_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE6_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET1_EDGE3_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM6_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET1_BIT28_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT13_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_PWM5_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET1_PWM1_DUTY.VALUE=50\r
+DRIVER.HET.VAR.HET1_BIT20_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT12_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP3_PIN_SELECT.VALUE=6\r
+DRIVER.HET.VAR.HET2_BIT10_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT2_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_PWM3_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_EDGE3_EVENT.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM6_PERIOD_PRESCALER.VALUE=159872\r
+DRIVER.HET.VAR.HET2_PWM3_DUTY_PRESCALER.VALUE=80128\r
+DRIVER.HET.VAR.HET1_BIT3_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET2_PWM1_ENA.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT1_PSL.VALUE=0x00000002\r
+DRIVER.HET.VAR.HET1_BIT26_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT18_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT6_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM1_DUTYTIME.VALUE=500.000\r
+DRIVER.HET.VAR.HET2_BIT5_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_PWM7_POLARITY.VALUE=3\r
+DRIVER.HET.VAR.HET2_BIT16_HRSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_CAP0_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET1_BIT4_XORSHARE.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_EDGE0_PIN_SELECT.VALUE=9\r
+DRIVER.HET.VAR.HET2_BIT10_DOUT.VALUE=0\r
+DRIVER.HET.VAR.HET1_CAP6_PIN_SELECT.VALUE=28\r
+DRIVER.HET.VAR.HET1_PWM2_PERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_EDGE5_BOTH.VALUE=0\r
+DRIVER.HET.VAR.HET2_BIT13_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_BIT3_PULDIS.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_EDGE0_POLARITY.VALUE=0\r
+DRIVER.HET.VAR.HET2_PWM7_ACTUALPERIOD.VALUE=1000.000\r
+DRIVER.HET.VAR.HET2_BIT3_PDR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT25_PSL.VALUE=0x02000000\r
+DRIVER.HET.VAR.HET1_BIT17_PSL.VALUE=0x00020000\r
+DRIVER.HET.VAR.HET2_EDGE4_LVL.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT31_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT29_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET1_BIT23_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT15_PULL.VALUE=1\r
+DRIVER.HET.VAR.HET1_BIT0_DIR.VALUE=0x00000000\r
+DRIVER.HET.VAR.HET2_CAP2_POLARITY.VALUE=0\r
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+DRIVER.DMM.VAR.DMM_PORT_BIT16_DOUT.VALUE=0\r
+DRIVER.DMM.VAR.DMM_PORT_BIT17_FUN.VALUE=1\r
+DRIVER.DMM.VAR.DMM_PORT_BIT15_PSL.VALUE=1\r
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PULDIS.VALUE=0\r
+DRIVER.DMM.VAR.DMM_PORT_BIT17_PDR.VALUE=0\r
+DRIVER.DMM.VAR.DMM_PORT_BIT10_PULDIS.VALUE=0\r
+DRIVER.DMM.VAR.DMM_PORT_BIT18_FUN.VALUE=1\r
+DRIVER.DMM.VAR.DMM_PORT_BIT16_PSL.VALUE=1\r
+DRIVER.DMM.VAR.DMM_PORT_BIT3_PULL.VALUE=2\r
+DRIVER.DMM.VAR.DMM_PORT_BIT0_DIR.VALUE=1\r
+DRIVER.DMM.VAR.DMM_PORT_BIT18_PDR.VALUE=0\r
+DRIVER.DMM.VAR.DMM_PORT_BIT6_DOUT.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PORT_BIT0_DIR.VALUE=0\r
+DRIVER.I2C.VAR.I2C_STOPBITS.VALUE=2\r
+DRIVER.I2C.VAR.I2C_PORT_BIT1_DIR.VALUE=0\r
+DRIVER.I2C.VAR.I2C_ICXRDYINTLVL.VALUE=0\r
+DRIVER.I2C.VAR.I2C_BASE_PORT.VALUE=0xFFF7D44C\r
+DRIVER.I2C.VAR.I2C_DATACOUNT.VALUE=8\r
+DRIVER.I2C.VAR.I2C_ADDRMODE.VALUE=7BIT_AMODE\r
+DRIVER.I2C.VAR.I2C_PORT_BIT0_FUN.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PDR.VALUE=0\r
+DRIVER.I2C.VAR.I2C_BC_VALUE.VALUE=0x0003\r
+DRIVER.I2C.VAR.I2C_PORT_BIT1_FUN.VALUE=0\r
+DRIVER.I2C.VAR.I2C_RM_ENA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_BC.VALUE=2_BIT\r
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PDR.VALUE=0\r
+DRIVER.I2C.VAR.I2C_TXRX_VALUE.VALUE=0\r
+DRIVER.I2C.VAR.I2C_SCDLVL.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PSL.VALUE=1\r
+DRIVER.I2C.VAR.I2C_STPCND.VALUE=1\r
+DRIVER.I2C.VAR.I2C_ALINTENA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PRESCALE.VALUE=9\r
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PSL.VALUE=1\r
+DRIVER.I2C.VAR.I2C_TXRX.VALUE=TRANSMITTER\r
+DRIVER.I2C.VAR.I2C_PORT_BIT0_DOUT.VALUE=0\r
+DRIVER.I2C.VAR.I2C_ALINTLVL.VALUE=0\r
+DRIVER.I2C.VAR.I2C_RXDMA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PULDIS.VALUE=0\r
+DRIVER.I2C.VAR.I2C_BASE.VALUE=0xFFF7D400\r
+DRIVER.I2C.VAR.I2C_ARDYINTENA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PORT_BIT1_DOUT.VALUE=0\r
+DRIVER.I2C.VAR.I2C_TXDMA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_MSMODE.VALUE=1\r
+DRIVER.I2C.VAR.I2C_ICCH.VALUE=35\r
+DRIVER.I2C.VAR.I2C_AASLVL.VALUE=0\r
+DRIVER.I2C.VAR.I2C_ICCL.VALUE=35\r
+DRIVER.I2C.VAR.I2C_AAS.VALUE=0\r
+DRIVER.I2C.VAR.I2C_ADDRMODE_VALUE.VALUE=0x0001\r
+DRIVER.I2C.VAR.I2C_ICRRDYINTENA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_FDF.VALUE=0\r
+DRIVER.I2C.VAR.I2C_ARDYINTLVL.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PARITYENA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PORT_BIT0_PULL.VALUE=2\r
+DRIVER.I2C.VAR.I2C_LENGTH.VALUE=8\r
+DRIVER.I2C.VAR.I2C_NACKINTENA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_SCD.VALUE=0\r
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PULL.VALUE=2\r
+DRIVER.I2C.VAR.I2C_ICRRDYINTLVL.VALUE=0\r
+DRIVER.I2C.VAR.I2C_STACND.VALUE=1\r
+DRIVER.I2C.VAR.I2C_PORT_BIT1_PULDIS.VALUE=0\r
+DRIVER.I2C.VAR.I2C_ICXRDYINTENA.VALUE=0\r
+DRIVER.I2C.VAR.I2C_NACKINTLVL.VALUE=0\r
+DRIVER.I2C.VAR.I2C_EVENPARITY.VALUE=0\r
+DRIVER.I2C.VAR.I2C_BAUDRATE.VALUE=100\r
+DRIVER.I2C.VAR.I2C_MODCLK.VALUE=8\r
+DRIVER.DCC.VAR.DCC1_ENABLE_KEY.VALUE=10\r
+DRIVER.DCC.VAR.PINMUX_BASE.VALUE=0xFFFFEA00\r
+DRIVER.DCC.VAR.DCC1_DETECTION_TIME.VALUE=5000.00\r
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_VALUE.VALUE=0x0002\r
+DRIVER.DCC.VAR.DCC1_ENABLE_ERROR_INTERRUPT.VALUE=0xA\r
+DRIVER.DCC.VAR.DCC2_ENABLE.VALUE=0xA\r
+DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40\r
+DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA\r
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001\r
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0\r
+DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0\r
+DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1\r
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0\r
+DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=5000.00\r
+DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0\r
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002\r
+DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1\r
+DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0\r
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN\r
+DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK\r
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0\r
+DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=1584\r
+DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00\r
+DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0\r
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=160.00\r
+DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0\r
+DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA\r
+DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5\r
+DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5\r
+DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400\r
+DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA\r
+DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA\r
+DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0x5\r
+DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=78408\r
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001\r
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN\r
+DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1\r
+DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0\r
+DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=792000\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_28.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_20.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_12.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_2.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX61_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX53_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX45_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX37_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX29_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX7_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_29.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_21.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_13.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_3.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX61_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_30.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_22.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_14.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_10.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_4.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX61_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX53_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX50_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX45_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_31.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_29_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_23.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_5.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX61_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX53_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX45_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX37_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX29_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_24.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_20.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_12.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_6.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_6.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX61_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX53_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX45_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX37_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX29_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_25.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_21.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_17.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_13.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_7.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_7.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX53_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX45_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX37_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX29_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_30.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_26.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_22.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_18.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_14.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_8.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_8.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_10.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX99_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_96_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_88_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_5_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_31.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_27.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_23.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_21_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_19.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_9.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_11.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_28.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_24.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_12.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_29.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_25.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_17.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_13.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_26.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_18.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_14.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_10.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_57_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_49_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_27.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_19.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_15.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_11.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_CHPR_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX30_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX22_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX14_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_28.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_16.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_12.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX30_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX22_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX14_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_29.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_13.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX30_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX22_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_14.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_18_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_28_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_15.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_1.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_16.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_2.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_3.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_PRITY_10.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.DMA_ENABLEINT_4.VALUE=1\r
+DRIVER.PINMUX.VAR.PINMUX10.VALUE="PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18"\r
+DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_PRITY_11.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.DMA_CHPR_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.PINMUX11.VALUE="PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24"\r
+DRIVER.PINMUX.VAR.DMA_PRITY_12.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.PINMUX20.VALUE="PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11"\r
+DRIVER.PINMUX.VAR.PINMUX12.VALUE="PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA"\r
+DRIVER.PINMUX.VAR.DMA_PRITY_13.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.PINMUX21.VALUE="PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9"\r
+DRIVER.PINMUX.VAR.PINMUX13.VALUE="PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0"\r
+DRIVER.PINMUX.VAR.DMA_PRITY_14.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.PINMUX30.VALUE=0\r
+DRIVER.PINMUX.VAR.PINMUX22.VALUE="PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11"\r
+DRIVER.PINMUX.VAR.PINMUX14.VALUE="PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1"\r
+DRIVER.PINMUX.VAR.MUX92_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX84_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX76_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX68_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_21_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_15.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.PINMUX31.VALUE=0\r
+DRIVER.PINMUX.VAR.PINMUX23.VALUE=PINMUX_BALL_C6_EMIF_ADDR_8\r
+DRIVER.PINMUX.VAR.PINMUX15.VALUE="PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18"\r
+DRIVER.PINMUX.VAR.DMA_PRITY_16.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.PINMUX32.VALUE=0\r
+DRIVER.PINMUX.VAR.PINMUX16.VALUE="PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13"\r
+DRIVER.PINMUX.VAR.PINMUX33.VALUE=0\r
+DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08"\r
+DRIVER.PINMUX.VAR.PINMUX34.VALUE=0\r
+DRIVER.PINMUX.VAR.PINMUX26.VALUE="PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3"\r
+DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0"\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_26_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_20_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_18_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.PINMUX35.VALUE=0\r
+DRIVER.PINMUX.VAR.PINMUX27.VALUE="PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2"\r
+DRIVER.PINMUX.VAR.PINMUX19.VALUE="PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10"\r
+DRIVER.PINMUX.VAR.PINMUX28.VALUE="PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3"\r
+DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.PINMUX29.VALUE=PINMUX_BALL_D3_SPI2NENA\r
+DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_10.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.MUX98_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX7_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_11.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_PRITY_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX98_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_20.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_12.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.MUX100_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX98_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_21.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_13.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.MUX100_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_30.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_22.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_14.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_0.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.MUX100_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_31.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_23.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_15.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_1.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_1.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX100_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_24.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_16.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_2.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_2.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX100_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX91_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX83_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX75_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX67_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX59_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_25.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_17.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_3.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_3.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX91_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX83_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX75_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX67_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX59_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_26.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_18.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_4.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_ENABLEREG_4.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX91_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX83_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX75_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX67_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX61_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX59_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX53_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX45_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX37_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX29_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_102_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_27.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_19.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_5.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_0_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX91_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX83_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX75_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX67_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX59_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_28.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_6.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_6.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.MUX91_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX83_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX75_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX67_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX59_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX6_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_29.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_7.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_7.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_8.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_8.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_31_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_26_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_23_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_18_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_9.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX44_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX36_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX28_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX6_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_10.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_10.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX60_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX52_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX44_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX36_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX28_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_25_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_17_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_11.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTASS_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX60_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX52_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX44_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX36_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX28_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_20.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_20.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_12.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_12.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX60_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX52_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX44_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX36_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX28_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_21.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_21.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_13.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_13.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX52_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX44_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX36_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX28_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_30.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_30.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_22.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_22.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_14.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_14.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX104_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_31.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_31.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_23.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_23.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_15.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_PRITY_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ACC_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_STADD_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_24.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_24.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_16.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_STADD_2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_25.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_25.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_17.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_17.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_STADD_3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX21_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX13_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_26.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_26.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_18.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_18.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_STADD_4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX30_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX22_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX21_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX14_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX13_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_71_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_63_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_55_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_47_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_39_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_27.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_27.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_19.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_19.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX21_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX13_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_28.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_28.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX21_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX13_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_29.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_29.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX21_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX13_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX95_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX87_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_24_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TRIG_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_0.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_28_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_1.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_6.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_2.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_7.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_3.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_8.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_4.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_5.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_6.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_7.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_8.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_4.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_30_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_22_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_9.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.GATE_EMIF_CLK.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX97_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX89_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX97_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX89_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_8.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX97_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX89_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX80_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX72_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX64_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX56_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX48_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX97_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX89_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX97_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX89_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_107_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_29_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX90_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX82_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX74_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX66_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX58_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_DEBUGMODE.VALUE=IGNORE_SUSPEND\r
+DRIVER.PINMUX.VAR.MUX90_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX82_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX74_OPTION1.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX66_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX58_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_0.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ERRACT.VALUE=IGNORE\r
+DRIVER.PINMUX.VAR.MUX90_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX82_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX74_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX66_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX58_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX3_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_100_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_1.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_CHPR_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX90_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX82_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX74_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX66_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX58_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_2.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_BASE_PORT.VALUE=0xFFFFF040\r
+DRIVER.PINMUX.VAR.MUX90_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX82_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_3.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.MUX5_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_4.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.MUX5_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_30_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_22_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_5.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_1.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX5_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_6.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_2.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_7.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_3.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX51_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX43_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX35_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX27_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX19_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX5_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_8.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_INTEN_10.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_4.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX51_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX43_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX41_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX35_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX33_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX27_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX25_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_27_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_21_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_19_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_9.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_INTEN_11.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_5.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX51_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX43_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX35_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX27_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX19_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_12.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_6.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX51_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_13.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_7.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX43_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX35_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX27_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX19_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_14.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_8.VALUE=1\r
+DRIVER.PINMUX.VAR.ALT_ADC_SELECT.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX98_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_92_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_84_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_76_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_68_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_1_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_15.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_PRITY_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_9.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTEN_16.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX20_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX12_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX20_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX12_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX20_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX12_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_61_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_53_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_45_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_37_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX20_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX12_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX20_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX12_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX20_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX12_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX100_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_30_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_22_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_14_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_20_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_0_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX10_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_27_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_24_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_19_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ENDADD_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ENDADD_2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ENDADD_3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ENDADD_4.VALUE=0\r
+DRIVER.PINMUX.VAR.ETHERNET_SELECT.VALUE=RMII\r
+DRIVER.PINMUX.VAR.MUX91_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX83_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX75_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX67_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX59_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_26_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_18_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTASS_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTASS_1.VALUE=TO_VIM\r
+DRIVER.PINMUX.VAR.DMA_INTASS_2.VALUE=TO_VIM\r
+DRIVER.PINMUX.VAR.CONCOUNT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTASS_3.VALUE=TO_VIM\r
+DRIVER.PINMUX.VAR.DMA_INTASS_4.VALUE=TO_VIM\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHAS_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ACC_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHAS_2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX96_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX88_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHAS_3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX96_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX88_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_10.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_10.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_CHAS_4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX96_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX88_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX6_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_11.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_INTMP_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHAS_5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX96_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX88_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_20.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_20.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_12.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_12.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_CHAS_6.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX96_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX88_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_21.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_21.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_13.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_13.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_3.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_CHAS_7.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_30.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_30.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_22.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_22.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_14.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_14.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_4.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_CHAS_8.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_105_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_31.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_31.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_25_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_23.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_23.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_17_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_15.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_TRIG_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHAS_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_24.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_24.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_16.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX81_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX73_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX65_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX57_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX49_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_25.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_25.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_17.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_17.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX81_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX73_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX65_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX57_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX49_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_26.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_26.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_18.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_18.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_8.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX81_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX73_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX65_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX60_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX57_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX52_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX49_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX44_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX36_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX28_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_29_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_27.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_27.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_19.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_19.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_9.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ENABLE1.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX81_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX73_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX65_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX57_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX49_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_28.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_28.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX81_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX73_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX65_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX57_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX49_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX4_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXS_29.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_29.VALUE=ENABLED\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX57_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX49_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX4_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_BYP_10.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX4_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_0_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_BYP_11.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_1.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX4_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_6.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_BYP_12.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_2.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX50_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX42_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX34_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX18_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX4_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_BYP_13.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_3.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX42_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX34_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX26_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX18_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX4_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_8.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_BYP_14.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_4.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX50_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX42_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX34_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX26_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX18_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_97_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_89_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_31_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_23_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_IFT_COUNT_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_BYP_15.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_5.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_PRITY_1.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.MUX50_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX42_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX34_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX26_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX18_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_BYP_16.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_6.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_PRITY_2.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.MUX50_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX42_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX34_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX26_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX18_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_7.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_PRITY_3.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.MUX50_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX42_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX34_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX26_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX18_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_8.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_PRITY_4.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.MUX103_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_90_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_82_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_74_SELECT.VALUE=1\r
+DRIVER.PINMUX.VAR.PIN_MUX_66_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_58_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTBTCEN_9.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_TRIG_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_5.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.DMA_PRITY_6.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.MUX11_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_PRITY_7.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.MUX11_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_PRITY_8.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.MUX21_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX13_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_51_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_43_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_35_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_27_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_9.VALUE=FIXED\r
+DRIVER.PINMUX.VAR.MUX11_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX11_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.AD1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX11_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.AD2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX94_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX86_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX78_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_20_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_12_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_0_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_31_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_23_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_20_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX9_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_30_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_28_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_22_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_0_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX104_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX104_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX104_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_PRITY_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.ALT_ADC.VALUE=0\r
+DRIVER.PINMUX.VAR.I2C.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX104_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX104_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX95_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX87_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX79_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX95_OPTION1.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX87_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX79_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX95_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX87_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX79_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX71_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX63_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX55_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX47_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX39_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_DEBUGMODE_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX95_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX87_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX79_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX95_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX87_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX79_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_10.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_103_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_21_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_20.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_12.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX80_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX72_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX64_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX56_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX48_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_21.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_13.VALUE=0\r
+DRIVER.PINMUX.VAR.HET1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX80_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX72_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX64_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX56_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX48_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_30.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_22.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_14.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_10.VALUE=0\r
+DRIVER.PINMUX.VAR.HET2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX80_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX72_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX64_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX56_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX48_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX2_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_31.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_28_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_25_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_23.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_17_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_1.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX80_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX72_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX64_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX56_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX48_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_24.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_20.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_12.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_2.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX80_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX72_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX64_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX56_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX48_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX3_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_25.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_21.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_17.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_13.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_3.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX56_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX48_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX3_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_30.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_26.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_22.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_18.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_14.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_10.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_INTEN_4.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX3_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_31.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_27_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_27.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_23.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_19_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_19.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_11.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_AIM_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTEN_5.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTASS_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX3_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_28.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_24.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_20.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_12.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_INTEN_6.VALUE=1\r
+DRIVER.PINMUX.VAR.EMIF.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX41_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX33_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX25_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX17_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX3_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_29.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_25.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_21.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_17.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_13.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_INTEN_7.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_26.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_22.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_18.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_14.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_10.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_8.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX41_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX40_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX33_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX32_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX25_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX24_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX17_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX16_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_95_SELECT.VALUE=1\r
+DRIVER.PINMUX.VAR.PIN_MUX_87_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_79_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_4_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_31.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_27.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_23.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_19.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_15.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTEN_9.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ACC_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX41_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX33_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX25_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX17_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_28.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_24.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_20.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_16.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_12.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX41_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX33_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX25_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX17_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_29.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_25.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_21.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_17.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_13.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX41_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX33_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX25_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX17_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_30.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_26.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_22.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_18.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_14.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX97_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX89_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_80_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_72_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_64_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_56_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_48_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_31.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_27.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_23.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_19.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_11.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.GIOA.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_28.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_24.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.GIOB.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_29.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_25.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_17.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.GIOB_DISABLE.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX10_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_26.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_18.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX10_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_27.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_26_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_23.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_19.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_18_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_15.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX10_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_28.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_24.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_16.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX10_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_29.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_25.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_17.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.MUX10_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.PIN_MUX_10_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_27.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_19.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_BYP_1.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_28.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_BYP_2.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_29.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_BYP_3.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_BYP_4.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_AIM_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_BYP_5.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_BYP_6.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_BYP_7.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_BYP_8.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX90_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX82_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX74_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX66_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX58_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_24_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_BYP_9.VALUE=1\r
+DRIVER.PINMUX.VAR.MIBSPI1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX103_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MIBSPI3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX103_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.OHCI0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX103_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MIBSPI5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMM.VALUE=0\r
+DRIVER.PINMUX.VAR.W2FC.VALUE=0\r
+DRIVER.PINMUX.VAR.OHCI1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX103_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX103_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX94_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX86_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX78_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX94_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX86_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX78_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX94_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX86_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX78_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX5_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_108_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX94_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX86_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX78_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX94_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX86_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX78_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX9_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX9_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_10.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_101_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_11.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_PRITY_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX9_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_12.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.MUX71_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX63_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX55_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX47_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX39_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX9_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_13.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.MUX71_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX63_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX55_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX47_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX39_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX9_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_10.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_14.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.MUX71_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX63_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX55_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX51_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX47_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX43_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX39_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX35_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX27_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX19_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_24_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_21_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_11.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_15.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.MUX71_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX63_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX55_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX47_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX39_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_20.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_12.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_6.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_16.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.MUX71_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX63_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX55_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX47_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX39_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_21.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_13.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_7.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX55_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX47_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX39_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX2_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_30.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_22.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_14.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_8.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TRIG_10.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.MUX2_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_31.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_31_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_29_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_23.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_23_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_15.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXD_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_11.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.MUX2_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_24.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_16.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_6.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TRIG_12.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.MUX40_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX32_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX24_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX16_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX2_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_25.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_17.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_7.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TRIG_13.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.ETM.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX40_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX32_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX24_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX16_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX2_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_26.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_18.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_8.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TRIG_14.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_10.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX40_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX32_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX24_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX16_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_93_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_85_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_77_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_69_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_2_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_27.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_19.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_IET_COUNT_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TRIG_15.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_PRITY_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_11.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX40_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX32_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX24_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX16_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_28.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_TRIG_16.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_12.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX40_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX32_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX24_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX16_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_29.VALUE=CONSTANT\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_13.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX40_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX32_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX24_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX16_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_14.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_10.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX102_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_70_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_62_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_54_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_46_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_38_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_0_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_15.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_11.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_CHPR_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ERRACT_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MII.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTFTCEN_16.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_12.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_13.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_14.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX20_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_30_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_22_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_15.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_TRIG_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHPR_1.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_16.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_CHPR_2.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_CHPR_3.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_INTMP_10.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_CHPR_4.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.MUX93_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX85_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX77_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX69_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_29_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_26_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_18_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_11.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_CHPR_5.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_TRIG_1.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTMP_12.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_CHPR_6.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_TRIG_2.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTMP_13.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_CHPR_7.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_TRIG_3.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTMP_14.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_CHPR_8.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_TRIG_4.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_28_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_26_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_18_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_6_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_15.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_CHPR_9.VALUE=HIGH\r
+DRIVER.PINMUX.VAR.DMA_TRIG_5.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_1.VALUE=1\r
+DRIVER.PINMUX.VAR.SCI.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_16.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_TRIG_6.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_2.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_TRIG_7.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_3.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_TRIG_8.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_4.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX8_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_20_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_9_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_9.VALUE=HARDWARE_TRIGGER\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_5.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_1.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_6.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_2.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_ENABLEPAR.VALUE=1\r
+DRIVER.PINMUX.VAR.MUX102_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_7.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_3.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.MUX102_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_8.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_4.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.MUX102_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTHBCEN_9.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_CHPR_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_5.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_TRIG_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ACC_1.VALUE=ALL\r
+DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTMP_6.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_ACC_2.VALUE=ALL\r
+DRIVER.PINMUX.VAR.MUX102_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX93_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX85_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX77_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX69_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTMP_7.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_ACC_3.VALUE=ALL\r
+DRIVER.PINMUX.VAR.MUX93_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX85_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX77_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX69_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTMP_8.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.DMA_ACC_4.VALUE=ALL\r
+DRIVER.PINMUX.VAR.MUX93_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX85_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX77_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX70_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX69_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX62_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX54_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX46_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX38_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_106_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_27_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_19_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_0_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTMP_9.VALUE=GROUP_A\r
+DRIVER.PINMUX.VAR.MUX93_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX85_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX77_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX69_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX93_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX85_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX77_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_BASE.VALUE=0xFFFFF000\r
+DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX62_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX54_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX38_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX8_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX70_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX62_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX54_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX46_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX38_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX8_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX70_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX62_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX54_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX46_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX38_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX1_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_20_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_12_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX70_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX62_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX54_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX46_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX38_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX70_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX62_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX54_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX46_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX38_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX1_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX54_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX46_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX38_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX1_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX1_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_98_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_7_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_25_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_17_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_75_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_67_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_59_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TRIG_8_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX31_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX23_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX15_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX31_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX23_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX15_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX31_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX23_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX15_OPTION5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX96_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX88_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_60_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_52_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_44_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_36_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_28_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_0.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_21_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_13_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_10_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_PRITY_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_BASE_RAM.VALUE=0xFFF80000\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_6.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_2.VALUE=0\r
+DRIVER.PINMUX.VAR.RTP.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_7.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_8.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHAS_10.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_30_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_25_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_22_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_AIM_17_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_5.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHAS_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_1.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_6.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHAS_12.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_2.VALUE=1\r
+DRIVER.PINMUX.VAR.SPI2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_7.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHAS_13.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_3.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_8.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHAS_14.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_4.VALUE=1\r
+DRIVER.PINMUX.VAR.SPI4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_30_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_24_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_22_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_16_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_9.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_AIM_2_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHAS_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_5.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTASS_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.RMII.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHAS_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_6.VALUE=1\r
+DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2"\r
+DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_7.VALUE=1\r
+DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21"\r
+DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_8.VALUE=1\r
+DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5"\r
+DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX65_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX57_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX49_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_11.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_PRITY_14_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_INTLFSEN_9.VALUE=1\r
+DRIVER.PINMUX.VAR.DMA_INTMP_5_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ACC_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24"\r
+DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03"\r
+DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26"\r
+DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_10.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_0.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28"\r
+DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_15.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_1_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_1.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHPR_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.PINMUX7.VALUE="PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_ETMDATA_30"\r
+DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_20.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_12.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_2.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31"\r
+DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX76_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX68_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_21.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_13.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_3.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3"\r
+DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX68_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_30.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_22.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_14.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_4.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.MUX92_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX84_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX76_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX68_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX4_CONFLICT.VALUE=0\r
+DRIVER.PINMUX.VAR.PIN_MUX_104_SELECT.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_31.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_31_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_26_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_23.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_23_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_19.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_18_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_15.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_ADDMW_15_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_ADDMR_7_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_5.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_4_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_3_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_TRIG_11_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.MUX92_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX84_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX76_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX68_OPTION3.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_28.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_24.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_16.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_6.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.MUX92_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29.VALUE=8BIT\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_25.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_17.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_7.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.MUX7_OPTION1.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_26.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_18.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_10.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_8.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_0.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_0.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX7_OPTION2.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_27.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_27_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_EIDXS_19.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_19_VALUE.VALUE=0x0001\r
+DRIVER.PINMUX.VAR.DMA_FIDXD_11.VALUE=0\r
+DRIVER.PINMUX.VAR.DMA_CHANNEL_9.VALUE=CHANNEL0\r
+DRIVER.PINMUX.VAR.DMA_TTYPE_1.VALUE=FRAME_TRANSFER\r
+DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_1.VALUE=0\r
+DRIVER.PINMUX.VAR.MUX7_OPTION3.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH2_PSIH.VALUE=0\r
+DRIVER.CRC.VAR.HTU_CPB_7_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH2_PSIL.VALUE=0\r
+DRIVER.CRC.VAR.HTU_DCP0_TRDIR_1.VALUE=HET_TO_MAIN_MEM\r
+DRIVER.CRC.VAR.CRC_CH1_CCI.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_ICPBL_7_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_ICPA_5_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_ICPB_1_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_DEBMOD_1.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH1_CFI.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_ICPAL_1_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_ENABUS_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_CPA_2_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH2_WDTO.VALUE=0x00000000\r
+DRIVER.CRC.VAR.CRC_CH2_CCI.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_MP1_ACC_1.VALUE=READ_ONLY\r
+DRIVER.CRC.VAR.HTU_CONTPAR_1.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH2_CFI.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_ICPB_6_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_DCP0_EC_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_DCP0_CPBFULADD_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPAL_6_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_CPA_7_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_CPB_3_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH1_DTE.VALUE=1\r
+DRIVER.CRC.VAR.HTU_DCP0_FC_1.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH1_CVH.VALUE=0x00000000\r
+DRIVER.CRC.VAR.CRC_CH1_PSSIH.VALUE=0\r
+DRIVER.CRC.VAR.HTU_BASE.VALUE=0xFFF7A400\r
+DRIVER.CRC.VAR.CRC_CH1_CVL.VALUE=0x00000000\r
+DRIVER.CRC.VAR.CRC_CH1_PSSIL.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPBL_3_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_ICPA_1_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH2_DTE.VALUE=1\r
+DRIVER.CRC.VAR.CRC_CH2_CVH.VALUE=0x00000000\r
+DRIVER.CRC.VAR.CRC_CH2_CVL.VALUE=0x00000000\r
+DRIVER.CRC.VAR.CRC_CH1_PCP.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_ICPA_6_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_ICPB_2_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH1_SCP.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_DCP0_CPAFULADD_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPAL_2_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.CRC_CH2_PCP.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_CPA_3_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH1_PSA.VALUE=1\r
+DRIVER.CRC.VAR.CRC_CH1_ORI.VALUE=0x00000000\r
+DRIVER.CRC.VAR.CRC_CH2_SCP.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_MP1_STADD_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPB_7_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH1_TOE.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_ICPAL_7_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.CRC_CH2_PSA.VALUE=1\r
+DRIVER.CRC.VAR.CRC_CH2_ORI.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_CPB_4_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_MP0_ENA_1.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH2_MODE_VALUE.VALUE=0x0001\r
+DRIVER.CRC.VAR.CRC_CH1_URI.VALUE=0x00000000\r
+DRIVER.CRC.VAR.CRC_CH2_PSSIH.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH2_TOE.VALUE=0x00000000\r
+DRIVER.CRC.VAR.CRC_CH2_PSSIL.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH1_BCTO.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_ICPBL_4_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_ICPA_2_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_PAR_1.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH2_URI.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_CONT_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ENAREQ_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_MP1_ERRENA_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_MP0_STADD_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPA_7_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_ICPB_3_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_ICPAL_3_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_CPA_4_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_CPB_0_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH2_BCTO.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_DCP0_MMADD_1.VALUE=POST_INCREMENT\r
+DRIVER.CRC.VAR.HTU_ENAINTMAP_1.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH1_MODE_VALUE.VALUE=0x0001\r
+DRIVER.CRC.VAR.HTU_ICPBL_0_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_CPB_5_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_MP1_ENA_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_DCP0_HETADD.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPBL_5_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_ICPA_3_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_CPA_0_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_RES_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_DCP0_CPATMOD_1.VALUE=POST_INCREMENT\r
+DRIVER.CRC.VAR.HTU_MP1_ENDADD_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPB_4_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_BASE.VALUE=0xFE000000\r
+DRIVER.CRC.VAR.HTU_ICPAL_4_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.CRC_CH1_MODE.VALUE=FULL_CPU\r
+DRIVER.CRC.VAR.HTU_CPA_5_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_CPB_1_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_VBHOLD_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_MP0_ERRENA_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPBL_1_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_CPB_6_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.CRC_CH2_MODE.VALUE=FULL_CPU\r
+DRIVER.CRC.VAR.HTU_DCP0_TRDAT_1.VALUE=32BIT\r
+DRIVER.CRC.VAR.HTU_ICPBL_6_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_ICPA_4_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_ICPB_0_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_ICPAL_0_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_CPA_1_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_DCP0_CPBTMOD_1.VALUE=POST_INCREMENT\r
+DRIVER.CRC.VAR.CRC_CH1_PSIH.VALUE=0\r
+DRIVER.CRC.VAR.HTU_MP0_ACC_1.VALUE=READ_ONLY\r
+DRIVER.CRC.VAR.CRC_CH1_PSIL.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPB_5_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_ICPAL_5_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_DCP0_ADMOD_1.VALUE=INCREMENT_16BIT\r
+DRIVER.CRC.VAR.HTU_CPA_6_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_CPB_2_SEL_1.VALUE=ENABLE\r
+DRIVER.CRC.VAR.HTU_ENA_1.VALUE=0\r
+DRIVER.CRC.VAR.CRC_CH1_WDTO.VALUE=0x00000000\r
+DRIVER.CRC.VAR.HTU_MP0_ENDADD_1.VALUE=0\r
+DRIVER.CRC.VAR.HTU_ICPBL_2_SEL_1.VALUE=HIGH\r
+DRIVER.CRC.VAR.HTU_ICPA_0_SEL_1.VALUE=ENABLE\r
+DRIVER.EMAC.VAR.EMAC_ADD1.VALUE=FF\r
+DRIVER.EMAC.VAR.EMAC_ADD2.VALUE=FF\r
+DRIVER.EMAC.VAR.EMAC_ADD3.VALUE=FF\r
+DRIVER.EMAC.VAR.EMAC_ADD4.VALUE=FF\r
+DRIVER.EMAC.VAR.EMAC_ADD5.VALUE=FF\r
+DRIVER.EMAC.VAR.EMAC_ADD6.VALUE=FF\r
+DRIVER.EMAC.VAR.EMAC_CTRL_BASE.VALUE=0xFCF78800\r
+DRIVER.EMAC.VAR.MDIO_BASE.VALUE=0xFCF78900\r
+DRIVER.EMAC.VAR.EMAC_BASE.VALUE=0xFCF78000\r
+DRIVER.EMAC.VAR.EMAC_BASE_PORT.VALUE=0xFFFFFFFF\r
+DRIVER.EMAC.VAR.EMAC_PHYADDRESS.VALUE=0\r
+DRIVER.EMAC.VAR.EMAC_CTRL_RAM_BASE.VALUE=0xFC520000\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TAVAV.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_EXTENDED_WAIT.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TA.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_WAIT.VALUE=pin0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_NOR_FLASH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHQZ.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TA.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ENA_SDRAM.VALUE=1\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TELQV.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_MODE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_ASIZE.VALUE=8_bit\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TAVAV.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_BANKS.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_BASE.VALUE=0xFCFFE800\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words\r
+DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=80000000\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_HOLD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_SETUP.VALUE=1\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TSU.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_HOLD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_DEFAULT.VALUE=2000\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_TSU.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_MODE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_STROBE_MODE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=1\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_CLK.VALUE=80\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_ASIZE.VALUE=8_bit\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_NOR_FLASH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_CAS_LATENCY.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY0.VALUE=pin_low\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY1.VALUE=pin_high\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_MODE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_SETUP.VALUE=1\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRC.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_W_STROBE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHEL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001\r
+DRIVER.EMIF.VAR.EMIF_NS.VALUE=0.000000001\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TWR.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_EXTENDED_WAIT.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_WAIT.VALUE=pin0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHEL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_VAL.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_R_HOLD.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_SDRAM_PAGE_SIZE.VALUE=elements_256\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_TELEH.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_IBANK.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC2_W_STROBE.VALUE=0\r
+DRIVER.EMIF.VAR.EMIF_ASYNC1_TA.VALUE=0\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD28.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD29.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_REGION_10_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_TIMEOUT_ENABLE.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_11_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_20_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_12_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_NO_OF_REGION.VALUE=1\r
+DRIVER.POM.VAR.POM_REGION_21_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_13_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_30_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_22_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_14_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_31_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_23_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_15_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_1_ENA.VALUE=1\r
+DRIVER.POM.VAR.POM_REGION_32_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_24_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_16_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_2_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_25_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_17_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD1.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD2.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD3.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD4.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD5.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD6.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD7.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD8.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVLY_TRG_REGION.VALUE=INTERNAL_RAM\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD9.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_REGION_3_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_26_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_18_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_4_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_27_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_19_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_5_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_28_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_6_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_SIZE10.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE11.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE20.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE12.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_29_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_REGION_SIZE21.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE13.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE30.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE22.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE14.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE31.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE23.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE15.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE32.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE24.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE16.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE25.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE17.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE26.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE18.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE27.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE19.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE28.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE29.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_7_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_BASE.VALUE=0xFFA04000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD10.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD11.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD20.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD12.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD21.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD13.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_REGION_8_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_PROG_START_ADD30.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD22.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD14.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD31.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD23.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD15.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD32.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD24.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD16.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD25.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD17.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD26.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD18.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD27.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD19.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_REGION_SIZE1.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_PROG_START_ADD28.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_REGION_SIZE2.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_PROG_START_ADD29.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_REGION_SIZE3.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE4.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE5.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE6.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE7.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE8.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_SIZE9.VALUE=SIZE_64BYTES\r
+DRIVER.POM.VAR.POM_REGION_9_ENA.VALUE=0\r
+DRIVER.POM.VAR.POM_PROG_START_ADD1.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD2.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD3.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD4.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD5.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD6.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD7.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD8.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_PROG_START_ADD9.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD10.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD11.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD20.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD12.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD21.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD13.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD30.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD22.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD14.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD31.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD23.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD15.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD32.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD24.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD16.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD25.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD17.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD26.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD18.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD27.VALUE=0x00000000\r
+DRIVER.POM.VAR.POM_OVRLY_START_ADD19.VALUE=0x00000000\r
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN2_ENABLE.VALUE=0\r
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN5_ENABLE.VALUE=0\r
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN3_ENABLE.VALUE=0\r
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN3_ENABLE.VALUE=0\r
+DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN1_ENABLE.VALUE=0\r
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0\r
+DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<SETTINGS>\r
+ <DEVICE>\r
+ <family>TMS570LS31x</family>\r
+ <device>TMS570LS3137ZWT_FREERTOS</device>\r
+ <dilfile>CommandStoring.dil</dilfile>\r
+ <tools>ti</tools>\r
+ </DEVICE>\r
+ <VERSION>\r
+ <version>03.01.01</version>\r
+ </VERSION>\r
+ <HET1>\r
+ <FILENAME>\r
+ <HET1ASMHDR>\r
+ <NAME/>\r
+ </HET1ASMHDR>\r
+ <HET1ASMSRC>\r
+ <NAME/>\r
+ </HET1ASMSRC>\r
+ </FILENAME>\r
+ </HET1>\r
+ <HET2>\r
+ <FILENAME>\r
+ <HET2ASMHDR>\r
+ <NAME/>\r
+ </HET2ASMHDR>\r
+ <HET2ASMSRC>\r
+ <NAME/>\r
+ </HET2ASMSRC>\r
+ </FILENAME>\r
+ </HET2>\r
+ <SYSTEM>\r
+ <FILENAMES>\r
+ <HDRCOMMON>\r
+ <NAME>sys_common.h</NAME>\r
+ <PATH>include\sys_common.h</PATH>\r
+ </HDRCOMMON>\r
+ <HDRSYSTEM>\r
+ <NAME>system.h</NAME>\r
+ <PATH>include\system.h</PATH>\r
+ </HDRSYSTEM>\r
+ <HDRVIM>\r
+ <NAME>sys_vim.h</NAME>\r
+ <PATH>include\sys_vim.h</PATH>\r
+ </HDRVIM>\r
+ <HDRCORE>\r
+ <NAME>sys_core.h</NAME>\r
+ <PATH>include\sys_core.h</PATH>\r
+ </HDRCORE>\r
+ <HDRMPU>\r
+ <NAME>os_mpu_wrappers.h</NAME>\r
+ <PATH>include\os_mpu_wrappers.h</PATH>\r
+ </HDRMPU>\r
+ <HDRPMU>\r
+ <NAME>sys_pmu.h</NAME>\r
+ <PATH>include\sys_pmu.h</PATH>\r
+ </HDRPMU>\r
+ <SRCSTARTUP>\r
+ <NAME>sys_startup.c</NAME>\r
+ <PATH>source\sys_startup.c</PATH>\r
+ </SRCSTARTUP>\r
+ <SRCSYSTEM>\r
+ <NAME>system.c</NAME>\r
+ <PATH>source\system.c</PATH>\r
+ </SRCSYSTEM>\r
+ <SRCCORE>\r
+ <NAME>sys_core.asm</NAME>\r
+ <PATH>source\sys_core.asm</PATH>\r
+ </SRCCORE>\r
+ <SRCINTVECS>\r
+ <NAME>sys_intvecs.asm</NAME>\r
+ <PATH>source\sys_intvecs.asm</PATH>\r
+ </SRCINTVECS>\r
+ <SRCPHANTOM>\r
+ <NAME>sys_phantom.c</NAME>\r
+ <PATH>source\sys_phantom.c</PATH>\r
+ </SRCPHANTOM>\r
+ <SRCCMD>\r
+ <NAME>sys_link.cmd</NAME>\r
+ <PATH>source\sys_link.cmd</PATH>\r
+ </SRCCMD>\r
+ <SRCMAIN>\r
+ <NAME>sys_main.c</NAME>\r
+ <PATH>source\sys_main.c</PATH>\r
+ </SRCMAIN>\r
+ <SRCMPU>\r
+ <NAME>sys_mpu.asm</NAME>\r
+ <PATH>source\sys_mpu.asm</PATH>\r
+ </SRCMPU>\r
+ <SRCPMU>\r
+ <NAME>sys_pmu.asm</NAME>\r
+ <PATH>source\sys_pmu.asm</PATH>\r
+ </SRCPMU>\r
+ <HDRSLF>\r
+ <NAME>sys_selftest.h</NAME>\r
+ <PATH>include\sys_selftest.h</PATH>\r
+ </HDRSLF>\r
+ <SRCSLF>\r
+ <NAME>sys_selftest.c</NAME>\r
+ <PATH>source\sys_selftest.c</PATH>\r
+ </SRCSLF>\r
+ <SRCDABORT>\r
+ <NAME>dabort.asm</NAME>\r
+ <PATH>source\dabort.asm</PATH>\r
+ </SRCDABORT>\r
+ <SRCNOTIFY>\r
+ <NAME>notification.c</NAME>\r
+ <PATH>source\notification.c</PATH>\r
+ </SRCNOTIFY>\r
+ <HDRPROJDEFS>\r
+ <NAME>os_projdefs.h</NAME>\r
+ </HDRPROJDEFS>\r
+ <HDRCONFIG>\r
+ <NAME>FreeRTOSConfig.h</NAME>\r
+ </HDRCONFIG>\r
+ <HDRPORT>\r
+ <NAME>os_portmacro.h</NAME>\r
+ </HDRPORT>\r
+ <HDRPORTABLE>\r
+ <NAME>os_portable.h</NAME>\r
+ </HDRPORTABLE>\r
+ <HDRMAIN>\r
+ <NAME>FreeRTOS.h</NAME>\r
+ </HDRMAIN>\r
+ <HDRLIST>\r
+ <NAME>os_list.h</NAME>\r
+ </HDRLIST>\r
+ <HDRQUEUE>\r
+ <NAME>os_queue.h</NAME>\r
+ </HDRQUEUE>\r
+ <HDRSEMPHR>\r
+ <NAME>os_semphr.h</NAME>\r
+ </HDRSEMPHR>\r
+ <HDRCOROUTINE>\r
+ <NAME>os_croutine.h</NAME>\r
+ </HDRCOROUTINE>\r
+ <HDRSTACK>\r
+ <NAME>os_StackMacros.h</NAME>\r
+ </HDRSTACK>\r
+ <HDRTASK>\r
+ <NAME>os_task.h</NAME>\r
+ </HDRTASK>\r
+ <HDRTIMER>\r
+ <NAME>os_timer.h</NAME>\r
+ </HDRTIMER>\r
+ <SRCPORT>\r
+ <NAME>os_port.c</NAME>\r
+ </SRCPORT>\r
+ <SRCINCPORT>\r
+ <NAME>os_portasm.inc</NAME>\r
+ </SRCINCPORT>\r
+ <SRCASMPORT>\r
+ <NAME>os_portasm.asm</NAME>\r
+ </SRCASMPORT>\r
+ <SRCTASK>\r
+ <NAME>os_tasks.c</NAME>\r
+ </SRCTASK>\r
+ <SRCQUEUE>\r
+ <NAME>os_queue.c</NAME>\r
+ </SRCQUEUE>\r
+ <SRCLIST>\r
+ <NAME>os_list.c</NAME>\r
+ </SRCLIST>\r
+ <SRCCOROUTINE>\r
+ <NAME>os_croutine.c</NAME>\r
+ </SRCCOROUTINE>\r
+ <SRCTIMER>\r
+ <NAME>os_timer.c</NAME>\r
+ </SRCTIMER>\r
+ <SRCHEAP>\r
+ <NAME>os_heap.c</NAME>\r
+ </SRCHEAP>\r
+ <HDRMUX>\r
+ <NAME>pinmux.h</NAME>\r
+ </HDRMUX>\r
+ <SRCMUX>\r
+ <NAME>pinmux.c</NAME>\r
+ </SRCMUX>\r
+ <HDRGIO>\r
+ <NAME>gio.h</NAME>\r
+ </HDRGIO>\r
+ <SRCGIO/>\r
+ <HDRSCI>\r
+ <NAME>sci.h</NAME>\r
+ </HDRSCI>\r
+ <SRCSCI>\r
+ <NAME>sci.c</NAME>\r
+ </SRCSCI>\r
+ <HDRLIN>\r
+ <NAME>lin.h</NAME>\r
+ </HDRLIN>\r
+ <SRCLIN/>\r
+ <HDRMIBSPI>\r
+ <NAME>mibspi.h</NAME>\r
+ </HDRMIBSPI>\r
+ <SRCMIBSPI/>\r
+ <HDRSPI>\r
+ <NAME>spi.h</NAME>\r
+ </HDRSPI>\r
+ <SRCSPI/>\r
+ <HDRCAN>\r
+ <NAME>can.h</NAME>\r
+ </HDRCAN>\r
+ <SRCCAN/>\r
+ <HDRADC>\r
+ <NAME>adc.h</NAME>\r
+ </HDRADC>\r
+ <SRCADC/>\r
+ <HET1ASMHDR>\r
+ <NAME/>\r
+ </HET1ASMHDR>\r
+ <HET1ASMSRC>\r
+ <NAME/>\r
+ </HET1ASMSRC>\r
+ <STDHDRHET>\r
+ <NAME>std_nhet.h</NAME>\r
+ </STDHDRHET>\r
+ <HDRHET>\r
+ <NAME>het.h</NAME>\r
+ </HDRHET>\r
+ <HDRHTU>\r
+ <NAME>htu.h</NAME>\r
+ </HDRHTU>\r
+ <SRCHET/>\r
+ <HET2ASMHDR>\r
+ <NAME/>\r
+ </HET2ASMHDR>\r
+ <HET2ASMSRC>\r
+ <NAME/>\r
+ </HET2ASMSRC>\r
+ <HDRESM>\r
+ <NAME>esm.h</NAME>\r
+ </HDRESM>\r
+ <SRCESM>\r
+ <NAME>esm.c</NAME>\r
+ </SRCESM>\r
+ <HDRI2C>\r
+ <NAME>i2c.h</NAME>\r
+ </HDRI2C>\r
+ <SRCI2C/>\r
+ <HDR1EMAC>\r
+ <NAME>emac.h</NAME>\r
+ </HDR1EMAC>\r
+ <HDR2EMAC>\r
+ <NAME>hw_emac.h</NAME>\r
+ </HDR2EMAC>\r
+ <HDR3EMAC>\r
+ <NAME>hw_emac_ctrl.h</NAME>\r
+ </HDR3EMAC>\r
+ <HDR4EMAC>\r
+ <NAME>hw_mdio.h</NAME>\r
+ </HDR4EMAC>\r
+ <HDR5EMAC>\r
+ <NAME>hw_reg_access.h</NAME>\r
+ </HDR5EMAC>\r
+ <HDR6EMAC>\r
+ <NAME>mdio.h</NAME>\r
+ </HDR6EMAC>\r
+ <SRC1EMAC/>\r
+ <SRC2EMAC/>\r
+ <HDRDCC>\r
+ <NAME>dcc.h</NAME>\r
+ </HDRDCC>\r
+ <SRCDCC/>\r
+ <HDRRTP>\r
+ <NAME>rtp.h</NAME>\r
+ </HDRRTP>\r
+ <SRCRTP/>\r
+ <HDRDMM>\r
+ <NAME>dmm.h</NAME>\r
+ </HDRDMM>\r
+ <SRCDMM/>\r
+ <HDREMIF>\r
+ <NAME>emif.h</NAME>\r
+ </HDREMIF>\r
+ <SRCEMIF/>\r
+ <HDRPOM>\r
+ <NAME>pom.h</NAME>\r
+ </HDRPOM>\r
+ <SRCPOM/>\r
+ <HDRCRC>\r
+ <NAME>crc.h</NAME>\r
+ </HDRCRC>\r
+ <SRCCRC/>\r
+ </FILENAMES>\r
+ </SYSTEM>\r
+ <OS>\r
+ <FILENAMES>\r
+ <HDRPROJDEFS>\r
+ <PATH>include\os_projdefs.h</PATH>\r
+ </HDRPROJDEFS>\r
+ <HDRCONFIG>\r
+ <PATH>include\FreeRTOSConfig.h</PATH>\r
+ </HDRCONFIG>\r
+ <HDRPORT>\r
+ <PATH>include\os_portmacro.h</PATH>\r
+ </HDRPORT>\r
+ <HDRMPU>\r
+ <PATH>include\os_mpu_wrappers.h</PATH>\r
+ </HDRMPU>\r
+ <HDRPORTABLE>\r
+ <PATH>include\os_portable.h</PATH>\r
+ </HDRPORTABLE>\r
+ <HDRMAIN>\r
+ <PATH>include\FreeRTOS.h</PATH>\r
+ </HDRMAIN>\r
+ <HDRLIST>\r
+ <PATH>include\os_list.h</PATH>\r
+ </HDRLIST>\r
+ <HDRQUEUE>\r
+ <PATH>include\os_queue.h</PATH>\r
+ </HDRQUEUE>\r
+ <HDRSEMPHR>\r
+ <PATH>include\os_semphr.h</PATH>\r
+ </HDRSEMPHR>\r
+ <HDRCOROUTINE>\r
+ <PATH>include\os_croutine.h</PATH>\r
+ </HDRCOROUTINE>\r
+ <HDRSTACK>\r
+ <PATH>include\os_StackMacros.h</PATH>\r
+ </HDRSTACK>\r
+ <HDRTASK>\r
+ <PATH>include\os_task.h</PATH>\r
+ </HDRTASK>\r
+ <HDRTIMER>\r
+ <PATH>include\os_timer.h</PATH>\r
+ </HDRTIMER>\r
+ <SRCPORT>\r
+ <PATH>source\os_port.c</PATH>\r
+ </SRCPORT>\r
+ <SRCINCPORT>\r
+ <PATH>source\os_portasm.inc</PATH>\r
+ </SRCINCPORT>\r
+ <SRCASMPORT>\r
+ <PATH>source\os_portasm.asm</PATH>\r
+ </SRCASMPORT>\r
+ <SRCTASK>\r
+ <PATH>source\os_tasks.c</PATH>\r
+ </SRCTASK>\r
+ <SRCQUEUE>\r
+ <PATH>source\os_queue.c</PATH>\r
+ </SRCQUEUE>\r
+ <SRCLIST>\r
+ <PATH>source\os_list.c</PATH>\r
+ </SRCLIST>\r
+ <SRCCOROUTINE>\r
+ <PATH>source\os_croutine.c</PATH>\r
+ </SRCCOROUTINE>\r
+ <SRCTIMER>\r
+ <PATH>source\os_timer.c</PATH>\r
+ </SRCTIMER>\r
+ <SRCHEAP>\r
+ <PATH>source\os_heap.c</PATH>\r
+ </SRCHEAP>\r
+ </FILENAMES>\r
+ </OS>\r
+ <PINMUX>\r
+ <FILENAMES>\r
+ <HDRMUX>\r
+ <PATH>include\pinmux.h</PATH>\r
+ </HDRMUX>\r
+ <SRCMUX>\r
+ <PATH>source\pinmux.c</PATH>\r
+ </SRCMUX>\r
+ </FILENAMES>\r
+ </PINMUX>\r
+ <GIO>\r
+ <FILENAMES>\r
+ <HDRGIO>\r
+ <PATH>include\gio.h</PATH>\r
+ </HDRGIO>\r
+ <SRCGIO>\r
+ <PATH/>\r
+ </SRCGIO>\r
+ </FILENAMES>\r
+ </GIO>\r
+ <SCI>\r
+ <FILENAMES>\r
+ <HDRSCI>\r
+ <PATH>include\sci.h</PATH>\r
+ </HDRSCI>\r
+ <SRCSCI>\r
+ <PATH>source\sci.c</PATH>\r
+ </SRCSCI>\r
+ </FILENAMES>\r
+ </SCI>\r
+ <LIN>\r
+ <FILENAMES>\r
+ <HDRLIN>\r
+ <PATH>include\lin.h</PATH>\r
+ </HDRLIN>\r
+ <SRCLIN>\r
+ <PATH/>\r
+ </SRCLIN>\r
+ </FILENAMES>\r
+ </LIN>\r
+ <MIBSPI>\r
+ <FILENAMES>\r
+ <HDRMIBSPI>\r
+ <PATH>include\mibspi.h</PATH>\r
+ </HDRMIBSPI>\r
+ <SRCMIBSPI>\r
+ <PATH/>\r
+ </SRCMIBSPI>\r
+ </FILENAMES>\r
+ </MIBSPI>\r
+ <SPI>\r
+ <FILENAMES>\r
+ <HDRSPI>\r
+ <PATH>include\spi.h</PATH>\r
+ </HDRSPI>\r
+ <SRCSPI>\r
+ <PATH/>\r
+ </SRCSPI>\r
+ </FILENAMES>\r
+ </SPI>\r
+ <CAN>\r
+ <FILENAMES>\r
+ <HDRCAN>\r
+ <PATH>include\can.h</PATH>\r
+ </HDRCAN>\r
+ <SRCCAN>\r
+ <PATH/>\r
+ </SRCCAN>\r
+ </FILENAMES>\r
+ </CAN>\r
+ <ADC>\r
+ <FILENAMES>\r
+ <HDRADC>\r
+ <PATH>include\adc.h</PATH>\r
+ </HDRADC>\r
+ <SRCADC>\r
+ <PATH/>\r
+ </SRCADC>\r
+ </FILENAMES>\r
+ </ADC>\r
+ <HET>\r
+ <FILENAMES>\r
+ <STDHDRHET>\r
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+ </STDHDRHET>\r
+ <HDRHET>\r
+ <PATH>include\het.h</PATH>\r
+ </HDRHET>\r
+ <HDRHTU>\r
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+ </HDRHTU>\r
+ <SRCHET>\r
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+ </SRCHET>\r
+ </FILENAMES>\r
+ </HET>\r
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+ <FILENAMES>\r
+ <HDRESM>\r
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+ </HDRESM>\r
+ <SRCESM>\r
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+ </SRCESM>\r
+ </FILENAMES>\r
+ </ESM>\r
+ <I2C>\r
+ <FILENAMES>\r
+ <HDRI2C>\r
+ <PATH>include\i2c.h</PATH>\r
+ </HDRI2C>\r
+ <SRCI2C>\r
+ <PATH/>\r
+ </SRCI2C>\r
+ </FILENAMES>\r
+ </I2C>\r
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+ <FILENAMES>\r
+ <HDR1EMAC>\r
+ <PATH>include\emac.h</PATH>\r
+ </HDR1EMAC>\r
+ <HDR2EMAC>\r
+ <PATH>include\hw_emac.h</PATH>\r
+ </HDR2EMAC>\r
+ <HDR3EMAC>\r
+ <PATH>include\hw_emac_ctrl.h</PATH>\r
+ </HDR3EMAC>\r
+ <HDR4EMAC>\r
+ <PATH>include\hw_mdio.h</PATH>\r
+ </HDR4EMAC>\r
+ <HDR5EMAC>\r
+ <PATH>include\hw_reg_access.h</PATH>\r
+ </HDR5EMAC>\r
+ <HDR6EMAC>\r
+ <PATH>include\mdio.h</PATH>\r
+ </HDR6EMAC>\r
+ <SRC1EMAC>\r
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+ </SRC1EMAC>\r
+ <SRC2EMAC>\r
+ <PATH/>\r
+ </SRC2EMAC>\r
+ </FILENAMES>\r
+ </EMAC>\r
+ <DCC>\r
+ <FILENAMES>\r
+ <HDRDCC>\r
+ <PATH>include\dcc.h</PATH>\r
+ </HDRDCC>\r
+ <SRCDCC>\r
+ <PATH/>\r
+ </SRCDCC>\r
+ </FILENAMES>\r
+ </DCC>\r
+ <RTP>\r
+ <FILENAMES>\r
+ <HDRRTP>\r
+ <PATH>include\rtp.h</PATH>\r
+ </HDRRTP>\r
+ <SRCRTP>\r
+ <PATH/>\r
+ </SRCRTP>\r
+ </FILENAMES>\r
+ </RTP>\r
+ <DMM>\r
+ <FILENAMES>\r
+ <HDRDMM>\r
+ <PATH>include\dmm.h</PATH>\r
+ </HDRDMM>\r
+ <SRCDMM>\r
+ <PATH/>\r
+ </SRCDMM>\r
+ </FILENAMES>\r
+ </DMM>\r
+ <EMIF>\r
+ <FILENAMES>\r
+ <HDREMIF>\r
+ <PATH>include\emif.h</PATH>\r
+ </HDREMIF>\r
+ <SRCEMIF>\r
+ <PATH/>\r
+ </SRCEMIF>\r
+ </FILENAMES>\r
+ </EMIF>\r
+ <POM>\r
+ <FILENAMES>\r
+ <HDRPOM>\r
+ <PATH>include\pom.h</PATH>\r
+ </HDRPOM>\r
+ <SRCPOM>\r
+ <PATH/>\r
+ </SRCPOM>\r
+ </FILENAMES>\r
+ </POM>\r
+ <CRC>\r
+ <FILENAMES>\r
+ <HDRCRC>\r
+ <PATH>include\crc.h</PATH>\r
+ </HDRCRC>\r
+ <SRCCRC>\r
+ <PATH/>\r
+ </SRCCRC>\r
+ </FILENAMES>\r
+ </CRC>\r
+</SETTINGS>\r
--- /dev/null
+******************************************************************************
+ TMS470 Linker Unix v4.9.1
+******************************************************************************
+>> Linked Mon Aug 6 19:05:36 2012
+
+OUTPUT FILE NAME: <CmdProcTISCI.out>
+ENTRY POINT SYMBOL: "_c_int00" address: 000045e0
+
+
+MEMORY CONFIGURATION
+
+ name origin length used unused attr fill
+---------------------- -------- --------- -------- -------- ---- --------
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+ FLASH0 00000020 0017ffe0 000088fc 001776e4 R X
+ FLASH1 00180000 00180000 00000000 00180000 R X
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+ RAM 08001500 00026b00 00004238 000228c8 RW
+
+
+SEGMENT ALLOCATION MAP
+
+run origin load origin length init length attrs members
+---------- ----------- ---------- ----------- ----- -------
+00000000 00000000 00008920 00008920 r-x
+ 00000000 00000000 00000020 00000020 r-x .intvecs
+ 00000020 00000020 00008040 00008040 r-x .text
+ 00008060 00008060 000007fc 000007fc r-- .const
+ 00008860 00008860 000000c0 000000c0 r-- .cinit
+08001500 08001500 00004148 00000000 rw-
+ 08001500 08001500 00004148 00000000 rw- .bss
+08005648 08005648 000000f0 000000f0 rw-
+ 08005648 08005648 000000f0 000000f0 rw- .data
+
+
+SECTION ALLOCATION MAP
+
+ output attributes/
+section page origin length input sections
+-------- ---- ---------- ---------- ----------------
+.intvecs 0 00000000 00000020
+ 00000000 00000020 sys_intvecs.obj (.intvecs)
+
+.text 0 00000020 00008040
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+ 000014e8 00001460 os_tasks.obj (.text)
+ 00002948 00000b48 os_queue.obj (.text)
+ 00003490 00000b18 cmd_proc.obj (.text)
+ 00003fa8 00000638 os_port.obj (.text)
+ 000045e0 000005a8 sys_startup.obj (.text:retain)
+ 00004b88 00000520 sci.obj (.text)
+ 000050a8 0000046c cmdio_tisci.obj (.text)
+ 00005514 0000043c esm.obj (.text)
+ 00005950 000003cc cmd_io_line.obj (.text)
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+ 000063f4 00000348 sci.obj (.text:retain)
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+ 00006d44 000002b8 i2str.obj (.text)
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+ 0000745c 000001d4 cmd_io.obj (.text)
+ 00007630 0000016c os_portasm.obj (.text)
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+ 000078ec 00000120 cmd_proc_freertos_tms570.obj (.text)
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+ 00007af4 000000c0 dabort.obj (.text)
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+ 00007c50 00000078 : memset_t2.obj (.text)
+ 00007cc8 00000068 notification.obj (.text)
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+ 00007e34 00000050 : atol.obj (.text)
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+ 00007f18 00000044 rtsv7R4_T_be_v3D16_eabi.lib : exit.obj (.text)
+ 00007f5c 00000030 : strncpy.obj (.text)
+ 00007f8c 00000026 : strncmp.obj (.text)
+ 00007fb2 00000002 --HOLE-- [fill = 0]
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+ 00007fcc 00000016 : strchr.obj (.text)
+ 00007fe2 00000014 : strlen.obj (.text)
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+ 00008008 00000010 : isalnum.obj (.text)
+ 00008018 00000010 : isdigit.obj (.text)
+ 00008028 00000010 : isspace.obj (.text)
+ 00008038 00000010 : strcpy.obj (.text)
+ 00008048 0000000e : copy_decompress_none.obj (.text:decompress:none)
+ 00008056 00000006 : copy_decompress_rle.obj (.text:decompress:rle24)
+ 0000805c 00000004 sys_phantom.obj (.text:retain)
+
+.const 0 00008060 000007fc
+ 00008060 00000304 commands.obj (.const:.string)
+ 00008364 00000204 sys_startup.obj (.const:s_vim_init)
+ 00008568 00000187 commands.obj (.const)
+ 000086ef 00000001 --HOLE-- [fill = 0]
+ 000086f0 00000101 rtsv7R4_T_be_v3D16_eabi.lib : ctype.obj (.const:_ctypes_)
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+ 0000881a 00000002 --HOLE-- [fill = 0]
+ 0000881c 00000023 commands.obj (.const:$P$T1$2)
+ 0000883f 00000001 --HOLE-- [fill = 0]
+ 00008840 0000001c cmdio_std_line.obj (.const)
+
+.cinit 0 00008860 000000c0
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+ 000088f9 00000003 --HOLE-- [fill = 0]
+ 000088fc 0000000c (__TI_handler_table)
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+
+.bss 0 08001500 00004148 UNINITIALIZED
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+ 080055b0 00000054 cmdio_std_line.obj (.bss:ed_line_out_std)
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+ 0800563c 00000008 cmd_proc_freertos_tms570.obj (.bss)
+ 08005644 00000004 commands.obj (.bss)
+
+.data 0 08005648 000000f0
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+ 080056d4 00000030 os_tasks.obj (.data)
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+ 08005728 00000008 : exit.obj (.data)
+ 08005730 00000004 os_heap.obj (.data)
+ 08005734 00000004 os_port.obj (.data)
+
+
+LINKER GENERATED COPY TABLES
+
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+ .data: load addr=00008860, load size=00000099 bytes, run addr=08005648, run size=000000f0 bytes, compression=rle
+ .bss: load addr=00008908, load size=00000008 bytes, run addr=08001500, run size=00004148 bytes, compression=zero_init
+
+
+LINKER GENERATED HANDLER TABLE
+
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+ index: 0, handler: __TI_zero_init
+ index: 1, handler: __TI_decompress_rle24
+ index: 2, handler: __TI_decompress_none
+
+
+GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
+
+address name
+-------- ----
+00007f19 C$$EXIT
+00008910 __TI_CINIT_Base
+00008920 __TI_CINIT_Limit
+000088fc __TI_Handler_Table_Base
+00008908 __TI_Handler_Table_Limit
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+00005f18 _coreDisableFlashEcc_
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+00005ecc _coreEnableRamEcc_
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+00005f80 _coreGetDataFaultAddress_
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+00005f9c _coreGetInstructionFaultAddress_
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+00005d1c _coreInitRegisters_
+00005e1c _coreInitStackPointer_
+000086f0 _ctypes_
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+00006010 _esmCcmErrorsClear_
+00005e68 _getCPSRValue_
+00005e70 _gotoCPUIdle_
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+00007fbb _register_lock
+00007fb5 _register_unlock
+08005724 _unlock
+00007f1d abort
+00000e28 adc1ParityCheck
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+00007de5 atoi
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+00005330 buf_getc
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+000053a0 buf_write
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+00000854 checkB0RAMECC
+00000978 checkB1RAMECC
+00000a98 checkFlashECC
+000006d8 checkefcSelfTest
+0000527c clearBuffer
+0000525c clearInputBuffer
+0000526c clearOutputBuffer
+00008688 cmd_des_char
+000086a0 cmd_des_charmid
+000085f8 cmd_des_error
+00008568 cmd_des_help
+000086b8 cmd_des_hiddedn
+00008670 cmd_des_num
+000085c8 cmd_des_opchar_test
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+00008610 cmd_des_param
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+00008580 cmd_des_val
+00008598 cmd_des_valro
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+00003da0 cmd_do_help
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+00003c78 cmd_do_rw_long
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+00003ab4 cmd_do_stamp
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+00006348 cmd_do_testcmdio
+000062e4 cmd_do_testerror
+000060a0 cmd_do_testopchar
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+000059c0 cmd_ed_line_buf
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+00005bf0 cmd_io_line_in
+00005af8 cmd_io_line_out
+00005ad8 cmd_io_line_putc
+00005cc8 cmd_io_line_rdline
+000074a0 cmd_io_puts
+000075ac cmd_io_read_bychar
+00008840 cmd_io_std_line
+00007534 cmd_io_write_bychar
+080056a0 cmd_list
+08005648 cmd_list_1
+08005660 cmd_list_2
+08005680 cmd_list_main
+000039e4 cmd_num_suffix
+00003968 cmd_opchar_check
+00003d18 cmd_opchar_replong
+000077d8 cmd_processor_run
+00007e85 copy_in
+00000224 cpuSelfTest
+00000b68 cpuSelfTestFail
+00000b60 custom_dabort
+00000be0 dmaParityCheck
+080056a4 ed_line_buf_in_std
+080056bc ed_line_buf_out_std
+0800555c ed_line_in_std
+080055b0 ed_line_out_std
+000005a0 efcCheck
+00000770 efcClass1Error
+00000774 efcClass2Error
+000006b0 efcSelfTest
+000005fc efcStuckZeroTest
+000056c4 esmActivateNormalOperation
+000057b0 esmClearStatus
+000057f0 esmClearStatusBuffer
+00005688 esmDisableError
+00005700 esmDisableInterrupt
+0000565c esmEnableError
+000056d4 esmEnableInterrupt
+00005640 esmError
+0000583c esmGetStatus
+000058a0 esmGetStatusBuffer
+00007cc8 esmGroup1Notification
+00007cd4 esmGroup2Notification
+0000723c esmHighInterrupt
+00005514 esmInit
+00007380 esmLowInterrupt
+0000581c esmSetCounterPreloadValue
+0000572c esmSetInterruptLevel
+000056b4 esmTriggerErrorPinReset
+00007f25 exit
+00000b58 flashClass1Error
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+00000778 fmcBus2Check
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+000007b4 fmcECCcheck
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+00000cbc htu1ParityCheck
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+00006d44 i2str
+08005630 inBuffer
+000078ec initCmdProc
+000050a8 initIoBuffer
+00008009 isalnum
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+000021e4 xTaskRemoveFromEventList
+00001d08 xTaskResumeAll
+
+
+GLOBAL SYMBOLS: SORTED BY Symbol Address
+
+address name
+-------- ----
+00000000 __TI_static_base__
+00000020 ccmSelfCheck
+00000104 ccmFail
+00000138 _memoryInit_
+0000017c stcSelfCheck
+00000224 cpuSelfTest
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+00000f00 can1ParityCheck
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+00001010 can3ParityCheck
+000010a4 mibspi1ParityCheck
+0000118c mibspi3ParityCheck
+00001284 mibspi5ParityCheck
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+000026ec xTaskGetCurrentTaskHandle
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+000039e4 cmd_num_suffix
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+000050a8 initIoBuffer
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+00005158 readFromOutputBuffer
+00005178 readFromInputBuffer
+00005198 read
+000051d4 print
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+000057b0 esmClearStatus
+000057f0 esmClearStatusBuffer
+0000581c esmSetCounterPreloadValue
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+000059c0 cmd_ed_line_buf
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+00005e68 _getCPSRValue_
+00005e70 _gotoCPUIdle_
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+00006000 _disable_IRQ_interrupt_
+00006008 _enable_interrupt_
+00006010 _esmCcmErrorsClear_
+00006098 __TI_PINIT_Base
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+000060a0 cmd_do_testopchar
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+00007070 vListInsertEnd
+000070f4 vListInsert
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+0000723c esmHighInterrupt
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+000074a0 cmd_io_puts
+00007534 cmd_io_write_bychar
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+00007630 vPortStartFirstTask
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+00007f1d abort
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+00008049 __TI_decompress_none
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+00008568 cmd_des_help
+00008580 cmd_des_val
+00008598 cmd_des_valro
+000085b0 cmd_des_valwo
+000085c8 cmd_des_opchar_test
+000085e0 cmd_des_testio
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+00008610 cmd_des_param
+00008628 cmd_des_opchar_testro
+00008640 cmd_des_test
+00008658 cmd_des_prefix
+00008670 cmd_des_num
+00008688 cmd_des_char
+000086a0 cmd_des_charmid
+000086b8 cmd_des_hiddedn
+000086f0 _ctypes_
+00008840 cmd_io_std_line
+000088fc __TI_Handler_Table_Base
+00008908 __TI_Handler_Table_Limit
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+00008920 __TI_CINIT_Limit
+0800555c ed_line_in_std
+080055b0 ed_line_out_std
+08005604 g_sciTransfer
+08005624 outBuffer
+08005630 inBuffer
+0800563c processCmdHandler
+08005640 prompt
+08005644 val
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+08005660 cmd_list_2
+08005680 cmd_list_main
+080056a0 cmd_list
+080056a4 ed_line_buf_in_std
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+080056d4 pxCurrentTCB
+08005704 cmd_io_buf
+08005720 _lock
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+08005728 _cleanup_ptr
+0800572c _dtors_ptr
+08005734 ulCriticalNesting
+ffffffff __binit__
+ffffffff __c_args__
+ffffffff binit
+
+[302 symbols]
--- /dev/null
+******************************************************************************
+ TMS470 Linker Unix v4.9.1
+******************************************************************************
+>> Linked Thu Aug 2 12:22:39 2012
+
+OUTPUT FILE NAME: <CommandProcessing.out>
+ENTRY POINT SYMBOL: "_c_int00" address: 000045e0
+
+
+MEMORY CONFIGURATION
+
+ name origin length used unused attr fill
+---------------------- -------- --------- -------- -------- ---- --------
+ VECTORS 00000000 00000020 00000020 00000000 X
+ FLASH0 00000020 0017ffe0 00008c28 001773b8 R X
+ FLASH1 00180000 00180000 00000000 00180000 R X
+ STACKS 08000000 00001500 00000000 00001500 RW
+ RAM 08001500 00026b00 00004258 000228a8 RW
+
+
+SEGMENT ALLOCATION MAP
+
+run origin load origin length init length attrs members
+---------- ----------- ---------- ----------- ----- -------
+00000000 00000000 00008c48 00008c48 r-x
+ 00000000 00000000 00000020 00000020 r-x .intvecs
+ 00000020 00000020 00008354 00008354 r-x .text
+ 00008374 00008374 000007fc 000007fc r-- .const
+ 00008b70 00008b70 000000d8 000000d8 r-- .cinit
+08001500 08001500 0000414c 00000000 rw-
+ 08001500 08001500 0000414c 00000000 rw- .bss
+0800564c 0800564c 0000010c 0000010c rw-
+ 0800564c 0800564c 0000010c 0000010c rw- .data
+
+
+SECTION ALLOCATION MAP
+
+ output attributes/
+section page origin length input sections
+-------- ---- ---------- ---------- ----------------
+.intvecs 0 00000000 00000020
+ 00000000 00000020 sys_intvecs.obj (.intvecs)
+
+.text 0 00000020 00008354
+ 00000020 000014c8 sys_selftest.obj (.text)
+ 000014e8 00001460 os_tasks.obj (.text)
+ 00002948 00000b48 os_queue.obj (.text)
+ 00003490 00000b18 cmd_proc.obj (.text)
+ 00003fa8 00000638 os_port.obj (.text)
+ 000045e0 000005a8 sys_startup.obj (.text:retain)
+ 00004b88 00000590 sci.obj (.text)
+ 00005118 0000044c cmdio_buffer.obj (.text)
+ 00005564 0000043c esm.obj (.text)
+ 000059a0 000003cc cmd_io_line.obj (.text)
+ 00005d6c 00000388 sci.obj (.text:retain)
+ 000060f4 00000384 sys_core.obj (.text)
+ 00006478 00000368 cmd_proc_freertos_tms570.obj (.text)
+ 000067e0 00000354 commands.obj (.text)
+ 00006b34 00000308 system.obj (.text)
+ 00006e3c 00000300 pinmux.obj (.text)
+ 0000713c 000002b8 i2str.obj (.text)
+ 000073f4 00000240 os_list.obj (.text)
+ 00007634 00000220 esm.obj (.text:retain)
+ 00007854 000001d4 cmd_io.obj (.text)
+ 00007a28 0000016c os_portasm.obj (.text)
+ 00007b94 00000150 cmd_proc_run.obj (.text)
+ 00007ce4 000000e8 os_heap.obj (.text)
+ 00007dcc 000000c0 dabort.obj (.text)
+ 00007e8c 0000009c rtsv7R4_T_be_v3D16_eabi.lib : memcpy_t2.obj (.text)
+ 00007f28 00000098 notification.obj (.text)
+ 00007fc0 00000078 rtsv7R4_T_be_v3D16_eabi.lib : memset_t2.obj (.text)
+ 00008038 00000060 : copy_decompress_rle.obj (.text)
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+ 00008190 00000050 : atol.obj (.text)
+ 000081e0 0000004c : cpy_tbl.obj (.text)
+ 0000822c 00000044 : exit.obj (.text)
+ 00008270 00000030 : strncpy.obj (.text)
+ 000082a0 00000026 : strncmp.obj (.text)
+ 000082c6 00000002 --HOLE-- [fill = 0]
+ 000082c8 00000018 : _lock.obj (.text)
+ 000082e0 00000016 : strchr.obj (.text)
+ 000082f6 00000014 : strlen.obj (.text)
+ 0000830a 00000012 : copy_zero_init.obj (.text:decompress:ZI)
+ 0000831c 00000010 : isalnum.obj (.text)
+ 0000832c 00000010 : isdigit.obj (.text)
+ 0000833c 00000010 : isspace.obj (.text)
+ 0000834c 00000010 : strcpy.obj (.text)
+ 0000835c 0000000e : copy_decompress_none.obj (.text:decompress:none)
+ 0000836a 00000006 : copy_decompress_rle.obj (.text:decompress:rle24)
+ 00008370 00000004 sys_phantom.obj (.text:retain)
+
+.const 0 00008374 000007fc
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+ 00008678 00000204 sys_startup.obj (.const:s_vim_init)
+ 0000887c 00000187 commands.obj (.const)
+ 00008a03 00000001 --HOLE-- [fill = 0]
+ 00008a04 00000101 rtsv7R4_T_be_v3D16_eabi.lib : ctype.obj (.const:_ctypes_)
+ 00008b05 00000003 --HOLE-- [fill = 0]
+ 00008b08 00000026 commands.obj (.const:$P$T0$1)
+ 00008b2e 00000002 --HOLE-- [fill = 0]
+ 00008b30 00000023 commands.obj (.const:$P$T1$2)
+ 00008b53 00000001 --HOLE-- [fill = 0]
+ 00008b54 0000001c cmdio_std_line.obj (.const)
+
+.cinit 0 00008b70 000000d8
+ 00008b70 000000b4 (.cinit..data.load) [load image, compression = rle]
+ 00008c24 0000000c (__TI_handler_table)
+ 00008c30 00000008 (.cinit..bss.load) [load image, compression = zero_init]
+ 00008c38 00000010 (__TI_cinit_table)
+
+.bss 0 08001500 0000414c UNINITIALIZED
+ 08001500 00003fa0 os_heap.obj (.bss:xHeap)
+ 080054a0 00000064 os_tasks.obj (.bss:pxReadyTasksLists)
+ 08005504 00000058 os_tasks.obj (.bss)
+ 0800555c 00000054 cmdio_std_line.obj (.bss:ed_line_in_std)
+ 080055b0 00000054 cmdio_std_line.obj (.bss:ed_line_out_std)
+ 08005604 0000001c cmd_proc_freertos_tms570.obj (.bss)
+ 08005620 00000018 sci.obj (.bss)
+ 08005638 00000010 cmdio_buffer.obj (.bss)
+ 08005648 00000004 commands.obj (.bss)
+
+.data 0 0800564c 0000010c
+ 0800564c 0000005c commands.obj (.data)
+ 080056a8 00000030 cmdio_std_line.obj (.data)
+ 080056d8 00000030 os_tasks.obj (.data)
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+ 0800573d 00000003 --HOLE--
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+ 08005748 00000008 : exit.obj (.data)
+ 08005750 00000004 os_heap.obj (.data)
+ 08005754 00000004 os_port.obj (.data)
+
+
+LINKER GENERATED COPY TABLES
+
+__TI_cinit_table @ 00008c38 records: 2, size/record: 8, table size: 16
+ .data: load addr=00008b70, load size=000000b4 bytes, run addr=0800564c, run size=0000010c bytes, compression=rle
+ .bss: load addr=00008c30, load size=00000008 bytes, run addr=08001500, run size=0000414c bytes, compression=zero_init
+
+
+LINKER GENERATED HANDLER TABLE
+
+__TI_handler_table @ 00008c24 records: 3, size/record: 4, table size: 12
+ index: 0, handler: __TI_zero_init
+ index: 1, handler: __TI_decompress_rle24
+ index: 2, handler: __TI_decompress_none
+
+
+GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
+
+address name
+-------- ----
+0000822d C$$EXIT
+00008c38 __TI_CINIT_Base
+00008c48 __TI_CINIT_Limit
+00008c24 __TI_Handler_Table_Base
+00008c30 __TI_Handler_Table_Limit
+00006470 __TI_PINIT_Base
+00006474 __TI_PINIT_Limit
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+00007fc3 __aeabi_memset8
+00008098 __aeabi_uidivmod
+ffffffff __binit__
+ffffffff __c_args__
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+08005748 _cleanup_ptr
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+00006328 _coreClearDataFault_
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+00006344 _coreClearInstructionFault_
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+000062f0 _coreDisableFlashEcc_
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+000062d4 _coreEnableFlashEcc_
+00006308 _coreEnableIrqVicOffset_
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+0000625c _coreEnableVfp_
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+00006358 _coreGetDataFaultAddress_
+00006320 _coreGetDataFault_
+00006374 _coreGetInstructionFaultAddress_
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+0800574c _dtors_ptr
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+000063e8 _esmCcmErrorsClear_
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+000073f4 vListInitialise
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+00002170 vTaskPlaceOnEventList
+00002860 vTaskPriorityDisinherit
+0000275c vTaskPriorityInherit
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+00001a2c vTaskSuspend
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+08005648 val
+00000b6c vimParityCheck
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+00002dc4 xQueueGenericReceive
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+00003458 xQueueIsQueueFullFromISR
+00002ff0 xQueueReceiveFromISR
+000022ec xTaskCheckForTimeOut
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+000026ec xTaskGetCurrentTaskHandle
+0000270c xTaskGetSchedulerState
+00001e78 xTaskGetTickCount
+00001e98 xTaskGetTickCountFromISR
+00001b04 xTaskIsTaskSuspended
+000021e4 xTaskRemoveFromEventList
+00001d08 xTaskResumeAll
+
+
+GLOBAL SYMBOLS: SORTED BY Symbol Address
+
+address name
+-------- ----
+00000000 __TI_static_base__
+00000020 ccmSelfCheck
+00000104 ccmFail
+00000138 _memoryInit_
+0000017c stcSelfCheck
+00000224 cpuSelfTest
+000002a4 pbistSelfCheck
+000003e0 pbistSelfCheckFail
+000003e4 pbistRun
+000004bc pbistStop
+000004ec pbistIsTestCompleted
+00000508 pbistIsTestPassed
+00000544 pbistPortTestStatus
+000005a0 efcCheck
+000005fc efcStuckZeroTest
+000006b0 efcSelfTest
+000006d8 checkefcSelfTest
+00000770 efcClass1Error
+00000774 efcClass2Error
+00000778 fmcBus2Check
+000007b4 fmcECCcheck
+0000084c fmcClass1Error
+00000850 fmcClass2Error
+00000854 checkB0RAMECC
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+00000a90 tcramClass1Error
+00000a94 tcramClass2Error
+00000a98 checkFlashECC
+00000b58 flashClass1Error
+00000b5c flashClass2Error
+00000b60 custom_dabort
+00000b64 stcSelfCheckFail
+00000b68 cpuSelfTestFail
+00000b6c vimParityCheck
+00000be0 dmaParityCheck
+00000c54 het1ParityCheck
+00000cbc htu1ParityCheck
+00000d30 het2ParityCheck
+00000db4 htu2ParityCheck
+00000e28 adc1ParityCheck
+00000e94 adc2ParityCheck
+00000f00 can1ParityCheck
+00000f80 can2ParityCheck
+00001010 can3ParityCheck
+000010a4 mibspi1ParityCheck
+0000118c mibspi3ParityCheck
+00001284 mibspi5ParityCheck
+000014e8 xTaskGenericCreate
+000016e8 vTaskDelayUntil
+000017e4 vTaskDelay
+0000184c uxTaskPriorityGet
+00001890 vTaskPrioritySet
+00001a2c vTaskSuspend
+00001b04 xTaskIsTaskSuspended
+00001b98 vTaskResume
+00001c5c vTaskStartScheduler
+00001cd8 vTaskEndScheduler
+00001cf4 vTaskSuspendAll
+00001d08 xTaskResumeAll
+00001e78 xTaskGetTickCount
+00001e98 xTaskGetTickCountFromISR
+00001ebc uxTaskGetNumberOfTasks
+00001ed0 vTaskIncrementTick
+000020a8 vTaskSwitchContext
+00002170 vTaskPlaceOnEventList
+000021e4 xTaskRemoveFromEventList
+000022bc vTaskSetTimeOutState
+000022ec xTaskCheckForTimeOut
+000023c4 vTaskMissedYield
+0000269c uxTaskGetStackHighWaterMark
+000026ec xTaskGetCurrentTaskHandle
+0000270c xTaskGetSchedulerState
+0000275c vTaskPriorityInherit
+00002860 vTaskPriorityDisinherit
+00002948 xQueueCreate
+00002a78 xQueueCreateMutex
+00002b34 xQueueCreateCountingSemaphore
+00002b70 xQueueGenericSend
+00002cf8 xQueueGenericSendFromISR
+00002dc4 xQueueGenericReceive
+00002ff0 xQueueReceiveFromISR
+000030bc uxQueueMessagesWaiting
+000030e0 uxQueueMessagesWaitingFromISR
+00003100 vQueueDelete
+000033ec xQueueIsQueueEmptyFromISR
+00003458 xQueueIsQueueFullFromISR
+00003510 skip_white
+00003544 proc_cmd_line
+00003968 cmd_opchar_check
+000039e4 cmd_num_suffix
+00003ab4 cmd_do_stamp
+00003b38 cmd_do_rw_short
+00003bd8 cmd_do_rw_int
+00003c78 cmd_do_rw_long
+00003d18 cmd_opchar_replong
+00003da0 cmd_do_help
+00003fa8 pxPortInitialiseStack
+00004488 xPortStartScheduler
+0000449c vPortEndScheduler
+000044a0 vPortEnterCritical
+000044b8 vPortExitCritical
+000045e0 _c_int00
+00004b88 sciInit
+00004c5c sciSetFunctional
+00004c7c sciSetBaudrate
+00004cfc sciIsTxReady
+00004d18 sciSendByte
+00004d48 sciSend
+00004e5c sciIsRxReady
+00004e78 sciRxError
+00004ea8 sciReceiveByte
+00004ed0 sciReceive
+00004fa8 sciEnableLoopback
+00004fdc sciDisableLoopback
+00004ff8 sciEnableNotification
+00005068 sciDisableNotification
+00005118 initIoBuffer
+00005160 printToOutputBuffer
+00005188 printToInputBuffer
+000051b0 readFromOutputBuffer
+000051d0 readFromInputBuffer
+000051f0 read
+0000522c print
+000052b4 clearInputBuffer
+000052c4 clearOutputBuffer
+000052d4 clearBuffer
+00005300 buf_putc
+00005388 buf_getc
+000053f8 buf_write
+000054a0 buf_read
+00005564 esmInit
+00005690 esmError
+000056ac esmEnableError
+000056d8 esmDisableError
+00005704 esmTriggerErrorPinReset
+00005714 esmActivateNormalOperation
+00005724 esmEnableInterrupt
+00005750 esmDisableInterrupt
+0000577c esmSetInterruptLevel
+00005800 esmClearStatus
+00005840 esmClearStatusBuffer
+0000586c esmSetCounterPreloadValue
+0000588c esmGetStatus
+000058f0 esmGetStatusBuffer
+00005a10 cmd_ed_line_buf
+00005b28 cmd_io_line_putc
+00005b48 cmd_io_line_out
+00005c40 cmd_io_line_in
+00005d18 cmd_io_line_rdline
+00005d6c sciHighLevelInterrupt
+00005f18 sciLowLevelInterrupt
+000060f4 _coreInitRegisters_
+000061f4 _coreInitStackPointer_
+00006240 _getCPSRValue_
+00006248 _gotoCPUIdle_
+0000625c _coreEnableVfp_
+00006274 _coreEnableEventBusExport_
+0000628c _coreDisableEventBusExport_
+000062a4 _coreEnableRamEcc_
+000062bc _coreDisableRamEcc_
+000062d4 _coreEnableFlashEcc_
+000062f0 _coreDisableFlashEcc_
+00006308 _coreEnableIrqVicOffset_
+00006320 _coreGetDataFault_
+00006328 _coreClearDataFault_
+0000633c _coreGetInstructionFault_
+00006344 _coreClearInstructionFault_
+00006358 _coreGetDataFaultAddress_
+00006360 _coreClearDataFaultAddress_
+00006374 _coreGetInstructionFaultAddress_
+0000637c _coreClearInstructionFaultAddress_
+00006390 _coreGetAuxiliaryDataFault_
+00006398 _coreClearAuxiliaryDataFault_
+000063ac _coreGetAuxiliaryInstructionFault_
+000063b4 _coreClearAuxiliaryInstructionFault_
+000063c8 _disable_interrupt_
+000063d0 _disable_FIQ_interrupt_
+000063d8 _disable_IRQ_interrupt_
+000063e0 _enable_interrupt_
+000063e8 _esmCcmErrorsClear_
+00006470 __TI_PINIT_Base
+00006474 __TI_PINIT_Limit
+00006478 initCmdProc
+000065d8 processCmd
+00006628 storeCmd
+00006748 printTask
+000067e0 cmd_do_testopchar
+0000694c cmd_do_testparam
+00006a24 cmd_do_testerror
+00006a40 cmd_do_test
+00006a88 cmd_do_testcmdio
+00006b34 setupPLL
+00006b68 trimLPO
+00006bb0 setupFlash
+00006bf0 periphInit
+00006c48 mapClocks
+00006d20 systemInit
+00006dac systemPowerDown
+00006e3c muxInit
+0000713c i2str
+000073f4 vListInitialise
+0000744c vListInitialiseItem
+00007468 vListInsertEnd
+000074ec vListInsert
+000075b0 vListRemove
+00007634 esmHighInterrupt
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+00007898 cmd_io_puts
+0000792c cmd_io_write_bychar
+000079a4 cmd_io_read_bychar
+00007a28 vPortStartFirstTask
+00007a5c vPortYieldProcessor
+00007ae4 vPreemptiveTick
+00007b80 vPortYield
+00007bd0 cmd_processor_run
+00007ce4 pvPortMalloc
+00007d8c vPortFree
+00007d9c vPortInitialiseBlocks
+00007dac xPortGetFreeHeapSize
+00007dcc _dabort
+00007e8d __aeabi_memcpy
+00007e8d __aeabi_memcpy4
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+00007e8d memcpy
+00007f28 esmGroup1Notification
+00007f34 esmGroup2Notification
+00007f40 memoryPort0TestFailNotification
+00007f58 memoryPort1TestFailNotification
+00007f70 sciNotification
+00007fc1 __aeabi_memclr
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+00007fc3 __aeabi_memset4
+00007fc3 __aeabi_memset8
+00007fc9 memset
+00008098 __aeabi_uidivmod
+000080ec main
+00008141 atoi
+00008191 atol
+000081e1 copy_in
+0000822d C$$EXIT
+00008231 abort
+00008239 exit
+00008271 strncpy
+000082a1 strncmp
+000082c9 _register_unlock
+000082cf _register_lock
+000082d5 _nop
+000082e1 strchr
+000082f7 strlen
+0000830b __TI_zero_init
+0000831d isalnum
+0000832d isdigit
+0000833d isspace
+0000834d strcpy
+0000835d __TI_decompress_none
+0000836b __TI_decompress_rle24
+00008370 phantomInterrupt
+0000887c cmd_des_help
+00008894 cmd_des_val
+000088ac cmd_des_valro
+000088c4 cmd_des_valwo
+000088dc cmd_des_opchar_test
+000088f4 cmd_des_testio
+0000890c cmd_des_error
+00008924 cmd_des_param
+0000893c cmd_des_opchar_testro
+00008954 cmd_des_test
+0000896c cmd_des_prefix
+00008984 cmd_des_num
+0000899c cmd_des_char
+000089b4 cmd_des_charmid
+000089cc cmd_des_hiddedn
+00008a04 _ctypes_
+00008b54 cmd_io_std_line
+00008c24 __TI_Handler_Table_Base
+00008c30 __TI_Handler_Table_Limit
+00008c38 __TI_CINIT_Base
+00008c48 __TI_CINIT_Limit
+0800555c ed_line_in_std
+080055b0 ed_line_out_std
+08005604 inputCharacterQueue
+08005608 processCmdSem
+0800560c storeCmdHandler
+08005610 printBufferHandler
+08005614 processCmdHandler
+08005618 character
+0800561c prompt
+08005620 g_sciTransfer
+08005638 outBuffer
+08005640 inBuffer
+08005648 val
+0800564c cmd_list_1
+08005664 cmd_list_2
+08005684 cmd_list_main
+080056a4 cmd_list
+080056a8 ed_line_buf_in_std
+080056c0 ed_line_buf_out_std
+080056d8 pxCurrentTCB
+08005708 cmd_io_buf
+08005724 cmdLenErr
+08005740 _lock
+08005744 _unlock
+08005748 _cleanup_ptr
+0800574c _dtors_ptr
+08005754 ulCriticalNesting
+ffffffff __binit__
+ffffffff __c_args__
+ffffffff binit
+
+[310 symbols]
--- /dev/null
+"../CommandProcessing/Debug/ccsObjs.opt"
\ No newline at end of file
--- /dev/null
+"../CommandProcessing/Debug/source/ccsSrcs.opt"
\ No newline at end of file
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Each subdirectory must supply rules for building sources it contributes
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+OBJ_SRCS += \
+../CommandProcessing/Debug/source/cmd_io.obj \
+../CommandProcessing/Debug/source/cmd_io_line.obj \
+../CommandProcessing/Debug/source/cmd_proc.obj \
+../CommandProcessing/Debug/source/cmd_proc_freertos_tms570.obj \
+../CommandProcessing/Debug/source/cmd_proc_run.obj \
+../CommandProcessing/Debug/source/cmdio_buffer.obj \
+../CommandProcessing/Debug/source/cmdio_std_line.obj \
+../CommandProcessing/Debug/source/commands.obj \
+../CommandProcessing/Debug/source/dabort.obj \
+../CommandProcessing/Debug/source/esm.obj \
+../CommandProcessing/Debug/source/i2str.obj \
+../CommandProcessing/Debug/source/notification.obj \
+../CommandProcessing/Debug/source/os_croutine.obj \
+../CommandProcessing/Debug/source/os_heap.obj \
+../CommandProcessing/Debug/source/os_list.obj \
+../CommandProcessing/Debug/source/os_port.obj \
+../CommandProcessing/Debug/source/os_portasm.obj \
+../CommandProcessing/Debug/source/os_queue.obj \
+../CommandProcessing/Debug/source/os_tasks.obj \
+../CommandProcessing/Debug/source/os_timer.obj \
+../CommandProcessing/Debug/source/pinmux.obj \
+../CommandProcessing/Debug/source/sci.obj \
+../CommandProcessing/Debug/source/sys_core.obj \
+../CommandProcessing/Debug/source/sys_intvecs.obj \
+../CommandProcessing/Debug/source/sys_main.obj \
+../CommandProcessing/Debug/source/sys_mpu.obj \
+../CommandProcessing/Debug/source/sys_phantom.obj \
+../CommandProcessing/Debug/source/sys_pmu.obj \
+../CommandProcessing/Debug/source/sys_selftest.obj \
+../CommandProcessing/Debug/source/sys_startup.obj \
+../CommandProcessing/Debug/source/system.obj
+
+OPT_SRCS += \
+../CommandProcessing/Debug/source/ccsSrcs.opt
+
+OPT_SRCS__QUOTED += \
+"../CommandProcessing/Debug/source/ccsSrcs.opt"
+
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Each subdirectory must supply rules for building sources it contributes
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+OPT_SRCS += \
+../CommandProcessing/Debug/ccsObjs.opt
+
+OPT_SRCS__QUOTED += \
+"../CommandProcessing/Debug/ccsObjs.opt"
+
+
--- /dev/null
+"../CommandProcessing/source/cmd_io.c" "../CommandProcessing/source/cmd_io_line.c" "../CommandProcessing/source/cmd_proc.c" "../CommandProcessing/source/cmd_proc_freertos_tms570.c" "../CommandProcessing/source/cmd_proc_run.c" "../CommandProcessing/source/cmdio_buffer.c" "../CommandProcessing/source/cmdio_std_line.c" "../CommandProcessing/source/commands.c" "../CommandProcessing/source/dabort.asm" "../CommandProcessing/source/esm.c" "../CommandProcessing/source/i2str.c" "../CommandProcessing/source/notification.c" "../CommandProcessing/source/os_croutine.c" "../CommandProcessing/source/os_heap.c" "../CommandProcessing/source/os_list.c" "../CommandProcessing/source/os_port.c" "../CommandProcessing/source/os_portasm.asm" "../CommandProcessing/source/os_queue.c" "../CommandProcessing/source/os_tasks.c" "../CommandProcessing/source/os_timer.c" "../CommandProcessing/source/pinmux.c" "../CommandProcessing/source/sci.c" "../CommandProcessing/source/sys_core.asm" "../CommandProcessing/source/sys_intvecs.asm" "../CommandProcessing/source/sys_main.c" "../CommandProcessing/source/sys_mpu.asm" "../CommandProcessing/source/sys_phantom.c" "../CommandProcessing/source/sys_pmu.asm" "../CommandProcessing/source/sys_selftest.c" "../CommandProcessing/source/sys_startup.c" "../CommandProcessing/source/system.c"
\ No newline at end of file
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Each subdirectory must supply rules for building sources it contributes
+CommandProcessing/source/cmd_io.obj: ../CommandProcessing/source/cmd_io.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/cmd_io.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/cmd_io_line.obj: ../CommandProcessing/source/cmd_io_line.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/cmd_io_line.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/cmd_proc.obj: ../CommandProcessing/source/cmd_proc.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/cmd_proc.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/cmd_proc_freertos_tms570.obj: ../CommandProcessing/source/cmd_proc_freertos_tms570.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/cmd_proc_freertos_tms570.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/cmd_proc_run.obj: ../CommandProcessing/source/cmd_proc_run.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/cmd_proc_run.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/cmdio_buffer.obj: ../CommandProcessing/source/cmdio_buffer.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/cmdio_buffer.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/cmdio_std_line.obj: ../CommandProcessing/source/cmdio_std_line.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/cmdio_std_line.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/commands.obj: ../CommandProcessing/source/commands.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/commands.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/dabort.obj: ../CommandProcessing/source/dabort.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/dabort.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/esm.obj: ../CommandProcessing/source/esm.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/esm.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/i2str.obj: ../CommandProcessing/source/i2str.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/i2str.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/notification.obj: ../CommandProcessing/source/notification.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/notification.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/os_croutine.obj: ../CommandProcessing/source/os_croutine.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/os_croutine.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/os_heap.obj: ../CommandProcessing/source/os_heap.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/os_heap.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/os_list.obj: ../CommandProcessing/source/os_list.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/os_list.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/os_port.obj: ../CommandProcessing/source/os_port.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/os_port.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/os_portasm.obj: ../CommandProcessing/source/os_portasm.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/os_portasm.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/os_queue.obj: ../CommandProcessing/source/os_queue.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/os_queue.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/os_tasks.obj: ../CommandProcessing/source/os_tasks.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/os_tasks.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/os_timer.obj: ../CommandProcessing/source/os_timer.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/os_timer.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/pinmux.obj: ../CommandProcessing/source/pinmux.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/pinmux.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sci.obj: ../CommandProcessing/source/sci.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sci.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sys_core.obj: ../CommandProcessing/source/sys_core.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sys_core.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sys_intvecs.obj: ../CommandProcessing/source/sys_intvecs.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sys_intvecs.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sys_main.obj: ../CommandProcessing/source/sys_main.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sys_main.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sys_mpu.obj: ../CommandProcessing/source/sys_mpu.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sys_mpu.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sys_phantom.obj: ../CommandProcessing/source/sys_phantom.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sys_phantom.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sys_pmu.obj: ../CommandProcessing/source/sys_pmu.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sys_pmu.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sys_selftest.obj: ../CommandProcessing/source/sys_selftest.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sys_selftest.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/sys_startup.obj: ../CommandProcessing/source/sys_startup.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/sys_startup.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+CommandProcessing/source/system.obj: ../CommandProcessing/source/system.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="CommandProcessing/source/system.pp" --obj_directory="CommandProcessing/source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+../CommandProcessing/source/sys_link.cmd
+
+ASM_SRCS += \
+../CommandProcessing/source/dabort.asm \
+../CommandProcessing/source/os_portasm.asm \
+../CommandProcessing/source/sys_core.asm \
+../CommandProcessing/source/sys_intvecs.asm \
+../CommandProcessing/source/sys_mpu.asm \
+../CommandProcessing/source/sys_pmu.asm
+
+C_SRCS += \
+../CommandProcessing/source/cmd_io.c \
+../CommandProcessing/source/cmd_io_line.c \
+../CommandProcessing/source/cmd_proc.c \
+../CommandProcessing/source/cmd_proc_freertos_tms570.c \
+../CommandProcessing/source/cmd_proc_run.c \
+../CommandProcessing/source/cmdio_buffer.c \
+../CommandProcessing/source/cmdio_std_line.c \
+../CommandProcessing/source/commands.c \
+../CommandProcessing/source/esm.c \
+../CommandProcessing/source/i2str.c \
+../CommandProcessing/source/notification.c \
+../CommandProcessing/source/os_croutine.c \
+../CommandProcessing/source/os_heap.c \
+../CommandProcessing/source/os_list.c \
+../CommandProcessing/source/os_port.c \
+../CommandProcessing/source/os_queue.c \
+../CommandProcessing/source/os_tasks.c \
+../CommandProcessing/source/os_timer.c \
+../CommandProcessing/source/pinmux.c \
+../CommandProcessing/source/sci.c \
+../CommandProcessing/source/sys_main.c \
+../CommandProcessing/source/sys_phantom.c \
+../CommandProcessing/source/sys_selftest.c \
+../CommandProcessing/source/sys_startup.c \
+../CommandProcessing/source/system.c
+
+OBJS += \
+./CommandProcessing/source/cmd_io.obj \
+./CommandProcessing/source/cmd_io_line.obj \
+./CommandProcessing/source/cmd_proc.obj \
+./CommandProcessing/source/cmd_proc_freertos_tms570.obj \
+./CommandProcessing/source/cmd_proc_run.obj \
+./CommandProcessing/source/cmdio_buffer.obj \
+./CommandProcessing/source/cmdio_std_line.obj \
+./CommandProcessing/source/commands.obj \
+./CommandProcessing/source/dabort.obj \
+./CommandProcessing/source/esm.obj \
+./CommandProcessing/source/i2str.obj \
+./CommandProcessing/source/notification.obj \
+./CommandProcessing/source/os_croutine.obj \
+./CommandProcessing/source/os_heap.obj \
+./CommandProcessing/source/os_list.obj \
+./CommandProcessing/source/os_port.obj \
+./CommandProcessing/source/os_portasm.obj \
+./CommandProcessing/source/os_queue.obj \
+./CommandProcessing/source/os_tasks.obj \
+./CommandProcessing/source/os_timer.obj \
+./CommandProcessing/source/pinmux.obj \
+./CommandProcessing/source/sci.obj \
+./CommandProcessing/source/sys_core.obj \
+./CommandProcessing/source/sys_intvecs.obj \
+./CommandProcessing/source/sys_main.obj \
+./CommandProcessing/source/sys_mpu.obj \
+./CommandProcessing/source/sys_phantom.obj \
+./CommandProcessing/source/sys_pmu.obj \
+./CommandProcessing/source/sys_selftest.obj \
+./CommandProcessing/source/sys_startup.obj \
+./CommandProcessing/source/system.obj
+
+ASM_DEPS += \
+./CommandProcessing/source/dabort.pp \
+./CommandProcessing/source/os_portasm.pp \
+./CommandProcessing/source/sys_core.pp \
+./CommandProcessing/source/sys_intvecs.pp \
+./CommandProcessing/source/sys_mpu.pp \
+./CommandProcessing/source/sys_pmu.pp
+
+C_DEPS += \
+./CommandProcessing/source/cmd_io.pp \
+./CommandProcessing/source/cmd_io_line.pp \
+./CommandProcessing/source/cmd_proc.pp \
+./CommandProcessing/source/cmd_proc_freertos_tms570.pp \
+./CommandProcessing/source/cmd_proc_run.pp \
+./CommandProcessing/source/cmdio_buffer.pp \
+./CommandProcessing/source/cmdio_std_line.pp \
+./CommandProcessing/source/commands.pp \
+./CommandProcessing/source/esm.pp \
+./CommandProcessing/source/i2str.pp \
+./CommandProcessing/source/notification.pp \
+./CommandProcessing/source/os_croutine.pp \
+./CommandProcessing/source/os_heap.pp \
+./CommandProcessing/source/os_list.pp \
+./CommandProcessing/source/os_port.pp \
+./CommandProcessing/source/os_queue.pp \
+./CommandProcessing/source/os_tasks.pp \
+./CommandProcessing/source/os_timer.pp \
+./CommandProcessing/source/pinmux.pp \
+./CommandProcessing/source/sci.pp \
+./CommandProcessing/source/sys_main.pp \
+./CommandProcessing/source/sys_phantom.pp \
+./CommandProcessing/source/sys_selftest.pp \
+./CommandProcessing/source/sys_startup.pp \
+./CommandProcessing/source/system.pp
+
+C_DEPS__QUOTED += \
+"CommandProcessing/source/cmd_io.pp" \
+"CommandProcessing/source/cmd_io_line.pp" \
+"CommandProcessing/source/cmd_proc.pp" \
+"CommandProcessing/source/cmd_proc_freertos_tms570.pp" \
+"CommandProcessing/source/cmd_proc_run.pp" \
+"CommandProcessing/source/cmdio_buffer.pp" \
+"CommandProcessing/source/cmdio_std_line.pp" \
+"CommandProcessing/source/commands.pp" \
+"CommandProcessing/source/esm.pp" \
+"CommandProcessing/source/i2str.pp" \
+"CommandProcessing/source/notification.pp" \
+"CommandProcessing/source/os_croutine.pp" \
+"CommandProcessing/source/os_heap.pp" \
+"CommandProcessing/source/os_list.pp" \
+"CommandProcessing/source/os_port.pp" \
+"CommandProcessing/source/os_queue.pp" \
+"CommandProcessing/source/os_tasks.pp" \
+"CommandProcessing/source/os_timer.pp" \
+"CommandProcessing/source/pinmux.pp" \
+"CommandProcessing/source/sci.pp" \
+"CommandProcessing/source/sys_main.pp" \
+"CommandProcessing/source/sys_phantom.pp" \
+"CommandProcessing/source/sys_selftest.pp" \
+"CommandProcessing/source/sys_startup.pp" \
+"CommandProcessing/source/system.pp"
+
+OBJS__QUOTED += \
+"CommandProcessing/source/cmd_io.obj" \
+"CommandProcessing/source/cmd_io_line.obj" \
+"CommandProcessing/source/cmd_proc.obj" \
+"CommandProcessing/source/cmd_proc_freertos_tms570.obj" \
+"CommandProcessing/source/cmd_proc_run.obj" \
+"CommandProcessing/source/cmdio_buffer.obj" \
+"CommandProcessing/source/cmdio_std_line.obj" \
+"CommandProcessing/source/commands.obj" \
+"CommandProcessing/source/dabort.obj" \
+"CommandProcessing/source/esm.obj" \
+"CommandProcessing/source/i2str.obj" \
+"CommandProcessing/source/notification.obj" \
+"CommandProcessing/source/os_croutine.obj" \
+"CommandProcessing/source/os_heap.obj" \
+"CommandProcessing/source/os_list.obj" \
+"CommandProcessing/source/os_port.obj" \
+"CommandProcessing/source/os_portasm.obj" \
+"CommandProcessing/source/os_queue.obj" \
+"CommandProcessing/source/os_tasks.obj" \
+"CommandProcessing/source/os_timer.obj" \
+"CommandProcessing/source/pinmux.obj" \
+"CommandProcessing/source/sci.obj" \
+"CommandProcessing/source/sys_core.obj" \
+"CommandProcessing/source/sys_intvecs.obj" \
+"CommandProcessing/source/sys_main.obj" \
+"CommandProcessing/source/sys_mpu.obj" \
+"CommandProcessing/source/sys_phantom.obj" \
+"CommandProcessing/source/sys_pmu.obj" \
+"CommandProcessing/source/sys_selftest.obj" \
+"CommandProcessing/source/sys_startup.obj" \
+"CommandProcessing/source/system.obj"
+
+ASM_DEPS__QUOTED += \
+"CommandProcessing/source/dabort.pp" \
+"CommandProcessing/source/os_portasm.pp" \
+"CommandProcessing/source/sys_core.pp" \
+"CommandProcessing/source/sys_intvecs.pp" \
+"CommandProcessing/source/sys_mpu.pp" \
+"CommandProcessing/source/sys_pmu.pp"
+
+C_SRCS__QUOTED += \
+"../CommandProcessing/source/cmd_io.c" \
+"../CommandProcessing/source/cmd_io_line.c" \
+"../CommandProcessing/source/cmd_proc.c" \
+"../CommandProcessing/source/cmd_proc_freertos_tms570.c" \
+"../CommandProcessing/source/cmd_proc_run.c" \
+"../CommandProcessing/source/cmdio_buffer.c" \
+"../CommandProcessing/source/cmdio_std_line.c" \
+"../CommandProcessing/source/commands.c" \
+"../CommandProcessing/source/esm.c" \
+"../CommandProcessing/source/i2str.c" \
+"../CommandProcessing/source/notification.c" \
+"../CommandProcessing/source/os_croutine.c" \
+"../CommandProcessing/source/os_heap.c" \
+"../CommandProcessing/source/os_list.c" \
+"../CommandProcessing/source/os_port.c" \
+"../CommandProcessing/source/os_queue.c" \
+"../CommandProcessing/source/os_tasks.c" \
+"../CommandProcessing/source/os_timer.c" \
+"../CommandProcessing/source/pinmux.c" \
+"../CommandProcessing/source/sci.c" \
+"../CommandProcessing/source/sys_main.c" \
+"../CommandProcessing/source/sys_phantom.c" \
+"../CommandProcessing/source/sys_selftest.c" \
+"../CommandProcessing/source/sys_startup.c" \
+"../CommandProcessing/source/system.c"
+
+ASM_SRCS__QUOTED += \
+"../CommandProcessing/source/dabort.asm" \
+"../CommandProcessing/source/os_portasm.asm" \
+"../CommandProcessing/source/sys_core.asm" \
+"../CommandProcessing/source/sys_intvecs.asm" \
+"../CommandProcessing/source/sys_mpu.asm" \
+"../CommandProcessing/source/sys_pmu.asm"
+
+
--- /dev/null
+******************************************************************************
+ TMS470 Linker Unix v4.9.1
+******************************************************************************
+>> Linked Tue Jul 17 10:58:24 2012
+
+OUTPUT FILE NAME: <CommandStoring.out>
+ENTRY POINT SYMBOL: "_c_int00" address: 00003760
+
+
+MEMORY CONFIGURATION
+
+ name origin length used unused attr fill
+---------------------- -------- --------- -------- -------- ---- --------
+ VECTORS 00000000 00000020 00000020 00000000 X
+ FLASH0 00000020 0017ffe0 000062cc 00179d14 R X
+ FLASH1 00180000 00180000 00000000 00180000 R X
+ STACKS 08000000 00001500 00000000 00001500 RW
+ RAM 08001500 00026b00 00002168 00024998 RW
+
+
+SEGMENT ALLOCATION MAP
+
+run origin load origin length init length attrs members
+---------- ----------- ---------- ----------- ----- -------
+00000000 00000000 000062f0 000062f0 r-x
+ 00000000 00000000 00000020 00000020 r-x .intvecs
+ 00000020 00000020 00006058 00006058 r-x .text
+ 00006078 00006078 00000204 00000204 r-- .const
+ 00006280 00006280 00000070 00000070 r-- .cinit
+08001500 08001500 000020f0 00000000 rw-
+ 08001500 08001500 000020f0 00000000 rw- .bss
+080035f0 080035f0 00000078 00000078 rw-
+ 080035f0 080035f0 00000078 00000078 rw- .data
+
+
+SECTION ALLOCATION MAP
+
+ output attributes/
+section page origin length input sections
+-------- ---- ---------- ---------- ----------------
+.intvecs 0 00000000 00000020
+ 00000000 00000020 sys_intvecs.obj (.intvecs)
+
+.text 0 00000020 00006058
+ 00000020 000014c8 sys_selftest.obj (.text)
+ 000014e8 0000125c os_tasks.obj (.text)
+ 00002744 000009e4 os_queue.obj (.text)
+ 00003128 00000638 os_port.obj (.text)
+ 00003760 000005a8 sys_startup.obj (.text:retain)
+ 00003d08 00000590 sci.obj (.text)
+ 00004298 0000043c esm.obj (.text)
+ 000046d4 00000388 sci.obj (.text:retain)
+ 00004a5c 00000384 sys_core.obj (.text)
+ 00004de0 00000308 system.obj (.text)
+ 000050e8 00000300 pinmux.obj (.text)
+ 000053e8 00000240 os_list.obj (.text)
+ 00005628 00000220 esm.obj (.text:retain)
+ 00005848 00000204 sys_main.obj (.text)
+ 00005a4c 0000016c os_portasm.obj (.text)
+ 00005bb8 000000dc os_heap.obj (.text)
+ 00005c94 000000c0 dabort.obj (.text)
+ 00005d54 0000009c rtsv7R4_T_be_v3D16_eabi.lib : memcpy_t2.obj (.text)
+ 00005df0 00000098 notification.obj (.text)
+ 00005e88 00000078 rtsv7R4_T_be_v3D16_eabi.lib : memset_t2.obj (.text)
+ 00005f00 00000060 : copy_decompress_rle.obj (.text)
+ 00005f60 0000004c : cpy_tbl.obj (.text)
+ 00005fac 00000044 : exit.obj (.text)
+ 00005ff0 00000030 : strncpy.obj (.text)
+ 00006020 00000018 : _lock.obj (.text)
+ 00006038 00000014 : strlen.obj (.text)
+ 0000604c 00000012 : copy_zero_init.obj (.text:decompress:ZI)
+ 0000605e 0000000e : copy_decompress_none.obj (.text:decompress:none)
+ 0000606c 00000006 : copy_decompress_rle.obj (.text:decompress:rle24)
+ 00006072 00000002 --HOLE-- [fill = 0]
+ 00006074 00000004 sys_phantom.obj (.text:retain)
+
+.const 0 00006078 00000204
+ 00006078 00000204 sys_startup.obj (.const:s_vim_init)
+
+.cinit 0 00006280 00000070
+ 00006280 00000046 (.cinit..data.load) [load image, compression = rle]
+ 000062c6 00000002 --HOLE-- [fill = 0]
+ 000062c8 0000000c (__TI_handler_table)
+ 000062d4 00000004 --HOLE-- [fill = 0]
+ 000062d8 00000008 (.cinit..bss.load) [load image, compression = zero_init]
+ 000062e0 00000010 (__TI_cinit_table)
+
+.bss 0 08001500 000020f0 UNINITIALIZED
+ 08001500 00002000 os_heap.obj (.bss:xHeap)
+ 08003500 00000064 os_tasks.obj (.bss:pxReadyTasksLists)
+ 08003564 00000058 os_tasks.obj (.bss)
+ 080035bc 00000019 sys_main.obj (.bss)
+ 080035d5 00000003 --HOLE--
+ 080035d8 00000018 sci.obj (.bss)
+
+.data 0 080035f0 00000078
+ 080035f0 00000030 os_tasks.obj (.data)
+ 08003620 0000002d sys_main.obj (.data)
+ 0800364d 00000003 --HOLE--
+ 08003650 00000008 rtsv7R4_T_be_v3D16_eabi.lib : _lock.obj (.data)
+ 08003658 00000008 : exit.obj (.data)
+ 08003660 00000004 os_heap.obj (.data)
+ 08003664 00000004 os_port.obj (.data)
+
+
+LINKER GENERATED COPY TABLES
+
+__TI_cinit_table @ 000062e0 records: 2, size/record: 8, table size: 16
+ .data: load addr=00006280, load size=00000046 bytes, run addr=080035f0, run size=00000078 bytes, compression=rle
+ .bss: load addr=000062d8, load size=00000008 bytes, run addr=08001500, run size=000020f0 bytes, compression=zero_init
+
+
+LINKER GENERATED HANDLER TABLE
+
+__TI_handler_table @ 000062c8 records: 3, size/record: 4, table size: 12
+ index: 0, handler: __TI_zero_init
+ index: 1, handler: __TI_decompress_rle24
+ index: 2, handler: __TI_decompress_none
+
+
+GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
+
+address name
+-------- ----
+00005fad C$$EXIT
+000062e0 __TI_CINIT_Base
+000062f0 __TI_CINIT_Limit
+000062c8 __TI_Handler_Table_Base
+000062d4 __TI_Handler_Table_Limit
+00004dd8 __TI_PINIT_Base
+00004ddc __TI_PINIT_Limit
+0000605f __TI_decompress_none
+0000606d __TI_decompress_rle24
+00000000 __TI_static_base__
+0000604d __TI_zero_init
+00005e89 __aeabi_memclr
+00005e89 __aeabi_memclr4
+00005e89 __aeabi_memclr8
+00005d55 __aeabi_memcpy
+00005d55 __aeabi_memcpy4
+00005d55 __aeabi_memcpy8
+00005e8b __aeabi_memset
+00005e8b __aeabi_memset4
+00005e8b __aeabi_memset8
+ffffffff __binit__
+ffffffff __c_args__
+00003760 _c_int00
+08003658 _cleanup_ptr
+00004d00 _coreClearAuxiliaryDataFault_
+00004d1c _coreClearAuxiliaryInstructionFault_
+00004cc8 _coreClearDataFaultAddress_
+00004c90 _coreClearDataFault_
+00004ce4 _coreClearInstructionFaultAddress_
+00004cac _coreClearInstructionFault_
+00004bf4 _coreDisableEventBusExport_
+00004c58 _coreDisableFlashEcc_
+00004c24 _coreDisableRamEcc_
+00004bdc _coreEnableEventBusExport_
+00004c3c _coreEnableFlashEcc_
+00004c70 _coreEnableIrqVicOffset_
+00004c0c _coreEnableRamEcc_
+00004bc4 _coreEnableVfp_
+00004cf8 _coreGetAuxiliaryDataFault_
+00004d14 _coreGetAuxiliaryInstructionFault_
+00004cc0 _coreGetDataFaultAddress_
+00004c88 _coreGetDataFault_
+00004cdc _coreGetInstructionFaultAddress_
+00004ca4 _coreGetInstructionFault_
+00004a5c _coreInitRegisters_
+00004b5c _coreInitStackPointer_
+00005c94 _dabort
+00004d38 _disable_FIQ_interrupt_
+00004d40 _disable_IRQ_interrupt_
+00004d30 _disable_interrupt_
+0800365c _dtors_ptr
+00004d48 _enable_interrupt_
+00004d50 _esmCcmErrorsClear_
+00004ba8 _getCPSRValue_
+00004bb0 _gotoCPUIdle_
+08003650 _lock
+00000138 _memoryInit_
+0000602d _nop
+00006027 _register_lock
+00006021 _register_unlock
+08003654 _unlock
+00005fb1 abort
+00000e28 adc1ParityCheck
+00000e94 adc2ParityCheck
+ffffffff binit
+080035c4 buffer
+00000f00 can1ParityCheck
+00000f80 can2ParityCheck
+00001010 can3ParityCheck
+00000104 ccmFail
+00000020 ccmSelfCheck
+080035d4 character
+00000854 checkB0RAMECC
+00000978 checkB1RAMECC
+00000a98 checkFlashECC
+000006d8 checkefcSelfTest
+08003634 cmdLenErr
+00005f61 copy_in
+00000224 cpuSelfTest
+00000b68 cpuSelfTestFail
+00000b60 custom_dabort
+00000be0 dmaParityCheck
+000005a0 efcCheck
+00000770 efcClass1Error
+00000774 efcClass2Error
+000006b0 efcSelfTest
+000005fc efcStuckZeroTest
+00004448 esmActivateNormalOperation
+00004534 esmClearStatus
+00004574 esmClearStatusBuffer
+0000440c esmDisableError
+00004484 esmDisableInterrupt
+000043e0 esmEnableError
+00004458 esmEnableInterrupt
+000043c4 esmError
+000045c0 esmGetStatus
+00004624 esmGetStatusBuffer
+00005df0 esmGroup1Notification
+00005dfc esmGroup2Notification
+00005628 esmHighInterrupt
+00004298 esmInit
+0000576c esmLowInterrupt
+000045a0 esmSetCounterPreloadValue
+000044b0 esmSetInterruptLevel
+00004438 esmTriggerErrorPinReset
+00005fb9 exit
+00000b58 flashClass1Error
+00000b5c flashClass2Error
+00000778 fmcBus2Check
+0000084c fmcClass1Error
+00000850 fmcClass2Error
+000007b4 fmcECCcheck
+080035d8 g_sciTransfer
+00000c54 het1ParityCheck
+00000d30 het2ParityCheck
+00000cbc htu1ParityCheck
+00000db4 htu2ParityCheck
+080035bc inputCharacterQueue
+08003620 intro
+00005978 main
+00004ef4 mapClocks
+00005d55 memcpy
+00005e08 memoryPort0TestFailNotification
+00005e20 memoryPort1TestFailNotification
+00005e91 memset
+000010a4 mibspi1ParityCheck
+0000118c mibspi3ParityCheck
+00001284 mibspi5ParityCheck
+000050e8 muxInit
+000004ec pbistIsTestCompleted
+00000508 pbistIsTestPassed
+00000544 pbistPortTestStatus
+000003e4 pbistRun
+000002a4 pbistSelfCheck
+000003e0 pbistSelfCheckFail
+000004bc pbistStop
+00004e9c periphInit
+00006074 phantomInterrupt
+00005848 processCmd
+00005bb8 pvPortMalloc
+080035f0 pxCurrentTCB
+00003128 pxPortInitialiseStack
+0000415c sciDisableLoopback
+000041e8 sciDisableNotification
+00004128 sciEnableLoopback
+00004178 sciEnableNotification
+000046d4 sciHighLevelInterrupt
+00003d08 sciInit
+00003fdc sciIsRxReady
+00003e7c sciIsTxReady
+00004880 sciLowLevelInterrupt
+00005e38 sciNotification
+00004050 sciReceive
+00004028 sciReceiveByte
+00003ff8 sciRxError
+00003ec8 sciSend
+00003e98 sciSendByte
+00003dfc sciSetBaudrate
+00003ddc sciSetFunctional
+00004e5c setupFlash
+00004de0 setupPLL
+0000017c stcSelfCheck
+00000b64 stcSelfCheckFail
+0000588c storeCmd
+080035c0 storeCmdHandler
+00006039 strlen
+00005ff1 strncpy
+00004fcc systemInit
+00005058 systemPowerDown
+00000a90 tcramClass1Error
+00000a94 tcramClass2Error
+00004e14 trimLPO
+08003664 ulCriticalNesting
+00002d80 uxQueueMessagesWaiting
+00002da4 uxQueueMessagesWaitingFromISR
+00001e98 uxTaskGetNumberOfTasks
+0000266c uxTaskGetStackHighWaterMark
+0000184c uxTaskPriorityGet
+000053e8 vListInitialise
+00005440 vListInitialiseItem
+000054e0 vListInsert
+0000545c vListInsertEnd
+000055a4 vListRemove
+0000361c vPortEndScheduler
+00003620 vPortEnterCritical
+00003638 vPortExitCritical
+00005c5c vPortFree
+00005c6c vPortInitialiseBlocks
+00005a4c vPortStartFirstTask
+00005ba4 vPortYield
+00005a80 vPortYieldProcessor
+00005b08 vPreemptiveTick
+00002dc4 vQueueDelete
+000017e4 vTaskDelay
+000016e8 vTaskDelayUntil
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+0000214c vTaskPlaceOnEventList
+00001890 vTaskPrioritySet
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+00002298 vTaskSetTimeOutState
+00001c38 vTaskStartScheduler
+00001a08 vTaskSuspend
+00001cd0 vTaskSuspendAll
+00002084 vTaskSwitchContext
+00000b6c vimParityCheck
+00005c7c xPortGetFreeHeapSize
+00003608 xPortStartScheduler
+00002744 xQueueCreate
+00002ac8 xQueueGenericReceive
+00002874 xQueueGenericSend
+000029fc xQueueGenericSendFromISR
+00003084 xQueueIsQueueEmptyFromISR
+000030f0 xQueueIsQueueFullFromISR
+00002cb4 xQueueReceiveFromISR
+000022c8 xTaskCheckForTimeOut
+000014e8 xTaskGenericCreate
+000026bc xTaskGetSchedulerState
+00001e54 xTaskGetTickCount
+00001e74 xTaskGetTickCountFromISR
+00001ae0 xTaskIsTaskSuspended
+000021c0 xTaskRemoveFromEventList
+00001ce4 xTaskResumeAll
+
+
+GLOBAL SYMBOLS: SORTED BY Symbol Address
+
+address name
+-------- ----
+00000000 __TI_static_base__
+00000020 ccmSelfCheck
+00000104 ccmFail
+00000138 _memoryInit_
+0000017c stcSelfCheck
+00000224 cpuSelfTest
+000002a4 pbistSelfCheck
+000003e0 pbistSelfCheckFail
+000003e4 pbistRun
+000004bc pbistStop
+000004ec pbistIsTestCompleted
+00000508 pbistIsTestPassed
+00000544 pbistPortTestStatus
+000005a0 efcCheck
+000005fc efcStuckZeroTest
+000006b0 efcSelfTest
+000006d8 checkefcSelfTest
+00000770 efcClass1Error
+00000774 efcClass2Error
+00000778 fmcBus2Check
+000007b4 fmcECCcheck
+0000084c fmcClass1Error
+00000850 fmcClass2Error
+00000854 checkB0RAMECC
+00000978 checkB1RAMECC
+00000a90 tcramClass1Error
+00000a94 tcramClass2Error
+00000a98 checkFlashECC
+00000b58 flashClass1Error
+00000b5c flashClass2Error
+00000b60 custom_dabort
+00000b64 stcSelfCheckFail
+00000b68 cpuSelfTestFail
+00000b6c vimParityCheck
+00000be0 dmaParityCheck
+00000c54 het1ParityCheck
+00000cbc htu1ParityCheck
+00000d30 het2ParityCheck
+00000db4 htu2ParityCheck
+00000e28 adc1ParityCheck
+00000e94 adc2ParityCheck
+00000f00 can1ParityCheck
+00000f80 can2ParityCheck
+00001010 can3ParityCheck
+000010a4 mibspi1ParityCheck
+0000118c mibspi3ParityCheck
+00001284 mibspi5ParityCheck
+000014e8 xTaskGenericCreate
+000016e8 vTaskDelayUntil
+000017e4 vTaskDelay
+0000184c uxTaskPriorityGet
+00001890 vTaskPrioritySet
+00001a08 vTaskSuspend
+00001ae0 xTaskIsTaskSuspended
+00001b74 vTaskResume
+00001c38 vTaskStartScheduler
+00001cb4 vTaskEndScheduler
+00001cd0 vTaskSuspendAll
+00001ce4 xTaskResumeAll
+00001e54 xTaskGetTickCount
+00001e74 xTaskGetTickCountFromISR
+00001e98 uxTaskGetNumberOfTasks
+00001eac vTaskIncrementTick
+00002084 vTaskSwitchContext
+0000214c vTaskPlaceOnEventList
+000021c0 xTaskRemoveFromEventList
+00002298 vTaskSetTimeOutState
+000022c8 xTaskCheckForTimeOut
+000023a0 vTaskMissedYield
+0000266c uxTaskGetStackHighWaterMark
+000026bc xTaskGetSchedulerState
+00002744 xQueueCreate
+00002874 xQueueGenericSend
+000029fc xQueueGenericSendFromISR
+00002ac8 xQueueGenericReceive
+00002cb4 xQueueReceiveFromISR
+00002d80 uxQueueMessagesWaiting
+00002da4 uxQueueMessagesWaitingFromISR
+00002dc4 vQueueDelete
+00003084 xQueueIsQueueEmptyFromISR
+000030f0 xQueueIsQueueFullFromISR
+00003128 pxPortInitialiseStack
+00003608 xPortStartScheduler
+0000361c vPortEndScheduler
+00003620 vPortEnterCritical
+00003638 vPortExitCritical
+00003760 _c_int00
+00003d08 sciInit
+00003ddc sciSetFunctional
+00003dfc sciSetBaudrate
+00003e7c sciIsTxReady
+00003e98 sciSendByte
+00003ec8 sciSend
+00003fdc sciIsRxReady
+00003ff8 sciRxError
+00004028 sciReceiveByte
+00004050 sciReceive
+00004128 sciEnableLoopback
+0000415c sciDisableLoopback
+00004178 sciEnableNotification
+000041e8 sciDisableNotification
+00004298 esmInit
+000043c4 esmError
+000043e0 esmEnableError
+0000440c esmDisableError
+00004438 esmTriggerErrorPinReset
+00004448 esmActivateNormalOperation
+00004458 esmEnableInterrupt
+00004484 esmDisableInterrupt
+000044b0 esmSetInterruptLevel
+00004534 esmClearStatus
+00004574 esmClearStatusBuffer
+000045a0 esmSetCounterPreloadValue
+000045c0 esmGetStatus
+00004624 esmGetStatusBuffer
+000046d4 sciHighLevelInterrupt
+00004880 sciLowLevelInterrupt
+00004a5c _coreInitRegisters_
+00004b5c _coreInitStackPointer_
+00004ba8 _getCPSRValue_
+00004bb0 _gotoCPUIdle_
+00004bc4 _coreEnableVfp_
+00004bdc _coreEnableEventBusExport_
+00004bf4 _coreDisableEventBusExport_
+00004c0c _coreEnableRamEcc_
+00004c24 _coreDisableRamEcc_
+00004c3c _coreEnableFlashEcc_
+00004c58 _coreDisableFlashEcc_
+00004c70 _coreEnableIrqVicOffset_
+00004c88 _coreGetDataFault_
+00004c90 _coreClearDataFault_
+00004ca4 _coreGetInstructionFault_
+00004cac _coreClearInstructionFault_
+00004cc0 _coreGetDataFaultAddress_
+00004cc8 _coreClearDataFaultAddress_
+00004cdc _coreGetInstructionFaultAddress_
+00004ce4 _coreClearInstructionFaultAddress_
+00004cf8 _coreGetAuxiliaryDataFault_
+00004d00 _coreClearAuxiliaryDataFault_
+00004d14 _coreGetAuxiliaryInstructionFault_
+00004d1c _coreClearAuxiliaryInstructionFault_
+00004d30 _disable_interrupt_
+00004d38 _disable_FIQ_interrupt_
+00004d40 _disable_IRQ_interrupt_
+00004d48 _enable_interrupt_
+00004d50 _esmCcmErrorsClear_
+00004dd8 __TI_PINIT_Base
+00004ddc __TI_PINIT_Limit
+00004de0 setupPLL
+00004e14 trimLPO
+00004e5c setupFlash
+00004e9c periphInit
+00004ef4 mapClocks
+00004fcc systemInit
+00005058 systemPowerDown
+000050e8 muxInit
+000053e8 vListInitialise
+00005440 vListInitialiseItem
+0000545c vListInsertEnd
+000054e0 vListInsert
+000055a4 vListRemove
+00005628 esmHighInterrupt
+0000576c esmLowInterrupt
+00005848 processCmd
+0000588c storeCmd
+00005978 main
+00005a4c vPortStartFirstTask
+00005a80 vPortYieldProcessor
+00005b08 vPreemptiveTick
+00005ba4 vPortYield
+00005bb8 pvPortMalloc
+00005c5c vPortFree
+00005c6c vPortInitialiseBlocks
+00005c7c xPortGetFreeHeapSize
+00005c94 _dabort
+00005d55 __aeabi_memcpy
+00005d55 __aeabi_memcpy4
+00005d55 __aeabi_memcpy8
+00005d55 memcpy
+00005df0 esmGroup1Notification
+00005dfc esmGroup2Notification
+00005e08 memoryPort0TestFailNotification
+00005e20 memoryPort1TestFailNotification
+00005e38 sciNotification
+00005e89 __aeabi_memclr
+00005e89 __aeabi_memclr4
+00005e89 __aeabi_memclr8
+00005e8b __aeabi_memset
+00005e8b __aeabi_memset4
+00005e8b __aeabi_memset8
+00005e91 memset
+00005f61 copy_in
+00005fad C$$EXIT
+00005fb1 abort
+00005fb9 exit
+00005ff1 strncpy
+00006021 _register_unlock
+00006027 _register_lock
+0000602d _nop
+00006039 strlen
+0000604d __TI_zero_init
+0000605f __TI_decompress_none
+0000606d __TI_decompress_rle24
+00006074 phantomInterrupt
+000062c8 __TI_Handler_Table_Base
+000062d4 __TI_Handler_Table_Limit
+000062e0 __TI_CINIT_Base
+000062f0 __TI_CINIT_Limit
+080035bc inputCharacterQueue
+080035c0 storeCmdHandler
+080035c4 buffer
+080035d4 character
+080035d8 g_sciTransfer
+080035f0 pxCurrentTCB
+08003620 intro
+08003634 cmdLenErr
+08003650 _lock
+08003654 _unlock
+08003658 _cleanup_ptr
+0800365c _dtors_ptr
+08003664 ulCriticalNesting
+ffffffff __binit__
+ffffffff __c_args__
+ffffffff binit
+
+[224 symbols]
--- /dev/null
+"./source/system.obj" "./source/sys_startup.obj" "./source/sys_selftest.obj" "./source/sys_pmu.obj" "./source/sys_phantom.obj" "./source/sys_mpu.obj" "./source/sys_main.obj" "./source/sys_intvecs.obj" "./source/sys_core.obj" "./source/sci.obj" "./source/pinmux.obj" "./source/os_timer.obj" "./source/os_tasks.obj" "./source/os_queue.obj" "./source/os_portasm.obj" "./source/os_port.obj" "./source/os_list.obj" "./source/os_heap.obj" "./source/os_croutine.obj" "./source/notification.obj" "./source/i2str.obj" "./source/esm.obj" "./source/dabort.obj" "./source/commands.obj" "./source/cmdio_tisci.obj" "./source/cmdio_std_line.obj" "./source/cmd_proc_run.obj" "./source/cmd_proc_freertos_tms570.obj" "./source/cmd_proc.obj" "./source/cmd_io_line.obj" "./source/cmd_io.obj" -l"rtsv7R4_T_be_v3D16_eabi.lib" "../source/sys_link.cmd"
\ No newline at end of file
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+CG_TOOL_ROOT := /opt/ti/ccsv5/tools/compiler/tms470_4.9.1
+
+ORDERED_OBJS += \
+$(GEN_CMDS__FLAG) \
+"./source/system.obj" \
+"./source/sys_startup.obj" \
+"./source/sys_selftest.obj" \
+"./source/sys_pmu.obj" \
+"./source/sys_phantom.obj" \
+"./source/sys_mpu.obj" \
+"./source/sys_main.obj" \
+"./source/sys_intvecs.obj" \
+"./source/sys_core.obj" \
+"./source/sci.obj" \
+"./source/pinmux.obj" \
+"./source/os_timer.obj" \
+"./source/os_tasks.obj" \
+"./source/os_queue.obj" \
+"./source/os_portasm.obj" \
+"./source/os_port.obj" \
+"./source/os_list.obj" \
+"./source/os_heap.obj" \
+"./source/os_croutine.obj" \
+"./source/notification.obj" \
+"./source/i2str.obj" \
+"./source/esm.obj" \
+"./source/dabort.obj" \
+"./source/commands.obj" \
+"./source/cmdio_tisci.obj" \
+"./source/cmdio_std_line.obj" \
+"./source/cmd_proc_run.obj" \
+"./source/cmd_proc_freertos_tms570.obj" \
+"./source/cmd_proc.obj" \
+"./source/cmd_io_line.obj" \
+"./source/cmd_io.obj" \
+-l"rtsv7R4_T_be_v3D16_eabi.lib" \
+"../source/sys_link.cmd" \
+
+-include ../makefile.init
+
+RM := rm -rf
+RMDIR := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include source/subdir_vars.mk
+-include source/subdir_rules.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(S_DEPS)),)
+-include $(S_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(S62_DEPS)),)
+-include $(S62_DEPS)
+endif
+ifneq ($(strip $(C64_DEPS)),)
+-include $(C64_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(S55_DEPS)),)
+-include $(S55_DEPS)
+endif
+ifneq ($(strip $(C67_DEPS)),)
+-include $(C67_DEPS)
+endif
+ifneq ($(strip $(C??_DEPS)),)
+-include $(C??_DEPS)
+endif
+ifneq ($(strip $(CLA_DEPS)),)
+-include $(CLA_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+ifneq ($(strip $(S??_DEPS)),)
+-include $(S??_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(C62_DEPS)),)
+-include $(C62_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(ASM_UPPER_DEPS)),)
+-include $(ASM_UPPER_DEPS)
+endif
+ifneq ($(strip $(K_DEPS)),)
+-include $(K_DEPS)
+endif
+ifneq ($(strip $(C43_DEPS)),)
+-include $(C43_DEPS)
+endif
+ifneq ($(strip $(S67_DEPS)),)
+-include $(S67_DEPS)
+endif
+ifneq ($(strip $(SA_DEPS)),)
+-include $(SA_DEPS)
+endif
+ifneq ($(strip $(S43_DEPS)),)
+-include $(S43_DEPS)
+endif
+ifneq ($(strip $(OPT_DEPS)),)
+-include $(OPT_DEPS)
+endif
+ifneq ($(strip $(S64_DEPS)),)
+-include $(S64_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(C55_DEPS)),)
+-include $(C55_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all: CmdProcTISCI.out
+
+# Tool invocations
+CmdProcTISCI.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: ARM Linker'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --diag_warning=225 --display_error_number --enum_type=packed -z -m"CmdProcTISCI.map" -i"/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/lib" -i"/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --reread_libs --warn_sections --display_error_number --rom_model --be32 -o "CmdProcTISCI.out" $(ORDERED_OBJS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) $(TMS470_EXECUTABLE_OUTPUTS__QUOTED) "CmdProcTISCI.out"
+ -$(RM) "source/cmd_io.pp" "source/cmd_io_line.pp" "source/cmd_proc.pp" "source/cmd_proc_freertos_tms570.pp" "source/cmd_proc_run.pp" "source/cmdio_std_line.pp" "source/cmdio_tisci.pp" "source/commands.pp" "source/esm.pp" "source/i2str.pp" "source/notification.pp" "source/os_croutine.pp" "source/os_heap.pp" "source/os_list.pp" "source/os_port.pp" "source/os_queue.pp" "source/os_tasks.pp" "source/os_timer.pp" "source/pinmux.pp" "source/sci.pp" "source/sys_main.pp" "source/sys_phantom.pp" "source/sys_selftest.pp" "source/sys_startup.pp" "source/system.pp"
+ -$(RM) "source/cmd_io.obj" "source/cmd_io_line.obj" "source/cmd_proc.obj" "source/cmd_proc_freertos_tms570.obj" "source/cmd_proc_run.obj" "source/cmdio_std_line.obj" "source/cmdio_tisci.obj" "source/commands.obj" "source/dabort.obj" "source/esm.obj" "source/i2str.obj" "source/notification.obj" "source/os_croutine.obj" "source/os_heap.obj" "source/os_list.obj" "source/os_port.obj" "source/os_portasm.obj" "source/os_queue.obj" "source/os_tasks.obj" "source/os_timer.obj" "source/pinmux.obj" "source/sci.obj" "source/sys_core.obj" "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_phantom.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/system.obj"
+ -$(RM) "source/dabort.pp" "source/os_portasm.pp" "source/sys_core.pp" "source/sys_intvecs.pp" "source/sys_mpu.pp" "source/sys_pmu.pp"
+ -@echo 'Finished clean'
+ -@echo ' '
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS := $(GEN_CMDS__FLAG) -l"rtsv7R4_T_be_v3D16_eabi.lib"
+
--- /dev/null
+"../source/cmd_io.c" "../source/cmd_io_line.c" "../source/cmd_proc.c" "../source/cmd_proc_freertos_tms570.c" "../source/cmd_proc_run.c" "../source/cmdio_std_line.c" "../source/cmdio_tisci.c" "../source/commands.c" "../source/dabort.asm" "../source/esm.c" "../source/i2str.c" "../source/notification.c" "../source/os_croutine.c" "../source/os_heap.c" "../source/os_list.c" "../source/os_port.c" "../source/os_portasm.asm" "../source/os_queue.c" "../source/os_tasks.c" "../source/os_timer.c" "../source/pinmux.c" "../source/sci.c" "../source/sys_core.asm" "../source/sys_intvecs.asm" "../source/sys_main.c" "../source/sys_mpu.asm" "../source/sys_phantom.c" "../source/sys_pmu.asm" "../source/sys_selftest.c" "../source/sys_startup.c" "../source/system.c"
\ No newline at end of file
--- /dev/null
+# FIXED
+
+source/cmd_io.obj: ../source/cmd_io.c
+source/cmd_io.obj: ../include/cmd_proc.h
+source/cmd_io.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/cmd_io.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/cmd_io.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdint.h
+
+../source/cmd_io.c:
+../include/cmd_proc.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdint.h:
--- /dev/null
+# FIXED
+
+source/cmd_io_line.obj: ../source/cmd_io_line.c
+source/cmd_io_line.obj: ../include/cmd_proc.h
+source/cmd_io_line.obj: ../include/cmd_proc_priv.h
+source/cmd_io_line.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h
+source/cmd_io_line.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/cmd_io_line.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h
+source/cmd_io_line.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+
+../source/cmd_io_line.c:
+../include/cmd_proc.h:
+../include/cmd_proc_priv.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
--- /dev/null
+# FIXED
+
+source/cmd_proc.obj: ../source/cmd_proc.c
+source/cmd_proc.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdint.h
+source/cmd_proc.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/ctype.h
+source/cmd_proc.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/cmd_proc.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/_isfuncdcl.h
+source/cmd_proc.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/cmd_proc.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h
+source/cmd_proc.obj: ../include/i2str.h
+source/cmd_proc.obj: ../include/cmd_proc.h
+source/cmd_proc.obj: ../include/cmd_proc_priv.h
+source/cmd_proc.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h
+source/cmd_proc.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h
+
+../source/cmd_proc.c:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdint.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/ctype.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/_isfuncdcl.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h:
+../include/i2str.h:
+../include/cmd_proc.h:
+../include/cmd_proc_priv.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h:
--- /dev/null
+# FIXED
+
+source/cmd_proc_freertos_tms570.obj: ../source/cmd_proc_freertos_tms570.c
+source/cmd_proc_freertos_tms570.obj: ../include/cmd_proc_freertos_tms570.h
+source/cmd_proc_freertos_tms570.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/cmd_proc_freertos_tms570.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/cmd_proc_freertos_tms570.obj: ../include/cmd_proc.h
+source/cmd_proc_freertos_tms570.obj: ../include/cmdio_tisci.h
+source/cmd_proc_freertos_tms570.obj: ../include/FreeRTOS.h
+source/cmd_proc_freertos_tms570.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/cmd_proc_freertos_tms570.obj: ../include/os_projdefs.h
+source/cmd_proc_freertos_tms570.obj: ../include/FreeRTOSConfig.h
+source/cmd_proc_freertos_tms570.obj: ../include/os_portable.h
+source/cmd_proc_freertos_tms570.obj: ../include/os_portmacro.h
+source/cmd_proc_freertos_tms570.obj: ../include/os_mpu_wrappers.h
+source/cmd_proc_freertos_tms570.obj: ../include/sys_core.h
+source/cmd_proc_freertos_tms570.obj: ../include/sys_common.h
+source/cmd_proc_freertos_tms570.obj: ../include/os_queue.h
+source/cmd_proc_freertos_tms570.obj: ../include/os_semphr.h
+source/cmd_proc_freertos_tms570.obj: ../include/sci.h
+source/cmd_proc_freertos_tms570.obj: ../include/gio.h
+source/cmd_proc_freertos_tms570.obj: ../include/os_task.h
+source/cmd_proc_freertos_tms570.obj: ../include/os_list.h
+
+../source/cmd_proc_freertos_tms570.c:
+../include/cmd_proc_freertos_tms570.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+../include/cmd_proc.h:
+../include/cmdio_tisci.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_queue.h:
+../include/os_semphr.h:
+../include/sci.h:
+../include/gio.h:
+../include/os_task.h:
+../include/os_list.h:
--- /dev/null
+# FIXED
+
+source/cmd_proc_run.obj: ../source/cmd_proc_run.c
+source/cmd_proc_run.obj: ../include/cmd_proc.h
+source/cmd_proc_run.obj: ../include/cmd_proc_priv.h
+source/cmd_proc_run.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h
+source/cmd_proc_run.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/cmd_proc_run.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h
+
+../source/cmd_proc_run.c:
+../include/cmd_proc.h:
+../include/cmd_proc_priv.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h:
--- /dev/null
+# FIXED
+
+source/cmdio_std_line.obj: ../source/cmdio_std_line.c
+source/cmdio_std_line.obj: ../include/cmd_proc.h
+source/cmdio_std_line.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/cmdio_std_line.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+
+../source/cmdio_std_line.c:
+../include/cmd_proc.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
--- /dev/null
+# FIXED
+
+source/cmdio_tisci.obj: ../source/cmdio_tisci.c
+source/cmdio_tisci.obj: ../include/cmdio_tisci.h
+source/cmdio_tisci.obj: ../include/cmd_proc.h
+source/cmdio_tisci.obj: ../include/FreeRTOS.h
+source/cmdio_tisci.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/cmdio_tisci.obj: ../include/os_projdefs.h
+source/cmdio_tisci.obj: ../include/FreeRTOSConfig.h
+source/cmdio_tisci.obj: ../include/os_portable.h
+source/cmdio_tisci.obj: ../include/os_portmacro.h
+source/cmdio_tisci.obj: ../include/os_mpu_wrappers.h
+source/cmdio_tisci.obj: ../include/sys_core.h
+source/cmdio_tisci.obj: ../include/sys_common.h
+source/cmdio_tisci.obj: ../include/os_queue.h
+source/cmdio_tisci.obj: ../include/os_semphr.h
+
+../source/cmdio_tisci.c:
+../include/cmdio_tisci.h:
+../include/cmd_proc.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_queue.h:
+../include/os_semphr.h:
--- /dev/null
+# FIXED
+
+source/commands.obj: ../source/commands.c
+source/commands.obj: ../include/cmd_proc.h
+source/commands.obj: ../include/sys_common.h
+source/commands.obj: ../include/cmdio_tisci.h
+source/commands.obj: ../include/FreeRTOS.h
+source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/commands.obj: ../include/os_projdefs.h
+source/commands.obj: ../include/FreeRTOSConfig.h
+source/commands.obj: ../include/os_portable.h
+source/commands.obj: ../include/os_portmacro.h
+source/commands.obj: ../include/os_mpu_wrappers.h
+source/commands.obj: ../include/sys_core.h
+source/commands.obj: ../include/os_queue.h
+source/commands.obj: ../include/os_semphr.h
+source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h
+source/commands.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h
+
+../source/commands.c:
+../include/cmd_proc.h:
+../include/sys_common.h:
+../include/cmdio_tisci.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/os_queue.h:
+../include/os_semphr.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h:
--- /dev/null
+# FIXED
+
+source/esm.obj: ../source/esm.c
+source/esm.obj: ../include/esm.h
+source/esm.obj: ../include/sys_common.h
+
+../source/esm.c:
+../include/esm.h:
+../include/sys_common.h:
--- /dev/null
+# FIXED
+
+source/i2str.obj: ../source/i2str.c
+source/i2str.obj: ../include/i2str.h
+
+../source/i2str.c:
+../include/i2str.h:
--- /dev/null
+# FIXED
+
+source/notification.obj: ../source/notification.c
+source/notification.obj: ../include/esm.h
+source/notification.obj: ../include/sys_common.h
+source/notification.obj: ../include/sys_selftest.h
+source/notification.obj: ../include/sys_core.h
+source/notification.obj: ../include/system.h
+source/notification.obj: ../include/gio.h
+source/notification.obj: ../include/sys_vim.h
+source/notification.obj: ../include/adc.h
+source/notification.obj: ../include/can.h
+source/notification.obj: ../include/mibspi.h
+source/notification.obj: ../include/gio.h
+source/notification.obj: ../include/het.h
+source/notification.obj: ../include/gio.h
+source/notification.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/notification.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/notification.obj: ../include/htu.h
+source/notification.obj: ../include/sci.h
+source/notification.obj: ../include/gio.h
+source/notification.obj: ../include/FreeRTOS.h
+source/notification.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/notification.obj: ../include/os_projdefs.h
+source/notification.obj: ../include/FreeRTOSConfig.h
+source/notification.obj: ../include/os_portable.h
+source/notification.obj: ../include/os_portmacro.h
+source/notification.obj: ../include/os_mpu_wrappers.h
+source/notification.obj: ../include/os_semphr.h
+source/notification.obj: ../include/os_queue.h
+source/notification.obj: ../include/os_task.h
+source/notification.obj: ../include/os_list.h
+
+../source/notification.c:
+../include/esm.h:
+../include/sys_common.h:
+../include/sys_selftest.h:
+../include/sys_core.h:
+../include/system.h:
+../include/gio.h:
+../include/sys_vim.h:
+../include/adc.h:
+../include/can.h:
+../include/mibspi.h:
+../include/gio.h:
+../include/het.h:
+../include/gio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+../include/htu.h:
+../include/sci.h:
+../include/gio.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/os_semphr.h:
+../include/os_queue.h:
+../include/os_task.h:
+../include/os_list.h:
--- /dev/null
+# FIXED
+
+source/os_croutine.obj: ../source/os_croutine.c
+source/os_croutine.obj: ../include/FreeRTOS.h
+source/os_croutine.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/os_croutine.obj: ../include/os_projdefs.h
+source/os_croutine.obj: ../include/FreeRTOSConfig.h
+source/os_croutine.obj: ../include/os_portable.h
+source/os_croutine.obj: ../include/os_portmacro.h
+source/os_croutine.obj: ../include/os_mpu_wrappers.h
+source/os_croutine.obj: ../include/sys_core.h
+source/os_croutine.obj: ../include/sys_common.h
+source/os_croutine.obj: ../include/os_task.h
+source/os_croutine.obj: ../include/os_list.h
+source/os_croutine.obj: ../include/os_croutine.h
+
+../source/os_croutine.c:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_task.h:
+../include/os_list.h:
+../include/os_croutine.h:
--- /dev/null
+# FIXED
+
+source/os_heap.obj: ../source/os_heap.c
+source/os_heap.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h
+source/os_heap.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/os_heap.obj: ../include/FreeRTOS.h
+source/os_heap.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/os_heap.obj: ../include/os_projdefs.h
+source/os_heap.obj: ../include/FreeRTOSConfig.h
+source/os_heap.obj: ../include/os_portable.h
+source/os_heap.obj: ../include/os_portmacro.h
+source/os_heap.obj: ../include/os_mpu_wrappers.h
+source/os_heap.obj: ../include/sys_core.h
+source/os_heap.obj: ../include/sys_common.h
+source/os_heap.obj: ../include/os_task.h
+source/os_heap.obj: ../include/os_list.h
+
+../source/os_heap.c:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_task.h:
+../include/os_list.h:
--- /dev/null
+# FIXED
+
+source/os_list.obj: ../source/os_list.c
+source/os_list.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h
+source/os_list.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/os_list.obj: ../include/FreeRTOS.h
+source/os_list.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/os_list.obj: ../include/os_projdefs.h
+source/os_list.obj: ../include/FreeRTOSConfig.h
+source/os_list.obj: ../include/os_portable.h
+source/os_list.obj: ../include/os_portmacro.h
+source/os_list.obj: ../include/os_mpu_wrappers.h
+source/os_list.obj: ../include/sys_core.h
+source/os_list.obj: ../include/sys_common.h
+source/os_list.obj: ../include/os_list.h
+
+../source/os_list.c:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_list.h:
--- /dev/null
+# FIXED
+
+source/os_port.obj: ../source/os_port.c
+source/os_port.obj: ../include/FreeRTOS.h
+source/os_port.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/os_port.obj: ../include/os_projdefs.h
+source/os_port.obj: ../include/FreeRTOSConfig.h
+source/os_port.obj: ../include/os_portable.h
+source/os_port.obj: ../include/os_portmacro.h
+source/os_port.obj: ../include/os_mpu_wrappers.h
+source/os_port.obj: ../include/sys_core.h
+source/os_port.obj: ../include/sys_common.h
+source/os_port.obj: ../include/os_task.h
+source/os_port.obj: ../include/os_list.h
+
+../source/os_port.c:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_task.h:
+../include/os_list.h:
--- /dev/null
+# FIXED
+
+source/os_queue.obj: ../source/os_queue.c
+source/os_queue.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h
+source/os_queue.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/os_queue.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/os_queue.obj: ../include/FreeRTOS.h
+source/os_queue.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/os_queue.obj: ../include/os_projdefs.h
+source/os_queue.obj: ../include/FreeRTOSConfig.h
+source/os_queue.obj: ../include/os_portable.h
+source/os_queue.obj: ../include/os_portmacro.h
+source/os_queue.obj: ../include/os_mpu_wrappers.h
+source/os_queue.obj: ../include/sys_core.h
+source/os_queue.obj: ../include/sys_common.h
+source/os_queue.obj: ../include/os_task.h
+source/os_queue.obj: ../include/os_list.h
+
+../source/os_queue.c:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_task.h:
+../include/os_list.h:
--- /dev/null
+# FIXED
+
+source/os_tasks.obj: ../source/os_tasks.c
+source/os_tasks.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h
+source/os_tasks.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/os_tasks.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h
+source/os_tasks.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h
+source/os_tasks.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/os_tasks.obj: ../include/FreeRTOS.h
+source/os_tasks.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/os_tasks.obj: ../include/os_projdefs.h
+source/os_tasks.obj: ../include/FreeRTOSConfig.h
+source/os_tasks.obj: ../include/os_portable.h
+source/os_tasks.obj: ../include/os_portmacro.h
+source/os_tasks.obj: ../include/os_mpu_wrappers.h
+source/os_tasks.obj: ../include/sys_core.h
+source/os_tasks.obj: ../include/sys_common.h
+source/os_tasks.obj: ../include/os_task.h
+source/os_tasks.obj: ../include/os_list.h
+source/os_tasks.obj: ../include/os_timer.h
+source/os_tasks.obj: ../include/os_StackMacros.h
+
+../source/os_tasks.c:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdarg.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stdlib.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_task.h:
+../include/os_list.h:
+../include/os_timer.h:
+../include/os_StackMacros.h:
--- /dev/null
+# FIXED
+
+source/os_timer.obj: ../source/os_timer.c
+source/os_timer.obj: ../include/FreeRTOS.h
+source/os_timer.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/os_timer.obj: ../include/os_projdefs.h
+source/os_timer.obj: ../include/FreeRTOSConfig.h
+source/os_timer.obj: ../include/os_portable.h
+source/os_timer.obj: ../include/os_portmacro.h
+source/os_timer.obj: ../include/os_mpu_wrappers.h
+source/os_timer.obj: ../include/sys_core.h
+source/os_timer.obj: ../include/sys_common.h
+source/os_timer.obj: ../include/os_task.h
+source/os_timer.obj: ../include/os_list.h
+source/os_timer.obj: ../include/os_queue.h
+source/os_timer.obj: ../include/os_timer.h
+
+../source/os_timer.c:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/sys_common.h:
+../include/os_task.h:
+../include/os_list.h:
+../include/os_queue.h:
+../include/os_timer.h:
--- /dev/null
+# FIXED
+
+source/pinmux.obj: ../source/pinmux.c
+source/pinmux.obj: ../include/pinmux.h
+source/pinmux.obj: ../include/sys_common.h
+
+../source/pinmux.c:
+../include/pinmux.h:
+../include/sys_common.h:
--- /dev/null
+# FIXED
+
+source/sci.obj: ../source/sci.c
+source/sci.obj: ../include/sci.h
+source/sci.obj: ../include/sys_common.h
+source/sci.obj: ../include/gio.h
+source/sci.obj: ../include/cmdio_tisci.h
+source/sci.obj: ../include/cmd_proc.h
+source/sci.obj: ../include/FreeRTOS.h
+source/sci.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/sci.obj: ../include/os_projdefs.h
+source/sci.obj: ../include/FreeRTOSConfig.h
+source/sci.obj: ../include/os_portable.h
+source/sci.obj: ../include/os_portmacro.h
+source/sci.obj: ../include/os_mpu_wrappers.h
+source/sci.obj: ../include/sys_core.h
+source/sci.obj: ../include/os_queue.h
+source/sci.obj: ../include/os_semphr.h
+
+../source/sci.c:
+../include/sci.h:
+../include/sys_common.h:
+../include/gio.h:
+../include/cmdio_tisci.h:
+../include/cmd_proc.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/os_queue.h:
+../include/os_semphr.h:
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Each subdirectory must supply rules for building sources it contributes
+source/cmd_io.obj: ../source/cmd_io.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/cmd_io.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/cmd_io_line.obj: ../source/cmd_io_line.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/cmd_io_line.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/cmd_proc.obj: ../source/cmd_proc.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/cmd_proc.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/cmd_proc_freertos_tms570.obj: ../source/cmd_proc_freertos_tms570.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/cmd_proc_freertos_tms570.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/cmd_proc_run.obj: ../source/cmd_proc_run.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/cmd_proc_run.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/cmdio_std_line.obj: ../source/cmdio_std_line.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/cmdio_std_line.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/cmdio_tisci.obj: ../source/cmdio_tisci.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/cmdio_tisci.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/commands.obj: ../source/commands.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/commands.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/dabort.obj: ../source/dabort.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/dabort.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/esm.obj: ../source/esm.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/esm.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/i2str.obj: ../source/i2str.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/i2str.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/notification.obj: ../source/notification.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/notification.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/os_croutine.obj: ../source/os_croutine.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/os_croutine.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/os_heap.obj: ../source/os_heap.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/os_heap.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/os_list.obj: ../source/os_list.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/os_list.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/os_port.obj: ../source/os_port.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/os_port.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/os_portasm.obj: ../source/os_portasm.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/os_portasm.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/os_queue.obj: ../source/os_queue.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/os_queue.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/os_tasks.obj: ../source/os_tasks.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/os_tasks.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/os_timer.obj: ../source/os_timer.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/os_timer.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/pinmux.obj: ../source/pinmux.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/pinmux.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sci.obj: ../source/sci.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sci.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sys_core.obj: ../source/sys_core.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sys_core.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sys_intvecs.obj: ../source/sys_intvecs.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sys_intvecs.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sys_main.obj: ../source/sys_main.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sys_main.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sys_mpu.obj: ../source/sys_mpu.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sys_mpu.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sys_phantom.obj: ../source/sys_phantom.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sys_phantom.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sys_pmu.obj: ../source/sys_pmu.asm $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sys_pmu.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sys_selftest.obj: ../source/sys_selftest.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sys_selftest.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/sys_startup.obj: ../source/sys_startup.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/sys_startup.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+source/system.obj: ../source/system.c $(GEN_OPTS) $(GEN_SRCS)
+ @echo 'Building file: $<'
+ @echo 'Invoking: ARM Compiler'
+ "/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/bin/cl470" -mv7R4 --code_state=32 --float_support=VFPv3D16 --abi=eabi -g --include_path="/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include" --include_path="../include" --diag_warning=225 --display_error_number --enum_type=packed --preproc_with_compile --preproc_dependency="source/system.pp" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+CMD_SRCS += \
+../source/sys_link.cmd
+
+ASM_SRCS += \
+../source/dabort.asm \
+../source/os_portasm.asm \
+../source/sys_core.asm \
+../source/sys_intvecs.asm \
+../source/sys_mpu.asm \
+../source/sys_pmu.asm
+
+C_SRCS += \
+../source/cmd_io.c \
+../source/cmd_io_line.c \
+../source/cmd_proc.c \
+../source/cmd_proc_freertos_tms570.c \
+../source/cmd_proc_run.c \
+../source/cmdio_std_line.c \
+../source/cmdio_tisci.c \
+../source/commands.c \
+../source/esm.c \
+../source/i2str.c \
+../source/notification.c \
+../source/os_croutine.c \
+../source/os_heap.c \
+../source/os_list.c \
+../source/os_port.c \
+../source/os_queue.c \
+../source/os_tasks.c \
+../source/os_timer.c \
+../source/pinmux.c \
+../source/sci.c \
+../source/sys_main.c \
+../source/sys_phantom.c \
+../source/sys_selftest.c \
+../source/sys_startup.c \
+../source/system.c
+
+OBJS += \
+./source/cmd_io.obj \
+./source/cmd_io_line.obj \
+./source/cmd_proc.obj \
+./source/cmd_proc_freertos_tms570.obj \
+./source/cmd_proc_run.obj \
+./source/cmdio_std_line.obj \
+./source/cmdio_tisci.obj \
+./source/commands.obj \
+./source/dabort.obj \
+./source/esm.obj \
+./source/i2str.obj \
+./source/notification.obj \
+./source/os_croutine.obj \
+./source/os_heap.obj \
+./source/os_list.obj \
+./source/os_port.obj \
+./source/os_portasm.obj \
+./source/os_queue.obj \
+./source/os_tasks.obj \
+./source/os_timer.obj \
+./source/pinmux.obj \
+./source/sci.obj \
+./source/sys_core.obj \
+./source/sys_intvecs.obj \
+./source/sys_main.obj \
+./source/sys_mpu.obj \
+./source/sys_phantom.obj \
+./source/sys_pmu.obj \
+./source/sys_selftest.obj \
+./source/sys_startup.obj \
+./source/system.obj
+
+ASM_DEPS += \
+./source/dabort.pp \
+./source/os_portasm.pp \
+./source/sys_core.pp \
+./source/sys_intvecs.pp \
+./source/sys_mpu.pp \
+./source/sys_pmu.pp
+
+C_DEPS += \
+./source/cmd_io.pp \
+./source/cmd_io_line.pp \
+./source/cmd_proc.pp \
+./source/cmd_proc_freertos_tms570.pp \
+./source/cmd_proc_run.pp \
+./source/cmdio_std_line.pp \
+./source/cmdio_tisci.pp \
+./source/commands.pp \
+./source/esm.pp \
+./source/i2str.pp \
+./source/notification.pp \
+./source/os_croutine.pp \
+./source/os_heap.pp \
+./source/os_list.pp \
+./source/os_port.pp \
+./source/os_queue.pp \
+./source/os_tasks.pp \
+./source/os_timer.pp \
+./source/pinmux.pp \
+./source/sci.pp \
+./source/sys_main.pp \
+./source/sys_phantom.pp \
+./source/sys_selftest.pp \
+./source/sys_startup.pp \
+./source/system.pp
+
+C_DEPS__QUOTED += \
+"source/cmd_io.pp" \
+"source/cmd_io_line.pp" \
+"source/cmd_proc.pp" \
+"source/cmd_proc_freertos_tms570.pp" \
+"source/cmd_proc_run.pp" \
+"source/cmdio_std_line.pp" \
+"source/cmdio_tisci.pp" \
+"source/commands.pp" \
+"source/esm.pp" \
+"source/i2str.pp" \
+"source/notification.pp" \
+"source/os_croutine.pp" \
+"source/os_heap.pp" \
+"source/os_list.pp" \
+"source/os_port.pp" \
+"source/os_queue.pp" \
+"source/os_tasks.pp" \
+"source/os_timer.pp" \
+"source/pinmux.pp" \
+"source/sci.pp" \
+"source/sys_main.pp" \
+"source/sys_phantom.pp" \
+"source/sys_selftest.pp" \
+"source/sys_startup.pp" \
+"source/system.pp"
+
+OBJS__QUOTED += \
+"source/cmd_io.obj" \
+"source/cmd_io_line.obj" \
+"source/cmd_proc.obj" \
+"source/cmd_proc_freertos_tms570.obj" \
+"source/cmd_proc_run.obj" \
+"source/cmdio_std_line.obj" \
+"source/cmdio_tisci.obj" \
+"source/commands.obj" \
+"source/dabort.obj" \
+"source/esm.obj" \
+"source/i2str.obj" \
+"source/notification.obj" \
+"source/os_croutine.obj" \
+"source/os_heap.obj" \
+"source/os_list.obj" \
+"source/os_port.obj" \
+"source/os_portasm.obj" \
+"source/os_queue.obj" \
+"source/os_tasks.obj" \
+"source/os_timer.obj" \
+"source/pinmux.obj" \
+"source/sci.obj" \
+"source/sys_core.obj" \
+"source/sys_intvecs.obj" \
+"source/sys_main.obj" \
+"source/sys_mpu.obj" \
+"source/sys_phantom.obj" \
+"source/sys_pmu.obj" \
+"source/sys_selftest.obj" \
+"source/sys_startup.obj" \
+"source/system.obj"
+
+ASM_DEPS__QUOTED += \
+"source/dabort.pp" \
+"source/os_portasm.pp" \
+"source/sys_core.pp" \
+"source/sys_intvecs.pp" \
+"source/sys_mpu.pp" \
+"source/sys_pmu.pp"
+
+C_SRCS__QUOTED += \
+"../source/cmd_io.c" \
+"../source/cmd_io_line.c" \
+"../source/cmd_proc.c" \
+"../source/cmd_proc_freertos_tms570.c" \
+"../source/cmd_proc_run.c" \
+"../source/cmdio_std_line.c" \
+"../source/cmdio_tisci.c" \
+"../source/commands.c" \
+"../source/esm.c" \
+"../source/i2str.c" \
+"../source/notification.c" \
+"../source/os_croutine.c" \
+"../source/os_heap.c" \
+"../source/os_list.c" \
+"../source/os_port.c" \
+"../source/os_queue.c" \
+"../source/os_tasks.c" \
+"../source/os_timer.c" \
+"../source/pinmux.c" \
+"../source/sci.c" \
+"../source/sys_main.c" \
+"../source/sys_phantom.c" \
+"../source/sys_selftest.c" \
+"../source/sys_startup.c" \
+"../source/system.c"
+
+ASM_SRCS__QUOTED += \
+"../source/dabort.asm" \
+"../source/os_portasm.asm" \
+"../source/sys_core.asm" \
+"../source/sys_intvecs.asm" \
+"../source/sys_mpu.asm" \
+"../source/sys_pmu.asm"
+
+
--- /dev/null
+# FIXED
+
+source/sys_main.obj: ../source/sys_main.c
+source/sys_main.obj: ../include/sys_common.h
+source/sys_main.obj: ../include/system.h
+source/sys_main.obj: ../include/gio.h
+source/sys_main.obj: ../include/cmd_proc_freertos_tms570.h
+source/sys_main.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/sys_main.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/sys_main.obj: ../include/cmd_proc.h
+source/sys_main.obj: ../include/cmdio_tisci.h
+source/sys_main.obj: ../include/FreeRTOS.h
+source/sys_main.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h
+source/sys_main.obj: ../include/os_projdefs.h
+source/sys_main.obj: ../include/FreeRTOSConfig.h
+source/sys_main.obj: ../include/os_portable.h
+source/sys_main.obj: ../include/os_portmacro.h
+source/sys_main.obj: ../include/os_mpu_wrappers.h
+source/sys_main.obj: ../include/sys_core.h
+source/sys_main.obj: ../include/os_queue.h
+source/sys_main.obj: ../include/os_semphr.h
+source/sys_main.obj: ../include/sci.h
+source/sys_main.obj: ../include/gio.h
+source/sys_main.obj: ../include/os_task.h
+source/sys_main.obj: ../include/os_list.h
+
+../source/sys_main.c:
+../include/sys_common.h:
+../include/system.h:
+../include/gio.h:
+../include/cmd_proc_freertos_tms570.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+../include/cmd_proc.h:
+../include/cmdio_tisci.h:
+../include/FreeRTOS.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/stddef.h:
+../include/os_projdefs.h:
+../include/FreeRTOSConfig.h:
+../include/os_portable.h:
+../include/os_portmacro.h:
+../include/os_mpu_wrappers.h:
+../include/sys_core.h:
+../include/os_queue.h:
+../include/os_semphr.h:
+../include/sci.h:
+../include/gio.h:
+../include/os_task.h:
+../include/os_list.h:
--- /dev/null
+# FIXED
+
+source/sys_phantom.obj: ../source/sys_phantom.c
+
+../source/sys_phantom.c:
--- /dev/null
+# FIXED
+
+source/sys_selftest.obj: ../source/sys_selftest.c
+source/sys_selftest.obj: ../include/sys_selftest.h
+source/sys_selftest.obj: ../include/sys_common.h
+source/sys_selftest.obj: ../include/sys_core.h
+source/sys_selftest.obj: ../include/system.h
+source/sys_selftest.obj: ../include/gio.h
+source/sys_selftest.obj: ../include/sys_vim.h
+source/sys_selftest.obj: ../include/adc.h
+source/sys_selftest.obj: ../include/can.h
+source/sys_selftest.obj: ../include/mibspi.h
+source/sys_selftest.obj: ../include/gio.h
+source/sys_selftest.obj: ../include/het.h
+source/sys_selftest.obj: ../include/gio.h
+source/sys_selftest.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/sys_selftest.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/sys_selftest.obj: ../include/htu.h
+source/sys_selftest.obj: ../include/esm.h
+
+../source/sys_selftest.c:
+../include/sys_selftest.h:
+../include/sys_common.h:
+../include/sys_core.h:
+../include/system.h:
+../include/gio.h:
+../include/sys_vim.h:
+../include/adc.h:
+../include/can.h:
+../include/mibspi.h:
+../include/gio.h:
+../include/het.h:
+../include/gio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+../include/htu.h:
+../include/esm.h:
--- /dev/null
+# FIXED
+
+source/sys_startup.obj: ../source/sys_startup.c
+source/sys_startup.obj: ../include/sys_common.h
+source/sys_startup.obj: ../include/system.h
+source/sys_startup.obj: ../include/gio.h
+source/sys_startup.obj: ../include/sys_vim.h
+source/sys_startup.obj: ../include/sys_core.h
+source/sys_startup.obj: ../include/sys_selftest.h
+source/sys_startup.obj: ../include/adc.h
+source/sys_startup.obj: ../include/can.h
+source/sys_startup.obj: ../include/mibspi.h
+source/sys_startup.obj: ../include/gio.h
+source/sys_startup.obj: ../include/het.h
+source/sys_startup.obj: ../include/gio.h
+source/sys_startup.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/sys_startup.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/sys_startup.obj: ../include/htu.h
+source/sys_startup.obj: ../include/esm.h
+
+../source/sys_startup.c:
+../include/sys_common.h:
+../include/system.h:
+../include/gio.h:
+../include/sys_vim.h:
+../include/sys_core.h:
+../include/sys_selftest.h:
+../include/adc.h:
+../include/can.h:
+../include/mibspi.h:
+../include/gio.h:
+../include/het.h:
+../include/gio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+../include/htu.h:
+../include/esm.h:
--- /dev/null
+# FIXED
+
+source/system.obj: ../source/system.c
+source/system.obj: ../include/system.h
+source/system.obj: ../include/sys_common.h
+source/system.obj: ../include/gio.h
+source/system.obj: ../include/sys_selftest.h
+source/system.obj: ../include/sys_core.h
+source/system.obj: ../include/sys_vim.h
+source/system.obj: ../include/adc.h
+source/system.obj: ../include/can.h
+source/system.obj: ../include/mibspi.h
+source/system.obj: ../include/gio.h
+source/system.obj: ../include/het.h
+source/system.obj: ../include/gio.h
+source/system.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h
+source/system.obj: /opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h
+source/system.obj: ../include/htu.h
+source/system.obj: ../include/esm.h
+source/system.obj: ../include/pinmux.h
+
+../source/system.c:
+../include/system.h:
+../include/sys_common.h:
+../include/gio.h:
+../include/sys_selftest.h:
+../include/sys_core.h:
+../include/sys_vim.h:
+../include/adc.h:
+../include/can.h:
+../include/mibspi.h:
+../include/gio.h:
+../include/het.h:
+../include/gio.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/string.h:
+/opt/ti/ccsv5/tools/compiler/tms470_4.9.1/include/linkage.h:
+../include/htu.h:
+../include/esm.h:
+../include/pinmux.h:
--- /dev/null
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+O_SRCS :=
+CPP_SRCS :=
+K_SRCS :=
+LD_SRCS :=
+S67_SRCS :=
+CMD_SRCS :=
+CXX_SRCS :=
+CMD_UPPER_SRCS :=
+C43_SRCS :=
+S55_SRCS :=
+LD_UPPER_SRCS :=
+C62_SRCS :=
+S_UPPER_SRCS :=
+A_SRCS :=
+C55_SRCS :=
+SA_SRCS :=
+C_UPPER_SRCS :=
+OBJ_SRCS :=
+S62_SRCS :=
+LIB_SRCS :=
+ASM_SRCS :=
+S??_SRCS :=
+C++_SRCS :=
+CLA_SRCS :=
+ASM_UPPER_SRCS :=
+C_SRCS :=
+C67_SRCS :=
+S_SRCS :=
+S43_SRCS :=
+OPT_SRCS :=
+C64_SRCS :=
+C??_SRCS :=
+CC_SRCS :=
+S64_SRCS :=
+OBJS :=
+S_DEPS :=
+S_UPPER_DEPS :=
+S62_DEPS :=
+C64_DEPS :=
+ASM_DEPS :=
+CC_DEPS :=
+S55_DEPS :=
+C67_DEPS :=
+C??_DEPS :=
+CLA_DEPS :=
+CPP_DEPS :=
+TMS470_EXECUTABLE_OUTPUTS :=
+S??_DEPS :=
+C_DEPS :=
+C62_DEPS :=
+CXX_DEPS :=
+C++_DEPS :=
+ASM_UPPER_DEPS :=
+K_DEPS :=
+C43_DEPS :=
+S67_DEPS :=
+SA_DEPS :=
+S43_DEPS :=
+OPT_DEPS :=
+S64_DEPS :=
+C_UPPER_DEPS :=
+C55_DEPS :=
+CPP_DEPS__QUOTED :=
+C67_DEPS__QUOTED :=
+C??_DEPS__QUOTED :=
+TMS470_EXECUTABLE_OUTPUTS__QUOTED :=
+S_UPPER_DEPS__QUOTED :=
+CLA_DEPS__QUOTED :=
+ASM_UPPER_DEPS__QUOTED :=
+C62_DEPS__QUOTED :=
+CXX_DEPS__QUOTED :=
+S67_DEPS__QUOTED :=
+C_DEPS__QUOTED :=
+C_UPPER_DEPS__QUOTED :=
+OPT_DEPS__QUOTED :=
+S_DEPS__QUOTED :=
+S??_DEPS__QUOTED :=
+K_DEPS__QUOTED :=
+C64_DEPS__QUOTED :=
+C++_DEPS__QUOTED :=
+OBJS__QUOTED :=
+S43_DEPS__QUOTED :=
+CC_DEPS__QUOTED :=
+S55_DEPS__QUOTED :=
+C55_DEPS__QUOTED :=
+SA_DEPS__QUOTED :=
+C43_DEPS__QUOTED :=
+S62_DEPS__QUOTED :=
+ASM_DEPS__QUOTED :=
+S64_DEPS__QUOTED :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+source \
+
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef INC_FREERTOS_H\r
+#define INC_FREERTOS_H\r
+\r
+\r
+/*\r
+ * Include the generic headers required for the FreeRTOS port being used.\r
+ */\r
+#include <stddef.h>\r
+\r
+/* Basic FreeRTOS definitions. */\r
+#include "os_projdefs.h"\r
+\r
+/* Application specific configuration options. */\r
+#include "FreeRTOSConfig.h"\r
+\r
+/* Definitions specific to the port being used. */\r
+#include "os_portable.h"\r
+\r
+/* Definitions specific R4 core. */\r
+#include "sys_core.h"\r
+\r
+/* Defines the prototype to which the application task hook function must\r
+conform. */\r
+typedef portBASE_TYPE (*pdTASK_HOOK_CODE)( void * );\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Check all the required application specific macros have been defined.\r
+ * These macros are application specific and (as downloaded) are defined\r
+ * within FreeRTOSConfig.h.\r
+ */\r
+\r
+#ifndef configUSE_PREEMPTION\r
+ #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_IDLE_HOOK\r
+ #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_TICK_HOOK\r
+ #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_CO_ROUTINES\r
+ #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskPrioritySet\r
+ #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_uxTaskPriorityGet\r
+ #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelete \r
+ #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskSuspend \r
+ #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelayUntil\r
+ #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_vTaskDelay\r
+ #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef configUSE_16_BIT_TICKS\r
+ #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.\r
+#endif\r
+\r
+#ifndef INCLUDE_xTaskGetIdleTaskHandle\r
+ #define INCLUDE_xTaskGetIdleTaskHandle 0\r
+#endif\r
+\r
+#ifndef INCLUDE_xTimerGetTimerDaemonTaskHandle\r
+ #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0\r
+#endif\r
+\r
+#ifndef INCLUDE_pcTaskGetTaskName\r
+ #define INCLUDE_pcTaskGetTaskName 0\r
+#endif\r
+\r
+#ifndef configUSE_APPLICATION_TASK_TAG\r
+ #define configUSE_APPLICATION_TASK_TAG 0\r
+#endif\r
+\r
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark\r
+ #define INCLUDE_uxTaskGetStackHighWaterMark 0\r
+#endif\r
+\r
+#ifndef configUSE_RECURSIVE_MUTEXES\r
+ #define configUSE_RECURSIVE_MUTEXES 0\r
+#endif\r
+\r
+#ifndef configUSE_MUTEXES\r
+ #define configUSE_MUTEXES 0\r
+#endif\r
+\r
+#ifndef configUSE_TIMERS\r
+ #define configUSE_TIMERS 0\r
+#endif\r
+\r
+#ifndef configUSE_COUNTING_SEMAPHORES\r
+ #define configUSE_COUNTING_SEMAPHORES 0\r
+#endif\r
+\r
+#ifndef configUSE_ALTERNATIVE_API\r
+ #define configUSE_ALTERNATIVE_API 0\r
+#endif\r
+\r
+#ifndef portCRITICAL_NESTING_IN_TCB\r
+ #define portCRITICAL_NESTING_IN_TCB 0\r
+#endif\r
+\r
+#ifndef configMAX_TASK_NAME_LEN\r
+ #define configMAX_TASK_NAME_LEN 16\r
+#endif\r
+\r
+#ifndef configIDLE_SHOULD_YIELD\r
+ #define configIDLE_SHOULD_YIELD 1\r
+#endif\r
+\r
+#if configMAX_TASK_NAME_LEN < 1\r
+ #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h\r
+#endif\r
+\r
+#ifndef INCLUDE_xTaskResumeFromISR\r
+ #define INCLUDE_xTaskResumeFromISR 1\r
+#endif\r
+\r
+#ifndef configASSERT\r
+ #define configASSERT( x )\r
+#endif\r
+\r
+/* The timers module relies on xTaskGetSchedulerState(). */\r
+#if configUSE_TIMERS == 1\r
+\r
+ #ifndef configTIMER_TASK_PRIORITY\r
+ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.\r
+ #endif /* configTIMER_TASK_PRIORITY */\r
+\r
+ #ifndef configTIMER_QUEUE_LENGTH\r
+ #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.\r
+ #endif /* configTIMER_QUEUE_LENGTH */\r
+\r
+ #ifndef configTIMER_TASK_STACK_DEPTH\r
+ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.\r
+ #endif /* configTIMER_TASK_STACK_DEPTH */\r
+\r
+#endif /* configUSE_TIMERS */\r
+\r
+#ifndef INCLUDE_xTaskGetSchedulerState\r
+ #define INCLUDE_xTaskGetSchedulerState 0\r
+#endif\r
+\r
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle\r
+ #define INCLUDE_xTaskGetCurrentTaskHandle 0\r
+#endif\r
+\r
+\r
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR\r
+ #define portSET_INTERRUPT_MASK_FROM_ISR() 0\r
+#endif\r
+\r
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR\r
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue\r
+#endif\r
+\r
+\r
+#ifndef configQUEUE_REGISTRY_SIZE\r
+ #define configQUEUE_REGISTRY_SIZE 0U\r
+#endif\r
+\r
+#if ( configQUEUE_REGISTRY_SIZE < 1 )\r
+ #define vQueueAddToRegistry( xQueue, pcName )\r
+ #define vQueueUnregisterQueue( xQueue )\r
+#endif\r
+\r
+#ifndef portPOINTER_SIZE_TYPE\r
+ #define portPOINTER_SIZE_TYPE unsigned long\r
+#endif\r
+\r
+/* Remove any unused trace macros. */\r
+#ifndef traceSTART\r
+ /* Used to perform any necessary initialisation - for example, open a file\r
+ into which trace is to be written. */\r
+ #define traceSTART()\r
+#endif\r
+\r
+#ifndef traceEND\r
+ /* Use to close a trace, for example close a file into which trace has been\r
+ written. */\r
+ #define traceEND()\r
+#endif\r
+\r
+#ifndef traceTASK_SWITCHED_IN\r
+ /* Called after a task has been selected to run. pxCurrentTCB holds a pointer\r
+ to the task control block of the selected task. */\r
+ #define traceTASK_SWITCHED_IN()\r
+#endif\r
+\r
+#ifndef traceTASK_SWITCHED_OUT\r
+ /* Called before a task has been selected to run. pxCurrentTCB holds a pointer\r
+ to the task control block of the task being switched out. */\r
+ #define traceTASK_SWITCHED_OUT()\r
+#endif\r
+\r
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE\r
+ /* Task is about to block because it cannot read from a\r
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore\r
+ upon which the read was attempted. pxCurrentTCB points to the TCB of the\r
+ task that attempted the read. */\r
+ #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )\r
+#endif\r
+\r
+#ifndef traceBLOCKING_ON_QUEUE_SEND\r
+ /* Task is about to block because it cannot write to a\r
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore\r
+ upon which the write was attempted. pxCurrentTCB points to the TCB of the\r
+ task that attempted the write. */\r
+ #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )\r
+#endif\r
+\r
+#ifndef configCHECK_FOR_STACK_OVERFLOW\r
+ #define configCHECK_FOR_STACK_OVERFLOW 0\r
+#endif\r
+\r
+/* The following event macros are embedded in the kernel API calls. */\r
+\r
+#ifndef traceQUEUE_CREATE \r
+ #define traceQUEUE_CREATE( pxNewQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_CREATE_FAILED\r
+ #define traceQUEUE_CREATE_FAILED()\r
+#endif\r
+\r
+#ifndef traceCREATE_MUTEX\r
+ #define traceCREATE_MUTEX( pxNewQueue )\r
+#endif\r
+\r
+#ifndef traceCREATE_MUTEX_FAILED\r
+ #define traceCREATE_MUTEX_FAILED()\r
+#endif\r
+\r
+#ifndef traceGIVE_MUTEX_RECURSIVE\r
+ #define traceGIVE_MUTEX_RECURSIVE( pxMutex )\r
+#endif\r
+\r
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED\r
+ #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )\r
+#endif\r
+\r
+#ifndef traceTAKE_MUTEX_RECURSIVE\r
+ #define traceTAKE_MUTEX_RECURSIVE( pxMutex )\r
+#endif\r
+\r
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED\r
+ #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )\r
+#endif\r
+\r
+#ifndef traceCREATE_COUNTING_SEMAPHORE\r
+ #define traceCREATE_COUNTING_SEMAPHORE()\r
+#endif\r
+\r
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED\r
+ #define traceCREATE_COUNTING_SEMAPHORE_FAILED()\r
+#endif\r
+\r
+#ifndef traceQUEUE_SEND\r
+ #define traceQUEUE_SEND( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_SEND_FAILED\r
+ #define traceQUEUE_SEND_FAILED( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_RECEIVE\r
+ #define traceQUEUE_RECEIVE( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_PEEK\r
+ #define traceQUEUE_PEEK( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_RECEIVE_FAILED\r
+ #define traceQUEUE_RECEIVE_FAILED( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_SEND_FROM_ISR\r
+ #define traceQUEUE_SEND_FROM_ISR( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED\r
+ #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_RECEIVE_FROM_ISR\r
+ #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED\r
+ #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )\r
+#endif\r
+\r
+#ifndef traceQUEUE_DELETE\r
+ #define traceQUEUE_DELETE( pxQueue )\r
+#endif\r
+\r
+#ifndef traceTASK_CREATE\r
+ #define traceTASK_CREATE( pxNewTCB )\r
+#endif\r
+\r
+#ifndef traceTASK_CREATE_FAILED\r
+ #define traceTASK_CREATE_FAILED()\r
+#endif\r
+\r
+#ifndef traceTASK_DELETE\r
+ #define traceTASK_DELETE( pxTaskToDelete )\r
+#endif\r
+\r
+#ifndef traceTASK_DELAY_UNTIL\r
+ #define traceTASK_DELAY_UNTIL()\r
+#endif\r
+\r
+#ifndef traceTASK_DELAY\r
+ #define traceTASK_DELAY()\r
+#endif\r
+\r
+#ifndef traceTASK_PRIORITY_SET\r
+ #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )\r
+#endif\r
+\r
+#ifndef traceTASK_SUSPEND\r
+ #define traceTASK_SUSPEND( pxTaskToSuspend )\r
+#endif\r
+\r
+#ifndef traceTASK_RESUME\r
+ #define traceTASK_RESUME( pxTaskToResume )\r
+#endif\r
+\r
+#ifndef traceTASK_RESUME_FROM_ISR\r
+ #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )\r
+#endif\r
+\r
+#ifndef traceTASK_INCREMENT_TICK\r
+ #define traceTASK_INCREMENT_TICK( xTickCount )\r
+#endif\r
+\r
+#ifndef traceTIMER_CREATE\r
+ #define traceTIMER_CREATE( pxNewTimer )\r
+#endif\r
+\r
+#ifndef traceTIMER_CREATE_FAILED\r
+ #define traceTIMER_CREATE_FAILED()\r
+#endif\r
+\r
+#ifndef traceTIMER_COMMAND_SEND\r
+ #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )\r
+#endif\r
+\r
+#ifndef traceTIMER_EXPIRED\r
+ #define traceTIMER_EXPIRED( pxTimer )\r
+#endif\r
+\r
+#ifndef traceTIMER_COMMAND_RECEIVED\r
+ #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )\r
+#endif\r
+\r
+#ifndef configGENERATE_RUN_TIME_STATS\r
+ #define configGENERATE_RUN_TIME_STATS 0\r
+#endif\r
+\r
+#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+\r
+ #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\r
+ #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.\r
+ #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */\r
+\r
+ #ifndef portGET_RUN_TIME_COUNTER_VALUE\r
+ #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE\r
+ #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information.\r
+ #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */\r
+ #endif /* portGET_RUN_TIME_COUNTER_VALUE */\r
+\r
+#endif /* configGENERATE_RUN_TIME_STATS */\r
+\r
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+#endif\r
+\r
+#ifndef configUSE_MALLOC_FAILED_HOOK\r
+ #define configUSE_MALLOC_FAILED_HOOK 0\r
+#endif\r
+\r
+#ifndef portPRIVILEGE_BIT\r
+ #define portPRIVILEGE_BIT ( ( unsigned portBASE_TYPE ) 0x00 )\r
+#endif\r
+\r
+#ifndef portYIELD_WITHIN_API\r
+ #define portYIELD_WITHIN_API portYIELD\r
+#endif\r
+\r
+#ifndef pvPortMallocAligned\r
+ #define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMalloc( ( x ) ) ) : ( puxStackBuffer ) )\r
+#endif\r
+\r
+#ifndef vPortFreeAligned\r
+ #define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree )\r
+#endif\r
+\r
+#endif /* INC_FREERTOS_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. \r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configUSE_TRACE_FACILITY 0\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 80000000 ) /* Timer clock. */\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 16284 )\r
+#define configMAX_TASK_NAME_LEN ( 16 )\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Mutexes */\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_RECURSIVE_MUTEXES 0\r
+\r
+/* Semaphores */\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+\r
+/* Timers */\r
+#define configUSE_TIMERS 0\r
+#define configTIMER_TASK_PRIORITY ( 0 )\r
+#define configTIMER_QUEUE_LENGTH 0\r
+#define configTIMER_TASK_STACK_DEPTH ( 0 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 0\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_xTaskResumeFromISR 0\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_xTaskGetSchedulerState 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
+/** @file adc.h\r
+* @brief ADC Driver Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Definitions\r
+* - Types\r
+* - Interface Prototypes\r
+* .\r
+* which are relevant for the ADC driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#include "sys_common.h"\r
+\r
+#ifndef __ADC_H__\r
+#define __ADC_H__\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* ADC General Definitions */\r
+\r
+/** @def adcGROUP0\r
+* @brief Alias name for ADC event group\r
+*\r
+* @note This value should be used for API argument @a group\r
+*/\r
+#define adcGROUP0 0U\r
+\r
+/** @def adcGROUP1\r
+* @brief Alias name for ADC group 1\r
+*\r
+* @note This value should be used for API argument @a group\r
+*/\r
+#define adcGROUP1 1U\r
+\r
+/** @def adcGROUP2\r
+* @brief Alias name for ADC group 2\r
+*\r
+* @note This value should be used for API argument @a group\r
+*/\r
+#define adcGROUP2 2U\r
+\r
+/** @enum adcResolution\r
+* @brief Alias names for data resolution\r
+* This enumeration is used to provide alias names for the data resolution:\r
+* - 12 bit resolution\r
+* - 10 bit resolution\r
+* - 8 bit resolution\r
+*/\r
+\r
+enum adcResolution\r
+{\r
+ ADC_12_BIT = 0x00000000, /**< Alias for 12 bit data resolution */\r
+ ADC_10_BIT = 0x00000100, /**< Alias for 10 bit data resolution */\r
+ ADC_8_BIT = 0x00000200 /**< Alias for 8 bit data resolution */\r
+};\r
+\r
+/** @enum adcFiFoStatus\r
+* @brief Alias names for FiFo status\r
+* This enumeration is used to provide alias names for the current FiFo states:\r
+* - FiFo is not full\r
+* - FiFo is full\r
+* - FiFo overflow occured\r
+*/\r
+\r
+enum adcFiFoStatus\r
+{\r
+ ADC_FIFO_IS_NOT_FULL = 0, /**< Alias for FiFo is not full */\r
+ ADC_FIFO_IS_FULL = 1, /**< Alias for FiFo is full */\r
+ ADC_FIFO_OVERFLOW = 3 /**< Alias for FiFo overflow occured */\r
+};\r
+\r
+/** @enum adcConversionStatus\r
+* @brief Alias names for conversion status\r
+* This enumeration is used to provide alias names for the current conversion states:\r
+* - Conversion is not finished\r
+* - Conversion is finished\r
+*/\r
+\r
+enum adcConversionStatus\r
+{\r
+ ADC_CONVERSION_IS_NOT_FINISHED = 0, /**< Alias for current conversion is not finished */\r
+ ADC_CONVERSION_IS_FINISHED = 8 /**< Alias for current conversion is finished */\r
+};\r
+\r
+/** @enum adc1HwTriggerSource\r
+* @brief Alias names for hardware trigger source\r
+* This enumeration is used to provide alias names for the hardware trigger sources:\r
+*/\r
+\r
+enum adc1HwTriggerSource\r
+{\r
+ ADC1_EVENT = 0, /**< Alias for event pin */\r
+ ADC1_HET1_8 = 1, /**< Alias for HET1 pin 8 */\r
+ ADC1_HET1_10 = 2, /**< Alias for HET1 pin 10 */\r
+ ADC1_RTI_COMP0 = 3, /**< Alias for RTI compare 0 match */\r
+ ADC1_HET1_12 = 4, /**< Alias for HET1 pin 12 */\r
+ ADC1_HET1_14 = 5, /**< Alias for HET1 pin 14 */\r
+ ADC1_GIOB0 = 6, /**< Alias for GIO port b pin 0 */\r
+ ADC1_GIOB1 = 7, /**< Alias for GIO port b pin 1 */\r
+\r
+ ADC1_HET2_5 = 1, /**< Alias for HET2 pin 5 */\r
+ ADC1_HET1_27 = 2, /**< Alias for HET1 pin 27 */\r
+ ADC1_HET1_17 = 4, /**< Alias for HET1 pin 17 */\r
+ ADC1_HET1_19 = 5, /**< Alias for HET1 pin 19 */\r
+ ADC1_HET1_11 = 6, /**< Alias for HET1 pin 11 */\r
+ ADC1_HET2_13 = 7, /**< Alias for HET2 pin 13 */\r
+\r
+ ADC1_EPWM_B = 1, /**< Alias for B Signal EPWM */\r
+ ADC1_EPWM_A1 = 3, /**< Alias for A1 Signal EPWM */ \r
+ ADC1_HET2_1 = 5, /**< Alias for HET2 pin 1 */\r
+ ADC1_EPWM_A2 = 6, /**< Alias for A2 Signal EPWM */\r
+ ADC1_EPWM_AB = 7 /**< Alias for AB Signal EPWM */ \r
+\r
+};\r
+\r
+/** @enum adc2HwTriggerSource\r
+* @brief Alias names for hardware trigger source\r
+* This enumeration is used to provide alias names for the hardware trigger sources:\r
+*/\r
+\r
+enum adc2HwTriggerSource\r
+{\r
+ ADC2_EVENT = 0, /**< Alias for event pin */\r
+ ADC2_HET1_8 = 1, /**< Alias for HET1 pin 8 */\r
+ ADC2_HET1_10 = 2, /**< Alias for HET1 pin 10 */\r
+ ADC2_RTI_COMP0 = 3, /**< Alias for RTI compare 0 match */\r
+ ADC2_HET1_12 = 4, /**< Alias for HET1 pin 12 */\r
+ ADC2_HET1_14 = 5, /**< Alias for HET1 pin 14 */\r
+ ADC2_GIOB0 = 6, /**< Alias for GIO port b pin 0 */\r
+ ADC2_GIOB1 = 7, /**< Alias for GIO port b pin 1 */\r
+ ADC2_HET2_5 = 1, /**< Alias for HET2 pin 5 */\r
+ ADC2_HET1_27 = 2, /**< Alias for HET1 pin 27 */\r
+ ADC2_HET1_17 = 4, /**< Alias for HET1 pin 17 */\r
+ ADC2_HET1_19 = 5, /**< Alias for HET1 pin 19 */\r
+ ADC2_HET1_11 = 6, /**< Alias for HET1 pin 11 */\r
+ ADC2_HET2_13 = 7, /**< Alias for HET2 pin 13 */\r
+ \r
+ ADC2_EPWM_B = 1, /**< Alias for B Signal EPWM */\r
+ ADC2_EPWM_A1 = 3, /**< Alias for A1 Signal EPWM */ \r
+ ADC2_HET2_1 = 5, /**< Alias for HET2 pin 1 */\r
+ ADC2_EPWM_A2 = 6, /**< Alias for A2 Signal EPWM */\r
+ ADC2_EPWM_AB = 7 /**< Alias for AB Signal EPWM */ \r
+\r
+};\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+/** @struct adcData\r
+* @brief ADC Conversion data structure\r
+*\r
+* This type is used to pass adc conversion data.\r
+*/\r
+/** @typedef adcData_t\r
+* @brief ADC Data Type Definition\r
+*/\r
+typedef struct adcData\r
+{\r
+ uint32_t id; /**< Channel/Pin Id */\r
+ uint16_t value; /**< Conversion data value */\r
+} adcData_t;\r
+\r
+/** @struct adcBase\r
+* @brief ADC Register Frame Definition\r
+*\r
+* This type is used to access the ADC Registers.\r
+*/\r
+/** @typedef adcBASE_t\r
+* @brief ADC Register Frame Type Definition\r
+*\r
+* This type is used to access the ADC Registers.\r
+*/\r
+typedef volatile struct adcBase\r
+{\r
+ uint32_t RSTCR; /**< 0x0000: Reset control register */\r
+ uint32_t OPMODECR; /**< 0x0004: Operating mode control register */\r
+ uint32_t CLOCKCR; /**< 0x0008: Clock control register */\r
+ uint32_t CALCR; /**< 0x000C: Calibration control register */\r
+ uint32_t GxMODECR[3U]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */\r
+ uint32_t G0SRC; /**< 0x001C: Group 0 trigger source control register */\r
+ uint32_t G1SRC; /**< 0x0020: Group 1 trigger source control register */\r
+ uint32_t G2SRC; /**< 0x0024: Group 2 trigger source control register */\r
+ uint32_t GxINTENA[3U]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register */\r
+ uint32_t GxINTFLG[3U]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */\r
+ uint32_t GxINTCR[3U]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */\r
+ uint32_t G0DMACR; /**< 0x004C: Group 0 DMA control register */\r
+ uint32_t G1DMACR; /**< 0x0050: Group 1 DMA control register */\r
+ uint32_t G2DMACR; /**< 0x0054: Group 2 DMA control register */\r
+ uint32_t BNDCR; /**< 0x0058: Buffer boundary control register */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) \r
+ uint32_t BNDEND : 16U; /**< 0x005C: Buffer boundary end register */\r
+ uint32_t BUFINIT : 16U; /**< 0x005C: Buffer initialization register */\r
+#else\r
+ uint32_t BUFINIT : 16U; /**< 0x005C: Buffer initialization register */\r
+ uint32_t BNDEND : 16U; /**< 0x005C: Buffer boundary end register */\r
+#endif\r
+ uint32_t G0SAMP; /**< 0x0060: Group 0 sample window register */\r
+ uint32_t G1SAMP; /**< 0x0064: Group 1 sample window register */\r
+ uint32_t G2SAMP; /**< 0x0068: Group 2 sample window register */\r
+ uint32_t G0SR; /**< 0x006C: Group 0 status register */\r
+ uint32_t G1SR; /**< 0x0070: Group 1 status register */\r
+ uint32_t G2SR; /**< 0x0074: Group 2 status register */\r
+ uint32_t GxSEL[3U]; /**< 0x0078-0x007C: Group 0-2 channel select register */\r
+ uint32_t CALR; /**< 0x0084: Calibration register */\r
+ uint32_t SMSTATE; /**< 0x0088: State machine state register */\r
+ uint32_t LASTCONV; /**< 0x008C: Last conversion register */\r
+ struct\r
+ {\r
+ uint32_t BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */\r
+ uint32_t BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */\r
+ uint32_t BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */\r
+ uint32_t BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */\r
+ uint32_t BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */\r
+ uint32_t BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */\r
+ uint32_t BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */\r
+ uint32_t BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */\r
+ } GxBUF[3U];\r
+ uint32_t G0EMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */\r
+ uint32_t G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */\r
+ uint32_t G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */\r
+ uint32_t EVTDIR; /**< 0x00FC: Event pin direction register */\r
+ uint32_t EVTOUT; /**< 0x0100: Event pin digital output register */\r
+ uint32_t EVTIN; /**< 0x0104: Event pin digital input register */\r
+ uint32_t EVTSET; /**< 0x0108: Event pin set register */\r
+ uint32_t EVTCLR; /**< 0x010C: Event pin clear register */\r
+ uint32_t EVTPDR; /**< 0x0110: Event pin open drain register */\r
+ uint32_t EVTDIS; /**< 0x0114: Event pin pull disable register */\r
+ uint32_t EVTPSEL; /**< 0x0118: Event pin pull select register */\r
+ uint32_t G0SAMPDISEN; /**< 0x011C: Group 0 sample discharge register */\r
+ uint32_t G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */\r
+ uint32_t G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */\r
+ uint32_t MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */\r
+ uint32_t MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */\r
+ uint32_t MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */\r
+ uint32_t MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */\r
+ uint32_t MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */\r
+ uint32_t MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */\r
+ uint32_t MAGINTCR4; /**< 0x0140: Magnitude interrupt control register 4 */\r
+ uint32_t MAGINT4MASK; /**< 0x0144: Magnitude interrupt mask register 4 */\r
+ uint32_t MAGINTCR5; /**< 0x0148: Magnitude interrupt control register 5 */\r
+ uint32_t MAGINT5MASK; /**< 0x014C: Magnitude interrupt mask register 5 */\r
+ uint32_t MAGINTCR6; /**< 0x0150: Magnitude interrupt control register 6 */\r
+ uint32_t MAGINT6MASK; /**< 0x0154: Magnitude interrupt mask register 6 */\r
+ uint32_t MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */\r
+ uint32_t MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */\r
+ uint32_t MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */\r
+ uint32_t MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */\r
+ uint32_t GxFIFORESETCR[3U]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register */\r
+ uint32_t G0RAMADDR; /**< 0x0174: Group 0 RAM pointer register */\r
+ uint32_t G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */\r
+ uint32_t G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */\r
+ uint32_t PARCR; /**< 0x0180: Parity control register */\r
+ uint32_t PARADDR; /**< 0x0184: Parity error address register */\r
+ uint32_t PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */\r
+} adcBASE_t;\r
+\r
+\r
+/** @def adcREG1\r
+* @brief ADC1 Register Frame Pointer\r
+*\r
+* This pointer is used by the ADC driver to access the ADC1 registers.\r
+*/\r
+#define adcREG1 ((adcBASE_t *)0xFFF7C000U)\r
+\r
+/** @def adcREG2\r
+* @brief ADC2 Register Frame Pointer\r
+*\r
+* This pointer is used by the ADC driver to access the ADC2 registers.\r
+*/\r
+#define adcREG2 ((adcBASE_t *)0xFFF7C200U)\r
+\r
+/** @def adcRAM1\r
+* @brief ADC1 RAM Pointer\r
+*\r
+* This pointer is used by the ADC driver to access the ADC1 RAM.\r
+*/\r
+#define adcRAM1 (*(unsigned int *)0xFF3E0000U)\r
+\r
+/** @def adcRAM2\r
+* @brief ADC2 RAM Pointer\r
+*\r
+* This pointer is used by the ADC driver to access the ADC2 RAM.\r
+*/\r
+#define adcRAM2 (*(unsigned int *)0xFF3A0000U)\r
+\r
+/** @def adcPARRAM1\r
+* @brief ADC1 Parity RAM Pointer\r
+*\r
+* This pointer is used by the ADC driver to access the ADC1 Parity RAM.\r
+*/\r
+#define adcPARRAM1 (*(unsigned int *)(0xFF3E0000U + 0x1000))\r
+\r
+/** @def adcPARRAM2\r
+* @brief ADC2 Parity RAM Pointer\r
+*\r
+* This pointer is used by the ADC driver to access the ADC2 Parity RAM.\r
+*/\r
+#define adcPARRAM2 (*(unsigned int *)(0xFF3A0000U + 0x1000))\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+\r
+/* ADC Interface Functions */\r
+\r
+void adcInit(void);\r
+void adcStartConversion(adcBASE_t *adc, uint32_t group);\r
+void adcStopConversion(adcBASE_t *adc, uint32_t group);\r
+void adcResetFiFo(adcBASE_t *adc, uint32_t group);\r
+uint32_t adcGetData(adcBASE_t *adc, uint32_t group, adcData_t *data);\r
+uint32_t adcIsFifoFull(adcBASE_t *adc, uint32_t group);\r
+uint32_t adcIsConversionComplete(adcBASE_t *adc, uint32_t group);\r
+void adcEnableNotification(adcBASE_t *adc, uint32_t group);\r
+void adcDisableNotification(adcBASE_t *adc, uint32_t group);\r
+void adcCalibration(adcBASE_t *adc);\r
+uint32_t adcMidPointCalibration(adcBASE_t *adc);\r
+\r
+/** @fn void adcNotification(adcBASE_t *adc, uint32_t group)\r
+* @brief Group notification\r
+* @param[in] adc Pointer to ADC node:\r
+* - adcREG1: ADC1 module pointer\r
+* - adcREG2: ADC2 module pointer\r
+* @param[in] group number of ADC node:\r
+* - adcGROUP0: ADC event group\r
+* - adcGROUP1: ADC group 1\r
+* - adcGROUP2: ADC group 2\r
+*\r
+* @note This function has to be provide by the user.\r
+*/\r
+void adcNotification(adcBASE_t *adc, uint32_t group);\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file can.h\r
+* @brief CAN Driver Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Definitions\r
+* - Types\r
+* - Interface Prototypes\r
+* .\r
+* which are relevant for the CAN driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#include "sys_common.h"\r
+\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* CAN General Definitions */\r
+\r
+/** @def canLEVEL_ACTIVE\r
+* @brief Alias name for CAN error operation level active (Error couter 0-95) \r
+*/\r
+#define canLEVEL_ACTIVE 0x00U\r
+\r
+/** @def canLEVEL_WARNING\r
+* @brief Alias name for CAN error operation level warning (Error couter 96-127) \r
+*/\r
+#define canLEVEL_WARNING 0x40U\r
+\r
+/** @def canLEVEL_PASSIVE\r
+* @brief Alias name for CAN error operation level passive (Error couter 128-255) \r
+*/\r
+#define canLEVEL_PASSIVE 0x20U\r
+\r
+/** @def canLEVEL_BUS_OFF\r
+* @brief Alias name for CAN error operation level bus off (Error couter 256) \r
+*/\r
+#define canLEVEL_BUS_OFF 0x80U\r
+\r
+/** @def canERROR_NO\r
+* @brief Alias name for no CAN error occured \r
+*/\r
+#define canERROR_OK 0U\r
+\r
+/** @def canERROR_STUFF\r
+* @brief Alias name for CAN stuff error an RX message \r
+*/\r
+#define canERROR_STUFF 1U\r
+\r
+/** @def canERROR_FORMAT\r
+* @brief Alias name for CAN form/format error an RX message \r
+*/\r
+#define canERROR_FORMAT 2U\r
+\r
+/** @def canERROR_ACKNOWLEDGE\r
+* @brief Alias name for CAN TX message wasn't acknowledged \r
+*/\r
+#define canERROR_ACKNOWLEDGE 3U\r
+\r
+/** @def canERROR_BIT1\r
+* @brief Alias name for CAN TX message sendig recessive level but monitoring dominant \r
+*/\r
+#define canERROR_BIT1 4U\r
+\r
+/** @def canERROR_BIT0\r
+* @brief Alias name for CAN TX message sendig dominant level but monitoring recessive \r
+*/\r
+#define canERROR_BIT0 5U\r
+\r
+/** @def canERROR_CRC\r
+* @brief Alias name for CAN RX message received wrong CRC \r
+*/\r
+#define canERROR_CRC 6U\r
+\r
+/** @def canERROR_NO\r
+* @brief Alias name for CAN no message has send or received sinced last call of CANGetLastError \r
+*/\r
+#define canERROR_NO 7U\r
+\r
+/** @def canMESSAGE_BOX1\r
+* @brief Alias name for CAN message box 1\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX1 1U\r
+\r
+/** @def canMESSAGE_BOX2\r
+* @brief Alias name for CAN message box 2\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX2 2U\r
+\r
+/** @def canMESSAGE_BOX3\r
+* @brief Alias name for CAN message box 3\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX3 3U\r
+\r
+/** @def canMESSAGE_BOX4\r
+* @brief Alias name for CAN message box 4\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX4 4U\r
+\r
+/** @def canMESSAGE_BOX5\r
+* @brief Alias name for CAN message box 5\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX5 5U\r
+\r
+/** @def canMESSAGE_BOX6\r
+* @brief Alias name for CAN message box 6\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX6 6U\r
+\r
+/** @def canMESSAGE_BOX7\r
+* @brief Alias name for CAN message box 7\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX7 7U\r
+\r
+/** @def canMESSAGE_BOX8\r
+* @brief Alias name for CAN message box 8\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX8 8U\r
+\r
+/** @def canMESSAGE_BOX9\r
+* @brief Alias name for CAN message box 9\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX9 9U\r
+\r
+/** @def canMESSAGE_BOX10\r
+* @brief Alias name for CAN message box 10\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX10 10U\r
+\r
+/** @def canMESSAGE_BOX11\r
+* @brief Alias name for CAN message box 11\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX11 11U\r
+\r
+/** @def canMESSAGE_BOX12\r
+* @brief Alias name for CAN message box 12\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX12 12U\r
+\r
+/** @def canMESSAGE_BOX13\r
+* @brief Alias name for CAN message box 13\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX13 13U\r
+\r
+/** @def canMESSAGE_BOX14\r
+* @brief Alias name for CAN message box 14\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX14 14U\r
+\r
+/** @def canMESSAGE_BOX15\r
+* @brief Alias name for CAN message box 15\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX15 15U\r
+\r
+/** @def canMESSAGE_BOX16\r
+* @brief Alias name for CAN message box 16\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX16 16U\r
+\r
+/** @def canMESSAGE_BOX17\r
+* @brief Alias name for CAN message box 17\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX17 17U\r
+\r
+/** @def canMESSAGE_BOX18\r
+* @brief Alias name for CAN message box 18\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX18 18U\r
+\r
+/** @def canMESSAGE_BOX19\r
+* @brief Alias name for CAN message box 19\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX19 19U\r
+\r
+/** @def canMESSAGE_BOX20\r
+* @brief Alias name for CAN message box 20\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX20 20U\r
+\r
+/** @def canMESSAGE_BOX21\r
+* @brief Alias name for CAN message box 21\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX21 21U\r
+\r
+/** @def canMESSAGE_BOX22\r
+* @brief Alias name for CAN message box 22\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX22 22U\r
+\r
+/** @def canMESSAGE_BOX23\r
+* @brief Alias name for CAN message box 23\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX23 23U\r
+\r
+/** @def canMESSAGE_BOX24\r
+* @brief Alias name for CAN message box 24\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX24 24U\r
+\r
+/** @def canMESSAGE_BOX25\r
+* @brief Alias name for CAN message box 25\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX25 25U\r
+\r
+/** @def canMESSAGE_BOX26\r
+* @brief Alias name for CAN message box 26\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX26 26U\r
+\r
+/** @def canMESSAGE_BOX27\r
+* @brief Alias name for CAN message box 27\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX27 27U\r
+\r
+/** @def canMESSAGE_BOX28\r
+* @brief Alias name for CAN message box 28\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX28 28U\r
+\r
+/** @def canMESSAGE_BOX29\r
+* @brief Alias name for CAN message box 29\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX29 29U\r
+\r
+/** @def canMESSAGE_BOX30\r
+* @brief Alias name for CAN message box 30\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX30 30U\r
+\r
+/** @def canMESSAGE_BOX31\r
+* @brief Alias name for CAN message box 31\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX31 31U\r
+\r
+/** @def canMESSAGE_BOX32\r
+* @brief Alias name for CAN message box 32\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX32 32U\r
+\r
+/** @def canMESSAGE_BOX33\r
+* @brief Alias name for CAN message box 33\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX33 33U\r
+\r
+/** @def canMESSAGE_BOX34\r
+* @brief Alias name for CAN message box 34\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX34 34U\r
+\r
+/** @def canMESSAGE_BOX35\r
+* @brief Alias name for CAN message box 35\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX35 35U\r
+\r
+/** @def canMESSAGE_BOX36\r
+* @brief Alias name for CAN message box 36\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX36 36U\r
+\r
+/** @def canMESSAGE_BOX37\r
+* @brief Alias name for CAN message box 37\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX37 37U\r
+\r
+/** @def canMESSAGE_BOX38\r
+* @brief Alias name for CAN message box 38\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX38 38U\r
+\r
+/** @def canMESSAGE_BOX39\r
+* @brief Alias name for CAN message box 39\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX39 39U\r
+\r
+/** @def canMESSAGE_BOX40\r
+* @brief Alias name for CAN message box 40\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX40 40U\r
+\r
+/** @def canMESSAGE_BOX41\r
+* @brief Alias name for CAN message box 41\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX41 41U\r
+\r
+/** @def canMESSAGE_BOX42\r
+* @brief Alias name for CAN message box 42\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX42 42U\r
+\r
+/** @def canMESSAGE_BOX43\r
+* @brief Alias name for CAN message box 43\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX43 43U\r
+\r
+/** @def canMESSAGE_BOX44\r
+* @brief Alias name for CAN message box 44\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX44 44U\r
+\r
+/** @def canMESSAGE_BOX45\r
+* @brief Alias name for CAN message box 45\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX45 45U\r
+\r
+/** @def canMESSAGE_BOX46\r
+* @brief Alias name for CAN message box 46\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX46 46U\r
+\r
+/** @def canMESSAGE_BOX47\r
+* @brief Alias name for CAN message box 47\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX47 47U\r
+\r
+/** @def canMESSAGE_BOX48\r
+* @brief Alias name for CAN message box 48\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX48 48U\r
+\r
+/** @def canMESSAGE_BOX49\r
+* @brief Alias name for CAN message box 49\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX49 49U\r
+\r
+/** @def canMESSAGE_BOX50\r
+* @brief Alias name for CAN message box 50\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX50 50U\r
+\r
+/** @def canMESSAGE_BOX51\r
+* @brief Alias name for CAN message box 51\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX51 51U\r
+\r
+/** @def canMESSAGE_BOX52\r
+* @brief Alias name for CAN message box 52\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX52 52U\r
+\r
+/** @def canMESSAGE_BOX53\r
+* @brief Alias name for CAN message box 53\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX53 53U\r
+\r
+/** @def canMESSAGE_BOX54\r
+* @brief Alias name for CAN message box 54\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX54 54U\r
+\r
+/** @def canMESSAGE_BOX55\r
+* @brief Alias name for CAN message box 55\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX55 55U\r
+\r
+/** @def canMESSAGE_BOX56\r
+* @brief Alias name for CAN message box 56\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX56 56U\r
+\r
+/** @def canMESSAGE_BOX57\r
+* @brief Alias name for CAN message box 57\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX57 57U\r
+\r
+/** @def canMESSAGE_BOX58\r
+* @brief Alias name for CAN message box 58\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX58 58U\r
+\r
+/** @def canMESSAGE_BOX59\r
+* @brief Alias name for CAN message box 59\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX59 59U\r
+\r
+/** @def canMESSAGE_BOX60\r
+* @brief Alias name for CAN message box 60\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX60 60U\r
+\r
+/** @def canMESSAGE_BOX61\r
+* @brief Alias name for CAN message box 61\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX61 61U\r
+\r
+/** @def canMESSAGE_BOX62\r
+* @brief Alias name for CAN message box 62\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX62 62U\r
+\r
+/** @def canMESSAGE_BOX63\r
+* @brief Alias name for CAN message box 63\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX63 63U\r
+\r
+/** @def canMESSAGE_BOX64\r
+* @brief Alias name for CAN message box 64\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX64 64U\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+/** @struct CANBase\r
+* @brief CAN Register Frame Definition\r
+*\r
+* This type is used to access the CAN Registers.\r
+*/\r
+/** @typedef canBASE_t\r
+* @brief CAN Register Frame Type Definition\r
+*\r
+* This type is used to access the CAN Registers.\r
+*/\r
+typedef volatile struct CANBase\r
+{\r
+ uint32_t CTL; /**< 0x0000: Control Register */\r
+ uint32_t ES; /**< 0x0004: Error and Status Register */\r
+ uint32_t EERC; /**< 0x0008: Error Counter Register */\r
+ uint32_t BTR; /**< 0x000C: Bit Timing Register */\r
+ uint32_t INT; /**< 0x0010: Interrupt Register */\r
+ uint32_t TEST; /**< 0x0014: Test Register */\r
+ uint32_t : 32U; /**< 0x0018: Reserved */\r
+ uint32_t PERR; /**< 0x001C: Parity/SECDED Error Code Register */\r
+ uint32_t REL; /**< 0x0020: Core Release Register */\r
+ uint32_t ECCDIAG; /**< 0x0024: ECC Diagnostic Register */\r
+ uint32_t ECCDIADSTAT; /**< 0x0028: ECC Diagnostic Status Register */\r
+ uint32_t : 32U; /**< 0x002C: Reserved */\r
+ uint32_t : 32U; /**< 0x0030: Reserved */\r
+ uint32_t : 32U; /**< 0x0034: Reserved */\r
+ uint32_t : 32U; /**< 0x0038: Reserved */\r
+ uint32_t : 32U; /**< 0x003C: Reserved */\r
+ uint32_t : 32U; /**< 0x0040: Reserved */\r
+ uint32_t : 32U; /**< 0x0044: Reserved */\r
+ uint32_t : 32U; /**< 0x0048: Reserved */\r
+ uint32_t : 32U; /**< 0x004C: Reserved */\r
+ uint32_t : 32U; /**< 0x0050: Reserved */\r
+ uint32_t : 32U; /**< 0x0054: Reserved */\r
+ uint32_t : 32U; /**< 0x0058: Reserved */\r
+ uint32_t : 32U; /**< 0x005C: Reserved */\r
+ uint32_t : 32U; /**< 0x0060: Reserved */\r
+ uint32_t : 32U; /**< 0x0064: Reserved */\r
+ uint32_t : 32U; /**< 0x0068: Reserved */\r
+ uint32_t : 32U; /**< 0x006C: Reserved */\r
+ uint32_t : 32U; /**< 0x0070: Reserved */\r
+ uint32_t : 32U; /**< 0x0074: Reserved */\r
+ uint32_t : 32U; /**< 0x0078: Reserved */\r
+ uint32_t : 32U; /**< 0x007C: Reserved */\r
+ uint32_t ABOTR; /**< 0x0080: Auto Bus On Time Register */\r
+ uint32_t TXRQX; /**< 0x0084: Transmission Request X Register */\r
+ uint32_t TXRQx[4U]; /**< 0x0088-0x0094: Transmission Request Registers */\r
+ uint32_t NWDATX; /**< 0x0098: New Data X Register */\r
+ uint32_t NWDATx[4U]; /**< 0x009C-0x00A8: New Data Registers */\r
+ uint32_t INTPNDX; /**< 0x00AC: Interrupt Pending X Register */\r
+ uint32_t INTPNDx[4U]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */\r
+ uint32_t MSGVALX; /**< 0x00C0: Message Valid X Register */\r
+ uint32_t MSGVALx[4U]; /**< 0x00C4-0x00D0: Message Valid Registers */\r
+ uint32_t : 32U; /**< 0x00D4: Reserved */\r
+ uint32_t INTMUXx[4U]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */\r
+ uint32_t : 32U; /**< 0x00E8: Reserved */\r
+ uint32_t : 32U; /**< 0x00EC: Reserved */\r
+ uint32_t : 32U; /**< 0x00F0: Reserved */\r
+ uint32_t : 32U; /**< 0x00F4: Reserved */\r
+ uint32_t : 32U; /**< 0x00F8: Reserved */\r
+ uint32_t : 32U; /**< 0x00FC: Reserved */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint8_t IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */\r
+ uint8_t IF1STAT; /**< 0x0100: IF1 Command Register, Status */\r
+ uint8_t IF1CMD; /**< 0x0100: IF1 Command Register, Command */\r
+ uint32_t : 8U; /**< 0x0100: IF1 Command Register, Reserved */\r
+#else\r
+ uint32_t : 8U; /**< 0x0100: IF1 Command Register, Reserved */\r
+ uint8_t IF1CMD; /**< 0x0100: IF1 Command Register, Command */\r
+ uint8_t IF1STAT; /**< 0x0100: IF1 Command Register, Status */\r
+ uint8_t IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */\r
+#endif\r
+ uint32_t IF1MSK; /**< 0x0104: IF1 Mask Register */\r
+ uint32_t IF1ARB; /**< 0x0108: IF1 Arbitration Register */\r
+ uint32_t IF1MCTL; /**< 0x010C: IF1 Message Control Register */\r
+ uint8_t IF1DATx[8U]; /**< 0x0110-0x0114: IF1 Data A and B Registers */\r
+ uint32_t : 32U; /**< 0x0118: Reserved */\r
+ uint32_t : 32U; /**< 0x011C: Reserved */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint8_t IF2NO; /**< 0x0120: IF2 Command Register, Msg No */\r
+ uint8_t IF2STAT; /**< 0x0120: IF2 Command Register, Status */\r
+ uint8_t IF2CMD; /**< 0x0120: IF2 Command Register, Command */\r
+ uint32_t : 8U; /**< 0x0120: IF2 Command Register, Reserved */\r
+#else\r
+ uint32_t : 8U; /**< 0x0120: IF2 Command Register, Reserved */\r
+ uint8_t IF2CMD; /**< 0x0120: IF2 Command Register, Command */\r
+ uint8_t IF2STAT; /**< 0x0120: IF2 Command Register, Status */\r
+ uint8_t IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */\r
+#endif\r
+ uint32_t IF2MSK; /**< 0x0124: IF2 Mask Register */\r
+ uint32_t IF2ARB; /**< 0x0128: IF2 Arbitration Register */\r
+ uint32_t IF2MCTL; /**< 0x012C: IF2 Message Control Register */\r
+ uint8_t IF2DATx[8U]; /**< 0x0130-0x0134: IF2 Data A and B Registers */\r
+ uint32_t : 32U; /**< 0x0138: Reserved */\r
+ uint32_t : 32U; /**< 0x013C: Reserved */\r
+ uint32_t IF3OBS; /**< 0x0140: IF3 Observation Register */\r
+ uint32_t IF3MSK; /**< 0x0144: IF3 Mask Register */\r
+ uint32_t IF3ARB; /**< 0x0148: IF3 Arbitration Register */\r
+ uint32_t IF3MCTL; /**< 0x014C: IF3 Message Control Register */\r
+ uint8_t IF3DATx[8U]; /**< 0x0150-0x0154: IF3 Data A and B Registers */\r
+ uint32_t : 32U; /**< 0x0158: Reserved */\r
+ uint32_t : 32U; /**< 0x015C: Reserved */\r
+ uint32_t IF3UEy[4U]; /**< 0x0160-0x016C: IF3 Update Enable Registers */\r
+ uint32_t : 32U; /**< 0x0170: Reserved */\r
+ uint32_t : 32U; /**< 0x0174: Reserved */\r
+ uint32_t : 32U; /**< 0x0178: Reserved */\r
+ uint32_t : 32U; /**< 0x017C: Reserved */\r
+ uint32_t : 32U; /**< 0x0180: Reserved */\r
+ uint32_t : 32U; /**< 0x0184: Reserved */\r
+ uint32_t : 32U; /**< 0x0188: Reserved */\r
+ uint32_t : 32U; /**< 0x018C: Reserved */\r
+ uint32_t : 32U; /**< 0x0190: Reserved */\r
+ uint32_t : 32U; /**< 0x0194: Reserved */\r
+ uint32_t : 32U; /**< 0x0198: Reserved */\r
+ uint32_t : 32U; /**< 0x019C: Reserved */\r
+ uint32_t : 32U; /**< 0x01A0: Reserved */\r
+ uint32_t : 32U; /**< 0x01A4: Reserved */\r
+ uint32_t : 32U; /**< 0x01A8: Reserved */\r
+ uint32_t : 32U; /**< 0x01AC: Reserved */\r
+ uint32_t : 32U; /**< 0x01B0: Reserved */\r
+ uint32_t : 32U; /**< 0x01B4: Reserved */\r
+ uint32_t : 32U; /**< 0x01B8: Reserved */\r
+ uint32_t : 32U; /**< 0x01BC: Reserved */\r
+ uint32_t : 32U; /**< 0x01C0: Reserved */\r
+ uint32_t : 32U; /**< 0x01C4: Reserved */\r
+ uint32_t : 32U; /**< 0x01C8: Reserved */\r
+ uint32_t : 32U; /**< 0x01CC: Reserved */\r
+ uint32_t : 32U; /**< 0x01D0: Reserved */\r
+ uint32_t : 32U; /**< 0x01D4: Reserved */\r
+ uint32_t : 32U; /**< 0x01D8: Reserved */\r
+ uint32_t : 32U; /**< 0x01DC: Reserved */\r
+ uint32_t TIOC; /**< 0x01E0: TX IO Control Register */\r
+ uint32_t RIOC; /**< 0x01E4: RX IO Control Register */\r
+} canBASE_t;\r
+\r
+\r
+/** @def canREG1\r
+* @brief CAN1 Register Frame Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN1 registers.\r
+*/\r
+#define canREG1 ((canBASE_t *)0xFFF7DC00U)\r
+\r
+/** @def canREG2\r
+* @brief CAN2 Register Frame Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN2 registers.\r
+*/\r
+#define canREG2 ((canBASE_t *)0xFFF7DE00U)\r
+\r
+/** @def canREG3\r
+* @brief CAN3 Register Frame Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN3 registers.\r
+*/\r
+#define canREG3 ((canBASE_t *)0xFFF7E000U)\r
+\r
+/** @def canRAM1\r
+* @brief CAN1 Mailbox RAM Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN1 RAM.\r
+*/\r
+#define canRAM1 (*(unsigned int *)0xFF1E0000U)\r
+\r
+/** @def canRAM2\r
+* @brief CAN2 Mailbox RAM Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN2 RAM.\r
+*/\r
+#define canRAM2 (*(unsigned int *)0xFF1C0000U)\r
+\r
+/** @def canRAM3\r
+* @brief CAN3 Mailbox RAM Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN3 RAM.\r
+*/\r
+#define canRAM3 (*(unsigned int *)0xFF1A0000U)\r
+\r
+/** @def canPARRAM1\r
+* @brief CAN1 Mailbox Parity RAM Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN1 Parity RAM\r
+* for testing RAM parity error detect logic.\r
+*/\r
+#define canPARRAM1 (*(unsigned int *)(0xFF1E0000U + 0x10))\r
+\r
+/** @def canPARRAM2\r
+* @brief CAN2 Mailbox Pairyt RAM Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN2 Parity RAM\r
+* for testing RAM parity error detect logic.\r
+*/\r
+#define canPARRAM2 (*(unsigned int *)(0xFF1C0000U + 0x10))\r
+\r
+/** @def canPARRAM3\r
+* @brief CAN3 Mailbox Parity RAM Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the CAN3 Parity RAM\r
+* for testing RAM parity error detect logic.\r
+*/\r
+#define canPARRAM3 (*(unsigned int *)(0xFF1A0000U + 0x10))\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+\r
+/* CAN Interface Functions */\r
+\r
+void canInit(void);\r
+uint32_t canTransmit(canBASE_t *node, uint32_t messageBox, const uint8_t *data);\r
+uint32_t canGetData(canBASE_t *node, uint32_t messageBox, uint8_t * const data);\r
+uint32_t canIsTxMessagePending(canBASE_t *node, uint32_t messageBox);\r
+uint32_t canIsRxMessageArrived(canBASE_t *node, uint32_t messageBox);\r
+uint32_t canIsMessageBoxValid(canBASE_t *node, uint32_t messageBox);\r
+uint32_t canGetLastError(canBASE_t *node);\r
+uint32_t canGetErrorLevel(canBASE_t *node);\r
+void canEnableErrorNotification(canBASE_t *node);\r
+void canDisableErrorNotification(canBASE_t *node);\r
+void canIoSetDirection(canBASE_t *node,uint32_t TxDir,uint32_t RxDir);\r
+void canIoSetPort(canBASE_t *node, uint32_t TxValue, uint32_t RxValue);\r
+uint32_t canIoTxGetBit(canBASE_t *node);\r
+uint32_t canIoRxGetBit(canBASE_t *node);\r
+\r
+/** @fn void canErrorNotification(canBASE_t *node, uint32_t notification)\r
+* @brief Error notification\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: CAN1 node pointer\r
+* - canREG2: CAN2 node pointer\r
+* - canREG3: CAN3 node pointer\r
+* @param[in] notification Error notification code:\r
+* - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127 \r
+* - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 \r
+*\r
+* @note This function has to be provide by the user.\r
+*/\r
+void canErrorNotification(canBASE_t *node, uint32_t notification);\r
+\r
+/** @fn void canMessageNotification(canBASE_t *node, uint32_t messageBox)\r
+* @brief Message notification\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: CAN1 node pointer\r
+* - canREG2: CAN2 node pointer\r
+* - canREG3: CAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+*\r
+* @note This function has to be provide by the user.\r
+*/\r
+void canMessageNotification(canBASE_t *node, uint32_t messageBox);\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+\r
+#endif\r
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ cmd_proc.h - text line command processor
+ designed for instruments control and setup
+ over RS-232 line
+
+ Copyright (C) 2001-2009 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002-2009 by PiKRON Ltd. http://www.pikron.com
+ (C) 2007 by Michal Sojka <sojkam1@fel.cvut.cz>
+
+ This file can be used and copied according to next
+ license alternatives
+ - MPL - Mozilla Public License
+ - GPL - GNU Public License
+ - other license provided by project originators
+ *******************************************************************/
+
+#ifndef _CMD_PROC_H_
+#define _CMD_PROC_H_
+
+//#define CMD_PROC_WITH_FILE
+
+#ifdef CMD_PROC_WITH_FILE
+#include <stdio.h>
+#endif
+
+#define FL_ELB_ECHO 0x10 /* Read characters are echoed back */
+#define FL_ELB_INSEND 0x20 /* The line is currently being sent */
+#define FL_ELB_NOCRLF 0x40 /* CR and/or LF will not start the new line */
+#define CMD_DES_CONTINUE_AT_ID ((cmd_des_t*)1)
+#define CMD_DES_INCLUDE_SUBLIST_ID ((cmd_des_t*)2)
+#define CMD_DES_CONTINUE_AT(list) CMD_DES_CONTINUE_AT_ID,((cmd_des_t*)list)
+#define CMD_DES_INCLUDE_SUBLIST(list) CMD_DES_INCLUDE_SUBLIST_ID,((cmd_des_t*)list)
+
+/* generic cmd_io structure */
+
+/* buffer for in/out line collection */
+typedef struct{
+ int flg; /* FL_ELB_xxx */
+ int inbuf; /* Index to store new characters */
+ int alloc; /* Size of the buffer pointed by buf */
+ int maxlen;
+ int lastch; /* Last characted added to the buffer.
+ * If FL_ELB_INSEND is set, lastch is
+ * index of last sent char. */
+ char *buf;
+} ed_line_buf_t;
+
+/* Structure for character input output. It is used either for direct
+ * access to IO device or for buffered IO. In the later case,
+ * priv.edline is used to store buffer information. */
+typedef struct cmd_io{
+ int (*putc)(struct cmd_io *cmd_io,int ch);
+ int (*getc)(struct cmd_io *cmd_io);
+ int (*write)(struct cmd_io *cmd_io,const void *buf,int count);
+ int (*read)(struct cmd_io *cmd_io,void *buf,int count);
+ union {
+ struct {
+ ed_line_buf_t *in;
+ ed_line_buf_t *out;
+ struct cmd_io *io_stack;
+ } ed_line;
+ struct {
+ long pos;
+ void *ptr;
+ } device;
+#ifdef CMD_PROC_WITH_FILE
+ struct {
+ FILE *in;
+ FILE *out;
+ } file;
+#endif /*CMD_PROC_WITH_FILE*/
+ struct {
+ int uartch;
+ } uart;
+ } priv;
+} cmd_io_t;
+
+static inline int cmd_io_putc(struct cmd_io *cmd_io,int ch)
+{ if(!cmd_io->putc) return -1;
+ return (*cmd_io->putc)(cmd_io,ch);
+}
+
+static inline int cmd_io_getc(struct cmd_io *cmd_io)
+{ if(!cmd_io->getc) return -1;
+ return (*cmd_io->getc)(cmd_io);
+}
+
+static inline int cmd_io_write(struct cmd_io *cmd_io,const void *buf,int count)
+{ if(!cmd_io->write) return -1;
+ return (*cmd_io->write)(cmd_io,buf,count);
+}
+
+static inline int cmd_io_read(struct cmd_io *cmd_io,void *buf,int count)
+{ if(!cmd_io->read) return -1;
+ return (*cmd_io->read)(cmd_io,buf,count);
+}
+
+int cmd_io_puts(cmd_io_t *cmd_io, const char *str);
+
+int cmd_io_line_putc(cmd_io_t *cmd_io,int ch);
+
+int cmd_io_write_bychar(cmd_io_t *cmd_io,const void *buf,int count);
+
+int cmd_io_read_bychar(cmd_io_t *cmd_io,void *buf,int count);
+
+/* command descriptions */
+
+#define CDESM_OPCHR 0x10 /* Command uses operation character */
+#define CDESM_RD 0x01 /* Value read is possible */
+#define CDESM_WR 0x02 /* Value write is possible */
+#define CDESM_RW (CDESM_RD|CDESM_WR) /* Both */
+
+typedef struct cmd_des{
+ int code;
+ int mode;
+ char *name;
+ char *help;
+ int (*fnc)(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]);
+ void *info;
+} cmd_des_t;
+
+#define CMDERR_BADCMD 2
+#define CMDERR_OPCHAR 10
+#define CMDERR_WRPERM 11
+#define CMDERR_RDPERM 12
+#define CMDERR_GARBAG 13
+#define CMDERR_BADSEP 14
+#define CMDERR_BADCFG 15
+#define CMDERR_NOMEM 16
+#define CMDERR_BADSUF 17
+#define CMDERR_BADPAR 20
+#define CMDERR_VALOOR 21
+#define CMDERR_BADREG 40
+#define CMDERR_BSYREG 41
+#define CMDERR_BADDIO 50
+#define CMDERR_NODEV 60
+#define CMDERR_TIMEOUT 61
+#define CMDERR_EIO 62
+
+int cmd_opchar_check(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]);
+
+int cmd_num_suffix(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[], unsigned *val);
+
+int proc_cmd_line(cmd_io_t *cmd_io, cmd_des_t const **des_arr, char *line);
+
+int i2str(char *s,long val,int len,int form);
+
+int cmd_do_stamp(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]);
+
+int cmd_do_help(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]);
+
+int cmd_do_rw_short(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]);
+
+int cmd_do_rw_int(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]);
+
+int cmd_do_rw_long(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]);
+
+int cmd_do_rw_bitflag(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]);
+
+int cmd_opchar_replong(cmd_io_t *cmd_io, char *param[], long val,int len,int form);
+
+int cmd_processor_run(cmd_io_t *cmd_io, cmd_des_t const **commands);
+
+#endif /* _CMD_PROC_H_ */
+
+/* Local Variables: */
+/* c-basic-offset: 2 */
+/* End */
--- /dev/null
+/*
+ * cmd_proc_freertos_tms570.h
+ *
+ * Created on: 1.8.2012
+ * Author: Michal Horn
+ *
+ * Header file for cmdProc with FreeRTOS procedures included.
+ */
+
+#ifndef CMD_PROC_FREERTOS_TMS570_H_
+#define CMD_PROC_FREERTOS_TMS570_H_
+
+#include "string.h"
+#include "cmd_proc.h"
+#include "cmdio_tisci.h"
+#include "sci.h"
+#include "os_task.h"
+#include "os_portmacro.h"
+
+
+/** Initializes CmdProc library, IO stack and creates tasks for FreeRTOS.
+ * SCI must be initialized before calling this procedure.
+ *
+ * @param[in] priority priorities for tasks.
+ * @param[in] introText string shown once after initialization before prompt is shown.
+ * @param[in] promptText string shown when software is ready to read command from RS-232
+ */
+void initCmdProc(unsigned portBASE_TYPE printPriority, uint8_t * intro, uint8_t * prompt);
+
+/** Procedure for task processCmd. Waits for semaphore, which indicates that command line is prepared for processing.
+ * After semaphore is given, calls cmdProc function that process the command line
+ */
+void processCmd(void *pvParameters );
+
+#endif /* CMD_PROC_FREERTOS_TMS570_H_ */
--- /dev/null
+#ifndef CMD_PROC_PRIV_H
+#define CMD_PROC_PRIV_H
+
+/* The maximal depth of command arrays nesting (see CMD_DES_INCLUDE_SUBLIST). */
+#define CMD_ARR_STACK_SIZE 4
+
+char *skip_white(char *p);
+int cmd_io_line_out(cmd_io_t *cmd_io);
+int cmd_io_line_in(cmd_io_t *cmd_io);
+
+#include <stdio.h>
+
+#endif
--- /dev/null
+/*
+ * cmd_proc_freertos_tms570.h
+ *
+ * Created on: 1.8.2012
+ * Author: Michal Horn
+ *
+ * Header file for cmdProc with FreeRTOS procedures included.
+ */
+
+#ifndef CMDIO_BUFFER_H_
+#define CMDIO_BUFFER_H_
+
+#define MAX_BUFFER_LEN 128
+
+#include "cmd_proc.h"
+#include "FreeRTOS.h"
+#include "os_queue.h"
+#include "os_semphr.h"
+
+
+typedef struct {
+ xQueueHandle buf;
+ xSemaphoreHandle mutex;
+ uint8_t initialized;
+} tBuffer;
+
+
+/** Initialize IO Buffers
+*/
+void initIoBuffer();
+
+/** Print string into an output buffer. Let it be blocking or nonblocking in case the buffer is full.
+ * @param[in] string String to be printed into buffer
+ * @param[in] length number of characters to be printed
+ * @param[in] ticks Number of FreeRTOS's ticks to block task, when buffer is full. portMAX_DELAY can be used.
+ * @return pdPASS when OK; errQUEUE_FULL when buffer is full and ran out of block time.
+ */
+portBASE_TYPE printToOutputBuffer(const uint8_t * string, uint32_t length, portTickType ticks);
+
+/** Print string into an input buffer. Let it be blocking or nonblocking in case the buffer is full.
+ * @param[in] string String to be printed into buffer
+ * @param[in] length number of characters to be printed
+ * @param[in] ticks Number of FreeRTOS's ticks to block task, when buffer is full. portMAX_DELAY can be used.
+ * @return pdPASS when OK; errQUEUE_FULL when buffer is full and ran out of block time.
+ */
+portBASE_TYPE printToInputBuffer(const uint8_t * string, uint32_t length, portTickType ticks);
+
+/** Read character from an output buffer. Let it be blocking or nonblocking in case the buffer is empty.
+ * @param[out] ch Character read from buffer
+ * @param[in] ticks Number of FreeRTOS's ticks to block task, when buffer is empty. portMAX_DELAY can be used.
+ * @return pdPASS when OK; errQUEUE_EMPTY when buffer is empty and ran out of block time.
+ */
+portBASE_TYPE readFromOutputBuffer(uint8_t * ch, portTickType ticks);
+
+/** Read character from an input buffer. Let it be blocking or nonblocking in case the buffer is empty.
+ * @param[out] ch Character read from buffer
+ * @param[in] ticks Number of FreeRTOS's ticks to block task, when buffer is full. portMAX_DELAY can be used.
+ * @return pdPASS when OK; errQUEUE_EMPTY when buffer is empty and ran out of block time.
+ */
+portBASE_TYPE readFromInputBuffer(uint8_t * ch, portTickType ticks);
+
+/** Read character from a buffer. Let it be blocking or nonblocking in case the buffer is empty.
+ * @param[in] buffer Pointer to buffer from which will be read.
+ * @param[out] ch Character read from buffer
+ * @param[in] ticks Number of FreeRTOS's ticks to block task, when buffer is empty. portMAX_DELAY can be used.
+ * @return pdPASS when OK; errQUEUE_EMPTY when buffer is empty and ran out of block time.
+ */
+portBASE_TYPE read(tBuffer* buffer, uint8_t * ch, portTickType ticks);
+
+/** Print string to a buffer. Let it be blocking or nonblocking in case the buffer is full.
+ * @param[in] buffer Pointer to buffer from which will be read.
+ * @param[in] string String to be printed into buffer
+ * @param[in] length number of characters to be printed
+ * @param[in] ticks Number of FreeRTOS's ticks to block task, when buffer is full. portMAX_DELAY can be used.
+ * @return pdPASS when OK; errQUEUE_FULL when buffer is full and ran out of block time.
+ */
+portBASE_TYPE print(tBuffer* buffer, const uint8_t * string, uint32_t length, portTickType ticks);
+
+/** Makes input buffer empty
+ */
+void clearInputBuffer();
+
+/** Makes output buffer empty
+ */
+void clearOutputBuffer();
+
+/** Makes buffer empty
+ * @param[in] buffer Buffer to be cleared
+ */
+void clearBuffer(tBuffer * buffer);
+
+/** Puts character into output buffer. Is blocking, when buffer is full.
+ * @param[in] cmd_io IO stack pointer
+ * @param[in] ch Character to be printed
+ * @return 1 when succes, 0 when fail
+ */
+int buf_putc(cmd_io_t *cmd_io, int ch);
+
+/** Gets character from input buffer, is blocking when buffer is empty.
+ * @param[in] cmd_io IO stack pointer
+ * @return read character
+ */
+int buf_getc(cmd_io_t *cmd_io);
+
+/** Writes string into output buffer, is blocking when buffer is full.
+ * @param[in] cmd_io IO stack pointer
+ * @param[in] buf String to be written
+ * @param[in] count Number of character to be written
+ * @return number of written characters
+ */
+int buf_write(cmd_io_t *cmd_io, const void *buf, int count);
+
+/** Reads string from input buffer, is blocking when buffer is empty.
+ * @param[in] cmd_io IO stack pointer
+ * @param[out] buf Buffer into which string be read
+ * @param[in] count Number of character to be read
+ * @return number of read characters
+ */
+int buf_read(cmd_io_t *cmd_io, void *buf, int count);
+
+#endif /* CMDIO_BUFFER_H_ */
+
--- /dev/null
+/** @file CRC.h\r
+* @brief CRC Driver Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Definitions\r
+* - Types\r
+* - Interface Prototypes\r
+* .\r
+* which are relevant for the CRC driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#include "sys_common.h"\r
+\r
+#ifndef __CRC_H__\r
+#define __CRC_H__\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* CRC General Definitions */\r
+\r
+/** @def CRCLEVEL_ACTIVE\r
+* @brief Alias name for CRC error operation level active (Error couter 0-95) \r
+*/\r
+#define CRCLEVEL_ACTIVE 0x00U\r
+\r
+\r
+/** @def CRC_AUTO\r
+* @brief Alias name for CRC auto mode\r
+*/\r
+#define CRC_AUTO 0x00000001\r
+\r
+\r
+/** @def CRC_SEMI_CPU\r
+* @brief Alias name for semi cpu mode setting\r
+*/\r
+#define CRC_SEMI_CPU 0x00000002\r
+\r
+\r
+/** @def CRC_FULL_CPU\r
+* @brief Alias name for CRC cpu full mode\r
+*/\r
+#define CRC_FULL_CPU 0x00000003\r
+\r
+\r
+/** @def CRC_CH4_TO\r
+* @brief Alias name for channel1 time out interrupt flag\r
+*/\r
+#define CRC_CH4_TO 0x10000000\r
+\r
+/** @def CRC_CH4_UR\r
+* @brief Alias name for channel1 underrun interrupt flag\r
+*/\r
+#define CRC_CH4_UR 0x08000000\r
+\r
+/** @def CRC_CH4_OR\r
+* @brief Alias name for channel1 overrun interrupt flag\r
+*/\r
+#define CRC_CH4_OR 0x04000000\r
+\r
+/** @def CRC_CH4_FAIL\r
+* @brief Alias name for channel1 crc fail interrupt flag\r
+*/\r
+#define CRC_CH4_FAIL 0x02000000\r
+\r
+/** @def CRC_CH4_CC\r
+* @brief Alias name for channel1 compression complete interrupt flag\r
+*/\r
+#define CRC_CH4_CC 0x01000000\r
+\r
+/** @def CRC_CH3_TO\r
+* @brief Alias name for channel2 time out interrupt flag\r
+*/\r
+#define CRC_CH3_TO 0x00100000\r
+\r
+/** @def CRC_CH3_UR\r
+* @brief Alias name for channel2 underrun interrupt flag\r
+*/\r
+#define CRC_CH3_UR 0x00080000\r
+\r
+/** @def CRC_CH3_OR\r
+* @brief Alias name for channel2 overrun interrupt flag\r
+*/\r
+#define CRC_CH3_OR 0x00040000\r
+\r
+/** @def CRC_CH3_FAIL\r
+* @brief Alias name for channel2 crc fail interrupt flag\r
+*/\r
+#define CRC_CH3_FAIL 0x00020000\r
+\r
+/** @def CRC_CH3_CC\r
+* @brief Alias name for channel2 compression complete interrupt flag\r
+*/\r
+#define CRC_CH3_CC 0x00010000\r
+\r
+/** @def CRC_CH2_TO\r
+* @brief Alias name for channel3 time out interrupt flag\r
+*/\r
+#define CRC_CH2_TO 0x00001000\r
+\r
+/** @def CRC_CH2_UR\r
+* @brief Alias name for channel3 underrun interrupt flag\r
+*/\r
+#define CRC_CH2_UR 0x00000800\r
+\r
+/** @def CRC_CH2_OR\r
+* @brief Alias name for channel3 overrun interrupt flag \r
+*/\r
+#define CRC_CH2_OR 0x00000400\r
+\r
+/** @def CRC_CH2_FAIL\r
+* @brief Alias name for channel3 crc fail interrupt flag \r
+*/\r
+#define CRC_CH2_FAIL 0x00000200\r
+\r
+/** @def CRC_CH2_CC\r
+* @brief Alias name for channel3 compression complete interrupt flag \r
+*/\r
+#define CRC_CH2_CC 0x00000100\r
+\r
+/** @def CRC_CH1_TO\r
+* @brief Alias name for channel4 time out interrupt flag \r
+*/\r
+#define CRC_CH1_TO 0x00000010\r
+\r
+/** @def CRC_CH1_UR\r
+* @brief Alias name for channel4 underrun interrupt flag\r
+*/\r
+#define CRC_CH1_UR 0x00000008\r
+\r
+\r
+/** @def CRC_CH1_OR\r
+* @brief Alias name for channel4 overrun interrupt flag \r
+*/\r
+#define CRC_CH1_OR 0x00000004\r
+\r
+/** @def CRC_CH1_FAIL\r
+* @brief Alias name for channel4 crc fail interrupt flag \r
+*/\r
+#define CRC_CH1_FAIL 0x00000002\r
+\r
+/** @def CRC_CH1_CC\r
+* @brief Alias name for channel4 compression complete interrupt flag \r
+*/\r
+#define CRC_CH1_CC 0x00000001\r
+\r
+\r
+\r
+/** @struct crcModConfig\r
+* @brief CRC configuration for different modes\r
+*\r
+* This type is used to pass crc mode configuration details\r
+*/\r
+/** @typedef crcModConfig_t\r
+* @brief CRC Data Type Definition\r
+*/\r
+typedef struct crcModConfig\r
+{\r
+ uint32_t mode; /**< Mode of operation */\r
+ uint32_t crc_channel; /**< CRC channel-0,1 */\r
+ uint32_t * src_data_pat; /**< Pattern data */\r
+ uint32_t data_length; /**< Pattern data length.Number of 64 bit size word*/\r
+} crcModConfig_t;\r
+\r
+/** @struct crcConfig\r
+* @brief CRC configuration for different modes\r
+*\r
+* This type is used to pass crc configuration\r
+*/\r
+/** @typedef crcConfig_t\r
+* @brief CRC Data Type Definition\r
+*/\r
+typedef struct crcConfig\r
+{\r
+ uint32_t crc_channel; /**< CRC channel-0,1 */\r
+ uint32_t mode; /**< Mode of operation */\r
+ uint32_t pcount; /**< Pattern count*/\r
+ uint32_t scount; /**< Sector count */\r
+ uint32_t wdg_preload; /**< Watchdog period */\r
+ uint32_t block_preload; /**< Block period*/\r
+\r
+} crcConfig_t;\r
+\r
+\r
+/** @struct crcBase\r
+* @brief CRC Register Frame Definition\r
+*\r
+* This type is used to access the CRC Registers.\r
+*/\r
+/** @typedef crcBASE_t\r
+* @brief CRC Register Frame Type Definition\r
+*\r
+* This type is used to access the CRC Registers.\r
+*/\r
+typedef volatile struct crcBase\r
+{\r
+ uint32_t CTRL0; /**< 0x0000: Global Control Register 0 >**/\r
+ uint32_t : 32U; /**< 0x0004: reserved >**/\r
+ uint32_t CTRL1; /**< 0x0008: Global Control Register 1 >**/\r
+ uint32_t : 32U; /**< 0x000C: reserved >**/ \r
+ uint32_t CTRL2; /**< 0x0010: Global Control Register 2 >**/\r
+ uint32_t : 32U; /**< 0x0014: reserved >**/ \r
+ uint32_t INTS; /**< 0x0018: Interrupt Enable Set Register >**/\r
+ uint32_t : 32U; /**< 0x001C: reserved >**/ \r
+ uint32_t INTR; /**< 0x0020: Interrupt Enable Reset Register >**/\r
+ uint32_t : 32U; /**< 0x0024: reserved >**/ \r
+ uint32_t STATUS; /**< 0x0028: Interrupt Status Register >**/\r
+ uint32_t : 32U; /**< 0x002C: reserved >**/ \r
+ uint32_t INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/\r
+ uint32_t : 32U; /**< 0x0034: reserved >**/ \r
+ uint32_t BUSY; /**< 0x0038: CRC Busy Register >**/\r
+ uint32_t : 32U; /**< 0x003C: reserved >**/ \r
+ uint32_t PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/\r
+ uint32_t SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/\r
+ uint32_t CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/\r
+ uint32_t WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/\r
+ uint32_t BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/\r
+ uint32_t : 32U; /**< 0x0054: reserved >**/\r
+ uint32_t : 32U; /**< 0x0058: reserved >**/\r
+ uint32_t : 32U; /**< 0x005C: reserved >**/\r
+ uint32_t PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/\r
+ uint32_t PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/\r
+ uint32_t REGL1; /**< 0x0068: Channel 1 CRC value low register >**/\r
+ uint32_t REGH1; /**< 0x006C: Channel 1 CRC value high register >**/\r
+ uint32_t PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/\r
+ uint32_t PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/\r
+ uint32_t RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/\r
+ uint32_t RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/\r
+ uint32_t PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/\r
+ uint32_t SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/\r
+ uint32_t CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/\r
+ uint32_t WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/\r
+ uint32_t BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/\r
+ uint32_t : 32U; /**< 0x0094: reserved >**/\r
+ uint32_t : 32U; /**< 0x0098: reserved >**/\r
+ uint32_t : 32U; /**< 0x009C: reserved >**/ \r
+ uint32_t PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/\r
+ uint32_t PSA_SIGREGH2; /**< 0x00A8: Channel 2 PSA signature high register >**/\r
+ uint32_t REGL2; /**< 0x00AC: Channel 2 CRC value low register >**/\r
+ uint32_t REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/\r
+ uint32_t PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/\r
+ uint32_t PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/\r
+ uint32_t RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/\r
+ uint32_t RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/\r
+}crcBASE_t;\r
+ \r
+/** @def crcREG\r
+* @brief CRC Register Frame Pointer\r
+*\r
+* This pointer is used by the CRC driver to access the CRC registers.\r
+*/\r
+#define crcREG ((crcBASE_t *)0xFE000000U)\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+/* CRC Interface Functions */\r
+void crcInit(void);\r
+void crcSendPowerDown(crcBASE_t *crc);\r
+void crcSignGen(crcBASE_t *crc,crcModConfig_t *param);\r
+void crcSetConfig(crcBASE_t *crc,crcConfig_t *param);\r
+uint64_t crcGetSectorSig(crcBASE_t *crc,uint32_t channel);\r
+uint32_t crcGetFailedSector(crcBASE_t *crc,uint32_t channel);\r
+uint32_t crcGetIntrPend(crcBASE_t *crc,uint32_t channel);\r
+void crcChannelReset(crcBASE_t *crc,uint32_t channel);\r
+void crcEnableNotification(crcBASE_t *crc, uint32_t flags);\r
+void crcDisableNotification(crcBASE_t *crc, uint32_t flags);\r
+\r
+/** @fn void crcNotification(crcBASE_t *crc, uint32_t flags)\r
+* @brief Interrupt callback\r
+* @param[in] crc - crc module base address\r
+* @param[in] flags - copy of error interrupt flags\r
+*\r
+* This is a callback that is provided by the application and is called apon\r
+* an interrupt. The parameter passed to the callback is a copy of the \r
+* interrupt flag register.\r
+*/\r
+void crcNotification(crcBASE_t *crc, uint32_t flags);\r
+\r
+\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+#endif\r
--- /dev/null
+/** @file dcc.h\r
+* @brief DCC Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __DCC_H__\r
+#define __DCC_H__\r
+\r
+#include "sys_common.h"\r
+\r
+/* DCC General Definitions */\r
+\r
+/** @def dcc1CNT0_CLKSRC_HFLPO\r
+* @brief Alias name for DCC1 Counter 0 Clock Source HFLPO\r
+*\r
+* This is an alias name for the Clock Source HFLPO for DCC1 Counter 0.\r
+*\r
+* @note This value should be used for API argument @a cnt0_Clock_Source\r
+*/\r
+#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U\r
+\r
+/** @def dcc1CNT0_CLKSRC_TCK\r
+* @brief Alias name for DCC1 Counter 0 Clock Source TCK\r
+*\r
+* This is an alias name for the Clock Source TCK for DCC1 Counter 0.\r
+*\r
+* @note This value should be used for API argument @a cnt0_Clock_Source\r
+*/\r
+#define dcc1CNT0_CLKSRC_TCK 0x0000000AU\r
+\r
+/** @def dcc1CNT0_CLKSRC_OSCIN\r
+* @brief Alias name for DCC1 Counter 0 Clock Source OSCIN\r
+*\r
+* This is an alias name for the Clock Source OSCIN for DCC1 Counter 0.\r
+*\r
+* @note This value should be used for API argument @a cnt0_Clock_Source\r
+*/\r
+#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU\r
+\r
+/** @def dcc1CNT1_CLKSRC_PLL1\r
+* @brief Alias name for DCC1 Counter 1 Clock Source PLL1\r
+*\r
+* This is an alias name for the Clock Source PLL for DCC1 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc1CNT1_CLKSRC_PLL1 0x0000A0000U\r
+\r
+/** @def dcc1CNT1_CLKSRC_PLL2\r
+* @brief Alias name for DCC1 Counter 1 Clock Source PLL2\r
+*\r
+* This is an alias name for the Clock Source OSCIN for DCC1 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc1CNT1_CLKSRC_PLL2 0x0000A0001U\r
+\r
+/** @def dcc1CNT1_CLKSRC_LFLPO\r
+* @brief Alias name for DCC1 Counter 1 Clock Source LFLPO\r
+*\r
+* This is an alias name for the Clock Source LFLPO for DCC1 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc1CNT1_CLKSRC_LFLPO 0x0000A0002U\r
+\r
+/** @def dcc1CNT1_CLKSRC_HFLPO\r
+* @brief Alias name for DCC1 Counter 1 Clock Source HFLPO\r
+*\r
+* This is an alias name for the Clock Source HFLPO for DCC1 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc1CNT1_CLKSRC_HFLPO 0x0000A0003U\r
+\r
+/** @def dcc1CNT1_CLKSRC_EXTCLKIN1\r
+* @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1\r
+*\r
+* This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A0005U\r
+\r
+/** @def dcc1CNT1_CLKSRC_EXTCLKIN2\r
+* @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2\r
+*\r
+* This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A0006U\r
+\r
+/** @def dcc1CNT1_CLKSRC_VCLK\r
+* @brief Alias name for DCC1 Counter 1 Clock Source VCLK\r
+*\r
+* This is an alias name for the Clock Source VCLK for DCC1 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc1CNT1_CLKSRC_VCLK 0x0000A0008U\r
+\r
+/** @def dcc1CNT1_CLKSRC_N2HET1_31\r
+* @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31\r
+*\r
+* This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc1CNT1_CLKSRC_N2HET1_31 0x00005000FU\r
+\r
+/** @def dcc2CNT0_CLKSRC_TCK\r
+* @brief Alias name for DCC2 Counter 0 Clock Source TCK\r
+*\r
+* This is an alias name for the Clock Source TCK for DCC2 Counter 0.\r
+*\r
+* @note This value should be used for API argument @a cnt0_Clock_Source\r
+*/\r
+#define dcc2CNT0_CLKSRC_TCK 0x0000000AU\r
+\r
+/** @def dcc1CNT0_CLKSRC_OSCIN\r
+* @brief Alias name for DCC1 Counter 0 Clock Source OSCIN\r
+*\r
+* This is an alias name for the Clock Source OSCIN for DCC2 Counter 0.\r
+*\r
+* @note This value should be used for API argument @a cnt0_Clock_Source\r
+*/\r
+#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU\r
+\r
+/** @def dcc2CNT1_CLKSRC_VCLK\r
+* @brief Alias name for DCC2 Counter 1 Clock Source VCLK\r
+*\r
+* This is an alias name for the Clock Source VCLK for DCC2 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc2CNT1_CLKSRC_VCLK 0x0000A0008U\r
+\r
+/** @def dcc2CNT1_CLKSRC_N2HET1_0\r
+* @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0\r
+*\r
+* This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1.\r
+*\r
+* @note This value should be used for API argument @a cnt1_Clock_Source\r
+*/\r
+#define dcc2CNT1_CLKSRC_N2HET1_0 0x00005000FU\r
+\r
+/** @def dccNOTIFICATION_DONE\r
+* @brief Alias name for DCC Done notification\r
+*\r
+* This is an alias name for the DCC Done notification.\r
+*\r
+* @note This value should be used for API argument @a notification\r
+*/\r
+#define dccNOTIFICATION_DONE 0x0000A000U\r
+\r
+/** @def dccNOTIFICATION_ERROR\r
+* @brief Alias name for DCC Error notification\r
+*\r
+* This is an alias name for the DCC Error notification.\r
+*\r
+* @note This value should be used for API argument @a notification\r
+*/\r
+#define dccNOTIFICATION_ERROR 0x000000A0U\r
+\r
+\r
+/** @enum dcc1clocksource\r
+* @brief Alias names for dcc clock sources\r
+*\r
+* This enumeration is used to provide alias names for the clock sources:\r
+*/\r
+enum dcc1clocksource\r
+{\r
+ DCC1_CNT0_HF_LPO = 0x5, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/\r
+ DCC1_CNT0_TCK = 0xA, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/\r
+ DCC1_CNT0_OSCIN = 0xF, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/\r
+\r
+ DCC1_CNT1_PLL1 = 0x0, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/\r
+ DCC1_CNT1_PLL2 = 0x1, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/\r
+ DCC1_CNT1_LF_LPO = 0x2, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/\r
+ DCC1_CNT1_HF_LPO = 0x3, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/\r
+ DCC1_CNT1_EXTCLKIN1 = 0x5, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/\r
+ DCC1_CNT1_EXTCLKIN2 = 0x6, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/\r
+ DCC1_CNT1_VCLK = 0x8, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/\r
+ DCC1_CNT1_N2HET1_31 = 0xA /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/\r
+};\r
+\r
+/** @enum dcc2clocksource\r
+* @brief Alias names for dcc clock sources\r
+*\r
+* This enumeration is used to provide alias names for the clock sources:\r
+*/\r
+enum dcc2clocksource\r
+{\r
+ DCC2_CNT0_OSCIN = 0xF, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/\r
+ DCC2_CNT0_TCK = 0xA, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/\r
+\r
+ DCC2_CNT1_VCLK = 0x8, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/\r
+ DCC2_CNT1_N2HET2_0 = 0xA /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/\r
+};\r
+\r
+/** @struct dccBase\r
+* @brief DCC Base Register Definition\r
+*\r
+* This structure is used to access the DCC module egisters.\r
+*/\r
+/** @typedef dccBASE_t\r
+* @brief DCC Register Frame Type Definition\r
+*\r
+* This type is used to access the DCC Registers.\r
+*/\r
+typedef volatile struct dccBase\r
+{\r
+ uint32_t GCTRL; /**< 0x0000: DCC Control Register */\r
+ uint32_t REV; /**< 0x0004: DCC Revision Id Register */\r
+ uint32_t CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */\r
+ uint32_t VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */\r
+ uint32_t CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */\r
+ uint32_t STAT; /**< 0x0014: DCC Status Register */\r
+ uint32_t CNT0; /**< 0x0018: DCC Counter0 Value Register */\r
+ uint32_t VALID0; /**< 0x001C: DCC Valid0 Value Register */\r
+ uint32_t CNT1; /**< 0x0020: DCC Counter1 Value Register */\r
+ uint32_t CLKSRC1; /**< 0x0024: DCC Counter1 Clock Source Selection Register */\r
+ uint32_t CLKSRC0; /**< 0x0028: DCC Counter0 Clock Source Selection Register */\r
+} dccBASE_t;\r
+\r
+\r
+/** @def dccREG1\r
+* @brief DCC1 Register Frame Pointer\r
+*\r
+* This pointer is used by the DCC driver to access the dcc2 module registers.\r
+*/\r
+#define dccREG1 ((dccBASE_t *)0xFFFFEC00U)\r
+\r
+\r
+/** @def dccREG2\r
+* @brief DCC2 Register Frame Pointer\r
+*\r
+* This pointer is used by the DCC driver to access the dcc2 module registers.\r
+*/\r
+#define dccREG2 ((dccBASE_t *)0xFFFFF400U)\r
+\r
+\r
+/* DCC Interface Functions */\r
+void dccInit(void);\r
+void dccSetCounter0Seed(dccBASE_t *dcc, uint32_t cnt0seed);\r
+void dccSetTolerance(dccBASE_t *dcc, uint32_t valid0seed);\r
+void dccSetCounter1Seed(dccBASE_t *dcc, uint32_t cnt1seed);\r
+void dccSetSeed(dccBASE_t *dcc, uint32_t cnt0seed, uint32_t valid0seed, uint32_t cn1seed);\r
+void dccSelectClockSource(dccBASE_t *dcc, uint32_t cnt0_Clock_Source, uint32_t cnt1_Clock_Source);\r
+void dccEnable(dccBASE_t *dcc);\r
+void dccDisable(dccBASE_t *dcc);\r
+uint32_t dccGetErrStatus(dccBASE_t *dcc);\r
+\r
+void dccEnableNotification(dccBASE_t *dcc, uint32_t notification);\r
+void dccDisableNotification(dccBASE_t *dcc, uint32_t notification);\r
+\r
+/** @fn void dccNotification(dccBASE_t *dcc,uint32_t flags)\r
+* @brief Interrupt callback\r
+* @param[in] dcc - dcc module base address\r
+* @param[in] flags - status flags\r
+*\r
+* This is a callback function provided by the application. It is call when\r
+* a dcc is complete or detected error.\r
+*/\r
+void dccNotification(dccBASE_t *dcc,uint32_t flags);\r
+\r
+#endif\r
--- /dev/null
+/** @file dmm.h\r
+* @brief DMM Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __DMM_H__\r
+#define __DMM_H__\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+\r
+\r
+/** @struct dmmBase\r
+* @brief DMM Base Register Definition\r
+*\r
+* This structure is used to access the DMM module egisters.\r
+*/\r
+/** @typedef dmmBASE_t\r
+* @brief DMM Register Frame Type Definition\r
+*\r
+* This type is used to access the DMM Registers.\r
+*/\r
+\r
+typedef volatile struct dmmBase\r
+{\r
+ uint32_t GLBCTRL; /**< 0x0000: Global control register 0 */\r
+ uint32_t INTSET; /**< 0x0004: DMM Interrupt Set Register */ \r
+ uint32_t INTCLR; /**< 0x0008: DMM Interrupt Clear Register */\r
+ uint32_t INTLVL; /**< 0x000C: DMM Interrupt Level Register */ \r
+ uint32_t INTFLG; /**< 0x0010: DMM Interrupt Flag Register */\r
+ uint32_t OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */\r
+ uint32_t OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */\r
+ uint32_t DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */\r
+ uint32_t DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */\r
+ uint32_t DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */\r
+ uint32_t INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */\r
+ uint32_t DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */\r
+ uint32_t DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */\r
+ uint32_t DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */\r
+ uint32_t DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */\r
+ uint32_t DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */\r
+ uint32_t DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */\r
+ uint32_t DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */\r
+ uint32_t DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */\r
+ uint32_t DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */\r
+ uint32_t DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */\r
+ uint32_t DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */\r
+ uint32_t DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */\r
+ uint32_t DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */\r
+ uint32_t DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */\r
+ uint32_t DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */\r
+ uint32_t DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */\r
+ uint32_t PC0; /**< 0x006C: DMM Pin Control 0 */\r
+ uint32_t PC1; /**< 0x0070: DMM Pin Control 1 */ \r
+ uint32_t PC2; /**< 0x0074: DMM Pin Control 2 */\r
+ uint32_t PC3; /**< 0x0078: DMM Pin Control 3 */\r
+ uint32_t PC4; /**< 0x007C: DMM Pin Control 4 */\r
+ uint32_t PC5; /**< 0x0080: DMM Pin Control 5 */\r
+ uint32_t PC6; /**< 0x0084: DMM Pin Control 6 */\r
+ uint32_t PC7; /**< 0x0088: DMM Pin Control 7 */\r
+ uint32_t PC8; /**< 0x008C: DMM Pin Control 8 */\r
+} dmmBASE_t;\r
+\r
+\r
+/** @def dmmREG\r
+* @brief DMM Register Frame Pointer\r
+*\r
+* This pointer is used by the DMM driver to access the DMM module registers.\r
+*/\r
+#define dmmREG ((dmmBASE_t *)0xFFFFF700U)\r
+\r
+/** @def dmmPORT\r
+* @brief DMM Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of DMM\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define dmmPORT ((gioPORT_t *)0xFFFFF738U)\r
+\r
+\r
+/* DMM Interface Functions */\r
+\r
+void dmmInit(void);\r
+\r
+#endif\r
--- /dev/null
+/**\r
+ * \file emac.h\r
+ *\r
+ * \brief EMAC APIs and macros.\r
+ *\r
+ * This file contains the driver API prototypes and macro definitions.\r
+ */\r
+\r
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ * ALL RIGHTS RESERVED\r
+ */\r
+#ifndef __EMAC_H__\r
+#define __EMAC_H__\r
+\r
+#include "hw_emac.h"\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*****************************************************************************/\r
+/*\r
+** Macros which can be used as speed parameter to the API EMACRMIISpeedSet\r
+*/\r
+#define EMAC_RMIISPEED_10MBPS (0x00000000u)\r
+#define EMAC_RMIISPEED_100MBPS (0x00008000u)\r
+\r
+/*\r
+** Macros which can be used as duplexMode parameter to the API \r
+** EMACDuplexSet\r
+*/\r
+#define EMAC_DUPLEX_FULL (0x00000001u)\r
+#define EMAC_DUPLEX_HALF (0x00000000u)\r
+\r
+/*\r
+** Macros which can be used as matchFilt parameters to the API \r
+** EMACMACAddrSet\r
+*/\r
+/* Address not used to match/filter incoming packets */\r
+#define EMAC_MACADDR_NO_MATCH_NO_FILTER (0x00000000u)\r
+\r
+/* Address will be used to filter incoming packets */\r
+#define EMAC_MACADDR_FILTER (0x00100000u)\r
+\r
+/* Address will be used to match incoming packets */\r
+#define EMAC_MACADDR_MATCH (0x00180000u)\r
+\r
+/*\r
+** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API\r
+*/\r
+#define EMAC_INT_CORE0_RX (0x1u)\r
+#define EMAC_INT_CORE1_RX (0x5u)\r
+#define EMAC_INT_CORE2_RX (0x9u)\r
+\r
+/*\r
+** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API\r
+*/\r
+#define EMAC_INT_CORE0_TX (0x2u)\r
+#define EMAC_INT_CORE1_TX (0x6u)\r
+#define EMAC_INT_CORE2_TX (0xAu)\r
+\r
+/*****************************************************************************/\r
+/*\r
+** Prototypes for the APIs\r
+*/\r
+extern void EMACTxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase,\r
+ unsigned int ctrlCore, unsigned int channel);\r
+extern void EMACTxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase,\r
+ unsigned int ctrlCore, unsigned int channel);\r
+extern void EMACRxIntPulseEnable(unsigned int emacBase, unsigned int emacCtrlBase,\r
+ unsigned int ctrlCore, unsigned int channel);\r
+extern void EMACRxIntPulseDisable(unsigned int emacBase, unsigned int emacCtrlBase,\r
+ unsigned int ctrlCore, unsigned int channel);\r
+extern void EMACRMIISpeedSet(unsigned int emacBase, unsigned int speed);\r
+extern void EMACDuplexSet(unsigned int emacBase, unsigned int duplexMode);\r
+extern void EMACTxEnable(unsigned int emacBase);\r
+extern void EMACRxEnable(unsigned int emacBase);\r
+extern void EMACTxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr,\r
+ unsigned int channel);\r
+extern void EMACRxHdrDescPtrWrite(unsigned int emacBase, unsigned int descHdr,\r
+ unsigned int channel);\r
+extern void EMACInit(unsigned int emacCtrlBase, unsigned int emacBase);\r
+extern void EMACMACSrcAddrSet(unsigned int emacBase, unsigned char *macAddr);\r
+extern void EMACMACAddrSet(unsigned int emacBase, unsigned int channel,\r
+ unsigned char *macAddr, unsigned int matchFilt);\r
+extern void EMACMIIEnable(unsigned int emacBase);\r
+extern void EMACRxUnicastSet(unsigned int emacBase, unsigned int channel);\r
+extern void EMACCoreIntAck(unsigned int emacBase, unsigned int eoiFlag);\r
+extern void EMACTxCPWrite(unsigned int emacBase, unsigned int channel,\r
+ unsigned int comPtr);\r
+extern void EMACRxCPWrite(unsigned int emacBase, unsigned int channel,\r
+ unsigned int comPtr);\r
+extern void EMACRxBroadCastEnable(unsigned int emacBase, unsigned int channel);\r
+extern void EMACNumFreeBufSet(unsigned int emacBase, unsigned int channel,\r
+ unsigned int nBuf);\r
+extern unsigned int EMACIntVectorGet(unsigned int emacBase);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __EMAC_H__ */\r
--- /dev/null
+/** @file emif.h\r
+* @brief emif Driver Definition File\r
+* @date 15.Feb.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#ifndef _EMIF_H_\r
+#define _EMIF_H_\r
+\r
+#include "sys_common.h"\r
+\r
+/** @enum emif_pins\r
+* @brief Alias for emif pins\r
+*\r
+*/\r
+enum emif_pins\r
+{\r
+ emif_wait_pin0 = 0,\r
+ emif_wait_pin1 = 1\r
+};\r
+\r
+\r
+/** @enum emif_size\r
+* @brief Alias for emif page size\r
+*\r
+*/\r
+enum emif_size\r
+{\r
+ elements_256 = 0,\r
+ elements_512 = 1,\r
+ elements_1024 = 2,\r
+ elements_2048 = 3\r
+};\r
+\r
+/** @enum emif_port\r
+* @brief Alias for emif port\r
+*\r
+*/\r
+enum emif_port\r
+{\r
+ emif_8_bit_port = 0,\r
+ emif_16_bit_port = 1\r
+};\r
+\r
+\r
+/** @enum emif_pagesize\r
+* @brief Alias for emif pagesize\r
+*\r
+*/\r
+enum emif_pagesize\r
+{\r
+ emif_4_words = 0,\r
+ emif_8_words = 1\r
+};\r
+\r
+/** @enum emif_wait_polarity\r
+* @brief Alias for emif wait polarity\r
+*\r
+*/\r
+enum emif_wait_polarity\r
+{\r
+ emif_pin_low = 0,\r
+ emif_pin_high = 1\r
+};\r
+\r
+\r
+#define PTR (uint32_t *)(0x80000000)\r
+\r
+/** @struct emifBASE_t\r
+* @brief emifBASE Register Definition\r
+*\r
+* This structure is used to access the EMIF module egisters.\r
+*/\r
+typedef volatile struct emifBase\r
+{\r
+ uint32_t MIDR; /**< 0x0000 Module ID Register */\r
+ uint32_t AWCC; /**< 0x0004 Asynchronous wait cycle register*/\r
+ uint32_t SDCR; /**< 0x0008 SDRAM configuratiopn register */\r
+ uint32_t SDRCR ; /**< 0x000C Set Interrupt Enable Register */\r
+ uint32_t CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */\r
+ uint32_t CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */\r
+ uint32_t CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */\r
+ uint32_t CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */\r
+ uint32_t SDTIMR; /**< 0x0020 SDRAM Timing Register */\r
+ uint32_t dummy1[6]; /** reserved **/\r
+ uint32_t SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */\r
+ uint32_t INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/\r
+ uint32_t INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */\r
+ uint32_t INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */\r
+ uint32_t INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */\r
+ uint32_t dummy2[6]; /** reserved **/\r
+ uint32_t PMCR; /**< 0x0068 Page Mode Control Register*/\r
+\r
+} emifBASE_t;\r
+\r
+#define emifREG ((emifBASE_t *)0xFCFFE800U)\r
+\r
+/* EMIF Interface Functions */\r
+\r
+void emif_SDRAMInit(void);\r
+void emif_ASYNC1Init(void);\r
+void emif_ASYNC2Init(void);\r
+void emif_ASYNC3Init(void);\r
+\r
+\r
+#endif /*EMIF_H_*/\r
--- /dev/null
+/** @file esm.h\r
+* @brief Error Signaling Module Driver Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Definitions\r
+* - Types\r
+* .\r
+* which are relevant for the Esm driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2010, All rights reserved. */\r
+\r
+#ifndef __ESM_H__\r
+#define __ESM_H__\r
+\r
+#include "sys_common.h"\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* ESM General Definitions */\r
+\r
+/** @def esmGROUP1\r
+* @brief Alias name for ESM group 1\r
+*\r
+* This is an alias name for the ESM group 1.\r
+*\r
+* @note This value should be used for API argument @a group\r
+*/\r
+#define esmGROUP1 0U\r
+\r
+/** @def esmGROUP2\r
+* @brief Alias name for ESM group 2\r
+*\r
+* This is an alias name for the ESM group 2.\r
+*\r
+* @note This value should be used for API argument @a group\r
+*/\r
+#define esmGROUP2 1U\r
+\r
+/** @def esmGROUP3\r
+* @brief Alias name for ESM group 3\r
+*\r
+* This is an alias name for the ESM group 3.\r
+*\r
+* @note This value should be used for API argument @a group\r
+*/\r
+#define esmGROUP3 2U\r
+\r
+/** @def esmCHANNEL0\r
+* @brief Alias name for ESM group x channel 0\r
+*\r
+* This is an alias name for the ESM group x channel 0.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL0 0x0000000000000001ULL\r
+\r
+/** @def esmCHANNEL1\r
+* @brief Alias name for ESM group x channel 1\r
+*\r
+* This is an alias name for the ESM group x channel 1.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL1 0x0000000000000002ULL\r
+\r
+/** @def esmCHANNEL2\r
+* @brief Alias name for ESM group x channel 2\r
+*\r
+* This is an alias name for the ESM group x channel 2.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL2 0x0000000000000004ULL\r
+\r
+/** @def esmCHANNEL3\r
+* @brief Alias name for ESM group x channel 3\r
+*\r
+* This is an alias name for the ESM group x channel 3.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL3 0x0000000000000008ULL\r
+\r
+/** @def esmCHANNEL4\r
+* @brief Alias name for ESM group x channel 4\r
+*\r
+* This is an alias name for the ESM group x channel 4.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL4 0x0000000000000010ULL\r
+\r
+/** @def esmCHANNEL5\r
+* @brief Alias name for ESM group x channel 5\r
+*\r
+* This is an alias name for the ESM group x channel 5.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL5 0x0000000000000020ULL\r
+\r
+/** @def esmCHANNEL6\r
+* @brief Alias name for ESM group x channel 6\r
+*\r
+* This is an alias name for the ESM group x channel 6.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL6 0x0000000000000040ULL\r
+\r
+/** @def esmCHANNEL7\r
+* @brief Alias name for ESM group x channel 7\r
+*\r
+* This is an alias name for the ESM group x channel 7.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL7 0x0000000000000080ULL\r
+\r
+/** @def esmCHANNEL8\r
+* @brief Alias name for ESM group x channel 8\r
+*\r
+* This is an alias name for the ESM group x channel 8.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL8 0x0000000000000100ULL\r
+\r
+/** @def esmCHANNEL9\r
+* @brief Alias name for ESM group x channel 9\r
+*\r
+* This is an alias name for the ESM group x channel 9.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL9 0x0000000000000200ULL\r
+\r
+/** @def esmCHANNEL10\r
+* @brief Alias name for ESM group x channel 10\r
+*\r
+* This is an alias name for the ESM group x channel 10.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL10 0x0000000000000400ULL\r
+\r
+/** @def esmCHANNEL11\r
+* @brief Alias name for ESM group x channel 11\r
+*\r
+* This is an alias name for the ESM group x channel 11.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL11 0x0000000000000800ULL\r
+\r
+/** @def esmCHANNEL12\r
+* @brief Alias name for ESM group x channel 12\r
+*\r
+* This is an alias name for the ESM group x channel 12.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL12 0x0000000000001000ULL\r
+\r
+/** @def esmCHANNEL13\r
+* @brief Alias name for ESM group x channel 13\r
+*\r
+* This is an alias name for the ESM group x channel 13.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL13 0x0000000000002000ULL\r
+\r
+/** @def esmCHANNEL14\r
+* @brief Alias name for ESM group x channel 14\r
+*\r
+* This is an alias name for the ESM group x channel 14.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL14 0x0000000000004000ULL\r
+\r
+/** @def esmCHANNEL15\r
+* @brief Alias name for ESM group x channel 15\r
+*\r
+* This is an alias name for the ESM group x channel 15.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL15 0x0000000000008000ULL\r
+\r
+/** @def esmCHANNEL16\r
+* @brief Alias name for ESM group x channel 16\r
+*\r
+* This is an alias name for the ESM group x channel 16.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL16 0x0000000000010000ULL\r
+\r
+/** @def esmCHANNEL17\r
+* @brief Alias name for ESM group x channel 17\r
+*\r
+* This is an alias name for the ESM group x channel 17.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL17 0x0000000000020000ULL\r
+\r
+/** @def esmCHANNEL18\r
+* @brief Alias name for ESM group x channel 18\r
+*\r
+* This is an alias name for the ESM group x channel 18.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL18 0x0000000000040000ULL\r
+\r
+/** @def esmCHANNEL19\r
+* @brief Alias name for ESM group x channel 19\r
+*\r
+* This is an alias name for the ESM group x channel 19.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL19 0x0000000000080000ULL\r
+\r
+/** @def esmCHANNEL20\r
+* @brief Alias name for ESM group x channel 20\r
+*\r
+* This is an alias name for the ESM group x channel 20.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL20 0x0000000000100000ULL\r
+\r
+/** @def esmCHANNEL21\r
+* @brief Alias name for ESM group x channel 21\r
+*\r
+* This is an alias name for the ESM group x channel 21.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL21 0x0000000000200000ULL\r
+\r
+/** @def esmCHANNEL22\r
+* @brief Alias name for ESM group x channel 22\r
+*\r
+* This is an alias name for the ESM group x channel 22.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL22 0x0000000000400000ULL\r
+\r
+/** @def esmCHANNEL23\r
+* @brief Alias name for ESM group x channel 23\r
+*\r
+* This is an alias name for the ESM group x channel 23.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL23 0x0000000000800000ULL\r
+\r
+/** @def esmCHANNEL24\r
+* @brief Alias name for ESM group x channel 24\r
+*\r
+* This is an alias name for the ESM group x channel 24.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL24 0x0000000001000000ULL\r
+\r
+/** @def esmCHANNEL25\r
+* @brief Alias name for ESM group x channel 25\r
+*\r
+* This is an alias name for the ESM group x channel 25.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL25 0x0000000002000000ULL\r
+\r
+/** @def esmCHANNEL26\r
+* @brief Alias name for ESM group x channel 26\r
+*\r
+* This is an alias name for the ESM group x channel 26.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL26 0x0000000004000000ULL\r
+\r
+/** @def esmCHANNEL27\r
+* @brief Alias name for ESM group x channel 27\r
+*\r
+* This is an alias name for the ESM group x channel 27.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL27 0x0000000008000000ULL\r
+\r
+/** @def esmCHANNEL28\r
+* @brief Alias name for ESM group x channel 28\r
+*\r
+* This is an alias name for the ESM group x channel 28.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL28 0x0000000010000000ULL\r
+\r
+/** @def esmCHANNEL29\r
+* @brief Alias name for ESM group x channel 29\r
+*\r
+* This is an alias name for the ESM group x channel 29.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL29 0x0000000020000000ULL\r
+\r
+/** @def esmCHANNEL30\r
+* @brief Alias name for ESM group x channel 30\r
+*\r
+* This is an alias name for the ESM group x channel 30.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL30 0x0000000040000000ULL\r
+\r
+/** @def esmCHANNEL31\r
+* @brief Alias name for ESM group x channel 31\r
+*\r
+* This is an alias name for the ESM group x channel 31.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL31 0x0000000080000000ULL\r
+\r
+/** @def esmCHANNEL32\r
+* @brief Alias name for ESM group x channel 32\r
+*\r
+* This is an alias name for the ESM group x channel 32.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL32 0x0000000100000000ULL\r
+\r
+/** @def esmCHANNEL33\r
+* @brief Alias name for ESM group x channel 33\r
+*\r
+* This is an alias name for the ESM group x channel 33.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL33 0x0000000200000000ULL\r
+\r
+/** @def esmCHANNEL34\r
+* @brief Alias name for ESM group x channel 34\r
+*\r
+* This is an alias name for the ESM group x channel 34.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL34 0x0000000400000000ULL\r
+\r
+/** @def esmCHANNEL35\r
+* @brief Alias name for ESM group x channel 35\r
+*\r
+* This is an alias name for the ESM group x channel 35.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL35 0x0000000800000000ULL\r
+\r
+/** @def esmCHANNEL36\r
+* @brief Alias name for ESM group x channel 36\r
+*\r
+* This is an alias name for the ESM group x channel 36.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL36 0x0000001000000000ULL\r
+\r
+/** @def esmCHANNEL37\r
+* @brief Alias name for ESM group x channel 37\r
+*\r
+* This is an alias name for the ESM group x channel 37.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL37 0x0000002000000000ULL\r
+\r
+/** @def esmCHANNEL38\r
+* @brief Alias name for ESM group x channel 38\r
+*\r
+* This is an alias name for the ESM group x channel 38.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL38 0x0000004000000000ULL\r
+\r
+/** @def esmCHANNEL39\r
+* @brief Alias name for ESM group x channel 39\r
+*\r
+* This is an alias name for the ESM group x channel 39.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL39 0x0000008000000000ULL\r
+\r
+/** @def esmCHANNEL40\r
+* @brief Alias name for ESM group x channel 40\r
+*\r
+* This is an alias name for the ESM group x channel 40.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL40 0x0000010000000000ULL\r
+\r
+/** @def esmCHANNEL41\r
+* @brief Alias name for ESM group x channel 41\r
+*\r
+* This is an alias name for the ESM group x channel 41.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL41 0x0000020000000000ULL\r
+\r
+/** @def esmCHANNEL42\r
+* @brief Alias name for ESM group x channel 42\r
+*\r
+* This is an alias name for the ESM group x channel 42.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL42 0x0000040000000000ULL\r
+\r
+/** @def esmCHANNEL43\r
+* @brief Alias name for ESM group x channel 43\r
+*\r
+* This is an alias name for the ESM group x channel 43.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL43 0x0000080000000000ULL\r
+\r
+/** @def esmCHANNEL44\r
+* @brief Alias name for ESM group x channel 44\r
+*\r
+* This is an alias name for the ESM group x channel 44.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL44 0x0000100000000000ULL\r
+\r
+/** @def esmCHANNEL45\r
+* @brief Alias name for ESM group x channel 45\r
+*\r
+* This is an alias name for the ESM group x channel 45.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL45 0x0000200000000000ULL\r
+\r
+/** @def esmCHANNEL46\r
+* @brief Alias name for ESM group x channel 46\r
+*\r
+* This is an alias name for the ESM group x channel 46.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL46 0x0000400000000000ULL\r
+\r
+/** @def esmCHANNEL47\r
+* @brief Alias name for ESM group x channel 47\r
+*\r
+* This is an alias name for the ESM group x channel 47.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL47 0x0000800000000000ULL\r
+\r
+/** @def esmCHANNEL48\r
+* @brief Alias name for ESM group x channel 48\r
+*\r
+* This is an alias name for the ESM group x channel 48.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL48 0x0001000000000000ULL\r
+\r
+/** @def esmCHANNEL49\r
+* @brief Alias name for ESM group x channel 49\r
+*\r
+* This is an alias name for the ESM group x channel 49.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL49 0x0002000000000000ULL\r
+\r
+/** @def esmCHANNEL50\r
+* @brief Alias name for ESM group x channel 50\r
+*\r
+* This is an alias name for the ESM group x channel 50.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL50 0x0004000000000000ULL\r
+\r
+/** @def esmCHANNEL51\r
+* @brief Alias name for ESM group x channel 51\r
+*\r
+* This is an alias name for the ESM group x channel 51.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL51 0x0008000000000000ULL\r
+\r
+/** @def esmCHANNEL52\r
+* @brief Alias name for ESM group x channel 52\r
+*\r
+* This is an alias name for the ESM group x channel 52.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL52 0x0010000000000000ULL\r
+\r
+/** @def esmCHANNEL53\r
+* @brief Alias name for ESM group x channel 53\r
+*\r
+* This is an alias name for the ESM group x channel 53.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL53 0x0020000000000000ULL\r
+\r
+/** @def esmCHANNEL54\r
+* @brief Alias name for ESM group x channel 54\r
+*\r
+* This is an alias name for the ESM group x channel 54.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL54 0x0040000000000000ULL\r
+\r
+/** @def esmCHANNEL55\r
+* @brief Alias name for ESM group x channel 55\r
+*\r
+* This is an alias name for the ESM group x channel 55.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL55 0x0080000000000000ULL\r
+\r
+/** @def esmCHANNEL56\r
+* @brief Alias name for ESM group x channel 56\r
+*\r
+* This is an alias name for the ESM group x channel 56.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL56 0x0100000000000000ULL\r
+\r
+/** @def esmCHANNEL57\r
+* @brief Alias name for ESM group x channel 57\r
+*\r
+* This is an alias name for the ESM group x channel 57.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL57 0x0200000000000000ULL\r
+\r
+/** @def esmCHANNEL58\r
+* @brief Alias name for ESM group x channel 58\r
+*\r
+* This is an alias name for the ESM group x channel 58.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL58 0x0400000000000000ULL\r
+\r
+/** @def esmCHANNEL59\r
+* @brief Alias name for ESM group x channel 59\r
+*\r
+* This is an alias name for the ESM group x channel 59.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL59 0x0800000000000000ULL\r
+\r
+/** @def esmCHANNEL60\r
+* @brief Alias name for ESM group x channel 60\r
+*\r
+* This is an alias name for the ESM group x channel 60.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL60 0x1000000000000000ULL\r
+\r
+/** @def esmCHANNEL61\r
+* @brief Alias name for ESM group x channel 61\r
+*\r
+* This is an alias name for the ESM group x channel 61.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL61 0x2000000000000000ULL\r
+\r
+/** @def esmCHANNEL62\r
+* @brief Alias name for ESM group x channel 62\r
+*\r
+* This is an alias name for the ESM group x channel 62.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL62 0x4000000000000000ULL\r
+\r
+/** @def esmCHANNEL63\r
+* @brief Alias name for ESM group x channel 63\r
+*\r
+* This is an alias name for the ESM group x channel 63.\r
+*\r
+* @note This value should be used for API argument @a channel\r
+*/\r
+#define esmCHANNEL63 0x8000000000000000ULL\r
+\r
+\r
+\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Esm Register Frame Definition */\r
+/** @struct esmBase\r
+* @brief Esm Register Frame Definition\r
+*\r
+* This type is used to access the Esm Registers.\r
+*/\r
+/** @typedef esmBASE_t\r
+* @brief Esm Register Frame Type Definition\r
+*\r
+* This type is used to access the Esm Registers.\r
+*/\r
+typedef volatile struct esmBase\r
+{\r
+ uint32_t EPENASET1; /* 0x0000 */\r
+ uint32_t EPENACLR1; /* 0x0004 */\r
+ uint32_t INTENASET1; /* 0x0008 */\r
+ uint32_t INTENACLR1; /* 0x000C */\r
+ uint32_t INTLVLSET1; /* 0x0010 */\r
+ uint32_t INTLVLCLR1; /* 0x0014 */\r
+ uint32_t ESTATUS1[3U]; /* 0x0018, 0x001C, 0x0020 */\r
+ uint32_t EPSTATUS; /* 0x0024 */\r
+ uint32_t INTOFFH; /* 0x0028 */\r
+ uint32_t INTOFFL; /* 0x002C */\r
+ uint32_t LTC; /* 0x0030 */\r
+ uint32_t LTCPRELOAD; /* 0x0034 */\r
+ uint32_t KEY; /* 0x0038 */\r
+ uint32_t ESTATUS2EMU; /* 0x003C */\r
+ uint32_t EPENASET4; /* 0x0040 */\r
+ uint32_t EPENACLR4; /* 0x0044 */\r
+ uint32_t INTENASET4; /* 0x0048 */\r
+ uint32_t INTENACLR4; /* 0x004C */\r
+ uint32_t INTLVLSET4; /* 0x0050 */\r
+ uint32_t INTLVLCLR4; /* 0x0054 */\r
+ uint32_t ESTATUS4[3U]; /* 0x0058, 0x005C, 0x0060 */\r
+ uint32_t ESTATUS5EMU; /* 0x0064 */\r
+} esmBASE_t;\r
+\r
+/** @def esmREG\r
+* @brief Esm Register Frame Pointer\r
+*\r
+* This pointer is used by the Esm driver to access the Esm registers.\r
+*/\r
+#define esmREG ((esmBASE_t *)0xFFFFF500U)\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Esm Interface Functions */\r
+void esmInit(void);\r
+uint32_t esmError(void);\r
+void esmEnableError(uint64_t channels);\r
+void esmDisableError(uint64_t channels);\r
+void esmTriggerErrorPinReset(void);\r
+void esmActivateNormalOperation(void);\r
+void esmEnableInterrupt(uint64_t channels);\r
+void esmDisableInterrupt(uint64_t channels);\r
+void esmSetInterruptLevel(uint64_t channels, uint64_t flags);\r
+void esmClearStatus(uint32_t group, uint64_t channels);\r
+void esmClearStatusBuffer(uint64_t channels);\r
+void esmSetCounterPreloadValue(uint32_t value);\r
+\r
+uint64_t esmGetStatus(uint32_t group, uint64_t channels);\r
+uint64_t esmGetStatusBuffer(uint64_t channels);\r
+\r
+\r
+/** @fn void esmGroup1Notification(uint32_t channel)\r
+* @brief Interrupt callback\r
+* @param[in] channel - Group 1 channel\r
+*\r
+* This is a callback that is provided by the application and is called apon\r
+* an interrupt. The parameter passed to the callback is group 1 channel caused the interrupt.\r
+*/\r
+void esmGroup1Notification(uint32_t channel);\r
+\r
+\r
+/** @fn void esmGroup2Notification(uint32_t channel)\r
+* @brief Interrupt callback\r
+* @param[in] channel - Group 2 channel\r
+*\r
+* This is a callback that is provided by the application and is called apon\r
+* an interrupt. The parameter passed to the callback is group 2 channel caused the interrupt.\r
+*/\r
+void esmGroup2Notification(uint32_t channel);\r
+\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file gio.h\r
+* @brief GIO Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#include "sys_common.h"\r
+\r
+#ifndef __GIO_H__\r
+#define __GIO_H__\r
+\r
+/** @struct gioBase\r
+* @brief GIO Base Register Definition\r
+*\r
+* This structure is used to access the GIO module egisters.\r
+*/\r
+/** @typedef gioBASE_t\r
+* @brief GIO Register Frame Type Definition\r
+*\r
+* This type is used to access the GIO Registers.\r
+*/\r
+typedef volatile struct gioBase\r
+{\r
+ uint32_t GCR0; /**< 0x0000: Global Control Register */\r
+ uint32_t PWDN; /**< 0x0004: Power Down Register */\r
+ uint32_t INTDET; /**< 0x0008: Interrupt Detect Regsiter*/\r
+ uint32_t POL; /**< 0x000C: Interrupt Polarity Register */\r
+ uint32_t INTENASET; /**< 0x0010: Interrupt Enable Set Register */\r
+ uint32_t INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */\r
+ uint32_t LVLSET; /**< 0x0018: Interrupt Priority Set Register */\r
+ uint32_t LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */\r
+ uint32_t FLG; /**< 0x0020: Interrupt Flag Register */\r
+ uint32_t OFFSET0; /**< 0x0024: Interrupt Offset A Register */\r
+ uint32_t OFFSET1; /**< 0x0028: Interrupt Offset B Register */\r
+} gioBASE_t;\r
+\r
+\r
+/** @struct gioPort\r
+* @brief GIO Port Register Definition\r
+*/\r
+/** @typedef gioPORT_t\r
+* @brief GIO Port Register Type Definition\r
+*\r
+* This type is used to access the GIO Port Registers.\r
+*/\r
+typedef volatile struct gioPort\r
+{\r
+ uint32_t DIR; /**< 0x0000: Data Direction Register */\r
+ uint32_t DIN; /**< 0x0004: Data Input Register */\r
+ uint32_t DOUT; /**< 0x0008: Data Output Register */\r
+ uint32_t DSET; /**< 0x000C: Data Output Set Register */\r
+ uint32_t DCLR; /**< 0x0010: Data Output Clear Register */\r
+ uint32_t PDR; /**< 0x0014: Open Drain Regsiter */\r
+ uint32_t PULDIS; /**< 0x0018: Pullup Disable Register */\r
+ uint32_t PSL; /**< 0x001C: Pull Up/Down Selection Register */\r
+} gioPORT_t;\r
+\r
+\r
+/** @def gioREG\r
+* @brief GIO Register Frame Pointer\r
+*\r
+* This pointer is used by the GIO driver to access the gio module registers.\r
+*/\r
+#define gioREG ((gioBASE_t *)0xFFF7BC00U)\r
+\r
+/** @def gioPORTA\r
+* @brief GIO Port (A) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTA\r
+*/\r
+#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)\r
+\r
+/** @def gioPORTB\r
+* @brief GIO Port (B) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTB\r
+*/\r
+#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)\r
+\r
+\r
+/* GIO Interface Functions */\r
+void gioInit(void);\r
+void gioSetDirection(gioPORT_t *port, uint32_t dir);\r
+void gioSetBit(gioPORT_t *port, uint32_t bit, uint32_t value);\r
+void gioSetPort(gioPORT_t *port, uint32_t value);\r
+uint32_t gioGetBit(gioPORT_t *port, uint32_t bit);\r
+uint32_t gioGetPort(gioPORT_t *port);\r
+void gioToggleBit(gioPORT_t *port, uint32_t bit);\r
+void gioEnableNotification(uint32_t bit);\r
+void gioDisableNotification(uint32_t bit);\r
+void gioNotification(int bit);\r
+\r
+#endif\r
--- /dev/null
+/** @file het.h\r
+* @brief HET Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __HET_H__\r
+#define __HET_H__\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+#include <string.h>\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+/** @def pwm0\r
+* @brief Pwm signal 0\r
+*\r
+* Alias for pwm signal 0\r
+*/\r
+#define pwm0 0U\r
+\r
+/** @def pwm1\r
+* @brief Pwm signal 1\r
+*\r
+* Alias for pwm signal 1\r
+*/\r
+#define pwm1 1U\r
+\r
+/** @def pwm2\r
+* @brief Pwm signal 2\r
+*\r
+* Alias for pwm signal 2\r
+*/\r
+#define pwm2 2U\r
+\r
+/** @def pwm3\r
+* @brief Pwm signal 3\r
+*\r
+* Alias for pwm signal 3\r
+*/\r
+#define pwm3 3U\r
+\r
+/** @def pwm4\r
+* @brief Pwm signal 4\r
+*\r
+* Alias for pwm signal 4\r
+*/\r
+#define pwm4 4U\r
+\r
+/** @def pwm5\r
+* @brief Pwm signal 5\r
+*\r
+* Alias for pwm signal 5\r
+*/\r
+#define pwm5 5U\r
+\r
+/** @def pwm6\r
+* @brief Pwm signal 6\r
+*\r
+* Alias for pwm signal 6\r
+*/\r
+#define pwm6 6U\r
+\r
+/** @def pwm7\r
+* @brief Pwm signal 7\r
+*\r
+* Alias for pwm signal 7\r
+*/\r
+#define pwm7 7U\r
+\r
+\r
+/** @def edge0\r
+* @brief Edge signal 0\r
+*\r
+* Alias for edge signal 0\r
+*/\r
+#define edge0 0U\r
+\r
+/** @def edge1\r
+* @brief Edge signal 1\r
+*\r
+* Alias for edge signal 1\r
+*/\r
+#define edge1 1U\r
+\r
+/** @def edge2\r
+* @brief Edge signal 2\r
+*\r
+* Alias for edge signal 2\r
+*/\r
+#define edge2 2U\r
+\r
+/** @def edge3\r
+* @brief Edge signal 3\r
+*\r
+* Alias for edge signal 3\r
+*/\r
+#define edge3 3U\r
+\r
+/** @def edge4\r
+* @brief Edge signal 4\r
+*\r
+* Alias for edge signal 4\r
+*/\r
+#define edge4 4U\r
+\r
+/** @def edge5\r
+* @brief Edge signal 5\r
+*\r
+* Alias for edge signal 5\r
+*/\r
+#define edge5 5U\r
+\r
+/** @def edge6\r
+* @brief Edge signal 6\r
+*\r
+* Alias for edge signal 6\r
+*/\r
+#define edge6 6U\r
+\r
+/** @def edge7\r
+* @brief Edge signal 7\r
+*\r
+* Alias for edge signal 7\r
+*/\r
+#define edge7 7U\r
+\r
+\r
+/** @def cap0\r
+* @brief Capture signal 0\r
+*\r
+* Alias for capture signal 0\r
+*/\r
+#define cap0 0U\r
+\r
+/** @def cap1\r
+* @brief Capture signal 1\r
+*\r
+* Alias for capture signal 1\r
+*/\r
+#define cap1 1U\r
+\r
+/** @def cap2\r
+* @brief Capture signal 2\r
+*\r
+* Alias for capture signal 2\r
+*/\r
+#define cap2 2U\r
+\r
+/** @def cap3\r
+* @brief Capture signal 3\r
+*\r
+* Alias for capture signal 3\r
+*/\r
+#define cap3 3U\r
+\r
+/** @def cap4\r
+* @brief Capture signal 4\r
+*\r
+* Alias for capture signal 4\r
+*/\r
+#define cap4 4U\r
+\r
+/** @def cap5\r
+* @brief Capture signal 5\r
+*\r
+* Alias for capture signal 5\r
+*/\r
+#define cap5 5U\r
+\r
+/** @def cap6\r
+* @brief Capture signal 6\r
+*\r
+* Alias for capture signal 6\r
+*/\r
+#define cap6 6U\r
+\r
+/** @def cap7\r
+* @brief Capture signal 7\r
+*\r
+* Alias for capture signal 7\r
+*/\r
+#define cap7 7U\r
+\r
+/** @def pwmEND_OF_DUTY\r
+* @brief Pwm end of duty\r
+*\r
+* Alias for pwm end of duty notification\r
+*/\r
+#define pwmEND_OF_DUTY 2U\r
+\r
+/** @def pwmEND_OF_PERIOD\r
+* @brief Pwm end of period\r
+*\r
+* Alias for pwm end of period notification\r
+*/\r
+#define pwmEND_OF_PERIOD 4U\r
+\r
+/** @def pwmEND_OF_BOTH\r
+* @brief Pwm end of duty and period\r
+*\r
+* Alias for pwm end of duty and period notification\r
+*/\r
+#define pwmEND_OF_BOTH 6U\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+/** @struct hetBase\r
+* @brief HET Register Definition\r
+*\r
+* This structure is used to access the HET module egisters.\r
+*/\r
+/** @typedef hetBASE_t\r
+* @brief HET Register Frame Type Definition\r
+*\r
+* This type is used to access the HET Registers.\r
+*/\r
+\r
+enum hetPinSelect\r
+{\r
+ PIN_HET_0 = 0,\r
+ PIN_HET_1 = 1,\r
+ PIN_HET_2 = 2,\r
+ PIN_HET_3 = 3,\r
+ PIN_HET_4 = 4,\r
+ PIN_HET_5 = 5,\r
+ PIN_HET_6 = 6,\r
+ PIN_HET_7 = 7,\r
+ PIN_HET_8 = 8,\r
+ PIN_HET_9 = 9,\r
+ PIN_HET_10 = 10,\r
+ PIN_HET_11 = 11,\r
+ PIN_HET_12 = 12,\r
+ PIN_HET_13 = 13,\r
+ PIN_HET_14 = 14,\r
+ PIN_HET_15 = 15,\r
+ PIN_HET_16 = 16,\r
+ PIN_HET_17 = 17,\r
+ PIN_HET_18 = 18,\r
+ PIN_HET_19 = 19,\r
+ PIN_HET_20 = 20,\r
+ PIN_HET_21 = 21,\r
+ PIN_HET_22 = 22,\r
+ PIN_HET_23 = 23,\r
+ PIN_HET_24 = 24,\r
+ PIN_HET_25 = 25,\r
+ PIN_HET_26 = 26,\r
+ PIN_HET_27 = 27,\r
+ PIN_HET_28 = 28,\r
+ PIN_HET_29 = 29,\r
+ PIN_HET_30 = 30,\r
+ PIN_HET_31 = 31\r
+};\r
+\r
+/** @struct hetBase\r
+* @brief HET Base Register Definition\r
+*\r
+* This structure is used to access the HET module egisters.\r
+*/\r
+/** @typedef hetBASE_t\r
+* @brief HET Register Frame Type Definition\r
+*\r
+* This type is used to access the HET Registers.\r
+*/\r
+\r
+typedef volatile struct hetBase\r
+{\r
+ uint32_t GCR; /**< 0x0000: Global control register */\r
+ uint32_t PFR; /**< 0x0004: Prescale factor register */\r
+ uint32_t ADDR; /**< 0x0008: Current address register */\r
+ uint32_t OFF1; /**< 0x000C: Interrupt offset register 1 */\r
+ uint32_t OFF2; /**< 0x0010: Interrupt offset register 2 */\r
+ uint32_t INTENAS; /**< 0x0014: Interrupt enable set register */\r
+ uint32_t INTENAC; /**< 0x0018: Interrupt enable clear register */\r
+ uint32_t EXC1; /**< 0x001C: Exeption control register 1 */\r
+ uint32_t EXC2; /**< 0x0020: Exeption control register 2 */\r
+ uint32_t PRY; /**< 0x0024: Interrupt priority register */\r
+ uint32_t FLG; /**< 0x0028: Interrupt flag register */\r
+ uint32_t AND; /**< 0x002C: AND share control register */\r
+ uint32_t : 32U; /**< 0x0030: Reserved */\r
+ uint32_t HRSH; /**< 0x0034: High resoltion share register */\r
+ uint32_t XOR; /**< 0x0038: XOR share register */\r
+ uint32_t REQENS; /**< 0x003C: Request enable set register */\r
+ uint32_t REQENC; /**< 0x0040: Request enable clear register */\r
+ uint32_t REQDS; /**< 0x0044: Request destination select register */\r
+ uint32_t : 32U; /**< 0x0048: Reserved */\r
+ uint32_t DIR; /**< 0x004C: Direction register */\r
+ uint32_t DIN; /**< 0x0050: Data input register */\r
+ uint32_t DOUT; /**< 0x0054: Data output register */\r
+ uint32_t DSET; /**< 0x0058: Data output set register */\r
+ uint32_t DCLR; /**< 0x005C: Data output clear register */\r
+ uint32_t PDR; /**< 0x0060: Open drain register */\r
+ uint32_t PULDIS; /**< 0x0064: Pull disable register */\r
+ uint32_t PSL; /**< 0x0068: Pull select register */\r
+ uint32_t : 32U; /**< 0x006C: Reserved */\r
+ uint32_t : 32U; /**< 0x0070: Reserved */\r
+ uint32_t PCREG; /**< 0x0074: Parity control register */\r
+ uint32_t PAR; /**< 0x0078: Parity address register */\r
+ uint32_t PPR; /**< 0x007C: Parity pin select register */\r
+ uint32_t SFPRLD; /**< 0x0080: Suppression filter preload register */\r
+ uint32_t SFENA; /**< 0x0084: Suppression filter enable register */\r
+ uint32_t : 32U; /**< 0x0088: Reserved */\r
+ uint32_t LBPSEL; /**< 0x008C: Loop back pair select register */\r
+ uint32_t LBPDIR; /**< 0x0090: Loop back pair direction register */\r
+ uint32_t PINDIS; /**< 0x0094: Pin disable register */\r
+ uint32_t : 32U; /**< 0x0098: Reserved */\r
+ uint32_t HWAPINSEL;/**< 0x009C: HWAG Pin select register */\r
+ uint32_t HWAGCR0; /**< 0x00A0: HWAG Global control register 0 */\r
+ uint32_t HWAGCR1; /**< 0x00A4: HWAG Global control register 1 */\r
+ uint32_t HWAGCR2; /**< 0x00A8: HWAG Global control register 2 */\r
+ uint32_t HWAENASET;/**< 0x00AC: HWAG Interrupt enable set register */\r
+ uint32_t HWAENACLR;/**< 0x00B0: HWAG Interrupt enable clear register*/\r
+ uint32_t HWALVLSET;/**< 0x00B4: HWAG Interrupt level set register */\r
+ uint32_t HWALVLCLR;/**< 0x00B8: HWAG Interrupt level clear register */\r
+ uint32_t HWAFLG; /**< 0x00BC: HWAG Interrupt flag register */\r
+ uint32_t HWAOFF1; /**< 0x00C0: HWAG Interrupt offset 1 register */\r
+ uint32_t HWAOFF2; /**< 0x00C4: HWAG Interrupt offset 2 register */\r
+ uint32_t HWAACNT; /**< 0x00C8: HWAG Angle value register */\r
+ uint32_t HWAPCNT1; /**< 0x00CC: HWAG Period value register 1 */\r
+ uint32_t HWAPCNT; /**< 0x00D0: HWAG Period value register */\r
+ uint32_t HWASTWD; /**< 0x00D4: HWAG Step width register */\r
+ uint32_t HWATHNB; /**< 0x00D8: HWAG Teeth number register */\r
+ uint32_t HWATHVL; /**< 0x00DC: HWAG Teeth Value register */\r
+ uint32_t HWAFIL; /**< 0x00E0: HWAG Filter register */\r
+ uint32_t : 32U; /**< 0x00E4: Reserved */\r
+ uint32_t HWAFIL2; /**< 0x00E8: HWAG Second filter register */\r
+ uint32_t : 32U; /**< 0x00EC: Reserved */\r
+ uint32_t HWAANGI; /**< 0x00F0: HWAG Angle increment register */\r
+} hetBASE_t;\r
+\r
+\r
+/** @def hetREG1\r
+* @brief HET Register Frame Pointer\r
+*\r
+* This pointer is used by the HET driver to access the het module registers.\r
+*/\r
+#define hetREG1 ((hetBASE_t *)0xFFF7B800U)\r
+\r
+\r
+/** @def hetPORT1\r
+* @brief HET GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of HET1\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define hetPORT1 ((gioPORT_t *)0xFFF7B84CU)\r
+\r
+\r
+/** @def hetREG2\r
+* @brief HET2 Register Frame Pointer\r
+*\r
+* This pointer is used by the HET driver to access the het module registers.\r
+*/\r
+#define hetREG2 ((hetBASE_t *)0xFFF7B900U)\r
+\r
+\r
+/** @def hetPORT2\r
+* @brief HET2 GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of HET2\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define hetPORT2 ((gioPORT_t *)0xFFF7B94CU)\r
+\r
+\r
+\r
+/** @struct hetInstructionBase\r
+* @brief HET Instruction Definition\r
+*\r
+* This structure is used to access the HET RAM.\r
+*/\r
+/** @typedef hetINSTRUCTION_t\r
+* @brief HET Instruction Type Definition\r
+*\r
+* This type is used to access a HET Instruction.\r
+*/\r
+typedef volatile struct hetInstructionBase\r
+{\r
+ uint32_t Program;\r
+ uint32_t Control;\r
+ uint32_t Data;\r
+ uint32_t : 32U;\r
+} hetINSTRUCTION_t;\r
+\r
+\r
+/** @struct hetRamBase\r
+* @brief HET RAM Definition\r
+*\r
+* This structure is used to access the HET RAM.\r
+*/\r
+/** @typedef hetRAMBASE_t\r
+* @brief HET RAM Type Definition\r
+*\r
+* This type is used to access the HET RAM.\r
+*/\r
+typedef volatile struct het1RamBase\r
+{\r
+ hetINSTRUCTION_t Instruction[160U];\r
+} hetRAMBASE_t;\r
+\r
+\r
+#define hetRAM1 ((hetRAMBASE_t *)0xFF460000U)\r
+\r
+#define hetRAM2 ((hetRAMBASE_t *)0xFF440000U)\r
+\r
+#define NHET1RAMPARLOC (*(unsigned int *)0xFF462000U)\r
+#define NHET1RAMLOC (*(unsigned int *)0xFF460000U)\r
+\r
+#define NHET2RAMPARLOC (*(unsigned int *)0xFF442000U)\r
+#define NHET2RAMLOC (*(unsigned int *)0xFF440000U)\r
+\r
+/** @struct hetSignal\r
+* @brief HET Signal Definition\r
+*\r
+* This structure is used to define a pwm signal.\r
+*/\r
+/** @typedef hetSIGNAL_t\r
+* @brief HET Signal Type Definition\r
+*\r
+* This type is used to access HET Signal Information.\r
+*/\r
+typedef struct hetSignal\r
+{\r
+ uint32_t duty; /**< Duty cycle in % of the period */\r
+ double period; /**< Period in us */\r
+} hetSIGNAL_t;\r
+\r
+\r
+/* HET Interface Functions */\r
+void hetInit(void);\r
+\r
+/* PWM Interface Functions */\r
+void pwmStart(hetRAMBASE_t * hetRAM,uint32_t pwm);\r
+void pwmStop(hetRAMBASE_t * hetRAM,uint32_t pwm);\r
+void pwmSetDuty(hetRAMBASE_t * hetRAM,uint32_t pwm, uint32_t duty);\r
+void pwmSetSignal(hetRAMBASE_t * hetRAM,uint32_t pwm, hetSIGNAL_t signal);\r
+hetSIGNAL_t pwmGetSignal(hetRAMBASE_t * hetRAM,uint32_t pwm);\r
+void pwmEnableNotification(hetBASE_t * hetREG,uint32_t pwm, uint32_t notification);\r
+void pwmDisableNotification(hetBASE_t * hetREG,uint32_t pwm, uint32_t notification);\r
+void pwmNotification(hetBASE_t * hetREG,uint32_t pwm, uint32_t notification);\r
+\r
+/* Edge Interface Functions */\r
+void edgeResetCounter(hetRAMBASE_t * hetRAM,uint32_t edge);\r
+uint32_t edgeGetCounter(hetRAMBASE_t * hetRAM,uint32_t edge);\r
+void edgeEnableNotification(hetBASE_t * hetREG,uint32_t edge);\r
+void edgeDisableNotification(hetBASE_t * hetREG,uint32_t edge);\r
+void edgeNotification(hetBASE_t * hetREG,uint32_t edge);\r
+\r
+/* Captured Signal Interface Functions */\r
+hetSIGNAL_t capGetSignal(hetRAMBASE_t * hetRAM,uint32_t cap);\r
+\r
+/* Timestamp Interface Functions */\r
+void hetResetTimestamp(hetRAMBASE_t * hetRAM);\r
+uint32_t hetGetTimestamp(hetRAMBASE_t * hetRAM);\r
+\r
+/** @fn void hetNotification(hetBASE_t *het, uint32_t offset)\r
+* @brief het interrupt callback\r
+* @param[in] het - Het module base address\r
+* - hetREG1: HET1 module base address pointer\r
+* - hetREG2: HET2 module base address pointer\r
+* @param[in] offset - het interrupt offset / Source number\r
+*\r
+* @note This function has to be provide by the user.\r
+*\r
+* This is a interrupt callback that is provided by the application and is call upon\r
+* an het interrupt. The paramer passed to the callback is a copy of the interrupt \r
+* offset register which is used to decode the interrupt source.\r
+*/\r
+void hetNotification(hetBASE_t *het, uint32_t offset);\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+#endif\r
--- /dev/null
+/** @file htu.h\r
+* @brief HTU Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __HTU_H__\r
+#define __HTU_H__\r
+\r
+/* HTU General Definitions */\r
+\r
+/** @struct htuBase\r
+* @brief HTU Base Register Definition\r
+*\r
+* This structure is used to access the HTU module egisters.\r
+*/\r
+/** @typedef stcBASE_t\r
+* @brief HTU Register Frame Type Definition\r
+*\r
+* This type is used to access the HTU Registers.\r
+*/\r
+typedef volatile struct htuBase\r
+{\r
+ uint32_t GC; // 0x00\r
+ uint32_t CPENA; // 0x04\r
+ uint32_t BUSY0; // 0x08\r
+ uint32_t BUSY1; // 0x0C\r
+ uint32_t BUSY2; // 0x10\r
+ uint32_t BUSY3; // 0x14\r
+ uint32_t ACPE; // 0x18\r
+ uint32_t : 32; // 0x1C\r
+ uint32_t RLBECTRL; // 0x20\r
+ uint32_t BFINTS; // 0x24\r
+ uint32_t BFINTC; // 0x28\r
+ uint32_t INTMAP; // 0x2C\r
+ uint32_t : 32; // 0x30\r
+ uint32_t INTOFF0; // 0x34\r
+ uint32_t INTOFF1; // 0x38\r
+ uint32_t BIM; // 0x3C\r
+ uint32_t RLOSTFL; // 0x40\r
+ uint32_t BFINTFL; // 0x44\r
+ uint32_t BERINTFL; // 0x48\r
+ uint32_t MP1S; // 0x4C\r
+ uint32_t MP1E; // 0x50\r
+ uint32_t DCTRL; // 0x54\r
+ uint32_t WPR; // 0x58\r
+ uint32_t WMR; // 0x5C\r
+ uint32_t ID; // 0x60\r
+ uint32_t PCR; // 0x64\r
+ uint32_t PAR; // 0x68\r
+ uint32_t : 32; // 0x6C\r
+ uint32_t MPCS; // 0x70\r
+ uint32_t MP0S; // 0x74\r
+ uint32_t MP0E; // 0x78\r
+} htuBASE_t;\r
+\r
+typedef volatile struct htudcp\r
+{\r
+ uint32_t IFADDRA; // 0x00\r
+ uint32_t IFADDRB; // 0x04\r
+ uint32_t IHADDRCT; // 0x08\r
+ uint32_t ITCOUNT; // 0x0C\r
+} htudcp_t;\r
+\r
+typedef volatile struct htucdcp\r
+{\r
+ uint32_t CFADDRA; // 0x100\r
+ uint32_t CFADDRB; // 0x104\r
+ uint32_t CFCOUNT; // 0x108\r
+} htucdcp_t;\r
+\r
+#define htuREG1 ((htuBASE_t *)0xFFF7A400U)\r
+#define htuREG2 ((htuBASE_t *)0xFFF7A500U)\r
+\r
+#define htuDCP1 ((htudcp_t *)0xFF4E0000U)\r
+#define htuDCP2 ((htudcp_t *)0xFF4C0000U)\r
+\r
+#define htuCDCP1 ((htucdcp_t *)0xFF4E0100U)\r
+#define htuCDCP2 ((htucdcp_t *)0xFF4C0100U)\r
+\r
+#define HTU1PARLOC (*(unsigned int *)0xFF4E0200U)\r
+#define HTU2PARLOC (*(unsigned int *)0xFF4C0200U)\r
+\r
+#define HTU1RAMLOC (*(unsigned int *)0xFF4E0000U)\r
+#define HTU2RAMLOC (*(unsigned int *)0xFF4C0000U)\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * hw_emac1.h\r
+ */\r
+\r
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ * ALL RIGHTS RESERVED\r
+ */\r
+\r
+#ifndef _HW_EMAC_H_\r
+#define _HW_EMAC_H_\r
+\r
+#define EMAC_BASE (0xFCF78000U)\r
+#define EMAC_CTRL_BASE (0xFCF78800U)\r
+#define EMAC_CTRL_RAM_BASE (0xFC520000U)\r
+\r
+#define EMAC_TXREVID (0x0)\r
+#define EMAC_TXCONTROL (0x4)\r
+#define EMAC_TXTEARDOWN (0x8)\r
+#define EMAC_RXREVID (0x10)\r
+#define EMAC_RXCONTROL (0x14)\r
+#define EMAC_RXTEARDOWN (0x18)\r
+#define EMAC_TXINTSTATRAW (0x80)\r
+#define EMAC_TXINTSTATMASKED (0x84)\r
+#define EMAC_TXINTMASKSET (0x88)\r
+#define EMAC_TXINTMASKCLEAR (0x8C)\r
+#define EMAC_MACINVECTOR (0x90)\r
+#define EMAC_MACEOIVECTOR (0x94)\r
+#define EMAC_RXINTSTATRAW (0xA0)\r
+#define EMAC_RXINTSTATMASKED (0xA4)\r
+#define EMAC_RXINTMASKSET (0xA8)\r
+#define EMAC_RXINTMASKCLEAR (0xAC)\r
+#define EMAC_MACINTSTATRAW (0xB0)\r
+#define EMAC_MACINTSTATMASKED (0xB4)\r
+#define EMAC_MACINTMASKSET (0xB8)\r
+#define EMAC_MACINTMASKCLEAR (0xBC)\r
+#define EMAC_RXMBPENABLE (0x100)\r
+#define EMAC_RXUNICASTSET (0x104)\r
+#define EMAC_RXUNICASTCLEAR (0x108)\r
+#define EMAC_RXMAXLEN (0x10C)\r
+#define EMAC_RXBUFFEROFFSET (0x110)\r
+#define EMAC_RXFILTERLOWTHRESH (0x114)\r
+#define EMAC_RXFLOWTHRESH(n) (0x120 + (n * 4))\r
+#define EMAC_RXFREEBUFFER(n) (0x140 + (n * 4))\r
+#define EMAC_MACCONTROL (0x160)\r
+#define EMAC_MACSTATUS (0x164)\r
+#define EMAC_EMCONTROL (0x168)\r
+#define EMAC_FIFOCONTROL (0x16C)\r
+#define EMAC_MACCONFIG (0x170)\r
+#define EMAC_SOFTRESET (0x174)\r
+#define EMAC_MACSRCADDRLO (0x1D0)\r
+#define EMAC_MACSRCADDRHI (0x1D4)\r
+#define EMAC_MACHASH1 (0x1D8)\r
+#define EMAC_MACHASH2 (0x1DC)\r
+#define EMAC_BOFFTEST (0x1E0)\r
+#define EMAC_TPACETEST (0x1E4)\r
+#define EMAC_RXPAUSE (0x1E8)\r
+#define EMAC_TXPAUSE (0x1EC)\r
+#define EMAC_RXGOODFRAMES (0x200)\r
+#define EMAC_RXBCASTFRAMES (0x204)\r
+#define EMAC_RXMCASTFRAMES (0x208)\r
+#define EMAC_RXPAUSEFRAMES (0x20C)\r
+#define EMAC_RXCRCERRORS (0x210)\r
+#define EMAC_RXALIGNCODEERRORS (0x214)\r
+#define EMAC_RXOVERSIZED (0x218)\r
+#define EMAC_RXJABBER (0x21C)\r
+#define EMAC_RXUNDERSIZED (0x220)\r
+#define EMAC_RXFRAGMENTS (0x224)\r
+#define EMAC_RXFILTERED (0x228)\r
+#define EMAC_RXQOSFILTERED (0x22C)\r
+#define EMAC_RXOCTETS (0x230)\r
+#define EMAC_TXGOODFRAMES (0x234)\r
+#define EMAC_TXBCASTFRAMES (0x238)\r
+#define EMAC_TXMCASTFRAMES (0x23C)\r
+#define EMAC_TXPAUSEFRAMES (0x240)\r
+#define EMAC_TXDEFERRED (0x244)\r
+#define EMAC_TXCOLLISION (0x248)\r
+#define EMAC_TXSINGLECOLL (0x24C)\r
+#define EMAC_TXMULTICOLL (0x250)\r
+#define EMAC_TXEXCESSIVECOLL (0x254)\r
+#define EMAC_TXLATECOLL (0x258)\r
+#define EMAC_TXUNDERRUN (0x25C)\r
+#define EMAC_TXCARRIERSENSE (0x260)\r
+#define EMAC_TXOCTETS (0x264)\r
+#define EMAC_FRAME64 (0x268)\r
+#define EMAC_FRAME65T127 (0x26C)\r
+#define EMAC_FRAME128T255 (0x270)\r
+#define EMAC_FRAME256T511 (0x274)\r
+#define EMAC_FRAME512T1023 (0x278)\r
+#define EMAC_FRAME1024TUP (0x27C)\r
+#define EMAC_NETOCTETS (0x208)\r
+#define EMAC_RXSOFOVERRUNS (0x284)\r
+#define EMAC_RXMOFOVERRUNS (0x288)\r
+#define EMAC_RXDMAOVERRUNS (0x28C)\r
+#define EMAC_MACADDRLO (0x500)\r
+#define EMAC_MACADDRHI (0x504)\r
+#define EMAC_MACINDEX (0x508)\r
+#define EMAC_TXHDP(n) (0x600 + (n * 4))\r
+#define EMAC_RXHDP(n) (0x620 + (n * 4))\r
+#define EMAC_TXCP(n) (0x640 + (n * 4))\r
+#define EMAC_RXCP(n) (0x660 + (n * 4))\r
+\r
+/**************************************************************************\\r
+* Field Definition Macros\r
+\**************************************************************************/\r
+\r
+/* TXREVID */\r
+\r
+#define EMAC_TXREVID_TXREV (0xFFFFFFFFu)\r
+#define EMAC_TXREVID_TXREV_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXCONTROL */\r
+\r
+\r
+#define EMAC_TXCONTROL_TXEN (0x00000001u)\r
+#define EMAC_TXCONTROL_TXEN_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXTEARDOWN */\r
+\r
+#define EMAC_TXTEARDOWN_TXTDNCH (0x00000007u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT (0x00000000u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 (0x00000000u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 (0x00000001u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 (0x00000002u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 (0x00000003u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 (0x00000004u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 (0x00000005u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 (0x00000006u)\r
+#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 (0x00000007u)\r
+\r
+\r
+/* RXREVID */\r
+\r
+#define EMAC_RXREVID_RXREV (0xFFFFFFFFu)\r
+#define EMAC_RXREVID_RXREV_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXCONTROL */\r
+\r
+\r
+#define EMAC_RXCONTROL_RXEN (0x00000001u)\r
+#define EMAC_RXCONTROL_RXEN_SHIFT (0x00000000u)\r
+\r
+/* RXTEARDOWN */\r
+\r
+\r
+\r
+#define EMAC_RXTEARDOWN_RXTDNCH (0x00000007u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT (0x00000000u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 (0x00000000u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 (0x00000001u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 (0x00000002u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 (0x00000003u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 (0x00000004u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 (0x00000005u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 (0x00000006u)\r
+#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 (0x00000007u)\r
+\r
+\r
+/* TXINTSTATRAW */\r
+\r
+\r
+#define EMAC_TXINTSTATRAW_TX7PEND (0x00000080u)\r
+#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT (0x00000007u)\r
+\r
+#define EMAC_TXINTSTATRAW_TX6PEND (0x00000040u)\r
+#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT (0x00000006u)\r
+\r
+#define EMAC_TXINTSTATRAW_TX5PEND (0x00000020u)\r
+#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT (0x00000005u)\r
+\r
+#define EMAC_TXINTSTATRAW_TX4PEND (0x00000010u)\r
+#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT (0x00000004u)\r
+\r
+#define EMAC_TXINTSTATRAW_TX3PEND (0x00000008u)\r
+#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT (0x00000003u)\r
+\r
+#define EMAC_TXINTSTATRAW_TX2PEND (0x00000004u)\r
+#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT (0x00000002u)\r
+\r
+#define EMAC_TXINTSTATRAW_TX1PEND (0x00000002u)\r
+#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT (0x00000001u)\r
+\r
+#define EMAC_TXINTSTATRAW_TX0PEND (0x00000001u)\r
+#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXINTSTATMASKED */\r
+\r
+\r
+#define EMAC_TXINTSTATMASKED_TX7PEND (0x00000080u)\r
+#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT (0x00000007u)\r
+\r
+#define EMAC_TXINTSTATMASKED_TX6PEND (0x00000040u)\r
+#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT (0x00000006u)\r
+\r
+#define EMAC_TXINTSTATMASKED_TX5PEND (0x00000020u)\r
+#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT (0x00000005u)\r
+\r
+#define EMAC_TXINTSTATMASKED_TX4PEND (0x00000010u)\r
+#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT (0x00000004u)\r
+\r
+#define EMAC_TXINTSTATMASKED_TX3PEND (0x00000008u)\r
+#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT (0x00000003u)\r
+\r
+#define EMAC_TXINTSTATMASKED_TX2PEND (0x00000004u)\r
+#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT (0x00000002u)\r
+\r
+#define EMAC_TXINTSTATMASKED_TX1PEND (0x00000002u)\r
+#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT (0x00000001u)\r
+\r
+#define EMAC_TXINTSTATMASKED_TX0PEND (0x00000001u)\r
+#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXINTMASKSET */\r
+\r
+\r
+#define EMAC_TXINTMASKSET_TX7MASK (0x00000080u)\r
+#define EMAC_TXINTMASKSET_TX7MASK_SHIFT (0x00000007u)\r
+\r
+#define EMAC_TXINTMASKSET_TX6MASK (0x00000040u)\r
+#define EMAC_TXINTMASKSET_TX6MASK_SHIFT (0x00000006u)\r
+\r
+#define EMAC_TXINTMASKSET_TX5MASK (0x00000020u)\r
+#define EMAC_TXINTMASKSET_TX5MASK_SHIFT (0x00000005u)\r
+\r
+#define EMAC_TXINTMASKSET_TX4MASK (0x00000010u)\r
+#define EMAC_TXINTMASKSET_TX4MASK_SHIFT (0x00000004u)\r
+\r
+#define EMAC_TXINTMASKSET_TX3MASK (0x00000008u)\r
+#define EMAC_TXINTMASKSET_TX3MASK_SHIFT (0x00000003u)\r
+\r
+#define EMAC_TXINTMASKSET_TX2MASK (0x00000004u)\r
+#define EMAC_TXINTMASKSET_TX2MASK_SHIFT (0x00000002u)\r
+\r
+#define EMAC_TXINTMASKSET_TX1MASK (0x00000002u)\r
+#define EMAC_TXINTMASKSET_TX1MASK_SHIFT (0x00000001u)\r
+\r
+#define EMAC_TXINTMASKSET_TX0MASK (0x00000001u)\r
+#define EMAC_TXINTMASKSET_TX0MASK_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXINTMASKCLEAR */\r
+\r
+\r
+#define EMAC_TXINTMASKCLEAR_TX7MASK (0x00000080u)\r
+#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT (0x00000007u)\r
+\r
+#define EMAC_TXINTMASKCLEAR_TX6MASK (0x00000040u)\r
+#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT (0x00000006u)\r
+\r
+#define EMAC_TXINTMASKCLEAR_TX5MASK (0x00000020u)\r
+#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT (0x00000005u)\r
+\r
+#define EMAC_TXINTMASKCLEAR_TX4MASK (0x00000010u)\r
+#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT (0x00000004u)\r
+\r
+#define EMAC_TXINTMASKCLEAR_TX3MASK (0x00000008u)\r
+#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT (0x00000003u)\r
+\r
+#define EMAC_TXINTMASKCLEAR_TX2MASK (0x00000004u)\r
+#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT (0x00000002u)\r
+\r
+#define EMAC_TXINTMASKCLEAR_TX1MASK (0x00000002u)\r
+#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT (0x00000001u)\r
+\r
+#define EMAC_TXINTMASKCLEAR_TX0MASK (0x00000001u)\r
+#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACINVECTOR */\r
+\r
+\r
+#define EMAC_MACINVECTOR_STATPEND (0x08000000u)\r
+#define EMAC_MACINVECTOR_STATPEND_SHIFT (0x0000001Bu)\r
+\r
+#define EMAC_MACINVECTOR_HOSTPEND (0x04000000u)\r
+#define EMAC_MACINVECTOR_HOSTPEND_SHIFT (0x0000001Au)\r
+\r
+#define EMAC_MACINVECTOR_LINKINT0 (0x02000000u)\r
+#define EMAC_MACINVECTOR_LINKINT0_SHIFT (0x00000019u)\r
+\r
+#define EMAC_MACINVECTOR_USERINT0 (0x01000000u)\r
+#define EMAC_MACINVECTOR_USERINT0_SHIFT (0x00000018u)\r
+\r
+#define EMAC_MACINVECTOR_TXPEND (0x00FF0000u)\r
+#define EMAC_MACINVECTOR_TXPEND_SHIFT (0x00000010u)\r
+\r
+#define EMAC_MACINVECTOR_RXTHRESHPEND (0x0000FF00u)\r
+#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT (0x00000008u)\r
+\r
+#define EMAC_MACINVECTOR_RXPEND (0x000000FFu)\r
+#define EMAC_MACINVECTOR_RXPEND_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACEOIVECTOR */\r
+\r
+\r
+#define EMAC_MACEOIVECTOR_INTVECT (0x0000001Fu)\r
+#define EMAC_MACEOIVECTOR_INTVECT_SHIFT (0x00000000u)\r
+/*----INTVECT Tokens----*/\r
+#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH (0x00000000u)\r
+#define EMAC_MACEOIVECTOR_INTVECT_C0RX (0x00000001u)\r
+#define EMAC_MACEOIVECTOR_INTVECT_C0TX (0x00000002u)\r
+#define EMAC_MACEOIVECTOR_INTVECT_C0MISC (0x00000003u)\r
+#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH (0x00000004u)\r
+#define EMAC_MACEOIVECTOR_INTVECT_C1RX (0x00000005u)\r
+#define EMAC_MACEOIVECTOR_INTVECT_C1TX (0x00000006u)\r
+#define EMAC_MACEOIVECTOR_INTVECT_C1MISC (0x00000007u)\r
+\r
+\r
+/* RXINTSTATRAW */\r
+\r
+\r
+#define EMAC_RXINTSTATRAW_RX7THRESHPEND (0x00008000u)\r
+#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT (0x0000000Fu)\r
+\r
+#define EMAC_RXINTSTATRAW_RX6THRESHPEND (0x00004000u)\r
+#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT (0x0000000Eu)\r
+\r
+#define EMAC_RXINTSTATRAW_RX5THRESHPEND (0x00002000u)\r
+#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT (0x0000000Du)\r
+\r
+#define EMAC_RXINTSTATRAW_RX4THRESHPEND (0x00001000u)\r
+#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT (0x0000000Cu)\r
+\r
+#define EMAC_RXINTSTATRAW_RX3THRESHPEND (0x00000800u)\r
+#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT (0x0000000Bu)\r
+\r
+#define EMAC_RXINTSTATRAW_RX2THRESHPEND (0x00000400u)\r
+#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT (0x0000000Au)\r
+\r
+#define EMAC_RXINTSTATRAW_RX1THRESHPEND (0x00000200u)\r
+#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT (0x00000009u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX0THRESHPEND (0x00000100u)\r
+#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT (0x00000008u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX7PEND (0x00000080u)\r
+#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT (0x00000007u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX6PEND (0x00000040u)\r
+#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT (0x00000006u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX5PEND (0x00000020u)\r
+#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT (0x00000005u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX4PEND (0x00000010u)\r
+#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT (0x00000004u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX3PEND (0x00000008u)\r
+#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT (0x00000003u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX2PEND (0x00000004u)\r
+#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT (0x00000002u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX1PEND (0x00000002u)\r
+#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT (0x00000001u)\r
+\r
+#define EMAC_RXINTSTATRAW_RX0PEND (0x00000001u)\r
+#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXINTSTATMASKED */\r
+\r
+\r
+#define EMAC_RXINTSTATMASKED_RX7THRESHPEND (0x00008000u)\r
+#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT (0x0000000Fu)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX6THRESHPEND (0x00004000u)\r
+#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT (0x0000000Eu)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX5THRESHPEND (0x00002000u)\r
+#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT (0x0000000Du)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX4THRESHPEND (0x00001000u)\r
+#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT (0x0000000Cu)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX3THRESHPEND (0x00000800u)\r
+#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT (0x0000000Bu)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX2THRESHPEND (0x00000400u)\r
+#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT (0x0000000Au)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX1THRESHPEND (0x00000200u)\r
+#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT (0x00000009u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX0THRESHPEND (0x00000100u)\r
+#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT (0x00000008u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX7PEND (0x00000080u)\r
+#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT (0x00000007u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX6PEND (0x00000040u)\r
+#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT (0x00000006u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX5PEND (0x00000020u)\r
+#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT (0x00000005u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX4PEND (0x00000010u)\r
+#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT (0x00000004u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX3PEND (0x00000008u)\r
+#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT (0x00000003u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX2PEND (0x00000004u)\r
+#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT (0x00000002u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX1PEND (0x00000002u)\r
+#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT (0x00000001u)\r
+\r
+#define EMAC_RXINTSTATMASKED_RX0PEND (0x00000001u)\r
+#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXINTMASKSET */\r
+\r
+\r
+#define EMAC_RXINTMASKSET_RX7THRESHMASK (0x00008000u)\r
+#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT (0x0000000Fu)\r
+\r
+#define EMAC_RXINTMASKSET_RX6THRESHMASK (0x00004000u)\r
+#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT (0x0000000Eu)\r
+\r
+#define EMAC_RXINTMASKSET_RX5THRESHMASK (0x00002000u)\r
+#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT (0x0000000Du)\r
+\r
+#define EMAC_RXINTMASKSET_RX4THRESHMASK (0x00001000u)\r
+#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT (0x0000000Cu)\r
+\r
+#define EMAC_RXINTMASKSET_RX3THRESHMASK (0x00000800u)\r
+#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT (0x0000000Bu)\r
+\r
+#define EMAC_RXINTMASKSET_RX2THRESHMASK (0x00000400u)\r
+#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT (0x0000000Au)\r
+\r
+#define EMAC_RXINTMASKSET_RX1THRESHMASK (0x00000200u)\r
+#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT (0x00000009u)\r
+\r
+#define EMAC_RXINTMASKSET_RX0THRESHMASK (0x00000100u)\r
+#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT (0x00000008u)\r
+\r
+#define EMAC_RXINTMASKSET_RX7MASK (0x00000080u)\r
+#define EMAC_RXINTMASKSET_RX7MASK_SHIFT (0x00000007u)\r
+\r
+#define EMAC_RXINTMASKSET_RX6MASK (0x00000040u)\r
+#define EMAC_RXINTMASKSET_RX6MASK_SHIFT (0x00000006u)\r
+\r
+#define EMAC_RXINTMASKSET_RX5MASK (0x00000020u)\r
+#define EMAC_RXINTMASKSET_RX5MASK_SHIFT (0x00000005u)\r
+\r
+#define EMAC_RXINTMASKSET_RX4MASK (0x00000010u)\r
+#define EMAC_RXINTMASKSET_RX4MASK_SHIFT (0x00000004u)\r
+\r
+#define EMAC_RXINTMASKSET_RX3MASK (0x00000008u)\r
+#define EMAC_RXINTMASKSET_RX3MASK_SHIFT (0x00000003u)\r
+\r
+#define EMAC_RXINTMASKSET_RX2MASK (0x00000004u)\r
+#define EMAC_RXINTMASKSET_RX2MASK_SHIFT (0x00000002u)\r
+\r
+#define EMAC_RXINTMASKSET_RX1MASK (0x00000002u)\r
+#define EMAC_RXINTMASKSET_RX1MASK_SHIFT (0x00000001u)\r
+\r
+#define EMAC_RXINTMASKSET_RX0MASK (0x00000001u)\r
+#define EMAC_RXINTMASKSET_RX0MASK_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXINTMASKCLEAR */\r
+\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK (0x00008000u)\r
+#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT (0x0000000Fu)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK (0x00004000u)\r
+#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT (0x0000000Eu)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK (0x00002000u)\r
+#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT (0x0000000Du)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK (0x00001000u)\r
+#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT (0x0000000Cu)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK (0x00000800u)\r
+#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT (0x0000000Bu)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK (0x00000400u)\r
+#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT (0x0000000Au)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK (0x00000200u)\r
+#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT (0x00000009u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK (0x00000100u)\r
+#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT (0x00000008u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX7MASK (0x00000080u)\r
+#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT (0x00000007u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX6MASK (0x00000040u)\r
+#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT (0x00000006u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX5MASK (0x00000020u)\r
+#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT (0x00000005u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX4MASK (0x00000010u)\r
+#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT (0x00000004u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX3MASK (0x00000008u)\r
+#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT (0x00000003u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX2MASK (0x00000004u)\r
+#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT (0x00000002u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX1MASK (0x00000002u)\r
+#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT (0x00000001u)\r
+\r
+#define EMAC_RXINTMASKCLEAR_RX0MASK (0x00000001u)\r
+#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACINTSTATRAW */\r
+\r
+\r
+#define EMAC_MACINTSTATRAW_HOSTPEND (0x00000002u)\r
+#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT (0x00000001u)\r
+\r
+#define EMAC_MACINTSTATRAW_STATPEND (0x00000001u)\r
+#define EMAC_MACINTSTATRAW_STATPEND_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACINTSTATMASKED */\r
+\r
+\r
+#define EMAC_MACINTSTATMASKED_HOSTPEND (0x00000002u)\r
+#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT (0x00000001u)\r
+\r
+#define EMAC_MACINTSTATMASKED_STATPEND (0x00000001u)\r
+#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACINTMASKSET */\r
+\r
+\r
+#define EMAC_MACINTMASKSET_HOSTMASK (0x00000002u)\r
+#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT (0x00000001u)\r
+\r
+#define EMAC_MACINTMASKSET_STATMASK (0x00000001u)\r
+#define EMAC_MACINTMASKSET_STATMASK_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACINTMASKCLEAR */\r
+\r
+\r
+#define EMAC_MACINTMASKCLEAR_HOSTMASK (0x00000002u)\r
+#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT (0x00000001u)\r
+\r
+#define EMAC_MACINTMASKCLEAR_STATMASK (0x00000001u)\r
+#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXMBPENABLE */\r
+\r
+\r
+#define EMAC_RXMBPENABLE_RXPASSCRC (0x40000000u)\r
+#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT (0x0000001Eu)\r
+#define EMAC_RXMBPENABLE_RXQOSEN (0x20000000u)\r
+#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT (0x0000001Du)\r
+#define EMAC_RXMBPENABLE_RXNOCHAIN (0x10000000u)\r
+#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT (0x0000001Cu)\r
+#define EMAC_RXMBPENABLE_RXCMFEN (0x01000000u)\r
+#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT (0x00000018u)\r
+#define EMAC_RXMBPENABLE_RXCSFEN (0x00800000u)\r
+#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT (0x00000017u)\r
+#define EMAC_RXMBPENABLE_RXCEFEN (0x00400000u)\r
+#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT (0x00000016u)\r
+#define EMAC_RXMBPENABLE_RXCAFEN (0x00200000u)\r
+#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT (0x00000015u)\r
+/*----RXCAFEN Tokens----*/\r
+#define EMAC_RXMBPENABLE_RXPROMCH (0x00070000u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT (0x00000010u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 (0x00000000u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 (0x00000001u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 (0x00000002u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 (0x00000003u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 (0x00000004u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 (0x00000005u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 (0x00000006u)\r
+#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 (0x00000007u)\r
+\r
+\r
+#define EMAC_RXMBPENABLE_RXBROADEN (0x00002000u)\r
+#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT (0x0000000Du)\r
+#define EMAC_RXMBPENABLE_RXBROADCH (0x00000700u)\r
+#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT (0x00000008u)\r
+/*----RXBROADCH Tokens----*/\r
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 (0x00000000u)\r
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 (0x00000001u)\r
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 (0x00000002u)\r
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 (0x00000003u)\r
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 (0x00000004u)\r
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 (0x00000005u)\r
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 (0x00000006u)\r
+#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 (0x00000007u)\r
+\r
+\r
+#define EMAC_RXMBPENABLE_RXMULTEN (0x00000020u)\r
+#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT (0x00000005u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH (0x00000007u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT (0x00000000u)\r
+/*----RXMULTCH Tokens----*/\r
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 (0x00000000u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 (0x00000001u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 (0x00000002u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 (0x00000003u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 (0x00000004u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 (0x00000005u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 (0x00000006u)\r
+#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 (0x00000007u)\r
+\r
+\r
+/* RXUNICASTSET */\r
+\r
+\r
+#define EMAC_RXUNICASTSET_RXCH7EN (0x00000080u)\r
+#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT (0x00000007u)\r
+#define EMAC_RXUNICASTSET_RXCH6EN (0x00000040u)\r
+#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT (0x00000006u)\r
+#define EMAC_RXUNICASTSET_RXCH5EN (0x00000020u)\r
+#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT (0x00000005u)\r
+#define EMAC_RXUNICASTSET_RXCH4EN (0x00000010u)\r
+#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT (0x00000004u)\r
+#define EMAC_RXUNICASTSET_RXCH3EN (0x00000008u)\r
+#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT (0x00000003u)\r
+#define EMAC_RXUNICASTSET_RXCH2EN (0x00000004u)\r
+#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT (0x00000002u)\r
+#define EMAC_RXUNICASTSET_RXCH1EN (0x00000002u)\r
+#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT (0x00000001u)\r
+#define EMAC_RXUNICASTSET_RXCH0EN (0x00000001u)\r
+#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT (0x00000000u)\r
+\r
+/* RXUNICASTCLEAR */\r
+\r
+\r
+#define EMAC_RXUNICASTCLEAR_RXCH7EN (0x00000080u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT (0x00000007u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH6EN (0x00000040u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT (0x00000006u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH5EN (0x00000020u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT (0x00000005u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH4EN (0x00000010u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT (0x00000004u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH3EN (0x00000008u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT (0x00000003u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH2EN (0x00000004u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT (0x00000002u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH1EN (0x00000002u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT (0x00000001u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH0EN (0x00000001u)\r
+#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT (0x00000000u)\r
+\r
+/* RXMAXLEN */\r
+\r
+\r
+#define EMAC_RXMAXLEN_RXMAXLEN (0x0000FFFFu)\r
+#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXBUFFEROFFSET */\r
+\r
+\r
+#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET (0x0000FFFFu)\r
+#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXFILTERLOWTHRESH */\r
+\r
+\r
+#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH (0x000000FFu)\r
+#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX0FLOWTHRESH */\r
+\r
+\r
+#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH (0x000000FFu)\r
+#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX1FLOWTHRESH */\r
+\r
+\r
+#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH (0x000000FFu)\r
+#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX2FLOWTHRESH */\r
+\r
+\r
+#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH (0x000000FFu)\r
+#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX3FLOWTHRESH */\r
+\r
+\r
+#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH (0x000000FFu)\r
+#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX4FLOWTHRESH */\r
+\r
+\r
+#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH (0x000000FFu)\r
+#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX5FLOWTHRESH */\r
+\r
+\r
+#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH (0x000000FFu)\r
+#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX6FLOWTHRESH */\r
+\r
+\r
+#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH (0x000000FFu)\r
+#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX7FLOWTHRESH */\r
+\r
+\r
+#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH (0x000000FFu)\r
+#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX0FREEBUFFER */\r
+\r
+\r
+#define EMAC_RX0FREEBUFFER_RX0FREEBUF (0x0000FFFFu)\r
+#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX1FREEBUFFER */\r
+\r
+\r
+#define EMAC_RX1FREEBUFFER_RX1FREEBUF (0x0000FFFFu)\r
+#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX2FREEBUFFER */\r
+\r
+\r
+#define EMAC_RX2FREEBUFFER_RX2FREEBUF (0x0000FFFFu)\r
+#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX3FREEBUFFER */\r
+\r
+\r
+#define EMAC_RX3FREEBUFFER_RX3FREEBUF (0x0000FFFFu)\r
+#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX4FREEBUFFER */\r
+\r
+\r
+#define EMAC_RX4FREEBUFFER_RX4FREEBUF (0x0000FFFFu)\r
+#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX5FREEBUFFER */\r
+\r
+\r
+#define EMAC_RX5FREEBUFFER_RX5FREEBUF (0x0000FFFFu)\r
+#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX6FREEBUFFER */\r
+\r
+\r
+#define EMAC_RX6FREEBUFFER_RX6FREEBUF (0x0000FFFFu)\r
+#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX7FREEBUFFER */\r
+\r
+\r
+#define EMAC_RX7FREEBUFFER_RX7FREEBUF (0x0000FFFFu)\r
+#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACCONTROL */\r
+\r
+\r
+\r
+\r
+\r
+#define EMAC_MACCONTROL_RMIISPEED (0x00008000u)\r
+#define EMAC_MACCONTROL_RMIISPEED_SHIFT (0x0000000Fu)\r
+#define EMAC_MACCONTROL_RXOFFLENBLOCK (0x00004000u)\r
+#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT (0x0000000Eu)\r
+#define EMAC_MACCONTROL_RXOWNERSHIP (0x00002000u)\r
+#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT (0x0000000Du)\r
+#define EMAC_MACCONTROL_CMDIDLE (0x00000800u)\r
+#define EMAC_MACCONTROL_CMDIDLE_SHIFT (0x0000000Bu)\r
+#define EMAC_MACCONTROL_TXSHORTGAPEN (0x00000400u)\r
+#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT (0x0000000Au)\r
+#define EMAC_MACCONTROL_TXPTYPE (0x00000200u)\r
+#define EMAC_MACCONTROL_TXPTYPE_SHIFT (0x00000009u)\r
+#define EMAC_MACCONTROL_TXPACE (0x00000040u)\r
+#define EMAC_MACCONTROL_TXPACE_SHIFT (0x00000006u)\r
+#define EMAC_MACCONTROL_GMIIEN (0x00000020u)\r
+#define EMAC_MACCONTROL_GMIIEN_SHIFT (0x00000005u)\r
+#define EMAC_MACCONTROL_TXFLOWEN (0x00000010u)\r
+#define EMAC_MACCONTROL_TXFLOWEN_SHIFT (0x00000004u)\r
+#define EMAC_MACCONTROL_RXBUFFERFLOWEN (0x00000008u)\r
+#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT (0x00000003u)\r
+#define EMAC_MACCONTROL_LOOPBACK (0x00000002u)\r
+#define EMAC_MACCONTROL_LOOPBACK_SHIFT (0x00000001u)\r
+#define EMAC_MACCONTROL_FULLDUPLEX (0x00000001u)\r
+#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACSTATUS */\r
+\r
+#define EMAC_MACSTATUS_IDLE (0x80000000u)\r
+#define EMAC_MACSTATUS_IDLE_SHIFT (0x0000001Fu)\r
+#define EMAC_MACSTATUS_TXERRCODE (0x00F00000u)\r
+#define EMAC_MACSTATUS_TXERRCODE_SHIFT (0x00000014u)\r
+/*----TXERRCODE Tokens----*/\r
+#define EMAC_MACSTATUS_TXERRCODE_NOERROR (0x00000000u)\r
+#define EMAC_MACSTATUS_TXERRCODE_SOPERROR (0x00000001u)\r
+#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP (0x00000002u)\r
+#define EMAC_MACSTATUS_TXERRCODE_NOEOP (0x00000003u)\r
+#define EMAC_MACSTATUS_TXERRCODE_NULLPTR (0x00000004u)\r
+#define EMAC_MACSTATUS_TXERRCODE_NULLEN (0x00000005u)\r
+#define EMAC_MACSTATUS_TXERRCODE_LENERROR (0x00000006u)\r
+\r
+\r
+#define EMAC_MACSTATUS_TXERRCH (0x00070000u)\r
+#define EMAC_MACSTATUS_TXERRCH_SHIFT (0x00000010u)\r
+/*----TXERRCH Tokens----*/\r
+#define EMAC_MACSTATUS_TXERRCH_CHA0 (0x00000000u)\r
+#define EMAC_MACSTATUS_TXERRCH_CHA1 (0x00000001u)\r
+#define EMAC_MACSTATUS_TXERRCH_CHA2 (0x00000002u)\r
+#define EMAC_MACSTATUS_TXERRCH_CHA3 (0x00000003u)\r
+#define EMAC_MACSTATUS_TXERRCH_CHA4 (0x00000004u)\r
+#define EMAC_MACSTATUS_TXERRCH_CHA5 (0x00000005u)\r
+#define EMAC_MACSTATUS_TXERRCH_CHA6 (0x00000006u)\r
+#define EMAC_MACSTATUS_TXERRCH_CHA7 (0x00000007u)\r
+\r
+#define EMAC_MACSTATUS_RXERRCODE (0x0000F000u)\r
+#define EMAC_MACSTATUS_RXERRCODE_SHIFT (0x0000000Cu)\r
+/*----RXERRCODE Tokens----*/\r
+#define EMAC_MACSTATUS_RXERRCODE_NOERROR (0x00000000u)\r
+#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP (0x00000002u)\r
+#define EMAC_MACSTATUS_RXERRCODE_NULLPTR (0x00000004u)\r
+\r
+\r
+#define EMAC_MACSTATUS_RXERRCH (0x00000700u)\r
+#define EMAC_MACSTATUS_RXERRCH_SHIFT (0x00000008u)\r
+/*----RXERRCH Tokens----*/\r
+#define EMAC_MACSTATUS_RXERRCH_CHA0 (0x00000000u)\r
+#define EMAC_MACSTATUS_RXERRCH_CHA1 (0x00000001u)\r
+#define EMAC_MACSTATUS_RXERRCH_CHA2 (0x00000002u)\r
+#define EMAC_MACSTATUS_RXERRCH_CHA3 (0x00000003u)\r
+#define EMAC_MACSTATUS_RXERRCH_CHA4 (0x00000004u)\r
+#define EMAC_MACSTATUS_RXERRCH_CHA5 (0x00000005u)\r
+#define EMAC_MACSTATUS_RXERRCH_CHA6 (0x00000006u)\r
+#define EMAC_MACSTATUS_RXERRCH_CHA7 (0x00000007u)\r
+\r
+\r
+\r
+\r
+#define EMAC_MACSTATUS_RXQOSACT (0x00000004u)\r
+#define EMAC_MACSTATUS_RXQOSACT_SHIFT (0x00000002u)\r
+#define EMAC_MACSTATUS_RXFLOWACT (0x00000002u)\r
+#define EMAC_MACSTATUS_RXFLOWACT_SHIFT (0x00000001u)\r
+#define EMAC_MACSTATUS_TXFLOWACT (0x00000001u)\r
+#define EMAC_MACSTATUS_TXFLOWACT_SHIFT (0x00000000u)\r
+\r
+/* EMCONTROL */\r
+\r
+\r
+#define EMAC_EMCONTROL_SOFT (0x00000002u)\r
+#define EMAC_EMCONTROL_SOFT_SHIFT (0x00000001u)\r
+\r
+#define EMAC_EMCONTROL_FREE (0x00000001u)\r
+#define EMAC_EMCONTROL_FREE_SHIFT (0x00000000u)\r
+\r
+\r
+/* FIFOCONTROL */\r
+\r
+\r
+#define EMAC_FIFOCONTROL_TXCELLTHRESH (0x00000003u)\r
+#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACCONFIG */\r
+\r
+#define EMAC_MACCONFIG_TXCELLDEPTH (0xFF000000u)\r
+#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT (0x00000018u)\r
+\r
+#define EMAC_MACCONFIG_RXCELLDEPTH (0x00FF0000u)\r
+#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT (0x00000010u)\r
+\r
+#define EMAC_MACCONFIG_ADDRESSTYPE (0x0000FF00u)\r
+#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT (0x00000008u)\r
+\r
+#define EMAC_MACCONFIG_MACCFIG (0x000000FFu)\r
+#define EMAC_MACCONFIG_MACCFIG_SHIFT (0x00000000u)\r
+\r
+\r
+/* SOFTRESET */\r
+\r
+\r
+#define EMAC_SOFTRESET_SOFTRESET (0x00000001u)\r
+#define EMAC_SOFTRESET_SOFTRESET_SHIFT (0x00000000u)\r
+\r
+/* MACSRCADDRLO */\r
+\r
+\r
+#define EMAC_MACSRCADDRLO_MACSRCADDR0 (0x0000FF00u)\r
+#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT (0x00000008u)\r
+#define EMAC_MACSRCADDRLO_MACSRCADDR1 (0x000000FFu)\r
+#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACSRCADDRHI */\r
+\r
+#define EMAC_MACSRCADDRHI_MACSRCADDR2 (0xFF000000u)\r
+#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT (0x00000018u)\r
+\r
+#define EMAC_MACSRCADDRHI_MACSRCADDR3 (0x00FF0000u)\r
+#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT (0x00000010u)\r
+\r
+#define EMAC_MACSRCADDRHI_MACSRCADDR4 (0x0000FF00u)\r
+#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT (0x00000008u)\r
+\r
+#define EMAC_MACSRCADDRHI_MACSRCADDR5 (0x000000FFu)\r
+#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACHASH1 */\r
+\r
+#define EMAC_MACHASH1_MACHASH1 (0xFFFFFFFFu)\r
+#define EMAC_MACHASH1_MACHASH1_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACHASH2 */\r
+\r
+#define EMAC_MACHASH2_MACHASH2 (0xFFFFFFFFu)\r
+#define EMAC_MACHASH2_MACHASH2_SHIFT (0x00000000u)\r
+\r
+\r
+/* BOFFTEST */\r
+\r
+\r
+#define EMAC_BOFFTEST_RNDNUM (0x03FF0000u)\r
+#define EMAC_BOFFTEST_RNDNUM_SHIFT (0x00000010u)\r
+\r
+#define EMAC_BOFFTEST_COLLCOUNT (0x0000F000u)\r
+#define EMAC_BOFFTEST_COLLCOUNT_SHIFT (0x0000000Cu)\r
+\r
+\r
+#define EMAC_BOFFTEST_TXBACKOFF (0x000003FFu)\r
+#define EMAC_BOFFTEST_TXBACKOFF_SHIFT (0x00000000u)\r
+\r
+\r
+/* TPACETEST */\r
+\r
+\r
+#define EMAC_TPACETEST_PACEVAL (0x0000001Fu)\r
+#define EMAC_TPACETEST_PACEVAL_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXPAUSE */\r
+\r
+\r
+#define EMAC_RXPAUSE_PAUSETIMER (0x0000FFFFu)\r
+#define EMAC_RXPAUSE_PAUSETIMER_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXPAUSE */\r
+\r
+\r
+#define EMAC_TXPAUSE_PAUSETIMER (0x0000FFFFu)\r
+#define EMAC_TXPAUSE_PAUSETIMER_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXGOODFRAMES */\r
+\r
+#define EMAC_RXGOODFRAMES_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXGOODFRAMES_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXBCASTFRAMES */\r
+\r
+#define EMAC_RXBCASTFRAMES_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXBCASTFRAMES_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXMCASTFRAMES */\r
+\r
+#define EMAC_RXMCASTFRAMES_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXMCASTFRAMES_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXPAUSEFRAMES */\r
+\r
+#define EMAC_RXPAUSEFRAMES_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXCRCERRORS */\r
+\r
+#define EMAC_RXCRCERRORS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXCRCERRORS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXALIGNCODEERRORS */\r
+\r
+#define EMAC_RXALIGNCODEERRORS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXOVERSIZED */\r
+\r
+#define EMAC_RXOVERSIZED_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXOVERSIZED_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXJABBER */\r
+\r
+#define EMAC_RXJABBER_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXJABBER_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXUNDERSIZED */\r
+\r
+#define EMAC_RXUNDERSIZED_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXUNDERSIZED_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXFRAGMENTS */\r
+\r
+#define EMAC_RXFRAGMENTS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXFRAGMENTS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXFILTERED */\r
+\r
+#define EMAC_RXFILTERED_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXFILTERED_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXQOSFILTERED */\r
+\r
+#define EMAC_RXQOSFILTERED_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXQOSFILTERED_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXOCTETS */\r
+\r
+#define EMAC_RXOCTETS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXOCTETS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXGOODFRAMES */\r
+\r
+#define EMAC_TXGOODFRAMES_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXGOODFRAMES_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXBCASTFRAMES */\r
+\r
+#define EMAC_TXBCASTFRAMES_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXBCASTFRAMES_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXMCASTFRAMES */\r
+\r
+#define EMAC_TXMCASTFRAMES_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXMCASTFRAMES_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXPAUSEFRAMES */\r
+\r
+#define EMAC_TXPAUSEFRAMES_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXDEFERRED */\r
+\r
+#define EMAC_TXDEFERRED_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXDEFERRED_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXCOLLISION */\r
+\r
+#define EMAC_TXCOLLISION_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXCOLLISION_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXSINGLECOLL */\r
+\r
+#define EMAC_TXSINGLECOLL_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXSINGLECOLL_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXMULTICOLL */\r
+\r
+#define EMAC_TXMULTICOLL_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXMULTICOLL_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXEXCESSIVECOLL */\r
+\r
+#define EMAC_TXEXCESSIVECOLL_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXLATECOLL */\r
+\r
+#define EMAC_TXLATECOLL_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXLATECOLL_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXUNDERRUN */\r
+\r
+#define EMAC_TXUNDERRUN_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXUNDERRUN_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXCARRIERSENSE */\r
+\r
+#define EMAC_TXCARRIERSENSE_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXCARRIERSENSE_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* TXOCTETS */\r
+\r
+#define EMAC_TXOCTETS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_TXOCTETS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* FRAME64 */\r
+\r
+#define EMAC_FRAME64_COUNT (0xFFFFFFFFu)\r
+#define EMAC_FRAME64_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* FRAME65T127 */\r
+\r
+#define EMAC_FRAME65T127_COUNT (0xFFFFFFFFu)\r
+#define EMAC_FRAME65T127_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* FRAME128T255 */\r
+\r
+#define EMAC_FRAME128T255_COUNT (0xFFFFFFFFu)\r
+#define EMAC_FRAME128T255_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* FRAME256T511 */\r
+\r
+#define EMAC_FRAME256T511_COUNT (0xFFFFFFFFu)\r
+#define EMAC_FRAME256T511_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* FRAME512T1023 */\r
+\r
+#define EMAC_FRAME512T1023_COUNT (0xFFFFFFFFu)\r
+#define EMAC_FRAME512T1023_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* FRAME1024TUP */\r
+\r
+#define EMAC_FRAME1024TUP_COUNT (0xFFFFFFFFu)\r
+#define EMAC_FRAME1024TUP_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* NETOCTETS */\r
+\r
+#define EMAC_NETOCTETS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_NETOCTETS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXSOFOVERRUNS */\r
+\r
+#define EMAC_RXSOFOVERRUNS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXMOFOVERRUNS */\r
+\r
+#define EMAC_RXMOFOVERRUNS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* RXDMAOVERRUNS */\r
+\r
+#define EMAC_RXDMAOVERRUNS_COUNT (0xFFFFFFFFu)\r
+#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACADDRLO */\r
+\r
+\r
+#define EMAC_MACADDRLO_VALID (0x00100000u)\r
+#define EMAC_MACADDRLO_VALID_SHIFT (0x00000014u)\r
+#define EMAC_MACADDRLO_MATCHFILT (0x00080000u)\r
+#define EMAC_MACADDRLO_MATCHFILT_SHIFT (0x00000013u)\r
+#define EMAC_MACADDRLO_CHANNEL (0x00070000u)\r
+#define EMAC_MACADDRLO_CHANNEL_SHIFT (0x00000010u)\r
+#define EMAC_MACADDRLO_MACADDR0 (0x0000FF00u)\r
+#define EMAC_MACADDRLO_MACADDR0_SHIFT (0x00000008u)\r
+#define EMAC_MACADDRLO_MACADDR1 (0x000000FFu)\r
+#define EMAC_MACADDRLO_MACADDR1_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACADDRHI */\r
+\r
+#define EMAC_MACADDRHI_MACADDR2 (0xFF000000u)\r
+#define EMAC_MACADDRHI_MACADDR2_SHIFT (0x00000018u)\r
+\r
+#define EMAC_MACADDRHI_MACADDR3 (0x00FF0000u)\r
+#define EMAC_MACADDRHI_MACADDR3_SHIFT (0x00000010u)\r
+\r
+#define EMAC_MACADDRHI_MACADDR4 (0x0000FF00u)\r
+#define EMAC_MACADDRHI_MACADDR4_SHIFT (0x00000008u)\r
+\r
+#define EMAC_MACADDRHI_MACADDR5 (0x000000FFu)\r
+#define EMAC_MACADDRHI_MACADDR5_SHIFT (0x00000000u)\r
+\r
+\r
+/* MACINDEX */\r
+\r
+\r
+#define EMAC_MACINDEX_MACINDEX (0x0000001Fu)\r
+#define EMAC_MACINDEX_MACINDEX_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX0HDP */\r
+\r
+#define EMAC_TX0HDP_TX0HDP (0xFFFFFFFFu)\r
+#define EMAC_TX0HDP_TX0HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX1HDP */\r
+\r
+#define EMAC_TX1HDP_TX1HDP (0xFFFFFFFFu)\r
+#define EMAC_TX1HDP_TX1HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX2HDP */\r
+\r
+#define EMAC_TX2HDP_TX2HDP (0xFFFFFFFFu)\r
+#define EMAC_TX2HDP_TX2HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX3HDP */\r
+\r
+#define EMAC_TX3HDP_TX3HDP (0xFFFFFFFFu)\r
+#define EMAC_TX3HDP_TX3HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX4HDP */\r
+\r
+#define EMAC_TX4HDP_TX4HDP (0xFFFFFFFFu)\r
+#define EMAC_TX4HDP_TX4HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX5HDP */\r
+\r
+#define EMAC_TX5HDP_TX5HDP (0xFFFFFFFFu)\r
+#define EMAC_TX5HDP_TX5HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX6HDP */\r
+\r
+#define EMAC_TX6HDP_TX6HDP (0xFFFFFFFFu)\r
+#define EMAC_TX6HDP_TX6HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX7HDP */\r
+\r
+#define EMAC_TX7HDP_TX7HDP (0xFFFFFFFFu)\r
+#define EMAC_TX7HDP_TX7HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX0HDP */\r
+\r
+#define EMAC_RX0HDP_RX0HDP (0xFFFFFFFFu)\r
+#define EMAC_RX0HDP_RX0HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX1HDP */\r
+\r
+#define EMAC_RX1HDP_RX1HDP (0xFFFFFFFFu)\r
+#define EMAC_RX1HDP_RX1HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX2HDP */\r
+\r
+#define EMAC_RX2HDP_RX2HDP (0xFFFFFFFFu)\r
+#define EMAC_RX2HDP_RX2HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX3HDP */\r
+\r
+#define EMAC_RX3HDP_RX3HDP (0xFFFFFFFFu)\r
+#define EMAC_RX3HDP_RX3HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX4HDP */\r
+\r
+#define EMAC_RX4HDP_RX4HDP (0xFFFFFFFFu)\r
+#define EMAC_RX4HDP_RX4HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX5HDP */\r
+\r
+#define EMAC_RX5HDP_RX5HDP (0xFFFFFFFFu)\r
+#define EMAC_RX5HDP_RX5HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX6HDP */\r
+\r
+#define EMAC_RX6HDP_RX6HDP (0xFFFFFFFFu)\r
+#define EMAC_RX6HDP_RX6HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX7HDP */\r
+\r
+#define EMAC_RX7HDP_RX7HDP (0xFFFFFFFFu)\r
+#define EMAC_RX7HDP_RX7HDP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX0CP */\r
+\r
+#define EMAC_TX0CP_TX0CP (0xFFFFFFFFu)\r
+#define EMAC_TX0CP_TX0CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX1CP */\r
+\r
+#define EMAC_TX1CP_TX1CP (0xFFFFFFFFu)\r
+#define EMAC_TX1CP_TX1CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX2CP */\r
+\r
+#define EMAC_TX2CP_TX2CP (0xFFFFFFFFu)\r
+#define EMAC_TX2CP_TX2CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX3CP */\r
+\r
+#define EMAC_TX3CP_TX3CP (0xFFFFFFFFu)\r
+#define EMAC_TX3CP_TX3CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX4CP */\r
+\r
+#define EMAC_TX4CP_TX4CP (0xFFFFFFFFu)\r
+#define EMAC_TX4CP_TX4CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX5CP */\r
+\r
+#define EMAC_TX5CP_TX5CP (0xFFFFFFFFu)\r
+#define EMAC_TX5CP_TX5CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX6CP */\r
+\r
+#define EMAC_TX6CP_TX6CP (0xFFFFFFFFu)\r
+#define EMAC_TX6CP_TX6CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* TX7CP */\r
+\r
+#define EMAC_TX7CP_TX7CP (0xFFFFFFFFu)\r
+#define EMAC_TX7CP_TX7CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX0CP */\r
+\r
+#define EMAC_RX0CP_RX0CP (0xFFFFFFFFu)\r
+#define EMAC_RX0CP_RX0CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX1CP */\r
+\r
+#define EMAC_RX1CP_RX1CP (0xFFFFFFFFu)\r
+#define EMAC_RX1CP_RX1CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX2CP */\r
+\r
+#define EMAC_RX2CP_RX2CP (0xFFFFFFFFu)\r
+#define EMAC_RX2CP_RX2CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX3CP */\r
+\r
+#define EMAC_RX3CP_RX3CP (0xFFFFFFFFu)\r
+#define EMAC_RX3CP_RX3CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX4CP */\r
+\r
+#define EMAC_RX4CP_RX4CP (0xFFFFFFFFu)\r
+#define EMAC_RX4CP_RX4CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX5CP */\r
+\r
+#define EMAC_RX5CP_RX5CP (0xFFFFFFFFu)\r
+#define EMAC_RX5CP_RX5CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX6CP */\r
+\r
+#define EMAC_RX6CP_RX6CP (0xFFFFFFFFu)\r
+#define EMAC_RX6CP_RX6CP_SHIFT (0x00000000u)\r
+\r
+\r
+/* RX7CP */\r
+\r
+#define EMAC_RX7CP_RX7CP (0xFFFFFFFFu)\r
+#define EMAC_RX7CP_RX7CP_SHIFT (0x00000000u)\r
+\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * hw_emac1.h\r
+ */\r
+\r
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ * ALL RIGHTS RESERVED\r
+ */\r
+\r
+#ifndef _HW_EMAC_CTRL_H_\r
+#define _HW_EMAC_CTRL_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#define EMAC_CTRL_REVID (0x0u)\r
+#define EMAC_CTRL_SOFTRESET (0x4u)\r
+#define EMAC_CTRL_INTCONTROL (0xCu)\r
+#define EMAC_CTRL_C0RXTHRESHEN (0x10u)\r
+#define EMAC_CTRL_CnRXEN(n) (0x14u + (n << 4))\r
+#define EMAC_CTRL_CnTXEN(n) (0x18u + (n << 4))\r
+#define EMAC_CTRL_CnMISCEN(n) (0x1Cu + (n << 4))\r
+#define EMAC_CTRL_CnRXTHRESHEN(n) (0x20u + (n << 4))\r
+#define EMAC_CTRL_C0RXTHRESHSTAT (0x40u)\r
+#define EMAC_CTRL_C0RXSTAT (0x44u)\r
+#define EMAC_CTRL_C0TXSTAT (0x48u)\r
+#define EMAC_CTRL_C0MISCSTAT (0x4Cu)\r
+#define EMAC_CTRL_C1RXTHRESHSTAT (0x50u)\r
+#define EMAC_CTRL_C1RXSTAT (0x54u)\r
+#define EMAC_CTRL_C1TXSTAT (0x58u)\r
+#define EMAC_CTRL_C1MISCSTAT (0x5Cu)\r
+#define EMAC_CTRL_C2RXTHRESHSTAT (0x60u)\r
+#define EMAC_CTRL_C2RXSTAT (0x64u)\r
+#define EMAC_CTRL_C2TXSTAT (0x68u)\r
+#define EMAC_CTRL_C2MISCSTAT (0x6Cu)\r
+#define EMAC_CTRL_C0RXIMAX (0x70u)\r
+#define EMAC_CTRL_C0TXIMAX (0x74u)\r
+#define EMAC_CTRL_C1RXIMAX (0x78u)\r
+#define EMAC_CTRL_C1TXIMAX (0x7Cu)\r
+#define EMAC_CTRL_C2RXIMAX (0x80u)\r
+#define EMAC_CTRL_C2TXIMAX (0x84u)\r
+\r
+/**************************************************************************\\r
+* Field Definition Macros\r
+\**************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * hw_mdio.h\r
+ */\r
+\r
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ * ALL RIGHTS RESERVED\r
+ */\r
+\r
+\r
+#ifndef _HW_MDIO_H_\r
+#define _HW_MDIO_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#define MDIO_BASE (0xFCF78900U)\r
+\r
+#define MDIO_REVID (0x0)\r
+#define MDIO_CONTROL (0x4)\r
+#define MDIO_ALIVE (0x8)\r
+#define MDIO_LINK (0xC)\r
+#define MDIO_LINKINTRAW (0x10)\r
+#define MDIO_LINKINTMASKED (0x14)\r
+#define MDIO_USERINTRAW (0x20)\r
+#define MDIO_USERINTMASKED (0x24)\r
+#define MDIO_USERINTMASKSET (0x28)\r
+#define MDIO_USERINTMASKCLEAR (0x2C)\r
+#define MDIO_USERACCESS0 (0x80)\r
+#define MDIO_USERPHYSEL0 (0x84)\r
+#define MDIO_USERACCESS1 (0x88)\r
+#define MDIO_USERPHYSEL1 (0x8C)\r
+\r
+/**************************************************************************\\r
+* Field Definition Macros\r
+\**************************************************************************/\r
+\r
+/* REVID */\r
+\r
+#define MDIO_REVID_REV (0xFFFFFFFFu)\r
+#define MDIO_REVID_REV_SHIFT (0x00000000u)\r
+\r
+\r
+/* CONTROL */\r
+\r
+#define MDIO_CONTROL_IDLE (0x80000000u)\r
+#define MDIO_CONTROL_IDLE_SHIFT (0x0000001Fu)\r
+/*----IDLE Tokens----*/\r
+#define MDIO_CONTROL_IDLE_NO (0x00000000u)\r
+#define MDIO_CONTROL_IDLE_YES (0x00000001u)\r
+\r
+#define MDIO_CONTROL_ENABLE (0x40000000u)\r
+#define MDIO_CONTROL_ENABLE_SHIFT (0x0000001Eu)\r
+\r
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL (0x1F000000u)\r
+#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT (0x00000018u)\r
+\r
+\r
+#define MDIO_CONTROL_PREAMBLE (0x00100000u)\r
+#define MDIO_CONTROL_PREAMBLE_SHIFT (0x00000014u)\r
+/*----PREAMBLE Tokens----*/\r
+\r
+#define MDIO_CONTROL_FAULT (0x00080000u)\r
+#define MDIO_CONTROL_FAULT_SHIFT (0x00000013u)\r
+\r
+#define MDIO_CONTROL_FAULTENB (0x00040000u)\r
+#define MDIO_CONTROL_FAULTENB_SHIFT (0x00000012u)\r
+/*----FAULTENB Tokens----*/\r
+\r
+\r
+\r
+#define MDIO_CONTROL_CLKDIV (0x0000FFFFu)\r
+#define MDIO_CONTROL_CLKDIV_SHIFT (0x00000000u)\r
+/*----CLKDIV Tokens----*/\r
+\r
+\r
+/* ALIVE */\r
+\r
+#define MDIO_ALIVE_REGVAL (0xFFFFFFFFu)\r
+#define MDIO_ALIVE_REGVAL_SHIFT (0x00000000u)\r
+\r
+\r
+/* LINK */\r
+\r
+#define MDIO_LINK_REGVAL (0xFFFFFFFFu)\r
+#define MDIO_LINK_REGVAL_SHIFT (0x00000000u)\r
+\r
+\r
+/* LINKINTRAW */\r
+\r
+\r
+#define MDIO_LINKINTRAW_USERPHY1 (0x00000002u)\r
+#define MDIO_LINKINTRAW_USERPHY1_SHIFT (0x00000001u)\r
+\r
+#define MDIO_LINKINTRAW_USERPHY0 (0x00000001u)\r
+#define MDIO_LINKINTRAW_USERPHY0_SHIFT (0x00000000u)\r
+\r
+\r
+/* LINKINTMASKED */\r
+\r
+\r
+#define MDIO_LINKINTMASKED_USERPHY1 (0x00000002u)\r
+#define MDIO_LINKINTMASKED_USERPHY1_SHIFT (0x00000001u)\r
+\r
+#define MDIO_LINKINTMASKED_USERPHY0 (0x00000001u)\r
+#define MDIO_LINKINTMASKED_USERPHY0_SHIFT (0x00000000u)\r
+\r
+\r
+/* USERINTRAW */\r
+\r
+\r
+#define MDIO_USERINTRAW_USERACCESS1 (0x00000002u)\r
+#define MDIO_USERINTRAW_USERACCESS1_SHIFT (0x00000001u)\r
+\r
+#define MDIO_USERINTRAW_USERACCESS0 (0x00000001u)\r
+#define MDIO_USERINTRAW_USERACCESS0_SHIFT (0x00000000u)\r
+\r
+\r
+/* USERINTMASKED */\r
+\r
+\r
+#define MDIO_USERINTMASKED_USERACCESS1 (0x00000002u)\r
+#define MDIO_USERINTMASKED_USERACCESS1_SHIFT (0x00000001u)\r
+\r
+#define MDIO_USERINTMASKED_USERACCESS0 (0x00000001u)\r
+#define MDIO_USERINTMASKED_USERACCESS0_SHIFT (0x00000000u)\r
+\r
+\r
+/* USERINTMASKSET */\r
+\r
+\r
+#define MDIO_USERINTMASKSET_USERACCESS1 (0x00000002u)\r
+#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT (0x00000001u)\r
+\r
+#define MDIO_USERINTMASKSET_USERACCESS0 (0x00000001u)\r
+#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT (0x00000000u)\r
+\r
+\r
+/* USERINTMASKCLEAR */\r
+\r
+\r
+#define MDIO_USERINTMASKCLEAR_USERACCESS1 (0x00000002u)\r
+#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT (0x00000001u)\r
+\r
+#define MDIO_USERINTMASKCLEAR_USERACCESS0 (0x00000001u)\r
+#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT (0x00000000u)\r
+\r
+\r
+/* USERACCESS0 */\r
+\r
+#define MDIO_USERACCESS0_GO (0x80000000u)\r
+#define MDIO_USERACCESS0_GO_SHIFT (0x0000001Fu)\r
+\r
+#define MDIO_USERACCESS0_WRITE (0x40000000u)\r
+#define MDIO_USERACCESS0_READ (0x00000000u)\r
+#define MDIO_USERACCESS0_WRITE_SHIFT (0x0000001Eu)\r
+\r
+#define MDIO_USERACCESS0_ACK (0x20000000u)\r
+#define MDIO_USERACCESS0_ACK_SHIFT (0x0000001Du)\r
+\r
+\r
+#define MDIO_USERACCESS0_REGADR (0x03E00000u)\r
+#define MDIO_USERACCESS0_REGADR_SHIFT (0x00000015u)\r
+\r
+#define MDIO_USERACCESS0_PHYADR (0x001F0000u)\r
+#define MDIO_USERACCESS0_PHYADR_SHIFT (0x00000010u)\r
+\r
+#define MDIO_USERACCESS0_DATA (0x0000FFFFu)\r
+#define MDIO_USERACCESS0_DATA_SHIFT (0x00000000u)\r
+\r
+\r
+/* USERPHYSEL0 */\r
+\r
+\r
+#define MDIO_USERPHYSEL0_LINKSEL (0x00000080u)\r
+#define MDIO_USERPHYSEL0_LINKSEL_SHIFT (0x00000007u)\r
+\r
+#define MDIO_USERPHYSEL0_LINKINTENB (0x00000040u)\r
+#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT (0x00000006u)\r
+\r
+\r
+#define MDIO_USERPHYSEL0_PHYADRMON (0x0000001Fu)\r
+#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT (0x00000000u)\r
+\r
+\r
+/* USERACCESS1 */\r
+\r
+#define MDIO_USERACCESS1_GO (0x80000000u)\r
+#define MDIO_USERACCESS1_GO_SHIFT (0x0000001Fu)\r
+\r
+#define MDIO_USERACCESS1_WRITE (0x40000000u)\r
+#define MDIO_USERACCESS1_WRITE_SHIFT (0x0000001Eu)\r
+\r
+#define MDIO_USERACCESS1_ACK (0x20000000u)\r
+#define MDIO_USERACCESS1_ACK_SHIFT (0x0000001Du)\r
+\r
+\r
+#define MDIO_USERACCESS1_REGADR (0x03E00000u)\r
+#define MDIO_USERACCESS1_REGADR_SHIFT (0x00000015u)\r
+\r
+#define MDIO_USERACCESS1_PHYADR (0x001F0000u)\r
+#define MDIO_USERACCESS1_PHYADR_SHIFT (0x00000010u)\r
+\r
+#define MDIO_USERACCESS1_DATA (0x0000FFFFu)\r
+#define MDIO_USERACCESS1_DATA_SHIFT (0x00000000u)\r
+\r
+\r
+/* USERPHYSEL1 */\r
+\r
+\r
+#define MDIO_USERPHYSEL1_LINKSEL (0x00000080u)\r
+#define MDIO_USERPHYSEL1_LINKSEL_SHIFT (0x00000007u)\r
+\r
+#define MDIO_USERPHYSEL1_LINKINTENB (0x00000040u)\r
+#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT (0x00000006u)\r
+\r
+\r
+#define MDIO_USERPHYSEL1_PHYADRMON (0x0000001Fu)\r
+#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0x00000000u)\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * hw_reg_access.h.h\r
+ */\r
+\r
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ * ALL RIGHTS RESERVED\r
+ */\r
+\r
+#ifndef _HW_REG_ACCESS_H_\r
+#define _HW_REG_ACCESS_H_\r
+\r
+//*****************************************************************************\r
+//\r
+// Macros for hardware access, both direct and via the bit-band region.\r
+//\r
+//*****************************************************************************\r
+#define HWREG(x) \\r
+ (*((volatile unsigned long *)(x)))\r
+#define HWREGH(x) \\r
+ (*((volatile unsigned short *)(x)))\r
+#define HWREGB(x) \\r
+ (*((volatile unsigned char *)(x)))\r
+#define HWREGBITW(x, b) \\r
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITH(x, b) \\r
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+#define HWREGBITB(x, b) \\r
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \\r
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))\r
+\r
+\r
+\r
+#endif // __HW_TYPES_H__\r
--- /dev/null
+/** @file I2C.h\r
+* @brief I2C Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#ifndef __I2C_H__\r
+#define __I2C_H__\r
+\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+\r
+\r
+/** @enum i2cMode\r
+* @brief Alias names for i2c modes\r
+* This enumeration is used to provide alias names for I2C modes:\r
+*/\r
+\r
+enum i2cMode\r
+{\r
+ I2C_FD_FORMAT = 0x0008, /* Free Data Format */\r
+ I2C_START_BYTE = 0x0010,\r
+ I2C_RESET_OUT = 0x0020, I2C_RESET_IN = 0x0000,\r
+ I2C_DLOOPBACK = 0x0040, \r
+ I2C_REPEATMODE = 0x0080, /* In Master Mode only */ \r
+ I2C_10BIT_AMODE = 0x0100, I2C_7BIT_AMODE = 0x0000,\r
+ I2C_TRANSMITTER = 0x0200, I2C_RECEIVER = 0x0000, \r
+ I2C_MASTER = 0x0400, I2C_SLAVE = 0x0000, \r
+ I2C_STOP_COND = 0x0800, /* In Master Mode only */\r
+ I2C_START_COND = 0x2000, /* In Master Mode only */ \r
+ I2C_FREE_RUN = 0x4000,\r
+ I2C_NACK_MODE = 0x8000\r
+};\r
+\r
+\r
+/** @enum i2cBitCount\r
+* @brief Alias names for i2c bit count\r
+* This enumeration is used to provide alias names for I2C bit count:\r
+*/\r
+\r
+enum i2cBitCount\r
+{\r
+ I2C_2_BIT = 0x2, \r
+ I2C_3_BIT = 0x3, \r
+ I2C_4_BIT = 0x4, \r
+ I2C_5_BIT = 0x5, \r
+ I2C_6_BIT = 0x6, \r
+ I2C_7_BIT = 0x7, \r
+ I2C_8_BIT = 0x0 \r
+};\r
+\r
+\r
+\r
+/** @enum i2cIntFlags\r
+* @brief Interrupt Flag Definitions\r
+*\r
+* Used with I2CEnableNotification, I2CDisableNotification\r
+*/\r
+enum i2cIntFlags\r
+{\r
+ I2C_AL_INT = 0x0001, /* arbitration lost */\r
+ I2C_NACK_INT = 0x0002, /* no acknowledgement */\r
+ I2C_ARDY_INT = 0x0004, /* access ready */\r
+ I2C_RX_INT = 0x0008, /* receive data ready */\r
+ I2C_TX_INT = 0x0010, /* transmit data ready */\r
+ I2C_SCD_INT = 0x0020, /* stop condition detect */\r
+ I2C_AAS_INT = 0x0040 /* address as slave */\r
+};\r
+\r
+\r
+/** @enum i2cStatFlags\r
+* @brief Interrupt Status Definitions\r
+*\r
+*/\r
+enum i2cStatFlags\r
+{\r
+ I2C_BUSBUSY = 0x1000, /* bus busy */\r
+ I2C_RXFULL = 0x0800 /* receive full */\r
+};\r
+\r
+\r
+/** @enum i2cDMA\r
+* @brief I2C DMA definitions \r
+*\r
+* Used before i2c transfer\r
+*/\r
+enum i2cDMA\r
+{\r
+ I2C_TXDMA = 0x20, \r
+ I2C_RXDMA = 0x10 \r
+};\r
+\r
+/** @struct i2cBase\r
+* @brief I2C Base Register Definition\r
+*\r
+* This structure is used to access the I2C module egisters.\r
+*/\r
+/** @typedef i2cBASE_t\r
+* @brief I2C Register Frame Type Definition\r
+*\r
+* This type is used to access the I2C Registers.\r
+*/\r
+typedef volatile struct i2cBase\r
+{\r
+\r
+ uint32_t OAR; /**< 0x0000 I2C Own Address register */\r
+ uint32_t IMR; /**< 0x0004 I2C Interrupt Mask/Status register */\r
+ uint32_t STR; /**< 0x0008 I2C Interrupt Status register */\r
+ uint32_t CLKL; /**< 0x000C I2C Clock Divider Low register */\r
+ uint32_t CLKH; /**< 0x0010 I2C Clock Divider High register */\r
+ uint32_t CNT; /**< 0x0014 I2C Data Count register */\r
+ uint32_t DRR; /**< 0x0018 I2C Data Receive register */\r
+ uint32_t SAR; /**< 0x001C I2C Slave Address register */\r
+ uint32_t DXR; /**< 0x0020 I2C Data Transmit register */\r
+ uint32_t MDR; /**< 0x0024 I2C Mode register */\r
+ uint32_t IVR; /**< 0x0028 I2C Interrupt Vector register */\r
+ uint32_t EMDR; /**< 0x002C I2C Extended Mode register */\r
+ uint32_t PSC; /**< 0x0030 I2C Prescaler register */\r
+ uint32_t PID11; /**< 0x0034 I2C Peripheral ID register 1 */\r
+ uint32_t PID12; /**< 0x0038 I2C Peripheral ID register 2 */\r
+ uint32_t DMAC; /**< 0x003C I2C DMA Control Register */\r
+ uint32_t : 32U; /**< 0x0040 Reserved */\r
+ uint32_t : 32U; /**< 0x0044 Reserved */\r
+ uint32_t FUN; /**< 0x0048 Pin Function Register */\r
+ uint32_t DIR; /**< 0x004C Pin Direction Register */\r
+ uint32_t DIN; /**< 0x0050 Pin Data In Register */\r
+ uint32_t DOUT; /**< 0x0054 Pin Data Out Register */\r
+ uint32_t SET; /**< 0x0058 Pin Data Set Register */\r
+ uint32_t CLR; /**< 0x005C Pin Data Clr Register */\r
+ uint32_t ODR; /**< 0x0060 Pin Open Drain Output Enable Register */\r
+ uint32_t PD; /**< 0x0064 Pin Pullup/Pulldown Disable Register */\r
+ uint32_t PSL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */\r
+} i2cBASE_t;\r
+\r
+\r
+/** @def i2cREG1\r
+* @brief I2C Register Frame Pointer\r
+*\r
+* This pointer is used by the I2C driver to access the I2C module registers.\r
+*/\r
+#define i2cREG1 ((i2cBASE_t *)0xFFF7D400U)\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/** @def i2cPORT1\r
+* @brief I2C GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of I2C\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define i2cPORT1 ((gioPORT_t *)0xFFF7D44CU)\r
+\r
+/* I2C Interface Functions */\r
+void i2cInit(void);\r
+void i2cSetOwnAdd(i2cBASE_t *i2c, uint32_t oadd);\r
+void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32_t sadd);\r
+void i2cSetBaudrate(i2cBASE_t *i2c, uint32_t baud);\r
+uint32_t i2cIsTxReady(i2cBASE_t *i2c);\r
+void i2cSendByte(i2cBASE_t *i2c, uint8_t byte);\r
+void i2cSend(i2cBASE_t *i2c, uint32_t length, uint8_t *data);\r
+uint32_t i2cIsRxReady(i2cBASE_t *i2c);\r
+void i2cClearSCD(i2cBASE_t *i2c);\r
+uint32_t i2cRxError(i2cBASE_t *i2c);\r
+uint32_t i2cReceiveByte(i2cBASE_t *i2c);\r
+void i2cReceive(i2cBASE_t *i2c, uint32_t length, uint8_t *data);\r
+void i2cEnableNotification(i2cBASE_t *i2c, uint32_t flags);\r
+void i2cDisableNotification(i2cBASE_t *i2c, uint32_t flags);\r
+void i2cSetStart(i2cBASE_t *i2c);\r
+void i2cSetStop(i2cBASE_t *i2c);\r
+void i2cSetCount(i2cBASE_t *i2c ,uint32_t cnt);\r
+void i2cEnableLoopback(i2cBASE_t *i2c);\r
+void i2cDisableLoopback(i2cBASE_t *i2c);\r
+\r
+/** @fn void i2cNotification(i2cBASE_t *i2c, uint32_t flags)\r
+* @brief Interrupt callback\r
+* @param[in] i2c - I2C module base address\r
+* @param[in] flags - copy of error interrupt flags\r
+*\r
+* This is a callback that is provided by the application and is called apon\r
+* an interrupt. The parameter passed to the callback is a copy of the \r
+* interrupt flag register.\r
+*/\r
+void i2cNotification(i2cBASE_t *i2c, uint32_t flags);\r
+\r
+#endif\r
--- /dev/null
+#define I2STR_PAD_0 0x100
+#define I2STR_LONG 0x200
+#define I2STR_NUMBER 0x400
+
+int i2str(char *s,long val,int len,int form);
--- /dev/null
+/** @file lin.h\r
+* @brief LIN Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __LIN_H__\r
+#define __LIN_H__\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+\r
+\r
+/** @def LIN_BREAK_INT\r
+* @brief Alias for break detect interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_BREAK_INT 0x00000001U\r
+\r
+\r
+/** @def LIN_WAKEUP_INT\r
+* @brief Alias for wakeup interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_WAKEUP_INT 0x00000002U\r
+\r
+\r
+/** @def LIN_TO_INT\r
+* @brief Alias for time out interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_TO_INT 0x00000010U\r
+\r
+\r
+/** @def LIN_TOAWUS_INT\r
+* @brief Alias for time out after wakeup signal interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_TOAWUS_INT 0x00000040U\r
+\r
+\r
+/** @def LIN_TOA3WUS_INT\r
+* @brief Alias for time out after 3 wakeup signals interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_TOA3WUS_INT 0x00000080U\r
+\r
+\r
+/** @def LIN_TX_READY\r
+* @brief Alias for transmit buffer ready flag\r
+*\r
+* Used with linIsTxReady.\r
+*/\r
+#define LIN_TX_READY 0x00000100U\r
+\r
+\r
+/** @def LIN_RX_INT\r
+* @brief Alias for receive buffer ready interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_RX_INT 0x00000200U\r
+\r
+\r
+/** @def LIN_ID_INT\r
+* @brief Alias for received matching identifier interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_ID_INT 0x00002000U\r
+\r
+\r
+/** @def LIN_PE_INT\r
+* @brief Alias for parity error interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_PE_INT 0x01000000U\r
+\r
+\r
+/** @def LIN_OE_INT\r
+* @brief Alias for overrun error interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_OE_INT 0x02000000U\r
+\r
+\r
+/** @def LIN_FE_INT\r
+* @brief Alias for framming error interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_FE_INT 0x04000000U\r
+\r
+\r
+/** @def LIN_NRE_INT\r
+* @brief Alias for no response error interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_NRE_INT 0x08000000U\r
+\r
+\r
+/** @def LIN_ISFE_INT\r
+* @brief Alias for inconsistent sync field error interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_ISFE_INT 0x10000000U\r
+\r
+\r
+/** @def LIN_CE_INT\r
+* @brief Alias for checksum error interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_CE_INT 0x20000000U\r
+\r
+\r
+/** @def LIN_PBE_INT\r
+* @brief Alias for physical bus error interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_PBE_INT 0x40000000U\r
+\r
+\r
+/** @def LIN_BE_INT\r
+* @brief Alias for bit error interrupt flag\r
+*\r
+* Used with linEnableNotification, linDisableNotification.\r
+*/\r
+#define LIN_BE_INT 0x80000000U\r
+\r
+\r
+/** @struct linBase\r
+* @brief LIN Register Definition\r
+*\r
+* This structure is used to access the LIN module egisters.\r
+*/\r
+/** @typedef linBASE_t\r
+* @brief LIN Register Frame Type Definition\r
+*\r
+* This type is used to access the LIN Registers.\r
+*/\r
+\r
+enum linPinSelect\r
+{\r
+ PIN_LIN_TX = 0,\r
+ PIN_LIN_RX = 1\r
+};\r
+\r
+/** @struct linBase\r
+* @brief LIN Base Register Definition\r
+*\r
+* This structure is used to access the LIN module egisters.\r
+*/\r
+/** @typedef linBASE_t\r
+* @brief LIN Register Frame Type Definition\r
+*\r
+* This type is used to access the LIN Registers.\r
+*/\r
+\r
+typedef volatile struct linBase\r
+{\r
+ uint32_t GCR0; /**< 0x0000: Global control register 0 */\r
+ uint32_t GCR1; /**< 0x0004: Global control register 1 */\r
+ uint32_t GCR2; /**< 0x0008: Global control register 2 */\r
+ uint32_t SETINT; /**< 0x000C: Set interrupt enable register */\r
+ uint32_t CLRINT; /**< 0x0010: Clear interrupt enable register */\r
+ uint32_t SETINTLVL; /**< 0x0014: Set interrupt level register */\r
+ uint32_t CLRINTLVL; /**< 0x0018: Set interrupt level register */\r
+ uint32_t FLR; /**< 0x001C: interrupt flag register */\r
+ uint32_t INTVECT0; /**< 0x0020: interrupt vector Offset 0 */\r
+ uint32_t INTVECT1; /**< 0x0024: interrupt vector Offset 1 */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) \r
+ uint32_t CHAR : 3U; /**< 0x0028: Character length control register */\r
+ uint32_t : 13U; /**< 0x0028: Reserved */\r
+ uint32_t LENGTH : 3U; /**< 0x0028: Length control register */\r
+ uint32_t : 13U; /**< 0x0028: Reserved */\r
+#else\r
+ uint32_t : 13U; /**< 0x0028: Reserved */\r
+ uint32_t LENGTH : 3U; /**< 0x0028: Length control register */\r
+ uint32_t : 13U; /**< 0x0028: Reserved */\r
+ uint32_t CHAR : 3U; /**< 0x0028: Character length control register */\r
+#endif\r
+ uint32_t BRSR; /**< 0x002C: Baud rate selection register */\r
+ uint32_t ED; /**< 0x0030: Emulation register */\r
+ uint32_t RD; /**< 0x0034: Receive data register */\r
+ uint32_t TD; /**< 0x0038: Transmit data register */\r
+ uint32_t FUN; /**< 0x003C: Pin function register */\r
+ uint32_t DIR; /**< 0x0040: Pin direction register */\r
+ uint32_t DIN; /**< 0x0044: Pin data in register */\r
+ uint32_t DOUT; /**< 0x0048: Pin data out register */\r
+ uint32_t SET; /**< 0x004C: Pin data set register */\r
+ uint32_t CLR; /**< 0x0050: Pin data clr register */\r
+ uint32_t ODR; /**< 0x0054: Pin open drain output enable register */\r
+ uint32_t PD; /**< 0x0058: Pin pullup/pulldown disable register */\r
+ uint32_t PSL; /**< 0x005C: Pin pullup/pulldown selection register */\r
+ uint32_t COMP; /**< 0x0060: Compare register */\r
+ uint8_t RDx[8U]; /**< 0x0064-0x0068: RX buffer register */\r
+ uint32_t MASK; /**< 0x006C: Mask register */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) \r
+ uint8_t IDBYTE; /**< 0x0070: Identifier byte register */\r
+ uint8_t IDSTB; /**< 0x0070: Identifier slave task byte register */\r
+ uint8_t RXID; /**< 0x0070: Received identifier register */\r
+ uint32_t : 8U; /**< 0x0070: Reserved */\r
+#else\r
+ uint32_t : 8U; /**< 0x0070: Reserved */\r
+ uint8_t RXID; /**< 0x0070: Received identifier register */\r
+ uint8_t IDSTB; /**< 0x0070: Identifier Slave task byte register */\r
+ uint8_t IDBYTE; /**< 0x0070: Identifier byte register */\r
+#endif\r
+ uint8_t TDx[8U]; /**< 0x0074-0x0078: TX buffer register */\r
+ uint32_t MBRSR; /**< 0x007C: Maximum baud rate selection register */\r
+ uint32_t SL; /**< 0x0080: Pin slew rate register */\r
+ uint32_t : 32U; /**< 0x0084: Reserved */\r
+ uint32_t : 32U; /**< 0x0088: Reserved */\r
+ uint32_t : 32U; /**< 0x008C: Reserved */\r
+ uint32_t IODFTCTRL; /**< 0x0090: IODFT loopback register */\r
+} linBASE_t;\r
+\r
+\r
+/** @def linREG\r
+* @brief LIN Register Frame Pointer\r
+*\r
+* This pointer is used by the LIN driver to access the lin module registers.\r
+*/\r
+#define linREG ((linBASE_t *)0xFFF7E400U)\r
+\r
+\r
+/** @def linPORT\r
+* @brief LIN GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of LIN\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define linPORT ((gioPORT_t *)0xFFF7E440U)\r
+\r
+/* LIN Interface Functions */\r
+void linInit(void);\r
+void linSetFunctional(linBASE_t *lin, uint32_t port);\r
+void linSendHeader(linBASE_t *lin, uint8_t identifier);\r
+void linSendWakupSignal(linBASE_t *lin);\r
+void linEnterSleep(linBASE_t *lin);\r
+void linSoftwareReset(linBASE_t *lin);\r
+uint32_t linIsTxReady(linBASE_t *lin);\r
+void linSetLength(linBASE_t *lin, uint32_t length);\r
+void linSend(linBASE_t *lin, const uint8_t *data);\r
+uint32_t linIsRxReady(linBASE_t *lin);\r
+uint32_t linTxRxError(linBASE_t *lin);\r
+uint32_t linGetIdentifier(linBASE_t *lin);\r
+void linGetData(linBASE_t *lin, uint8_t * const data);\r
+void linEnableNotification(linBASE_t *lin, uint32_t flags);\r
+void linDisableNotification(linBASE_t *lin, uint32_t flags);\r
+void linEnableLoopback(linBASE_t *lin, Loopbacktype_t Loopbacktype);\r
+void linDisableLoopback(linBASE_t *lin);\r
+\r
+/** @fn void linNotification(linBASE_t *lin, uint32_t flags)\r
+* @brief Interrupt callback\r
+* @param[in] lin - lin module base address\r
+* @param[in] flags - copy of error interrupt flags\r
+*\r
+* This is a callback that is provided by the application and is called apon\r
+* an interrupt. The parameter passed to the callback is a copy of the \r
+* interrupt flag register.\r
+*/\r
+void linNotification(linBASE_t *lin, uint32_t flags);\r
+#endif\r
--- /dev/null
+/**\r
+ * \file mdio.h\r
+ *\r
+ * \brief MDIO APIs and macros.\r
+ *\r
+ * This file contains the driver API prototypes and macro definitions.\r
+ */\r
+\r
+/* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/\r
+ * ALL RIGHTS RESERVED\r
+ */\r
+#ifndef __MDIO_H__\r
+#define __MDIO_H__\r
+\r
+#include "hw_mdio.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/*****************************************************************************/\r
+/*\r
+** Prototypes for the APIs\r
+*/\r
+extern unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr);\r
+extern unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr);\r
+extern void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,\r
+ unsigned int mdioOutputFreq);\r
+extern unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,\r
+ unsigned int regNum, volatile unsigned short *dataPtr);\r
+extern void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,\r
+ unsigned int regNum, unsigned short RegVal);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* __MDIO_H__ */\r
--- /dev/null
+/** @file mibspi.h\r
+* @brief MIBSPI Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __MIBSPI_H__\r
+#define __MIBSPI_H__\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+\r
+\r
+/** @enum triggerEvent\r
+* @brief Transfer Group Trigger Event\r
+*/\r
+enum triggerEvent\r
+{\r
+ TRG_NEVER = 0,\r
+ TRG_RISING = 1,\r
+ TRG_FALLING = 2,\r
+ TRG_BOTH = 3,\r
+ TRG_HIGH = 5,\r
+ TRG_LOW = 6,\r
+ TRG_ALWAYS = 7\r
+};\r
+\r
+/** @enum triggerSource\r
+* @brief Transfer Group Trigger Source\r
+*/\r
+enum triggerSource\r
+{\r
+ TRG_DISABLED,\r
+ TRG_GIOA0,\r
+ TRG_GIOA1,\r
+ TRG_GIOA2,\r
+ TRG_GIOA3,\r
+ TRG_GIOA4,\r
+ TRG_GIOA5,\r
+ TRG_GIOA6,\r
+ TRG_GIOA7,\r
+ TRG_HET8,\r
+ TRG_HET10,\r
+ TRG_HET12,\r
+ TRG_HET14,\r
+ TRG_HET16,\r
+ TRG_HET18,\r
+ TRG_TICK\r
+};\r
+\r
+\r
+/** @enum mibspiPinSelect\r
+* @brief mibspi Pin Select\r
+*/\r
+enum mibspiPinSelect\r
+{\r
+ PIN_CS0 = 0,\r
+ PIN_CS1 = 1,\r
+ PIN_CS2 = 2,\r
+ PIN_CS3 = 3,\r
+ PIN_CS4 = 4,\r
+ PIN_CS5 = 5,\r
+ PIN_CS6 = 6,\r
+ PIN_CS7 = 7,\r
+ PIN_ENA = 8,\r
+ PIN_CLK = 9,\r
+ PIN_SIMO = 10,\r
+ PIN_SOMI = 11,\r
+ PIN_SIMO_1 = 17,\r
+ PIN_SIMO_2 = 18,\r
+ PIN_SIMO_3 = 19,\r
+ PIN_SIMO_4 = 20,\r
+ PIN_SIMO_5 = 21,\r
+ PIN_SIMO_6 = 22,\r
+ PIN_SIMO_7 = 23,\r
+ PIN_SOMI_1 = 25,\r
+ PIN_SOMI_2 = 26,\r
+ PIN_SOMI_3 = 27,\r
+ PIN_SOMI_4 = 28,\r
+ PIN_SOMI_5 = 29,\r
+ PIN_SOMI_6 = 30,\r
+ PIN_SOMI_7 = 31\r
+};\r
+\r
+\r
+/** @enum chipSelect\r
+* @brief Transfer Group Chip Select\r
+*/\r
+enum chipSelect\r
+{\r
+ CS_NONE = 0xFF,\r
+ CS_0 = 0xFE,\r
+ CS_1 = 0xFD,\r
+ CS_2 = 0xFB,\r
+ CS_3 = 0xF7,\r
+ CS_4 = 0xEF,\r
+ CS_5 = 0xDF,\r
+ CS_6 = 0xBF,\r
+ CS_7 = 0x7F\r
+};\r
+\r
+\r
+\r
+/** @struct mibspiBase\r
+* @brief MIBSPI Register Definition\r
+*\r
+* This structure is used to access the MIBSPI module egisters.\r
+*/\r
+/** @typedef mibspiBASE_t\r
+* @brief MIBSPI Register Frame Type Definition\r
+*\r
+* This type is used to access the MIBSPI Registers.\r
+*/\r
+typedef volatile struct mibspiBase\r
+{\r
+ uint32_t GCR0; /**< 0x0000: Global Control 0 */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */\r
+ uint32_t PD : 1U; /**< 0x0006: Power down bit */\r
+ uint32_t : 7U;\r
+ uint32_t LB : 1U; /**< 0x0005: Loop back bit */\r
+ uint32_t : 7U;\r
+ uint32_t ENA : 1U; /**< 0x0004: MIBSPI Enable bit */\r
+ uint32_t : 7U; \r
+ uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */\r
+ uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */\r
+ uint32_t : 7U;\r
+ uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */\r
+ uint32_t : 7U;\r
+#else\r
+ uint32_t : 7U; \r
+ uint32_t ENA : 1U; /**< 0x0004: MIBSPI Enable bit */\r
+ uint32_t : 7U;\r
+ uint32_t LB : 1U; /**< 0x0005: Loop back bit */\r
+ uint32_t : 7U;\r
+ uint32_t PD : 1U; /**< 0x0006: Power down bit */\r
+ uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */\r
+ uint32_t : 7U;\r
+ uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */\r
+ uint32_t : 7U;\r
+ uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */\r
+ uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */\r
+#endif\r
+ uint32_t LVL; /**< 0x000C: Interrupt Level */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */\r
+ uint32_t : 8U;\r
+ uint32_t BUFINIT : 1U; /**< 0x0010: Buffer inialisation active flag */\r
+ uint32_t : 7U;\r
+#else\r
+ uint32_t : 7U;\r
+ uint32_t BUFINIT : 1U; /**< 0x0010: Buffer inialisation active flag */\r
+ uint32_t : 8U;\r
+ uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */ \r
+#endif\r
+ uint32_t PCFUN; /**< 0x0014: Function Pin Enable */\r
+ uint32_t PCDIR; /**< 0x0018: Pin Direction */\r
+ uint32_t PCDIN; /**< 0x001C: Pin Input Latch */\r
+ uint32_t PCDOUT; /**< 0x0020: Pin Output Latch */\r
+ uint32_t PCSET; /**< 0x0024: Output Pin Set */\r
+ uint32_t PCCLR; /**< 0x0028: Output Pin Clr */\r
+ uint32_t PCPDR; /**< 0x002C: Open Drain Output Enable */\r
+ uint32_t PCDIS; /**< 0x0030: Pullup/Pulldown Disable */\r
+ uint32_t PCPSL; /**< 0x0034: Pullup/Pulldown Selection */\r
+ uint32_t DAT0; /**< 0x0038: Transmit Data */\r
+ uint32_t DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */\r
+ uint32_t BUF; /**< 0x0040: Receive Buffer */\r
+ uint32_t EMU; /**< 0x0044: Emulation Receive Buffer */\r
+ uint32_t DELAY; /**< 0x0048: Delays */\r
+ uint32_t CSDEF; /**< 0x004C: Default Chip Select */\r
+ uint32_t FMT0; /**< 0x0050: Data Format 0 */\r
+ uint32_t FMT1; /**< 0x0054: Data Format 1 */\r
+ uint32_t FMT2; /**< 0x0058: Data Format 2 */\r
+ uint32_t FMT3; /**< 0x005C: Data Format 3 */\r
+ uint32_t INTVECT0; /**< 0x0060: Interrupt Vector 0 */\r
+ uint32_t INTVECT1; /**< 0x0064: Interrupt Vector 1 */\r
+ uint32_t SRSEL; /**< 0x0068: Slew Rate Select */\r
+ uint32_t PMCTRL; /**< 0x006C: Parrallel Mode Control */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t MIBSPIE : 16U; /**< 0x0072: MibSPI Enable */\r
+ uint32_t RAMACCESS : 16U; /**< 0x0070: RX Ram Write Access Enable */\r
+ uint32_t SETINTENASUS : 16U;\r
+ uint32_t SETINTENARDY : 16U; /**< 0x0074: Transfer Group Interrupt Enable Set Register */\r
+ uint32_t CLRINTENASUS : 16U;\r
+ uint32_t CLRINTENARDY : 16U; /**< 0x0078: Transfer Group Interrupt Enable Clear Register */\r
+ uint32_t SETINTLVLSUS : 16U;\r
+ uint32_t SETINTLVLRDY : 16U; /**< 0x007C: Transfer Group Interrupt Level Set Register */\r
+ uint32_t CLRINTLVLSUS : 16U;\r
+ uint32_t CLRINTLVLRDY : 16U; /**< 0x0080: Transfer Group Interrupt Level Clear Register */\r
+ uint32_t INTFLGSUS : 16U;\r
+ uint32_t INTFLGRDY : 16U; /**< 0x0084: Transfer Group Interrupt Flags */\r
+#else\r
+ uint32_t RAMACCESS : 16U; /**< 0x0070: RX Ram Write Access Enable */\r
+ uint32_t MIBSPIE : 16U; /**< 0x0072: MibSPI Enable */\r
+ uint32_t SETINTENARDY : 16U; /**< 0x0074: Transfer Group Interrupt Enable Set Register */\r
+ uint32_t SETINTENASUS : 16U;\r
+ uint32_t CLRINTENARDY : 16U; /**< 0x0078: Transfer Group Interrupt Enable Clear Register */\r
+ uint32_t CLRINTENASUS : 16U;\r
+ uint32_t SETINTLVLRDY : 16U; /**< 0x007C: Transfer Group Interrupt Level Set Register */\r
+ uint32_t SETINTLVLSUS : 16U;\r
+ uint32_t CLRINTLVLRDY : 16U; /**< 0x0080: Transfer Group Interrupt Level Clear Register */\r
+ uint32_t CLRINTLVLSUS : 16U;\r
+ uint32_t INTFLGRDY : 16U; /**< 0x0084: Transfer Group Interrupt Flags */\r
+ uint32_t INTFLGSUS : 16U;\r
+#endif\r
+ uint32_t : 32U;\r
+ uint32_t : 32U;\r
+ uint32_t TICKCNT; /**< 0x0090: Tick Counter */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t : 8U;\r
+ uint32_t LTGPEND : 7U; /**< 0x0096: Transfer Group End Pointer */\r
+ uint32_t : 9U;\r
+ uint32_t TGINSERVICE : 5U;\r
+ uint32_t : 3U;\r
+#else\r
+ uint32_t : 3U;\r
+ uint32_t TGINSERVICE : 5U;\r
+ uint32_t : 9U;\r
+ uint32_t LTGPEND : 7U; /**< 0x0096: Transfer Group End Pointer */\r
+ uint32_t : 8U;\r
+#endif\r
+ uint32_t TGCTRL[16U]; /**< 0x0098 - 0x00D4: Transfer Group Control */\r
+ uint32_t DMACTRL[8U]; /**< 0x00D8 - 0x00F4: DMA Control */\r
+ uint32_t DMACOUNT[8U]; /**< 0x00F8 - 0x0114: DMA Count */\r
+ uint32_t DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */\r
+ uint32_t : 32U;\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t EDEN : 4U;\r
+ uint32_t : 4U;\r
+ uint32_t PTESTEN : 1U;\r
+ uint32_t : 23U;\r
+#else\r
+ uint32_t : 23U;\r
+ uint32_t PTESTEN : 1U;\r
+ uint32_t : 4U;\r
+ uint32_t EDEN : 4U;\r
+#endif\r
+ uint32_t UERRSTAT;\r
+ uint32_t UERRADDRRX;\r
+ uint32_t UERRADDRTX;\r
+ uint32_t RXOVRN_BUF_ADDR; /**< 0x0130: */\r
+ uint32_t IOLPKTSTCR; /**< 0x0134: IO loopback */\r
+ uint32_t EXT_PRESCALE1; /**< 0x0138: */\r
+ uint32_t EXT_PRESCALE2; /**< 0x013C: */\r
+} mibspiBASE_t;\r
+\r
+\r
+/** @def mibspiREG1\r
+* @brief MIBSPI1 Register Frame Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi module registers.\r
+*/\r
+#define mibspiREG1 ((mibspiBASE_t *)0xFFF7F400U)\r
+\r
+\r
+/** @def mibspiPORT1\r
+* @brief MIBSPI1 GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of MIBSPI1\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define mibspiPORT1 ((gioPORT_t *)0xFFF7F418U)\r
+\r
+/** @def mibspiREG3\r
+* @brief MIBSPI3 Register Frame Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi module registers.\r
+*/\r
+#define mibspiREG3 ((mibspiBASE_t *)0xFFF7F800U)\r
+\r
+\r
+/** @def mibspiPORT3\r
+* @brief MIBSPI3 GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of MIBSPI3\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define mibspiPORT3 ((gioPORT_t *)0xFFF7F818U)\r
+\r
+/** @def mibspiREG5\r
+* @brief MIBSPI5 Register Frame Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi module registers.\r
+*/\r
+#define mibspiREG5 ((mibspiBASE_t *)0xFFF7FC00U)\r
+\r
+\r
+/** @def mibspiPORT5\r
+* @brief MIBSPI5 GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of MIBSPI5\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define mibspiPORT5 ((gioPORT_t *)0xFFF7FC18U)\r
+\r
+\r
+/** @struct mibspiRamBase\r
+* @brief MIBSPI Buffer RAM Definition\r
+*\r
+* This structure is used to access the MIBSPI buffer memory.\r
+*/\r
+/** @typedef mibspiRAM_t\r
+* @brief MIBSPI RAM Type Definition\r
+*\r
+* This type is used to access the MIBSPI RAM.\r
+*/\r
+typedef volatile struct mibspiRamBase\r
+{\r
+ struct \r
+ {\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint16_t data; /**< tx buffer data */ \r
+ uint16_t control; /**< tx buffer control */ \r
+#else\r
+ uint16_t control; /**< tx buffer control */\r
+ uint16_t data; /**< tx buffer data */\r
+#endif\r
+ } tx[128];\r
+ struct\r
+ {\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint16_t data; /**< rx buffer data */\r
+ uint16_t flags; /**< rx buffer flags */\r
+#else\r
+ uint16_t flags; /**< rx buffer flags */\r
+ uint16_t data; /**< rx buffer data */\r
+#endif\r
+ } rx[128];\r
+} mibspiRAM_t;\r
+\r
+\r
+/** @def mibspiRAM1\r
+* @brief MIBSPI1 Buffer RAM Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.\r
+*/\r
+#define mibspiRAM1 ((mibspiRAM_t *)0xFF0E0000U)\r
+\r
+/** @def mibspiRAM3\r
+* @brief MIBSPI3 Buffer RAM Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.\r
+*/\r
+#define mibspiRAM3 ((mibspiRAM_t *)0xFF0C0000U)\r
+\r
+/** @def mibspiRAM5\r
+* @brief MIBSPI5 Buffer RAM Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.\r
+*/\r
+#define mibspiRAM5 ((mibspiRAM_t *)0xFF0A0000U)\r
+\r
+/** @def mibspiPARRAM1\r
+* @brief MIBSPI1 Buffer RAM PARITY Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.\r
+*/\r
+#define mibspiPARRAM1 (*(unsigned int *)(0xFF0E0000U + 0x00000400U))\r
+\r
+/** @def mibspiPARRAM3\r
+* @brief MIBSPI3 Buffer RAM PARITY Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.\r
+*/\r
+#define mibspiPARRAM3 (*(unsigned int *)(0xFF0C0000U + 0x00000400U))\r
+\r
+\r
+/** @def mibspiPARRAM5\r
+* @brief MIBSPI5 Buffer RAM PARITY Pointer\r
+*\r
+* This pointer is used by the MIBSPI driver to access the mibspi buffer memory.\r
+*/\r
+#define mibspiPARRAM5 (*(unsigned int *)(0xFF0A0000U + 0x00000400U))\r
+\r
+\r
+/* MIBSPI Interface Functions */\r
+void mibspiInit(void);\r
+void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32_t port);\r
+void mibspiSetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[]);\r
+uint32_t mibspiGetData(mibspiBASE_t *mibspi, uint32_t group, uint16_t data[]);\r
+void mibspiTransfer(mibspiBASE_t *mibspi, uint32_t group);\r
+int mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32_t group);\r
+void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32_t group, uint32_t level);\r
+void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32_t group);\r
+void mibspiEnableLoopback(mibspiBASE_t *mibspi, Loopbacktype_t Loopbacktype);\r
+void mibspiDisableLoopback(mibspiBASE_t *mibspi);\r
+\r
+\r
+/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32_t flags)\r
+* @brief Error interrupt callback\r
+* @param[in] mibspi - mibSpi module base address\r
+* @param[in] flags - Copy of error interrupt flags\r
+*\r
+* This is a error callback that is provided by the application and is call apon\r
+* an error interrupt. The paramer passed to the callback is a copy of the error\r
+* interrupt flag register.\r
+*/\r
+void mibspiNotification(mibspiBASE_t *mibspi, uint32_t flags);\r
+\r
+\r
+/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32_t group)\r
+* @brief Transfer complete notification callback\r
+* @param[in] mibspi - mibSpi module base address\r
+* @param[in] group - Transfer group\r
+*\r
+* This is a callback function provided by the application. It is call when\r
+* a transfer is complete. The paramter is the transfer group that triggered\r
+* the interrupt.\r
+*/\r
+void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32_t group);\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef STACK_MACROS_H\r
+#define STACK_MACROS_H\r
+\r
+/*\r
+ * Call the stack overflow hook function if the stack of the task being swapped\r
+ * out is currently overflowed, or looks like it might have overflowed in the\r
+ * past.\r
+ *\r
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check\r
+ * the current stack state only - comparing the current top of stack value to\r
+ * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1\r
+ * will also cause the last few stack bytes to be checked to ensure the value\r
+ * to which the bytes were set when the task was created have not been\r
+ * overwritten. Note this second test does not guarantee that an overflowed\r
+ * stack will always be recognised.\r
+ */\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configCHECK_FOR_STACK_OVERFLOW == 0 )\r
+\r
+ /* FreeRTOSConfig.h is not set to check for stack overflows. */\r
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW()\r
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()\r
+\r
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( configCHECK_FOR_STACK_OVERFLOW == 1 )\r
+\r
+ /* FreeRTOSConfig.h is only set to use the first method of\r
+ overflow checking. */\r
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) )\r
+\r
+ /* Only the current stack state is to be checked. */\r
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \\r
+ { \\r
+ /* Is the currently saved stack pointer within the stack limit? */ \\r
+ if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \\r
+ { \\r
+ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\r
+ } \\r
+ }\r
+\r
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 0 */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) )\r
+\r
+ /* Only the current stack state is to be checked. */\r
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \\r
+ { \\r
+ \\r
+ /* Is the currently saved stack pointer within the stack limit? */ \\r
+ if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \\r
+ { \\r
+ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\r
+ } \\r
+ }\r
+\r
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )\r
+\r
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \\r
+ { \\r
+ static const unsigned char ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \\r
+ \\r
+ \\r
+ /* Has the extremity of the task stack ever been written over? */ \\r
+ if( memcmp( ( void * ) pxCurrentTCB->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \\r
+ { \\r
+ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\r
+ } \\r
+ }\r
+\r
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )\r
+\r
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \\r
+ { \\r
+ char *pcEndOfStack = ( char * ) pxCurrentTCB->pxEndOfStack; \\r
+ static const unsigned char ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \\r
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \\r
+ \\r
+ \\r
+ pcEndOfStack -= sizeof( ucExpectedStackBytes ); \\r
+ \\r
+ /* Has the extremity of the task stack ever been written over? */ \\r
+ if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \\r
+ { \\r
+ vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \\r
+ } \\r
+ }\r
+\r
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\r
+/*-----------------------------------------------------------*/\r
+\r
+#endif /* STACK_MACROS_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef CO_ROUTINE_H\r
+#define CO_ROUTINE_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h must appear in source files before include croutine.h"\r
+#endif\r
+\r
+#include "os_list.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Used to hide the implementation of the co-routine control block. The\r
+control block structure however has to be included in the header due to\r
+the macro implementation of the co-routine functionality. */\r
+typedef void * xCoRoutineHandle;\r
+\r
+/* Defines the prototype to which co-routine functions must conform. */\r
+typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE );\r
+\r
+typedef struct corCoRoutineControlBlock\r
+{\r
+ crCOROUTINE_CODE pxCoRoutineFunction;\r
+ xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */\r
+ xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */\r
+ unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */\r
+ unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */\r
+ unsigned short uxState; /*< Used internally by the co-routine implementation. */\r
+} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ portBASE_TYPE xCoRoutineCreate(\r
+ crCOROUTINE_CODE pxCoRoutineCode,\r
+ unsigned portBASE_TYPE uxPriority,\r
+ unsigned portBASE_TYPE uxIndex\r
+ );</pre>\r
+ *\r
+ * Create a new co-routine and add it to the list of co-routines that are\r
+ * ready to run.\r
+ *\r
+ * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine\r
+ * functions require special syntax - see the co-routine section of the WEB\r
+ * documentation for more information.\r
+ *\r
+ * @param uxPriority The priority with respect to other co-routines at which\r
+ * the co-routine will run.\r
+ *\r
+ * @param uxIndex Used to distinguish between different co-routines that\r
+ * execute the same function. See the example below and the co-routine section\r
+ * of the WEB documentation for further information.\r
+ *\r
+ * @return pdPASS if the co-routine was successfully created and added to a ready\r
+ * list, otherwise an error code defined with ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ // This may not be necessary for const variables.\r
+ static const char cLedToFlash[ 2 ] = { 5, 6 };\r
+ static const portTickType uxFlashRates[ 2 ] = { 200, 400 };\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // This co-routine just delays for a fixed period, then toggles\r
+ // an LED. Two co-routines are created using this function, so\r
+ // the uxIndex parameter is used to tell the co-routine which\r
+ // LED to flash and how long to delay. This assumes xQueue has\r
+ // already been created.\r
+ vParTestToggleLED( cLedToFlash[ uxIndex ] );\r
+ crDELAY( xHandle, uxFlashRates[ uxIndex ] );\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }\r
+\r
+ // Function that creates two co-routines.\r
+ void vOtherFunction( void )\r
+ {\r
+ unsigned char ucParameterToPass;\r
+ xTaskHandle xHandle;\r
+ \r
+ // Create two co-routines at priority 0. The first is given index 0\r
+ // so (from the code above) toggles LED 5 every 200 ticks. The second\r
+ // is given index 1 so toggles LED 6 every 400 ticks.\r
+ for( uxIndex = 0; uxIndex < 2; uxIndex++ )\r
+ {\r
+ xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xCoRoutineCreate xCoRoutineCreate\r
+ * \ingroup Tasks\r
+ */\r
+signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex );\r
+\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ void vCoRoutineSchedule( void );</pre>\r
+ *\r
+ * Run a co-routine.\r
+ *\r
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able\r
+ * to run. The co-routine will execute until it either blocks, yields or is\r
+ * preempted by a task. Co-routines execute cooperatively so one\r
+ * co-routine cannot be preempted by another, but can be preempted by a task.\r
+ *\r
+ * If an application comprises of both tasks and co-routines then\r
+ * vCoRoutineSchedule should be called from the idle task (in an idle task\r
+ * hook).\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // This idle task hook will schedule a co-routine each time it is called.\r
+ // The rest of the idle task will execute between co-routine calls.\r
+ void vApplicationIdleHook( void )\r
+ {\r
+ vCoRoutineSchedule();\r
+ }\r
+\r
+ // Alternatively, if you do not require any other part of the idle task to\r
+ // execute, the idle task hook can call vCoRoutineScheduler() within an\r
+ // infinite loop.\r
+ void vApplicationIdleHook( void )\r
+ {\r
+ for( ;; )\r
+ {\r
+ vCoRoutineSchedule();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule\r
+ * \ingroup Tasks\r
+ */\r
+void vCoRoutineSchedule( void );\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crSTART( xCoRoutineHandle xHandle );</pre>\r
+ *\r
+ * This macro MUST always be called at the start of a co-routine function.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static long ulAVariable;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Co-routine functionality goes here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crSTART crSTART\r
+ * \ingroup Tasks\r
+ */\r
+#define crSTART( pxCRCB ) switch( ( ( corCRCB * )( pxCRCB ) )->uxState ) { case 0:\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crEND();</pre>\r
+ *\r
+ * This macro MUST always be called at the end of a co-routine function.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static long ulAVariable;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Co-routine functionality goes here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crSTART crSTART\r
+ * \ingroup Tasks\r
+ */\r
+#define crEND() }\r
+\r
+/*\r
+ * These macros are intended for internal use by the co-routine implementation\r
+ * only. The macros should not be used directly by application writers.\r
+ */\r
+#define crSET_STATE0( xHandle ) ( ( corCRCB * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):\r
+#define crSET_STATE1( xHandle ) ( ( corCRCB * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):\r
+\r
+/**\r
+ * croutine. h\r
+ *<pre>\r
+ crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );</pre>\r
+ *\r
+ * Delay a co-routine for a fixed period of time.\r
+ *\r
+ * crDELAY can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * @param xHandle The handle of the co-routine to delay. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should delay\r
+ * for. The actual amount of time this equates to is defined by\r
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS\r
+ * can be used to convert ticks to milliseconds.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine to be created.\r
+ void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ // This may not be necessary for const variables.\r
+ // We are to delay for 200ms.\r
+ static const xTickType xDelayTime = 200 / portTICK_RATE_MS;\r
+\r
+ // Must start every co-routine with a call to crSTART();\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Delay for 200ms.\r
+ crDELAY( xHandle, xDelayTime );\r
+\r
+ // Do something here.\r
+ }\r
+\r
+ // Must end every co-routine with a call to crEND();\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crDELAY crDELAY\r
+ * \ingroup Tasks\r
+ */\r
+#define crDELAY( xHandle, xTicksToDelay ) \\r
+ if( ( xTicksToDelay ) > 0 ) \\r
+ { \\r
+ vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \\r
+ } \\r
+ crSET_STATE0( ( xHandle ) );\r
+\r
+/**\r
+ * <pre>\r
+ crQUEUE_SEND(\r
+ xCoRoutineHandle xHandle,\r
+ xQueueHandle pxQueue,\r
+ void *pvItemToQueue,\r
+ portTickType xTicksToWait,\r
+ portBASE_TYPE *pxResult\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\r
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\r
+ *\r
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\r
+ * xQueueSend() and xQueueReceive() can only be used from tasks.\r
+ *\r
+ * crQUEUE_SEND can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on\r
+ * passing data between tasks and co-routines and between ISR's and\r
+ * co-routines.\r
+ *\r
+ * @param xHandle The handle of the calling co-routine. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param pxQueue The handle of the queue on which the data will be posted.\r
+ * The handle is obtained as the return value when the queue is created using\r
+ * the xQueueCreate() API function.\r
+ *\r
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.\r
+ * The number of bytes of each queued item is specified when the queue is\r
+ * created. This number of bytes is copied from pvItemToQueue into the queue\r
+ * itself.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should block\r
+ * to wait for space to become available on the queue, should space not be\r
+ * available immediately. The actual amount of time this equates to is defined\r
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant\r
+ * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example\r
+ * below).\r
+ *\r
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\r
+ * data was successfully posted onto the queue, otherwise it will be set to an\r
+ * error defined within ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Co-routine function that blocks for a fixed period then posts a number onto\r
+ // a queue.\r
+ static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static portBASE_TYPE xNumberToPost = 0;\r
+ static portBASE_TYPE xResult;\r
+\r
+ // Co-routines must begin with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // This assumes the queue has already been created.\r
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );\r
+\r
+ if( xResult != pdPASS )\r
+ {\r
+ // The message was not posted!\r
+ }\r
+\r
+ // Increment the number to be posted onto the queue.\r
+ xNumberToPost++;\r
+\r
+ // Delay for 100 ticks.\r
+ crDELAY( xHandle, 100 );\r
+ }\r
+\r
+ // Co-routines must end with a call to crEND().\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crQUEUE_SEND crQUEUE_SEND\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \\r
+{ \\r
+ *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \\r
+ if( *( pxResult ) == errQUEUE_BLOCKED ) \\r
+ { \\r
+ crSET_STATE0( ( xHandle ) ); \\r
+ *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \\r
+ } \\r
+ if( *pxResult == errQUEUE_YIELD ) \\r
+ { \\r
+ crSET_STATE1( ( xHandle ) ); \\r
+ *pxResult = pdPASS; \\r
+ } \\r
+}\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_RECEIVE(\r
+ xCoRoutineHandle xHandle,\r
+ xQueueHandle pxQueue,\r
+ void *pvBuffer,\r
+ portTickType xTicksToWait,\r
+ portBASE_TYPE *pxResult\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\r
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\r
+ *\r
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\r
+ * xQueueSend() and xQueueReceive() can only be used from tasks.\r
+ *\r
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not\r
+ * from within a function called by the co-routine function. This is because\r
+ * co-routines do not maintain their own stack.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on\r
+ * passing data between tasks and co-routines and between ISR's and\r
+ * co-routines.\r
+ *\r
+ * @param xHandle The handle of the calling co-routine. This is the xHandle\r
+ * parameter of the co-routine function.\r
+ *\r
+ * @param pxQueue The handle of the queue from which the data will be received.\r
+ * The handle is obtained as the return value when the queue is created using\r
+ * the xQueueCreate() API function.\r
+ *\r
+ * @param pvBuffer The buffer into which the received item is to be copied.\r
+ * The number of bytes of each queued item is specified when the queue is\r
+ * created. This number of bytes is copied into pvBuffer.\r
+ *\r
+ * @param xTickToDelay The number of ticks that the co-routine should block\r
+ * to wait for data to become available from the queue, should data not be\r
+ * available immediately. The actual amount of time this equates to is defined\r
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant\r
+ * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the\r
+ * crQUEUE_SEND example).\r
+ *\r
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\r
+ * data was successfully retrieved from the queue, otherwise it will be set to\r
+ * an error code as defined within ProjDefs.h.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine receives the number of an LED to flash from a queue. It\r
+ // blocks on the queue until the number is received.\r
+ static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.\r
+ static portBASE_TYPE xResult;\r
+ static unsigned portBASE_TYPE uxLEDToFlash;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Wait for data to become available on the queue.\r
+ crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\r
+\r
+ if( xResult == pdPASS )\r
+ {\r
+ // We received the LED to flash - flash it!\r
+ vParTestToggleLED( uxLEDToFlash );\r
+ }\r
+ }\r
+\r
+ crEND();\r
+ }</pre>\r
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \\r
+{ \\r
+ *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \\r
+ if( *( pxResult ) == errQUEUE_BLOCKED ) \\r
+ { \\r
+ crSET_STATE0( ( xHandle ) ); \\r
+ *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \\r
+ } \\r
+ if( *( pxResult ) == errQUEUE_YIELD ) \\r
+ { \\r
+ crSET_STATE1( ( xHandle ) ); \\r
+ *( pxResult ) = pdPASS; \\r
+ } \\r
+}\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_SEND_FROM_ISR(\r
+ xQueueHandle pxQueue,\r
+ void *pvItemToQueue,\r
+ portBASE_TYPE xCoRoutinePreviouslyWoken\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\r
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\r
+ * functions used by tasks.\r
+ *\r
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\r
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\r
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and\r
+ * ISR.\r
+ *\r
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue\r
+ * that is being used from within a co-routine.\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on\r
+ * passing data between tasks and co-routines and between ISR's and\r
+ * co-routines.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto\r
+ * the same queue multiple times from a single interrupt. The first call\r
+ * should always pass in pdFALSE. Subsequent calls should pass in\r
+ * the value returned from the previous call.\r
+ *\r
+ * @return pdTRUE if a co-routine was woken by posting onto the queue. This is\r
+ * used by the ISR to determine if a context switch may be required following\r
+ * the ISR.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine that blocks on a queue waiting for characters to be received.\r
+ static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ char cRxedChar;\r
+ portBASE_TYPE xResult;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Wait for data to become available on the queue. This assumes the\r
+ // queue xCommsRxQueue has already been created!\r
+ crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\r
+\r
+ // Was a character received?\r
+ if( xResult == pdPASS )\r
+ {\r
+ // Process the character here.\r
+ }\r
+ }\r
+\r
+ // All co-routines must end with a call to crEND().\r
+ crEND();\r
+ }\r
+\r
+ // An ISR that uses a queue to send characters received on a serial port to\r
+ // a co-routine.\r
+ void vUART_ISR( void )\r
+ {\r
+ char cRxedChar;\r
+ portBASE_TYPE xCRWokenByPost = pdFALSE;\r
+\r
+ // We loop around reading characters until there are none left in the UART.\r
+ while( UART_RX_REG_NOT_EMPTY() )\r
+ {\r
+ // Obtain the character from the UART.\r
+ cRxedChar = UART_RX_REG;\r
+\r
+ // Post the character onto a queue. xCRWokenByPost will be pdFALSE\r
+ // the first time around the loop. If the post causes a co-routine\r
+ // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.\r
+ // In this manner we can ensure that if more than one co-routine is\r
+ // blocked on the queue only one is woken by this ISR no matter how\r
+ // many characters are posted to the queue.\r
+ xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );\r
+ }\r
+ }</pre>\r
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )\r
+\r
+\r
+/**\r
+ * croutine. h\r
+ * <pre>\r
+ crQUEUE_SEND_FROM_ISR(\r
+ xQueueHandle pxQueue,\r
+ void *pvBuffer,\r
+ portBASE_TYPE * pxCoRoutineWoken\r
+ )</pre>\r
+ *\r
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\r
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\r
+ * functions used by tasks.\r
+ *\r
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\r
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\r
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and\r
+ * ISR.\r
+ *\r
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data\r
+ * from a queue that is being used from within a co-routine (a co-routine\r
+ * posted to the queue).\r
+ *\r
+ * See the co-routine section of the WEB documentation for information on\r
+ * passing data between tasks and co-routines and between ISR's and\r
+ * co-routines.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvBuffer A pointer to a buffer into which the received item will be\r
+ * placed. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from the queue into\r
+ * pvBuffer.\r
+ *\r
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become\r
+ * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a\r
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise\r
+ * *pxCoRoutineWoken will remain unchanged.\r
+ *\r
+ * @return pdTRUE an item was successfully received from the queue, otherwise\r
+ * pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // A co-routine that posts a character to a queue then blocks for a fixed\r
+ // period. The character is incremented each time.\r
+ static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )\r
+ {\r
+ // cChar holds its value while this co-routine is blocked and must therefore\r
+ // be declared static.\r
+ static char cCharToTx = 'a';\r
+ portBASE_TYPE xResult;\r
+\r
+ // All co-routines must start with a call to crSTART().\r
+ crSTART( xHandle );\r
+\r
+ for( ;; )\r
+ {\r
+ // Send the next character to the queue.\r
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );\r
+\r
+ if( xResult == pdPASS )\r
+ {\r
+ // The character was successfully posted to the queue.\r
+ }\r
+ else\r
+ {\r
+ // Could not post the character to the queue.\r
+ }\r
+\r
+ // Enable the UART Tx interrupt to cause an interrupt in this\r
+ // hypothetical UART. The interrupt will obtain the character\r
+ // from the queue and send it.\r
+ ENABLE_RX_INTERRUPT();\r
+\r
+ // Increment to the next character then block for a fixed period.\r
+ // cCharToTx will maintain its value across the delay as it is\r
+ // declared static.\r
+ cCharToTx++;\r
+ if( cCharToTx > 'x' )\r
+ {\r
+ cCharToTx = 'a';\r
+ }\r
+ crDELAY( 100 );\r
+ }\r
+\r
+ // All co-routines must end with a call to crEND().\r
+ crEND();\r
+ }\r
+\r
+ // An ISR that uses a queue to receive characters to send on a UART.\r
+ void vUART_ISR( void )\r
+ {\r
+ char cCharToTx;\r
+ portBASE_TYPE xCRWokenByPost = pdFALSE;\r
+\r
+ while( UART_TX_REG_EMPTY() )\r
+ {\r
+ // Are there any characters in the queue waiting to be sent?\r
+ // xCRWokenByPost will automatically be set to pdTRUE if a co-routine\r
+ // is woken by the post - ensuring that only a single co-routine is\r
+ // woken no matter how many times we go around this loop.\r
+ if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )\r
+ {\r
+ SEND_CHARACTER( cCharToTx );\r
+ }\r
+ }\r
+ }</pre>\r
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR\r
+ * \ingroup Tasks\r
+ */\r
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )\r
+\r
+/*\r
+ * This function is intended for internal use by the co-routine macros only.\r
+ * The macro nature of the co-routine implementation requires that the\r
+ * prototype appears here. The function should not be used by application\r
+ * writers.\r
+ *\r
+ * Removes the current co-routine from its ready list and places it in the\r
+ * appropriate delayed list.\r
+ */\r
+void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList );\r
+\r
+/*\r
+ * This function is intended for internal use by the queue implementation only.\r
+ * The function should not be used by application writers.\r
+ *\r
+ * Removes the highest priority co-routine from the event list and places it in\r
+ * the pending ready list.\r
+ */\r
+signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList );\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* CO_ROUTINE_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*\r
+ * This is the list implementation used by the scheduler. While it is tailored\r
+ * heavily for the schedulers needs, it is also available for use by\r
+ * application code.\r
+ *\r
+ * xLists can only store pointers to xListItems. Each xListItem contains a\r
+ * numeric value (xItemValue). Most of the time the lists are sorted in\r
+ * descending item value order.\r
+ *\r
+ * Lists are created already containing one list item. The value of this\r
+ * item is the maximum possible that can be stored, it is therefore always at\r
+ * the end of the list and acts as a marker. The list member pxHead always\r
+ * points to this marker - even though it is at the tail of the list. This\r
+ * is because the tail contains a wrap back pointer to the true head of\r
+ * the list.\r
+ *\r
+ * In addition to it's value, each list item contains a pointer to the next\r
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)\r
+ * and a pointer to back to the object that contains it. These later two\r
+ * pointers are included for efficiency of list manipulation. There is\r
+ * effectively a two way link between the object containing the list item and\r
+ * the list item itself.\r
+ *\r
+ *\r
+ * \page ListIntroduction List Implementation\r
+ * \ingroup FreeRTOSIntro\r
+ */\r
+\r
+\r
+#ifndef LIST_H\r
+#define LIST_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+/*\r
+ * Definition of the only type of object that a list can contain.\r
+ */\r
+struct xLIST_ITEM\r
+{\r
+ portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */\r
+ volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */\r
+ volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */\r
+ void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */\r
+ void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */\r
+};\r
+typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */\r
+\r
+struct xMINI_LIST_ITEM\r
+{\r
+ portTickType xItemValue;\r
+ volatile struct xLIST_ITEM *pxNext;\r
+ volatile struct xLIST_ITEM *pxPrevious;\r
+};\r
+typedef struct xMINI_LIST_ITEM xMiniListItem;\r
+\r
+/*\r
+ * Definition of the type of queue used by the scheduler.\r
+ */\r
+typedef struct xLIST\r
+{\r
+ volatile unsigned portBASE_TYPE uxNumberOfItems;\r
+ volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */\r
+ volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */\r
+} xList;\r
+\r
+/*\r
+ * Access macro to set the owner of a list item. The owner of a list item\r
+ * is the object (usually a TCB) that contains the list item.\r
+ *\r
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\r
+ * \ingroup LinkedList\r
+ */\r
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) ( pxOwner )\r
+\r
+/*\r
+ * Access macro to set the value of the list item. In most cases the value is\r
+ * used to sort the list in descending order.\r
+ *\r
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE\r
+ * \ingroup LinkedList\r
+ */\r
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = ( xValue )\r
+\r
+/*\r
+ * Access macro the retrieve the value of the list item. The value can\r
+ * represent anything - for example a the priority of a task, or the time at\r
+ * which a task should be unblocked.\r
+ *\r
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue )\r
+\r
+/*\r
+ * Access macro the retrieve the value of the list item at the head of a given\r
+ * list.\r
+ *\r
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->xItemValue )\r
+\r
+/*\r
+ * Access macro to determine if a list contains any items. The macro will\r
+ * only have the value true if the list is empty.\r
+ *\r
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 )\r
+\r
+/*\r
+ * Access macro to return the number of items in the list.\r
+ */\r
+#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems )\r
+\r
+/*\r
+ * Access function to obtain the owner of the next entry in a list.\r
+ *\r
+ * The list member pxIndex is used to walk through a list. Calling\r
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list\r
+ * and returns that entries pxOwner parameter. Using multiple calls to this\r
+ * function it is therefore possible to move through every item contained in\r
+ * a list.\r
+ *\r
+ * The pxOwner parameter of a list item is a pointer to the object that owns\r
+ * the list item. In the scheduler this is normally a task control block.\r
+ * The pxOwner parameter effectively creates a two way link between the list\r
+ * item and its owner.\r
+ *\r
+ * @param pxList The list from which the next item owner is to be returned.\r
+ *\r
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \\r
+{ \\r
+xList * const pxConstList = ( pxList ); \\r
+ /* Increment the index to the next item and return the item, ensuring */ \\r
+ /* we don't return the marker used at the end of the list. */ \\r
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \\r
+ if( ( pxConstList )->pxIndex == ( xListItem * ) &( ( pxConstList )->xListEnd ) ) \\r
+ { \\r
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \\r
+ } \\r
+ ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \\r
+}\r
+\r
+\r
+/*\r
+ * Access function to obtain the owner of the first entry in a list. Lists\r
+ * are normally sorted in ascending item value order.\r
+ *\r
+ * This function returns the pxOwner member of the first item in the list.\r
+ * The pxOwner parameter of a list item is a pointer to the object that owns\r
+ * the list item. In the scheduler this is normally a task control block.\r
+ * The pxOwner parameter effectively creates a two way link between the list\r
+ * item and its owner.\r
+ *\r
+ * @param pxList The list from which the owner of the head item is to be\r
+ * returned.\r
+ *\r
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY\r
+ * \ingroup LinkedList\r
+ */\r
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )\r
+\r
+/*\r
+ * Check to see if a list item is within a list. The list item maintains a\r
+ * "container" pointer that points to the list it is in. All this macro does\r
+ * is check to see if the container and the list match.\r
+ *\r
+ * @param pxList The list we want to know if the list item is within.\r
+ * @param pxListItem The list item we want to know if is in the list.\r
+ * @return pdTRUE is the list item is in the list, otherwise pdFALSE.\r
+ * pointer against\r
+ */\r
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) )\r
+\r
+/*\r
+ * Must be called before a list is used! This initialises all the members\r
+ * of the list structure and inserts the xListEnd item into the list as a\r
+ * marker to the back of the list.\r
+ *\r
+ * @param pxList Pointer to the list being initialised.\r
+ *\r
+ * \page vListInitialise vListInitialise\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInitialise( xList *pxList );\r
+\r
+/*\r
+ * Must be called before a list item is used. This sets the list container to\r
+ * null so the item does not think that it is already contained in a list.\r
+ *\r
+ * @param pxItem Pointer to the list item being initialised.\r
+ *\r
+ * \page vListInitialiseItem vListInitialiseItem\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInitialiseItem( xListItem *pxItem );\r
+\r
+/*\r
+ * Insert a list item into a list. The item will be inserted into the list in\r
+ * a position determined by its item value (descending item value order).\r
+ *\r
+ * @param pxList The list into which the item is to be inserted.\r
+ *\r
+ * @param pxNewListItem The item to that is to be placed in the list.\r
+ *\r
+ * \page vListInsert vListInsert\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInsert( xList *pxList, xListItem *pxNewListItem );\r
+\r
+/*\r
+ * Insert a list item into a list. The item will be inserted in a position\r
+ * such that it will be the last item within the list returned by multiple\r
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.\r
+ *\r
+ * The list member pvIndex is used to walk through a list. Calling\r
+ * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.\r
+ * Placing an item in a list using vListInsertEnd effectively places the item\r
+ * in the list position pointed to by pvIndex. This means that every other\r
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before\r
+ * the pvIndex parameter again points to the item being inserted.\r
+ *\r
+ * @param pxList The list into which the item is to be inserted.\r
+ *\r
+ * @param pxNewListItem The list item to be inserted into the list.\r
+ *\r
+ * \page vListInsertEnd vListInsertEnd\r
+ * \ingroup LinkedList\r
+ */\r
+void vListInsertEnd( xList *pxList, xListItem *pxNewListItem );\r
+\r
+/*\r
+ * Remove an item from a list. The list item has a pointer to the list that\r
+ * it is in, so only the list item need be passed into the function.\r
+ *\r
+ * @param vListRemove The item to be removed. The item will remove itself from\r
+ * the list pointed to by it's pxContainer parameter.\r
+ *\r
+ * \page vListRemove vListRemove\r
+ * \ingroup LinkedList\r
+ */\r
+void vListRemove( xListItem *pxItemToRemove );\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef MPU_WRAPPERS_H\r
+#define MPU_WRAPPERS_H\r
+\r
+/* This file redefines API functions to be called through a wrapper macro, but\r
+only for ports that are using the MPU. */\r
+#ifdef portUSING_MPU_WRAPPERS\r
+\r
+ /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is\r
+ included from queue.c or task.c to prevent it from having an effect within\r
+ those files. */\r
+ #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+ #define xTaskGenericCreate MPU_xTaskGenericCreate\r
+ #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions\r
+ #define vTaskDelete MPU_vTaskDelete\r
+ #define vTaskDelayUntil MPU_vTaskDelayUntil\r
+ #define vTaskDelay MPU_vTaskDelay\r
+ #define uxTaskPriorityGet MPU_uxTaskPriorityGet\r
+ #define vTaskPrioritySet MPU_vTaskPrioritySet\r
+ #define vTaskSuspend MPU_vTaskSuspend\r
+ #define xTaskIsTaskSuspended MPU_xTaskIsTaskSuspended\r
+ #define vTaskResume MPU_vTaskResume\r
+ #define vTaskSuspendAll MPU_vTaskSuspendAll\r
+ #define xTaskResumeAll MPU_xTaskResumeAll\r
+ #define xTaskGetTickCount MPU_xTaskGetTickCount\r
+ #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks\r
+ #define vTaskList MPU_vTaskList\r
+ #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats\r
+ #define vTaskStartTrace MPU_vTaskStartTrace\r
+ #define ulTaskEndTrace MPU_ulTaskEndTrace\r
+ #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag\r
+ #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag\r
+ #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook\r
+ #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark\r
+ #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle\r
+ #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState\r
+\r
+ #define xQueueCreate MPU_xQueueCreate\r
+ #define xQueueCreateMutex MPU_xQueueCreateMutex\r
+ #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive\r
+ #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive\r
+ #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore\r
+ #define xQueueGenericSend MPU_xQueueGenericSend\r
+ #define xQueueAltGenericSend MPU_xQueueAltGenericSend\r
+ #define xQueueAltGenericReceive MPU_xQueueAltGenericReceive\r
+ #define xQueueGenericReceive MPU_xQueueGenericReceive\r
+ #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting\r
+ #define vQueueDelete MPU_vQueueDelete\r
+\r
+ #define pvPortMalloc MPU_pvPortMalloc\r
+ #define vPortFree MPU_vPortFree\r
+ #define xPortGetFreeHeapSize MPU_xPortGetFreeHeapSize\r
+ #define vPortInitialiseBlocks MPU_vPortInitialiseBlocks\r
+\r
+ #if configQUEUE_REGISTRY_SIZE > 0\r
+ #define vQueueAddToRegistry MPU_vQueueAddToRegistry\r
+ #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue\r
+ #endif\r
+\r
+ /* Remove the privileged function macro. */\r
+ #define PRIVILEGED_FUNCTION\r
+\r
+ #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\r
+\r
+ /* Ensure API functions go in the privileged execution section. */\r
+ #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))\r
+ #define PRIVILEGED_DATA __attribute__((section("privileged_data")))\r
+ //#define PRIVILEGED_DATA\r
+\r
+ #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\r
+\r
+#else /* portUSING_MPU_WRAPPERS */\r
+\r
+ #define PRIVILEGED_FUNCTION\r
+ #define PRIVILEGED_DATA\r
+ #define portUSING_MPU_WRAPPERS 0\r
+\r
+#endif /* portUSING_MPU_WRAPPERS */\r
+\r
+\r
+#endif /* MPU_WRAPPERS_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Portable layer API. Each function must be defined for each port.\r
+ *----------------------------------------------------------*/\r
+\r
+#ifndef PORTABLE_H\r
+#define PORTABLE_H\r
+\r
+/* Include the macro file relevant to the port being used. */\r
+\r
+#include "os_portmacro.h"\r
+\r
+\r
+/* Catch all to ensure portmacro.h is included in the build. Newer demos\r
+have the path as part of the project options, rather than as relative from\r
+the project location. If portENTER_CRITICAL() has not been defined then\r
+portmacro.h has not yet been included - as every portmacro.h provides a\r
+portENTER_CRITICAL() definition. Check the demo application for your demo\r
+to find the path to the correct portmacro.h file. */\r
+#ifndef portENTER_CRITICAL\r
+ #include "portmacro.h" \r
+#endif\r
+ \r
+#if portBYTE_ALIGNMENT == 8\r
+ #define portBYTE_ALIGNMENT_MASK ( 0x0007 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 4\r
+ #define portBYTE_ALIGNMENT_MASK ( 0x0003 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 2\r
+ #define portBYTE_ALIGNMENT_MASK ( 0x0001 )\r
+#endif\r
+\r
+#if portBYTE_ALIGNMENT == 1\r
+ #define portBYTE_ALIGNMENT_MASK ( 0x0000 )\r
+#endif\r
+\r
+#ifndef portBYTE_ALIGNMENT_MASK\r
+ #error "Invalid portBYTE_ALIGNMENT definition"\r
+#endif\r
+\r
+#ifndef portNUM_CONFIGURABLE_REGIONS\r
+ #define portNUM_CONFIGURABLE_REGIONS 1\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include "os_mpu_wrappers.h"\r
+\r
+/*\r
+ * Setup the stack of a new task so it is ready to be placed under the\r
+ * scheduler control. The registers have to be placed on the stack in\r
+ * the order that the port expects to find them.\r
+ *\r
+ */\r
+#if( portUSING_MPU_WRAPPERS == 1 )\r
+ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged ) PRIVILEGED_FUNCTION;\r
+#else\r
+ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters );\r
+#endif\r
+\r
+/*\r
+ * Map to the memory management routines required for the port.\r
+ */\r
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;\r
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;\r
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;\r
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Setup the hardware ready for the scheduler to take control. This generally\r
+ * sets up a tick interrupt and sets timers for the correct tick frequency.\r
+ */\r
+portBASE_TYPE xPortStartScheduler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so\r
+ * the hardware is left in its original condition after the scheduler stops\r
+ * executing.\r
+ */\r
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The structures and methods of manipulating the MPU are contained within the\r
+ * port layer.\r
+ *\r
+ * Fills the xMPUSettings structure with the memory region information\r
+ * contained in xRegions.\r
+ */\r
+#if( portUSING_MPU_WRAPPERS == 1 ) \r
+ struct xMEMORY_REGION;\r
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth ) PRIVILEGED_FUNCTION;\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* PORTABLE_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+ Atollic AB - Atollic provides professional embedded systems development \r
+ tools for C/C++ development, code analysis and test automation. \r
+ See http://www.atollic.com\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef __OS_PORTMACRO_H__\r
+#define __OS_PORTMACRO_H__\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* RTI Register Frame Definition */\r
+\r
+struct rti\r
+{\r
+ unsigned GCTRL;\r
+ unsigned TBCTRL;\r
+ unsigned CAPCTRL;\r
+ unsigned COMPCTRL;\r
+ struct\r
+ {\r
+ unsigned FRCx;\r
+ unsigned UCx;\r
+ unsigned CPUCx;\r
+ unsigned : 32;\r
+ unsigned CAFRCx;\r
+ unsigned CAUCx;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ } CNT[2U];\r
+ struct\r
+ {\r
+ unsigned COMPx;\r
+ unsigned UDCPx;\r
+ } CMP[4U];\r
+ unsigned TBLCOMP;\r
+ unsigned TBHCOMP;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned SETINT;\r
+ unsigned CLEARINT;\r
+ unsigned INTFLAG;\r
+ unsigned : 32;\r
+ unsigned DWDCTRL;\r
+ unsigned DWDPRLD;\r
+ unsigned WDSTATUS;\r
+ unsigned WDKEY;\r
+ unsigned WDCNTR;\r
+};\r
+\r
+#define RTI ((volatile struct rti *)0xFFFFFC00U)\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Type Definitions */\r
+\r
+#define portCHAR char\r
+#define portFLOAT float\r
+#define portDOUBLE double\r
+#define portLONG long\r
+#define portSHORT short\r
+#define portSTACK_TYPE unsigned long\r
+#define portBASE_TYPE long\r
+\r
+#if (configUSE_16_BIT_TICKS == 1)\r
+ typedef unsigned portSHORT portTickType;\r
+ #define portMAX_DELAY (portTickType) 0xFFFF\r
+#else\r
+ typedef unsigned portLONG portTickType;\r
+ #define portMAX_DELAY (portTickType) 0xFFFFFFFFF\r
+#endif\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Architecture Definitions */\r
+\r
+#define portSTACK_GROWTH (-1)\r
+#define portTICK_RATE_MS ((portTickType) 1000 / configTICK_RATE_HZ) \r
+#define portBYTE_ALIGNMENT 8\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* External Functions */\r
+\r
+extern void vPortEnterCritical(void);\r
+extern void vPortExitCritical(void);\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Functions Macros */\r
+\r
+#define portNOP() asm (" nop")\r
+#define portYIELD() _call_swi(0)\r
+#define portYIELD_FROM_ISR() vTaskSwitchContext()\r
+#define portENTER_CRITICAL() vPortEnterCritical()\r
+#define portEXIT_CRITICAL() vPortExitCritical()\r
+#define portDISABLE_INTERRUPTS() asm (" CPSID if")\r
+#define portENABLE_INTERRUPTS() asm (" CPSIE if")\r
+\r
+#define portTASK_FUNCTION(vFunction, pvParameters) void vFunction(void *pvParameters)\r
+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)\r
+\r
+#if (configGENERATE_RUN_TIME_STATS == 1)\r
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() \\r
+{ \\r
+ RTI->GCTRL = 0x00000000U; \\r
+ RTI->TBCTRL = 0x00000000U; \\r
+ RTI->COMPCTRL = 0x00000000U; \\r
+ RTI->CNT[1U].UCx = 0x00000000U; \\r
+ RTI->CNT[1U].FRCx = 0x00000000U; \\r
+ RTI->CNT[1U].CPUCx = (configCPU_CLOCK_HZ / 2 / configTICK_RATE_HZ) / 16; \\r
+ RTI->CMP[1U].UDCPx = (configCPU_CLOCK_HZ / 2 / configTICK_RATE_HZ) / 16; \\r
+ RTI->GCTRL = 0x00000002U; \\r
+}\r
+#define portGET_RUN_TIME_COUNTER_VALUE() (RTI->CNT[1].FRCx)\r
+#endif\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef PROJDEFS_H\r
+#define PROJDEFS_H\r
+\r
+/* Defines the prototype to which task functions must conform. */\r
+typedef void (*pdTASK_CODE)( void * );\r
+\r
+#define pdTRUE ( 1 )\r
+#define pdFALSE ( 0 )\r
+\r
+#define pdPASS ( 1 )\r
+#define pdFAIL ( 0 )\r
+#define errQUEUE_EMPTY ( 0 )\r
+#define errQUEUE_FULL ( 0 )\r
+\r
+/* Error definitions. */\r
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )\r
+#define errNO_TASK_TO_RUN ( -2 )\r
+#define errQUEUE_BLOCKED ( -4 )\r
+#define errQUEUE_YIELD ( -5 )\r
+\r
+#endif /* PROJDEFS_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef QUEUE_H\r
+#define QUEUE_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "#include FreeRTOS.h" must appear in source files before "#include queue.h"\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+#include "os_mpu_wrappers.h"\r
+\r
+/**\r
+ * Type by which queues are referenced. For example, a call to xQueueCreate\r
+ * returns (via a pointer parameter) an xQueueHandle variable that can then\r
+ * be used as a parameter to xQueueSend(), xQueueReceive(), etc.\r
+ */\r
+typedef void * xQueueHandle;\r
+\r
+\r
+/* For internal use only. */\r
+#define queueSEND_TO_BACK ( 0 )\r
+#define queueSEND_TO_FRONT ( 1 )\r
+\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ xQueueHandle xQueueCreate(\r
+ unsigned portBASE_TYPE uxQueueLength,\r
+ unsigned portBASE_TYPE uxItemSize\r
+ );\r
+ * </pre>\r
+ *\r
+ * Creates a new queue instance. This allocates the storage required by the\r
+ * new queue and returns a handle for the queue.\r
+ *\r
+ * @param uxQueueLength The maximum number of items that the queue can contain.\r
+ *\r
+ * @param uxItemSize The number of bytes each item in the queue will require.\r
+ * Items are queued by copy, not by reference, so this is the number of bytes\r
+ * that will be copied for each posted item. Each item on the queue must be\r
+ * the same size.\r
+ *\r
+ * @return If the queue is successfully create then a handle to the newly\r
+ * created queue is returned. If the queue cannot be created then 0 is\r
+ * returned.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ };\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+ if( xQueue1 == 0 )\r
+ {\r
+ // Queue was not created and must not be used.\r
+ }\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue2 == 0 )\r
+ {\r
+ // Queue was not created and must not be used.\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueCreate xQueueCreate\r
+ * \ingroup QueueManagement\r
+ */\r
+xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendToToFront(\r
+ xQueueHandle xQueue,\r
+ const void * pvItemToQueue,\r
+ portTickType xTicksToWait\r
+ );\r
+ * </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSend().\r
+ *\r
+ * Post an item to the front of a queue. The item is queued by copy, not by\r
+ * reference. This function must not be called from an interrupt service\r
+ * routine. See xQueueSendFromISR () for an alternative which may be used\r
+ * in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0 and the\r
+ * queue is full. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned long ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become\r
+ // available if necessary.\r
+ if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendToBack(\r
+ xQueueHandle xQueue,\r
+ const void * pvItemToQueue,\r
+ portTickType xTicksToWait\r
+ );\r
+ * </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSend().\r
+ *\r
+ * Post an item to the back of a queue. The item is queued by copy, not by\r
+ * reference. This function must not be called from an interrupt service\r
+ * routine. See xQueueSendFromISR () for an alternative which may be used\r
+ * in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0 and the queue\r
+ * is full. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned long ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become\r
+ // available if necessary.\r
+ if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSend(\r
+ xQueueHandle xQueue,\r
+ const void * pvItemToQueue,\r
+ portTickType xTicksToWait\r
+ );\r
+ * </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSend(). It is included for\r
+ * backward compatibility with versions of FreeRTOS.org that did not\r
+ * include the xQueueSendToFront() and xQueueSendToBack() macros. It is\r
+ * equivalent to xQueueSendToBack().\r
+ *\r
+ * Post an item on a queue. The item is queued by copy, not by reference.\r
+ * This function must not be called from an interrupt service routine.\r
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0 and the\r
+ * queue is full. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned long ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become\r
+ // available if necessary.\r
+ if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r
+\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueGenericSend(\r
+ xQueueHandle xQueue,\r
+ const void * pvItemToQueue,\r
+ portTickType xTicksToWait\r
+ portBASE_TYPE xCopyPosition\r
+ );\r
+ * </pre>\r
+ *\r
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and\r
+ * xQueueSendToBack() are used in place of calling this function directly.\r
+ *\r
+ * Post an item on a queue. The item is queued by copy, not by reference.\r
+ * This function must not be called from an interrupt service routine.\r
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for space to become available on the queue, should it already\r
+ * be full. The call will return immediately if this is set to 0 and the\r
+ * queue is full. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ *\r
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\r
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item\r
+ * at the front of the queue (for high priority messages).\r
+ *\r
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ unsigned long ulVar = 10UL;\r
+\r
+ void vATask( void *pvParameters )\r
+ {\r
+ xQueueHandle xQueue1, xQueue2;\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 unsigned long values.\r
+ xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+\r
+ // ...\r
+\r
+ if( xQueue1 != 0 )\r
+ {\r
+ // Send an unsigned long. Wait for 10 ticks for space to become\r
+ // available if necessary.\r
+ if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10, queueSEND_TO_BACK ) != pdPASS )\r
+ {\r
+ // Failed to post the message, even after 10 ticks.\r
+ }\r
+ }\r
+\r
+ if( xQueue2 != 0 )\r
+ {\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0, queueSEND_TO_BACK );\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueSend xQueueSend\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueuePeek(\r
+ xQueueHandle xQueue,\r
+ void *pvBuffer,\r
+ portTickType xTicksToWait\r
+ );</pre>\r
+ *\r
+ * This is a macro that calls the xQueueGenericReceive() function.\r
+ *\r
+ * Receive an item from a queue without removing the item from the queue.\r
+ * The item is received by copy so a buffer of adequate size must be\r
+ * provided. The number of bytes copied into the buffer was defined when\r
+ * the queue was created.\r
+ *\r
+ * Successfully received items remain on the queue so will be returned again\r
+ * by the next call, or a call to xQueueReceive().\r
+ *\r
+ * This macro must not be used in an interrupt service routine.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for an item to receive should the queue be empty at the time\r
+ * of the call. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue\r
+ * is empty.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ xQueueHandle xQueue;\r
+\r
+ // Task to create a queue and post a value.\r
+ void vATask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+\r
+ // ... Rest of task code.\r
+ }\r
+\r
+ // Task to peek the data from the queue.\r
+ void vADifferentTask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxRxedMessage;\r
+\r
+ if( xQueue != 0 )\r
+ {\r
+ // Peek a message on the created queue. Block for 10 ticks if a\r
+ // message is not immediately available.\r
+ if( xQueuePeek( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )\r
+ {\r
+ // pcRxedMessage now points to the struct AMessage variable posted\r
+ // by vATask, but the item still remains on the queue.\r
+ }\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceive xQueueReceive\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueReceive(\r
+ xQueueHandle xQueue,\r
+ void *pvBuffer,\r
+ portTickType xTicksToWait\r
+ );</pre>\r
+ *\r
+ * This is a macro that calls the xQueueGenericReceive() function.\r
+ *\r
+ * Receive an item from a queue. The item is received by copy so a buffer of\r
+ * adequate size must be provided. The number of bytes copied into the buffer\r
+ * was defined when the queue was created.\r
+ *\r
+ * Successfully received items are removed from the queue.\r
+ *\r
+ * This function must not be used in an interrupt service routine. See\r
+ * xQueueReceiveFromISR for an alternative that can.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for an item to receive should the queue be empty at the time\r
+ * of the call. xQueueReceive() will return immediately if xTicksToWait\r
+ * is zero and the queue is empty. The time is defined in tick periods so the\r
+ * constant portTICK_RATE_MS should be used to convert to real time if this is\r
+ * required.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ xQueueHandle xQueue;\r
+\r
+ // Task to create a queue and post a value.\r
+ void vATask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+\r
+ // ... Rest of task code.\r
+ }\r
+\r
+ // Task to receive from the queue.\r
+ void vADifferentTask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxRxedMessage;\r
+\r
+ if( xQueue != 0 )\r
+ {\r
+ // Receive a message on the created queue. Block for 10 ticks if a\r
+ // message is not immediately available.\r
+ if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )\r
+ {\r
+ // pcRxedMessage now points to the struct AMessage variable posted\r
+ // by vATask.\r
+ }\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceive xQueueReceive\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )\r
+\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueGenericReceive(\r
+ xQueueHandle xQueue,\r
+ void *pvBuffer,\r
+ portTickType xTicksToWait\r
+ portBASE_TYPE xJustPeek\r
+ );</pre>\r
+ *\r
+ * It is preferred that the macro xQueueReceive() be used rather than calling\r
+ * this function directly.\r
+ *\r
+ * Receive an item from a queue. The item is received by copy so a buffer of\r
+ * adequate size must be provided. The number of bytes copied into the buffer\r
+ * was defined when the queue was created.\r
+ *\r
+ * This function must not be used in an interrupt service routine. See\r
+ * xQueueReceiveFromISR for an alternative that can.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time the task should block\r
+ * waiting for an item to receive should the queue be empty at the time\r
+ * of the call. The time is defined in tick periods so the constant\r
+ * portTICK_RATE_MS should be used to convert to real time if this is required.\r
+ * xQueueGenericReceive() will return immediately if the queue is empty and\r
+ * xTicksToWait is 0.\r
+ *\r
+ * @param xJustPeek When set to true, the item received from the queue is not\r
+ * actually removed from the queue - meaning a subsequent call to\r
+ * xQueueReceive() will return the same item. When set to false, the item\r
+ * being received from the queue is also removed from the queue.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ struct AMessage\r
+ {\r
+ char ucMessageID;\r
+ char ucData[ 20 ];\r
+ } xMessage;\r
+\r
+ xQueueHandle xQueue;\r
+\r
+ // Task to create a queue and post a value.\r
+ void vATask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxMessage;\r
+\r
+ // Create a queue capable of containing 10 pointers to AMessage structures.\r
+ // These should be passed by pointer as they contain a lot of data.\r
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Send a pointer to a struct AMessage object. Don't block if the\r
+ // queue is already full.\r
+ pxMessage = & xMessage;\r
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );\r
+\r
+ // ... Rest of task code.\r
+ }\r
+\r
+ // Task to receive from the queue.\r
+ void vADifferentTask( void *pvParameters )\r
+ {\r
+ struct AMessage *pxRxedMessage;\r
+\r
+ if( xQueue != 0 )\r
+ {\r
+ // Receive a message on the created queue. Block for 10 ticks if a\r
+ // message is not immediately available.\r
+ if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )\r
+ {\r
+ // pcRxedMessage now points to the struct AMessage variable posted\r
+ // by vATask.\r
+ }\r
+ }\r
+\r
+ // ... Rest of task code.\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceive xQueueReceive\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueGenericReceive( xQueueHandle xQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeek );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue );</pre>\r
+ *\r
+ * Return the number of messages stored in a queue.\r
+ *\r
+ * @param xQueue A handle to the queue being queried.\r
+ *\r
+ * @return The number of messages available in the queue.\r
+ *\r
+ * \page uxQueueMessagesWaiting uxQueueMessagesWaiting\r
+ * \ingroup QueueManagement\r
+ */\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>void vQueueDelete( xQueueHandle xQueue );</pre>\r
+ *\r
+ * Delete a queue - freeing all the memory allocated for storing of items\r
+ * placed on the queue.\r
+ *\r
+ * @param xQueue A handle to the queue to be deleted.\r
+ *\r
+ * \page vQueueDelete vQueueDelete\r
+ * \ingroup QueueManagement\r
+ */\r
+void vQueueDelete( xQueueHandle pxQueue );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendToFrontFromISR(\r
+ xQueueHandle pxQueue,\r
+ const void *pvItemToQueue,\r
+ portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ );\r
+ </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSendFromISR().\r
+ *\r
+ * Post an item to the front of a queue. It is safe to use this macro from\r
+ * within an interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise\r
+ * errQUEUE_FULL.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ char cIn;\r
+ portBASE_TYPE xHigherPrioritTaskWoken;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r
+\r
+ // Post the byte.\r
+ xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary.\r
+ if( xHigherPriorityTaskWoken )\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendToFrontFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )\r
+\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendToBackFromISR(\r
+ xQueueHandle pxQueue,\r
+ const void *pvItemToQueue,\r
+ portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ );\r
+ </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSendFromISR().\r
+ *\r
+ * Post an item to the back of a queue. It is safe to use this macro from\r
+ * within an interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise\r
+ * errQUEUE_FULL.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ char cIn;\r
+ portBASE_TYPE xHigherPriorityTaskWoken;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r
+\r
+ // Post the byte.\r
+ xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary.\r
+ if( xHigherPriorityTaskWoken )\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendToBackFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueSendFromISR(\r
+ xQueueHandle pxQueue,\r
+ const void *pvItemToQueue,\r
+ portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ );\r
+ </pre>\r
+ *\r
+ * This is a macro that calls xQueueGenericSendFromISR(). It is included\r
+ * for backward compatibility with versions of FreeRTOS.org that did not\r
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()\r
+ * macros.\r
+ *\r
+ * Post an item to the back of a queue. It is safe to use this function from\r
+ * within an interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xQueueSendFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise\r
+ * errQUEUE_FULL.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ char cIn;\r
+ portBASE_TYPE xHigherPriorityTaskWoken;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ xHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r
+\r
+ // Post the byte.\r
+ xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary.\r
+ if( xHigherPriorityTaskWoken )\r
+ {\r
+ // Actual macro used here is port specific.\r
+ taskYIELD_FROM_ISR ();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+#define xQueueSendFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueGenericSendFromISR(\r
+ xQueueHandle pxQueue,\r
+ const void *pvItemToQueue,\r
+ portBASE_TYPE *pxHigherPriorityTaskWoken,\r
+ portBASE_TYPE xCopyPosition\r
+ );\r
+ </pre>\r
+ *\r
+ * It is preferred that the macros xQueueSendFromISR(),\r
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place\r
+ * of calling this function directly.\r
+ *\r
+ * Post an item on a queue. It is safe to use this function from within an\r
+ * interrupt service routine.\r
+ *\r
+ * Items are queued by copy not reference so it is preferable to only\r
+ * queue small items, especially when called from an ISR. In most cases\r
+ * it would be preferable to store a pointer to the item being queued.\r
+ *\r
+ * @param xQueue The handle to the queue on which the item is to be posted.\r
+ *\r
+ * @param pvItemToQueue A pointer to the item that is to be placed on the\r
+ * queue. The size of the items the queue will hold was defined when the\r
+ * queue was created, so this many bytes will be copied from pvItemToQueue\r
+ * into the queue storage area.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\r
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item\r
+ * at the front of the queue (for high priority messages).\r
+ *\r
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise\r
+ * errQUEUE_FULL.\r
+ *\r
+ * Example usage for buffered IO (where the ISR can obtain more than one value\r
+ * per call):\r
+ <pre>\r
+ void vBufferISR( void )\r
+ {\r
+ char cIn;\r
+ portBASE_TYPE xHigherPriorityTaskWokenByPost;\r
+\r
+ // We have not woken a task at the start of the ISR.\r
+ xHigherPriorityTaskWokenByPost = pdFALSE;\r
+\r
+ // Loop until the buffer is empty.\r
+ do\r
+ {\r
+ // Obtain a byte from the buffer.\r
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\r
+\r
+ // Post each byte.\r
+ xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );\r
+\r
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );\r
+\r
+ // Now the buffer is empty we can switch context if necessary. Note that the\r
+ // name of the yield function required is port specific.\r
+ if( xHigherPriorityTaskWokenByPost )\r
+ {\r
+ taskYIELD_YIELD_FROM_ISR();\r
+ }\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup xQueueSendFromISR xQueueSendFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition );\r
+\r
+/**\r
+ * queue. h\r
+ * <pre>\r
+ portBASE_TYPE xQueueReceiveFromISR(\r
+ xQueueHandle pxQueue,\r
+ void *pvBuffer,\r
+ portBASE_TYPE *pxTaskWoken\r
+ );\r
+ * </pre>\r
+ *\r
+ * Receive an item from a queue. It is safe to use this function from within an\r
+ * interrupt service routine.\r
+ *\r
+ * @param pxQueue The handle to the queue from which the item is to be\r
+ * received.\r
+ *\r
+ * @param pvBuffer Pointer to the buffer into which the received item will\r
+ * be copied.\r
+ *\r
+ * @param pxTaskWoken A task may be blocked waiting for space to become\r
+ * available on the queue. If xQueueReceiveFromISR causes such a task to\r
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will\r
+ * remain unchanged.\r
+ *\r
+ * @return pdTRUE if an item was successfully received from the queue,\r
+ * otherwise pdFALSE.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+\r
+ xQueueHandle xQueue;\r
+\r
+ // Function to create a queue and post some values.\r
+ void vAFunction( void *pvParameters )\r
+ {\r
+ char cValueToPost;\r
+ const portTickType xBlockTime = ( portTickType )0xff;\r
+\r
+ // Create a queue capable of containing 10 characters.\r
+ xQueue = xQueueCreate( 10, sizeof( char ) );\r
+ if( xQueue == 0 )\r
+ {\r
+ // Failed to create the queue.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Post some characters that will be used within an ISR. If the queue\r
+ // is full then this task will block for xBlockTime ticks.\r
+ cValueToPost = 'a';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+ cValueToPost = 'b';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+\r
+ // ... keep posting characters ... this task may block when the queue\r
+ // becomes full.\r
+\r
+ cValueToPost = 'c';\r
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );\r
+ }\r
+\r
+ // ISR that outputs all the characters received on the queue.\r
+ void vISR_Routine( void )\r
+ {\r
+ portBASE_TYPE xTaskWokenByReceive = pdFALSE;\r
+ char cRxedChar;\r
+\r
+ while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )\r
+ {\r
+ // A character was received. Output the character now.\r
+ vOutputCharacter( cRxedChar );\r
+\r
+ // If removing the character from the queue woke the task that was\r
+ // posting onto the queue cTaskWokenByReceive will have been set to\r
+ // pdTRUE. No matter how many times this loop iterates only one\r
+ // task will be woken.\r
+ }\r
+\r
+ if( cTaskWokenByPost != ( char ) pdFALSE;\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR\r
+ * \ingroup QueueManagement\r
+ */\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken );\r
+\r
+/*\r
+ * Utilities to query queue that are safe to use from an ISR. These utilities\r
+ * should be used only from witin an ISR, or within a critical section.\r
+ */\r
+signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue );\r
+signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue );\r
+unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue );\r
+\r
+\r
+/*\r
+ * xQueueAltGenericSend() is an alternative version of xQueueGenericSend().\r
+ * Likewise xQueueAltGenericReceive() is an alternative version of\r
+ * xQueueGenericReceive().\r
+ *\r
+ * The source code that implements the alternative (Alt) API is much\r
+ * simpler because it executes everything from within a critical section.\r
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the\r
+ * preferred fully featured API too. The fully featured API has more\r
+ * complex code that takes longer to execute, but makes much less use of\r
+ * critical sections. Therefore the alternative API sacrifices interrupt\r
+ * responsiveness to gain execution speed, whereas the fully featured API\r
+ * sacrifices execution speed to ensure better interrupt responsiveness.\r
+ */\r
+signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
+signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
+#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\r
+#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\r
+#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )\r
+#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )\r
+\r
+/*\r
+ * The functions defined above are for passing data to and from tasks. The\r
+ * functions below are the equivalents for passing data to and from\r
+ * co-routines.\r
+ *\r
+ * These functions are called from the co-routine macro implementation and\r
+ * should not be called directly from application code. Instead use the macro\r
+ * wrappers defined within croutine.h.\r
+ */\r
+signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken );\r
+signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken );\r
+signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait );\r
+signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait );\r
+\r
+/*\r
+ * For internal use only. Use xSemaphoreCreateMutex() or\r
+ * xSemaphoreCreateCounting() instead of calling these functions directly.\r
+ */\r
+xQueueHandle xQueueCreateMutex( void );\r
+xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount );\r
+\r
+/*\r
+ * For internal use only. Use xSemaphoreTakeMutexRecursive() or\r
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.\r
+ */\r
+portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle pxMutex, portTickType xBlockTime );\r
+portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle pxMutex );\r
+\r
+/*\r
+ * The registry is provided as a means for kernel aware debuggers to\r
+ * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add\r
+ * a queue, semaphore or mutex handle to the registry if you want the handle\r
+ * to be available to a kernel aware debugger. If you are not using a kernel\r
+ * aware debugger then this function can be ignored.\r
+ *\r
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the\r
+ * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0\r
+ * within FreeRTOSConfig.h for the registry to be available. Its value\r
+ * does not effect the number of queues, semaphores and mutexes that can be\r
+ * created - just the number that the registry can hold.\r
+ *\r
+ * @param xQueue The handle of the queue being added to the registry. This\r
+ * is the handle returned by a call to xQueueCreate(). Semaphore and mutex\r
+ * handles can also be passed in here.\r
+ *\r
+ * @param pcName The name to be associated with the handle. This is the\r
+ * name that the kernel aware debugger will display.\r
+ */\r
+#if configQUEUE_REGISTRY_SIZE > 0U\r
+ void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName );\r
+#endif\r
+\r
+/* Not a public API function, hence the 'Restricted' in the name. */\r
+void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait );\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* QUEUE_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#ifndef SEMAPHORE_H\r
+#define SEMAPHORE_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "#include FreeRTOS.h" must appear in source files before "#include semphr.h"\r
+#endif\r
+\r
+#include "os_queue.h"\r
+\r
+typedef xQueueHandle xSemaphoreHandle;\r
+\r
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned char ) 1U )\r
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned char ) 0U )\r
+#define semGIVE_BLOCK_TIME ( ( portTickType ) 0U )\r
+\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )</pre>\r
+ *\r
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.\r
+ * The queue length is 1 as this is a binary semaphore. The data size is 0\r
+ * as we don't want to actually store any data - we just want to know if the\r
+ * queue is empty or full.\r
+ *\r
+ * This type of semaphore can be used for pure synchronisation between tasks or\r
+ * between an interrupt and a task. The semaphore need not be given back once\r
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while\r
+ * another continuously 'takes' the semaphore. For this reason this type of\r
+ * semaphore does not use a priority inheritance mechanism. For an alternative\r
+ * that does use priority inheritance see xSemaphoreCreateMutex().\r
+ *\r
+ * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().\r
+ // This is a macro so pass the variable in directly.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary\r
+ * \ingroup Semaphores\r
+ */\r
+#define vSemaphoreCreateBinary( xSemaphore ) { \\r
+ ( xSemaphore ) = xQueueCreate( ( unsigned portBASE_TYPE ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \\r
+ if( ( xSemaphore ) != NULL ) \\r
+ { \\r
+ xSemaphoreGive( ( xSemaphore ) ); \\r
+ } \\r
+ }\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreTake( \r
+ * xSemaphoreHandle xSemaphore, \r
+ * portTickType xBlockTime \r
+ * )</pre>\r
+ *\r
+ * <i>Macro</i> to obtain a semaphore. The semaphore must have previously been\r
+ * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\r
+ * xSemaphoreCreateCounting().\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being taken - obtained when\r
+ * the semaphore was created.\r
+ *\r
+ * @param xBlockTime The time in ticks to wait for the semaphore to become\r
+ * available. The macro portTICK_RATE_MS can be used to convert this to a\r
+ * real time. A block time of zero can be used to poll the semaphore. A block\r
+ * time of portMAX_DELAY can be used to block indefinitely (provided\r
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).\r
+ *\r
+ * @return pdTRUE if the semaphore was obtained. pdFALSE\r
+ * if xBlockTime expired without the semaphore becoming available.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ // A task that creates a semaphore.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the semaphore to guard a shared resource.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+ }\r
+\r
+ // A task that uses the semaphore.\r
+ void vAnotherTask( void * pvParameters )\r
+ {\r
+ // ... Do other things.\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // See if we can obtain the semaphore. If the semaphore is not available\r
+ // wait 10 ticks to see if it becomes free. \r
+ if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )\r
+ {\r
+ // We were able to obtain the semaphore and can now access the\r
+ // shared resource.\r
+\r
+ // ...\r
+\r
+ // We have finished accessing the shared resource. Release the \r
+ // semaphore.\r
+ xSemaphoreGive( xSemaphore );\r
+ }\r
+ else\r
+ {\r
+ // We could not obtain the semaphore and can therefore not access\r
+ // the shared resource safely.\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreTake xSemaphoreTake\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueGenericReceive( ( xQueueHandle ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )\r
+\r
+/**\r
+ * semphr. h\r
+ * xSemaphoreTakeRecursive( \r
+ * xSemaphoreHandle xMutex, \r
+ * portTickType xBlockTime \r
+ * )\r
+ *\r
+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore. \r
+ * The mutex must have previously been created using a call to \r
+ * xSemaphoreCreateRecursiveMutex();\r
+ * \r
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\r
+ * macro to be available.\r
+ * \r
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\r
+ *\r
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex \r
+ * doesn't become available again until the owner has called \r
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example, \r
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will \r
+ * not be available to any other task until it has also 'given' the mutex back\r
+ * exactly five times.\r
+ *\r
+ * @param xMutex A handle to the mutex being obtained. This is the\r
+ * handle returned by xSemaphoreCreateRecursiveMutex();\r
+ *\r
+ * @param xBlockTime The time in ticks to wait for the semaphore to become\r
+ * available. The macro portTICK_RATE_MS can be used to convert this to a\r
+ * real time. A block time of zero can be used to poll the semaphore. If\r
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will\r
+ * return immediately no matter what the value of xBlockTime. \r
+ *\r
+ * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime\r
+ * expired without the semaphore becoming available.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xMutex = NULL;\r
+\r
+ // A task that creates a mutex.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the mutex to guard a shared resource.\r
+ xMutex = xSemaphoreCreateRecursiveMutex();\r
+ }\r
+\r
+ // A task that uses the mutex.\r
+ void vAnotherTask( void * pvParameters )\r
+ {\r
+ // ... Do other things.\r
+\r
+ if( xMutex != NULL )\r
+ {\r
+ // See if we can obtain the mutex. If the mutex is not available\r
+ // wait 10 ticks to see if it becomes free. \r
+ if( xSemaphoreTakeRecursive( xSemaphore, ( portTickType ) 10 ) == pdTRUE )\r
+ {\r
+ // We were able to obtain the mutex and can now access the\r
+ // shared resource.\r
+\r
+ // ...\r
+ // For some reason due to the nature of the code further calls to \r
+ // xSemaphoreTakeRecursive() are made on the same mutex. In real\r
+ // code these would not be just sequential calls as this would make\r
+ // no sense. Instead the calls are likely to be buried inside\r
+ // a more complex call structure.\r
+ xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );\r
+ xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );\r
+\r
+ // The mutex has now been 'taken' three times, so will not be \r
+ // available to another task until it has also been given back\r
+ // three times. Again it is unlikely that real code would have\r
+ // these calls sequentially, but instead buried in a more complex\r
+ // call structure. This is just for illustrative purposes.\r
+ xSemaphoreGiveRecursive( xMutex );\r
+ xSemaphoreGiveRecursive( xMutex );\r
+ xSemaphoreGiveRecursive( xMutex );\r
+\r
+ // Now the mutex can be taken by other tasks.\r
+ }\r
+ else\r
+ {\r
+ // We could not obtain the mutex and can therefore not access\r
+ // the shared resource safely.\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )\r
+\r
+\r
+/* \r
+ * xSemaphoreAltTake() is an alternative version of xSemaphoreTake().\r
+ *\r
+ * The source code that implements the alternative (Alt) API is much \r
+ * simpler because it executes everything from within a critical section. \r
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the \r
+ * preferred fully featured API too. The fully featured API has more \r
+ * complex code that takes longer to execute, but makes much less use of \r
+ * critical sections. Therefore the alternative API sacrifices interrupt \r
+ * responsiveness to gain execution speed, whereas the fully featured API\r
+ * sacrifices execution speed to ensure better interrupt responsiveness.\r
+ */\r
+#define xSemaphoreAltTake( xSemaphore, xBlockTime ) xQueueAltGenericReceive( ( xQueueHandle ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreGive( xSemaphoreHandle xSemaphore )</pre>\r
+ *\r
+ * <i>Macro</i> to release a semaphore. The semaphore must have previously been\r
+ * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\r
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().\r
+ *\r
+ * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for\r
+ * an alternative which can be used from an ISR.\r
+ *\r
+ * This macro must also not be used on semaphores created using \r
+ * xSemaphoreCreateRecursiveMutex().\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being released. This is the\r
+ * handle returned when the semaphore was created.\r
+ *\r
+ * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred.\r
+ * Semaphores are implemented using queues. An error can occur if there is\r
+ * no space on the queue to post a message - indicating that the \r
+ * semaphore was not first obtained correctly.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the semaphore to guard a shared resource.\r
+ vSemaphoreCreateBinary( xSemaphore );\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )\r
+ {\r
+ // We would expect this call to fail because we cannot give\r
+ // a semaphore without first "taking" it!\r
+ }\r
+\r
+ // Obtain the semaphore - don't block if the semaphore is not\r
+ // immediately available.\r
+ if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )\r
+ {\r
+ // We now have the semaphore and can access the shared resource.\r
+\r
+ // ...\r
+\r
+ // We have finished accessing the shared resource so can free the\r
+ // semaphore.\r
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )\r
+ {\r
+ // We would not expect this call to fail because we must have\r
+ // obtained the semaphore to get here.\r
+ }\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreGive xSemaphoreGive\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( xQueueHandle ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreGiveRecursive( xSemaphoreHandle xMutex )</pre>\r
+ *\r
+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.\r
+ * The mutex must have previously been created using a call to \r
+ * xSemaphoreCreateRecursiveMutex();\r
+ * \r
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\r
+ * macro to be available.\r
+ *\r
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\r
+ * \r
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex \r
+ * doesn't become available again until the owner has called \r
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example, \r
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will \r
+ * not be available to any other task until it has also 'given' the mutex back\r
+ * exactly five times.\r
+ *\r
+ * @param xMutex A handle to the mutex being released, or 'given'. This is the\r
+ * handle returned by xSemaphoreCreateMutex();\r
+ *\r
+ * @return pdTRUE if the semaphore was given.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xMutex = NULL;\r
+\r
+ // A task that creates a mutex.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Create the mutex to guard a shared resource.\r
+ xMutex = xSemaphoreCreateRecursiveMutex();\r
+ }\r
+\r
+ // A task that uses the mutex.\r
+ void vAnotherTask( void * pvParameters )\r
+ {\r
+ // ... Do other things.\r
+\r
+ if( xMutex != NULL )\r
+ {\r
+ // See if we can obtain the mutex. If the mutex is not available\r
+ // wait 10 ticks to see if it becomes free. \r
+ if( xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ) == pdTRUE )\r
+ {\r
+ // We were able to obtain the mutex and can now access the\r
+ // shared resource.\r
+\r
+ // ...\r
+ // For some reason due to the nature of the code further calls to \r
+ // xSemaphoreTakeRecursive() are made on the same mutex. In real\r
+ // code these would not be just sequential calls as this would make\r
+ // no sense. Instead the calls are likely to be buried inside\r
+ // a more complex call structure.\r
+ xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );\r
+ xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );\r
+\r
+ // The mutex has now been 'taken' three times, so will not be \r
+ // available to another task until it has also been given back\r
+ // three times. Again it is unlikely that real code would have\r
+ // these calls sequentially, it would be more likely that the calls\r
+ // to xSemaphoreGiveRecursive() would be called as a call stack\r
+ // unwound. This is just for demonstrative purposes.\r
+ xSemaphoreGiveRecursive( xMutex );\r
+ xSemaphoreGiveRecursive( xMutex );\r
+ xSemaphoreGiveRecursive( xMutex );\r
+\r
+ // Now the mutex can be taken by other tasks.\r
+ }\r
+ else\r
+ {\r
+ // We could not obtain the mutex and can therefore not access\r
+ // the shared resource safely.\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) )\r
+\r
+/* \r
+ * xSemaphoreAltGive() is an alternative version of xSemaphoreGive().\r
+ *\r
+ * The source code that implements the alternative (Alt) API is much \r
+ * simpler because it executes everything from within a critical section. \r
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the \r
+ * preferred fully featured API too. The fully featured API has more \r
+ * complex code that takes longer to execute, but makes much less use of \r
+ * critical sections. Therefore the alternative API sacrifices interrupt \r
+ * responsiveness to gain execution speed, whereas the fully featured API\r
+ * sacrifices execution speed to ensure better interrupt responsiveness.\r
+ */\r
+#define xSemaphoreAltGive( xSemaphore ) xQueueAltGenericSend( ( xQueueHandle ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>\r
+ xSemaphoreGiveFromISR( \r
+ xSemaphoreHandle xSemaphore, \r
+ signed portBASE_TYPE *pxHigherPriorityTaskWoken\r
+ )</pre>\r
+ *\r
+ * <i>Macro</i> to release a semaphore. The semaphore must have previously been\r
+ * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting().\r
+ *\r
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\r
+ * must not be used with this macro.\r
+ *\r
+ * This macro can be used from an ISR.\r
+ *\r
+ * @param xSemaphore A handle to the semaphore being released. This is the\r
+ * handle returned when the semaphore was created.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set\r
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task\r
+ * to unblock, and the unblocked task has a priority higher than the currently\r
+ * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then\r
+ * a context switch should be requested before the interrupt is exited.\r
+ *\r
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ \#define LONG_TIME 0xffff\r
+ \#define TICKS_TO_WAIT 10\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ // Repetitive task.\r
+ void vATask( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // We want this task to run every 10 ticks of a timer. The semaphore \r
+ // was created before this task was started.\r
+\r
+ // Block waiting for the semaphore to become available.\r
+ if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )\r
+ {\r
+ // It is time to execute.\r
+\r
+ // ...\r
+\r
+ // We have finished our task. Return to the top of the loop where\r
+ // we will block on the semaphore until it is time to execute \r
+ // again. Note when using the semaphore for synchronisation with an\r
+ // ISR in this manner there is no need to 'give' the semaphore back.\r
+ }\r
+ }\r
+ }\r
+\r
+ // Timer ISR\r
+ void vTimerISR( void * pvParameters )\r
+ {\r
+ static unsigned char ucLocalTickCount = 0;\r
+ static signed portBASE_TYPE xHigherPriorityTaskWoken;\r
+\r
+ // A timer tick has occurred.\r
+\r
+ // ... Do other time functions.\r
+\r
+ // Is it time for vATask () to run?\r
+ xHigherPriorityTaskWoken = pdFALSE;\r
+ ucLocalTickCount++;\r
+ if( ucLocalTickCount >= TICKS_TO_WAIT )\r
+ {\r
+ // Unblock the task by releasing the semaphore.\r
+ xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );\r
+\r
+ // Reset the count so we release the semaphore again in 10 ticks time.\r
+ ucLocalTickCount = 0;\r
+ }\r
+\r
+ if( xHigherPriorityTaskWoken != pdFALSE )\r
+ {\r
+ // We can force a context switch here. Context switching from an\r
+ // ISR uses port specific syntax. Check the demo task for your port\r
+ // to find the syntax required.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueueHandle ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreHandle xSemaphoreCreateMutex( void )</pre>\r
+ *\r
+ * <i>Macro</i> that implements a mutex semaphore by using the existing queue \r
+ * mechanism.\r
+ *\r
+ * Mutexes created using this macro can be accessed using the xSemaphoreTake()\r
+ * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and \r
+ * xSemaphoreGiveRecursive() macros should not be used.\r
+ * \r
+ * This type of semaphore uses a priority inheritance mechanism so a task \r
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the \r
+ * semaphore it is no longer required. \r
+ *\r
+ * Mutex type semaphores cannot be used from within interrupt service routines. \r
+ *\r
+ * See vSemaphoreCreateBinary() for an alternative implementation that can be \r
+ * used for pure synchronisation (where one task or interrupt always 'gives' the \r
+ * semaphore and another always 'takes' the semaphore) and from within interrupt \r
+ * service routines.\r
+ *\r
+ * @return xSemaphore Handle to the created mutex semaphore. Should be of type \r
+ * xSemaphoreHandle.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\r
+ // This is a macro so pass the variable in directly.\r
+ xSemaphore = xSemaphoreCreateMutex();\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreCreateMutex() xQueueCreateMutex()\r
+\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreHandle xSemaphoreCreateRecursiveMutex( void )</pre>\r
+ *\r
+ * <i>Macro</i> that implements a recursive mutex by using the existing queue \r
+ * mechanism.\r
+ *\r
+ * Mutexes created using this macro can be accessed using the \r
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The \r
+ * xSemaphoreTake() and xSemaphoreGive() macros should not be used.\r
+ *\r
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex \r
+ * doesn't become available again until the owner has called \r
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example, \r
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will \r
+ * not be available to any other task until it has also 'given' the mutex back\r
+ * exactly five times.\r
+ * \r
+ * This type of semaphore uses a priority inheritance mechanism so a task \r
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the \r
+ * semaphore it is no longer required. \r
+ *\r
+ * Mutex type semaphores cannot be used from within interrupt service routines. \r
+ *\r
+ * See vSemaphoreCreateBinary() for an alternative implementation that can be \r
+ * used for pure synchronisation (where one task or interrupt always 'gives' the \r
+ * semaphore and another always 'takes' the semaphore) and from within interrupt \r
+ * service routines.\r
+ *\r
+ * @return xSemaphore Handle to the created mutex semaphore. Should be of type \r
+ * xSemaphoreHandle.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\r
+ // This is a macro so pass the variable in directly.\r
+ xSemaphore = xSemaphoreCreateRecursiveMutex();\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex()\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>xSemaphoreHandle xSemaphoreCreateCounting( unsigned portBASE_TYPE uxMaxCount, unsigned portBASE_TYPE uxInitialCount )</pre>\r
+ *\r
+ * <i>Macro</i> that creates a counting semaphore by using the existing \r
+ * queue mechanism. \r
+ *\r
+ * Counting semaphores are typically used for two things:\r
+ *\r
+ * 1) Counting events. \r
+ *\r
+ * In this usage scenario an event handler will 'give' a semaphore each time\r
+ * an event occurs (incrementing the semaphore count value), and a handler \r
+ * task will 'take' a semaphore each time it processes an event \r
+ * (decrementing the semaphore count value). The count value is therefore \r
+ * the difference between the number of events that have occurred and the \r
+ * number that have been processed. In this case it is desirable for the \r
+ * initial count value to be zero.\r
+ *\r
+ * 2) Resource management.\r
+ *\r
+ * In this usage scenario the count value indicates the number of resources\r
+ * available. To obtain control of a resource a task must first obtain a \r
+ * semaphore - decrementing the semaphore count value. When the count value\r
+ * reaches zero there are no free resources. When a task finishes with the\r
+ * resource it 'gives' the semaphore back - incrementing the semaphore count\r
+ * value. In this case it is desirable for the initial count value to be\r
+ * equal to the maximum count value, indicating that all resources are free.\r
+ *\r
+ * @param uxMaxCount The maximum count value that can be reached. When the \r
+ * semaphore reaches this value it can no longer be 'given'.\r
+ *\r
+ * @param uxInitialCount The count value assigned to the semaphore when it is\r
+ * created.\r
+ *\r
+ * @return Handle to the created semaphore. Null if the semaphore could not be\r
+ * created.\r
+ * \r
+ * Example usage:\r
+ <pre>\r
+ xSemaphoreHandle xSemaphore;\r
+\r
+ void vATask( void * pvParameters )\r
+ {\r
+ xSemaphoreHandle xSemaphore = NULL;\r
+\r
+ // Semaphore cannot be used before a call to xSemaphoreCreateCounting().\r
+ // The max value to which the semaphore can count should be 10, and the\r
+ // initial value assigned to the count should be 0.\r
+ xSemaphore = xSemaphoreCreateCounting( 10, 0 );\r
+\r
+ if( xSemaphore != NULL )\r
+ {\r
+ // The semaphore was created successfully.\r
+ // The semaphore can now be used. \r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting\r
+ * \ingroup Semaphores\r
+ */\r
+#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )\r
+\r
+/**\r
+ * semphr. h\r
+ * <pre>void vSemaphoreDelete( xSemaphoreHandle xSemaphore );</pre>\r
+ *\r
+ * Delete a semaphore. This function must be used with care. For example,\r
+ * do not delete a mutex type semaphore if the mutex is held by a task.\r
+ *\r
+ * @param xSemaphore A handle to the semaphore to be deleted.\r
+ *\r
+ * \page vSemaphoreDelete vSemaphoreDelete\r
+ * \ingroup Semaphores\r
+ */\r
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( xQueueHandle ) xSemaphore )\r
+\r
+#endif /* SEMAPHORE_H */\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef TASK_H\r
+#define TASK_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h must appear in source files before include task.h"\r
+#endif\r
+\r
+#include "os_portable.h"\r
+#include "os_list.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * MACROS AND DEFINITIONS\r
+ *----------------------------------------------------------*/\r
+\r
+#define tskKERNEL_VERSION_NUMBER "V7.0.2"\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Type by which tasks are referenced. For example, a call to xTaskCreate\r
+ * returns (via a pointer parameter) an xTaskHandle variable that can then\r
+ * be used as a parameter to vTaskDelete to delete the task.\r
+ *\r
+ * \page xTaskHandle xTaskHandle\r
+ * \ingroup Tasks\r
+ */\r
+typedef void * xTaskHandle;\r
+\r
+/*\r
+ * Used internally only.\r
+ */\r
+typedef struct xTIME_OUT\r
+{\r
+ portBASE_TYPE xOverflowCount;\r
+ portTickType xTimeOnEntering;\r
+} xTimeOutType;\r
+\r
+/*\r
+ * Defines the memory ranges allocated to the task when an MPU is used.\r
+ */\r
+typedef struct xMEMORY_REGION\r
+{\r
+ void *pvBaseAddress;\r
+ unsigned long ulLengthInBytes;\r
+ unsigned long ulParameters;\r
+} xMemoryRegion;\r
+\r
+/*\r
+ * Parameters required to create an MPU protected task.\r
+ */\r
+typedef struct xTASK_PARAMTERS\r
+{\r
+ pdTASK_CODE pvTaskCode;\r
+ const signed char * const pcName;\r
+ unsigned short usStackDepth;\r
+ void *pvParameters;\r
+ unsigned portBASE_TYPE uxPriority;\r
+ portSTACK_TYPE *puxStackBuffer;\r
+ xMemoryRegion xRegions[ portNUM_CONFIGURABLE_REGIONS ];\r
+} xTaskParameters;\r
+\r
+/*\r
+ * Defines the priority used by the idle task. This must not be modified.\r
+ *\r
+ * \ingroup TaskUtils\r
+ */\r
+#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0U )\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro for forcing a context switch.\r
+ *\r
+ * \page taskYIELD taskYIELD\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskYIELD() portYIELD()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to mark the start of a critical code region. Preemptive context\r
+ * switches cannot occur when in a critical region.\r
+ *\r
+ * NOTE: This may alter the stack (depending on the portable implementation)\r
+ * so must be used with care!\r
+ *\r
+ * \page taskENTER_CRITICAL taskENTER_CRITICAL\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskENTER_CRITICAL() portENTER_CRITICAL()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to mark the end of a critical code region. Preemptive context\r
+ * switches cannot occur when in a critical region.\r
+ *\r
+ * NOTE: This may alter the stack (depending on the portable implementation)\r
+ * so must be used with care!\r
+ *\r
+ * \page taskEXIT_CRITICAL taskEXIT_CRITICAL\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskEXIT_CRITICAL() portEXIT_CRITICAL()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to disable all maskable interrupts.\r
+ *\r
+ * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()\r
+\r
+/**\r
+ * task. h\r
+ *\r
+ * Macro to enable microcontroller interrupts.\r
+ *\r
+ * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS\r
+ * \ingroup SchedulerControl\r
+ */\r
+#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()\r
+\r
+/* Definitions returned by xTaskGetSchedulerState(). */\r
+#define taskSCHEDULER_NOT_STARTED 0\r
+#define taskSCHEDULER_RUNNING 1\r
+#define taskSCHEDULER_SUSPENDED 2\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CREATION API\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ *<pre>\r
+ portBASE_TYPE xTaskCreate(\r
+ pdTASK_CODE pvTaskCode,\r
+ const char * const pcName,\r
+ unsigned short usStackDepth,\r
+ void *pvParameters,\r
+ unsigned portBASE_TYPE uxPriority,\r
+ xTaskHandle *pvCreatedTask\r
+ );</pre>\r
+ *\r
+ * Create a new task and add it to the list of tasks that are ready to run.\r
+ *\r
+ * xTaskCreate() can only be used to create a task that has unrestricted\r
+ * access to the entire microcontroller memory map. Systems that include MPU\r
+ * support can alternatively create an MPU constrained task using\r
+ * xTaskCreateRestricted().\r
+ *\r
+ * @param pvTaskCode Pointer to the task entry function. Tasks\r
+ * must be implemented to never return (i.e. continuous loop).\r
+ *\r
+ * @param pcName A descriptive name for the task. This is mainly used to\r
+ * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default\r
+ * is 16.\r
+ *\r
+ * @param usStackDepth The size of the task stack specified as the number of\r
+ * variables the stack can hold - not the number of bytes. For example, if\r
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes\r
+ * will be allocated for stack storage.\r
+ *\r
+ * @param pvParameters Pointer that will be used as the parameter for the task\r
+ * being created.\r
+ *\r
+ * @param uxPriority The priority at which the task should run. Systems that\r
+ * include MPU support can optionally create tasks in a privileged (system)\r
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For\r
+ * example, to create a privileged task at priority 2 the uxPriority parameter\r
+ * should be set to ( 2 | portPRIVILEGE_BIT ).\r
+ *\r
+ * @param pvCreatedTask Used to pass back a handle by which the created task\r
+ * can be referenced.\r
+ *\r
+ * @return pdPASS if the task was successfully created and added to a ready\r
+ * list, otherwise an error code defined in the file errors. h\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Task to be created.\r
+ void vTaskCode( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+ }\r
+ }\r
+\r
+ // Function that creates a task.\r
+ void vOtherFunction( void )\r
+ {\r
+ static unsigned char ucParameterToPass;\r
+ xTaskHandle xHandle;\r
+\r
+ // Create the task, storing the handle. Note that the passed parameter ucParameterToPass\r
+ // must exist for the lifetime of the task, so in this case is declared static. If it was just an\r
+ // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time\r
+ // the new task attempts to access it.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // Use the handle to delete the task.\r
+ vTaskDelete( xHandle );\r
+ }\r
+ </pre>\r
+ * \defgroup xTaskCreate xTaskCreate\r
+ * \ingroup Tasks\r
+ */\r
+#define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ) )\r
+\r
+/**\r
+ * task. h\r
+ *<pre>\r
+ portBASE_TYPE xTaskCreateRestricted( xTaskParameters *pxTaskDefinition, xTaskHandle *pxCreatedTask );</pre>\r
+ *\r
+ * xTaskCreateRestricted() should only be used in systems that include an MPU\r
+ * implementation.\r
+ *\r
+ * Create a new task and add it to the list of tasks that are ready to run.\r
+ * The function parameters define the memory regions and associated access\r
+ * permissions allocated to the task.\r
+ *\r
+ * @param pxTaskDefinition Pointer to a structure that contains a member\r
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\r
+ * documentation) plus an optional stack buffer and the memory region\r
+ * definitions.\r
+ *\r
+ * @param pxCreatedTask Used to pass back a handle by which the created task\r
+ * can be referenced.\r
+ *\r
+ * @return pdPASS if the task was successfully created and added to a ready\r
+ * list, otherwise an error code defined in the file errors. h\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+// Create an xTaskParameters structure that defines the task to be created.\r
+static const xTaskParameters xCheckTaskParameters =\r
+{\r
+ vATask, // pvTaskCode - the function that implements the task.\r
+ "ATask", // pcName - just a text name for the task to assist debugging.\r
+ 100, // usStackDepth - the stack size DEFINED IN WORDS.\r
+ NULL, // pvParameters - passed into the task function as the function parameters.\r
+ ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\r
+ cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\r
+\r
+ // xRegions - Allocate up to three separate memory regions for access by\r
+ // the task, with appropriate access permissions. Different processors have\r
+ // different memory alignment requirements - refer to the FreeRTOS documentation\r
+ // for full information.\r
+ { \r
+ // Base address Length Parameters\r
+ { cReadWriteArray, 32, portMPU_REGION_READ_WRITE },\r
+ { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY },\r
+ { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE }\r
+ }\r
+};\r
+\r
+int main( void )\r
+{\r
+xTaskHandle xHandle;\r
+\r
+ // Create a task from the const structure defined above. The task handle\r
+ // is requested (the second parameter is not NULL) but in this case just for\r
+ // demonstration purposes as its not actually used.\r
+ xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );\r
+\r
+ // Start the scheduler.\r
+ vTaskStartScheduler();\r
+\r
+ // Will only get here if there was insufficient memory to create the idle\r
+ // task.\r
+ for( ;; );\r
+}\r
+ </pre>\r
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted\r
+ * \ingroup Tasks\r
+ */\r
+#define xTaskCreateRestricted( x, pxCreatedTask ) xTaskGenericCreate( ((x)->pvTaskCode), ((x)->pcName), ((x)->usStackDepth), ((x)->pvParameters), ((x)->uxPriority), (pxCreatedTask), ((x)->puxStackBuffer), ((x)->xRegions) )\r
+\r
+/**\r
+ * task. h\r
+ *<pre>\r
+ void vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const pxRegions );</pre>\r
+ *\r
+ * Memory regions are assigned to a restricted task when the task is created by\r
+ * a call to xTaskCreateRestricted(). These regions can be redefined using\r
+ * vTaskAllocateMPURegions().\r
+ *\r
+ * @param xTask The handle of the task being updated.\r
+ *\r
+ * @param xRegions A pointer to an xMemoryRegion structure that contains the\r
+ * new memory region definitions.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+// Define an array of xMemoryRegion structures that configures an MPU region\r
+// allowing read/write access for 1024 bytes starting at the beginning of the\r
+// ucOneKByte array. The other two of the maximum 3 definable regions are\r
+// unused so set to zero.\r
+static const xMemoryRegion xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =\r
+{ \r
+ // Base address Length Parameters\r
+ { ucOneKByte, 1024, portMPU_REGION_READ_WRITE },\r
+ { 0, 0, 0 },\r
+ { 0, 0, 0 }\r
+};\r
+\r
+void vATask( void *pvParameters )\r
+{\r
+ // This task was created such that it has access to certain regions of\r
+ // memory as defined by the MPU configuration. At some point it is\r
+ // desired that these MPU regions are replaced with that defined in the\r
+ // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions()\r
+ // for this purpose. NULL is used as the task handle to indicate that this\r
+ // function should modify the MPU regions of the calling task.\r
+ vTaskAllocateMPURegions( NULL, xAltRegions );\r
+ \r
+ // Now the task can continue its function, but from this point on can only\r
+ // access its stack and the ucOneKByte array (unless any other statically\r
+ // defined or shared regions have been declared elsewhere).\r
+}\r
+ </pre>\r
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted\r
+ * \ingroup Tasks\r
+ */\r
+void vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const pxRegions ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelete( xTaskHandle pxTask );</pre>\r
+ *\r
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Remove a task from the RTOS real time kernels management. The task being\r
+ * deleted will be removed from all ready, blocked, suspended and event lists.\r
+ *\r
+ * NOTE: The idle task is responsible for freeing the kernel allocated\r
+ * memory from tasks that have been deleted. It is therefore important that\r
+ * the idle task is not starved of microcontroller processing time if your\r
+ * application makes any calls to vTaskDelete (). Memory allocated by the\r
+ * task code is not automatically freed, and should be freed before the task\r
+ * is deleted.\r
+ *\r
+ * See the demo application file death.c for sample code that utilises\r
+ * vTaskDelete ().\r
+ *\r
+ * @param pxTask The handle of the task to be deleted. Passing NULL will\r
+ * cause the calling task to be deleted.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vOtherFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create the task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // Use the handle to delete the task.\r
+ vTaskDelete( xHandle );\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskDelete vTaskDelete\r
+ * \ingroup Tasks\r
+ */\r
+void vTaskDelete( xTaskHandle pxTaskToDelete ) PRIVILEGED_FUNCTION;\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CONTROL API\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelay( portTickType xTicksToDelay );</pre>\r
+ *\r
+ * Delay a task for a given number of ticks. The actual time that the\r
+ * task remains blocked depends on the tick rate. The constant\r
+ * portTICK_RATE_MS can be used to calculate real time from the tick\r
+ * rate - with the resolution of one tick period.\r
+ *\r
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ *\r
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to\r
+ * the time at which vTaskDelay() is called. For example, specifying a block\r
+ * period of 100 ticks will cause the task to unblock 100 ticks after\r
+ * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method\r
+ * of controlling the frequency of a cyclical task as the path taken through the\r
+ * code, as well as other task and interrupt activity, will effect the frequency\r
+ * at which vTaskDelay() gets called and therefore the time at which the task\r
+ * next executes. See vTaskDelayUntil() for an alternative API function designed\r
+ * to facilitate fixed frequency execution. It does this by specifying an\r
+ * absolute time (rather than a relative time) at which the calling task should\r
+ * unblock.\r
+ *\r
+ * @param xTicksToDelay The amount of time, in tick periods, that\r
+ * the calling task should block.\r
+ *\r
+ * Example usage:\r
+\r
+ void vTaskFunction( void * pvParameters )\r
+ {\r
+ void vTaskFunction( void * pvParameters )\r
+ {\r
+ // Block for 500ms.\r
+ const portTickType xDelay = 500 / portTICK_RATE_MS;\r
+\r
+ for( ;; )\r
+ {\r
+ // Simply toggle the LED every 500ms, blocking between each toggle.\r
+ vToggleLED();\r
+ vTaskDelay( xDelay );\r
+ }\r
+ }\r
+\r
+ * \defgroup vTaskDelay vTaskDelay\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskDelay( portTickType xTicksToDelay ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );</pre>\r
+ *\r
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Delay a task until a specified time. This function can be used by cyclical\r
+ * tasks to ensure a constant execution frequency.\r
+ *\r
+ * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will\r
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is\r
+ * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed\r
+ * execution frequency as the time between a task starting to execute and that task\r
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the\r
+ * code between calls, or may get interrupted or preempted a different number of times\r
+ * each time it executes].\r
+ *\r
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function\r
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to\r
+ * unblock.\r
+ *\r
+ * The constant portTICK_RATE_MS can be used to calculate real time from the tick\r
+ * rate - with the resolution of one tick period.\r
+ *\r
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the\r
+ * task was last unblocked. The variable must be initialised with the current time\r
+ * prior to its first use (see the example below). Following this the variable is\r
+ * automatically updated within vTaskDelayUntil ().\r
+ *\r
+ * @param xTimeIncrement The cycle time period. The task will be unblocked at\r
+ * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the\r
+ * same xTimeIncrement parameter value will cause the task to execute with\r
+ * a fixed interface period.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ // Perform an action every 10 ticks.\r
+ void vTaskFunction( void * pvParameters )\r
+ {\r
+ portTickType xLastWakeTime;\r
+ const portTickType xFrequency = 10;\r
+\r
+ // Initialise the xLastWakeTime variable with the current time.\r
+ xLastWakeTime = xTaskGetTickCount ();\r
+ for( ;; )\r
+ {\r
+ // Wait for the next cycle.\r
+ vTaskDelayUntil( &xLastWakeTime, xFrequency );\r
+\r
+ // Perform action here.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskDelayUntil vTaskDelayUntil\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );</pre>\r
+ *\r
+ * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Obtain the priority of any task.\r
+ *\r
+ * @param pxTask Handle of the task to be queried. Passing a NULL\r
+ * handle results in the priority of the calling task being returned.\r
+ *\r
+ * @return The priority of pxTask.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to obtain the priority of the created task.\r
+ // It was created with tskIDLE_PRIORITY, but may have changed\r
+ // it itself.\r
+ if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )\r
+ {\r
+ // The task has changed it's priority.\r
+ }\r
+\r
+ // ...\r
+\r
+ // Is our priority higher than the created task?\r
+ if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )\r
+ {\r
+ // Our priority (obtained using NULL handle) is higher.\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet\r
+ * \ingroup TaskCtrl\r
+ */\r
+unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );</pre>\r
+ *\r
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Set the priority of any task.\r
+ *\r
+ * A context switch will occur before the function returns if the priority\r
+ * being set is higher than the currently executing task.\r
+ *\r
+ * @param pxTask Handle to the task for which the priority is being set.\r
+ * Passing a NULL handle results in the priority of the calling task being set.\r
+ *\r
+ * @param uxNewPriority The priority to which the task will be set.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to raise the priority of the created task.\r
+ vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );\r
+\r
+ // ...\r
+\r
+ // Use a NULL handle to raise our priority to the same value.\r
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskPrioritySet vTaskPrioritySet\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskSuspend( xTaskHandle pxTaskToSuspend );</pre>\r
+ *\r
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Suspend any task. When suspended a task will never get any microcontroller\r
+ * processing time, no matter what its priority.\r
+ *\r
+ * Calls to vTaskSuspend are not accumulative -\r
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one\r
+ * call to vTaskResume () to ready the suspended task.\r
+ *\r
+ * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL\r
+ * handle will cause the calling task to be suspended.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to suspend the created task.\r
+ vTaskSuspend( xHandle );\r
+\r
+ // ...\r
+\r
+ // The created task will not run during this period, unless\r
+ // another task calls vTaskResume( xHandle ).\r
+\r
+ //...\r
+\r
+\r
+ // Suspend ourselves.\r
+ vTaskSuspend( NULL );\r
+\r
+ // We cannot get here unless another task calls vTaskResume\r
+ // with our handle as the parameter.\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskSuspend vTaskSuspend\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskSuspend( xTaskHandle pxTaskToSuspend ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskResume( xTaskHandle pxTaskToResume );</pre>\r
+ *\r
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\r
+ * See the configuration section for more information.\r
+ *\r
+ * Resumes a suspended task.\r
+ *\r
+ * A task that has been suspended by one of more calls to vTaskSuspend ()\r
+ * will be made available for running again by a single call to\r
+ * vTaskResume ().\r
+ *\r
+ * @param pxTaskToResume Handle to the task being readied.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ xTaskHandle xHandle;\r
+\r
+ // Create a task, storing the handle.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\r
+\r
+ // ...\r
+\r
+ // Use the handle to suspend the created task.\r
+ vTaskSuspend( xHandle );\r
+\r
+ // ...\r
+\r
+ // The created task will not run during this period, unless\r
+ // another task calls vTaskResume( xHandle ).\r
+\r
+ //...\r
+\r
+\r
+ // Resume the suspended task ourselves.\r
+ vTaskResume( xHandle );\r
+\r
+ // The created task will once again get microcontroller processing\r
+ // time in accordance with it priority within the system.\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskResume vTaskResume\r
+ * \ingroup TaskCtrl\r
+ */\r
+void vTaskResume( xTaskHandle pxTaskToResume ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void xTaskResumeFromISR( xTaskHandle pxTaskToResume );</pre>\r
+ *\r
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be\r
+ * available. See the configuration section for more information.\r
+ *\r
+ * An implementation of vTaskResume() that can be called from within an ISR.\r
+ *\r
+ * A task that has been suspended by one of more calls to vTaskSuspend ()\r
+ * will be made available for running again by a single call to\r
+ * xTaskResumeFromISR ().\r
+ *\r
+ * @param pxTaskToResume Handle to the task being readied.\r
+ *\r
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR\r
+ * \ingroup TaskCtrl\r
+ */\r
+portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) PRIVILEGED_FUNCTION;\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER CONTROL\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskStartScheduler( void );</pre>\r
+ *\r
+ * Starts the real time kernel tick processing. After calling the kernel\r
+ * has control over which tasks are executed and when. This function\r
+ * does not return until an executing task calls vTaskEndScheduler ().\r
+ *\r
+ * At least one task should be created via a call to xTaskCreate ()\r
+ * before calling vTaskStartScheduler (). The idle task is created\r
+ * automatically when the first application task is created.\r
+ *\r
+ * See the demo application file main.c for an example of creating\r
+ * tasks and starting the kernel.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vAFunction( void )\r
+ {\r
+ // Create at least one task before starting the kernel.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ // Start the real time kernel with preemption.\r
+ vTaskStartScheduler ();\r
+\r
+ // Will not get here unless a task calls vTaskEndScheduler ()\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup vTaskStartScheduler vTaskStartScheduler\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskEndScheduler( void );</pre>\r
+ *\r
+ * Stops the real time kernel tick. All created tasks will be automatically\r
+ * deleted and multitasking (either preemptive or cooperative) will\r
+ * stop. Execution then resumes from the point where vTaskStartScheduler ()\r
+ * was called, as if vTaskStartScheduler () had just returned.\r
+ *\r
+ * See the demo application file main. c in the demo/PC directory for an\r
+ * example that uses vTaskEndScheduler ().\r
+ *\r
+ * vTaskEndScheduler () requires an exit function to be defined within the\r
+ * portable layer (see vPortEndScheduler () in port. c for the PC port). This\r
+ * performs hardware specific operations such as stopping the kernel tick.\r
+ *\r
+ * vTaskEndScheduler () will cause all of the resources allocated by the\r
+ * kernel to be freed - but will not free resources allocated by application\r
+ * tasks.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTaskCode( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // At some point we want to end the real time kernel processing\r
+ // so call ...\r
+ vTaskEndScheduler ();\r
+ }\r
+ }\r
+\r
+ void vAFunction( void )\r
+ {\r
+ // Create at least one task before starting the kernel.\r
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
+\r
+ // Start the real time kernel with preemption.\r
+ vTaskStartScheduler ();\r
+\r
+ // Will only get here when the vTaskCode () task has called\r
+ // vTaskEndScheduler (). When we get here we are back to single task\r
+ // execution.\r
+ }\r
+ </pre>\r
+ *\r
+ * \defgroup vTaskEndScheduler vTaskEndScheduler\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>void vTaskSuspendAll( void );</pre>\r
+ *\r
+ * Suspends all real time kernel activity while keeping interrupts (including the\r
+ * kernel tick) enabled.\r
+ *\r
+ * After calling vTaskSuspendAll () the calling task will continue to execute\r
+ * without risk of being swapped out until a call to xTaskResumeAll () has been\r
+ * made.\r
+ *\r
+ * API functions that have the potential to cause a context switch (for example,\r
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler\r
+ * is suspended.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTask1( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // ...\r
+\r
+ // At some point the task wants to perform a long operation during\r
+ // which it does not want to get swapped out. It cannot use\r
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\r
+ // operation may cause interrupts to be missed - including the\r
+ // ticks.\r
+\r
+ // Prevent the real time kernel swapping out the task.\r
+ vTaskSuspendAll ();\r
+\r
+ // Perform the operation here. There is no need to use critical\r
+ // sections as we have all the microcontroller processing time.\r
+ // During this time interrupts will still operate and the kernel\r
+ // tick count will be maintained.\r
+\r
+ // ...\r
+\r
+ // The operation is complete. Restart the kernel.\r
+ xTaskResumeAll ();\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup vTaskSuspendAll vTaskSuspendAll\r
+ * \ingroup SchedulerControl\r
+ */\r
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>char xTaskResumeAll( void );</pre>\r
+ *\r
+ * Resumes real time kernel activity following a call to vTaskSuspendAll ().\r
+ * After a call to vTaskSuspendAll () the kernel will take control of which\r
+ * task is executing at any time.\r
+ *\r
+ * @return If resuming the scheduler caused a context switch then pdTRUE is\r
+ * returned, otherwise pdFALSE is returned.\r
+ *\r
+ * Example usage:\r
+ <pre>\r
+ void vTask1( void * pvParameters )\r
+ {\r
+ for( ;; )\r
+ {\r
+ // Task code goes here.\r
+\r
+ // ...\r
+\r
+ // At some point the task wants to perform a long operation during\r
+ // which it does not want to get swapped out. It cannot use\r
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\r
+ // operation may cause interrupts to be missed - including the\r
+ // ticks.\r
+\r
+ // Prevent the real time kernel swapping out the task.\r
+ vTaskSuspendAll ();\r
+\r
+ // Perform the operation here. There is no need to use critical\r
+ // sections as we have all the microcontroller processing time.\r
+ // During this time interrupts will still operate and the real\r
+ // time kernel tick count will be maintained.\r
+\r
+ // ...\r
+\r
+ // The operation is complete. Restart the kernel. We want to force\r
+ // a context switch - but there is no point if resuming the scheduler\r
+ // caused a context switch already.\r
+ if( !xTaskResumeAll () )\r
+ {\r
+ taskYIELD ();\r
+ }\r
+ }\r
+ }\r
+ </pre>\r
+ * \defgroup xTaskResumeAll xTaskResumeAll\r
+ * \ingroup SchedulerControl\r
+ */\r
+signed portBASE_TYPE xTaskResumeAll( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <pre>signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask );</pre>\r
+ *\r
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is\r
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask\r
+ * is in any other state.\r
+ *\r
+ */\r
+signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask ) PRIVILEGED_FUNCTION;\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK UTILITIES\r
+ *----------------------------------------------------------*/\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>portTickType xTaskGetTickCount( void );</PRE>\r
+ *\r
+ * @return The count of ticks since vTaskStartScheduler was called.\r
+ *\r
+ * \page xTaskGetTickCount xTaskGetTickCount\r
+ * \ingroup TaskUtils\r
+ */\r
+portTickType xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>portTickType xTaskGetTickCountFromISR( void );</PRE>\r
+ *\r
+ * @return The count of ticks since vTaskStartScheduler was called.\r
+ *\r
+ * This is a version of xTaskGetTickCount() that is safe to be called from an\r
+ * ISR - provided that portTickType is the natural word size of the\r
+ * microcontroller being used or interrupt nesting is either not supported or\r
+ * not being used.\r
+ *\r
+ * \page xTaskGetTickCount xTaskGetTickCount\r
+ * \ingroup TaskUtils\r
+ */\r
+portTickType xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>unsigned short uxTaskGetNumberOfTasks( void );</PRE>\r
+ *\r
+ * @return The number of tasks that the real time kernel is currently managing.\r
+ * This includes all ready, blocked and suspended tasks. A task that\r
+ * has been deleted but not yet freed by the idle task will also be\r
+ * included in the count.\r
+ *\r
+ * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks\r
+ * \ingroup TaskUtils\r
+ */\r
+unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery );</PRE>\r
+ *\r
+ * @return The text (human readable) name of the task referenced by the handle\r
+ * xTaskToQueury. A task can query its own name by either passing in its own\r
+ * handle, or by setting xTaskToQuery to NULL. INCLUDE_pcTaskGetTaskName must be\r
+ * set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available.\r
+ *\r
+ * \page pcTaskGetTaskName pcTaskGetTaskName\r
+ * \ingroup TaskUtils\r
+ */\r
+signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery );\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>\r
+ *\r
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be\r
+ * available. See the configuration section for more information.\r
+ *\r
+ * NOTE: This function will disable interrupts for its duration. It is\r
+ * not intended for normal application runtime use but as a debug aid.\r
+ *\r
+ * Lists all the current tasks, along with their current state and stack\r
+ * usage high water mark.\r
+ *\r
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or\r
+ * suspended ('S').\r
+ *\r
+ * @param pcWriteBuffer A buffer into which the above mentioned details\r
+ * will be written, in ascii form. This buffer is assumed to be large\r
+ * enough to contain the generated report. Approximately 40 bytes per\r
+ * task should be sufficient.\r
+ *\r
+ * \page vTaskList vTaskList\r
+ * \ingroup TaskUtils\r
+ */\r
+void vTaskList( signed char *pcWriteBuffer ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>\r
+ *\r
+ * configGENERATE_RUN_TIME_STATS must be defined as 1 for this function\r
+ * to be available. The application must also then provide definitions\r
+ * for portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and\r
+ * portGET_RUN_TIME_COUNTER_VALUE to configure a peripheral timer/counter\r
+ * and return the timers current count value respectively. The counter\r
+ * should be at least 10 times the frequency of the tick count.\r
+ *\r
+ * NOTE: This function will disable interrupts for its duration. It is\r
+ * not intended for normal application runtime use but as a debug aid.\r
+ *\r
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\r
+ * accumulated execution time being stored for each task. The resolution\r
+ * of the accumulated time value depends on the frequency of the timer\r
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\r
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each\r
+ * task into a buffer, both as an absolute count value and as a percentage\r
+ * of the total system execution time.\r
+ *\r
+ * @param pcWriteBuffer A buffer into which the execution times will be\r
+ * written, in ascii form. This buffer is assumed to be large enough to\r
+ * contain the generated report. Approximately 40 bytes per task should\r
+ * be sufficient.\r
+ *\r
+ * \page vTaskGetRunTimeStats vTaskGetRunTimeStats\r
+ * \ingroup TaskUtils\r
+ */\r
+void vTaskGetRunTimeStats( signed char *pcWriteBuffer ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>void vTaskStartTrace( char * pcBuffer, unsigned portBASE_TYPE uxBufferSize );</PRE>\r
+ *\r
+ * Starts a real time kernel activity trace. The trace logs the identity of\r
+ * which task is running when.\r
+ *\r
+ * The trace file is stored in binary format. A separate DOS utility called\r
+ * convtrce.exe is used to convert this into a tab delimited text file which\r
+ * can be viewed and plotted in a spread sheet.\r
+ *\r
+ * @param pcBuffer The buffer into which the trace will be written.\r
+ *\r
+ * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue\r
+ * until either the buffer in full, or ulTaskEndTrace () is called.\r
+ *\r
+ * \page vTaskStartTrace vTaskStartTrace\r
+ * \ingroup TaskUtils\r
+ */\r
+void vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task. h\r
+ * <PRE>unsigned long ulTaskEndTrace( void );</PRE>\r
+ *\r
+ * Stops a kernel activity trace. See vTaskStartTrace ().\r
+ *\r
+ * @return The number of bytes that have been written into the trace buffer.\r
+ *\r
+ * \page usTaskEndTrace usTaskEndTrace\r
+ * \ingroup TaskUtils\r
+ */\r
+unsigned long ulTaskEndTrace( void ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * task.h\r
+ * <PRE>unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask );</PRE>\r
+ *\r
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for\r
+ * this function to be available.\r
+ *\r
+ * Returns the high water mark of the stack associated with xTask. That is,\r
+ * the minimum free stack space there has been (in words, so on a 32 bit machine\r
+ * a value of 1 means 4 bytes) since the task started. The smaller the returned\r
+ * number the closer the task has come to overflowing its stack.\r
+ *\r
+ * @param xTask Handle of the task associated with the stack to be checked.\r
+ * Set xTask to NULL to check the stack of the calling task.\r
+ *\r
+ * @return The smallest amount of free stack space there has been (in bytes)\r
+ * since the task referenced by xTask was created.\r
+ */\r
+unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask ) PRIVILEGED_FUNCTION;\r
+\r
+/* When using trace macros it is sometimes necessary to include tasks.h before\r
+FreeRTOS.h. When this is done pdTASK_HOOK_CODE will not yet have been defined,\r
+so the following two prototypes will cause a compilation error. This can be\r
+fixed by simply guarding against the inclusion of these two prototypes unless\r
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration\r
+constant. */\r
+#ifdef configUSE_APPLICATION_TASK_TAG\r
+ #if configUSE_APPLICATION_TASK_TAG == 1\r
+ /**\r
+ * task.h\r
+ * <pre>void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction );</pre>\r
+ *\r
+ * Sets pxHookFunction to be the task hook function used by the task xTask.\r
+ * Passing xTask as NULL has the effect of setting the calling tasks hook\r
+ * function.\r
+ */\r
+ void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction ) PRIVILEGED_FUNCTION;\r
+\r
+ /**\r
+ * task.h\r
+ * <pre>void xTaskGetApplicationTaskTag( xTaskHandle xTask );</pre>\r
+ *\r
+ * Returns the pxHookFunction value assigned to the task xTask.\r
+ */\r
+ pdTASK_HOOK_CODE xTaskGetApplicationTaskTag( xTaskHandle xTask ) PRIVILEGED_FUNCTION;\r
+ #endif /* configUSE_APPLICATION_TASK_TAG ==1 */\r
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */\r
+\r
+/**\r
+ * task.h\r
+ * <pre>portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction );</pre>\r
+ *\r
+ * Calls the hook function associated with xTask. Passing xTask as NULL has\r
+ * the effect of calling the Running tasks (the calling task) hook function.\r
+ *\r
+ * pvParameter is passed to the hook function for the task to interpret as it\r
+ * wants.\r
+ */\r
+portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * xTaskGetIdleTaskHandle() is only available if \r
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.\r
+ *\r
+ * Simply returns the handle of the idle task. It is not valid to call\r
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.\r
+ */\r
+xTaskHandle xTaskGetIdleTaskHandle( void );\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\r
+ *----------------------------------------------------------*/\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY\r
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\r
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * Called from the real time kernel tick (either preemptive or cooperative),\r
+ * this increments the tick count and checks if any tasks that are blocked\r
+ * for a finite period required removing from a blocked list and placing on\r
+ * a ready list.\r
+ */\r
+void vTaskIncrementTick( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r
+ *\r
+ * Removes the calling task from the ready list and places it both\r
+ * on the list of tasks waiting for a particular event, and the\r
+ * list of delayed tasks. The task will be removed from both lists\r
+ * and replaced on the ready list should either the event occur (and\r
+ * there be no higher priority tasks waiting on the same event) or\r
+ * the delay period expires.\r
+ *\r
+ * @param pxEventList The list containing tasks that are blocked waiting\r
+ * for the event to occur.\r
+ *\r
+ * @param xTicksToWait The maximum amount of time that the task should wait\r
+ * for the event to occur. This is specified in kernel ticks,the constant\r
+ * portTICK_RATE_MS can be used to convert kernel ticks into a real time\r
+ * period.\r
+ */\r
+void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r
+ *\r
+ * This function performs nearly the same function as vTaskPlaceOnEventList().\r
+ * The difference being that this function does not permit tasks to block\r
+ * indefinitely, whereas vTaskPlaceOnEventList() does.\r
+ *\r
+ * @return pdTRUE if the task being removed has a higher priority than the task\r
+ * making the call, otherwise pdFALSE.\r
+ */\r
+void vTaskPlaceOnEventListRestricted( const xList * const pxEventList, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN\r
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\r
+ *\r
+ * Removes a task from both the specified event list and the list of blocked\r
+ * tasks, and places it on a ready queue.\r
+ *\r
+ * xTaskRemoveFromEventList () will be called if either an event occurs to\r
+ * unblock a task, or the block timeout period expires.\r
+ *\r
+ * @return pdTRUE if the task being removed has a higher priority than the task\r
+ * making the call, otherwise pdFALSE.\r
+ */\r
+signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY\r
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\r
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\r
+ *\r
+ * Sets the pointer to the current TCB to the TCB of the highest priority task\r
+ * that is ready to run.\r
+ */\r
+void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Return the handle of the calling task.\r
+ */\r
+xTaskHandle xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Capture the current time status for future reference.\r
+ */\r
+void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Compare the time status now with that previously captured to see if the\r
+ * timeout has expired.\r
+ */\r
+portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Shortcut used by the queue implementation to prevent unnecessary call to\r
+ * taskYIELD();\r
+ */\r
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,\r
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.\r
+ */\r
+portBASE_TYPE xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Raises the priority of the mutex holder to that of the calling task should\r
+ * the mutex holder have a priority less than the calling task.\r
+ */\r
+void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Set the priority of a task back to its proper priority in the case that it\r
+ * inherited a higher priority while it was holding a semaphore.\r
+ */\r
+void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Generic version of the task creation function which is in turn called by the\r
+ * xTaskCreate() and xTaskCreateRestricted() macros.\r
+ */\r
+signed portBASE_TYPE xTaskGenericCreate( pdTASK_CODE pxTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions ) PRIVILEGED_FUNCTION;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* TASK_H */\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#ifndef TIMERS_H\r
+#define TIMERS_H\r
+\r
+#ifndef INC_FREERTOS_H\r
+ #error "include FreeRTOS.h must appear in source files before include timers.h"\r
+#endif\r
+\r
+#include "os_portable.h"\r
+#include "os_list.h"\r
+#include "os_task.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* IDs for commands that can be sent/received on the timer queue. These are to\r
+be used solely through the macros that make up the public software timer API,\r
+as defined below. */\r
+#define tmrCOMMAND_START 0\r
+#define tmrCOMMAND_STOP 1\r
+#define tmrCOMMAND_CHANGE_PERIOD 2\r
+#define tmrCOMMAND_DELETE 3\r
+\r
+/*-----------------------------------------------------------\r
+ * MACROS AND DEFINITIONS\r
+ *----------------------------------------------------------*/\r
+\r
+ /**\r
+ * Type by which software timers are referenced. For example, a call to\r
+ * xTimerCreate() returns an xTimerHandle variable that can then be used to\r
+ * reference the subject timer in calls to other software timer API functions\r
+ * (for example, xTimerStart(), xTimerReset(), etc.).\r
+ */\r
+typedef void * xTimerHandle;\r
+\r
+/* Define the prototype to which timer callback functions must conform. */\r
+typedef void (*tmrTIMER_CALLBACK)( xTimerHandle xTimer );\r
+\r
+/**\r
+ * xTimerHandle xTimerCreate( const signed char *pcTimerName,\r
+ * portTickType xTimerPeriodInTicks,\r
+ * unsigned portBASE_TYPE uxAutoReload,\r
+ * void * pvTimerID,\r
+ * tmrTIMER_CALLBACK pxCallbackFunction );\r
+ *\r
+ * Creates a new software timer instance. This allocates the storage required\r
+ * by the new timer, initialises the new timers internal state, and returns a\r
+ * handle by which the new timer can be referenced.\r
+ *\r
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),\r
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\r
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the\r
+ * active state.\r
+ *\r
+ * @param pcTimerName A text name that is assigned to the timer. This is done\r
+ * purely to assist debugging. The kernel itself only ever references a timer by\r
+ * its handle, and never by its name.\r
+ *\r
+ * @param xTimerPeriodInTicks The timer period. The time is defined in tick periods so\r
+ * the constant portTICK_RATE_MS can be used to convert a time that has been\r
+ * specified in milliseconds. For example, if the timer must expire after 100\r
+ * ticks, then xTimerPeriodInTicks should be set to 100. Alternatively, if the timer\r
+ * must expire after 500ms, then xPeriod can be set to ( 500 / portTICK_RATE_MS )\r
+ * provided configTICK_RATE_HZ is less than or equal to 1000.\r
+ *\r
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\r
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. If\r
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\r
+ * enter the dormant state after it expires.\r
+ *\r
+ * @param pvTimerID An identifier that is assigned to the timer being created.\r
+ * Typically this would be used in the timer callback function to identify which\r
+ * timer expired when the same callback function is assigned to more than one\r
+ * timer.\r
+ *\r
+ * @param pxCallbackFunction The function to call when the timer expires.\r
+ * Callback functions must have the prototype defined by tmrTIMER_CALLBACK,\r
+ * which is "void vCallbackFunction( xTimerHandle xTimer );".\r
+ *\r
+ * @return If the timer is successfully create then a handle to the newly\r
+ * created timer is returned. If the timer cannot be created (because either\r
+ * there is insufficient FreeRTOS heap remaining to allocate the timer\r
+ * structures, or the timer period was set to 0) then 0 is returned.\r
+ *\r
+ * Example usage:\r
+ *\r
+ *\r
+ * define NUM_TIMERS 5\r
+ *\r
+ * // An array to hold handles to the created timers.\r
+ * xTimerHandle xTimers[ NUM_TIMERS ];\r
+ *\r
+ * // An array to hold a count of the number of times each timer expires.\r
+ * long lExpireCounters[ NUM_TIMERS ] = { 0 };\r
+ *\r
+ * // Define a callback function that will be used by multiple timer instances.\r
+ * // The callback function does nothing but count the number of times the\r
+ * // associated timer expires, and stop the timer once the timer has expired\r
+ * // 10 times.\r
+ * void vTimerCallback( xTimerHandle pxTimer )\r
+ * {\r
+ * long lArrayIndex;\r
+ * const long xMaxExpiryCountBeforeStopping = 10;\r
+ *\r
+ * // Optionally do something if the pxTimer parameter is NULL.\r
+ * configASSERT( pxTimer );\r
+ * \r
+ * // Which timer expired?\r
+ * lArrayIndex = ( long ) pvTimerGetTimerID( pxTimer );\r
+ *\r
+ * // Increment the number of times that pxTimer has expired.\r
+ * lExpireCounters[ lArrayIndex ] += 1;\r
+ *\r
+ * // If the timer has expired 10 times then stop it from running.\r
+ * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )\r
+ * {\r
+ * // Do not use a block time if calling a timer API function from a\r
+ * // timer callback function, as doing so could cause a deadlock!\r
+ * xTimerStop( pxTimer, 0 );\r
+ * }\r
+ * }\r
+ *\r
+ * void main( void )\r
+ * {\r
+ * long x;\r
+ *\r
+ * // Create then start some timers. Starting the timers before the scheduler\r
+ * // has been started means the timers will start running immediately that\r
+ * // the scheduler starts.\r
+ * for( x = 0; x < NUM_TIMERS; x++ )\r
+ * {\r
+ * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel.\r
+ * ( 100 * x ), // The timer period in ticks.\r
+ * pdTRUE, // The timers will auto-reload themselves when they expire.\r
+ * ( void * ) x, // Assign each timer a unique id equal to its array index.\r
+ * vTimerCallback // Each timer calls the same callback when it expires.\r
+ * );\r
+ *\r
+ * if( xTimers[ x ] == NULL )\r
+ * {\r
+ * // The timer was not created.\r
+ * }\r
+ * else\r
+ * {\r
+ * // Start the timer. No block time is specified, and even if one was\r
+ * // it would be ignored because the scheduler has not yet been\r
+ * // started.\r
+ * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )\r
+ * {\r
+ * // The timer could not be set into the Active state.\r
+ * }\r
+ * }\r
+ * }\r
+ *\r
+ * // ...\r
+ * // Create tasks here.\r
+ * // ...\r
+ *\r
+ * // Starting the scheduler will start the timers running as they have already\r
+ * // been set into the active state.\r
+ * xTaskStartScheduler();\r
+ *\r
+ * // Should not reach here.\r
+ * for( ;; );\r
+ * }\r
+ */\r
+xTimerHandle xTimerCreate( const signed char *pcTimerName, portTickType xTimerPeriodInTicks, unsigned portBASE_TYPE uxAutoReload, void * pvTimerID, tmrTIMER_CALLBACK pxCallbackFunction ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * void *pvTimerGetTimerID( xTimerHandle xTimer );\r
+ *\r
+ * Returns the ID assigned to the timer.\r
+ *\r
+ * IDs are assigned to timers using the pvTimerID parameter of the call to\r
+ * xTimerCreated() that was used to create the timer.\r
+ *\r
+ * If the same callback function is assigned to multiple timers then the timer\r
+ * ID can be used within the callback function to identify which timer actually\r
+ * expired.\r
+ *\r
+ * @param xTimer The timer being queried.\r
+ *\r
+ * @return The ID assigned to the timer being queried.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * See the xTimerCreate() API function example usage scenario.\r
+ */\r
+void *pvTimerGetTimerID( xTimerHandle xTimer ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer );\r
+ *\r
+ * Queries a timer to see if it is active or dormant.\r
+ *\r
+ * A timer will be dormant if:\r
+ * 1) It has been created but not started, or\r
+ * 2) It is an expired on-shot timer that has not been restarted.\r
+ *\r
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),\r
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\r
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the\r
+ * active state.\r
+ *\r
+ * @param xTimer The timer being queried.\r
+ *\r
+ * @return pdFALSE will be returned if the timer is dormant. A value other than\r
+ * pdFALSE will be returned if the timer is active.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This function assumes xTimer has already been created.\r
+ * void vAFunction( xTimerHandle xTimer )\r
+ * {\r
+ * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"\r
+ * {\r
+ * // xTimer is active, do something.\r
+ * }\r
+ * else\r
+ * {\r
+ * // xTimer is not active, do something else.\r
+ * }\r
+ * }\r
+ */\r
+portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer ) PRIVILEGED_FUNCTION;\r
+\r
+/**\r
+ * xTimerGetTimerDaemonTaskHandle() is only available if \r
+ * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h.\r
+ *\r
+ * Simply returns the handle of the timer service/daemon task. It it not valid\r
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.\r
+ */\r
+xTaskHandle xTimerGetTimerDaemonTaskHandle( void );\r
+\r
+/**\r
+ * portBASE_TYPE xTimerStart( xTimerHandle xTimer, portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerStart() starts a timer that was previously created using the\r
+ * xTimerCreate() API function. If the timer had already been started and was\r
+ * already in the active state, then xTimerStart() has equivalent functionality\r
+ * to the xTimerReset() API function.\r
+ *\r
+ * Starting a timer ensures the timer is in the active state. If the timer\r
+ * is not stopped, deleted, or reset in the mean time, the callback function\r
+ * associated with the timer will get called 'n' ticks after xTimerStart() was\r
+ * called, where 'n' is the timers defined period.\r
+ *\r
+ * It is valid to call xTimerStart() before the scheduler has been started, but\r
+ * when this is done the timer will not actually start until the scheduler is\r
+ * started, and the timers expiry time will be relative to when the scheduler is\r
+ * started, not relative to when xTimerStart() was called.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()\r
+ * to be available.\r
+ *\r
+ * @param xTimer The handle of the timer being started/restarted.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the start command to be successfully\r
+ * sent to the timer command queue, should the queue already be full when\r
+ * xTimerStart() was called. xBlockTime is ignored if xTimerStart() is called\r
+ * before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the start command could not be sent to\r
+ * the timer command queue even after xBlockTime ticks had passed. pdPASS will\r
+ * be returned if the command was successfully sent to the timer command queue.\r
+ * When the command is actually processed will depend on the priority of the\r
+ * timer service/daemon task relative to other tasks in the system, although the\r
+ * timers expiry time is relative to when xTimerStart() is actually called. The\r
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r
+ * configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * See the xTimerCreate() API function example usage scenario.\r
+ *\r
+ */\r
+#define xTimerStart( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerStop( xTimerHandle xTimer, portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerStop() stops a timer that was previously started using either of the\r
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),\r
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.\r
+ *\r
+ * Stopping a timer ensures the timer is not in the active state.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()\r
+ * to be available.\r
+ *\r
+ * @param xTimer The handle of the timer being stopped.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the stop command to be successfully\r
+ * sent to the timer command queue, should the queue already be full when\r
+ * xTimerStop() was called. xBlockTime is ignored if xTimerStop() is called\r
+ * before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the stop command could not be sent to\r
+ * the timer command queue even after xBlockTime ticks had passed. pdPASS will\r
+ * be returned if the command was successfully sent to the timer command queue.\r
+ * When the command is actually processed will depend on the priority of the\r
+ * timer service/daemon task relative to other tasks in the system. The timer\r
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r
+ * configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * See the xTimerCreate() API function example usage scenario.\r
+ *\r
+ */\r
+#define xTimerStop( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerChangePeriod( xTimerHandle xTimer,\r
+ * portTickType xNewPeriod,\r
+ * portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerChangePeriod() changes the period of a timer that was previously\r
+ * created using the xTimerCreate() API function.\r
+ *\r
+ * xTimerChangePeriod() can be called to change the period of an active or\r
+ * dormant state timer.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for\r
+ * xTimerChangePeriod() to be available.\r
+ *\r
+ * @param xTimer The handle of the timer that is having its period changed.\r
+ *\r
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in\r
+ * tick periods, so the constant portTICK_RATE_MS can be used to convert a time\r
+ * that has been specified in milliseconds. For example, if the timer must\r
+ * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively,\r
+ * if the timer must expire after 500ms, then xNewPeriod can be set to\r
+ * ( 500 / portTICK_RATE_MS ) provided configTICK_RATE_HZ is less than\r
+ * or equal to 1000.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the change period command to be\r
+ * successfully sent to the timer command queue, should the queue already be\r
+ * full when xTimerChangePeriod() was called. xBlockTime is ignored if\r
+ * xTimerChangePeriod() is called before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the change period command could not be\r
+ * sent to the timer command queue even after xBlockTime ticks had passed.\r
+ * pdPASS will be returned if the command was successfully sent to the timer\r
+ * command queue. When the command is actually processed will depend on the\r
+ * priority of the timer service/daemon task relative to other tasks in the\r
+ * system. The timer service/daemon task priority is set by the\r
+ * configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This function assumes xTimer has already been created. If the timer\r
+ * // referenced by xTimer is already active when it is called, then the timer\r
+ * // is deleted. If the timer referenced by xTimer is not active when it is\r
+ * // called, then the period of the timer is set to 500ms and the timer is\r
+ * // started.\r
+ * void vAFunction( xTimerHandle xTimer )\r
+ * {\r
+ * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"\r
+ * {\r
+ * // xTimer is already active - delete it.\r
+ * xTimerDelete( xTimer );\r
+ * }\r
+ * else\r
+ * {\r
+ * // xTimer is not active, change its period to 500ms. This will also\r
+ * // cause the timer to start. Block for a maximum of 100 ticks if the\r
+ * // change period command cannot immediately be sent to the timer\r
+ * // command queue.\r
+ * if( xTimerChangePeriod( xTimer, 500 / portTICK_RATE_MS, 100 ) == pdPASS )\r
+ * {\r
+ * // The command was successfully sent.\r
+ * }\r
+ * else\r
+ * {\r
+ * // The command could not be sent, even after waiting for 100 ticks\r
+ * // to pass. Take appropriate action here.\r
+ * }\r
+ * }\r
+ * }\r
+ */\r
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerDelete( xTimerHandle xTimer, portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerDelete() deletes a timer that was previously created using the\r
+ * xTimerCreate() API function.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for\r
+ * xTimerDelete() to be available.\r
+ *\r
+ * @param xTimer The handle of the timer being deleted.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the delete command to be\r
+ * successfully sent to the timer command queue, should the queue already be\r
+ * full when xTimerDelete() was called. xBlockTime is ignored if xTimerDelete()\r
+ * is called before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the delete command could not be sent to\r
+ * the timer command queue even after xBlockTime ticks had passed. pdPASS will\r
+ * be returned if the command was successfully sent to the timer command queue.\r
+ * When the command is actually processed will depend on the priority of the\r
+ * timer service/daemon task relative to other tasks in the system. The timer\r
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r
+ * configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * See the xTimerChangePeriod() API function example usage scenario.\r
+ */\r
+#define xTimerDelete( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerReset( xTimerHandle xTimer, portTickType xBlockTime );\r
+ *\r
+ * Timer functionality is provided by a timer service/daemon task. Many of the\r
+ * public FreeRTOS timer API functions send commands to the timer service task\r
+ * though a queue called the timer command queue. The timer command queue is\r
+ * private to the kernel itself and is not directly accessible to application\r
+ * code. The length of the timer command queue is set by the\r
+ * configTIMER_QUEUE_LENGTH configuration constant.\r
+ *\r
+ * xTimerReset() re-starts a timer that was previously created using the\r
+ * xTimerCreate() API function. If the timer had already been started and was\r
+ * already in the active state, then xTimerReset() will cause the timer to\r
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was\r
+ * called. If the timer was in the dormant state then xTimerReset() has\r
+ * equivalent functionality to the xTimerStart() API function.\r
+ *\r
+ * Resetting a timer ensures the timer is in the active state. If the timer\r
+ * is not stopped, deleted, or reset in the mean time, the callback function\r
+ * associated with the timer will get called 'n' ticks after xTimerReset() was\r
+ * called, where 'n' is the timers defined period.\r
+ *\r
+ * It is valid to call xTimerReset() before the scheduler has been started, but\r
+ * when this is done the timer will not actually start until the scheduler is\r
+ * started, and the timers expiry time will be relative to when the scheduler is\r
+ * started, not relative to when xTimerReset() was called.\r
+ *\r
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()\r
+ * to be available.\r
+ *\r
+ * @param xTimer The handle of the timer being reset/started/restarted.\r
+ *\r
+ * @param xBlockTime Specifies the time, in ticks, that the calling task should\r
+ * be held in the Blocked state to wait for the reset command to be successfully\r
+ * sent to the timer command queue, should the queue already be full when\r
+ * xTimerReset() was called. xBlockTime is ignored if xTimerReset() is called\r
+ * before the scheduler is started.\r
+ *\r
+ * @return pdFAIL will be returned if the reset command could not be sent to\r
+ * the timer command queue even after xBlockTime ticks had passed. pdPASS will\r
+ * be returned if the command was successfully sent to the timer command queue.\r
+ * When the command is actually processed will depend on the priority of the\r
+ * timer service/daemon task relative to other tasks in the system, although the\r
+ * timers expiry time is relative to when xTimerStart() is actually called. The\r
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\r
+ * configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass\r
+ * // without a key being pressed, then the LCD back-light is switched off. In\r
+ * // this case, the timer is a one-shot timer.\r
+ *\r
+ * xTimerHandle xBacklightTimer = NULL;\r
+ *\r
+ * // The callback function assigned to the one-shot timer. In this case the\r
+ * // parameter is not used.\r
+ * void vBacklightTimerCallback( xTimerHandle pxTimer )\r
+ * {\r
+ * // The timer expired, therefore 5 seconds must have passed since a key\r
+ * // was pressed. Switch off the LCD back-light.\r
+ * vSetBacklightState( BACKLIGHT_OFF );\r
+ * }\r
+ *\r
+ * // The key press event handler.\r
+ * void vKeyPressEventHandler( char cKey )\r
+ * {\r
+ * // Ensure the LCD back-light is on, then reset the timer that is\r
+ * // responsible for turning the back-light off after 5 seconds of\r
+ * // key inactivity. Wait 10 ticks for the command to be successfully sent\r
+ * // if it cannot be sent immediately.\r
+ * vSetBacklightState( BACKLIGHT_ON );\r
+ * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )\r
+ * {\r
+ * // The reset command was not executed successfully. Take appropriate\r
+ * // action here.\r
+ * }\r
+ *\r
+ * // Perform the rest of the key processing here.\r
+ * }\r
+ *\r
+ * void main( void )\r
+ * {\r
+ * long x;\r
+ *\r
+ * // Create then start the one-shot timer that is responsible for turning\r
+ * // the back-light off if no keys are pressed within a 5 second period.\r
+ * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel.\r
+ * ( 5000 / portTICK_RATE_MS), // The timer period in ticks.\r
+ * pdFALSE, // The timer is a one-shot timer.\r
+ * 0, // The id is not used by the callback so can take any value.\r
+ * vBacklightTimerCallback // The callback function that switches the LCD back-light off.\r
+ * );\r
+ *\r
+ * if( xBacklightTimer == NULL )\r
+ * {\r
+ * // The timer was not created.\r
+ * }\r
+ * else\r
+ * {\r
+ * // Start the timer. No block time is specified, and even if one was\r
+ * // it would be ignored because the scheduler has not yet been\r
+ * // started.\r
+ * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )\r
+ * {\r
+ * // The timer could not be set into the Active state.\r
+ * }\r
+ * }\r
+ *\r
+ * // ...\r
+ * // Create tasks here.\r
+ * // ...\r
+ *\r
+ * // Starting the scheduler will start the timer running as it has already\r
+ * // been set into the active state.\r
+ * xTaskStartScheduler();\r
+ *\r
+ * // Should not reach here.\r
+ * for( ;; );\r
+ * }\r
+ */\r
+#define xTimerReset( xTimer, xBlockTime ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xBlockTime ) )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerStartFromISR( xTimerHandle xTimer,\r
+ * portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+ *\r
+ * A version of xTimerStart() that can be called from an interrupt service\r
+ * routine.\r
+ *\r
+ * @param xTimer The handle of the timer being started/restarted.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r
+ * of its time in the Blocked state, waiting for messages to arrive on the timer\r
+ * command queue. Calling xTimerStartFromISR() writes a message to the timer\r
+ * command queue, so has the potential to transition the timer service/daemon\r
+ * task out of the Blocked state. If calling xTimerStartFromISR() causes the\r
+ * timer service/daemon task to leave the Blocked state, and the timer service/\r
+ * daemon task has a priority equal to or greater than the currently executing\r
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r
+ * get set to pdTRUE internally within the xTimerStartFromISR() function. If\r
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should\r
+ * be performed before the interrupt exits.\r
+ *\r
+ * @return pdFAIL will be returned if the start command could not be sent to\r
+ * the timer command queue. pdPASS will be returned if the command was\r
+ * successfully sent to the timer command queue. When the command is actually\r
+ * processed will depend on the priority of the timer service/daemon task\r
+ * relative to other tasks in the system, although the timers expiry time is\r
+ * relative to when xTimerStartFromISR() is actually called. The timer service/daemon\r
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This scenario assumes xBacklightTimer has already been created. When a\r
+ * // key is pressed, an LCD back-light is switched on. If 5 seconds pass\r
+ * // without a key being pressed, then the LCD back-light is switched off. In\r
+ * // this case, the timer is a one-shot timer, and unlike the example given for\r
+ * // the xTimerReset() function, the key press event handler is an interrupt\r
+ * // service routine.\r
+ *\r
+ * // The callback function assigned to the one-shot timer. In this case the\r
+ * // parameter is not used.\r
+ * void vBacklightTimerCallback( xTimerHandle pxTimer )\r
+ * {\r
+ * // The timer expired, therefore 5 seconds must have passed since a key\r
+ * // was pressed. Switch off the LCD back-light.\r
+ * vSetBacklightState( BACKLIGHT_OFF );\r
+ * }\r
+ *\r
+ * // The key press interrupt service routine.\r
+ * void vKeyPressEventInterruptHandler( void )\r
+ * {\r
+ * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ *\r
+ * // Ensure the LCD back-light is on, then restart the timer that is\r
+ * // responsible for turning the back-light off after 5 seconds of\r
+ * // key inactivity. This is an interrupt service routine so can only\r
+ * // call FreeRTOS API functions that end in "FromISR".\r
+ * vSetBacklightState( BACKLIGHT_ON );\r
+ *\r
+ * // xTimerStartFromISR() or xTimerResetFromISR() could be called here\r
+ * // as both cause the timer to re-calculate its expiry time.\r
+ * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\r
+ * // declared (in this function).\r
+ * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r
+ * {\r
+ * // The start command was not executed successfully. Take appropriate\r
+ * // action here.\r
+ * }\r
+ *\r
+ * // Perform the rest of the key processing here.\r
+ *\r
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r
+ * // should be performed. The syntax required to perform a context switch\r
+ * // from inside an ISR varies from port to port, and from compiler to\r
+ * // compiler. Inspect the demos for the port you are using to find the\r
+ * // actual syntax required.\r
+ * if( xHigherPriorityTaskWoken != pdFALSE )\r
+ * {\r
+ * // Call the interrupt safe yield function here (actual function\r
+ * // depends on the FreeRTOS port being used.\r
+ * }\r
+ * }\r
+ */\r
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerStopFromISR( xTimerHandle xTimer,\r
+ * portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+ *\r
+ * A version of xTimerStop() that can be called from an interrupt service\r
+ * routine.\r
+ *\r
+ * @param xTimer The handle of the timer being stopped.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r
+ * of its time in the Blocked state, waiting for messages to arrive on the timer\r
+ * command queue. Calling xTimerStopFromISR() writes a message to the timer\r
+ * command queue, so has the potential to transition the timer service/daemon\r
+ * task out of the Blocked state. If calling xTimerStopFromISR() causes the\r
+ * timer service/daemon task to leave the Blocked state, and the timer service/\r
+ * daemon task has a priority equal to or greater than the currently executing\r
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r
+ * get set to pdTRUE internally within the xTimerStopFromISR() function. If\r
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should\r
+ * be performed before the interrupt exits.\r
+ *\r
+ * @return pdFAIL will be returned if the stop command could not be sent to\r
+ * the timer command queue. pdPASS will be returned if the command was\r
+ * successfully sent to the timer command queue. When the command is actually\r
+ * processed will depend on the priority of the timer service/daemon task\r
+ * relative to other tasks in the system. The timer service/daemon task\r
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This scenario assumes xTimer has already been created and started. When\r
+ * // an interrupt occurs, the timer should be simply stopped.\r
+ *\r
+ * // The interrupt service routine that stops the timer.\r
+ * void vAnExampleInterruptServiceRoutine( void )\r
+ * {\r
+ * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ *\r
+ * // The interrupt has occurred - simply stop the timer.\r
+ * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\r
+ * // (within this function). As this is an interrupt service routine, only\r
+ * // FreeRTOS API functions that end in "FromISR" can be used.\r
+ * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r
+ * {\r
+ * // The stop command was not executed successfully. Take appropriate\r
+ * // action here.\r
+ * }\r
+ *\r
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r
+ * // should be performed. The syntax required to perform a context switch\r
+ * // from inside an ISR varies from port to port, and from compiler to\r
+ * // compiler. Inspect the demos for the port you are using to find the\r
+ * // actual syntax required.\r
+ * if( xHigherPriorityTaskWoken != pdFALSE )\r
+ * {\r
+ * // Call the interrupt safe yield function here (actual function\r
+ * // depends on the FreeRTOS port being used.\r
+ * }\r
+ * }\r
+ */\r
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0, ( pxHigherPriorityTaskWoken ), 0U )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerChangePeriodFromISR( xTimerHandle xTimer,\r
+ * portTickType xNewPeriod,\r
+ * portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+ *\r
+ * A version of xTimerChangePeriod() that can be called from an interrupt\r
+ * service routine.\r
+ *\r
+ * @param xTimer The handle of the timer that is having its period changed.\r
+ *\r
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in\r
+ * tick periods, so the constant portTICK_RATE_MS can be used to convert a time\r
+ * that has been specified in milliseconds. For example, if the timer must\r
+ * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively,\r
+ * if the timer must expire after 500ms, then xNewPeriod can be set to\r
+ * ( 500 / portTICK_RATE_MS ) provided configTICK_RATE_HZ is less than\r
+ * or equal to 1000.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r
+ * of its time in the Blocked state, waiting for messages to arrive on the timer\r
+ * command queue. Calling xTimerChangePeriodFromISR() writes a message to the\r
+ * timer command queue, so has the potential to transition the timer service/\r
+ * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR()\r
+ * causes the timer service/daemon task to leave the Blocked state, and the\r
+ * timer service/daemon task has a priority equal to or greater than the\r
+ * currently executing task (the task that was interrupted), then\r
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the\r
+ * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets\r
+ * this value to pdTRUE then a context switch should be performed before the\r
+ * interrupt exits.\r
+ *\r
+ * @return pdFAIL will be returned if the command to change the timers period\r
+ * could not be sent to the timer command queue. pdPASS will be returned if the\r
+ * command was successfully sent to the timer command queue. When the command\r
+ * is actually processed will depend on the priority of the timer service/daemon\r
+ * task relative to other tasks in the system. The timer service/daemon task\r
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This scenario assumes xTimer has already been created and started. When\r
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.\r
+ *\r
+ * // The interrupt service routine that changes the period of xTimer.\r
+ * void vAnExampleInterruptServiceRoutine( void )\r
+ * {\r
+ * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ *\r
+ * // The interrupt has occurred - change the period of xTimer to 500ms.\r
+ * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\r
+ * // (within this function). As this is an interrupt service routine, only\r
+ * // FreeRTOS API functions that end in "FromISR" can be used.\r
+ * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r
+ * {\r
+ * // The command to change the timers period was not executed\r
+ * // successfully. Take appropriate action here.\r
+ * }\r
+ *\r
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r
+ * // should be performed. The syntax required to perform a context switch\r
+ * // from inside an ISR varies from port to port, and from compiler to\r
+ * // compiler. Inspect the demos for the port you are using to find the\r
+ * // actual syntax required.\r
+ * if( xHigherPriorityTaskWoken != pdFALSE )\r
+ * {\r
+ * // Call the interrupt safe yield function here (actual function\r
+ * // depends on the FreeRTOS port being used.\r
+ * }\r
+ * }\r
+ */\r
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )\r
+\r
+/**\r
+ * portBASE_TYPE xTimerResetFromISR( xTimerHandle xTimer,\r
+ * portBASE_TYPE *pxHigherPriorityTaskWoken );\r
+ *\r
+ * A version of xTimerReset() that can be called from an interrupt service\r
+ * routine.\r
+ *\r
+ * @param xTimer The handle of the timer that is to be started, reset, or\r
+ * restarted.\r
+ *\r
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\r
+ * of its time in the Blocked state, waiting for messages to arrive on the timer\r
+ * command queue. Calling xTimerResetFromISR() writes a message to the timer\r
+ * command queue, so has the potential to transition the timer service/daemon\r
+ * task out of the Blocked state. If calling xTimerResetFromISR() causes the\r
+ * timer service/daemon task to leave the Blocked state, and the timer service/\r
+ * daemon task has a priority equal to or greater than the currently executing\r
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\r
+ * get set to pdTRUE internally within the xTimerResetFromISR() function. If\r
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should\r
+ * be performed before the interrupt exits.\r
+ *\r
+ * @return pdFAIL will be returned if the reset command could not be sent to\r
+ * the timer command queue. pdPASS will be returned if the command was\r
+ * successfully sent to the timer command queue. When the command is actually\r
+ * processed will depend on the priority of the timer service/daemon task\r
+ * relative to other tasks in the system, although the timers expiry time is\r
+ * relative to when xTimerResetFromISR() is actually called. The timer service/daemon\r
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.\r
+ *\r
+ * Example usage:\r
+ *\r
+ * // This scenario assumes xBacklightTimer has already been created. When a\r
+ * // key is pressed, an LCD back-light is switched on. If 5 seconds pass\r
+ * // without a key being pressed, then the LCD back-light is switched off. In\r
+ * // this case, the timer is a one-shot timer, and unlike the example given for\r
+ * // the xTimerReset() function, the key press event handler is an interrupt\r
+ * // service routine.\r
+ *\r
+ * // The callback function assigned to the one-shot timer. In this case the\r
+ * // parameter is not used.\r
+ * void vBacklightTimerCallback( xTimerHandle pxTimer )\r
+ * {\r
+ * // The timer expired, therefore 5 seconds must have passed since a key\r
+ * // was pressed. Switch off the LCD back-light.\r
+ * vSetBacklightState( BACKLIGHT_OFF );\r
+ * }\r
+ *\r
+ * // The key press interrupt service routine.\r
+ * void vKeyPressEventInterruptHandler( void )\r
+ * {\r
+ * portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;\r
+ *\r
+ * // Ensure the LCD back-light is on, then reset the timer that is\r
+ * // responsible for turning the back-light off after 5 seconds of\r
+ * // key inactivity. This is an interrupt service routine so can only\r
+ * // call FreeRTOS API functions that end in "FromISR".\r
+ * vSetBacklightState( BACKLIGHT_ON );\r
+ *\r
+ * // xTimerStartFromISR() or xTimerResetFromISR() could be called here\r
+ * // as both cause the timer to re-calculate its expiry time.\r
+ * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\r
+ * // declared (in this function).\r
+ * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\r
+ * {\r
+ * // The reset command was not executed successfully. Take appropriate\r
+ * // action here.\r
+ * }\r
+ *\r
+ * // Perform the rest of the key processing here.\r
+ *\r
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\r
+ * // should be performed. The syntax required to perform a context switch\r
+ * // from inside an ISR varies from port to port, and from compiler to\r
+ * // compiler. Inspect the demos for the port you are using to find the\r
+ * // actual syntax required.\r
+ * if( xHigherPriorityTaskWoken != pdFALSE )\r
+ * {\r
+ * // Call the interrupt safe yield function here (actual function\r
+ * // depends on the FreeRTOS port being used.\r
+ * }\r
+ * }\r
+ */\r
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\r
+\r
+/*\r
+ * Functions beyond this part are not part of the public API and are intended\r
+ * for use by the kernel only.\r
+ */\r
+portBASE_TYPE xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;\r
+portBASE_TYPE xTimerGenericCommand( xTimerHandle xTimer, portBASE_TYPE xCommandID, portTickType xOptionalValue, portBASE_TYPE *pxHigherPriorityTaskWoken, portTickType xBlockTime ) PRIVILEGED_FUNCTION;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* TIMERS_H */\r
+\r
+\r
+\r
--- /dev/null
+/** @file pinmux.h \r
+* @brief PINMUX Driver Implementation File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#include "sys_common.h"\r
+\r
+#ifndef __PINMUX_H__\r
+#define __PINMUX_H__\r
+\r
+#define PINMUX_BALL_A5_SHIFT 8\r
+#define PINMUX_BALL_A11_SHIFT 8\r
+#define PINMUX_BALL_A14_SHIFT 0\r
+#define PINMUX_BALL_B2_SHIFT 24\r
+#define PINMUX_BALL_B3_SHIFT 8\r
+#define PINMUX_BALL_B4_SHIFT 16\r
+#define PINMUX_BALL_B5_SHIFT 24\r
+#define PINMUX_BALL_B6_SHIFT 8\r
+#define PINMUX_BALL_B11_SHIFT 8\r
+#define PINMUX_BALL_C1_SHIFT 0\r
+#define PINMUX_BALL_C2_SHIFT 0\r
+#define PINMUX_BALL_C3_SHIFT 16\r
+#define PINMUX_BALL_C4_SHIFT 16\r
+#define PINMUX_BALL_C5_SHIFT 8\r
+#define PINMUX_BALL_C6_SHIFT 0\r
+#define PINMUX_BALL_C7_SHIFT 24\r
+#define PINMUX_BALL_C8_SHIFT 16\r
+#define PINMUX_BALL_C9_SHIFT 24\r
+#define PINMUX_BALL_C10_SHIFT 8\r
+#define PINMUX_BALL_C11_SHIFT 0\r
+#define PINMUX_BALL_C12_SHIFT 16\r
+#define PINMUX_BALL_C13_SHIFT 0\r
+#define PINMUX_BALL_C14_SHIFT 8\r
+#define PINMUX_BALL_C15_SHIFT 16\r
+#define PINMUX_BALL_C16_SHIFT 8\r
+#define PINMUX_BALL_C17_SHIFT 0\r
+#define PINMUX_BALL_D3_SHIFT 0\r
+#define PINMUX_BALL_D4_SHIFT 0\r
+#define PINMUX_BALL_D5_SHIFT 0\r
+#define PINMUX_BALL_D14_SHIFT 16\r
+#define PINMUX_BALL_D15_SHIFT 24\r
+#define PINMUX_BALL_D16_SHIFT 24\r
+#define PINMUX_BALL_D17_SHIFT 16\r
+#define PINMUX_BALL_D19_SHIFT 0\r
+#define PINMUX_BALL_E1_SHIFT 16\r
+#define PINMUX_BALL_E3_SHIFT 8\r
+#define PINMUX_BALL_E5_SHIFT 16\r
+#define PINMUX_BALL_E6_SHIFT 24\r
+#define PINMUX_BALL_E7_SHIFT 24\r
+#define PINMUX_BALL_E8_SHIFT 0\r
+#define PINMUX_BALL_E9_SHIFT 24\r
+#define PINMUX_BALL_E10_SHIFT 16\r
+#define PINMUX_BALL_E11_SHIFT 8\r
+#define PINMUX_BALL_E12_SHIFT 24\r
+#define PINMUX_BALL_E13_SHIFT 0\r
+#define PINMUX_BALL_E16_SHIFT 16\r
+#define PINMUX_BALL_E17_SHIFT 8\r
+#define PINMUX_BALL_E18_SHIFT 0\r
+#define PINMUX_BALL_E19_SHIFT 0\r
+#define PINMUX_BALL_F3_SHIFT 16\r
+#define PINMUX_BALL_F5_SHIFT 24\r
+#define PINMUX_BALL_G3_SHIFT 8\r
+#define PINMUX_BALL_G5_SHIFT 8\r
+#define PINMUX_BALL_G16_SHIFT 24\r
+#define PINMUX_BALL_G17_SHIFT 0\r
+#define PINMUX_BALL_G19_SHIFT 16\r
+#define PINMUX_BALL_H3_SHIFT 16\r
+#define PINMUX_BALL_H16_SHIFT 16\r
+#define PINMUX_BALL_H17_SHIFT 24\r
+#define PINMUX_BALL_H18_SHIFT 24\r
+#define PINMUX_BALL_H19_SHIFT 16\r
+#define PINMUX_BALL_J3_SHIFT 24\r
+#define PINMUX_BALL_J18_SHIFT 0\r
+#define PINMUX_BALL_J19_SHIFT 8\r
+#define PINMUX_BALL_K2_SHIFT 8\r
+#define PINMUX_BALL_K5_SHIFT 0\r
+#define PINMUX_BALL_K15_SHIFT 8\r
+#define PINMUX_BALL_K17_SHIFT 0\r
+#define PINMUX_BALL_K18_SHIFT 0\r
+#define PINMUX_BALL_K19_SHIFT 8\r
+#define PINMUX_BALL_L5_SHIFT 24\r
+#define PINMUX_BALL_L15_SHIFT 16\r
+#define PINMUX_BALL_M1_SHIFT 0\r
+#define PINMUX_BALL_M2_SHIFT 24\r
+#define PINMUX_BALL_M5_SHIFT 8\r
+#define PINMUX_BALL_M15_SHIFT 24\r
+#define PINMUX_BALL_M17_SHIFT 8\r
+#define PINMUX_BALL_N1_SHIFT 16\r
+#define PINMUX_BALL_N2_SHIFT 0\r
+#define PINMUX_BALL_N5_SHIFT 24\r
+#define PINMUX_BALL_N15_SHIFT 8\r
+#define PINMUX_BALL_N17_SHIFT 16\r
+#define PINMUX_BALL_N19_SHIFT 0\r
+#define PINMUX_BALL_P1_SHIFT 24\r
+#define PINMUX_BALL_P5_SHIFT 8\r
+#define PINMUX_BALL_R2_SHIFT 24\r
+#define PINMUX_BALL_R5_SHIFT 24\r
+#define PINMUX_BALL_R6_SHIFT 0\r
+#define PINMUX_BALL_R7_SHIFT 24\r
+#define PINMUX_BALL_R8_SHIFT 24\r
+#define PINMUX_BALL_R9_SHIFT 0\r
+#define PINMUX_BALL_T1_SHIFT 0\r
+#define PINMUX_BALL_T12_SHIFT 24\r
+#define PINMUX_BALL_U1_SHIFT 24\r
+#define PINMUX_BALL_V2_SHIFT 16\r
+#define PINMUX_BALL_V5_SHIFT 8\r
+#define PINMUX_BALL_V6_SHIFT 16\r
+#define PINMUX_BALL_V7_SHIFT 16\r
+#define PINMUX_BALL_V10_SHIFT 16\r
+#define PINMUX_BALL_W3_SHIFT 16\r
+#define PINMUX_BALL_W5_SHIFT 8\r
+#define PINMUX_BALL_W6_SHIFT 16\r
+#define PINMUX_BALL_W9_SHIFT 8\r
+#define PINMUX_BALL_W10_SHIFT 0\r
+\r
+#define PINMUX_GATE_EMIF_CLK_SHIFT 8\r
+#define PINMUX_GIOB_DISABLE_HET2_SHIFT 16\r
+#define PINMUX_ALT_ADC_TRIGGER_SHIFT 0\r
+#define PINMUX_ETHERNET_SHIFT 24\r
+\r
+#define PINMUX_BALL_A5_MASK (~(0xFF << PINMUX_BALL_A5_SHIFT))\r
+#define PINMUX_BALL_A11_MASK (~(0xFF << PINMUX_BALL_A11_SHIFT))\r
+#define PINMUX_BALL_A14_MASK (~(0xFF << PINMUX_BALL_A14_SHIFT))\r
+#define PINMUX_BALL_B2_MASK (~(0xFF << PINMUX_BALL_B2_SHIFT))\r
+#define PINMUX_BALL_B3_MASK (~(0xFF << PINMUX_BALL_B3_SHIFT))\r
+#define PINMUX_BALL_B4_MASK (~(0xFF << PINMUX_BALL_B4_SHIFT))\r
+#define PINMUX_BALL_B5_MASK (~(0xFF << PINMUX_BALL_B5_SHIFT))\r
+#define PINMUX_BALL_B6_MASK (~(0xFF << PINMUX_BALL_B6_SHIFT))\r
+#define PINMUX_BALL_B11_MASK (~(0xFF << PINMUX_BALL_B11_SHIFT))\r
+#define PINMUX_BALL_C1_MASK (~(0xFF << PINMUX_BALL_C1_SHIFT))\r
+#define PINMUX_BALL_C2_MASK (~(0xFF << PINMUX_BALL_C2_SHIFT))\r
+#define PINMUX_BALL_C3_MASK (~(0xFF << PINMUX_BALL_C3_SHIFT))\r
+#define PINMUX_BALL_C4_MASK (~(0xFF << PINMUX_BALL_C4_SHIFT))\r
+#define PINMUX_BALL_C5_MASK (~(0xFF << PINMUX_BALL_C5_SHIFT))\r
+#define PINMUX_BALL_C6_MASK (~(0xFF << PINMUX_BALL_C6_SHIFT))\r
+#define PINMUX_BALL_C7_MASK (~(0xFF << PINMUX_BALL_C7_SHIFT))\r
+#define PINMUX_BALL_C8_MASK (~(0xFF << PINMUX_BALL_C8_SHIFT))\r
+#define PINMUX_BALL_C9_MASK (~(0xFF << PINMUX_BALL_C9_SHIFT))\r
+#define PINMUX_BALL_C10_MASK (~(0xFF << PINMUX_BALL_C10_SHIFT))\r
+#define PINMUX_BALL_C11_MASK (~(0xFF << PINMUX_BALL_C11_SHIFT))\r
+#define PINMUX_BALL_C12_MASK (~(0xFF << PINMUX_BALL_C12_SHIFT))\r
+#define PINMUX_BALL_C13_MASK (~(0xFF << PINMUX_BALL_C13_SHIFT))\r
+#define PINMUX_BALL_C14_MASK (~(0xFF << PINMUX_BALL_C14_SHIFT))\r
+#define PINMUX_BALL_C15_MASK (~(0xFF << PINMUX_BALL_C15_SHIFT))\r
+#define PINMUX_BALL_C16_MASK (~(0xFF << PINMUX_BALL_C16_SHIFT))\r
+#define PINMUX_BALL_C17_MASK (~(0xFF << PINMUX_BALL_C17_SHIFT))\r
+#define PINMUX_BALL_D3_MASK (~(0xFF << PINMUX_BALL_D3_SHIFT))\r
+#define PINMUX_BALL_D4_MASK (~(0xFF << PINMUX_BALL_D4_SHIFT))\r
+#define PINMUX_BALL_D5_MASK (~(0xFF << PINMUX_BALL_D5_SHIFT))\r
+#define PINMUX_BALL_D14_MASK (~(0xFF << PINMUX_BALL_D14_SHIFT))\r
+#define PINMUX_BALL_D15_MASK (~(0xFF << PINMUX_BALL_D15_SHIFT))\r
+#define PINMUX_BALL_D16_MASK (~(0xFF << PINMUX_BALL_D16_SHIFT))\r
+#define PINMUX_BALL_D17_MASK (~(0xFF << PINMUX_BALL_D17_SHIFT))\r
+#define PINMUX_BALL_D19_MASK (~(0xFF << PINMUX_BALL_D19_SHIFT))\r
+#define PINMUX_BALL_E1_MASK (~(0xFF << PINMUX_BALL_E1_SHIFT))\r
+#define PINMUX_BALL_E3_MASK (~(0xFF << PINMUX_BALL_E3_SHIFT))\r
+#define PINMUX_BALL_E5_MASK (~(0xFF << PINMUX_BALL_E5_SHIFT))\r
+#define PINMUX_BALL_E6_MASK (~(0xFF << PINMUX_BALL_E6_SHIFT))\r
+#define PINMUX_BALL_E7_MASK (~(0xFF << PINMUX_BALL_E7_SHIFT))\r
+#define PINMUX_BALL_E8_MASK (~(0xFF << PINMUX_BALL_E8_SHIFT))\r
+#define PINMUX_BALL_E9_MASK (~(0xFF << PINMUX_BALL_E9_SHIFT))\r
+#define PINMUX_BALL_E10_MASK (~(0xFF << PINMUX_BALL_E10_SHIFT))\r
+#define PINMUX_BALL_E11_MASK (~(0xFF << PINMUX_BALL_E11_SHIFT))\r
+#define PINMUX_BALL_E12_MASK (~(0xFF << PINMUX_BALL_E12_SHIFT))\r
+#define PINMUX_BALL_E13_MASK (~(0xFF << PINMUX_BALL_E13_SHIFT))\r
+#define PINMUX_BALL_E16_MASK (~(0xFF << PINMUX_BALL_E16_SHIFT))\r
+#define PINMUX_BALL_E17_MASK (~(0xFF << PINMUX_BALL_E17_SHIFT))\r
+#define PINMUX_BALL_E18_MASK (~(0xFF << PINMUX_BALL_E18_SHIFT))\r
+#define PINMUX_BALL_E19_MASK (~(0xFF << PINMUX_BALL_E19_SHIFT))\r
+#define PINMUX_BALL_F3_MASK (~(0xFF << PINMUX_BALL_F3_SHIFT))\r
+#define PINMUX_BALL_F5_MASK (~(0xFF << PINMUX_BALL_F4_SHIFT))\r
+#define PINMUX_BALL_G3_MASK (~(0xFF << PINMUX_BALL_G3_SHIFT))\r
+#define PINMUX_BALL_G5_MASK (~(0xFF << PINMUX_BALL_G4_SHIFT))\r
+#define PINMUX_BALL_G16_MASK (~(0xFF << PINMUX_BALL_G16_SHIFT))\r
+#define PINMUX_BALL_G17_MASK (~(0xFF << PINMUX_BALL_G17_SHIFT))\r
+#define PINMUX_BALL_G19_MASK (~(0xFF << PINMUX_BALL_G19_SHIFT))\r
+#define PINMUX_BALL_H3_MASK (~(0xFF << PINMUX_BALL_H3_SHIFT))\r
+#define PINMUX_BALL_H16_MASK (~(0xFF << PINMUX_BALL_H16_SHIFT))\r
+#define PINMUX_BALL_H17_MASK (~(0xFF << PINMUX_BALL_H17_SHIFT))\r
+#define PINMUX_BALL_H18_MASK (~(0xFF << PINMUX_BALL_H18_SHIFT))\r
+#define PINMUX_BALL_H19_MASK (~(0xFF << PINMUX_BALL_H19_SHIFT))\r
+#define PINMUX_BALL_J3_MASK (~(0xFF << PINMUX_BALL_J3_SHIFT))\r
+#define PINMUX_BALL_J18_MASK (~(0xFF << PINMUX_BALL_J18_SHIFT))\r
+#define PINMUX_BALL_J19_MASK (~(0xFF << PINMUX_BALL_J19_SHIFT))\r
+#define PINMUX_BALL_K2_MASK (~(0xFF << PINMUX_BALL_K2_SHIFT))\r
+#define PINMUX_BALL_K5_MASK (~(0xFF << PINMUX_BALL_K4_SHIFT))\r
+#define PINMUX_BALL_K15_MASK (~(0xFF << PINMUX_BALL_K15_SHIFT))\r
+#define PINMUX_BALL_K17_MASK (~(0xFF << PINMUX_BALL_K17_SHIFT))\r
+#define PINMUX_BALL_K18_MASK (~(0xFF << PINMUX_BALL_K18_SHIFT))\r
+#define PINMUX_BALL_K19_MASK (~(0xFF << PINMUX_BALL_K19_SHIFT))\r
+#define PINMUX_BALL_L5_MASK (~(0xFF << PINMUX_BALL_L4_SHIFT))\r
+#define PINMUX_BALL_L15_MASK (~(0xFF << PINMUX_BALL_L15_SHIFT))\r
+#define PINMUX_BALL_M1_MASK (~(0xFF << PINMUX_BALL_M1_SHIFT))\r
+#define PINMUX_BALL_M2_MASK (~(0xFF << PINMUX_BALL_M2_SHIFT))\r
+#define PINMUX_BALL_M5_MASK (~(0xFF << PINMUX_BALL_M4_SHIFT))\r
+#define PINMUX_BALL_M15_MASK (~(0xFF << PINMUX_BALL_M15_SHIFT))\r
+#define PINMUX_BALL_M17_MASK (~(0xFF << PINMUX_BALL_M17_SHIFT))\r
+#define PINMUX_BALL_N1_MASK (~(0xFF << PINMUX_BALL_N1_SHIFT))\r
+#define PINMUX_BALL_N2_MASK (~(0xFF << PINMUX_BALL_N2_SHIFT))\r
+#define PINMUX_BALL_N5_MASK (~(0xFF << PINMUX_BALL_N4_SHIFT))\r
+#define PINMUX_BALL_N15_MASK (~(0xFF << PINMUX_BALL_N15_SHIFT))\r
+#define PINMUX_BALL_N17_MASK (~(0xFF << PINMUX_BALL_N17_SHIFT))\r
+#define PINMUX_BALL_N19_MASK (~(0xFF << PINMUX_BALL_N19_SHIFT))\r
+#define PINMUX_BALL_P1_MASK (~(0xFF << PINMUX_BALL_P1_SHIFT))\r
+#define PINMUX_BALL_P5_MASK (~(0xFF << PINMUX_BALL_P4_SHIFT))\r
+#define PINMUX_BALL_R2_MASK (~(0xFF << PINMUX_BALL_R2_SHIFT))\r
+#define PINMUX_BALL_R5_MASK (~(0xFF << PINMUX_BALL_R5_SHIFT))\r
+#define PINMUX_BALL_R6_MASK (~(0xFF << PINMUX_BALL_R6_SHIFT))\r
+#define PINMUX_BALL_R7_MASK (~(0xFF << PINMUX_BALL_R7_SHIFT))\r
+#define PINMUX_BALL_R8_MASK (~(0xFF << PINMUX_BALL_R8_SHIFT))\r
+#define PINMUX_BALL_R9_MASK (~(0xFF << PINMUX_BALL_R9_SHIFT))\r
+#define PINMUX_BALL_T1_MASK (~(0xFF << PINMUX_BALL_T1_SHIFT))\r
+#define PINMUX_BALL_T12_MASK (~(0xFF << PINMUX_BALL_T12_SHIFT))\r
+#define PINMUX_BALL_U1_MASK (~(0xFF << PINMUX_BALL_U1_SHIFT))\r
+#define PINMUX_BALL_V2_MASK (~(0xFF << PINMUX_BALL_V2_SHIFT))\r
+#define PINMUX_BALL_V5_MASK (~(0xFF << PINMUX_BALL_V5_SHIFT))\r
+#define PINMUX_BALL_V6_MASK (~(0xFF << PINMUX_BALL_V6_SHIFT))\r
+#define PINMUX_BALL_V7_MASK (~(0xFF << PINMUX_BALL_V7_SHIFT))\r
+#define PINMUX_BALL_V10_MASK (~(0xFF << PINMUX_BALL_V10_SHIFT))\r
+#define PINMUX_BALL_W3_MASK (~(0xFF << PINMUX_BALL_W3_SHIFT))\r
+#define PINMUX_BALL_W5_MASK (~(0xFF << PINMUX_BALL_W5_SHIFT))\r
+#define PINMUX_BALL_W6_MASK (~(0xFF << PINMUX_BALL_W6_SHIFT))\r
+#define PINMUX_BALL_W9_MASK (~(0xFF << PINMUX_BALL_W9_SHIFT))\r
+#define PINMUX_BALL_W10_MASK (~(0xFF << PINMUX_BALL_W10_SHIFT))\r
+\r
+#define PINMUX_GATE_EMIF_CLK_MASK (~(0xFF << PINMUX_GATE_EMIF_CLK_SHIFT))\r
+#define PINMUX_GIOB_DISABLE_HET2_MASK (~(0xFF << PINMUX_GIOB_DISABLE_HET2_SHIFT))\r
+#define PINMUX_ALT_ADC_TRIGGER_MASK (~(0xFF << PINMUX_ALT_ADC_TRIGGER_SHIFT))\r
+#define PINMUX_ETHERNET_MASK (~(0xFF << PINMUX_ETHERNET_SHIFT))\r
+\r
+\r
+\r
+#define PINMUX_BALL_A5_GIOA_0 (0x1 << PINMUX_BALL_A5_SHIFT)\r
+#define PINMUX_BALL_A5_OHCI_PRT_RcvDpls_1 (0x2 << PINMUX_BALL_A5_SHIFT)\r
+#define PINMUX_BALL_A5_W2FC_RXDPI (0x4 << PINMUX_BALL_A5_SHIFT)\r
+\r
+#define PINMUX_BALL_A11_HET1_14 (0x1 << PINMUX_BALL_A11_SHIFT)\r
+#define PINMUX_BALL_A11_OHCI_RCFG_txSe0_0 (0x2 << PINMUX_BALL_A11_SHIFT)\r
+\r
+#define PINMUX_BALL_A14_HET1_26 (0x1 << PINMUX_BALL_A14_SHIFT)\r
+#define PINMUX_BALL_A14_MII_RXD_1 (0x2 << PINMUX_BALL_A14_SHIFT)\r
+#define PINMUX_BALL_A14_RMII_RXD_1 (0x4 << PINMUX_BALL_A14_SHIFT)\r
+\r
+#define PINMUX_BALL_B2_MIBSPI3NCS_2 (0x1 << PINMUX_BALL_B2_SHIFT)\r
+#define PINMUX_BALL_B2_I2C_SDA (0x2 << PINMUX_BALL_B2_SHIFT)\r
+#define PINMUX_BALL_B2_HET1_27 (0x4 << PINMUX_BALL_B2_SHIFT)\r
+\r
+#define PINMUX_BALL_B3_HET1_22 (0x1 << PINMUX_BALL_B3_SHIFT)\r
+#define PINMUX_BALL_B3_OHCI_RCFG_txSe0_1 (0x2 << PINMUX_BALL_B3_SHIFT)\r
+#define PINMUX_BALL_B3_W2FC_SE0O (0x4 << PINMUX_BALL_B3_SHIFT)\r
+\r
+#define PINMUX_BALL_B4_HET1_12 (0x1 << PINMUX_BALL_B4_SHIFT)\r
+#define PINMUX_BALL_B4_MII_CRS (0x2 << PINMUX_BALL_B4_SHIFT)\r
+#define PINMUX_BALL_B4_RMII_CRS_DV (0x4 << PINMUX_BALL_B4_SHIFT)\r
+\r
+#define PINMUX_BALL_B5_GIOA_5 (0x1 << PINMUX_BALL_B5_SHIFT)\r
+#define PINMUX_BALL_B5_EXTCLKIN (0x2 << PINMUX_BALL_B5_SHIFT)\r
+\r
+#define PINMUX_BALL_B6_MIBSPI5NCS_1 (0x1 << PINMUX_BALL_B6_SHIFT)\r
+#define PINMUX_BALL_B6_DMM_DATA_6 (0x2 << PINMUX_BALL_B6_SHIFT)\r
+\r
+#define PINMUX_BALL_B11_HET1_30 (0x1 << PINMUX_BALL_B11_SHIFT)\r
+#define PINMUX_BALL_B11_MII_RX_DV (0x2 << PINMUX_BALL_B11_SHIFT)\r
+#define PINMUX_BALL_B11_OHCI_RCFG_speed_0 (0x4 << PINMUX_BALL_B11_SHIFT)\r
+\r
+#define PINMUX_BALL_C1_GIOA_2 (0x1 << PINMUX_BALL_C1_SHIFT)\r
+#define PINMUX_BALL_C1_OHCI_RCFG_txdPls_1 (0x2 << PINMUX_BALL_C1_SHIFT)\r
+#define PINMUX_BALL_C1_W2FC_TXDO (0x4 << PINMUX_BALL_C1_SHIFT)\r
+#define PINMUX_BALL_C1_HET2_0 (0x8 << PINMUX_BALL_C1_SHIFT)\r
+\r
+#define PINMUX_BALL_C2_GIOA_1 (0x1 << PINMUX_BALL_C2_SHIFT)\r
+#define PINMUX_BALL_C2_OHCI_PRT_RcvDmns_1 (0x2 << PINMUX_BALL_C2_SHIFT)\r
+#define PINMUX_BALL_C2_W2FC_RXDMI (0x4 << PINMUX_BALL_C2_SHIFT)\r
+\r
+#define PINMUX_BALL_C3_MIBSPI3NCS_3 (0x1 << PINMUX_BALL_C3_SHIFT)\r
+#define PINMUX_BALL_C3_I2C_SCL (0x2 << PINMUX_BALL_C3_SHIFT)\r
+#define PINMUX_BALL_C3_HET1_29 (0x4 << PINMUX_BALL_C3_SHIFT)\r
+\r
+#define PINMUX_BALL_C4_EMIF_ADDR_6 (0x1 << PINMUX_BALL_C4_SHIFT)\r
+#define PINMUX_BALL_C4_RTP_DATA_13 (0x2 << PINMUX_BALL_C4_SHIFT)\r
+#define PINMUX_BALL_C4_HET2_11 (0x4 << PINMUX_BALL_C4_SHIFT)\r
+\r
+#define PINMUX_BALL_C5_EMIF_ADDR_7 (0x1 << PINMUX_BALL_C5_SHIFT)\r
+#define PINMUX_BALL_C5_RTP_DATA_12 (0x2 << PINMUX_BALL_C5_SHIFT)\r
+#define PINMUX_BALL_C5_HET2_13 (0x4 << PINMUX_BALL_C5_SHIFT)\r
+\r
+#define PINMUX_BALL_C6_EMIF_ADDR_8 (0x1 << PINMUX_BALL_C6_SHIFT)\r
+#define PINMUX_BALL_C6_RTP_DATA_11 (0x2 << PINMUX_BALL_C6_SHIFT)\r
+#define PINMUX_BALL_C6_HET2_15 (0x4 << PINMUX_BALL_C6_SHIFT)\r
+\r
+#define PINMUX_BALL_C7_EMIF_ADDR_9 (0x1 << PINMUX_BALL_C7_SHIFT)\r
+#define PINMUX_BALL_C7_RTP_DATA_10 (0x2 << PINMUX_BALL_C7_SHIFT)\r
+\r
+#define PINMUX_BALL_C8_EMIF_ADDR_10 (0x1 << PINMUX_BALL_C8_SHIFT)\r
+#define PINMUX_BALL_C8_RTP_DATA_09 (0x2 << PINMUX_BALL_C8_SHIFT)\r
+\r
+#define PINMUX_BALL_C9_EMIF_ADDR_11 (0x1 << PINMUX_BALL_C9_SHIFT)\r
+#define PINMUX_BALL_C9_RTP_DATA_08 (0x2 << PINMUX_BALL_C9_SHIFT)\r
+\r
+#define PINMUX_BALL_C10_EMIF_ADDR_12 (0x1 << PINMUX_BALL_C10_SHIFT)\r
+#define PINMUX_BALL_C10_RTP_DATA_06 (0x2 << PINMUX_BALL_C10_SHIFT)\r
+\r
+#define PINMUX_BALL_C11_EMIF_ADDR_13 (0x1 << PINMUX_BALL_C11_SHIFT)\r
+#define PINMUX_BALL_C11_RTP_DATA_05 (0x2 << PINMUX_BALL_C11_SHIFT)\r
+\r
+#define PINMUX_BALL_C12_EMIF_ADDR_14 (0x1 << PINMUX_BALL_C12_SHIFT)\r
+#define PINMUX_BALL_C12_RTP_DATA_04 (0x2 << PINMUX_BALL_C12_SHIFT)\r
+\r
+#define PINMUX_BALL_C13_EMIF_ADDR_15 (0x1 << PINMUX_BALL_C13_SHIFT)\r
+#define PINMUX_BALL_C13_RTP_DATA_03 (0x2 << PINMUX_BALL_C13_SHIFT)\r
+\r
+#define PINMUX_BALL_C14_EMIF_ADDR_17 (0x1 << PINMUX_BALL_C14_SHIFT)\r
+#define PINMUX_BALL_C14_RTP_DATA_01 (0x2 << PINMUX_BALL_C14_SHIFT)\r
+\r
+#define PINMUX_BALL_C15_EMIF_ADDR_19 (0x1 << PINMUX_BALL_C15_SHIFT)\r
+#define PINMUX_BALL_C15_RTP_nENA (0x2 << PINMUX_BALL_C15_SHIFT)\r
+\r
+#define PINMUX_BALL_C16_EMIF_ADDR_20 (0x1 << PINMUX_BALL_C16_SHIFT)\r
+#define PINMUX_BALL_C16_RTP_nSYNC (0x2 << PINMUX_BALL_C16_SHIFT)\r
+\r
+#define PINMUX_BALL_C17_EMIF_ADDR_21 (0x1 << PINMUX_BALL_C17_SHIFT)\r
+#define PINMUX_BALL_C17_RTP_CLK (0x2 << PINMUX_BALL_C17_SHIFT)\r
+\r
+#define PINMUX_BALL_D3_SPI2NENA (0x1 << PINMUX_BALL_D3_SHIFT)\r
+#define PINMUX_BALL_D3_SPI2NCS_1 (0x2 << PINMUX_BALL_D3_SHIFT)\r
+\r
+#define PINMUX_BALL_D4_EMIF_ADDR_0 (0x1 << PINMUX_BALL_D4_SHIFT)\r
+#define PINMUX_BALL_D4_HET2_1 (0x2 << PINMUX_BALL_D4_SHIFT)\r
+\r
+#define PINMUX_BALL_D5_EMIF_ADDR_1 (0x1 << PINMUX_BALL_D5_SHIFT)\r
+#define PINMUX_BALL_D5_HET2_3 (0x2 << PINMUX_BALL_D5_SHIFT)\r
+\r
+#define PINMUX_BALL_D14_EMIF_ADDR_16 (0x1 << PINMUX_BALL_D14_SHIFT)\r
+#define PINMUX_BALL_D14_RTP_DATA_02 (0x2 << PINMUX_BALL_D14_SHIFT)\r
+\r
+#define PINMUX_BALL_D15_EMIF_ADDR_18 (0x1 << PINMUX_BALL_D15_SHIFT)\r
+#define PINMUX_BALL_D15_RTP_DATA_0 (0x2 << PINMUX_BALL_D15_SHIFT)\r
+\r
+#define PINMUX_BALL_D16_EMIF_BA_1 (0x1 << PINMUX_BALL_D16_SHIFT)\r
+#define PINMUX_BALL_D16_HET2_5 (0x2 << PINMUX_BALL_D16_SHIFT)\r
+\r
+#define PINMUX_BALL_D17_EMIF_nWE (0x1 << PINMUX_BALL_D17_SHIFT)\r
+#define PINMUX_BALL_D17_EMIF_RNW (0x2 << PINMUX_BALL_D17_SHIFT)\r
+\r
+#define PINMUX_BALL_D19_HET1_10 (0x1 << PINMUX_BALL_D19_SHIFT)\r
+#define PINMUX_BALL_D19_MII_TX_CLK (0x2 << PINMUX_BALL_D19_SHIFT)\r
+#define PINMUX_BALL_D19_OHCI_RCFG_txEnL_0 (0x4 << PINMUX_BALL_D19_SHIFT)\r
+#define PINMUX_BALL_D19_MII_TX_AVCLK4 (0x8 << PINMUX_BALL_D19_SHIFT)\r
+\r
+#define PINMUX_BALL_E1_GIOA_3 (0x1 << PINMUX_BALL_E1_SHIFT)\r
+#define PINMUX_BALL_E1_HET2_2 (0x2 << PINMUX_BALL_E1_SHIFT)\r
+\r
+#define PINMUX_BALL_E3_HET1_11 (0x1 << PINMUX_BALL_E3_SHIFT)\r
+#define PINMUX_BALL_E3_MIBSPI3NCS_4 (0x2 << PINMUX_BALL_E3_SHIFT)\r
+#define PINMUX_BALL_E3_HET2_18 (0x4 << PINMUX_BALL_E3_SHIFT)\r
+#define PINMUX_BALL_E3_OHCI_PRT_OvrCurrent_1 (0x8 << PINMUX_BALL_E3_SHIFT)\r
+#define PINMUX_BALL_E3_W2FC_VBUSI (0x10 << PINMUX_BALL_E3_SHIFT)\r
+\r
+#define PINMUX_BALL_E5_ETMDATA_20 (0x1 << PINMUX_BALL_E5_SHIFT)\r
+#define PINMUX_BALL_E5_EMIF_DATA_4 (0x2 << PINMUX_BALL_E5_SHIFT)\r
+\r
+#define PINMUX_BALL_E6_ETMDATA_11 (0x1 << PINMUX_BALL_E6_SHIFT)\r
+#define PINMUX_BALL_E6_EMIF_ADDR_2 (0x2 << PINMUX_BALL_E6_SHIFT)\r
+\r
+#define PINMUX_BALL_E7_ETMDATA_10 (0x1 << PINMUX_BALL_E7_SHIFT)\r
+#define PINMUX_BALL_E7_EMIF_ADDR_3 (0x2 << PINMUX_BALL_E7_SHIFT)\r
+\r
+#define PINMUX_BALL_E8_ETMDATA_09 (0x1 << PINMUX_BALL_E8_SHIFT)\r
+#define PINMUX_BALL_E8_EMIF_ADDR_4 (0x2 << PINMUX_BALL_E8_SHIFT)\r
+\r
+#define PINMUX_BALL_E9_ETMDATA_08 (0x1 << PINMUX_BALL_E9_SHIFT)\r
+#define PINMUX_BALL_E9_EMIF_ADDR_5 (0x2 << PINMUX_BALL_E9_SHIFT)\r
+\r
+#define PINMUX_BALL_E10_ETMDATA_15 (0x1 << PINMUX_BALL_E10_SHIFT)\r
+#define PINMUX_BALL_E10_EMIF_nDQM_0 (0x2 << PINMUX_BALL_E10_SHIFT)\r
+\r
+#define PINMUX_BALL_E11_ETMDATA_14 (0x1 << PINMUX_BALL_E11_SHIFT)\r
+#define PINMUX_BALL_E11_EMIF_nDQM_1 (0x2 << PINMUX_BALL_E11_SHIFT)\r
+\r
+#define PINMUX_BALL_E12_ETMDATA_13 (0x1 << PINMUX_BALL_E12_SHIFT)\r
+#define PINMUX_BALL_E12_EMIF_nOE (0x2 << PINMUX_BALL_E12_SHIFT)\r
+\r
+#define PINMUX_BALL_E13_ETMDATA_12 (0x1 << PINMUX_BALL_E13_SHIFT)\r
+#define PINMUX_BALL_E13_EMIF_BA_0 (0x2 << PINMUX_BALL_E13_SHIFT)\r
+\r
+#define PINMUX_BALL_E16_MIBSPI5SIMO_1 (0x1 << PINMUX_BALL_E16_SHIFT)\r
+#define PINMUX_BALL_E16_DMM_DATA_9 (0x2 << PINMUX_BALL_E16_SHIFT)\r
+\r
+#define PINMUX_BALL_E17_MIBSPI5SOMI_1 (0x1 << PINMUX_BALL_E17_SHIFT)\r
+#define PINMUX_BALL_E17_DMM_DATA_13 (0x2 << PINMUX_BALL_E17_SHIFT)\r
+\r
+#define PINMUX_BALL_E18_HET1_08 (0x1 << PINMUX_BALL_E18_SHIFT)\r
+#define PINMUX_BALL_E18_MIBSPI1SIMO_1 (0x2 << PINMUX_BALL_E18_SHIFT)\r
+#define PINMUX_BALL_E18_MII_TXD_3 (0x4 << PINMUX_BALL_E18_SHIFT)\r
+#define PINMUX_BALL_E18_OHCI_PRT_OvrCurrent_0 (0x8 << PINMUX_BALL_E18_SHIFT)\r
+\r
+#define PINMUX_BALL_E19_MIBSPI5NCS_0 (0x1 << PINMUX_BALL_E19_SHIFT)\r
+#define PINMUX_BALL_E19_DMM_DATA_5 (0x2 << PINMUX_BALL_E19_SHIFT)\r
+\r
+#define PINMUX_BALL_F3_MIBSPI1NCS_1 (0x1 << PINMUX_BALL_F3_SHIFT)\r
+#define PINMUX_BALL_F3_HET1_17 (0x2 << PINMUX_BALL_F3_SHIFT)\r
+#define PINMUX_BALL_F3_MII_COL (0x4 << PINMUX_BALL_F3_SHIFT)\r
+#define PINMUX_BALL_F3_OHCI_RCFG_suspend_0 (0x8 << PINMUX_BALL_F3_SHIFT)\r
+\r
+#define PINMUX_BALL_F5_ETMDATA_21 (0x1 << PINMUX_BALL_F5_SHIFT)\r
+#define PINMUX_BALL_F5_EMIF_DATA_5 (0x2 << PINMUX_BALL_F5_SHIFT)\r
+\r
+#define PINMUX_BALL_G3_MIBSPI1NCS_2 (0x1 << PINMUX_BALL_G3_SHIFT)\r
+#define PINMUX_BALL_G3_HET1_19 (0x2 << PINMUX_BALL_G3_SHIFT)\r
+#define PINMUX_BALL_G3_MDIO (0x4 << PINMUX_BALL_G3_SHIFT)\r
+\r
+#define PINMUX_BALL_G5_ETMDATA_22 (0x1 << PINMUX_BALL_G5_SHIFT)\r
+#define PINMUX_BALL_G5_EMIF_DATA_6 (0x2 << PINMUX_BALL_G5_SHIFT)\r
+\r
+#define PINMUX_BALL_G16_MIBSPI5SOMI_3 (0x1 << PINMUX_BALL_G16_SHIFT)\r
+#define PINMUX_BALL_G16_DMM_DATA_15 (0x2 << PINMUX_BALL_G16_SHIFT)\r
+\r
+#define PINMUX_BALL_G17_MIBSPI5SIMO_3 (0x1 << PINMUX_BALL_G17_SHIFT)\r
+#define PINMUX_BALL_G17_DMM_DATA_11 (0x2 << PINMUX_BALL_G17_SHIFT)\r
+\r
+#define PINMUX_BALL_G19_MIBSPI1NENA (0x1 << PINMUX_BALL_G19_SHIFT)\r
+#define PINMUX_BALL_G19_HET1_23 (0x2 << PINMUX_BALL_G19_SHIFT)\r
+#define PINMUX_BALL_G19_MII_RXD_2 (0x4 << PINMUX_BALL_G19_SHIFT)\r
+#define PINMUX_BALL_G19_OHCI_PRT_RcvDpls_0 (0x8 << PINMUX_BALL_G19_SHIFT)\r
+\r
+#define PINMUX_BALL_H3_GIOA_6 (0x1 << PINMUX_BALL_H3_SHIFT)\r
+#define PINMUX_BALL_H3_HET2_4 (0x2 << PINMUX_BALL_H3_SHIFT)\r
+\r
+#define PINMUX_BALL_H16_MIBSPI5SOMI_2 (0x1 << PINMUX_BALL_H16_SHIFT)\r
+#define PINMUX_BALL_H16_DMM_DATA_14 (0x2 << PINMUX_BALL_H16_SHIFT)\r
+\r
+#define PINMUX_BALL_H17_MIBSPI5SIMO_2 (0x1 << PINMUX_BALL_H17_SHIFT)\r
+#define PINMUX_BALL_H17_DMM_DATA_10 (0x2 << PINMUX_BALL_H17_SHIFT)\r
+\r
+#define PINMUX_BALL_H18_MIBSPI5NENA (0x1 << PINMUX_BALL_H18_SHIFT)\r
+#define PINMUX_BALL_H18_DMM_DATA_7 (0x2 << PINMUX_BALL_H18_SHIFT)\r
+#define PINMUX_BALL_H18_MII_RXD_3 (0x4 << PINMUX_BALL_H18_SHIFT)\r
+#define PINMUX_BALL_H18_OHCI_PRT_RcvDmns_0 (0x8 << PINMUX_BALL_H18_SHIFT)\r
+\r
+#define PINMUX_BALL_H19_MIBSPI5CLK (0x1 << PINMUX_BALL_H19_SHIFT)\r
+#define PINMUX_BALL_H19_DMM_DATA_4 (0x2 << PINMUX_BALL_H19_SHIFT)\r
+#define PINMUX_BALL_H19_MII_TXEN (0x4 << PINMUX_BALL_H19_SHIFT)\r
+#define PINMUX_BALL_H19_RMII_TXEN (0x8 << PINMUX_BALL_H19_SHIFT)\r
+\r
+#define PINMUX_BALL_J3_MIBSPI1NCS_3 (0x1 << PINMUX_BALL_J3_SHIFT)\r
+#define PINMUX_BALL_J3_HET1_21 (0x2 << PINMUX_BALL_J3_SHIFT)\r
+\r
+#define PINMUX_BALL_J18_MIBSPI5SOMI_0 (0x1 << PINMUX_BALL_J18_SHIFT)\r
+#define PINMUX_BALL_J18_DMM_DATA_12 (0x2 << PINMUX_BALL_J18_SHIFT)\r
+#define PINMUX_BALL_J18_MII_TXD_0 (0x4 << PINMUX_BALL_J18_SHIFT)\r
+#define PINMUX_BALL_J18_RMII_TXD_0 (0x8 << PINMUX_BALL_J18_SHIFT)\r
+\r
+#define PINMUX_BALL_J19_MIBSPI5SIMO_0 (0x1 << PINMUX_BALL_J19_SHIFT)\r
+#define PINMUX_BALL_J19_DMM_DATA_8 (0x2 << PINMUX_BALL_J19_SHIFT)\r
+#define PINMUX_BALL_J19_MII_TXD_1 (0x4 << PINMUX_BALL_J19_SHIFT)\r
+#define PINMUX_BALL_J19_RMII_TXD_1 (0x8 << PINMUX_BALL_J19_SHIFT)\r
+\r
+#define PINMUX_BALL_K2_GIOB_1 (0x1 << PINMUX_BALL_K2_SHIFT)\r
+#define PINMUX_BALL_K2_OHCI_RCFG_PrtPower_0 (0x2 << PINMUX_BALL_K2_SHIFT)\r
+\r
+#define PINMUX_BALL_K5_ETMDATA_23 (0x1 << PINMUX_BALL_K5_SHIFT)\r
+#define PINMUX_BALL_K5_EMIF_DATA_7 (0x2 << PINMUX_BALL_K5_SHIFT)\r
+\r
+#define PINMUX_BALL_K15_ETMDATA_16 (0x1 << PINMUX_BALL_K15_SHIFT)\r
+#define PINMUX_BALL_K15_EMIF_DATA_0 (0x2 << PINMUX_BALL_K15_SHIFT)\r
+\r
+#define PINMUX_BALL_K17_EMIF_nCS_3 (0x1 << PINMUX_BALL_K17_SHIFT)\r
+#define PINMUX_BALL_K17_RTP_DATA_14 (0x2 << PINMUX_BALL_K17_SHIFT)\r
+#define PINMUX_BALL_K17_HET2_9 (0x4 << PINMUX_BALL_K17_SHIFT)\r
+\r
+#define PINMUX_BALL_K18_HET1_0 (0x1 << PINMUX_BALL_K18_SHIFT)\r
+#define PINMUX_BALL_K18_SPI4CLK (0x2 << PINMUX_BALL_K18_SHIFT)\r
+\r
+#define PINMUX_BALL_K19_HET1_28 (0x1 << PINMUX_BALL_K19_SHIFT)\r
+#define PINMUX_BALL_K19_MII_RXCLK (0x2 << PINMUX_BALL_K19_SHIFT)\r
+#define PINMUX_BALL_K19_RMII_REFCLK (0x4 << PINMUX_BALL_K19_SHIFT)\r
+#define PINMUX_BALL_K19_MII_RX_AVCLK4 (0x8 << PINMUX_BALL_K19_SHIFT)\r
+\r
+#define PINMUX_BALL_L5_ETMDATA_24 (0x1 << PINMUX_BALL_L5_SHIFT)\r
+#define PINMUX_BALL_L5_EMIF_DATA_8 (0x2 << PINMUX_BALL_L5_SHIFT)\r
+\r
+#define PINMUX_BALL_L15_ETMDATA_17 (0x1 << PINMUX_BALL_L15_SHIFT)\r
+#define PINMUX_BALL_L15_EMIF_DATA_1 (0x2 << PINMUX_BALL_L15_SHIFT)\r
+\r
+#define PINMUX_BALL_M1_GIOA_7 (0x1 << PINMUX_BALL_M1_SHIFT)\r
+#define PINMUX_BALL_M1_HET2_6 (0x2 << PINMUX_BALL_M1_SHIFT)\r
+\r
+#define PINMUX_BALL_M2_GIOB_0 (0x1 << PINMUX_BALL_M2_SHIFT)\r
+#define PINMUX_BALL_M2_OHCI_RCFG_txDpls_0 (0x2 << PINMUX_BALL_M2_SHIFT)\r
+\r
+#define PINMUX_BALL_M5_ETMDATA_25 (0x1 << PINMUX_BALL_M5_SHIFT)\r
+#define PINMUX_BALL_M5_EMIF_DATA_9 (0x2 << PINMUX_BALL_M5_SHIFT)\r
+\r
+#define PINMUX_BALL_M15_ETMDATA_18 (0x1 << PINMUX_BALL_M15_SHIFT)\r
+#define PINMUX_BALL_M15_EMIF_DATA_2 (0x2 << PINMUX_BALL_M15_SHIFT)\r
+\r
+#define PINMUX_BALL_M17_EMIF_nCS_4 (0x1 << PINMUX_BALL_M17_SHIFT)\r
+#define PINMUX_BALL_M17_RTP_DATA_07 (0x2 << PINMUX_BALL_M17_SHIFT)\r
+\r
+#define PINMUX_BALL_N1_HET1_15 (0x1 << PINMUX_BALL_N1_SHIFT)\r
+#define PINMUX_BALL_N1_MIBSPI1NCS_4 (0x2 << PINMUX_BALL_N1_SHIFT)\r
+\r
+#define PINMUX_BALL_N2_HET1_13 (0x1 << PINMUX_BALL_N2_SHIFT)\r
+#define PINMUX_BALL_N2_SCITX (0x2 << PINMUX_BALL_N2_SHIFT)\r
+\r
+#define PINMUX_BALL_N5_ETMDATA_26 (0x1 << PINMUX_BALL_N5_SHIFT)\r
+#define PINMUX_BALL_N5_EMIF_DATA_10 (0x2 << PINMUX_BALL_N5_SHIFT)\r
+\r
+#define PINMUX_BALL_N15_ETMDATA_19 (0x1 << PINMUX_BALL_N15_SHIFT)\r
+#define PINMUX_BALL_N15_EMIF_DATA_3 (0x2 << PINMUX_BALL_N15_SHIFT)\r
+\r
+#define PINMUX_BALL_N17_EMIF_nCS_0 (0x1 << PINMUX_BALL_N17_SHIFT)\r
+#define PINMUX_BALL_N17_RTP_DATA_15 (0x2 << PINMUX_BALL_N17_SHIFT)\r
+#define PINMUX_BALL_N17_HET2_7 (0x4 << PINMUX_BALL_N17_SHIFT)\r
+\r
+#define PINMUX_BALL_N19_AD1EVT (0x1 << PINMUX_BALL_N19_SHIFT)\r
+#define PINMUX_BALL_N19_MII_RX_ER (0x2 << PINMUX_BALL_N19_SHIFT)\r
+#define PINMUX_BALL_N19_RMII_RX_ER (0x4 << PINMUX_BALL_N19_SHIFT)\r
+\r
+#define PINMUX_BALL_P1_HET1_24 (0x1 << PINMUX_BALL_P1_SHIFT)\r
+#define PINMUX_BALL_P1_MIBSPI1NCS_5 (0x2 << PINMUX_BALL_P1_SHIFT)\r
+#define PINMUX_BALL_P1_MII_RXD_0 (0x4 << PINMUX_BALL_P1_SHIFT)\r
+#define PINMUX_BALL_P1_RMII_RXD_0 (0x8 << PINMUX_BALL_P1_SHIFT)\r
+\r
+#define PINMUX_BALL_P5_ETMDATA_27 (0x1 << PINMUX_BALL_P5_SHIFT)\r
+#define PINMUX_BALL_P5_EMIF_DATA_11 (0x2 << PINMUX_BALL_P5_SHIFT)\r
+\r
+#define PINMUX_BALL_R2_MIBSPI1NCS_0 (0x1 << PINMUX_BALL_R2_SHIFT)\r
+#define PINMUX_BALL_R2_MIBSPI1SOMI_1 (0x2 << PINMUX_BALL_R2_SHIFT)\r
+#define PINMUX_BALL_R2_MII_TXD_2 (0x4 << PINMUX_BALL_R2_SHIFT)\r
+#define PINMUX_BALL_R2_OHCI_PRT_RcvData_0 (0x8 << PINMUX_BALL_R2_SHIFT)\r
+\r
+#define PINMUX_BALL_R5_ETMDATA_28 (0x1 << PINMUX_BALL_R5_SHIFT)\r
+#define PINMUX_BALL_R5_EMIF_DATA_12 (0x2 << PINMUX_BALL_R5_SHIFT)\r
+\r
+#define PINMUX_BALL_R6_ETMDATA_29 (0x1 << PINMUX_BALL_R6_SHIFT)\r
+#define PINMUX_BALL_R6_EMIF_DATA_13 (0x2 << PINMUX_BALL_R6_SHIFT)\r
+\r
+#define PINMUX_BALL_R7_ETMDATA_30 (0x1 << PINMUX_BALL_R7_SHIFT)\r
+#define PINMUX_BALL_R7_EMIF_DATA_14 (0x2 << PINMUX_BALL_R7_SHIFT)\r
+ \r
+#define PINMUX_BALL_R8_ETMDATA_31 (0x1 << PINMUX_BALL_R8_SHIFT)\r
+#define PINMUX_BALL_R8_EMIF_DATA_15 (0x2 << PINMUX_BALL_R8_SHIFT)\r
+\r
+#define PINMUX_BALL_R9_ETMTRACECLKIN (0x1 << PINMUX_BALL_R9_SHIFT)\r
+#define PINMUX_BALL_R9_EXTCLKIN2 (0x2 << PINMUX_BALL_R9_SHIFT)\r
+\r
+#define PINMUX_BALL_T1_HET1_07 (0x1 << PINMUX_BALL_T1_SHIFT)\r
+#define PINMUX_BALL_T1_OHCI_RCFG_PrtPower_1 (0x2 << PINMUX_BALL_T1_SHIFT)\r
+#define PINMUX_BALL_T1_W2FC_GZO (0x4 << PINMUX_BALL_T1_SHIFT)\r
+#define PINMUX_BALL_T1_HET2_14 (0x8 << PINMUX_BALL_T1_SHIFT)\r
+\r
+#define PINMUX_BALL_T12_MIBSPI5NCS_3 (0x1 << PINMUX_BALL_T12_SHIFT)\r
+#define PINMUX_BALL_T12_DMM_DATA_3 (0x2 << PINMUX_BALL_T12_SHIFT)\r
+\r
+#define PINMUX_BALL_U1_HET1_03 (0x1 << PINMUX_BALL_U1_SHIFT)\r
+#define PINMUX_BALL_U1_SPI4NCS_0 (0x2 << PINMUX_BALL_U1_SHIFT)\r
+#define PINMUX_BALL_U1_OHCI_RCFG_speed_1 (0x4 << PINMUX_BALL_U1_SHIFT)\r
+#define PINMUX_BALL_U1_W2FC_PUENON (0x8 << PINMUX_BALL_U1_SHIFT)\r
+#define PINMUX_BALL_U1_HET2_10 (0x10 << PINMUX_BALL_U1_SHIFT)\r
+\r
+#define PINMUX_BALL_V2_HET1_01 (0x1 << PINMUX_BALL_V2_SHIFT)\r
+#define PINMUX_BALL_V2_SPI4NENA (0x2 << PINMUX_BALL_V2_SHIFT)\r
+#define PINMUX_BALL_V2_OHCI_RCFG_txEnL_1 (0x4 << PINMUX_BALL_V2_SHIFT)\r
+#define PINMUX_BALL_V2_W2FC_PUENO (0x8 << PINMUX_BALL_V2_SHIFT)\r
+#define PINMUX_BALL_V2_HET2_8 (0x10 << PINMUX_BALL_V2_SHIFT)\r
+\r
+#define PINMUX_BALL_V5_MIBSPI3NCS_1 (0x1 << PINMUX_BALL_V5_SHIFT)\r
+#define PINMUX_BALL_V5_HET1_25 (0x2 << PINMUX_BALL_V5_SHIFT)\r
+#define PINMUX_BALL_V5_MDCLK (0x4 << PINMUX_BALL_V5_SHIFT)\r
+\r
+#define PINMUX_BALL_V6_HET1_05 (0x1 << PINMUX_BALL_V6_SHIFT)\r
+#define PINMUX_BALL_V6_SPI4SOMI (0x2 << PINMUX_BALL_V6_SHIFT)\r
+#define PINMUX_BALL_V6_HET2_12 (0x4 << PINMUX_BALL_V6_SHIFT)\r
+\r
+#define PINMUX_BALL_V7_HET1_09 (0x1 << PINMUX_BALL_V7_SHIFT)\r
+#define PINMUX_BALL_V7_HET2_16 (0x2 << PINMUX_BALL_V7_SHIFT)\r
+#define PINMUX_BALL_V7_OHCI_RCFG_suspend_1 (0x4 << PINMUX_BALL_V7_SHIFT)\r
+#define PINMUX_BALL_V7_W2FC_SUSPENDO (0x8 << PINMUX_BALL_V7_SHIFT)\r
+\r
+#define PINMUX_BALL_V10_MIBSPI3NCS_0 (0x1 << PINMUX_BALL_V10_SHIFT)\r
+#define PINMUX_BALL_V10_AD2EVT (0x2 << PINMUX_BALL_V10_SHIFT)\r
+#define PINMUX_BALL_V10_GIOB_2 (0x4 << PINMUX_BALL_V10_SHIFT)\r
+\r
+#define PINMUX_BALL_W3_HET1_06 (0x1 << PINMUX_BALL_W3_SHIFT)\r
+#define PINMUX_BALL_W3_SCIRX (0x2 << PINMUX_BALL_W3_SHIFT)\r
+\r
+#define PINMUX_BALL_W5_HET1_02 (0x1 << PINMUX_BALL_W5_SHIFT)\r
+#define PINMUX_BALL_W5_SPI4SIMO (0x2 << PINMUX_BALL_W5_SHIFT)\r
+\r
+#define PINMUX_BALL_W6_MIBSPI5NCS_2 (0x1 << PINMUX_BALL_W6_SHIFT)\r
+#define PINMUX_BALL_W6_DMM_DATA_2 (0x2 << PINMUX_BALL_W6_SHIFT)\r
+\r
+#define PINMUX_BALL_W9_MIBSPI3NENA (0x1 << PINMUX_BALL_W9_SHIFT)\r
+#define PINMUX_BALL_W9_MIBSPI3NCS_5 (0x2 << PINMUX_BALL_W9_SHIFT)\r
+#define PINMUX_BALL_W9_HET1_31 (0x4 << PINMUX_BALL_W9_SHIFT)\r
+\r
+#define PINMUX_BALL_W10_GIOB_3 (0x1 << PINMUX_BALL_W10_SHIFT)\r
+#define PINMUX_BALL_W10_OHCI_PRT_RcvData_1 (0x2 << PINMUX_BALL_W10_SHIFT)\r
+#define PINMUX_BALL_W10_W2FC_RXDI (0x4 << PINMUX_BALL_W10_SHIFT)\r
+\r
+#define PINMUX_GATE_EMIF_CLK (0x0 << PINMUX_GATE_EMIF_CLK_SHIFT) /**/ \r
+#define PINMUX_GIOB_DISABLE_HET2 (0x1 << PINMUX_GIOB_DISABLE_HET2_SHIFT)\r
+#define PINMUX_ALT_ADC_TRIGGER_1 (0x1 << PINMUX_ALT_ADC_TRIGGER_SHIFT)\r
+#define PINMUX_ALT_ADC_TRIGGER_2 (0x2 << PINMUX_ALT_ADC_TRIGGER_SHIFT)\r
+#define PINMUX_ETHERNET_MII (0x0 << PINMUX_ETHERNET_SHIFT)\r
+#define PINMUX_ETHERNET_RMII (0x1 << PINMUX_ETHERNET_SHIFT)\r
+\r
+/** @struct pinMuxKicker\r
+* @brief Pin Muxing Kicker Register Definition\r
+*\r
+* This structure is used to access the Pin Muxing Kicker registers.\r
+*/\r
+typedef volatile struct pinMuxKicker\r
+{\r
+ uint32_t KICKER0; /* kicker 0 register */\r
+ uint32_t KICKER1; /* kicker 1 register */\r
+} pinMuxKICKER_t;\r
+\r
+/** @struct pinMuxBase\r
+* @brief PINMUX Register Definition\r
+*\r
+* This structure is used to access the PINMUX module egisters.\r
+*/\r
+/** @typedef pinMuxBASE_t\r
+* @brief PINMUX Register Frame Type Definition\r
+*\r
+* This type is used to access the PINMUX Registers.\r
+*/\r
+typedef volatile struct pinMuxBase\r
+{\r
+ uint32_t PINMUX0; /**< 0xEB10 Pin Mux 0 register*/\r
+ uint32_t PINMUX1; /**< 0xEB14 Pin Mux 1 register*/\r
+ uint32_t PINMUX2; /**< 0xEB18 Pin Mux 2 register*/\r
+ uint32_t PINMUX3; /**< 0xEB1C Pin Mux 3 register*/\r
+ uint32_t PINMUX4; /**< 0xEB20 Pin Mux 4 register*/\r
+ uint32_t PINMUX5; /**< 0xEB24 Pin Mux 5 register*/\r
+ uint32_t PINMUX6; /**< 0xEB28 Pin Mux 6 register*/\r
+ uint32_t PINMUX7; /**< 0xEB2C Pin Mux 7 register*/\r
+ uint32_t PINMUX8; /**< 0xEB30 Pin Mux 8 register*/\r
+ uint32_t PINMUX9; /**< 0xEB34 Pin Mux 9 register*/\r
+ uint32_t PINMUX10; /**< 0xEB38 Pin Mux 10 register*/\r
+ uint32_t PINMUX11; /**< 0xEB3C Pin Mux 11 register*/\r
+ uint32_t PINMUX12; /**< 0xEB40 Pin Mux 12 register*/\r
+ uint32_t PINMUX13; /**< 0xEB44 Pin Mux 13 register*/\r
+ uint32_t PINMUX14; /**< 0xEB48 Pin Mux 14 register*/\r
+ uint32_t PINMUX15; /**< 0xEB4C Pin Mux 15 register*/\r
+ uint32_t PINMUX16; /**< 0xEB50 Pin Mux 16 register*/\r
+ uint32_t PINMUX17; /**< 0xEB54 Pin Mux 17 register*/\r
+ uint32_t PINMUX18; /**< 0xEB58 Pin Mux 18 register*/\r
+ uint32_t PINMUX19; /**< 0xEB5C Pin Mux 19 register*/\r
+ uint32_t PINMUX20; /**< 0xEB60 Pin Mux 20 register*/\r
+ uint32_t PINMUX21; /**< 0xEB64 Pin Mux 21 register*/\r
+ uint32_t PINMUX22; /**< 0xEB68 Pin Mux 22 register*/\r
+ uint32_t PINMUX23; /**< 0xEB6C Pin Mux 23 register*/\r
+ uint32_t PINMUX24; /**< 0xEB70 Pin Mux 24 register*/\r
+ uint32_t PINMUX25; /**< 0xEB74 Pin Mux 25 register*/\r
+ uint32_t PINMUX26; /**< 0xEB78 Pin Mux 26 register*/\r
+ uint32_t PINMUX27; /**< 0xEB7C Pin Mux 27 register*/\r
+ uint32_t PINMUX28; /**< 0xEB80 Pin Mux 28 register*/\r
+ uint32_t PINMUX29; /**< 0xEB84 Pin Mux 29 register*/\r
+ uint32_t PINMUX30; /**< 0xEB88 Pin Mux 30 register*/\r
+}pinMuxBASE_t;\r
+\r
+ \r
+/** @def kickerReg\r
+* @brief Pin Muxing Kicker Register Frame Pointer\r
+*\r
+* This pointer is used to enable and disable muxing accross the device.\r
+*/ \r
+#define kickerReg ((pinMuxKICKER_t *) 0xFFFFEA38)\r
+\r
+/** @def pinMuxReg\r
+* @brief Pin Muxing Control Register Frame Pointer\r
+*\r
+* This pointer is used to set the muxing registers accross the device.\r
+*/ \r
+#define pinMuxReg ((pinMuxBASE_t *) 0xFFFFEB10)\r
+\r
+/* PINMUX Interface Functions */\r
+void muxInit(void);\r
+\r
+#endif\r
--- /dev/null
+/** @file pom.h\r
+* @brief POM Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#include "sys_common.h"\r
+\r
+#ifndef __POM_H__\r
+#define __POM_H__\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/** @enum pom_region_size\r
+* @brief Alias names for pom region size\r
+* This enumeration is used to provide alias names for POM region size:\r
+*/\r
+enum pom_region_size\r
+{\r
+ SIZE_32BYTES = 0,\r
+ SIZE_64BYTES = 1,\r
+ SIZE_128BYTES = 2,\r
+ SIZE_256BYTES = 3,\r
+ SIZE_512BYTES = 4,\r
+ SIZE_1KB = 5,\r
+ SIZE_2KB = 6,\r
+ SIZE_4KB = 7,\r
+ SIZE_8KB = 8,\r
+ SIZE_16KB = 9,\r
+ SIZE_32KB = 10,\r
+ SIZE_64KB = 11,\r
+ SIZE_128KB = 12,\r
+ SIZE_256KB = 13\r
+};\r
+\r
+/** @def INTERNAL_RAM \r
+* @brief Alias name for Internal RAM\r
+*/ \r
+#define INTERNAL_RAM 0x08000000U\r
+\r
+/** @def SDRAM \r
+* @brief Alias name for SD RAM\r
+*/ \r
+#define SDRAM 0x80000000U\r
+\r
+/** @def ASYNC_MEMORY \r
+* @brief Alias name for Async RAM\r
+*/ \r
+#define ASYNC_MEMORY 0x60000000\r
+\r
+\r
+typedef uint32_t REGION;\r
+\r
+/** @struct REGION_CONFIG_ST\r
+* @brief POM region configuration\r
+*/\r
+typedef struct\r
+{ \r
+ uint32_t Prog_Reg_Sta_Addr;\r
+ uint32_t Ovly_Reg_Sta_Addr;\r
+ uint32_t Reg_Size;\r
+}REGION_CONFIG_ST;\r
+\r
+/** @struct POMBase\r
+* @brief POM Register Frame Definition\r
+*\r
+* This structure is used to access the POM module registers(POM Register Map).\r
+*/\r
+typedef struct\r
+{\r
+ uint32_t POMGLBCTRL_UL; /* 0x00 */\r
+ uint32_t POMREV_UL; /* 0x04 */\r
+ uint32_t POMCLKCTRL_UL; /* 0x08 */\r
+ uint32_t POMFLG_UL; /* 0x0C */\r
+ struct\r
+ {\r
+ uint32_t Reserved_Reg_B32: 32;\r
+ }RESERVED_REG[124];\r
+ struct /* 0x200 ... */\r
+ {\r
+ uint32_t POMPROGSTART_UL; \r
+ uint32_t POMOVLSTART_UL; \r
+ uint32_t POMREGSIZE_UL; \r
+ uint32_t : 32; \r
+ }POMRGNCONF_ST[32];\r
+}pomBASE_t;\r
+\r
+\r
+/** @struct POM_CORESIGHT_ST\r
+* @brief POM_CORESIGHT_ST Register Definition\r
+*\r
+* This structure is used to access the POM module registers(POM CoreSight Registers ).\r
+*/\r
+typedef struct\r
+{\r
+ uint32_t POMITCTRL_UL; /* 0xF00 */\r
+ struct /* 0xF04 to 0xF9C */ \r
+ {\r
+ uint32_t Reserved_Reg_UL;\r
+ }Reserved1_ST[39];\r
+ uint32_t POMCLAIMSET_UL; /* 0xFA0 */\r
+ uint32_t POMCLAIMCLR_UL; /* 0xFA4 */\r
+ uint32_t : 32; /* 0xFA8 */\r
+ uint32_t : 32; /* 0xFAC */\r
+ uint32_t POMLOCKACCESS_UL; /* 0xFB0 */\r
+ uint32_t POMLOCKSTATUS_UL; /* 0xFB4 */\r
+ uint32_t POMAUTHSTATUS_UL; /* 0xFB8 */\r
+ uint32_t : 32; /* 0xFBC */\r
+ uint32_t : 32; /* 0xFC0 */\r
+ uint32_t : 32; /* 0xFC4 */\r
+ uint32_t POMDEVID_UL; /* 0xFC8 */\r
+ uint32_t POMDEVTYPE_UL; /* 0xFCC */\r
+ uint32_t POMPERIPHERALID4_UL; /* 0xFD0 */\r
+ uint32_t POMPERIPHERALID5_UL; /* 0xFD4 */\r
+ uint32_t POMPERIPHERALID6_UL; /* 0xFD8 */\r
+ uint32_t POMPERIPHERALID7_UL; /* 0xFDC */\r
+ uint32_t POMPERIPHERALID0_UL; /* 0xFE0 */\r
+ uint32_t POMPERIPHERALID1_UL; /* 0xFE4 */\r
+ uint32_t POMPERIPHERALID2_UL; /* 0xFE8 */\r
+ uint32_t POMPERIPHERALID3_UL; /* 0xFEC */ \r
+ uint32_t POMCOMPONENTID0_UL; /* 0xFF0 */\r
+ uint32_t POMCOMPONENTID1_UL; /* 0xFF4 */\r
+ uint32_t POMCOMPONENTID2_UL; /* 0xFF8 */\r
+ uint32_t POMCOMPONENTID3_UL; /* 0xFFC */\r
+}POM_CORESIGHT_ST;\r
+\r
+\r
+#define pomREG ((pomBASE_t *)0xFFA04000U)\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+/* POM Interface Functions */\r
+void POM_Init(void);\r
+void POM_Disable(void);\r
+void POM_Reset(void);\r
+\r
+#endif /* __POM_H_*/\r
--- /dev/null
+/** @file rtp.h\r
+* @brief RTP Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __RTP_H__\r
+#define __RTP_H__\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+\r
+/** @struct rtpBase\r
+* @brief RTP Base Register Definition\r
+*\r
+* This structure is used to access the RTP module egisters.\r
+*/\r
+/** @typedef rtpBASE_t\r
+* @brief RTP Register Frame Type Definition\r
+*\r
+* This type is used to access the RTP Registers.\r
+*/\r
+typedef volatile struct rtpBase\r
+{\r
+ uint32_t GLBCTRL; /**< 0x0000: RTP Global Control Register */\r
+ uint32_t TRENA; /**< 0x0004: RTP Trace Enable Register */ \r
+ uint32_t GSR; /**< 0x0008: RTP Global Status Register */\r
+ uint32_t RAM1REG1; /**< 0x000C: RTP RAM 1 Trace Region 1 Register */\r
+ uint32_t RAM1REG2; /**< 0x0010: RTP RAM 1 Trace Region 2 Register */\r
+ uint32_t RAM2REG1; /**< 0x0014: RTP RAM 2 Trace Region 1 Register */\r
+ uint32_t RAM2REG2; /**< 0x0018: RTP RAM 2 Trace Region 2 Register */\r
+ uint32_t : 32; /**< 0x001C: Reserved */\r
+ uint32_t : 32; /**< 0x0020: Reserved */\r
+ uint32_t ERREG1; /**< 0x0024: RTP Peripheral Trace Region 1 Register */\r
+ uint32_t ERREG2; /**< 0x0028: RTP Peripheral Trace Region 2 Register */\r
+ uint32_t DDMW; /**< 0x002C: RTP Direct Data Mode Write Register */\r
+ uint32_t : 32; /**< 0x0030: Reserved */\r
+ uint32_t PC0; /**< 0x0034: RTP Pin Control 0 Register */\r
+ uint32_t PC1; /**< 0x0038: RTP Pin Control 1 Register */\r
+ uint32_t PC2; /**< 0x003C: RTP Pin Control 2 Register */\r
+ uint32_t PC3; /**< 0x0040: RTP Pin Control 3 Register */\r
+ uint32_t PC4; /**< 0x0044: RTP Pin Control 4 Register */\r
+ uint32_t PC5; /**< 0x0048: RTP Pin Control 5 Register */\r
+ uint32_t PC6; /**< 0x004C: RTP Pin Control 6 Register */\r
+ uint32_t PC7; /**< 0x0050: RTP Pin Control 7 Register */\r
+ uint32_t PC8; /**< 0x0054: RTP Pin Control 8 Register */\r
+} rtpBASE_t;\r
+\r
+\r
+/** @def rtpREG\r
+* @brief RTP Register Frame Pointer\r
+*\r
+* This pointer is used by the RTP driver to access the RTP module registers.\r
+*/\r
+#define rtpREG ((rtpBASE_t *)0xFFFFFA00U)\r
+\r
+/** @def rtpPORT\r
+* @brief RTP Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of RTP\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define rtpPORT ((gioPORT_t *)0xFFFFFA38U)\r
+\r
+\r
+/* RTP Interface Functions */\r
+void rtpInit(void);\r
+#endif\r
--- /dev/null
+/** @file sci.h\r
+* @brief SCI Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __SCI_H__\r
+#define __SCI_H__\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+\r
+\r
+/** @enum sciIntFlags\r
+* @brief Interrupt Flag Definitions\r
+*\r
+* Used with sciEnableNotification, sciDisableNotification\r
+*/\r
+enum sciIntFlags\r
+{\r
+ SCI_FE_INT = 0x04000000, /* framming error */\r
+ SCI_OE_INT = 0x02000000, /* overrun error */\r
+ SCI_PE_INT = 0x01000000, /* parity error */\r
+ SCI_RX_INT = 0x00000200, /* receive buffer ready */\r
+ SCI_TX_INT = 0x00000100, /* transmit buffer ready */\r
+ SCI_WAKE_INT = 0x00000002, /* wakeup */\r
+ SCI_BREAK_INT = 0x00000001 /* break detect */\r
+};\r
+\r
+\r
+/** @struct sciBase\r
+* @brief SCI Register Definition\r
+*\r
+* This structure is used to access the SCI module egisters.\r
+*/\r
+/** @typedef sciBASE_t\r
+* @brief SCI Register Frame Type Definition\r
+*\r
+* This type is used to access the SCI Registers.\r
+*/\r
+\r
+enum sciPinSelect\r
+{\r
+ PIN_SCI_TX = 0,\r
+ PIN_SCI_RX = 1\r
+};\r
+\r
+/** @struct sciBase\r
+* @brief SCI Base Register Definition\r
+*\r
+* This structure is used to access the SCI module egisters.\r
+*/\r
+/** @typedef sciBASE_t\r
+* @brief SCI Register Frame Type Definition\r
+*\r
+* This type is used to access the SCI Registers.\r
+*/\r
+typedef volatile struct sciBase\r
+{\r
+ uint32_t GCR0; /**< 0x0000 Global Control Register 0 */\r
+ uint32_t GCR1; /**< 0x0004 Global Control Register 1 */\r
+ uint32_t GCR2; /**< 0x0008 Global Control Register 2 */\r
+ uint32_t SETINT; /**< 0x000C Set Interrupt Enable Register */\r
+ uint32_t CLRINT; /**< 0x0010 Clear Interrupt Enable Register */\r
+ uint32_t SETINTLVL; /**< 0x0014 Set Interrupt Level Register */\r
+ uint32_t CLRINTLVL; /**< 0x0018 Set Interrupt Level Register */\r
+ uint32_t FLR; /**< 0x001C Interrupt Flag Register */\r
+ uint32_t INTVECT0; /**< 0x0020 Interrupt Vector Offset 0 */\r
+ uint32_t INTVECT1; /**< 0x0024 Interrupt Vector Offset 1 */\r
+ uint32_t LENGTH; /**< 0x0028 Format Control Register */\r
+ uint32_t BAUD; /**< 0x002C Baud Rate Selection Register */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint8_t ED; /**< 0x0033 Emulation Register */\r
+ uint32_t : 24U;\r
+ uint8_t RD; /**< 0x0037 Receive Data Buffer */\r
+ uint32_t : 24U;\r
+ uint8_t TD; /**< 0x003B Transmit Data Buffer */\r
+ uint32_t : 24U; \r
+#else\r
+ uint32_t : 24U;\r
+ uint8_t ED; /**< 0x0033 Emulation Register */\r
+ uint32_t : 24U;\r
+ uint8_t RD; /**< 0x0037 Receive Data Buffer */\r
+ uint32_t : 24U;\r
+ uint8_t TD; /**< 0x003B Transmit Data Buffer */\r
+#endif\r
+ uint32_t FUN; /**< 0x003C Pin Function Register */\r
+ uint32_t DIR; /**< 0x0040 Pin Direction Register */\r
+ uint32_t DIN; /**< 0x0044 Pin Data In Register */\r
+ uint32_t DOUT; /**< 0x0048 Pin Data Out Register */\r
+ uint32_t SET; /**< 0x004C Pin Data Set Register */\r
+ uint32_t CLR; /**< 0x0050 Pin Data Clr Register */\r
+ uint32_t ODR; /**< 0x0054: Pin Open Drain Output Enable Register */\r
+ uint32_t PD; /**< 0x0058: Pin Pullup/Pulldown Disable Register */\r
+ uint32_t PSL; /**< 0x005C: Pin Pullup/Pulldown Selection Register */\r
+ uint32_t : 32U; /**< 0x060: Reserved */\r
+ uint32_t : 32U; /**< 0x064: Reserved */\r
+ uint32_t : 32U; /**< 0x068: Reserved */\r
+ uint32_t : 32U; /**< 0x06C: Reserved */\r
+ uint32_t : 32U; /**< 0x070: Reserved */\r
+ uint32_t : 32U; /**< 0x074: Reserved */\r
+ uint32_t : 32U; /**< 0x078: Reserved */\r
+ uint32_t : 32U; /**< 0x07C: Reserved */\r
+ uint32_t : 32U; /**< 0x080: Reserved */\r
+ uint32_t : 32U; /**< 0x084: Reserved */\r
+ uint32_t : 32U; /**< 0x088: Reserved */\r
+ uint32_t : 32U; /**< 0x08C: Reserved */\r
+ uint32_t IODFTCTRL; /**< 0x0090: I/O Error Enable Register */\r
+} sciBASE_t;\r
+\r
+\r
+/** @def sciREG\r
+* @brief Register Frame Pointer\r
+*\r
+* This pointer is used by the SCI driver to access the sci module registers.\r
+*/\r
+#define sciREG ((sciBASE_t *)0xFFF7E500U)\r
+\r
+\r
+/** @def sciPORT\r
+* @brief SCI GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of SCI\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define sciPORT ((gioPORT_t *)0xFFF7E540U)\r
+\r
+\r
+/** @def scilinREG\r
+* @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer\r
+*\r
+* This pointer is used by the SCI driver to access the sci module registers.\r
+*/\r
+#define scilinREG ((sciBASE_t *)0xFFF7E400U)\r
+\r
+\r
+/** @def scilinPORT\r
+* @brief SCILIN (LIN - Compatibility Mode) Register Frame Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of LIN\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define scilinPORT ((gioPORT_t *)0xFFF7E440U)\r
+\r
+\r
+/* SCI Interface Functions */\r
+void sciInit(void);\r
+void sciSetFunctional(sciBASE_t *sci, uint32_t port);\r
+void sciSetBaudrate(sciBASE_t *sci, uint32_t baud);\r
+int sciIsTxReady(sciBASE_t *sci);\r
+void sciSendByte(sciBASE_t *sci, uint8_t byte);\r
+void sciSend(sciBASE_t *sci, uint32_t length, uint8_t *data);\r
+int sciIsRxReady(sciBASE_t *sci);\r
+int sciRxError(sciBASE_t *sci);\r
+int sciReceiveByte(sciBASE_t *sci);\r
+void sciReceive(sciBASE_t *sci, uint32_t length, uint8_t *data);\r
+void sciEnableNotification(sciBASE_t *sci, uint32_t flags);\r
+void sciDisableNotification(sciBASE_t *sci, uint32_t flags);\r
+void sciEnableLoopback(sciBASE_t *sci, Loopbacktype_t Loopbacktype);\r
+void sciDisableLoopback(sciBASE_t *sci);\r
+\r
+/** @fn void sciNotification(sciBASE_t *sci, uint32_t flags)\r
+* @brief Interrupt callback\r
+* @param[in] sci - sci module base address\r
+* @param[in] flags - copy of error interrupt flags\r
+*\r
+* This is a callback that is provided by the application and is called apon\r
+* an interrupt. The parameter passed to the callback is a copy of the \r
+* interrupt flag register.\r
+*/\r
+void sciNotification(sciBASE_t *sci, uint32_t flags);\r
+\r
+#endif\r
--- /dev/null
+/** @file spi.h\r
+* @brief SPI Driver Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* (c) Texas Instruments 2009-2012, All rights reserved.\r
+*/\r
+\r
+\r
+#ifndef __SPI_H__\r
+#define __SPI_H__\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+\r
+#ifndef BOOL\r
+#define BOOL uint32_t char\r
+#endif\r
+\r
+#ifndef TRUE\r
+#define TRUE 1\r
+#endif\r
+\r
+#ifndef FALSE\r
+#define FALSE 0\r
+#endif\r
+\r
+/** @enum chipSelect\r
+* @brief Transfer Group Chip Select\r
+*/\r
+enum spiChipSelect\r
+{\r
+ SPI_CS_NONE = 0xFF,\r
+ SPI_CS_0 = 0xFE,\r
+ SPI_CS_1 = 0xFD,\r
+ SPI_CS_2 = 0xFB,\r
+ SPI_CS_3 = 0xF7,\r
+ SPI_CS_4 = 0xEF,\r
+ SPI_CS_5 = 0xDF,\r
+ SPI_CS_6 = 0xBF,\r
+ SPI_CS_7 = 0x7F\r
+};\r
+\r
+/** @enum spiPinSelect\r
+* @brief spi Pin Select\r
+*/\r
+enum spiPinSelect\r
+{\r
+ SPI_PIN_CS0 = 0,\r
+ SPI_PIN_CS1 = 1,\r
+ SPI_PIN_CS2 = 2,\r
+ SPI_PIN_CS3 = 3,\r
+ SPI_PIN_CS4 = 4,\r
+ SPI_PIN_CS5 = 5,\r
+ SPI_PIN_CS6 = 6,\r
+ SPI_PIN_CS7 = 7,\r
+ SPI_PIN_ENA = 8,\r
+ SPI_PIN_CLK = 9,\r
+ SPI_PIN_SIMO = 10,\r
+ SPI_PIN_SOMI = 11,\r
+ SPI_PIN_SIMO_1 = 17,\r
+ SPI_PIN_SIMO_2 = 18,\r
+ SPI_PIN_SIMO_3 = 19,\r
+ SPI_PIN_SIMO_4 = 20,\r
+ SPI_PIN_SIMO_5 = 21,\r
+ SPI_PIN_SIMO_6 = 22,\r
+ SPI_PIN_SIMO_7 = 23,\r
+ SPI_PIN_SOMI_1 = 25,\r
+ SPI_PIN_SOMI_2 = 26,\r
+ SPI_PIN_SOMI_3 = 27,\r
+ SPI_PIN_SOMI_4 = 28,\r
+ SPI_PIN_SOMI_5 = 29,\r
+ SPI_PIN_SOMI_6 = 30,\r
+ SPI_PIN_SOMI_7 = 31\r
+};\r
+\r
+/** @enum dataformat\r
+* @brief SPI dataformat register select\r
+*/\r
+typedef enum dataformat\r
+{\r
+ SPI_FMT_0 = 0,\r
+ SPI_FMT_1 = 1,\r
+ SPI_FMT_2 = 2,\r
+ SPI_FMT_3 = 3\r
+}SPIDATAFMT;\r
+\r
+\r
+/** @struct spiDAT1RegConfig\r
+* @brief SPI data register configuration\r
+*/\r
+typedef struct spiDAT1RegConfig\r
+{\r
+ uint32_t CS_HOLD;\r
+ uint32_t WDEL;\r
+ uint32_t DFSEL;\r
+ uint32_t CSNR;\r
+}spiDAT1_t;\r
+\r
+/** @struct spiBase\r
+* @brief SPI Register Definition\r
+*\r
+* This structure is used to access the SPI module egisters.\r
+*/\r
+/** @typedef spiBASE_t\r
+* @brief SPI Register Frame Type Definition\r
+*\r
+* This type is used to access the SPI Registers.\r
+*/\r
+typedef volatile struct spiBase\r
+{\r
+ uint32_t GCR0; /**< 0x0000: Global Control 0 */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */\r
+ uint32_t PD : 1U; /**< 0x0006: Power down bit */\r
+ uint32_t : 7U;\r
+ uint32_t LB : 1U; /**< 0x0005: Loop back bit */\r
+ uint32_t : 7U;\r
+ uint32_t ENA : 1U; /**< 0x0004: SPI Enable bit */\r
+ uint32_t : 7U; \r
+ uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */\r
+ uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */\r
+ uint32_t : 7U;\r
+ uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */\r
+ uint32_t : 7U;\r
+#else\r
+ uint32_t : 7U; \r
+ uint32_t ENA : 1U; /**< 0x0004: SPI Enable bit */\r
+ uint32_t : 7U;\r
+ uint32_t LB : 1U; /**< 0x0005: Loop back bit */\r
+ uint32_t : 7U;\r
+ uint32_t PD : 1U; /**< 0x0006: Power down bit */\r
+ uint32_t GCR1 : 8U; /**< 0x0007: Global Control 1 */\r
+ uint32_t : 7U;\r
+ uint32_t ENAHIGHZ : 1U; /**< 0x0008: Enable HIGHZ outputs */\r
+ uint32_t : 7U;\r
+ uint32_t DMAREQEN : 1U; /**< 0x0009: DMA Request enable */\r
+ uint32_t INT0 : 16U; /**< 0x000A: Interrupt Enable bits */\r
+#endif\r
+ uint32_t LVL; /**< 0x000C: Interrupt Level */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */\r
+ uint32_t : 8U;\r
+ uint32_t BUFINIT : 1U; /**< 0x0010: Buffer inialisation active flag */\r
+ uint32_t : 7U;\r
+#else\r
+ uint32_t : 7U;\r
+ uint32_t BUFINIT : 1U; /**< 0x0010: Buffer inialisation active flag */\r
+ uint32_t : 8U;\r
+ uint32_t FLG : 16U; /**< 0x0012: Interrupt flags */\r
+#endif\r
+ uint32_t PCFUN; /**< 0x0014: Function Pin Enable */\r
+ uint32_t PCDIR; /**< 0x0018: Pin Direction */\r
+ uint32_t PCDIN; /**< 0x001C: Pin Input Latch */\r
+ uint32_t PCDOUT; /**< 0x0020: Pin Output Latch */\r
+ uint32_t PCSET; /**< 0x0024: Output Pin Set */\r
+ uint32_t PCCLR; /**< 0x0028: Output Pin Clr */\r
+ uint32_t PCPDR; /**< 0x002C: Open Drain Output Enable */\r
+ uint32_t PCDIS; /**< 0x0030: Pullup/Pulldown Disable */\r
+ uint32_t PCPSL; /**< 0x0034: Pullup/Pulldown Selection */\r
+ uint32_t DAT0; /**< 0x0038: Transmit Data */\r
+ uint32_t DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */\r
+ uint32_t BUF; /**< 0x0040: Receive Buffer */\r
+ uint32_t EMU; /**< 0x0044: Emulation Receive Buffer */\r
+ uint32_t DELAY; /**< 0x0048: Delays */\r
+ uint32_t CSDEF; /**< 0x004C: Default Chip Select */\r
+ uint32_t FMT0; /**< 0x0050: Data Format 0 */\r
+ uint32_t FMT1; /**< 0x0054: Data Format 1 */\r
+ uint32_t FMT2; /**< 0x0058: Data Format 2 */\r
+ uint32_t FMT3; /**< 0x005C: Data Format 3 */\r
+ uint32_t INTVECT0; /**< 0x0060: Interrupt Vector 0 */\r
+ uint32_t INTVECT1; /**< 0x0064: Interrupt Vector 1 */\r
+ uint32_t SRSEL; /**< 0x0068: Slew Rate Select */\r
+ uint32_t RESERVED[51U]; /**< 0x006C to 0x0130: Reserved */ \r
+ uint32_t IOLPKTSTCR; /**< 0x0134: IO loopback */\r
+} spiBASE_t;\r
+\r
+/** @def spiREG2\r
+* @brief SPI2 Register Frame Pointer\r
+*\r
+* This pointer is used by the SPI driver to access the spi module registers.\r
+*/\r
+#define spiREG2 ((spiBASE_t *)0xFFF7F600U)\r
+\r
+\r
+/** @def spiPORT2\r
+* @brief SPI2 GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of SPI2\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define spiPORT2 ((gioPORT_t *)0xFFF7F618U)\r
+\r
+\r
+/** @def spiREG4\r
+* @brief SPI4 Register Frame Pointer\r
+*\r
+* This pointer is used by the SPI driver to access the spi module registers.\r
+*/\r
+#define spiREG4 ((spiBASE_t *)0xFFF7FA00U)\r
+\r
+\r
+/** @def spiPORT4\r
+* @brief SPI4 GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of SPI4\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define spiPORT4 ((gioPORT_t *)0xFFF7FA18U)\r
+\r
+\r
+/* SPI Interface Functions */\r
+void spiInit(void);\r
+void spiSetFunctional(spiBASE_t *spi, uint32_t port);\r
+void spiEnableNotification(spiBASE_t *spi, uint32_t flags);\r
+void spiDisableNotification(spiBASE_t *spi, uint32_t flags);\r
+uint32_t spiTransmitData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32_t blocksize, uint16_t *srcbuff);\r
+void spiSendData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32_t blocksize, uint16_t *srcbuff);\r
+uint32_t spiReceiveData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32_t blocksize, uint16_t *destbuff);\r
+void spiGetData(spiBASE_t *spi, spiDAT1_t *dataconfig_t, uint32_t blocksize, uint16_t *destbuff);\r
+void spiEnableLoopback(spiBASE_t *spi, Loopbacktype_t Loopbacktype);\r
+void spiDisableLoopback(spiBASE_t *spi);\r
+\r
+/** @fn void spiNotification(spiBASE_t *spi, uint32_t flags)\r
+* @brief Interrupt callback\r
+* @param[in] spi - Spi module base address\r
+* @param[in] flags - Copy of error interrupt flags\r
+*\r
+* This is a callback that is provided by the application and is called upon\r
+* an interrupt. The parameter passed to the callback is a copy of the \r
+* interrupt flag register.\r
+*/\r
+void spiNotification(spiBASE_t *spi, uint32_t flags);\r
+\r
+#endif\r
--- /dev/null
+/** @file std_nhet.h\r
+* @brief - NHET Instruction Definition File\r
+* @date 04.March.2010\r
+* @version 1.00.000\r
+* \r
+* (c) Texas Instruments 2009, All rights reserved.\r
+*/\r
+\r
+#ifndef __STD_NHET_H__\r
+#define __STD_NHET_H__\r
+\r
+#if defined(_TMS470_BIG) || defined(__big_endian__)\r
+\r
+#ifndef HET_v2\r
+# define HET_v2 0\r
+#endif\r
+\r
+#ifndef HETBYTE\r
+# define HETBYTE unsigned char\r
+#endif\r
+\r
+typedef struct memory_format\r
+{\r
+ unsigned int program_word ;\r
+ unsigned int control_word ;\r
+ unsigned int data_word ;\r
+ unsigned int reserved_word ;\r
+} HET_MEMORY ;\r
+ \r
+\r
+/*---------------------------------------------*/\r
+/* ACMP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct acmp_format\r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int coutprv : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int ext_reg : 1 ;\r
+ unsigned int : 2 ; \r
+ unsigned int pin_action : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+ \r
+} ACMP_FIELDS;\r
+ \r
+typedef union\r
+{\r
+ ACMP_FIELDS acmp ;\r
+ HET_MEMORY memory ;\r
+} ACMP_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* ECMP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct ecmp_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int hr_lr : 1 ;\r
+ unsigned int angle_compare : 1 ;\r
+ unsigned int : 7 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int sub_opcode : 2 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+\r
+} ECMP_FIELDS;\r
+\r
+typedef union \r
+{\r
+ ECMP_FIELDS ecmp ;\r
+ HET_MEMORY memory ;\r
+} ECMP_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* SCMP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct scmp_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 2 ;\r
+ unsigned int : 2 ;\r
+ unsigned int : 5 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int coutprv : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int compare_mode : 2 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int restart_en : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+\r
+} SCMP_FIELDS ;\r
+\r
+typedef union \r
+{\r
+ SCMP_FIELDS scmp ;\r
+ HET_MEMORY memory ;\r
+} SCMP_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* MCMP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct mcmp_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int hr_lr : 1 ;\r
+ unsigned int angle_compare : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int save_subtract : 1 ;\r
+ unsigned int : 5 ;\r
+ \r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int sub_opcode : 1 ; \r
+ unsigned int order : 1 ; \r
+ unsigned int pin_action : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} MCMP_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ MCMP_FIELDS mcmp ;\r
+ HET_MEMORY memory ;\r
+} MCMP_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* MOV64 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct mov64_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int compare_mode : 2 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+\r
+} MOV64_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ MOV64_FIELDS mov64 ;\r
+ HET_MEMORY memory ;\r
+} MOV64_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* DADM64 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct dadm64_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int compare_mode : 2 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} DADM64_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ DADM64_FIELDS dadm64 ;\r
+ HET_MEMORY memory ;\r
+} DADM64_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* RADM64 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct RADM64_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int compare_mode : 2 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} RADM64_FIELDS ; \r
+\r
+\r
+typedef union \r
+{\r
+ RADM64_FIELDS radm64 ;\r
+ HET_MEMORY memory ;\r
+} RADM64_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* MOV32 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct MOV32_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int z_flag : 1 ;\r
+ unsigned int : 15 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode : 1 ; \r
+ unsigned int move_type : 2 ; \r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} MOV32_FIELDS ; \r
+\r
+\r
+typedef union \r
+{\r
+ MOV32_FIELDS mov32 ;\r
+ HET_MEMORY memory ;\r
+} MOV32_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* ADM32 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct ADM32_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 19 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode : 1 ;\r
+ unsigned int move_type : 2 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} ADM32_FIELDS ; \r
+\r
+\r
+typedef union \r
+{\r
+ ADM32_FIELDS adm32 ;\r
+ HET_MEMORY memory ;\r
+} ADM32_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* ADCNST INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct ADCNST_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int control : 1 ; /* pk */\r
+ unsigned int : 1 ;\r
+ unsigned int constant : 25 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} ADCNST_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ ADCNST_FIELDS adcnst ;\r
+ HET_MEMORY memory ;\r
+} ADCNST_INSTRUCTION;\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* ADD INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct ADD_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int control : 1;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int reg : 2 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} ADD_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ ADD_FIELDS add ;\r
+ HET_MEMORY memory ;\r
+} ADD_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* ADC INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct ADC_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int control : 1;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int reg : 2 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} ADC_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ ADC_FIELDS adc ;\r
+ HET_MEMORY memory ;\r
+} ADC_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* SUB INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct SUB_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int control : 1;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int reg : 2 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} SUB_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ SUB_FIELDS sub ;\r
+ HET_MEMORY memory ;\r
+} SUB_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* SBB INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct SBB_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int control : 1;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int reg : 2 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} SBB_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ SBB_FIELDS sbb ;\r
+ HET_MEMORY memory ;\r
+} SBB_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* AND INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct AND_format\r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int control : 1;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int reg : 2 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} AND_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ AND_FIELDS and ;\r
+ HET_MEMORY memory ;\r
+} AND_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* OR INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+\r
+typedef struct OR_format\r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int control : 1;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int reg : 2 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} OR_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ OR_FIELDS or ;\r
+ HET_MEMORY memory ;\r
+} OR_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* XOR INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct XOR_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int remote_address : 9 ;\r
+ \r
+ unsigned int : 5 ;\r
+ unsigned int control : 1;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int reg : 2 ;\r
+ unsigned int : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} XOR_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ XOR_FIELDS xor ;\r
+ HET_MEMORY memory ;\r
+} XOR_INSTRUCTION;\r
+\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* CNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct CNT_format \r
+{\r
+ unsigned int : 9 ; \r
+ unsigned int brk : 1 ; \r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int angle_cnt : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int : 4 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ \r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int max : 25 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+\r
+} CNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ CNT_FIELDS cnt ; \r
+ HET_MEMORY memory ;\r
+} CNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* APCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct apcnt_format\r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int edge_select : 2 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int count : 25 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+ \r
+} APCNT_FIELDS ;\r
+ \r
+typedef union\r
+{\r
+ APCNT_FIELDS apcnt ;\r
+ HET_MEMORY memory ;\r
+} APCNT_INSTRUCTION;\r
+ \r
+ \r
+\r
+/*---------------------------------------------*/\r
+/* PCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct pcnt_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int period_pulse_select : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int count : 25 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+\r
+} PCNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ PCNT_FIELDS pcnt ; \r
+ HET_MEMORY memory ;\r
+} PCNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* SCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct scnt_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 1 ;\r
+ unsigned int count_mode : 2 ;\r
+ unsigned int step_width : 2 ;\r
+ unsigned int : 4 ;\r
+\r
+ unsigned int : 5 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int gap_start : 25 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+\r
+} SCNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ SCNT_FIELDS scnt ; \r
+ HET_MEMORY memory ;\r
+} SCNT_INSTRUCTION;\r
+\r
+\r
+\f\r
+/*---------------------------------------------*/\r
+/* ACNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct acnt_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int edge_select : 1 ;\r
+ unsigned int : 7 ;\r
+ unsigned int interrupt_enable : 1 ; \r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int gap_end : 25 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+\r
+} ACNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ ACNT_FIELDS acnt ; \r
+ HET_MEMORY memory ;\r
+} ACNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* ECNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct ecnt_format\r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 1 ;\r
+ unsigned int count_mode : 2 ;\r
+ unsigned int : 6 ;\r
+ \r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int count_cond : 3 ;\r
+ unsigned int : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+ \r
+} ECNT_FIELDS ;\r
+ \r
+typedef union\r
+{\r
+ ECNT_FIELDS ecnt ;\r
+ HET_MEMORY memory ;\r
+} ECNT_INSTRUCTION;\r
+\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* RCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct rcnt_format\r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 1 ;\r
+ unsigned int count_mode : 2 ;\r
+ unsigned int : 5 ;\r
+ unsigned int count_mode1 : 1 ;\r
+ \r
+ unsigned int : 3 ;\r
+ unsigned int : 2 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int divisor : 25 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+ \r
+} RCNT_FIELDS ;\r
+ \r
+typedef union\r
+{\r
+ RCNT_FIELDS rcnt ;\r
+ HET_MEMORY memory ;\r
+} RCNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* DJNZ INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct djnz_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 1 ;\r
+ unsigned int sub_opcode : 2 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 4 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int : 10 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+\r
+} DJNZ_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ DJNZ_FIELDS djnz ; \r
+ HET_MEMORY memory ;\r
+} DJNZ_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* DJZ INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct djz_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 1 ;\r
+ unsigned int sub_opcode : 2 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 4 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int : 10 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+\r
+} DJZ_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ DJZ_FIELDS djz ; \r
+ HET_MEMORY memory ;\r
+} DJZ_INSTRUCTION;\r
+\r
+/*---------------------------------------------*/\r
+/* PWCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct pwcnt_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int hr_lr : 1 ;\r
+ unsigned int count_mode : 2 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 3 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} PWCNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ PWCNT_FIELDS pwcnt ;\r
+ HET_MEMORY memory ;\r
+} PWCNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* WCAP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct wcap_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int hr_lr : 1 ;\r
+ unsigned int : 8 ;\r
+ \r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int capture_condition : 2 ;\r
+ unsigned int : 2 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+\r
+} WCAP_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ WCAP_FIELDS wcap ; \r
+ HET_MEMORY memory ;\r
+} WCAP_INSTRUCTION;\r
+ \r
+/*----------------------------------------------*/\r
+/* WCAPE INSTRUCTION */\r
+/*----------------------------------------------*/\r
+typedef struct wcape_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 9 ;\r
+ \r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int capture_condition : 2 ;\r
+ unsigned int : 2 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int ts_data : 25 ;\r
+ unsigned int ec_data : 7 ;\r
+\r
+} WCAPE_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ WCAPE_FIELDS wcape ; \r
+ HET_MEMORY memory ;\r
+} WCAPE_INSTRUCTION;\r
+ \r
+\r
+/*---------------------------------------------*/\r
+/* BR INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct br_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+\r
+#if HET_v2\r
+ unsigned int branch_condition : 5 ;\r
+#else \r
+ unsigned int branch_condition : 3 ;\r
+ unsigned int : 1 ;\r
+ unsigned int : 1 ;\r
+#endif \r
+\r
+ unsigned int : 2 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ \r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int hr_data : 7 ;\r
+ \r
+} BR_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ BR_FIELDS br ; \r
+ HET_MEMORY memory ;\r
+} BR_INSTRUCTION;\r
+\r
+ \r
+/*---------------------------------------------*/\r
+/* SHFT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct shft_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int : 5 ;\r
+ unsigned int shift_mode : 4 ;\r
+ \r
+ unsigned int : 3 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int shift_condition : 2 ;\r
+ unsigned int : 2 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+\r
+ \r
+ unsigned int data : 25 ;\r
+ unsigned int : 7 ;\r
+\r
+} SHFT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ SHFT_FIELDS shft ; \r
+ HET_MEMORY memory ;\r
+} SHFT_INSTRUCTION;\r
+\r
+/* ---------------------------------------------------------------------------------------------------- */\r
+\r
+#elif defined(_TMS470_LITTLE) || defined(__little_endian__)\r
+\r
+#ifndef HETBYTE\r
+# define HETBYTE unsigned char\r
+#endif\r
+\r
+typedef struct memory_format\r
+{\r
+ unsigned int program_word ;\r
+ unsigned int control_word ;\r
+ unsigned int data_word ;\r
+ unsigned int reserved_word ;\r
+} HET_MEMORY ;\r
+ \r
+/*---------------------------------------------*/\r
+/* ACMP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct acmp_format\r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ; \r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int coutprv : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ; \r
+\r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ;\r
+ \r
+} ACMP_FIELDS;\r
+ \r
+typedef union\r
+{\r
+ ACMP_FIELDS acmp ;\r
+ HET_MEMORY memory ;\r
+} ACMP_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* ECMP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct ecmp_format \r
+{\r
+ unsigned int : 7 ;\r
+ unsigned int angle_compare : 1 ;\r
+ unsigned int hr_lr : 1 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int sub_opcode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int auto_read_clear : 1 ; \r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} ECMP_FIELDS;\r
+\r
+typedef union \r
+{\r
+ ECMP_FIELDS ecmp ;\r
+ HET_MEMORY memory ;\r
+} ECMP_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* SCMP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct scmp_format \r
+{\r
+ unsigned int : 5 ;\r
+ unsigned int : 2 ;\r
+ unsigned int : 2 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int restart_en : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int compare_mode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int coutprv : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} SCMP_FIELDS ;\r
+\r
+typedef union \r
+{\r
+ SCMP_FIELDS scmp ;\r
+ HET_MEMORY memory ;\r
+} SCMP_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* MCMP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct mcmp_format \r
+{\r
+ unsigned int : 5 ;\r
+ unsigned int save_subtract : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int angle_compare : 1 ;\r
+ unsigned int hr_lr : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+ \r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int order : 1 ; \r
+ unsigned int sub_opcode : 1 ; \r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ; \r
+\r
+} MCMP_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ MCMP_FIELDS mcmp ;\r
+ HET_MEMORY memory ;\r
+} MCMP_INSTRUCTION;\r
+\r
+/*---------------------------------------------*/\r
+/* MOV64 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct mov64_format \r
+{\r
+ unsigned int remote_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int brk : 1 ;\r
+ unsigned int : 9 ;\r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int compare_mode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ; \r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} MOV64_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ MOV64_FIELDS mov64 ;\r
+ HET_MEMORY memory ;\r
+} MOV64_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* DADM64 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct dadm64_format \r
+{\r
+ unsigned int remote_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int : 9 ; \r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int compare_mode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ; \r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ;\r
+ \r
+} DADM64_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ DADM64_FIELDS dadm64 ;\r
+ HET_MEMORY memory ;\r
+} DADM64_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* RADM64 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct RADM64_format \r
+{\r
+ unsigned int remote_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int : 9 ; \r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int compare_mode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ; \r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ; \r
+\r
+} RADM64_FIELDS ; \r
+\r
+\r
+typedef union \r
+{\r
+ RADM64_FIELDS radm64 ;\r
+ HET_MEMORY memory ;\r
+} RADM64_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* MOV32 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct MOV32_format \r
+{\r
+ unsigned int remote_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int : 9 ;\r
+ \r
+ unsigned int : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int move_type : 2 ;\r
+ unsigned int sub_opcode : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int : 15 ;\r
+ unsigned int z_flag : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 5 ; \r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ;\r
+ \r
+} MOV32_FIELDS ; \r
+\r
+\r
+typedef union \r
+{\r
+ MOV32_FIELDS mov32 ;\r
+ HET_MEMORY memory ;\r
+} MOV32_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* ADM32 INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct ADM32_format \r
+{\r
+ unsigned int remote_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int : 9 ; \r
+\r
+ unsigned int : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int move_type : 2 ;\r
+ unsigned int sub_opcode : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int : 19 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 5 ; \r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ;\r
+ \r
+} ADM32_FIELDS ; \r
+\r
+\r
+typedef union \r
+{\r
+ ADM32_FIELDS adm32 ;\r
+ HET_MEMORY memory ;\r
+} ADM32_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* ADCNST INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct ADCNST_format \r
+{\r
+ unsigned int remote_address : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int : 9 ;\r
+ \r
+ unsigned int constant : 25 ;\r
+ unsigned int : 1 ;\r
+ unsigned int : 5 ; \r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ; \r
+\r
+} ADCNST_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ ADCNST_FIELDS adcnst ;\r
+ HET_MEMORY memory ;\r
+} ADCNST_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* ADD INSTRUCTION */\r
+/*----------------------------------------------*/\r
+typedef struct ADD_format \r
+{\r
+\r
+ unsigned int remote_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 1 ; \r
+ unsigned int reg : 2 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 5 ;\r
+\r
+ unsigned int hr_data : 7 ; \r
+ unsigned int data : 25 ;\r
+ \r
+ \r
+} ADD_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ ADD_FIELDS add ;\r
+ HET_MEMORY memory ;\r
+} ADD_INSTRUCTION;\r
+\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* ADC INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+\r
+typedef struct ADC_format \r
+{\r
+\r
+ unsigned int remote_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 1 ; \r
+ unsigned int reg : 2 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 5 ;\r
+\r
+ unsigned int hr_data : 7 ; \r
+ unsigned int data : 25 ;\r
+ \r
+ \r
+} ADC_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ ADC_FIELDS adc ;\r
+ HET_MEMORY memory ;\r
+} ADC_INSTRUCTION;\r
+\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* SUB INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct SUB_format \r
+{\r
+\r
+ unsigned int remote_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 1 ; \r
+ unsigned int reg : 2 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 5 ;\r
+\r
+ unsigned int hr_data : 7 ; \r
+ unsigned int data : 25 ;\r
+ \r
+ \r
+} SUB_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ SUB_FIELDS sub ;\r
+ HET_MEMORY memory ;\r
+} SUB_INSTRUCTION;\r
+\r
+\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* SBB INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct SBB_format\r
+{\r
+\r
+ unsigned int remote_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 1 ; \r
+ unsigned int reg : 2 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 5 ;\r
+\r
+ unsigned int hr_data : 7 ; \r
+ unsigned int data : 25 ;\r
+ \r
+ \r
+} SBB_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ SBB_FIELDS sbb ;\r
+ HET_MEMORY memory ;\r
+} SBB_INSTRUCTION;\r
+\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* AND INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct AND_format\r
+{\r
+\r
+ unsigned int remote_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 1 ; \r
+ unsigned int reg : 2 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 5 ;\r
+\r
+ unsigned int hr_data : 7 ; \r
+ unsigned int data : 25 ;\r
+ \r
+ \r
+} AND_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ AND_FIELDS and ;\r
+ HET_MEMORY memory ;\r
+} AND_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* OR INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct OR_format\r
+{\r
+\r
+ unsigned int remote_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 1 ; \r
+ unsigned int reg : 2 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 5 ;\r
+\r
+ unsigned int hr_data : 7 ; \r
+ unsigned int data : 25 ;\r
+ \r
+ \r
+} OR_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ OR_FIELDS or ;\r
+ HET_MEMORY memory ;\r
+} OR_INSTRUCTION;\r
+\r
+\r
+\r
+/*----------------------------------------------*/\r
+/* XOR INSTRUCTION */\r
+/*----------------------------------------------*/\r
+\r
+typedef struct XOR_format\r
+{\r
+\r
+ unsigned int remote_address : 9 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int : 9 ;\r
+\r
+ unsigned int : 1 ; \r
+ unsigned int reg : 2 ;\r
+ unsigned int rem_dest : 2 ;\r
+ unsigned int sub_opcode1 : 1 ;\r
+ unsigned int init_flag : 1 ;\r
+ unsigned int reg_ext : 1 ;\r
+ unsigned int shft_cnt : 5 ;\r
+ unsigned int shft_mode : 3 ;\r
+ unsigned int src_2 : 3 ;\r
+ unsigned int src_1 : 4 ;\r
+ unsigned int sub_opcode3 : 3 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 5 ;\r
+\r
+ unsigned int hr_data : 7 ; \r
+ unsigned int data : 25 ;\r
+ \r
+ \r
+} XOR_FIELDS ;\r
+\r
+\r
+typedef union \r
+{\r
+ XOR_FIELDS xor ;\r
+ HET_MEMORY memory ;\r
+} XOR_INSTRUCTION;\r
+\r
+\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* CNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct CNT_format \r
+{\r
+ unsigned int interrupt_enable : 1 ; \r
+ unsigned int : 4 ; \r
+ unsigned int ab_register_select : 1 ; \r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int angle_cnt : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ; \r
+ unsigned int : 9 ; \r
+\r
+ unsigned int max : 25 ;\r
+ unsigned int : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} CNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ CNT_FIELDS cnt ; \r
+ HET_MEMORY memory ;\r
+} CNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* APCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct apcnt_format\r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int edge_select : 2 ;\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int count : 25 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ; \r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ; \r
+\r
+} APCNT_FIELDS ;\r
+ \r
+typedef union\r
+{\r
+ APCNT_FIELDS apcnt ;\r
+ HET_MEMORY memory ;\r
+} APCNT_INSTRUCTION;\r
+ \r
+ \r
+\r
+/*---------------------------------------------*/\r
+/* PCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct pcnt_format \r
+{\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int : 1 ;\r
+ unsigned int period_pulse_select : 2 ; \r
+ unsigned int interrupt_enable : 1 ; \r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int count : 25 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} PCNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ PCNT_FIELDS pcnt ; \r
+ HET_MEMORY memory ;\r
+} PCNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* SCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct scnt_format \r
+{\r
+ unsigned int : 4 ;\r
+ unsigned int step_width : 2 ;\r
+ unsigned int count_mode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int : 9 ;\r
+\r
+ unsigned int gap_start : 25 ;\r
+ unsigned int : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int : 5 ;\r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} SCNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ SCNT_FIELDS scnt ; \r
+ HET_MEMORY memory ;\r
+} SCNT_INSTRUCTION;\r
+\r
+/*---------------------------------------------*/\r
+/* ACNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct acnt_format \r
+{\r
+ unsigned int interrupt_enable : 1 ; \r
+ unsigned int : 7 ;\r
+ unsigned int edge_select : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int gap_end : 25 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ; \r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} ACNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ ACNT_FIELDS acnt ; \r
+ HET_MEMORY memory ;\r
+} ACNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* ECNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct ecnt_format\r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int count_mode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+ \r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int count_cond : 3 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int : 3 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ; \r
+ \r
+\r
+} ECNT_FIELDS ;\r
+ \r
+typedef union\r
+{\r
+ ECNT_FIELDS ecnt ;\r
+ HET_MEMORY memory ;\r
+} ECNT_INSTRUCTION;\r
+\r
+/*---------------------------------------------*/\r
+/* RCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct rcnt_format\r
+{\r
+\r
+ unsigned int count_mode1 : 1 ;\r
+ unsigned int : 5 ;\r
+ unsigned int count_mode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+\r
+ unsigned int divisor : 25 ; \r
+ unsigned int : 1 ;\r
+ unsigned int control : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int : 3 ;\r
+\r
+ unsigned int : 7 ; \r
+ unsigned int data : 25 ;\r
+\r
+ \r
+} RCNT_FIELDS ;\r
+ \r
+typedef union\r
+{\r
+ RCNT_FIELDS rcnt ;\r
+ HET_MEMORY memory ;\r
+} RCNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* DJNZ INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct djnz_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int sub_opcode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int : 10 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int : 4 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} DJNZ_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ DJNZ_FIELDS djnz ; \r
+ HET_MEMORY memory ;\r
+} DJNZ_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* DJZ INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct djz_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int sub_opcode : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ; \r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int : 10 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int : 4 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} DJZ_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ DJZ_FIELDS djz ; \r
+ HET_MEMORY memory ;\r
+} DJZ_INSTRUCTION;\r
+\f\r
+/*---------------------------------------------*/\r
+/* PWCNT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct pwcnt_format \r
+{\r
+ unsigned int : 6 ;\r
+ unsigned int count_mode : 2 ;\r
+ unsigned int hr_lr : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int opposite_action : 1 ;\r
+ unsigned int pin_action : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int en_pin_action : 1 ;\r
+ unsigned int : 3 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+\r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ; \r
+ \r
+} PWCNT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ PWCNT_FIELDS pwcnt ;\r
+ HET_MEMORY memory ;\r
+} PWCNT_INSTRUCTION;\r
+\r
+\r
+/*---------------------------------------------*/\r
+/* WCAP INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct wcap_format \r
+{\r
+ unsigned int : 8 ;\r
+ unsigned int hr_lr : 1 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ; \r
+ \r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int capture_condition : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int : 3 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} WCAP_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ WCAP_FIELDS wcap ; \r
+ HET_MEMORY memory ;\r
+} WCAP_INSTRUCTION;\r
+ \r
+/*----------------------------------------------*/\r
+/* WCAPE INSTRUCTION */\r
+/*----------------------------------------------*/\r
+typedef struct wcape_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ; \r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int capture_condition : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int ec_data : 7 ;\r
+ unsigned int ts_data : 25 ;\r
+\r
+} WCAPE_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ WCAPE_FIELDS wcape ; \r
+ HET_MEMORY memory ;\r
+} WCAPE_INSTRUCTION;\r
+ \r
+\r
+/*---------------------------------------------*/\r
+/* BR INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct br_format \r
+{\r
+ unsigned int : 9 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ;\r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int : 1 ;\r
+ unsigned int branch_condition : 3 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int : 3 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ; \r
+ \r
+ unsigned int hr_data : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} BR_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ BR_FIELDS br ; \r
+ HET_MEMORY memory ;\r
+} BR_INSTRUCTION;\r
+\r
+ \r
+/*---------------------------------------------*/\r
+/* SHFT INSTRUCTION */\r
+/*---------------------------------------------*/\r
+typedef struct shft_format \r
+{\r
+ unsigned int shift_mode : 4 ;\r
+ unsigned int : 5 ;\r
+ unsigned int op_code : 4 ;\r
+ unsigned int next_program_address : 9 ;\r
+ unsigned int brk : 1 ;\r
+ unsigned int reqnum : 3 ;\r
+ unsigned int : 6 ; \r
+\r
+ unsigned int interrupt_enable : 1 ;\r
+ unsigned int ab_register_select : 1 ;\r
+ unsigned int t_register_select : 1 ;\r
+ unsigned int : 2 ;\r
+ unsigned int shift_condition : 2 ;\r
+ unsigned int : 1 ;\r
+ unsigned int pin_select : 5 ;\r
+ unsigned int cond_addr : 9 ;\r
+ unsigned int : 3 ;\r
+ unsigned int previous_bit : 1 ;\r
+ unsigned int auto_read_clear : 1 ;\r
+ unsigned int request : 2 ;\r
+ unsigned int : 3 ;\r
+ \r
+ unsigned int : 7 ;\r
+ unsigned int data : 25 ;\r
+\r
+} SHFT_FIELDS ; \r
+\r
+typedef union \r
+{\r
+ SHFT_FIELDS shft ; \r
+ HET_MEMORY memory ;\r
+} SHFT_INSTRUCTION;\r
+\r
+#endif\r
+\r
+#endif\r
+/*--------------------------- End Of File ----------------------------------*/\r
--- /dev/null
+/** @file sys_common.h\r
+* @brief Common Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - General Definitions\r
+* .\r
+* which are relevant for all drivers.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+\r
+#ifndef __SYS_COMMON_H__\r
+#define __SYS_COMMON_H__\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+/* General Definitios */\r
+\r
+/** @def NULL\r
+* @brief NULL definition\r
+*/\r
+#ifndef NULL\r
+ #define NULL ((void *) 0U)\r
+#endif\r
+\r
+/** @def TRUE\r
+* @brief definition for TRUE\r
+*/\r
+#ifndef TRUE\r
+ #define TRUE 1U\r
+#endif\r
+\r
+/** @def FALSE\r
+* @brief BOOLEAN definition for FALSE\r
+*/\r
+#ifndef FALSE\r
+ #define FALSE 0U\r
+#endif\r
+\r
+#ifndef _UINT64_T_DECLARED\r
+typedef unsigned long long uint64_t;\r
+#define _UINT64_T_DECLARED\r
+#endif\r
+\r
+#ifndef _UINT32_T_DECLARED\r
+typedef unsigned int uint32_t;\r
+#define _UINT32_T_DECLARED\r
+#endif\r
+\r
+#ifndef _UINT16_T_DECLARED\r
+typedef unsigned short uint16_t;\r
+#define _UINT16_T_DECLARED\r
+#endif\r
+\r
+#ifndef _UINT8_T_DECLARED\r
+typedef unsigned char uint8_t;\r
+#define _UINT8_T_DECLARED\r
+#endif\r
+\r
+#ifndef _BOOLEAN_T_DECLARED\r
+typedef unsigned char boolean_t;\r
+typedef unsigned char tBoolean;\r
+#define _BOOLEAN_T_DECLARED\r
+#endif\r
+\r
+/** @enum Loopbacktype\r
+* @brief Loopback type definition\r
+*/\r
+/** @typedef Loopbacktype_t\r
+* @brief Loopback type Type Definition\r
+*\r
+* This type is used to select the module Loopback type Digital or Analog loopback.\r
+*/\r
+typedef enum Loopbacktype \r
+{\r
+ Digital = 0, \r
+ Analog = 1\r
+}Loopbacktype_t;\r
+\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+//*****************************************************************************\r
+//\r
+// The ASSERT macro, which does the actual assertion checking. Typically, this\r
+// will be for procedure arguments.\r
+//\r
+//*****************************************************************************\r
+#ifdef DEBUG\r
+#define ASSERT(expr) { \\r
+ if(!(expr)) \\r
+ { \\r
+ __error__(__FILE__, __LINE__); \\r
+ } \\r
+ }\r
+#else\r
+#define ASSERT(expr)\r
+#endif\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+#endif\r
--- /dev/null
+/** @file sys_core.h\r
+* @brief System Core Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Core Interface Functions\r
+* .\r
+* which are relevant for the System driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#ifndef __SYS_CORE_H__\r
+#define __SYS_CORE_H__\r
+\r
+#include "sys_common.h"\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* System Core Interface Functions */\r
+\r
+/** @fn void _coreInitRegisters_(void)\r
+* @brief Initialize Core register\r
+*/\r
+void _coreInitRegisters_(void);\r
+\r
+/** @fn void _coreInitStackPointer_(void)\r
+* @brief Initialize Core stack pointer\r
+*/\r
+void _coreInitStackPointer_(void);\r
+\r
+/** @fn void _coreEnableVfp_(void)\r
+* @brief Get CPSR Value\r
+*/\r
+uint32_t _getCPSRValue_(void);\r
+\r
+/** @fn void _gotoCPUIdle_(void)\r
+* @brief Take CPU to Idle state\r
+*/\r
+void _gotoCPUIdle_(void);\r
+\r
+/** @fn void _coreEnableIrqVicOffset_(void)\r
+* @brief Enable Irq offset propagation via Vic controller\r
+*/\r
+void _coreEnableIrqVicOffset_(void);\r
+\r
+/** @fn void _coreEnableVfp_(void)\r
+* @brief Enable vector floating point unit\r
+*/\r
+void _coreEnableVfp_(void);\r
+\r
+/** @fn void _coreEnableEventBusExport_(void)\r
+* @brief Enable event bus export for external monitoring modules\r
+* @note It is required to enable event bus export to process ecc issues.\r
+*\r
+* This function enables event bus exports to external monitoring modules\r
+* like tightly coupled RAM wrapper, Flash wrapper and error signaling module.\r
+*/\r
+void _coreEnableEventBusExport_(void);\r
+\r
+/** @fn void _coreDisableEventBusExport_(void)\r
+* @brief Disable event bus export for external monitoring modules\r
+*\r
+* This function disables event bus exports to external monitoring modules\r
+* like tightly coupled RAM wrapper, Flash wrapper and error signaling module.\r
+*/\r
+void _coreDisableEventBusExport_(void);\r
+\r
+/** @fn void _coreEnableRamEcc_(void)\r
+* @brief Enable external ecc error for RAM odd and even bank\r
+* @note It is required to enable event bus export to process ecc issues.\r
+*/\r
+void _coreEnableRamEcc_(void);\r
+\r
+/** @fn void _coreDisableRamEcc_(void)\r
+* @brief Disable external ecc error for RAM odd and even bank\r
+*/\r
+void _coreDisableRamEcc_(void);\r
+\r
+/** @fn void _coreEnableFlashEcc_(void)\r
+* @brief Enable external ecc error for the Flash\r
+* @note It is required to enable event bus export to process ecc issues.\r
+*/\r
+void _coreEnableFlashEcc_(void);\r
+\r
+/** @fn void _coreDisableFlashEcc_(void)\r
+* @brief Disable external ecc error for the Flash\r
+*/\r
+void _coreDisableFlashEcc_(void);\r
+\r
+/** @fn uint32_t _coreGetDataFault_(void)\r
+* @brief Get core data fault status register\r
+* @return The function will return the data fault status register value:\r
+* - bit [10,3..0]: \r
+* - 0b00001: Alignment -> address is valid\r
+* - 0b00000: Background -> address is valid\r
+* - 0b01101: Permission -> address is valid\r
+* - 0b01000: Precise External Abort -> address is valid\r
+* - 0b10110: Imprecise External Abort -> address is unpredictable\r
+* - 0b11001: Precise ECC Error -> address is valid\r
+* - 0b11000: Imprecise ECC Error -> address is unpredictable\r
+* - 0b00010: Debug -> address is unchanged\r
+* - bit [11]: \r
+* - 0: Read\r
+* - 1: Write\r
+* - bit [12]: \r
+* - 0: AXI Decode Error (DECERR)\r
+* - 1: AXI Slave Error (SLVERR)\r
+*/\r
+uint32_t _coreGetDataFault_(void);\r
+\r
+/** @fn void _coreClearDataFault_(void)\r
+* @brief Clear core data fault status register\r
+*/\r
+void _coreClearDataFault_(void);\r
+\r
+/** @fn uint32_t _coreGetInstructionFault_(void)\r
+* @brief Get core instruction fault status register\r
+* @return The function will return the instruction fault status register value:\r
+* - bit [10,3..0]: \r
+* - 0b00001: Alignment -> address is valid\r
+* - 0b00000: Background -> address is valid\r
+* - 0b01101: Permission -> address is valid\r
+* - 0b01000: Precise External Abort -> address is valid\r
+* - 0b10110: Imprecise External Abort -> address is unpredictable\r
+* - 0b11001: Precise ECC Error -> address is valid\r
+* - 0b11000: Imprecise ECC Error -> address is unpredictable\r
+* - 0b00010: Debug -> address is unchanged\r
+* - bit [12]: \r
+* - 0: AXI Decode Error (DECERR)\r
+* - 1: AXI Slave Error (SLVERR)\r
+*/\r
+uint32_t _coreGetInstructionFault_(void);\r
+\r
+/** @fn void _coreClearInstructionFault_(void)\r
+* @brief Clear core instruction fault status register\r
+*/\r
+void _coreClearInstructionFault_(void);\r
+\r
+/** @fn uint32_t _coreGetDataFaultAddress_(void)\r
+* @brief Get core data fault address register\r
+* @return The function will return the data fault address:\r
+*/\r
+uint32_t _coreGetDataFaultAddress_(void);\r
+\r
+/** @fn void _coreClearDataFaultAddress_(void)\r
+* @brief Clear core data fault address register\r
+*/\r
+void _coreClearDataFaultAddress_(void);\r
+\r
+/** @fn uint32_t _coreGetInstructionFaultAddress_(void)\r
+* @brief Get core instruction fault address register\r
+* @return The function will return the instruction fault address:\r
+*/\r
+uint32_t _coreGetInstructionFaultAddress_(void);\r
+\r
+/** @fn void _coreClearInstructionFaultAddress_(void)\r
+* @brief Clear core instruction fault address register\r
+*/\r
+void _coreClearInstructionFaultAddress_(void);\r
+\r
+/** @fn uint32_t _coreGetAuxiliaryDataFault_(void)\r
+* @brief Get core axiliary data fault status register\r
+* @return The function will return the axiliary data fault status register value:\r
+* - bit [13..5]:\r
+* - Index value for access giving error\r
+* - bit [21]: \r
+* - 0: Unrecoverable error\r
+* - 1: Recoverable error\r
+* - bit [23..22]:\r
+* - 0: Side cache\r
+* - 1: Side ATCM (Flash)\r
+* - 2: Side BTCM (RAM)\r
+* - 3: Reserved\r
+* - bit [27..24]: \r
+* - Cach way or way in which error occured\r
+*/\r
+uint32_t _coreGetAuxiliaryDataFault_(void);\r
+\r
+/** @fn void _coreClearAuxiliaryDataFault_(void)\r
+* @brief Clear core axiliary data fault status register\r
+*/\r
+void _coreClearAuxiliaryDataFault_(void);\r
+\r
+/** @fn uint32_t _coreGetAuxiliaryInstructionFault_(void)\r
+* @brief Get core axiliary instruction fault status register\r
+* @return The function will return the axiliary instruction fault status register value:\r
+* - bit [13..5]:\r
+* - Index value for access giving error\r
+* - bit [21]: \r
+* - 0: Unrecoverable error\r
+* - 1: Recoverable error\r
+* - bit [23..22]:\r
+* - 0: Side cache\r
+* - 1: Side ATCM (Flash)\r
+* - 2: Side BTCM (RAM)\r
+* - 3: Reserved\r
+* - bit [27..24]: \r
+* - Cach way or way in which error occured\r
+*/\r
+uint32_t _coreGetAuxiliaryInstructionFault_(void);\r
+\r
+/** @fn void _coreClearAuxiliaryInstructionFault_(void)\r
+* @brief Clear core axiliary instruction fault status register\r
+*/\r
+void _coreClearAuxiliaryInstructionFault_(void);\r
+\r
+/** @fn void _disable_interrupt_(void)\r
+* @brief Disable IRQ and FIQ Interrupt mode in CPSR register\r
+*\r
+* This function disables IRQ and FIQ Interrupt mode in CPSR register.\r
+*/\r
+void _disable_interrupt_(void);\r
+\r
+/** @fn void _disable_IRQ_interrupt_(void)\r
+* @brief Disable IRQ Interrupt mode in CPSR register\r
+*\r
+* This function disables IRQ Interrupt mode in CPSR register.\r
+*/\r
+void _disable_IRQ_interrupt_(void);\r
+\r
+/** @fn void _disable_FIQ_interrupt_(void)\r
+* @brief Disable FIQ Interrupt mode in CPSR register\r
+*\r
+* This function disables IRQ Interrupt mode in CPSR register.\r
+*/\r
+void _disable_FIQ_interrupt_(void);\r
+\r
+/** @fn void _enable_interrupt_(void)\r
+* @brief Enable IRQ and FIQ Interrupt mode in CPSR register\r
+*\r
+* This function Enables IRQ and FIQ Interrupt mode in CPSR register.\r
+* User must call this function to enable Interrupts in non-OS environments.\r
+*/\r
+void _enable_interrupt_(void);\r
+\r
+/** @fn void _esmCcmErrorsClear_(void)\r
+* @brief Clears ESM Error caused due to CCM Errata in RevA Silicon\r
+*\r
+* This function Clears ESM Error caused due to CCM Errata \r
+* in RevA Silicon immediately after powerup.\r
+*/\r
+void _esmCcmErrorsClear_(void);\r
+\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file sys_mpu.h\r
+* @brief System Mpu Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Mpu Interface Functions\r
+* .\r
+* which are relevant for the memory protection unit driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#ifndef __SYS_MPU_H__\r
+#define __SYS_MPU_H__\r
+\r
+#include "sys_common.h"\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+/** @def mpuREGION1\r
+* @brief Mpu region 1\r
+*\r
+* Alias for Mpu region 1\r
+*/\r
+#define mpuREGION1 0U\r
+\r
+/** @def mpuREGION2\r
+* @brief Mpu region 2\r
+*\r
+* Alias for Mpu region 1\r
+*/\r
+#define mpuREGION2 1U\r
+\r
+/** @def mpuREGION3\r
+* @brief Mpu region 3\r
+*\r
+* Alias for Mpu region 3\r
+*/\r
+#define mpuREGION3 2U\r
+\r
+/** @def mpuREGION4\r
+* @brief Mpu region 4\r
+*\r
+* Alias for Mpu region 4\r
+*/\r
+#define mpuREGION4 3U\r
+\r
+/** @def mpuREGION5\r
+* @brief Mpu region 5\r
+*\r
+* Alias for Mpu region 5\r
+*/\r
+#define mpuREGION5 4U\r
+\r
+/** @def mpuREGION6\r
+* @brief Mpu region 6\r
+*\r
+* Alias for Mpu region 6\r
+*/\r
+#define mpuREGION6 5U\r
+\r
+/** @def mpuREGION7\r
+* @brief Mpu region 7\r
+*\r
+* Alias for Mpu region 7\r
+*/\r
+#define mpuREGION7 6U\r
+\r
+/** @def mpuREGION8\r
+* @brief Mpu region 8\r
+*\r
+* Alias for Mpu region 8\r
+*/\r
+#define mpuREGION8 7U\r
+\r
+/** @def mpuREGION9\r
+* @brief Mpu region 9\r
+*\r
+* Alias for Mpu region 9\r
+*/\r
+#define mpuREGION9 8U\r
+\r
+/** @def mpuREGION10\r
+* @brief Mpu region 10\r
+*\r
+* Alias for Mpu region 10\r
+*/\r
+#define mpuREGION10 9U\r
+\r
+/** @def mpuREGION11\r
+* @brief Mpu region 11\r
+*\r
+* Alias for Mpu region 11\r
+*/\r
+#define mpuREGION11 10U\r
+\r
+/** @def mpuREGION12\r
+* @brief Mpu region 12\r
+*\r
+* Alias for Mpu region 12\r
+*/\r
+#define mpuREGION12 11U\r
+\r
+\r
+\r
+\r
+/** @enum mpuRegionAccessPermission\r
+* @brief Alias names for mpu region access permissions\r
+*\r
+* This enumeration is used to provide alias names for the mpu region access permission:\r
+* - MPU_PRIV_NA_USER_NA_EXEC no access in priviledged mode, no access in user mode and execute\r
+* - MPU_PRIV_RW_USER_NA_EXEC read/write in priviledged mode, no access in user mode and execute\r
+* - MPU_PRIV_RW_USER_RO_EXEC read/write in priviledged mode, read only in user mode and execute\r
+* - MPU_PRIV_RW_USER_RW_EXEC read/write in priviledged mode, read/write in user mode and execute\r
+* - MPU_PRIV_RO_USER_NA_EXEC read only in priviledged mode, no access in user mode and execute\r
+* - MPU_PRIV_RO_USER_RO_EXEC read only in priviledged mode, read only in user mode and execute\r
+* - MPU_PRIV_NA_USER_NA_NOEXEC no access in priviledged mode, no access in user mode and no execution\r
+* - MPU_PRIV_RW_USER_NA_NOEXEC read/write in priviledged mode, no access in user mode and no execution\r
+* - MPU_PRIV_RW_USER_RO_NOEXEC read/write in priviledged mode, read only in user mode and no execution\r
+* - MPU_PRIV_RW_USER_RW_NOEXEC read/write in priviledged mode, read/write in user mode and no execution\r
+* - MPU_PRIV_RO_USER_NA_NOEXEC read only in priviledged mode, no access in user mode and no execution\r
+* - MPU_PRIV_RO_USER_RO_NOEXEC read only in priviledged mode, read only in user mode and no execution\r
+*\r
+*/\r
+enum mpuRegionAccessPermission\r
+{\r
+ MPU_PRIV_NA_USER_NA_EXEC = 0x0000, /**< Alias no access in priviledged mode, no access in user mode and execute */\r
+ MPU_PRIV_RW_USER_NA_EXEC = 0x0100, /**< Alias no read/write in priviledged mode, no access in user mode and execute */\r
+ MPU_PRIV_RW_USER_RO_EXEC = 0x0200, /**< Alias no read/write in priviledged mode, read only in user mode and execute */\r
+ MPU_PRIV_RW_USER_RW_EXEC = 0x0300, /**< Alias no read/write in priviledged mode, read/write in user mode and execute */\r
+ MPU_PRIV_RO_USER_NA_EXEC = 0x0500, /**< Alias no read only in priviledged mode, no access in user mode and execute */\r
+ MPU_PRIV_RO_USER_RO_EXEC = 0x0600, /**< Alias no read only in priviledged mode, read only in user mode and execute */\r
+ MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000, /**< Alias no access in priviledged mode, no access in user mode and no execution */\r
+ MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100, /**< Alias no read/write in priviledged mode, no access in user mode and no execution */\r
+ MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200, /**< Alias no read/write in priviledged mode, read only in user mode and no execution */\r
+ MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300, /**< Alias no read/write in priviledged mode, read/write in user mode and no execution */\r
+ MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500, /**< Alias no read only in priviledged mode, no access in user mode and no execution */\r
+ MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600 /**< Alias no read only in priviledged mode, read only in user mode and no execution */\r
+};\r
+\r
+/** @enum mpuRegionType\r
+* @brief Alias names for mpu region type\r
+*\r
+* This enumeration is used to provide alias names for the mpu region type:\r
+* - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and shareable\r
+* - MPU_DEVICE_SHAREABLE Memory type device and shareable\r
+* - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, no write allocate and non shared\r
+* - MPU_NORMAL_OIWTNOWA_SHARED Memory type normal outer and inner write-through, no write allocate and shared\r
+* - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no write allocate and non shared\r
+* - MPU_NORMAL_OIWBNOWA_SHARED Memory type normal outer and inner write-back, no write allocate and shared\r
+* - MPU_NORMAL_OINC_NONSHARED Memory type normal outer and inner non-cachable and non shared\r
+* - MPU_NORMAL_OINC_SHARED Memory type normal outer and inner non-cachable and shared\r
+* - MPU_NORMAL_OIWBWA_NONSHARED Memory type normal outer and inner write-back, write allocate and non shared\r
+* - MPU_NORMAL_OIWBWA_SHARED Memory type normal outer and inner write-back, write allocate and shared\r
+* - MPU_DEVICE_NONSHAREABLE Memory type device and non shareable\r
+*/\r
+enum mpuRegionType\r
+{\r
+ MPU_STRONGLYORDERED_SHAREABLE = 0x0000, /**< Memory type strongly ordered and shareable */\r
+ MPU_DEVICE_SHAREABLE = 0x0001, /**< Memory type device and shareable */\r
+ MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002, /**< Memory type normal outer and inner write-through, no write allocate and non shared */\r
+ MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003, /**< Memory type normal outer and inner write-back, no write allocate and non shared */\r
+ MPU_NORMAL_OIWTNOWA_SHARED = 0x0006, /**< Memory type normal outer and inner write-through, no write allocate and shared */\r
+ MPU_NORMAL_OIWBNOWA_SHARED = 0x0007, /**< Memory type normal outer and inner write-back, no write allocate and shared */\r
+ MPU_NORMAL_OINC_NONSHARED = 0x0008, /**< Memory type normal outer and inner non-cachable and non shared */\r
+ MPU_NORMAL_OIWBWA_NONSHARED = 0x000B, /**< Memory type normal outer and inner write-back, write allocate and non shared */\r
+ MPU_NORMAL_OINC_SHARED = 0x000C, /**< Memory type normal outer and inner non-cachable and shared */\r
+ MPU_NORMAL_OIWBWA_SHARED = 0x000F, /**< Memory type normal outer and inner write-back, write allocate and shared */\r
+ MPU_DEVICE_NONSHAREABLE = 0x0010 /**< Memory type device and non shareable */\r
+};\r
+\r
+/** @enum mpuRegionSize\r
+* @brief Alias names for mpu region type\r
+*\r
+* This enumeration is used to provide alias names for the mpu region type:\r
+* - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and shareable\r
+* - MPU_32_BYTES Memory size in bytes\r
+* - MPU_64_BYTES Memory size in bytes\r
+* - MPU_128_BYTES Memory size in bytes\r
+* - MPU_256_BYTES Memory size in bytes\r
+* - MPU_512_BYTES Memory size in bytes\r
+* - MPU_1_KB Memory size in kB\r
+* - MPU_2_KB Memory size in kB\r
+* - MPU_4_KB Memory size in kB\r
+* - MPU_8_KB Memory size in kB\r
+* - MPU_16_KB Memory size in kB\r
+* - MPU_32_KB Memory size in kB\r
+* - MPU_64_KB Memory size in kB\r
+* - MPU_128_KB Memory size in kB\r
+* - MPU_256_KB Memory size in kB\r
+* - MPU_512_KB Memory size in kB\r
+* - MPU_1_MB Memory size in MB\r
+* - MPU_2_MB Memory size in MB\r
+* - MPU_4_MB Memory size in MB\r
+* - MPU_8_MBv Memory size in MB\r
+* - MPU_16_MB Memory size in MB\r
+* - MPU_32_MB Memory size in MB\r
+* - MPU_64_MB Memory size in MB\r
+* - MPU_128_MB Memory size in MB\r
+* - MPU_256_MB Memory size in MB\r
+* - MPU_512_MB Memory size in MB\r
+* - MPU_1_GB Memory size in GB\r
+* - MPU_2_GB Memory size in GB\r
+* - MPU_4_GB Memory size in GB\r
+*/\r
+enum mpuRegionSize\r
+{\r
+ MPU_32_BYTES = 0x04, /**< Memory size in bytes */\r
+ MPU_64_BYTES = 0x05, /**< Memory size in bytes */\r
+ MPU_128_BYTES = 0x06, /**< Memory size in bytes */\r
+ MPU_256_BYTES = 0x07, /**< Memory size in bytes */\r
+ MPU_512_BYTES = 0x08, /**< Memory size in bytes */\r
+ MPU_1_KB = 0x09, /**< Memory size in kB */\r
+ MPU_2_KB = 0x0A, /**< Memory size in kB */\r
+ MPU_4_KB = 0x0B, /**< Memory size in kB */\r
+ MPU_8_KB = 0x0C, /**< Memory size in kB */\r
+ MPU_16_KB = 0x0D, /**< Memory size in kB */\r
+ MPU_32_KB = 0x0E, /**< Memory size in kB */\r
+ MPU_64_KB = 0x0F, /**< Memory size in kB */\r
+ MPU_128_KB = 0x10, /**< Memory size in kB */\r
+ MPU_256_KB = 0x11, /**< Memory size in kB */\r
+ MPU_512_KB = 0x12, /**< Memory size in kB */\r
+ MPU_1_MB = 0x13, /**< Memory size in MB */\r
+ MPU_2_MB = 0x14, /**< Memory size in MB */\r
+ MPU_4_MB = 0x15, /**< Memory size in MB */\r
+ MPU_8_MB = 0x16, /**< Memory size in MB */\r
+ MPU_16_MB = 0x17, /**< Memory size in MB */\r
+ MPU_32_MB = 0x18, /**< Memory size in MB */\r
+ MPU_64_MB = 0x19, /**< Memory size in MB */\r
+ MPU_128_MB = 0x1A, /**< Memory size in MB */\r
+ MPU_256_MB = 0x1B, /**< Memory size in MB */\r
+ MPU_512_MB = 0x1C, /**< Memory size in MB */\r
+ MPU_1_GB = 0x1D, /**< Memory size in GB */\r
+ MPU_2_GB = 0x1E, /**< Memory size in GB */\r
+ MPU_4_GB = 0x1F /**< Memory size in GB */\r
+};\r
+\r
+/** @fn void _mpuInit_(void)\r
+* @brief Initialize Mpu\r
+*\r
+* This function initalizes memory protection unit.\r
+*/\r
+void _mpuInit_(void);\r
+\r
+/** @fn void _mpuEnable_(void)\r
+* @brief Enable Mpu\r
+*\r
+* This function enables memory protection unit.\r
+*/\r
+void _mpuEnable_(void);\r
+\r
+/** @fn void _mpuDisable_(void)\r
+* @brief Disable Mpu\r
+*\r
+* This function disables memory protection unit.\r
+*/\r
+void _mpuDisable_(void);\r
+\r
+/** @fn void _mpuEnableBackgroundRegion_(void)\r
+* @brief Enable Mpu background region\r
+*\r
+* This function enables background region of the memory protection unit.\r
+*/\r
+void _mpuEnableBackgroundRegion_(void);\r
+\r
+/** @fn void _mpuDisableBackgroundRegion_(void)\r
+* @brief Disable Mpu background region\r
+*\r
+* This function disables background region of the memory protection unit.\r
+*/\r
+void _mpuDisableBackgroundRegion_(void);\r
+\r
+/** @fn uint32_t _mpuGetNumberOfRegions_(void)\r
+* @brief Returns number of implemented Mpu regions\r
+* @return Number of implemented mpu regions\r
+*\r
+* This function returns the number of implemented mpu regions.\r
+*/\r
+uint32_t _mpuGetNumberOfRegions_(void);\r
+\r
+/** @fn uint32_t _mpuAreRegionsSeparate_(void)\r
+* @brief Returns the type of the implemented mpu regions\r
+* @return Mpu type of regions\r
+*\r
+* This function returns 0 when mpu regions are of type unified atherwise regions are of type separate.\r
+*/\r
+uint32_t _mpuAreRegionsSeparate_(void);\r
+\r
+/** @fn void _mpuSetRegion_(uint32_t region)\r
+* @brief Set mpu region number\r
+*\r
+* This function selects one of the implemented mpu regions.\r
+*/\r
+void _mpuSetRegion_(uint32_t region);\r
+\r
+/** @fn uint32_t _mpuGetRegion_(void)\r
+* @brief Returns the currently selected mpu region\r
+* @return Mpu region number\r
+*\r
+* This function returns currently selected mpu region number.\r
+*/\r
+uint32_t _mpuGetRegion_(void);\r
+\r
+/** @fn void _mpuSetRegionBaseAddress_(uint32_t address)\r
+* @brief Set base address of currently selected mpu region\r
+* @note The base address must always aligned with region size\r
+*\r
+* This function sets the base address of currently selected mpu region.\r
+*/\r
+void _mpuSetRegionBaseAddress_(uint32_t address);\r
+\r
+/** @fn uint32_t _mpuGetRegionBaseAddress_(void)\r
+* @brief Returns base address of currently selected mpu region\r
+* @return Current base address of selected mpu region\r
+*\r
+* This function returns the base address of currently selected mpu region.\r
+*/\r
+uint32_t _mpuGetRegionBaseAddress_(void);\r
+\r
+/** @fn void _mpuSetRegionTypeAndPermission_(uint32_t type, uint32_t permission)\r
+* @brief Set type of currently selected mpu region\r
+*\r
+* This function sets the type of currently selected mpu region.\r
+*/\r
+void _mpuSetRegionTypeAndPermission_(uint32_t type, uint32_t permission);\r
+\r
+/** @fn uint32_t _mpuGetRegionType_(void)\r
+* @brief Returns the type of currently selected mpu region\r
+* @return Current type of selected mpu region\r
+*\r
+* This function returns the type of currently selected mpu region.\r
+*/\r
+uint32_t _mpuGetRegionType_(void);\r
+\r
+/** @fn uint32_t _mpuGetRegionPermission_(void)\r
+* @brief Returns permission of currently selected mpu region\r
+* @return Current type of selected mpu region\r
+*\r
+* This function returns permission of currently selected mpu region.\r
+*/\r
+uint32_t _mpuGetRegionPermission_(void);\r
+\r
+/** @fn void _mpuSetRegionSizeRegister_(uint32_t value)\r
+* @brief Set mpu region size register value\r
+*\r
+* This function sets mpu region size register value.\r
+*/\r
+void _mpuSetRegionSizeRegister_(uint32_t value);\r
+\r
+#endif\r
--- /dev/null
+/** @file sys_pmu.h\r
+* @brief System Pmu Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Pmu Interface Functions\r
+* .\r
+* which are relevant for the performance monitor unit driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#ifndef __SYS_PMU_H__\r
+#define __SYS_PMU_H__\r
+\r
+#include "sys_common.h"\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+/** @def pmuCOUNTER0\r
+* @brief pmu event counter 0\r
+*\r
+* Alias for pmu event counter 0\r
+*/\r
+#define pmuCOUNTER0 0x00000001U\r
+\r
+/** @def pmuCOUNTER1\r
+* @brief pmu event counter 1\r
+*\r
+* Alias for pmu event counter 1\r
+*/\r
+#define pmuCOUNTER1 0x00000002U\r
+\r
+/** @def pmuCOUNTER2\r
+* @brief pmu event counter 2\r
+*\r
+* Alias for pmu event counter 2\r
+*/\r
+#define pmuCOUNTER2 0x00000004U\r
+\r
+/** @def pmuCYCLE_COUNTER\r
+* @brief pmu cycle counter\r
+*\r
+* Alias for pmu event counter\r
+*/\r
+#define pmuCYCLE_COUNTER 0x80000000U\r
+\r
+/** @enum pmuEvent\r
+* @brief pmu event\r
+*\r
+* Alias for pmu event counter increment source\r
+*/\r
+enum pmuEvent\r
+{\r
+ PMU_INST_CACHE_MISS = 0x01,\r
+ PMU_DATA_CACHE_MISS = 0x03,\r
+ PMU_DATA_CACHE_ACCESS = 0x04,\r
+ PMU_DATA_READ_ARCH_EXECUTED = 0x06,\r
+ PMU_DATA_WRITE_ARCH_EXECUTED = 0x07,\r
+ PMU_INST_ARCH_EXECUTED = 0x08,\r
+ PMU_EXCEPTION_TAKEN = 0x09,\r
+ PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0A,\r
+ PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0B,\r
+ PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0C,\r
+ PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0D,\r
+ PMU_PROC_RETURN_ARCH_EXECUTED = 0x0E,\r
+ PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0F,\r
+ PMU_BRANCH_MISSPREDICTED = 0x10,\r
+ PMU_CYCLE_COUNT = 0x11,\r
+ PMU_PREDICTABLE_BRANCHES = 0x12,\r
+ PMU_INST_BUFFER_STALL = 0x40,\r
+ PMU_DATA_DEPENDENCY_INST_STALL = 0x41,\r
+ PMU_DATA_CACHE_WRITE_BACK = 0x42,\r
+ PMU_EXT_MEMORY_REQUEST = 0x43,\r
+ PMU_LSU_BUSY_STALL = 0x44,\r
+ PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45,\r
+ PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46,\r
+ PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47,\r
+ PMU_ETMEXTOUT_0 = 0x48,\r
+ PMU_ETMEXTOUT_1 = 0x49,\r
+ PMU_INST_CACHE_TAG_ECC_ERROR = 0x4A,\r
+ PMU_INST_CACHE_DATA_ECC_ERROR = 0x4B,\r
+ PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4C,\r
+ PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4D,\r
+ PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4E,\r
+ PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4F,\r
+ PMU_STORE_BUFFER_MERGE = 0x50,\r
+ PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51,\r
+ PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52,\r
+ PMU_INTEGER_DIV_EXECUTED = 0x53,\r
+ PMU_STALL_INTEGER_DIV = 0x54,\r
+ PMU_PLD_INST_LINE_FILL = 0x55,\r
+ PMU_PLD_INST_NO_LINE_FILL = 0x56,\r
+ PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57,\r
+ PMU_INST_CACHE_ACCESS = 0x58,\r
+ PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59,\r
+ PMU_DUAL_ISSUE_CASE_A = 0x5A,\r
+ PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5B,\r
+ PMU_DUAL_ISSUE_OTHER = 0x5C,\r
+ PMU_DP_FLOAT_INST_EXCECUTED = 0x5D,\r
+ PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5E,\r
+ PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60,\r
+ PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61,\r
+ PMU_PROCESSOR_LIVE_LOCK = 0x62,\r
+ PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64,\r
+ PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65,\r
+ PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66,\r
+ PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67,\r
+ PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68,\r
+ PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69,\r
+ PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6A,\r
+ PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6B,\r
+ PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6C,\r
+ PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6D\r
+};\r
+\r
+/** @fn void _pmuInit_(void)\r
+* @brief Initialize Perfprmance Monitor Unit\r
+*/\r
+void _pmuInit_(void);\r
+\r
+/** @fn void _pmuEnableCountersGlobal_(void)\r
+* @brief Enable and reset cycle counter and all 3 event counters\r
+*/\r
+void _pmuEnableCountersGlobal_(void);\r
+\r
+/** @fn void _pmuDisableCountersGlobal_(void)\r
+* @brief Disable cycle counter and all 3 event counters\r
+*/\r
+void _pmuDisableCountersGlobal_(void);\r
+\r
+/** @fn void _pmuResetCycleCounter_(void)\r
+* @brief Reset cycle counter\r
+*/\r
+void _pmuResetCycleCounter_(void);\r
+\r
+/** @fn void _pmuResetEventCounters_(void)\r
+* @brief Reset event counters 0-2\r
+*/\r
+void _pmuResetEventCounters_(void);\r
+\r
+/** @fn void _pmuResetCounters_(void)\r
+* @brief Reset cycle counter and event counters 0-2\r
+*/\r
+void _pmuResetCounters_(void);\r
+\r
+/** @fn void _pmuStartCounters_(uint32_t counters)\r
+* @brief Starts selected counters\r
+* @param[in] counters - Counter mask\r
+*/\r
+void _pmuStartCounters_(uint32_t counters);\r
+\r
+/** @fn void _pmuStopCounters_(uint32_t counters)\r
+* @brief Stops selected counters\r
+* @param[in] counters - Counter mask\r
+*/\r
+void _pmuStopCounters_(uint32_t counters);\r
+\r
+/** @fn void _pmuSetCountEvent_(uint32_t counter, uint32_t event)\r
+* @brief Set event counter count event\r
+* @param[in] counter - Counter select 0..2\r
+* @param[in] event - Count event\r
+*/\r
+void _pmuSetCountEvent_(uint32_t counter, uint32_t event);\r
+\r
+/** @fn uint32_t _pmuGetCycleCount_(void)\r
+* @brief Returns current cycle counter value\r
+*\r
+* @return cycle count.\r
+*/\r
+uint32_t _pmuGetCycleCount_(void);\r
+\r
+/** @fn uint32_t _pmuGetEventCount_(uint32_t counter)\r
+* @brief Returns current event counter value\r
+* @param[in] counter - Counter select 0..2\r
+*\r
+* @return event counter count.\r
+*/\r
+uint32_t _pmuGetEventCount_(uint32_t counter);\r
+\r
+/** @fn uint32_t _pmuGetOverflow_(void)\r
+* @brief Returns current overflow register and clear flags\r
+*\r
+* @return overflow flags.\r
+*/\r
+uint32_t _pmuGetOverflow_(void);\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file sys_selftest.h\r
+* @brief System Memory Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Efuse Self Test Functions\r
+* .\r
+* which are relevant for the System driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#ifndef __sys_selftest_H__\r
+#define __sys_selftest_H__\r
+\r
+#include "sys_common.h"\r
+#include "sys_core.h"\r
+#include "system.h"\r
+#include "sys_vim.h"\r
+#include "adc.h"\r
+#include "can.h"\r
+#include "mibspi.h"\r
+#include "het.h"\r
+#include "htu.h"\r
+#include "esm.h"\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+#define flash1bitError (*(unsigned int *) 0xF00803F0)\r
+#define flash2bitError (*(unsigned int *) 0xF00803F8)\r
+\r
+#define tcramA1bitError (*(unsigned int *)(0x08400000))\r
+#define tcramA2bitError (*(unsigned int *)(0x08400010))\r
+\r
+#define tcramB1bitError (*(unsigned int *)(0x08400008))\r
+#define tcramB2bitError (*(unsigned int *)(0x08400018))\r
+\r
+#define tcramA1bit (*(unsigned int *)0x08000000)\r
+#define tcramA2bit (*(unsigned int *)0x08000010)\r
+\r
+#define tcramB1bit (*(unsigned int *)0x08000008)\r
+#define tcramB2bit (*(unsigned int *)0x08000018)\r
+\r
+#define flashBadECC (*(unsigned int *)0x20080000)\r
+\r
+#define CCMSR (*(unsigned int *)0xFFFFF600U)\r
+#define CCMKEYR (*(unsigned int *)0xFFFFF604U)\r
+\r
+#define DMA_PARCR (*(unsigned int *)0xFFFFF1A8U)\r
+#define DMA_PARADDR (*(unsigned int *)0xFFFFF1ACU)\r
+\r
+#define DMARAMLOC (*(unsigned int *)0xFFF80000U)\r
+#define DMARAMPARLOC (*(unsigned int *)0xFFF80A00U)\r
+\r
+#ifndef __PBIST_H__\r
+#define __PBIST_H__\r
+\r
+/** @enum pbistPort\r
+* @brief Alias names for pbist Port number\r
+*\r
+* This enumeration is used to provide alias names for the pbist Port number\r
+* - PBIST_PORT0\r
+* - PBIST_PORT1\r
+*/\r
+enum pbistPort\r
+{\r
+ PBIST_PORT0 = 0, /**< Alias for PBIST Port 0 */\r
+ PBIST_PORT1 = 1 /**< Alias for PBIST Port 1 */\r
+};\r
+/** @enum pbistAlgo\r
+* @brief Alias names for pbist Algorithm\r
+*\r
+* This enumeration is used to provide alias names for the pbist Algorithm\r
+* - PBIST_TripleReadSlow \r
+* - PBIST_TripleReadFast \r
+* - PBIST_March13N_DP \r
+* - PBIST_March13N_SP \r
+* - PBIST_DOWN1a_DP \r
+* - PBIST_DOWN1a_SP \r
+* - PBIST_MapColumn_DP \r
+* - PBIST_MapColumn_SP \r
+* - PBIST_Precharge_DP \r
+* - PBIST_Precharge_SP \r
+* - PBIST_DTXN2a_DP \r
+* - PBIST_DTXN2a_SP \r
+* - PBIST_PMOSOpen_DP \r
+* - PBIST_PMOSOpen_SP \r
+* - PBIST_PPMOSOpenSlice1_DP\r
+* - PBIST_PPMOSOpenSlice1_SP\r
+* - PBIST_PPMOSOpenSlice2_DP\r
+* - PBIST_PPMOSOpenSlice2_SP\r
+\r
+*/\r
+enum pbistAlgo\r
+{\r
+ PBIST_TripleReadSlow = 0x00000001,\r
+ PBIST_TripleReadFast = 0x00000002,\r
+ PBIST_March13N_DP = 0x00000004,\r
+ PBIST_March13N_SP = 0x00000008,\r
+ PBIST_DOWN1a_DP = 0x00000010,\r
+ PBIST_DOWN1a_SP = 0x00000020,\r
+ PBIST_MapColumn_DP = 0x00000040,\r
+ PBIST_MapColumn_SP = 0x00000080,\r
+ PBIST_Precharge_DP = 0x00000100,\r
+ PBIST_Precharge_SP = 0x00000200,\r
+ PBIST_DTXN2a_DP = 0x00000400,\r
+ PBIST_DTXN2a_SP = 0x00000800,\r
+ PBIST_PMOSOpen_DP = 0x00001000,\r
+ PBIST_PMOSOpen_SP = 0x00002000,\r
+ PBIST_PPMOSOpenSlice1_DP = 0x00004000,\r
+ PBIST_PPMOSOpenSlice1_SP = 0x00008000,\r
+ PBIST_PPMOSOpenSlice2_DP = 0x00010000,\r
+ PBIST_PPMOSOpenSlice2_SP = 0x00020000\r
+};\r
+\r
+/* PBIST General Definitions */\r
+\r
+/** @struct pbistBase\r
+* @brief PBIST Base Register Definition\r
+*\r
+* This structure is used to access the PBIST module egisters.\r
+*/\r
+/** @typedef pbistBASE_t\r
+* @brief PBIST Register Frame Type Definition\r
+*\r
+* This type is used to access the PBIST Registers.\r
+*/\r
+typedef volatile struct pbistBase\r
+{\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1)) /* 0x0160: RAM Configuration Register */\r
+ uint32_t RLS : 2U; /* 0x0160: RAM Latency Select */\r
+ uint32_t PLS : 4U; /* 0x0160: Pipeline Latency Select */\r
+ uint32_t SMS : 2U; /* 0x0160: Sense Margin Select Register */\r
+ uint32_t DWR : 8U; /* 0x0160: Data Width Register */\r
+ uint32_t RDS : 8U; /* 0x0160: Return Data Select */\r
+ uint32_t RGS : 8U; /* 0x0160: RAM Group Select */\r
+#else\r
+ uint32_t RGS : 8U; /* 0x0160: RAM Group Select */\r
+ uint32_t RDS : 8U; /* 0x0160: Return Data Select */\r
+ uint32_t DWR : 8U; /* 0x0160: Data Width Register */\r
+ uint32_t SMS : 2U; /* 0x0160: Sense Margin Select Register */\r
+ uint32_t PLS : 4U; /* 0x0160: Pipeline Latency Select */\r
+ uint32_t RLS : 2U; /* 0x0160: RAM Latency Select */\r
+#endif\r
+\r
+ uint32_t DLR; /* 0x0164: Datalogger Register */\r
+ uint32_t : 32U; /* 0x0168 */\r
+ uint32_t : 32U; /* 0x016C */\r
+ uint32_t : 32U; /* 0x0170 */\r
+ uint32_t : 32U; /* 0x0174 */\r
+ uint32_t : 32U; /* 0x0178 */\r
+ uint32_t : 32U; /* 0x017C */\r
+ uint32_t PACT; /* 0x0180: PBIST Activate Register */\r
+ uint32_t PBISTID; /* 0x0184: PBIST ID Register */\r
+ uint32_t OVER; /* 0x0188: Override Register */\r
+ uint32_t : 32U; /* 0x018C */\r
+ uint32_t FSRF0; /* 0x0190: Fail Status Fail Register 0 */\r
+ uint32_t FSRF1; /* 0x0194: Fail Status Fail Register 1 */\r
+ uint32_t FSRC0; /* 0x0198: Fail Status Count Register 0 */\r
+ uint32_t FSRC1; /* 0x019C: Fail Status Count Register 1 */\r
+ uint32_t FSRA0; /* 0x01A0: Fail Status Address 0 Register */\r
+ uint32_t FSRA1; /* 0x01A4: Fail Status Address 1 Register */\r
+ uint32_t FSRDL0; /* 0x01A8: Fail Status Data Register 0 */\r
+ uint32_t : 32U; /* 0x01AC */\r
+ uint32_t FSRDL1; /* 0x01B0: Fail Status Data Register 1 */\r
+ uint32_t : 32U; /* 0x01B4 */\r
+ uint32_t : 32U; /* 0x01B8 */\r
+ uint32_t : 32U; /* 0x01BC */\r
+ uint32_t ROM; /* 0x01C0: ROM Mask Register */\r
+ uint32_t ALGO; /* 0x01C4: Algorithm Mask Register */\r
+ uint32_t RINFOL; /* 0x01C8: RAM Info Mask Lower Register */\r
+ uint32_t RINFOU; /* 0x01CC: RAM Info Mask Upper Register */\r
+} pbistBASE_t;\r
+\r
+#define pbistREG ((pbistBASE_t *)0xFFFFE560U)\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+/** @fn void memoryPort0TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data)\r
+* @brief Memory Port 0 test fail notification\r
+* @param[in] groupSelect Failing Ram group select:\r
+* @param[in] dataSelect Failing Ram data select:\r
+* @param[in] address Failing Ram offset:\r
+* @param[in] data Failing data at address:\r
+*\r
+* @note This function has to be provide by the user.\r
+*/\r
+void memoryPort0TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data);\r
+\r
+/** @fn void memoryPort1TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data)\r
+* @brief Memory Port 1 test fail notification\r
+* @param[in] groupSelect Failing Ram group select:\r
+* @param[in] dataSelect Failing Ram data select:\r
+* @param[in] address Failing Ram offset:\r
+* @param[in] data Failing data at address:\r
+*\r
+* @note This function has to be provide by the user.\r
+*/\r
+void memoryPort1TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data);\r
+\r
+#endif\r
+\r
+#ifndef __STC_H__\r
+#define __STC_H__\r
+\r
+/* STC General Definitions */\r
+\r
+/* STC Test Intervals supported in the Device */\r
+#define STC_INTERVAL 24\r
+#define STC_MAX_TIMEOUT 0xFFFFFFFF\r
+\r
+/** @struct stcBase\r
+* @brief STC Base Register Definition\r
+*\r
+* This structure is used to access the STC module egisters.\r
+*/\r
+/** @typedef stcBASE_t\r
+* @brief STC Register Frame Type Definition\r
+*\r
+* This type is used to access the STC Registers.\r
+*/\r
+typedef volatile struct stcBase\r
+{\r
+ uint32_t STCGCR0; /**< 0x0000: STC Control Register 0 */\r
+ uint32_t STCGCR1; /**< 0x0004: STC Control Register 1 */\r
+ uint32_t STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */\r
+ uint32_t STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */\r
+ uint32_t STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */\r
+ uint32_t STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */\r
+ uint32_t STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */\r
+ uint32_t CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */\r
+ uint32_t CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */\r
+ uint32_t CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */\r
+ uint32_t CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */\r
+ uint32_t CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */\r
+ uint32_t CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */\r
+ uint32_t CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */\r
+ uint32_t CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */\r
+ uint32_t STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */\r
+} stcBASE_t;\r
+\r
+#define stcREG ((stcBASE_t *)0xFFFFE600U)\r
+\r
+#endif\r
+\r
+#ifndef __EFC_H__\r
+#define __EFC_H__\r
+\r
+typedef volatile struct efcBase\r
+{\r
+ unsigned int INSTRUCTION; /* 0x0 INSTRUCTION AN DUMPWORD REGISTER */\r
+ unsigned int ADDRESS; /* 0x4 ADDRESS REGISTER */\r
+ unsigned int DATA_UPPER; /* 0x8 DATA UPPER REGISTER */\r
+ unsigned int DATA_LOWER; /* 0xc DATA LOWER REGISTER */\r
+ unsigned int SYSTEM_CONFIG; /* 0x10 SYSTEM CONFIG REGISTER */\r
+ unsigned int SYSTEM_STATUS; /* 0x14 SYSTEM STATUS REGISTER */\r
+ unsigned int ACCUMULATOR; /* 0x18 ACCUMULATOR REGISTER */\r
+ unsigned int BOUNDARY; /* 0x1C BOUNDARY REGISTER */\r
+ unsigned int KEY_FLAG; /* 0x20 KEY FLAG REGISTER */\r
+ unsigned int KEY; /* 0x24 KEY REGISTER */\r
+ unsigned int : 32; /* 0x28 RESERVED */\r
+ unsigned int PINS; /* 0x2C PINS REGISTER */\r
+ unsigned int CRA; /* 0x30 CRA */\r
+ unsigned int READ; /* 0x34 READ REGISTER */\r
+ unsigned int PROGRAMME; /* 0x38 PROGRAMME REGISTER */\r
+ unsigned int ERROR; /* 0x3C ERROR STATUS REGISTER */\r
+ unsigned int SINGLE_BIT; /* 0x40 SINGLE BIT ERROR */\r
+ unsigned int TWO_BIT_ERROR; /* 0x44 DOUBLE BIT ERROR */\r
+ unsigned int SELF_TEST_CYCLES; /* 0x48 SELF TEST CYCLEX */\r
+ unsigned int SELF_TEST_SIGN; /* 0x4C SELF TEST SIGNATURE */\r
+} efcBASE_t;\r
+\r
+#define efcREG ((efcBASE_t *)0xFFF8C000U)\r
+\r
+#define INPUT_ENABLE 0x0000000F\r
+#define INPUT_DISABLE 0x00000000\r
+\r
+#define SYS_WS_READ_STATES 0x00000000\r
+\r
+\r
+#define SYS_REPAIR_EN_0 0x00000000\r
+#define SYS_REPAIR_EN_3 0x00000100\r
+#define SYS_REPAIR_EN_5 0x00000200\r
+\r
+#define SYS_DEID_AUTOLOAD_EN 0x00000400\r
+#define SYS_DEID_AUTOLOAD_EN 0x00000400\r
+\r
+#define EFC_FDI_EN 0x00000800\r
+#define EFC_FDI_DIS 0x00000000\r
+\r
+#define SYS_ECC_OVERRIDE_EN 0x00001000\r
+#define SYS_ECC_OVERRIDE_DIS 0x00000000\r
+\r
+#define SYS_ECC_SELF_TEST_EN 0x00002000\r
+#define SYS_ECC_SELF_TEST_DIS 0x00000000\r
+\r
+#define OUTPUT_ENABLE 0x0003C000\r
+#define OUTPUT_DISABLE 0x00000000\r
+\r
+/*********** OUTPUT **************/\r
+\r
+#define EFC_AUTOLOAD_ERROR_EN 0x00040000\r
+#define EFC_INSTRUCTION_ERROR_EN 0x00080000\r
+#define EFC_INSTRUCTION_INFO_EN 0x00100000\r
+#define EFC_SELF_TEST_ERROR_EN 0x00200000\r
+\r
+\r
+#define EFC_AUTOLOAD_ERROR_DIS 0x00000000\r
+#define EFC_INSTRUCTION_ERROR_DIS 0x00000000\r
+#define EFC_INSTRUCTION_INFO_DIS 0x00000000\r
+#define EFC_SELF_TEST_ERROR_DIS 0x00000000\r
+\r
+#define DISABLE_READ_ROW0 0x00800000\r
+\r
+/********************************************************************/\r
+\r
+#define SYS_REPAIR_0 0x00000010\r
+#define SYS_REPAIR_3 0x00000010\r
+#define SYS_REPAIR_5 0x00000020\r
+\r
+#define SYS_DEID_AUTOLOAD 0x00000040\r
+#define SYS_FCLRZ 0x00000080\r
+#define EFC_READY 0x00000100\r
+#define SYS_ECC_OVERRIDE 0x00000200\r
+#define EFC_AUTOLOAD_ERROR 0x00000400\r
+#define EFC_INSTRUCTION_ERROR 0x00000800\r
+#define EFC_INSTRUCTION_INFO 0x00001000\r
+#define SYS_ECC_SELF_TEST 0x00002000\r
+#define EFC_SELF_TEST_ERROR 0x00004000\r
+#define EFC_SELF_TEST_DONE 0x00008000\r
+\r
+/************** 0x3C error status register ******************************************************/\r
+\r
+#define TIME_OUT 0x01\r
+#define AUTOLOAD_NO_FUSEROM_DATA 0x02 \r
+#define AUTOLOAD_SIGN_FAIL 0x03\r
+#define AUTOLOAD_PROG_INTERRUPT 0x04\r
+#define AUTOLOAD_TWO_BIT_ERR 0x05\r
+#define PROGRAME_WR_P_SET 0x06\r
+#define PROGRAME_MNY_DATA_ITERTN 0x07\r
+#define PROGRAME_MNY_CNTR_ITERTN 0x08\r
+#define UN_PROGRAME_BIT_SET 0x09\r
+#define REDUNDANT_REPAIR_ROW 0x0A\r
+#define PROGRAME_MNY_CRA_ITERTN 0x0B\r
+#define PROGRAME_SAME_DATA 0x0C\r
+#define PROGRAME_CMP_SKIP 0x0D\r
+#define PROGRAME_ABORT 0x0E\r
+#define PROGRAME_INCORRECT_KEY 0x0F\r
+#define FUSEROM_LASTROW_STUCK 0x10\r
+#define AUTOLOAD_SINGLE_BIT_ERR 0x15\r
+#define DUMPWORD_TWO_BIT_ERR 0x16\r
+#define DUMPWORD_ONE_BIT_ERR 0x17\r
+#define SELF_TEST_ERROR 0x18\r
+\r
+#define INSTRUCTION_DONE 0x20\r
+\r
+/************** Efuse Instruction set ******************************************************/\r
+\r
+#define TEST_UNPROGRAME_ROM 0x01000000\r
+#define PROGRAME_CRA 0x02000000 \r
+#define DUMP_WORD 0x04000000\r
+#define LOAD_FUSE_SCAN_CHAIN 0x05000000\r
+#define PROGRAME_DATA 0x07000000\r
+#define RUN_AUTOLOAD_8 0x08000000\r
+#define RUN_AUTOLOAD_A 0x0A000000\r
+\r
+#endif\r
+\r
+/* safety Init Interface Functions */\r
+void ccmSelfCheck(void);\r
+void ccmFail(unsigned int);\r
+\r
+void stcSelfCheck(void);\r
+void stcSelfCheckFail(void);\r
+void cpuSelfTest(unsigned int no_of_intervals, unsigned int max_timeout, boolean_t restart_test);\r
+void cpuSelfTestFail(void);\r
+\r
+void _memoryInit_(uint32_t);\r
+\r
+void pbistSelfCheck(void);\r
+void pbistRun(unsigned int, unsigned int);\r
+void pbistStop(void);\r
+void pbistSelfCheckFail(void);\r
+boolean_t pbistIsTestCompleted(void);\r
+boolean_t pbistIsTestPassed(void);\r
+boolean_t pbistPortTestStatus(uint32_t port);\r
+\r
+void efcCheck(void);\r
+void efcSelfTest(void);\r
+boolean_t efcStuckZeroTest(void);\r
+boolean_t checkefcSelfTest(void);\r
+void efcClass1Error(void);\r
+void efcClass2Error(void);\r
+\r
+void fmcBus2Check(void);\r
+void fmcECCcheck(void);\r
+void fmcClass1Error(void);\r
+void fmcClass2Error(void);\r
+\r
+void checkB0RAMECC(void);\r
+void checkB1RAMECC(void);\r
+void tcramClass1Error(void);\r
+void tcramClass2Error(void);\r
+\r
+void checkFlashECC(void);\r
+void flashClass1Error(void);\r
+void flashClass2Error(void);\r
+\r
+void vimParityCheck(void);\r
+void dmaParityCheck(void);\r
+void adc1ParityCheck(void);\r
+void adc2ParityCheck(void);\r
+void het1ParityCheck(void);\r
+void htu1ParityCheck(void);\r
+void het2ParityCheck(void);\r
+void htu2ParityCheck(void);\r
+void can1ParityCheck(void);\r
+void can2ParityCheck(void);\r
+void can3ParityCheck(void);\r
+void mibspi1ParityCheck(void);\r
+void mibspi3ParityCheck(void);\r
+void mibspi5ParityCheck(void);\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+#endif\r
--- /dev/null
+/** @file sys_vim.h\r
+* @brief Vectored Interrupt Module Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - VIM Type Definitions\r
+* - VIM General Definitions\r
+* .\r
+* which are relevant for Vectored Interrupt Controller.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#ifndef __SYS_VIM_H__\r
+#define __SYS_VIM_H__\r
+\r
+#include "sys_common.h"\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* VIM Type Definitions */\r
+\r
+/** @typedef t_isrFuncPTR\r
+* @brief ISR Function Pointer Type Definition\r
+*\r
+* This type is used to access the ISR handler.\r
+*/\r
+typedef void (*t_isrFuncPTR)();\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+/* VIM General Configuration */\r
+\r
+#define VIM_CHANNELS 96U\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+/* Interrupt Handlers */\r
+\r
+extern void phantomInterrupt(void);\r
+extern void esmHighInterrupt(void);\r
+extern void phantomInterrupt(void);\r
+extern void vPreemptiveTick(void);\r
+extern void sciHighLevelInterrupt(void);\r
+\r
+\r
+/* Vim Register Frame Definition */\r
+/** @struct vimBase\r
+* @brief Vim Register Frame Definition\r
+*\r
+* This type is used to access the Vim Registers.\r
+*/\r
+/** @typedef vimBASE_t\r
+* @brief VIM Register Frame Type Definition\r
+*\r
+* This type is used to access the VIM Registers.\r
+*/\r
+typedef volatile struct vimBase\r
+{\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t IRQIVEC : 8U; /* 0x0000 */\r
+ uint32_t : 24U; /* 0x0000 */\r
+ uint32_t FIQIVEC : 8U; /* 0x0004 */\r
+ uint32_t : 24U; /* 0x0004 */\r
+#else\r
+ uint32_t : 24U; /* 0x0000 */\r
+ uint32_t IRQIVEC : 8U; /* 0x0000 */\r
+ uint32_t : 24U; /* 0x0004 */\r
+ uint32_t FIQIVEC : 8U; /* 0x0004 */\r
+#endif\r
+ uint32_t : 32U; /* 0x0008 */\r
+ uint32_t : 32U; /* 0x000C */\r
+ uint32_t FIRQPR0; /* 0x0010 */\r
+ uint32_t FIRQPR1; /* 0x0014 */\r
+ uint32_t FIRQPR2; /* 0x0018 */\r
+ uint32_t FIRQPR3; /* 0x001C */\r
+ uint32_t INTREQ0; /* 0x0020 */\r
+ uint32_t INTREQ1; /* 0x0024 */\r
+ uint32_t INTREQ2; /* 0x0028 */\r
+ uint32_t INTREQ3; /* 0x002C */\r
+ uint32_t REQMASKSET0; /* 0x0030 */\r
+ uint32_t REQMASKSET1; /* 0x0034 */\r
+ uint32_t REQMASKSET2; /* 0x0038 */\r
+ uint32_t REQMASKSET3; /* 0x003C */\r
+ uint32_t REQMASKCLR0; /* 0x0040 */\r
+ uint32_t REQMASKCLR1; /* 0x0044 */\r
+ uint32_t REQMASKCLR2; /* 0x0048 */\r
+ uint32_t REQMASKCLR3; /* 0x004C */\r
+ uint32_t WAKEMASKSET0; /* 0x0050 */\r
+ uint32_t WAKEMASKSET1; /* 0x0054 */\r
+ uint32_t WAKEMASKSET2; /* 0x0058 */\r
+ uint32_t WAKEMASKSET3; /* 0x005C */\r
+ uint32_t WAKEMASKCLR0; /* 0x0060 */\r
+ uint32_t WAKEMASKCLR1; /* 0x0064 */\r
+ uint32_t WAKEMASKCLR2; /* 0x0068 */\r
+ uint32_t WAKEMASKCLR3; /* 0x006C */\r
+ uint32_t IRQVECREG; /* 0x0070 */\r
+ uint32_t FIQVECREQ; /* 0x0074 */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t CAPEVTSRC0 : 7U; /* 0x0078 */\r
+ uint32_t : 9U; /* 0x0078 */\r
+ uint32_t CAPEVTSRC1 : 7U; /* 0x0078 */\r
+ uint32_t : 9U; /* 0x0078 */\r
+#else\r
+ uint32_t : 9U; /* 0x0078 */\r
+ uint32_t CAPEVTSRC1 : 7U; /* 0x0078 */\r
+ uint32_t : 9U; /* 0x0078 */\r
+ uint32_t CAPEVTSRC0 : 7U; /* 0x0078 */\r
+#endif\r
+ uint32_t : 32U; /* 0x007C */\r
+ uint8_t CHANMAP[64U]; /* 0x0080-0x017C */\r
+} vimBASE_t;\r
+\r
+#define vimREG ((vimBASE_t *)0xFFFFFE00U)\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+#define VIM_PARFLG (*(unsigned int *)0xFFFFFDECU)\r
+#define VIM_PARCTL (*(unsigned int *)0xFFFFFDF0U)\r
+#define VIM_ADDERR (*(unsigned int *)0xFFFFFDF4U)\r
+#define VIM_FBPARERR (*(unsigned int *)0xFFFFFDF8U)\r
+\r
+#define VIMRAMPARLOC (*(unsigned int *)0xFFF82400U)\r
+#define VIMRAMLOC (*(unsigned int *)0xFFF82000U)\r
+\r
+#endif\r
--- /dev/null
+/** @file system.h\r
+* @brief System Driver Header File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+* \r
+* This file contains:\r
+* - Definitions\r
+* - Types\r
+* .\r
+* which are relevant for the System driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+#ifndef __SYS_SYSTEM_H__\r
+#define __SYS_SYSTEM_H__\r
+\r
+#include "sys_common.h"\r
+#include "gio.h"\r
+\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* System General Definitions */\r
+\r
+/** @enum systemInterrupt\r
+* @brief Alias names for clock sources\r
+*\r
+* This enumeration is used to provide alias names for the clock sources:\r
+* - IRQ\r
+* - FIQ\r
+*/\r
+enum systemInterrupt\r
+{\r
+ SYS_IRQ, /**< Alias for IRQ interrupt */\r
+ SYS_FIQ /**< Alias for FIQ interrupt */\r
+};\r
+\r
+/** @enum systemClockSource\r
+* @brief Alias names for clock sources\r
+*\r
+* This enumeration is used to provide alias names for the clock sources:\r
+* - Oscillator\r
+* - Pll1\r
+* - External1\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - PLL2\r
+* - External2\r
+* - Synchronous VCLK1\r
+*/\r
+enum systemClockSource\r
+{\r
+ SYS_OSC = 0, /**< Alias for oscillator clock Source */\r
+ SYS_PLL1 = 1, /**< Alias for Pll1 clock Source */\r
+ SYS_EXTERNAL1 = 3, /**< Alias for external clock Source */\r
+ SYS_LPO_LOW = 4, /**< Alias for low power oscillator low clock Source */\r
+ SYS_LPO_HIGH = 5, /**< Alias for low power oscillator high clock Source */\r
+ SYS_PLL2 = 6, /**< Alias for Pll2 clock Source */\r
+ SYS_EXTERNAL2 = 7, /**< Alias for external 2 clock Source */\r
+ SYS_VCLK = 9 /**< Alias for synchronous VCLK1 clock Source */\r
+};\r
+\r
+#define SYS_DOZE_MODE 0x000F3F02U\r
+#define SYS_SNOOZE_MODE 0x000F3F03U\r
+#define SYS_SLEEP_MODE 0x000FFFFFU\r
+#define LPO_TRIM_VALUE (((*(uint32_t *)0xF00801B4U) & 0xFFFF0000)>>16)\r
+#define SYS_EXCEPTION (*(uint32_t *)0xFFFFFFE4U)\r
+\r
+#define POWERON_RESET 0x8000\r
+#define OSC_FAILURE_RESET 0x4000\r
+#define WATCHDOG_RESET 0x2000\r
+#define ICEPICK_RESET 0x2000\r
+#define CPU_RESET 0x0020\r
+#define SW_RESET 0x0010\r
+\r
+#define WATCHDOG_STATUS (*(uint32_t *)0xFFFFFC98U)\r
+#define DEVICE_ID_REV (*(uint32_t *)0xFFFFFFF0U)\r
+\r
+/** @def OSC_FREQ\r
+* @brief Oscillator clock source exported from HALCoGen GUI\r
+*\r
+* Oscillator clock source exported from HALCoGen GUI\r
+*/\r
+#define OSC_FREQ 16.0\r
+\r
+/** @def PLL1_FREQ\r
+* @brief PLL 1 clock source exported from HALCoGen GUI\r
+*\r
+* PLL 1 clock source exported from HALCoGen GUI\r
+*/\r
+#define PLL1_FREQ 160.00\r
+\r
+/** @def LPO_LF_FREQ\r
+* @brief LPO Low Freq Oscillator source exported from HALCoGen GUI\r
+*\r
+* LPO Low Freq Oscillator source exported from HALCoGen GUI\r
+*/\r
+#define LPO_LF_FREQ 0.080\r
+\r
+/** @def LPO_HF_FREQ\r
+* @brief LPO High Freq Oscillator source exported from HALCoGen GUI\r
+*\r
+* LPO High Freq Oscillator source exported from HALCoGen GUI\r
+*/\r
+#define LPO_HF_FREQ 10.000\r
+\r
+/** @def PLL1_FREQ\r
+* @brief PLL 2 clock source exported from HALCoGen GUI\r
+*\r
+* PLL 2 clock source exported from HALCoGen GUI\r
+*/\r
+#define PLL2_FREQ 160.00\r
+\r
+/** @def GCLK_FREQ\r
+* @brief GCLK domain frequency exported from HALCoGen GUI\r
+*\r
+* GCLK domain frequency exported from HALCoGen GUI\r
+*/\r
+#define GCLK_FREQ 160.000\r
+\r
+/** @def HCLK_FREQ\r
+* @brief HCLK domain frequency exported from HALCoGen GUI\r
+*\r
+* HCLK domain frequency exported from HALCoGen GUI\r
+*/\r
+#define HCLK_FREQ 160.000\r
+\r
+/** @def RTI_FREQ\r
+* @brief RTI Clock frequency exported from HALCoGen GUI\r
+*\r
+* RTI Clock frequency exported from HALCoGen GUI\r
+*/\r
+#define RTI_FREQ 80.000\r
+\r
+/** @def AVCLK1_FREQ\r
+* @brief AVCLK1 Domain frequency exported from HALCoGen GUI\r
+*\r
+* AVCLK Domain frequency exported from HALCoGen GUI\r
+*/\r
+#define AVCLK1_FREQ 80.000\r
+\r
+/** @def AVCLK2_FREQ\r
+* @brief AVCLK2 Domain frequency exported from HALCoGen GUI\r
+*\r
+* AVCLK2 Domain frequency exported from HALCoGen GUI\r
+*/\r
+#define AVCLK2_FREQ 80.000\r
+\r
+/** @def AVCLK3_FREQ\r
+* @brief AVCLK3 Domain frequency exported from HALCoGen GUI\r
+*\r
+* AVCLK3 Domain frequency exported from HALCoGen GUI\r
+*/\r
+#define AVCLK3_FREQ 80.000\r
+\r
+/** @def VCLK1_FREQ\r
+* @brief VCLK1 Domain frequency exported from HALCoGen GUI\r
+*\r
+* VCLK1 Domain frequency exported from HALCoGen GUI\r
+*/\r
+#define VCLK1_FREQ 80.000\r
+\r
+/** @def VCLK2_FREQ\r
+* @brief VCLK2 Domain frequency exported from HALCoGen GUI\r
+*\r
+* VCLK2 Domain frequency exported from HALCoGen GUI\r
+*/\r
+#define VCLK2_FREQ 80.000\r
+\r
+\r
+/** @def SYS_PRE1\r
+* @brief Alias name for RTI1CLK PRE clock source\r
+*\r
+* This is an alias name for the RTI1CLK pre clock source.\r
+* This can be either:\r
+* - Oscillator\r
+* - Pll\r
+* - 32 kHz Oscillator\r
+* - External\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - Flexray Pll\r
+*/\r
+#define SYS_PRE1 SYS_PLL1\r
+\r
+/** @def SYS_PRE2\r
+* @brief Alias name for RTI2CLK pre clock source\r
+*\r
+* This is an alias name for the RTI2CLK pre clock source.\r
+* This can be either:\r
+* - Oscillator\r
+* - Pll\r
+* - 32 kHz Oscillator\r
+* - External\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - Flexray Pll\r
+*/\r
+#define SYS_PRE2 SYS_PLL1\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+/* System Register Frame 1 Definition */\r
+/** @struct systemBase1\r
+* @brief System Register Frame 1 Definition\r
+*\r
+* This type is used to access the System 1 Registers.\r
+*/\r
+/** @typedef systemBASE1_t\r
+* @brief System Register Frame 1 Type Definition\r
+*\r
+* This type is used to access the System 1 Registers.\r
+*/\r
+typedef volatile struct systemBase1\r
+{\r
+ uint32_t SYSPC1; /* 0x0000 */\r
+ uint32_t SYSPC2; /* 0x0004 */\r
+ uint32_t SYSPC3; /* 0x0008 */\r
+ uint32_t SYSPC4; /* 0x000C */\r
+ uint32_t SYSPC5; /* 0x0010 */\r
+ uint32_t SYSPC6; /* 0x0014 */\r
+ uint32_t SYSPC7; /* 0x0018 */\r
+ uint32_t SYSPC8; /* 0x001C */\r
+ uint32_t SYSPC9; /* 0x0020 */\r
+ uint32_t SSWPLL1; /* 0x0024 */\r
+ uint32_t SSWPLL2; /* 0x0028 */\r
+ uint32_t SSWPLL3; /* 0x002C */\r
+ uint32_t CSDIS; /* 0x0030 */\r
+ uint32_t CSDISSET; /* 0x0034 */\r
+ uint32_t CSDISCLR; /* 0x0038 */\r
+ uint32_t CDDIS; /* 0x003C */\r
+ uint32_t CDDISSET; /* 0x0040 */\r
+ uint32_t CDDISCLR; /* 0x0044 */\r
+ uint32_t GHVSRC; /* 0x0048 */\r
+ uint32_t VCLKASRC; /* 0x004C */\r
+ uint32_t RCLKSRC; /* 0x0050 */\r
+ uint32_t CSVSTAT; /* 0x0054 */\r
+ uint32_t MSTGCR; /* 0x0058 */\r
+ uint32_t MINITGCR; /* 0x005C */\r
+ uint32_t MSINENA; /* 0x0060 */\r
+ uint32_t MSTFAIL; /* 0x0064 */\r
+ uint32_t MSTCGSTAT; /* 0x0068 */\r
+ uint32_t MINISTAT; /* 0x006C */\r
+ uint32_t PLLCTL1; /* 0x0070 */\r
+ uint32_t PLLCTL2; /* 0x0074 */\r
+ uint32_t UERFLAG; /* 0x0078 */\r
+ uint32_t DIEIDL; /* 0x007C */\r
+ uint32_t DIEIDH; /* 0x0080 */\r
+ uint32_t VRCTL; /* 0x0084 */\r
+ uint32_t LPOMONCTL; /* 0x0088 */\r
+ uint32_t CLKTEST; /* 0x008C */\r
+ uint32_t DFTCTRLREG1; /* 0x0090 */\r
+ uint32_t DFTCTRLREG2; /* 0x0094 */\r
+ uint32_t : 32U; /* 0x0098 */\r
+ uint32_t : 32U; /* 0x009C */\r
+ uint32_t GPREG1; /* 0x00A0 */\r
+ uint32_t BTRMSEL; /* 0x00A4 */\r
+ uint32_t IMPFASTS; /* 0x00A8 */\r
+ uint32_t IMPFTADD; /* 0x00AC */\r
+ uint32_t SSISR1; /* 0x00B0 */\r
+ uint32_t SSISR2; /* 0x00B4 */\r
+ uint32_t SSISR3; /* 0x00B8 */\r
+ uint32_t SSISR4; /* 0x00BC */\r
+ uint32_t RAMGCR; /* 0x00C0 */\r
+ uint32_t BMMCR1; /* 0x00C4 */\r
+ uint32_t BMMCR2; /* 0x00C8 */\r
+ uint32_t MMUGCR; /* 0x00CC */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t : 8U; /* 0x00D0 */\r
+ uint32_t PENA : 1U; /* 0x00D0 */\r
+ uint32_t : 7U; /* 0x00D0 */\r
+ uint32_t VCLKR : 4U; /* 0x00D0 */\r
+ uint32_t : 4U; /* 0x00D0 */\r
+ uint32_t VCLK2R : 4U; /* 0x00D0 */\r
+ uint32_t : 4U; /* 0x00D0 */\r
+#else\r
+ uint32_t : 4U; /* 0x00D0 */\r
+ uint32_t VCLK2R : 4U; /* 0x00D0 */\r
+ uint32_t : 4U; /* 0x00D0 */\r
+ uint32_t VCLKR : 4U; /* 0x00D0 */\r
+ uint32_t : 7U; /* 0x00D0 */\r
+ uint32_t PENA : 1U; /* 0x00D0 */\r
+ uint32_t : 8U; /* 0x00D0 */\r
+#endif\r
+ uint32_t ECPCNTL; /* 0x00D4 */\r
+ uint32_t DSPGCR; /* 0x00D8 */\r
+ uint32_t DEVCR1; /* 0x00DC */\r
+ uint32_t SYSECR; /* 0x00E0 */\r
+ uint32_t SYSESR; /* 0x00E4 */\r
+ uint32_t SYSTASR; /* 0x00E8 */\r
+ uint32_t GBLSTAT; /* 0x00EC */\r
+ uint32_t DEV; /* 0x00F0 */\r
+ uint32_t SSIVEC; /* 0x00F4 */\r
+ uint32_t SSIF; /* 0x00F8 */\r
+ uint32_t SSIR1; /* 0x00FC */ \r
+} systemBASE1_t;\r
+\r
+\r
+/** @def systemREG1\r
+* @brief System Register Frame 1 Pointer\r
+*\r
+* This pointer is used by the system driver to access the system frame 1 registers.\r
+*/\r
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)\r
+\r
+/** @def systemPORT\r
+* @brief ECLK GIO Port Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access I/O PORT of System/Eclk\r
+* (use the GIO drivers to access the port pins).\r
+*/\r
+#define systemPORT ((gioPORT_t *)0xFFFFFF04U)\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+\r
+/* System Register Frame 2 Definition */\r
+/** @struct systemBase2\r
+* @brief System Register Frame 2 Definition\r
+*\r
+* This type is used to access the System 2 Registers.\r
+*/\r
+/** @typedef systemBASE2_t\r
+* @brief System Register Frame 2 Type Definition\r
+*\r
+* This type is used to access the System 2 Registers.\r
+*/\r
+typedef volatile struct systemBase2\r
+{\r
+ uint32_t PLLCTL3; /* 0x0000 */\r
+ uint32_t : 32U; /* 0x0004 */\r
+ uint32_t STCCLKDIV; /* 0x0008 */\r
+ uint32_t : 32U; /* 0x000C */\r
+ uint32_t : 32U; /* 0x0010 */\r
+ uint32_t : 32U; /* 0x0014 */\r
+ uint32_t : 32U; /* 0x0018 */\r
+ uint32_t : 32U; /* 0x001C */\r
+ uint32_t : 32U; /* 0x0020 */\r
+ uint32_t ECPCNTRL0; /* 0x0024 */\r
+ uint32_t : 32U; /* 0x0028 */\r
+ uint32_t : 32U; /* 0x002C */\r
+ uint32_t : 32U; /* 0x0030 */\r
+ uint32_t : 32U; /* 0x0034 */\r
+ uint32_t : 32U; /* 0x0038 */\r
+#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))\r
+ uint32_t VCLK3R : 4U; /* 0x003C */\r
+ uint32_t : 4U; /* 0x003C */\r
+ uint32_t VCLK4R : 4U; /* 0x003C */\r
+ uint32_t : 20U; /* 0x003C */\r
+#else\r
+ uint32_t : 20U; /* 0x003C */\r
+ uint32_t VCLK4R : 4U; /* 0x003C */\r
+ uint32_t : 4U; /* 0x003C */\r
+ uint32_t VCLK3R : 4U; /* 0x003C */\r
+#endif \r
+ uint32_t VCLKACON1; /* 0x0040 */\r
+ uint32_t : 32U; /* 0x0044 */\r
+ uint32_t : 32U; /* 0x0048*/\r
+ uint32_t : 32U; /* 0x004C */\r
+ uint32_t : 32U; /* 0x0050 */\r
+ uint32_t : 32U; /* 0x0054 */\r
+ uint32_t : 32U; /* 0x0058 */\r
+ uint32_t : 32U; /* 0x005C */\r
+ uint32_t : 32U; /* 0x0060 */\r
+ uint32_t : 32U; /* 0x0064 */\r
+ uint32_t : 32U; /* 0x0068 */\r
+ uint32_t : 32U; /* 0x006C */\r
+ uint32_t CLKSLIP; /* 0x0070 */\r
+ uint32_t : 32U; /* 0x0074 */\r
+ uint32_t : 32U; /* 0x0078*/\r
+ uint32_t : 32U; /* 0x007C */\r
+ uint32_t : 32U; /* 0x0080 */\r
+ uint32_t : 32U; /* 0x0084 */\r
+ uint32_t : 32U; /* 0x0088 */\r
+ uint32_t : 32U; /* 0x008C */\r
+ uint32_t : 32U; /* 0x0090 */\r
+ uint32_t : 32U; /* 0x0094 */\r
+ uint32_t : 32U; /* 0x0098 */\r
+ uint32_t : 32U; /* 0x009C */\r
+ uint32_t : 32U; /* 0x00A0 */\r
+ uint32_t : 32U; /* 0x00A4 */\r
+ uint32_t : 32U; /* 0x00A8 */\r
+ uint32_t : 32U; /* 0x00AC */\r
+ uint32_t : 32U; /* 0x00B0 */\r
+ uint32_t : 32U; /* 0x00B4 */\r
+ uint32_t : 32U; /* 0x00B8 */\r
+ uint32_t : 32U; /* 0x00BC */\r
+ uint32_t : 32U; /* 0x00C0 */\r
+ uint32_t : 32U; /* 0x00C4 */\r
+ uint32_t : 32U; /* 0x00C8 */\r
+ uint32_t : 32U; /* 0x00CC */\r
+ uint32_t : 32U; /* 0x00D0 */\r
+ uint32_t : 32U; /* 0x00D4 */\r
+ uint32_t : 32U; /* 0x00D8 */\r
+ uint32_t : 32U; /* 0x00DC */\r
+ uint32_t : 32U; /* 0x00E0 */\r
+ uint32_t : 32U; /* 0x00E4 */\r
+ uint32_t : 32U; /* 0x00E8 */\r
+ uint32_t EFC_CTLEN; /* 0x00EC */\r
+ uint32_t DIEIDL_REG0; /* 0x00F0 */\r
+ uint32_t DIEIDH_REG1; /* 0x00F4 */\r
+ uint32_t DIEIDL_REG2; /* 0x00F8 */\r
+ uint32_t DIEIDH_REG3; /* 0x00FC */\r
+} systemBASE2_t;\r
+\r
+\r
+/** @def systemREG2\r
+* @brief System Register Frame 2 Pointer\r
+*\r
+* This pointer is used by the system driver to access the system frame 2 registers.\r
+*/\r
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+\r
+/** @struct pcrBase\r
+* @brief Pcr Register Frame Definition\r
+*\r
+* This type is used to access the Pcr Registers.\r
+*/\r
+/** @typedef pcrBASE_t\r
+* @brief PCR Register Frame Type Definition\r
+*\r
+* This type is used to access the PCR Registers.\r
+*/\r
+typedef volatile struct pcrBase\r
+{\r
+ uint32_t PMPROTSET0; /* 0x0000 */\r
+ uint32_t PMPROTSET1; /* 0x0004 */\r
+ uint32_t : 32U; /* 0x0008 */\r
+ uint32_t : 32U; /* 0x000C */\r
+ uint32_t PMPROTCLR0; /* 0x0010 */\r
+ uint32_t PMPROTCLR1; /* 0x0014 */\r
+ uint32_t : 32U; /* 0x0018 */\r
+ uint32_t : 32U; /* 0x001C */\r
+ uint32_t PPROTSET0; /* 0x0020 */\r
+ uint32_t PPROTSET1; /* 0x0024 */\r
+ uint32_t PPROTSET2; /* 0x0028 */\r
+ uint32_t PPROTSET3; /* 0x002C */\r
+ uint32_t : 32U; /* 0x0030 */\r
+ uint32_t : 32U; /* 0x0034 */\r
+ uint32_t : 32U; /* 0x0038 */\r
+ uint32_t : 32U; /* 0x003C */\r
+ uint32_t PPROTCLR0; /* 0x0040 */\r
+ uint32_t PPROTCLR1; /* 0x0044 */\r
+ uint32_t PPROTCLR2; /* 0x0048 */\r
+ uint32_t PPROTCLR3; /* 0x004C */\r
+ uint32_t : 32U; /* 0x0050 */\r
+ uint32_t : 32U; /* 0x0054 */\r
+ uint32_t : 32U; /* 0x0058 */\r
+ uint32_t : 32U; /* 0x005C */\r
+ uint32_t PCSPWRDWNSET0; /* 0x0060 */\r
+ uint32_t PCSPWRDWNSET1; /* 0x0064 */\r
+ uint32_t : 32U; /* 0x0068 */\r
+ uint32_t : 32U; /* 0x006C */\r
+ uint32_t PCSPWRDWNCLR0; /* 0x0070 */\r
+ uint32_t PCSPWRDWNCLR1; /* 0x0074 */\r
+ uint32_t : 32U; /* 0x0078 */\r
+ uint32_t : 32U; /* 0x007C */\r
+ uint32_t PSPWRDWNSET0; /* 0x0080 */\r
+ uint32_t PSPWRDWNSET1; /* 0x0084 */\r
+ uint32_t PSPWRDWNSET2; /* 0x0088 */\r
+ uint32_t PSPWRDWNSET3; /* 0x008C */\r
+ uint32_t : 32U; /* 0x0090 */\r
+ uint32_t : 32U; /* 0x0094 */\r
+ uint32_t : 32U; /* 0x0098 */\r
+ uint32_t : 32U; /* 0x009C */\r
+ uint32_t PSPWRDWNCLR0; /* 0x00A0 */\r
+ uint32_t PSPWRDWNCLR1; /* 0x00A4 */\r
+ uint32_t PSPWRDWNCLR2; /* 0x00A8 */\r
+ uint32_t PSPWRDWNCLR3; /* 0x00AC */\r
+} pcrBASE_t;\r
+\r
+/** @def pcrREG\r
+* @brief Pcr Register Frame Pointer\r
+*\r
+* This pointer is used by the system driver to access the Pcr registers.\r
+*/\r
+#define pcrREG ((pcrBASE_t *)0xFFFFE000U)\r
+\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+\r
+\r
+/* FlashW General Definitions */\r
+\r
+\r
+/** @enum flashWPowerModes\r
+* @brief Alias names for flash bank power modes\r
+*\r
+* This enumeration is used to provide alias names for the flash bank power modes:\r
+* - sleep\r
+* - standby\r
+* - active\r
+*/\r
+enum flashWPowerModes\r
+{\r
+ SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */\r
+ SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */\r
+ SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */\r
+};\r
+\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+\r
+\r
+/** @struct flashWBase\r
+* @brief Flash Wrapper Register Frame Definition\r
+*\r
+* This type is used to access the Flash Wrapper Registers.\r
+*/\r
+/** @typedef flashWBASE_t\r
+* @brief Flash Wrapper Register Frame Type Definition\r
+*\r
+* This type is used to access the Flash Wrapper Registers.\r
+*/\r
+typedef volatile struct flashWBase\r
+{\r
+ uint32_t FRDCNTL; /* 0x0000 */\r
+ uint32_t FSPRD; /* 0x0004 */\r
+ uint32_t FEDACCTRL1; /* 0x0008 */\r
+ uint32_t FEDACCTRL2; /* 0x000C */\r
+ uint32_t FCORERRCNT; /* 0x0010 */\r
+ uint32_t FCORERRADD; /* 0x0014 */\r
+ uint32_t FCORERRPOS; /* 0x0018 */\r
+ uint32_t FEDACSTATUS; /* 0x001C */\r
+ uint32_t FUNCERRADD; /* 0x0020 */\r
+ uint32_t FEDACSDIS; /* 0x0024 */\r
+ uint32_t FPRIMADDTAG; /* 0x0028 */\r
+ uint32_t FREDUADDTAG; /* 0x002C */\r
+ uint32_t FBPROT; /* 0x0030 */\r
+ uint32_t FBSE; /* 0x0034 */\r
+ uint32_t FBBUSY; /* 0x0038 */\r
+ uint32_t FBAC; /* 0x003C */\r
+ uint32_t FBFALLBACK; /* 0x0040 */\r
+ uint32_t FBPRDY; /* 0x0044 */\r
+ uint32_t FPAC1; /* 0x0048 */\r
+ uint32_t FPAC2; /* 0x004C */\r
+ uint32_t FMAC; /* 0x0050 */\r
+ uint32_t FMSTAT; /* 0x0054 */\r
+ uint32_t FEMUDMSW; /* 0x0058 */\r
+ uint32_t FEMUDLSW; /* 0x005C */\r
+ uint32_t FEMUECC; /* 0x0060 */\r
+ uint32_t FLOCK; /* 0x0064 */\r
+ uint32_t FEMUADDR; /* 0x0068 */\r
+ uint32_t FDIAGCTRL; /* 0x006C */\r
+ uint32_t FRAWDATAH; /* 0x0070 */\r
+ uint32_t FRAWDATAL; /* 0x0074 */\r
+ uint32_t FRAWECC; /* 0x0078 */\r
+ uint32_t FPAROVR; /* 0x007C */\r
+ uint32_t FVREADCT; /* 0x0080 */\r
+ uint32_t FVHVCT1; /* 0x0084 */\r
+ uint32_t FVHVCT2; /* 0x0088 */\r
+ uint32_t FVNVCT; /* 0x008C */\r
+ uint32_t FVPPCT; /* 0x0090 */\r
+ uint32_t FVWLCT; /* 0x0094 */\r
+ uint32_t FEFUSE; /* 0x0098 */\r
+ uint32_t : 32U; /* 0x009C */\r
+ uint32_t : 32U; /* 0x00A0 */\r
+ uint32_t : 32U; /* 0x00A4 */\r
+ uint32_t : 32U; /* 0x00A8 */\r
+ uint32_t : 32U; /* 0x00AC */\r
+ uint32_t : 32U; /* 0x00B0 */\r
+ uint32_t : 32U; /* 0x00B4 */\r
+ uint32_t : 32U; /* 0x00B8 */\r
+ uint32_t : 32U; /* 0x00BC */\r
+ uint32_t FEDACSDIS2; /* 0x00C0 */\r
+ uint32_t : 32U; /* 0x00C4 */\r
+ uint32_t : 32U; /* 0x00C8 */\r
+ uint32_t : 32U; /* 0x00CC */\r
+ uint32_t : 32U; /* 0x00D0 */\r
+ uint32_t : 32U; /* 0x00D4 */\r
+ uint32_t : 32U; /* 0x00D8 */\r
+ uint32_t : 32U; /* 0x00DC */\r
+ uint32_t : 32U; /* 0x00E0 */\r
+ uint32_t : 32U; /* 0x00E4 */\r
+ uint32_t : 32U; /* 0x00E8 */\r
+ uint32_t : 32U; /* 0x00EC */\r
+ uint32_t : 32U; /* 0x00F0 */\r
+ uint32_t : 32U; /* 0x00F4 */\r
+ uint32_t : 32U; /* 0x00F8 */\r
+ uint32_t : 32U; /* 0x00FC */\r
+ uint32_t FBSTROBES; /* 0x0100 */\r
+ uint32_t FPSTROBES; /* 0x0104 */\r
+ uint32_t FBMODE; /* 0x0108 */\r
+ uint32_t FTCR; /* 0x010C */\r
+ uint32_t FADDR; /* 0x0110 */\r
+ uint32_t FWRITE; /* 0x0114 */\r
+ uint32_t FCBITSEL; /* 0x0118 */\r
+ uint32_t FTCTRL; /* 0x011C */\r
+ uint32_t FWPWRITE0; /* 0x0120 */\r
+ uint32_t FWPWRITE1; /* 0x0124 */\r
+ uint32_t FWPWRITE2; /* 0x0128 */\r
+ uint32_t FWPWRITE3; /* 0x012C */\r
+ uint32_t FWPWRITE4; /* 0x0130 */\r
+} flashWBASE_t;\r
+\r
+/** @def flashWREG\r
+* @brief Flash Wrapper Register Frame Pointer\r
+*\r
+* This pointer is used by the system driver to access the flash wrapper registers.\r
+*/\r
+#define flashWREG ((flashWBASE_t *)(0xFFF87000U))\r
+\r
+#define FSM_WR_ENA (*(unsigned int *)0xFFF87288U)\r
+#define EEPROM_CONFIG (*(unsigned int *)0xFFF872B8U)\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+\r
+/* System Interface Functions */\r
+void systemInit(void);\r
+void systemPowerDown(uint32_t mode);\r
+\r
+\r
+/** @struct tcramBase\r
+* @brief TCRAM Wrapper Register Frame Definition\r
+*\r
+* This type is used to access the TCRAM Wrapper Registers.\r
+*/\r
+/** @typedef tcramBASE_t\r
+* @brief TCRAM Wrapper Register Frame Type Definition\r
+*\r
+* This type is used to access the TCRAM Wrapper Registers.\r
+*/\r
+\r
+typedef volatile struct tcramBase\r
+{\r
+ uint32_t RAMCTRL; /* 0x0000 */\r
+ uint32_t RAMTHRESHOLD; /* 0x0004 */\r
+ uint32_t RAMOCCUR; /* 0x0008 */\r
+ uint32_t RAMINTCTRL; /* 0x000C */\r
+ uint32_t RAMERRSTATUS; /* 0x0010 */\r
+ uint32_t RAMSERRADDR; /* 0x0014 */\r
+ uint32_t : 32U; /* 0x0018 */\r
+ uint32_t RAMUERRADDR; /* 0x001C */\r
+ uint32_t : 32U; /* 0x0020 */\r
+ uint32_t : 32U; /* 0x0024 */\r
+ uint32_t : 32U; /* 0x0028 */\r
+ uint32_t : 32U; /* 0x002C */\r
+ uint32_t RAMTEST; /* 0x0030 */\r
+ uint32_t : 32U; /* 0x0034 */\r
+ uint32_t RAMADDRDECVECT; /* 0x0038 */\r
+ uint32_t RAMPERADDR; /* 0x003C */\r
+} tcramBASE_t;\r
+\r
+#define tcram1REG ((tcramBASE_t *)(0xFFFFF800))\r
+#define tcram2REG ((tcramBASE_t *)(0xFFFFF900))\r
+\r
+\r
+#endif\r
--- /dev/null
+#include "cmd_proc.h"
+#include <string.h>
+#include <stdint.h>
+
+/**
+ * Blocking call to print a string.
+ *
+ * @param cmd_io cmd_io structure.
+ * @param str Zero terminated string to print.
+ *
+ * @return Upon successful completion, puts() shall return a
+ * non-negative number. In case of error, negative number is returned.
+ */
+int cmd_io_puts(cmd_io_t *cmd_io, const char *str)
+{
+ int ret;
+ unsigned len;
+ if (!str) return 0;
+ len = strlen(str);
+ do {
+ ret = cmd_io_write(cmd_io, str, len);
+ if (ret > 0) {
+ str+=ret;
+ len-=ret;
+ }
+ } while (ret>=0 && len>0);
+ return ret;
+}
+
+int cmd_io_write_bychar(cmd_io_t *cmd_io,const void *buf,int count)
+{
+ int cn=0;
+ uint8_t* p=(uint8_t*)buf;
+ while(count--&&(*cmd_io->putc)(cmd_io,*p++)>=0){
+ cn++;
+ }
+ return cn;
+}
+
+int cmd_io_read_bychar(cmd_io_t *cmd_io,void *buf,int count)
+{
+ int cn=0;
+ int ch;
+ uint8_t* p=(uint8_t*)buf;
+ while(count--&&(ch=(*cmd_io->getc)(cmd_io))>=0){
+ *p++=ch;
+ cn++;
+ }
+ return cn;
+}
+
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ cmd_proc.h - text line command processor
+ designed for instruments control and setup
+ over RS-232 line
+
+ Copyright (C) 2001 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002 by PiKRON Ltd. http://www.pikron.com
+ (C) 2007 by Michal Sojka <sojkam1@fel.cvut.cz>
+
+ This file can be used and copied according to next
+ license alternatives
+ - MPL - Mozilla Public License
+ - GPL - GNU Public License
+ - other license provided by project originators
+ *******************************************************************/
+
+#include "cmd_proc.h"
+#include "cmd_proc_priv.h"
+#include <string.h>
+
+/* cmd_io line editor */
+
+/**
+ * Adds new characters to an edit line buffer.
+ *
+ * @param elb Edit line buffer.
+ * @param ch character to add.
+ *
+ * @return 1 in case of end of line, 0 otherwise.
+ */
+int cmd_ed_line_buf(ed_line_buf_t *elb, int ch)
+{
+ int lastch=elb->lastch;
+ if (elb->flg&FL_ELB_INSEND)
+ return -1;
+ elb->lastch=ch;
+ if(!lastch){
+ elb->inbuf=0; /* Start new line */
+ }
+ if((!(elb->flg&FL_ELB_NOCRLF))&&((ch=='\n')||(ch=='\r'))){
+ if((lastch=='\n')&&(ch=='\r')) /* Empty line, ignore it. */
+ return 0;
+ elb->lastch=0; /* End the string */
+ elb->buf[elb->inbuf]=0;
+ return 1;
+ }
+ if(elb->inbuf>=elb->alloc-1){
+ /* try to reallocate buffer len not implemented */
+ return 0;
+ }
+ elb->buf[elb->inbuf++]=ch;
+ return 0;
+}
+
+int cmd_io_line_putc(cmd_io_t *cmd_io,int ch)
+{
+ return cmd_ed_line_buf(cmd_io->priv.ed_line.out,ch);
+}
+
+/* Process pending output */
+int cmd_io_line_out(cmd_io_t *cmd_io)
+{
+ cmd_io_t* io_stack=cmd_io->priv.ed_line.io_stack;
+ ed_line_buf_t* ed_line_out=cmd_io->priv.ed_line.out;
+
+ if(!ed_line_out->inbuf) return 0;
+ if(!io_stack)
+ return -1;
+
+ if(!(ed_line_out->flg&FL_ELB_INSEND)){
+ ed_line_out->flg|=FL_ELB_INSEND;
+ ed_line_out->lastch=0;
+ }
+ while(cmd_io_putc(io_stack, ed_line_out->buf[ed_line_out->lastch])>=0){
+ if(++ed_line_out->lastch >= ed_line_out->inbuf){
+ ed_line_out->lastch=0;
+ ed_line_out->inbuf=0;
+ ed_line_out->flg&=~FL_ELB_INSEND;
+ return 0;
+ }
+ }
+ return 1;
+}
+
+/* process input */
+int cmd_io_line_in(cmd_io_t *cmd_io)
+{
+ int ch;
+ cmd_io_t* io_stack = cmd_io->priv.ed_line.io_stack;
+ ed_line_buf_t *ed_line_in = cmd_io->priv.ed_line.in;
+
+ if(!io_stack)
+ return -1;
+
+ while((ch=cmd_io_getc(io_stack))>=0){
+// DPRINT("Added %c (%d)\n", ch, ch);
+ int eol = cmd_ed_line_buf(ed_line_in,ch);
+ if(eol){
+ if(ed_line_in->flg&FL_ELB_ECHO){
+ while(cmd_io_putc(io_stack,'\r')<0);
+ while(cmd_io_putc(io_stack,'\n')<0);
+ }
+ return 1;
+ }
+ else
+ if(ed_line_in->flg&FL_ELB_ECHO) {
+ while(cmd_io_putc(io_stack,ch)<0);
+ }
+ }
+ return 0;
+}
+
+/* The possibly blocking read of one line, should be used only
+ when other options fails */
+char *cmd_io_line_rdline(cmd_io_t *cmd_io, int mode)
+{
+ int ret;
+ while((ret=cmd_io_line_in(cmd_io))==0)
+ if(!mode) break;
+ if(ret<=0) return NULL;
+ return cmd_io->priv.ed_line.in->buf;
+}
+
+/* Local Variables: */
+/* c-basic-offset: 2 */
+/* End */
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ cmd_proc.c - text command processor
+ enables to define multilevel tables of commands
+ which can be received from more inputs and send reply
+ to respective I/O stream output
+
+ Copyright (C) 2001-2009 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002-2009 by PiKRON Ltd. http://www.pikron.com
+ (C) 2007 by Michal Sojka <sojkam1@fel.cvut.cz>
+
+ This file can be used and copied according to next
+ license alternatives
+ - MPL - Mozilla Public License
+ - GPL - GNU Public License
+ - other license provided by project originators
+ *******************************************************************/
+
+#include <stdint.h>
+#include <ctype.h>
+#include <string.h>
+#include <stdlib.h>
+#include "i2str.h"
+#include "cmd_proc.h"
+#include "cmd_proc_priv.h"
+
+/* cmd_line processing */
+
+char *skip_white(char *p)
+{
+ while(isspace((uint8_t)*p)) p++;
+ return p;
+}
+
+/**
+ *
+ * @return Zero if no command was given in line, -CMDERR_BADCMD if
+ * command is not known or has no function assigned to it. If a
+ * command is executed, then the return value of the command function
+ * is returned.
+ */
+int proc_cmd_line(cmd_io_t *cmd_io, cmd_des_t const **des_arr, char *line)
+{
+ char *p=line, *r, *var;
+ const cmd_des_t *des;
+ cmd_des_t const **arr_stack[CMD_ARR_STACK_SIZE];
+ int arr_stack_sp=0;
+ char *param[10];
+ short cmd_len;
+ int res, i, parcnt;
+ param[0]=p=skip_white(p);
+ if(!*p) return 0;
+ /* Determine the name of the command */
+ if(!isalnum((uint8_t)*p)){
+ cmd_len=1;
+ p++;
+ }else{
+ while(isalnum((uint8_t)*p)) p++;
+ cmd_len=p-param[0];
+ }
+ param[1]=param[2]=skip_white(p);
+
+ /* Find the command in des_arr */
+ while(1){
+ des=*(des_arr++);
+ if(!des){
+ if(!arr_stack_sp) break;
+ des_arr=arr_stack[--arr_stack_sp];
+ continue;
+ }
+ if(des==CMD_DES_CONTINUE_AT_ID){
+ /* list continues at new address */
+ des_arr=(const cmd_des_t **)*des_arr;continue;
+ }
+ if(des==CMD_DES_INCLUDE_SUBLIST_ID){
+ /* list includes commands from sublists */
+ if(arr_stack_sp>=CMD_ARR_STACK_SIZE){
+ des_arr++;
+ }else{
+ arr_stack[arr_stack_sp++]=des_arr+1;
+ des_arr=(const cmd_des_t **)*des_arr;
+ continue;
+ }
+ }
+ p=param[0];
+ if(!(r=des->name))continue;
+ i=cmd_len;
+ var=NULL;
+ while(*r){
+ while((*p==*r)&&i){i--;r++;p++;};
+ if((i==0)&&!*r) break; /* We've found the command */
+ if((*r=='?')&&i){
+ if(!var) var=p;
+ p++; r++; i--;
+ continue;
+ }
+ if((*r=='#')&&i&&isdigit((uint8_t)*p)){
+ if(!var) var=p;
+ p++; r++; i--;
+ continue;
+ }
+ if(*r=='*'){
+ if(!var) var=p;
+ i=0;
+ break;
+ }
+ i=1;
+ break;
+ }
+ if(i!=0) continue; /* Try next command */
+ if(des->mode&CDESM_OPCHR){
+ if(!param[2])continue;
+ if(!*param[2])continue;
+ param[3]=skip_white(param[2]+1);
+ param[1]=var;
+ parcnt=4;
+ }else{
+ parcnt=1;
+ if(var){param[1]=var;parcnt++;}
+ if(param[parcnt])
+ if(*param[parcnt]) parcnt++;
+ }
+ param[parcnt]=0;
+ if(!des->fnc) return -CMDERR_BADCMD;
+ res=des->fnc(cmd_io,des,param);
+ return res;
+ }
+ return -CMDERR_BADCMD;
+}
+
+/**
+ * Checks whether the the command allows the operation specified by
+ * opchar.
+ *
+ * @return opchar if perimssions allow this operations, -CMDERR_WRPERM
+ * or -CMDERR_RDPERM if the operation is not allows, -CMDERR_OPCHAR,
+ * if the opchar is not ':' or '?'.
+ */
+int cmd_opchar_check(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ int opchar=*param[2];
+ if(opchar==':'){
+ if(!(des->mode&CDESM_WR)){
+ return -CMDERR_WRPERM;
+ }
+ }else if(opchar=='?'){
+ if(!(des->mode&CDESM_RD)){
+ return -CMDERR_RDPERM;
+ }
+ }
+ else return -CMDERR_OPCHAR;
+ return opchar;
+}
+
+int cmd_num_suffix(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[], unsigned *pval)
+{
+ unsigned val=0;
+ unsigned x;
+ char *p;
+ p=param[1];
+ if(!p) return -CMDERR_BADSUF;
+
+ do{
+ x=*p-'0';
+ if((unsigned)x>9)
+ return -CMDERR_BADSUF;
+ val*=10;
+ val+=x;
+ p++;
+ }while(*p && !strchr(" :?=",*p));
+ *pval=val;
+ return 0;
+}
+
+
+int cmd_do_stamp(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ if(*param[2]!=':') return -CMDERR_OPCHAR;
+ cmd_io_write(cmd_io,param[0],param[2]-param[0]);
+ cmd_io_putc(cmd_io,'=');
+ cmd_io_write(cmd_io,param[3],strlen(param[3]));
+ return 0;
+}
+
+/**
+ * Implementation of a command that reads or writes short pointed by des->info.
+ */
+int cmd_do_rw_short(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ short val;
+ short *ptr;
+ int opchar;
+
+ if((opchar=cmd_opchar_check(cmd_io,des,param))<0) return opchar;
+ ptr=(short*)(des->info);
+ if(opchar==':'){
+ val=atoi(param[3]);
+ *ptr=val;
+ }else{
+ return cmd_opchar_replong(cmd_io, param, (long)*ptr, 0, 0);
+ }
+ return 0;
+}
+
+/**
+ * Implementation of a command that reads or writes int pointed by des->info.
+ */
+int cmd_do_rw_int(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ int val;
+ int *ptr;
+ int opchar;
+
+ if((opchar=cmd_opchar_check(cmd_io,des,param))<0) return opchar;
+ ptr=(int*)(des->info);
+ if(opchar==':'){
+ val=atoi(param[3]);
+ *ptr=val;
+ }else{
+ return cmd_opchar_replong(cmd_io, param, (long)*ptr, 0, 0);
+ }
+ return 0;
+}
+
+
+/**
+ * Implementation of a command that reads or writes long pointed by des->info.
+ */
+int cmd_do_rw_long(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ long val;
+ long *ptr;
+ int opchar;
+
+ if((opchar=cmd_opchar_check(cmd_io,des,param))<0) return opchar;
+ ptr=(long*)(des->info);
+ if(opchar==':'){
+ val=atol(param[3]);
+ *ptr=val;
+ }else{
+ return cmd_opchar_replong(cmd_io, param, (long)*ptr, 0, 0);
+ }
+ return 0;
+}
+
+/**
+ * Prints name of the command followed by '=' and the value of val.
+ */
+int cmd_opchar_replong(cmd_io_t *cmd_io, char *param[], long val,int len,int form)
+{
+ char str[20];
+ cmd_io_write(cmd_io,param[0],param[2]-param[0]);
+ cmd_io_putc(cmd_io,'=');
+ i2str(str,val,len,form);
+ cmd_io_write(cmd_io,str,strlen(str));
+ return 0;
+}
+
+#if 0
+
+int cmd_do_rw_bitflag(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ unsigned val,mask,*pval;
+ int opchar;
+
+ if((opchar=cmd_opchar_check(cmd_io,des,param))<0) return opchar;
+ pval=(unsigned*)(des->info);
+ mask=(unsigned)(des->info);
+ if(opchar==':'){
+ val=*param[3];
+ if(val=='0')
+ atomic_clear_mask(mask,pval);
+ else if(val=='1')
+ atomic_set_mask(mask,pval);
+ else return -CMDERR_BADPAR;
+ }else{
+ cmd_io_write(cmd_io,param[0],param[2]-param[0]);
+ cmd_io_putc(cmd_io,'=');
+ cmd_io_putc(cmd_io,*pval&mask?'1':'0');
+ }
+
+ return 0;
+}
+
+#endif
+
+/**
+ * Implementation of help command
+ */
+int cmd_do_help(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ char *help;
+ char *filt=param[1];
+ const cmd_des_t **des_arr=*(const cmd_des_t ***)des->info;
+ cmd_des_t const **arr_stack[CMD_ARR_STACK_SIZE];
+ int arr_stack_sp=0;
+
+ /* FIXME: This should not be there unconditional */
+ if (cmd_io->priv.ed_line.io_stack)
+ cmd_io = cmd_io->priv.ed_line.io_stack;
+
+ if(filt) {
+ filt=skip_white(filt);
+ if(!*filt) filt=NULL;
+ }
+ cmd_io_puts(cmd_io,"Help for commands\r\n");
+ while(1){
+ des=*(des_arr++);
+ if(!des){
+ if(!arr_stack_sp) break;
+ des_arr=arr_stack[--arr_stack_sp];
+ continue;
+ }
+ if(des==CMD_DES_CONTINUE_AT_ID){
+ /* list continues at new address */
+ des_arr=(const cmd_des_t **)*des_arr;
+ continue;
+ }
+ if(des==CMD_DES_INCLUDE_SUBLIST_ID){
+ /* list includes commands from sublists */
+ if(arr_stack_sp>=CMD_ARR_STACK_SIZE){
+ des_arr++;
+ }else{
+ arr_stack[arr_stack_sp++]=des_arr+1;
+ des_arr=(const cmd_des_t **)*des_arr;
+ continue;
+ }
+ }
+ if(des->name){
+ if(!filt || !strncmp(des->name,filt,strlen(filt))) {
+ help=des->help;
+ if(!help) help="?";
+ cmd_io_puts(cmd_io,des->name);
+ cmd_io_puts(cmd_io," - ");
+ cmd_io_puts(cmd_io,help);
+ cmd_io_puts(cmd_io, "\r\n");
+ }
+ }
+ }
+ return 0;
+}
+
+/* Local Variables: */
+/* c-basic-offset: 2 */
+/* End */
--- /dev/null
+/*
+ * cmd_proc_freertos_tms570.c
+ *
+ * Created on: 1.8.2012
+ * Author: Michal Horn
+ *
+ * All stuff that are needed for input commands via RS-232, processing command using CmdProc library and printing output back on RS-232.
+ *
+ */
+#include "cmd_proc_freertos_tms570.h"
+
+xTaskHandle processCmdHandler;
+uint8_t* prompt;
+extern cmd_des_t const *cmd_list_main[]; // Main list of commands
+extern cmd_io_t cmd_io_std_line; // IO stack
+
+void initCmdProc(unsigned portBASE_TYPE priority, uint8_t * introText, uint8_t * promptText) {
+ initIoBuffer();
+ prompt = (uint8_t *)pvPortMalloc(strlen((char*)promptText));
+ strcpy((char *)prompt, (const char*)promptText);
+ xTaskCreate(processCmd, (const signed char *)"processCmd", 200, NULL, priority, processCmdHandler);
+ sciSend(sciREG, strlen((char *)introText), (uint8_t *)introText);
+ sciSend(sciREG, strlen((char *)prompt), (uint8_t *)prompt);
+ sciReceive(sciREG, 1, NULL);
+}
+
+void processCmd(void *pvParameters ) {
+ for (;;) {
+ cmd_processor_run(&cmd_io_std_line, cmd_list_main);
+ printToOutputBuffer((uint8_t *)prompt, strlen((char*)prompt), portMAX_DELAY);
+ }
+}
+
+
+
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ cmd_proc.c - text command processor
+ enables to define multilevel tables of commands
+ which can be received from more inputs and send reply
+ to respective I/O stream output
+
+ Copyright (C) 2001-2009 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002-2009 by PiKRON Ltd. http://www.pikron.com
+ (C) 2007 by Michal Sojka <sojkam1@fel.cvut.cz>
+
+ This file can be used and copied according to next
+ license alternatives
+ - MPL - Mozilla Public License
+ - GPL - GNU Public License
+ - other license provided by project originators
+ *******************************************************************/
+
+#include "cmd_proc.h"
+#include "cmd_proc_priv.h"
+
+/**
+ * Executes command processor. This function is usually called from
+ * application's main loop.
+ */
+int cmd_processor_run(cmd_io_t *cmd_io, cmd_des_t const **commands)
+{
+ int val;
+
+ if(cmd_io_line_out(cmd_io))
+ return 1; /* Not all the output has been sent. */
+
+ if(cmd_io_line_in(cmd_io)<=0)
+ return 0; /* Input line not finished or error. */
+
+ if(commands){
+ val=proc_cmd_line(cmd_io, commands, cmd_io->priv.ed_line.in->buf);
+ }else{
+ val=-CMDERR_BADCMD;
+ }
+
+ if(cmd_io->priv.ed_line.out->inbuf){
+ cmd_io_putc(cmd_io,'\r');
+ cmd_io_putc(cmd_io,'\n');
+ }else if(val<0){
+ char s[20];
+ cmd_io_puts(cmd_io,"ERROR ");
+ i2str(s,-val,0,0);
+ cmd_io_puts(cmd_io,s);
+ cmd_io_putc(cmd_io,'\r');
+ cmd_io_putc(cmd_io,'\n');
+ }
+ cmd_io_line_out(cmd_io);
+ return 1; /* Command line processed */
+}
+
+
+/* Local Variables: */
+/* c-basic-offset: 2 */
+/* End */
--- /dev/null
+#include "cmd_proc.h"
+#include <string.h>
+
+#define ED_LINE_CHARS 80
+
+char ed_line_in_std[ED_LINE_CHARS+1];
+char ed_line_out_std[ED_LINE_CHARS+1];
+
+
+ed_line_buf_t ed_line_buf_in_std={
+ 0,
+ 0,
+ sizeof(ed_line_in_std),
+ 0,
+ 0,
+ ed_line_in_std
+};
+
+ed_line_buf_t ed_line_buf_out_std={
+ FL_ELB_NOCRLF,
+ 0,
+ sizeof(ed_line_out_std),
+ 0,
+ 0,
+ ed_line_out_std
+};
+
+extern cmd_io_t cmd_io_buf;
+const cmd_io_t cmd_io_std_line={
+ cmd_io_line_putc,
+ NULL,
+ cmd_io_write_bychar,
+ NULL,
+ {
+ {
+ &ed_line_buf_in_std,
+ &ed_line_buf_out_std,
+ &cmd_io_buf
+ }
+ }
+};
--- /dev/null
+/*
+ * cmdio_buffer.c
+ *
+ * Created on: 17.7.2012
+ * Author: Michal Horn
+ *
+ * Definition of IO. This implementation uses queues as buffers, which are than used for input and output.
+ *
+ */
+
+#include "cmdio_tisci.h"
+
+tBuffer outBuffer;
+tBuffer inBuffer;
+
+void initIoBuffer() {
+ outBuffer.buf = xQueueCreate(MAX_BUFFER_LEN, sizeof(uint8_t));
+ outBuffer.mutex = xSemaphoreCreateMutex();
+ outBuffer.initialized = 1;
+ inBuffer.buf = xQueueCreate(MAX_BUFFER_LEN, sizeof(uint8_t));
+ inBuffer.mutex = xSemaphoreCreateMutex();
+ inBuffer.initialized = 1;
+}
+portBASE_TYPE printToOutputBuffer(const uint8_t * string, uint32_t length, portTickType ticks) {
+ return print(&outBuffer, string, length, ticks);
+}
+portBASE_TYPE printToInputBuffer(const uint8_t * string, uint32_t length, portTickType ticks) {
+ return print(&inBuffer, string, length, ticks);
+}
+portBASE_TYPE readFromOutputBuffer(uint8_t * ch, portTickType ticks) {
+ return read(&outBuffer, ch, ticks);
+}
+portBASE_TYPE readFromInputBuffer(uint8_t * ch, portTickType ticks) {
+ return read(&inBuffer, ch, ticks);
+}
+portBASE_TYPE read(tBuffer* buffer, uint8_t * ch, portTickType ticks) {
+ portBASE_TYPE ret;
+ ret = xQueueReceive(buffer->buf, ch, ticks);
+ return ret;
+}
+portBASE_TYPE print(tBuffer* buffer, const uint8_t * string, uint32_t length, portTickType ticks) {
+ uint32_t i = 0;
+ portBASE_TYPE ret = pdPASS;
+ while (i < length && string[i] != '\0') {
+ ret = xQueueSend(buffer->buf, (void*)&string[i++], ticks);
+ }
+
+ return ret;
+}
+void clearInputBuffer() {
+ clearBuffer(&inBuffer);
+}
+void clearOutputBuffer() {
+ clearBuffer(&outBuffer);
+}
+void clearBuffer(tBuffer * buffer) {
+ while ((xQueueReceive(buffer->buf, NULL, 0)) != errQUEUE_EMPTY) // Delete content of queue
+ ;
+}
+
+int buf_putc(cmd_io_t *cmd_io, int ch) {
+ uint8_t c = (uint8_t)ch;
+ xSemaphoreTake(outBuffer.mutex, portMAX_DELAY);
+ if (print(&outBuffer, (uint8_t *)&c, 1, portMAX_DELAY) != pdPASS) {
+ xSemaphoreGive(outBuffer.mutex);
+ return 0;
+ }
+ xSemaphoreGive(outBuffer.mutex);
+ return 1;
+}
+
+int buf_getc(cmd_io_t *cmd_io) {
+ uint8_t ret = '\0';
+ xSemaphoreTake(inBuffer.mutex, portMAX_DELAY);
+ if (xQueueReceive(inBuffer.buf, &ret, portMAX_DELAY) != pdPASS) {
+ ret = '\0';
+ }
+ xSemaphoreGive(inBuffer.mutex);
+ return ret;
+}
+int buf_write(cmd_io_t *cmd_io, const void *buf, int count) {
+ const char *tmpBuf = buf;
+ int i = 0;
+ xSemaphoreTake(outBuffer.mutex, portMAX_DELAY);
+ while (i < count) {
+ print(&outBuffer, (uint8_t *)&tmpBuf[i], 1, portMAX_DELAY);
+ i++;
+ }
+ xSemaphoreGive(outBuffer.mutex);
+ return i;
+}
+int buf_read(cmd_io_t *cmd_io, void *buf, int count) {
+ char *tmpBuf = buf;
+ int i = 0;
+ xSemaphoreTake(inBuffer.mutex, portMAX_DELAY);
+
+ while (i < count) {
+ if (xQueueReceive(inBuffer.buf, &tmpBuf[i], 0) != pdPASS)
+ break;
+ i++;
+ }
+ xSemaphoreGive(inBuffer.mutex);
+ return i;
+}
+
+/* Setting io stack for cmdProc */
+cmd_io_t cmd_io_buf={
+ buf_putc,
+ buf_getc,
+ buf_write,
+ buf_read
+};
+
--- /dev/null
+/*
+ * commands.c
+ *
+ * Created on: 31.7.2012
+ * Author: Michal Horn
+ *
+ * Definition of commands for cmdProc library. Command are stored as lists.
+ *
+ */
+
+#include "cmd_proc.h"
+#include "sys_common.h"
+#include "cmdio_tisci.h"
+#include "string.h"
+#include "stdio.h"
+
+cmd_des_t const **cmd_list;
+
+/* ------------------------------
+ * User defined command functions
+ * ------------------------------
+ */
+int cmd_do_testopchar(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ int opchar;
+
+ opchar=cmd_opchar_check(cmd_io,des,param);
+ if(opchar<0) return opchar;
+ char str[] = {"\r\ncmd_do_testopchar called\r\nparam[0]="};
+
+ printToOutputBuffer((uint8_t *)str, strlen(str), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)param[0], strlen(param[0]), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)"\r\nparam[1]=", 11, portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)param[1], strlen(param[1]), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)"\r\nparam[2]=", 11, portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)param[2], strlen(param[2]), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)"\r\nparam[3]=", 11, portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)param[3], strlen(param[3]), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)"\r\nopchar=", 9, portMAX_DELAY);
+ char opcharBuf[4];
+ i2str(opcharBuf, opchar, 1, 10);
+ printToOutputBuffer((uint8_t *)opcharBuf, strlen(opcharBuf), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)"\r\n", 2, portMAX_DELAY);
+ return 0;
+}
+
+int cmd_do_testparam(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+
+ char str[] = {"cmd_do_testparam called\r\nparam[0]="};
+
+ printToOutputBuffer((uint8_t *)str, strlen(str), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)param[0], strlen(param[0]), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)"\r\nparam[1]=", 11, portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)param[1], strlen(param[1]), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)"\r\nparam[2]=", 11, portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)param[2], strlen(param[2]), portMAX_DELAY);
+ printToOutputBuffer((uint8_t *)"\r\n", 2, portMAX_DELAY);
+
+ return 0;
+}
+
+int cmd_do_testerror(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ return -1234;
+}
+
+int cmd_do_test(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ char str[] = {"This is the simplest command\r\n"};
+ printToOutputBuffer((uint8_t *)str, strlen(str), portMAX_DELAY);
+
+ return 0;
+}
+
+int cmd_do_testcmdio(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ cmd_io_puts(cmd_io, "The first line of text\r\n");
+ cmd_io_puts(cmd_io, "The second line of text\r\n");
+ /* Only ED_LINE_CHARS character can be sent. */
+ return 0;
+}
+
+
+/* ------------------------------
+ * User defined command variables
+ * ------------------------------
+ */
+int val;
+
+/* -------------------
+ * Command definitions
+ * -------------------
+ */
+cmd_des_t const cmd_des_help={
+ 0, 0,
+ "HELP","prints help for commands\r\n",
+ cmd_do_help, (void *)&cmd_list
+};
+
+cmd_des_t const cmd_des_val={
+ 0, CDESM_OPCHR|CDESM_RW,
+ "VAL","use ':' or '?' to store/read value of an integer variable",
+ cmd_do_rw_int, (void *)&val};
+
+cmd_des_t const cmd_des_valro={
+ 0, CDESM_OPCHR|CDESM_RD,
+ "VALRO","read only access to an integer variable",
+ cmd_do_rw_int, (void *)&val};
+
+cmd_des_t const cmd_des_valwo={
+ 0, CDESM_OPCHR|CDESM_WR,
+ "VALWO","write only access to an integer variable",
+ cmd_do_rw_int, (void *)&val};
+
+cmd_des_t const cmd_des_opchar_test={
+ 0, CDESM_OPCHR|CDESM_RW,
+ "OPCHAR","opchar test (use ':' or '?' as suffix)",
+ cmd_do_testopchar};
+
+cmd_des_t const cmd_des_testio={
+ 0, 0,
+ "TESTIO","test of cmd_io inside functions (universal way to print results)",
+ cmd_do_testcmdio};
+
+cmd_des_t const cmd_des_error={
+ 0, 0,
+ "TESTERROR","should produce an error",
+ cmd_do_testerror};
+
+cmd_des_t const cmd_des_param={
+ 0, 0,
+ "PARAM","test of parameters",
+ cmd_do_testparam};
+
+cmd_des_t const cmd_des_opchar_testro={
+ 0, CDESM_OPCHR|CDESM_RD,
+ "OPCHARRO","opchar test (only '?' is allowed)",
+ cmd_do_testopchar};
+
+cmd_des_t const cmd_des_test={
+ 0, 0,
+ "TEST","the simplest command",
+ cmd_do_test};
+
+cmd_des_t const cmd_des_prefix={
+ 0, 0,
+ "PREFIX*","suffix of the command is supplied as a parametr",
+ cmd_do_testparam};
+
+cmd_des_t const cmd_des_num={
+ 0, 0,
+ "NUM##","suffix of the command (two digits) is supplied as a parametr",
+ cmd_do_testparam};
+
+cmd_des_t const cmd_des_char={
+ 0, 0,
+ "CHAR?","suffix of the command (one character) is supplied as a parametr",
+ cmd_do_testparam};
+
+cmd_des_t const cmd_des_charmid={
+ 0, 0,
+ "CHAR?MID","middle character of the command is supplied as a parametr",
+ cmd_do_testparam};
+
+cmd_des_t const cmd_des_hiddedn={
+ 0, 0,
+ "HIDDEN","should not be available",
+ cmd_do_test};
+
+/* ------------------------
+ * Command lists definitons
+ * ------------------------
+ */
+cmd_des_t const *cmd_list_1[]={
+ &cmd_des_val,
+ &cmd_des_valro,
+ &cmd_des_valwo,
+ &cmd_des_opchar_test,
+ &cmd_des_opchar_testro,
+ NULL
+ };
+
+cmd_des_t const *cmd_list_2[]={
+ &cmd_des_test,
+ &cmd_des_testio,
+ &cmd_des_param,
+ &cmd_des_prefix,
+ &cmd_des_num,
+ &cmd_des_char,
+ &cmd_des_charmid,
+ NULL
+ };
+
+cmd_des_t const *cmd_list_main[]={
+ &cmd_des_help,
+ &cmd_des_error,
+ CMD_DES_INCLUDE_SUBLIST(cmd_list_1),
+ CMD_DES_CONTINUE_AT(cmd_list_2),
+ &cmd_des_hiddedn,
+ NULL
+};
+
+cmd_des_t const **cmd_list = cmd_list_main;
--- /dev/null
+;-------------------------------------------------------------------------------\r
+; dabort.asm\r
+;\r
+; (c) Texas Instruments 2009-2010, All rights reserved.\r
+;\r
+\r
+ .text\r
+ .arm\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Run Memory Test\r
+\r
+ .ref custom_dabort\r
+ .def _dabort\r
+ .asmfunc\r
+\r
+_dabort\r
+ stmfd r13!, {r0 - r12, lr}; push registers and link register on to stack\r
+\r
+ ldr r12, esmsr3 ; ESM Group3 status register\r
+ ldr r0, [r12]\r
+ tst r0, #0x8 ; check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM\r
+ bne ramErrorFound\r
+ tst r0, #0x20 ; check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM\r
+ bne ramErrorFound\r
+\r
+noRAMerror\r
+ tst r0, #0x80 ; check if bit 7 is set, this indicates uncorrectable ECC error on ATCM\r
+ bne flashErrorFound\r
+\r
+ bl custom_dabort ; custom data abort handler required\r
+ ; If this custom handler is written in assembly, all registers used in the routine\r
+ ; and the link register must be saved on to the stack upon entry, and restored before\r
+ ; return from the routine.\r
+\r
+ ldmfd r13!, {r0 - r12, lr}; pop registers and link register from stack\r
+ subs pc, lr, #8 ; restore state of CPU when abort occurred, and branch back to instruction that was aborted\r
+\r
+ramErrorFound\r
+ ldr r1, ramctrl ; RAM control register for B0TCM TCRAMW\r
+ ldr r2, [r1]\r
+ tst r2, #0x100 ; check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled\r
+ beq ramErrorReal\r
+ mov r2, #0x20\r
+ str r2, [r1, #0x10] ; clear RAM error status register\r
+ ldr r1, ram2ctrl\r
+ str r2, [r1, #0x10] ; clear RAM error status register\r
+\r
+ mov r2, #0x28\r
+ str r2, [r12] ; clear ESM group3 flags for uncorrectable RAM ECC errors\r
+ mov r2, #5\r
+ str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires\r
+\r
+ ldmfd r13!, {r0 - r12, lr}\r
+ subs pc, lr, #4 ; branch to instruction after the one that caused the abort\r
+ ; this is the case because the data abort was caused intentionally\r
+ ; and we do not want to cause the same data abort again.\r
+\r
+ramErrorReal\r
+ b ramErrorReal ; branch here forever as continuing operation is not recommended\r
+\r
+flashErrorFound\r
+ ldr r1, flashbase\r
+ ldr r2, [r1, #0x6C] ; read FDIAGCTRL register\r
+\r
+ mov r2, r2, lsr #16\r
+ tst r2, #5 ; check if bits 19:16 are 5, this indicates diagnostic mode is enabled\r
+ beq flashErrorReal\r
+ mov r2, #1\r
+ mov r2, r2, lsl #8 \r
+ \r
+ str r2, [r1, #0x1C] ; clear FEDACSTATUS error flag\r
+\r
+ mov r2, #0x80\r
+ str r2, [r12] ; clear ESM group3 flag for uncorrectable flash ECC error\r
+ mov r2, #5\r
+ str r2, [r12, #0x18] ; The nERROR pin will become inactive once the LTC counter expires\r
+\r
+ ldmfd r13!, {r0 - r12, lr}\r
+ subs pc, lr, #4 ; branch to instruction after the one that caused the abort\r
+ ; this is the case because the data abort was caused intentionally\r
+ ; and we do not want to cause the same data abort again.\r
+\r
+\r
+flashErrorReal\r
+ b flashErrorReal ; branch here forever as continuing operation is not recommended\r
+ \r
+esmsr3 .word 0xFFFFF520\r
+ramctrl .word 0xFFFFF800\r
+ram2ctrl .word 0xFFFFF900\r
+ram1errstat .word 0xFFFFF810\r
+ram2errstat .word 0xFFFFF910\r
+flashbase .word 0xFFF87000\r
+\r
+ .endasmfunc\r
+ \r
+ \r
--- /dev/null
+/** @file esm.c \r
+* @brief Esm Driver Source File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+* This file contains:\r
+* - API Funcions\r
+* .\r
+* which are relevant for the Esm driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+/* Include Files */\r
+\r
+#include "esm.h"\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+/** @fn void esmInit(void)\r
+* @brief Initializes Esm Driver\r
+*\r
+* This function initializes the Esm driver.\r
+*\r
+*/\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+void esmInit(void)\r
+{\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+ /** - Disable error pin channels */\r
+ esmREG->EPENACLR1 = 0xFFFFFFFFU;\r
+ esmREG->EPENACLR4 = 0xFFFFFFFFU;\r
+\r
+ /** - Disable interrupts */\r
+ esmREG->INTENACLR1 = 0xFFFFFFFFU;\r
+ esmREG->INTENACLR4 = 0xFFFFFFFFU;\r
+\r
+ /** - Clear error status flags */\r
+ esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS2EMU = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS1[2U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS5EMU = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS4[2U] = 0xFFFFFFFFU;\r
+\r
+ /** - Setup LPC preload */\r
+ esmREG->LTCPRELOAD = 16384U - 1U;\r
+\r
+ /** - Reset error pin */\r
+ if (esmREG->EPSTATUS == 0U)\r
+ {\r
+ esmREG->KEY = 0x00000005U;\r
+ }\r
+ else\r
+ {\r
+ esmREG->KEY = 0x00000000U;\r
+ }\r
+\r
+ /** - Clear interrupt level */\r
+ esmREG->INTLVLCLR1 = 0xFFFFFFFFU;\r
+ esmREG->INTLVLCLR4 = 0xFFFFFFFFU;\r
+\r
+ /** - Set interrupt level */\r
+ esmREG->INTLVLSET1 = (0U << 31U)\r
+ | (0U << 30U)\r
+ | (0U << 29U)\r
+ | (0U << 28U)\r
+ | (0U << 27U)\r
+ | (0U << 26U)\r
+ | (0U << 25U)\r
+ | (0U << 24U)\r
+ | (0U << 23U)\r
+ | (0U << 22U)\r
+ | (0U << 21U)\r
+ | (0U << 20U)\r
+ | (0U << 19U)\r
+ | (0U << 18U)\r
+ | (0U << 17U)\r
+ | (0U << 16U)\r
+ | (0U << 15U)\r
+ | (0U << 14U)\r
+ | (0U << 13U)\r
+ | (0U << 12U)\r
+ | (0U << 11U)\r
+ | (0U << 10U)\r
+ | (0U << 9U)\r
+ | (0U << 8U)\r
+ | (0U << 7U)\r
+ | (0U << 6U)\r
+ | (0U << 5U)\r
+ | (0U << 4U)\r
+ | (0U << 3U)\r
+ | (0U << 2U)\r
+ | (0U << 1U)\r
+ | (0U);\r
+\r
+ esmREG->INTLVLSET4 = (0U << 31U)\r
+ | (0U << 30U)\r
+ | (0U << 29U)\r
+ | (0U << 28U)\r
+ | (0U << 27U)\r
+ | (0U << 26U)\r
+ | (0U << 25U)\r
+ | (0U << 24U)\r
+ | (0U << 23U)\r
+ | (0U << 22U)\r
+ | (0U << 21U)\r
+ | (0U << 20U)\r
+ | (0U << 19U)\r
+ | (0U << 18U)\r
+ | (0U << 17U)\r
+ | (0U << 16U)\r
+ | (0U << 15U)\r
+ | (0U << 14U)\r
+ | (0U << 13U)\r
+ | (0U << 12U)\r
+ | (0U << 11U)\r
+ | (0U << 10U)\r
+ | (0U << 9U)\r
+ | (0U << 8U)\r
+ | (0U << 7U)\r
+ | (0U << 6U)\r
+ | (0U << 5U)\r
+ | (0U << 4U)\r
+ | (0U << 3U)\r
+ | (0U << 2U)\r
+ | (0U << 1U)\r
+ | (0U);\r
+\r
+ /** - Enable error pin channels */\r
+ esmREG->EPENASET1 = (0U << 31U)\r
+ | (0U << 30U)\r
+ | (0U << 29U)\r
+ | (0U << 28U)\r
+ | (0U << 27U)\r
+ | (0U << 26U)\r
+ | (0U << 25U)\r
+ | (0U << 24U)\r
+ | (0U << 23U)\r
+ | (0U << 22U)\r
+ | (0U << 21U)\r
+ | (0U << 20U)\r
+ | (0U << 19U)\r
+ | (0U << 18U)\r
+ | (0U << 17U)\r
+ | (0U << 16U)\r
+ | (0U << 15U)\r
+ | (0U << 14U)\r
+ | (0U << 13U)\r
+ | (0U << 12U)\r
+ | (0U << 11U)\r
+ | (0U << 10U)\r
+ | (0U << 9U)\r
+ | (0U << 8U)\r
+ | (0U << 7U)\r
+ | (0U << 6U)\r
+ | (0U << 5U)\r
+ | (0U << 4U)\r
+ | (0U << 3U)\r
+ | (0U << 2U)\r
+ | (0U << 1U)\r
+ | (0U);\r
+\r
+ esmREG->EPENASET4 = (0U << 31U)\r
+ | (0U << 30U)\r
+ | (0U << 29U)\r
+ | (0U << 28U)\r
+ | (0U << 27U)\r
+ | (0U << 26U)\r
+ | (0U << 25U)\r
+ | (0U << 24U)\r
+ | (0U << 23U)\r
+ | (0U << 22U)\r
+ | (0U << 21U)\r
+ | (0U << 20U)\r
+ | (0U << 19U)\r
+ | (0U << 18U)\r
+ | (0U << 17U)\r
+ | (0U << 16U)\r
+ | (0U << 15U)\r
+ | (0U << 14U)\r
+ | (0U << 13U)\r
+ | (0U << 12U)\r
+ | (0U << 11U)\r
+ | (0U << 10U)\r
+ | (0U << 9U)\r
+ | (0U << 8U)\r
+ | (0U << 7U)\r
+ | (0U << 6U)\r
+ | (0U << 5U)\r
+ | (0U << 4U)\r
+ | (0U << 3U)\r
+ | (0U << 2U)\r
+ | (0U << 1U)\r
+ | (0U);\r
+\r
+ /** - Enable interrpts */\r
+ esmREG->INTENASET1 = (0U << 31U)\r
+ | (0U << 30U)\r
+ | (0U << 29U)\r
+ | (0U << 28U)\r
+ | (0U << 27U)\r
+ | (0U << 26U)\r
+ | (0U << 25U)\r
+ | (0U << 24U)\r
+ | (0U << 23U)\r
+ | (0U << 22U)\r
+ | (0U << 21U)\r
+ | (0U << 20U)\r
+ | (0U << 19U)\r
+ | (0U << 18U)\r
+ | (0U << 17U)\r
+ | (0U << 16U)\r
+ | (0U << 15U)\r
+ | (0U << 14U)\r
+ | (0U << 13U)\r
+ | (0U << 12U)\r
+ | (0U << 11U)\r
+ | (0U << 10U)\r
+ | (0U << 9U)\r
+ | (0U << 8U)\r
+ | (0U << 7U)\r
+ | (0U << 6U)\r
+ | (0U << 5U)\r
+ | (0U << 4U)\r
+ | (0U << 3U)\r
+ | (0U << 2U)\r
+ | (0U << 1U)\r
+ | (0U);\r
+\r
+ esmREG->INTENASET4 = (0U << 31U)\r
+ | (0U << 30U)\r
+ | (0U << 29U)\r
+ | (0U << 28U)\r
+ | (0U << 27U)\r
+ | (0U << 26U)\r
+ | (0U << 25U)\r
+ | (0U << 24U)\r
+ | (0U << 23U)\r
+ | (0U << 22U)\r
+ | (0U << 21U)\r
+ | (0U << 20U)\r
+ | (0U << 19U)\r
+ | (0U << 18U)\r
+ | (0U << 17U)\r
+ | (0U << 16U)\r
+ | (0U << 15U)\r
+ | (0U << 14U)\r
+ | (0U << 13U)\r
+ | (0U << 12U)\r
+ | (0U << 11U)\r
+ | (0U << 10U)\r
+ | (0U << 9U)\r
+ | (0U << 8U)\r
+ | (0U << 7U)\r
+ | (0U << 6U)\r
+ | (0U << 5U)\r
+ | (0U << 4U)\r
+ | (0U << 3U)\r
+ | (0U << 2U)\r
+ | (0U << 1U)\r
+ | (0U);\r
+\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn uint32_t esmError(void)\r
+* @brief Return Error status\r
+*\r
+* @return The error status\r
+*\r
+* Returns the error status.\r
+*/\r
+uint32_t esmError(void)\r
+{\r
+ uint32_t status;\r
+\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+\r
+ status = esmREG->EPSTATUS;\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/** @fn void esmEnableError(uint64_t channels)\r
+* @brief Enable Group 1 Channels Error Signals propagation\r
+*\r
+* @param[in] channels - Channel mask\r
+*\r
+* Enable Group 1 Channels Error Signals propagation to the error pin.\r
+*/\r
+void esmEnableError(uint64_t channels)\r
+{\r
+/* USER CODE BEGIN (7) */\r
+/* USER CODE END */\r
+\r
+ esmREG->EPENASET4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
+ esmREG->EPENASET1 = (uint32_t)(channels & 0xFFFFFFFF);\r
+\r
+/* USER CODE BEGIN (8) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmDisableError(uint64_t channels)\r
+* @brief Disable Group 1 Channels Error Signals propagation\r
+*\r
+* @param[in] channels - Channel mask\r
+*\r
+* Disable Group 1 Channels Error Signals propagation to the error pin.\r
+*/\r
+void esmDisableError(uint64_t channels)\r
+{\r
+/* USER CODE BEGIN (9) */\r
+/* USER CODE END */\r
+\r
+ esmREG->EPENACLR4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
+ esmREG->EPENACLR1 = (uint32_t)(channels & 0xFFFFFFFF);\r
+\r
+/* USER CODE BEGIN (10) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmTriggerErrorPinReset(void)\r
+* @brief Trigger error pin reset and switch back to normal operation\r
+*\r
+* Trigger error pin reset and switch back to normal operation.\r
+*/\r
+void esmTriggerErrorPinReset(void)\r
+{\r
+/* USER CODE BEGIN (11) */\r
+/* USER CODE END */\r
+\r
+ esmREG->KEY = 5U;\r
+\r
+/* USER CODE BEGIN (12) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmActivateNormalOperation(void)\r
+* @brief Activate normal operation\r
+*\r
+* Activates normal operation mode.\r
+*/\r
+void esmActivateNormalOperation(void)\r
+{\r
+/* USER CODE BEGIN (13) */\r
+/* USER CODE END */\r
+\r
+ esmREG->KEY = 0U;\r
+\r
+/* USER CODE BEGIN (14) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmEnableInterrupt(uint64_t channels)\r
+* @brief Enable Group 1 Channels Interrupts\r
+*\r
+* @param[in] channels - Channel mask\r
+*\r
+* Enable Group 1 Channels Interrupts.\r
+*/\r
+void esmEnableInterrupt(uint64_t channels)\r
+{\r
+/* USER CODE BEGIN (15) */\r
+/* USER CODE END */\r
+\r
+ esmREG->INTENASET4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
+ esmREG->INTENASET1 = (uint32_t)(channels & 0xFFFFFFFF);\r
+\r
+/* USER CODE BEGIN (16) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmDisableInterrupt(uint64_t channels)\r
+* @brief Disable Group 1 Channels Interrupts\r
+*\r
+* @param[in] channels - Channel mask\r
+*\r
+* Disable Group 1 Channels Interrupts.\r
+*/\r
+void esmDisableInterrupt(uint64_t channels)\r
+{\r
+/* USER CODE BEGIN (17) */\r
+/* USER CODE END */\r
+\r
+ esmREG->INTENACLR4 = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
+ esmREG->INTENACLR1 = (uint32_t)(channels & 0xFFFFFFFF);\r
+\r
+/* USER CODE BEGIN (18) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmSetInterruptLevel(uint64_t channels, uint64_t flags)\r
+* @brief Set Group 1 Channels Interrupt Levels\r
+*\r
+* @param[in] channels - Channel mask\r
+* @param[in] flags - Level mask: - 0: Low priority interrupt\r
+* - 1: High priority interrupt\r
+*\r
+* Set Group 1 Channels Interrupts levels.\r
+*/\r
+void esmSetInterruptLevel(uint64_t channels, uint64_t flags)\r
+{\r
+/* USER CODE BEGIN (19) */\r
+/* USER CODE END */\r
+\r
+ esmREG->INTLVLCLR4 = (uint32_t)(((channels & ~flags) >> 32) & 0xFFFFFFF);\r
+ esmREG->INTLVLSET4 = (uint32_t)(((channels & flags) >> 32) & 0xFFFFFFFF);\r
+ esmREG->INTLVLCLR1 = (uint32_t)(channels & ~flags & 0xFFFFFFF);\r
+ esmREG->INTLVLSET1 = (uint32_t)(channels & flags & 0xFFFFFFFF);\r
+\r
+/* USER CODE BEGIN (20) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmClearStatus(uint32_t group, uint64_t channels)\r
+* @brief Clear Group error status\r
+*\r
+* @param[in] group - Error group\r
+* @param[in] channels - Channel mask\r
+*\r
+* Clear Group error status.\r
+*/\r
+void esmClearStatus(uint32_t group, uint64_t channels)\r
+{\r
+/* USER CODE BEGIN (21) */\r
+/* USER CODE END */\r
+\r
+ esmREG->ESTATUS4[group] = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
+ esmREG->ESTATUS1[group] = (uint32_t)(channels & 0xFFFFFFFF);\r
+\r
+/* USER CODE BEGIN (22) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmClearStatusBuffer(uint64_t channels)\r
+* @brief Clear Group 2 error status buffer\r
+*\r
+* @param[in] channels - Channel mask\r
+*\r
+* Clear Group 2 error status buffer.\r
+*/\r
+void esmClearStatusBuffer(uint64_t channels)\r
+{\r
+/* USER CODE BEGIN (23) */\r
+/* USER CODE END */\r
+\r
+ esmREG->ESTATUS5EMU = (uint32_t)((channels >> 32) & 0xFFFFFFFF);\r
+ esmREG->ESTATUS2EMU = (uint32_t)(channels & 0xFFFFFFFF);\r
+\r
+/* USER CODE BEGIN (24) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmSetCounterPreloadValue(uint32_t value)\r
+* @brief Set couter preload value\r
+*\r
+* @param[in] value - Counter preload value\r
+*\r
+* Set counter preload value.\r
+*/\r
+void esmSetCounterPreloadValue(uint32_t value)\r
+{\r
+/* USER CODE BEGIN (25) */\r
+/* USER CODE END */\r
+\r
+ esmREG->LTCPRELOAD = value & 0xC000U;\r
+\r
+/* USER CODE BEGIN (26) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn uint64_t esmGetStatus(uint32_t group, uint64_t channels)\r
+* @brief Return Error status\r
+*\r
+* @param[in] group - Error group\r
+* @param[in] channels - Error Channels\r
+*\r
+* @return The channels status of selected group\r
+*\r
+* Returns the channels status of selected group.\r
+*/\r
+uint64_t esmGetStatus(uint32_t group, uint64_t channels)\r
+{\r
+ uint64_t status;\r
+\r
+/* USER CODE BEGIN (27) */\r
+/* USER CODE END */\r
+\r
+ status = (((uint64_t)esmREG->ESTATUS4[group] << 32) | (uint64_t)esmREG->ESTATUS1[group]) & channels;\r
+\r
+/* USER CODE BEGIN (28) */\r
+/* USER CODE END */\r
+\r
+ return status;\r
+}\r
+\r
+\r
+/** @fn uint64_t esmGetStatusBuffer(uint64_t channels)\r
+* @brief Return Group 2 channel x Error status buffer\r
+*\r
+* @param[in] channels - Error Channels\r
+*\r
+* @return The channels status\r
+*\r
+* Returns the group 2 bufferd status of selected channels.\r
+*/\r
+uint64_t esmGetStatusBuffer(uint64_t channels)\r
+{\r
+ uint64_t status;\r
+\r
+/* USER CODE BEGIN (29) */\r
+/* USER CODE END */\r
+\r
+ status = (((uint64_t)esmREG->ESTATUS5EMU << 32) | (uint64_t)esmREG->ESTATUS2EMU) & channels;\r
+\r
+/* USER CODE BEGIN (30) */\r
+/* USER CODE END */\r
+\r
+ return status;\r
+}\r
+\r
+/** @fn void esmHighInterrupt(void)\r
+* @brief High Level Interrupt for ESM\r
+*/\r
+#pragma INTERRUPT(esmHighInterrupt, FIQ)\r
+\r
+\r
+void esmHighInterrupt(void)\r
+{\r
+ int vec = esmREG->INTOFFH - 1;\r
+\r
+/* USER CODE BEGIN (31) */\r
+/* USER CODE END */\r
+\r
+ if (vec >= 96)\r
+ {\r
+ esmREG->ESTATUS4[1U] = 1U << (vec-96);\r
+ esmGroup2Notification(vec-64);\r
+ }\r
+ else if (vec >= 64)\r
+ {\r
+ esmREG->ESTATUS4[0U] = 1U << (vec-64);\r
+ esmGroup1Notification(vec-32);\r
+ }\r
+ else if (vec >= 32)\r
+ {\r
+ esmREG->ESTATUS1[1U] = 1U << (vec-32);\r
+ esmGroup2Notification(vec-32);\r
+ }\r
+ else if (vec >= 0)\r
+ {\r
+ esmREG->ESTATUS1[0U] = 1 << vec;\r
+ esmGroup1Notification(vec);\r
+ }\r
+ else\r
+ {\r
+ esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;\r
+ }\r
+\r
+/* USER CODE BEGIN (32) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void esmLowInterrupt(void)\r
+* @brief Low Level Interrupt for ESM\r
+*/\r
+#pragma INTERRUPT(esmLowInterrupt, IRQ)\r
+\r
+void esmLowInterrupt(void)\r
+{\r
+\r
+ /* Note : Group 1 Error */\r
+ /* 1 to 32 -> channel 0 to 31 */\r
+ /* 65 to 96 -> channel 32 to 63 */\r
+\r
+ int vec = esmREG->INTOFFL - 1;\r
+\r
+/* USER CODE BEGIN (33) */\r
+/* USER CODE END */\r
+\r
+\r
+ if (vec >= 64) /* channel 32 to 63 */\r
+ {\r
+ esmREG->ESTATUS4[0U] = 1U << (vec-64);\r
+ esmGroup1Notification(vec-32);\r
+ }\r
+ else if (vec >= 0) /* channel 0 to 31 */\r
+ {\r
+ esmREG->ESTATUS1[0U] = 1U << vec;\r
+ esmGroup1Notification(vec);\r
+ }\r
+ else\r
+ {\r
+ esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;\r
+ esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;\r
+ }\r
+\r
+/* USER CODE BEGIN (34) */\r
+/* USER CODE END */\r
+}\r
+\r
+/* USER CODE BEGIN (35) */\r
+/* USER CODE END */\r
--- /dev/null
+/*******************************************************************
+ Components for embedded applications builded for
+ laboratory and medical instruments firmware
+
+ cmd_i2str.c - formated text to string conversion
+ without need to pull in whole stdio support
+
+ Copyright (C) 2001-2010 by Pavel Pisa pisa@cmp.felk.cvut.cz
+ (C) 2002-2010 by PiKRON Ltd. http://www.pikron.com
+ (C) 2007 by Michal Sojka <sojkam1@fel.cvut.cz>
+
+ This file can be used and copied according to next
+ license alternatives
+ - MPL - Mozilla Public License
+ - GPL - GNU Public License
+ - other license provided by project originators
+ *******************************************************************/
+
+#include "i2str.h"
+
+/**
+ * Converts integer to string.
+ * @param s Buffer to store the result.
+ * @param val Value to convert.
+ * @param len Minimal width of the converted strign (padded by ' ').
+ * @param form Unused.
+ * @return 0
+ */
+int i2str(char *s,long val,int len,int form)
+{
+ int sig;
+ int dig=1;
+ int padd=0;
+ unsigned base=form&0xff;
+ unsigned long u;
+ unsigned long mag;
+ unsigned long num;
+ if(!base) base=10;
+ if((sig=(val<0)&&(base==10))) num=-val;
+ else num=val;
+
+ mag=1;
+ u=base*mag;
+ while(num>=u){
+ dig++;
+ mag=u;
+ if(mag>(unsigned long)(~(unsigned long)0)/base) break;
+ u*=base;
+ }
+
+ if(len){
+ padd=len-dig;
+ if(sig) padd--;
+ }
+ if(padd<0) padd=0;
+
+
+ if(form&I2STR_PAD_0) {
+ if(sig) *(s++)='-';
+ while(padd){
+ *(s++)='0';
+ padd--;
+ }
+ }else{
+ while(padd){
+ *(s++)=' ';
+ padd--;
+ }
+ if(sig) *(s++)='-';
+ }
+
+ while(dig--){
+ u=num/mag;
+ if(u>9) *(s++)='A'-10+u;
+ else *(s++)='0'+u;
+ num=num%mag;
+ mag/=base;
+ }
+ *s=0;
+ return 0;
+}
+
--- /dev/null
+/** @file notification.c \r
+* @brief User Notification Definition File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+* This file defines empty notification routines.\r
+* The user needs to remove the while loop and define \r
+* the sequence.\r
+*\r
+*/\r
+\r
+/* Include Files */\r
+\r
+#include "esm.h"\r
+#include "sys_selftest.h"\r
+#include "sci.h"\r
+/* USER CODE BEGIN (0) */\r
+#include "FreeRTOS.h"\r
+#include "os_semphr.h"\r
+#include "os_task.h"\r
+\r
+extern xQueueHandle inputCharacterQueue;\r
+extern uint8_t character;\r
+/* USER CODE END */\r
+\r
+void esmGroup1Notification(uint32_t channel)\r
+{\r
+/* enter user code and remove the while loop... */\r
+ while(1);\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+void esmGroup2Notification(uint32_t channel)\r
+{\r
+/* enter user code and remove the while loop... */\r
+ while(1);\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+\r
+void memoryPort0TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data)\r
+{\r
+/* enter user code and remove the while loop... */\r
+ while(1);\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+void memoryPort1TestFailNotification(uint32_t groupSelect, uint32_t dataSelect, uint32_t address, uint32_t data)\r
+{\r
+/* enter user code and remove the while loop... */\r
+ while(1);\r
+/* USER CODE BEGIN (7) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+/* USER CODE BEGIN (8) */\r
+/* USER CODE END */\r
+\r
+void sciNotification(sciBASE_t *sci, uint32_t flags) \r
+{\r
+/* USER CODE BEGIN (29) */\r
+ sciReceive(sci, 1, NULL);\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+/* USER CODE BEGIN (30) */\r
+/* USER CODE END */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include "FreeRTOS.h"\r
+#include "os_task.h"\r
+#include "os_croutine.h"\r
+\r
+/*\r
+ * Some kernel aware debuggers require data to be viewed to be global, rather\r
+ * than file scope.\r
+ */\r
+#ifdef portREMOVE_STATIC_QUALIFIER\r
+ #define static\r
+#endif\r
+\r
+\r
+/* Lists for ready and blocked co-routines. --------------------*/\r
+static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */\r
+static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */\r
+static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */\r
+static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */\r
+static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */\r
+static xList xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */\r
+\r
+/* Other file private variables. --------------------------------*/\r
+corCRCB * pxCurrentCoRoutine = NULL;\r
+static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0;\r
+static portTickType xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;\r
+\r
+/* The initial state of the co-routine when it is created. */\r
+#define corINITIAL_STATE ( 0 )\r
+\r
+/*\r
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue\r
+ * for the priority. It is inserted at the end of the list.\r
+ *\r
+ * This macro accesses the co-routine ready lists and therefore must not be\r
+ * used from within an ISR.\r
+ */\r
+#define prvAddCoRoutineToReadyQueue( pxCRCB ) \\r
+{ \\r
+ if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \\r
+ { \\r
+ uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \\r
+ } \\r
+ vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \\r
+} \r
+\r
+/*\r
+ * Utility to ready all the lists used by the scheduler. This is called\r
+ * automatically upon the creation of the first co-routine.\r
+ */\r
+static void prvInitialiseCoRoutineLists( void );\r
+\r
+/*\r
+ * Co-routines that are readied by an interrupt cannot be placed directly into\r
+ * the ready lists (there is no mutual exclusion). Instead they are placed in\r
+ * in the pending ready list in order that they can later be moved to the ready\r
+ * list by the co-routine scheduler.\r
+ */\r
+static void prvCheckPendingReadyList( void );\r
+\r
+/*\r
+ * Macro that looks at the list of co-routines that are currently delayed to\r
+ * see if any require waking.\r
+ *\r
+ * Co-routines are stored in the queue in the order of their wake time -\r
+ * meaning once one co-routine has been found whose timer has not expired\r
+ * we need not look any further down the list.\r
+ */\r
+static void prvCheckDelayedList( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+corCRCB *pxCoRoutine;\r
+\r
+ /* Allocate the memory that will store the co-routine control block. */\r
+ pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) );\r
+ if( pxCoRoutine )\r
+ {\r
+ /* If pxCurrentCoRoutine is NULL then this is the first co-routine to\r
+ be created and the co-routine data structures need initialising. */\r
+ if( pxCurrentCoRoutine == NULL )\r
+ {\r
+ pxCurrentCoRoutine = pxCoRoutine;\r
+ prvInitialiseCoRoutineLists();\r
+ }\r
+\r
+ /* Check the priority is within limits. */\r
+ if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )\r
+ {\r
+ uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;\r
+ }\r
+\r
+ /* Fill out the co-routine control block from the function parameters. */\r
+ pxCoRoutine->uxState = corINITIAL_STATE;\r
+ pxCoRoutine->uxPriority = uxPriority;\r
+ pxCoRoutine->uxIndex = uxIndex;\r
+ pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;\r
+\r
+ /* Initialise all the other co-routine control block parameters. */\r
+ vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );\r
+ vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );\r
+\r
+ /* Set the co-routine control block as a link back from the xListItem.\r
+ This is so we can get back to the containing CRCB from a generic item\r
+ in a list. */\r
+ listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );\r
+ listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );\r
+ \r
+ /* Event lists are always in priority order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority );\r
+ \r
+ /* Now the co-routine has been initialised it can be added to the ready\r
+ list at the correct priority. */\r
+ prvAddCoRoutineToReadyQueue( pxCoRoutine );\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ { \r
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r
+ }\r
+ \r
+ return xReturn; \r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList )\r
+{\r
+portTickType xTimeToWake;\r
+\r
+ /* Calculate the time to wake - this may overflow but this is\r
+ not a problem. */\r
+ xTimeToWake = xCoRoutineTickCount + xTicksToDelay;\r
+\r
+ /* We must remove ourselves from the ready list before adding\r
+ ourselves to the blocked list as the same list item is used for\r
+ both lists. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r
+\r
+ /* The list item will be inserted in wake time order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );\r
+\r
+ if( xTimeToWake < xCoRoutineTickCount )\r
+ {\r
+ /* Wake time has overflowed. Place this item in the\r
+ overflow list. */\r
+ vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* The wake time has not overflowed, so we can use the\r
+ current block list. */\r
+ vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) );\r
+ }\r
+\r
+ if( pxEventList )\r
+ {\r
+ /* Also add the co-routine to an event list. If this is done then the\r
+ function must be called with interrupts disabled. */\r
+ vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckPendingReadyList( void )\r
+{\r
+ /* Are there any co-routines waiting to get moved to the ready list? These\r
+ are co-routines that have been readied by an ISR. The ISR cannot access\r
+ the ready lists itself. */\r
+ while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )\r
+ {\r
+ corCRCB *pxUnblockedCRCB;\r
+\r
+ /* The pending ready list can be accessed by an ISR. */\r
+ portDISABLE_INTERRUPTS();\r
+ { \r
+ pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); \r
+ vListRemove( &( pxUnblockedCRCB->xEventListItem ) );\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ vListRemove( &( pxUnblockedCRCB->xGenericListItem ) );\r
+ prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckDelayedList( void )\r
+{\r
+corCRCB *pxCRCB;\r
+\r
+ xPassedTicks = xTaskGetTickCount() - xLastTickCount;\r
+ while( xPassedTicks )\r
+ {\r
+ xCoRoutineTickCount++;\r
+ xPassedTicks--;\r
+\r
+ /* If the tick count has overflowed we need to swap the ready lists. */\r
+ if( xCoRoutineTickCount == 0 )\r
+ {\r
+ xList * pxTemp;\r
+\r
+ /* Tick count has overflowed so we need to swap the delay lists. If there are\r
+ any items in pxDelayedCoRoutineList here then there is an error! */\r
+ pxTemp = pxDelayedCoRoutineList;\r
+ pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;\r
+ pxOverflowDelayedCoRoutineList = pxTemp;\r
+ }\r
+\r
+ /* See if this tick has made a timeout expire. */\r
+ while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )\r
+ {\r
+ pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );\r
+\r
+ if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) \r
+ { \r
+ /* Timeout not yet expired. */ \r
+ break; \r
+ } \r
+\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ /* The event could have occurred just before this critical\r
+ section. If this is the case then the generic list item will\r
+ have been moved to the pending ready list and the following\r
+ line is still valid. Also the pvContainer parameter will have\r
+ been set to NULL so the following lines are also valid. */\r
+ vListRemove( &( pxCRCB->xGenericListItem ) ); \r
+\r
+ /* Is the co-routine waiting on an event also? */ \r
+ if( pxCRCB->xEventListItem.pvContainer ) \r
+ { \r
+ vListRemove( &( pxCRCB->xEventListItem ) ); \r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ prvAddCoRoutineToReadyQueue( pxCRCB ); \r
+ } \r
+ }\r
+\r
+ xLastTickCount = xCoRoutineTickCount;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vCoRoutineSchedule( void )\r
+{\r
+ /* See if any co-routines readied by events need moving to the ready lists. */\r
+ prvCheckPendingReadyList();\r
+\r
+ /* See if any delayed co-routines have timed out. */\r
+ prvCheckDelayedList();\r
+\r
+ /* Find the highest priority queue that contains ready co-routines. */\r
+ while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )\r
+ {\r
+ if( uxTopCoRoutineReadyPriority == 0 )\r
+ {\r
+ /* No more co-routines to check. */\r
+ return;\r
+ }\r
+ --uxTopCoRoutineReadyPriority;\r
+ }\r
+\r
+ /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines\r
+ of the same priority get an equal share of the processor time. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );\r
+\r
+ /* Call the co-routine. */\r
+ ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );\r
+\r
+ return;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvInitialiseCoRoutineLists( void )\r
+{\r
+unsigned portBASE_TYPE uxPriority;\r
+\r
+ for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )\r
+ {\r
+ vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );\r
+ }\r
+\r
+ vListInitialise( ( xList * ) &xDelayedCoRoutineList1 );\r
+ vListInitialise( ( xList * ) &xDelayedCoRoutineList2 );\r
+ vListInitialise( ( xList * ) &xPendingReadyCoRoutineList );\r
+\r
+ /* Start with pxDelayedCoRoutineList using list1 and the\r
+ pxOverflowDelayedCoRoutineList using list2. */\r
+ pxDelayedCoRoutineList = &xDelayedCoRoutineList1;\r
+ pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList )\r
+{\r
+corCRCB *pxUnblockedCRCB;\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* This function is called from within an interrupt. It can only access\r
+ event lists and the pending ready list. This function assumes that a\r
+ check has already been made to ensure pxEventList is not empty. */\r
+ pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r
+ vListRemove( &( pxUnblockedCRCB->xEventListItem ) );\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );\r
+\r
+ if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+/*\r
+ * The simplest possible implementation of pvPortMalloc(). Note that this\r
+ * implementation does NOT allow allocated memory to be freed again.\r
+ *\r
+ * See heap_2.c and heap_3.c for alternative implementations, and the memory\r
+ * management pages of http://www.FreeRTOS.org for more information.\r
+ */\r
+#include <stdlib.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers. That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#include "FreeRTOS.h"\r
+#include "os_task.h"\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* Allocate the memory for the heap. The struct is used to force byte\r
+alignment without using any non-portable code. */\r
+static union xRTOS_HEAP\r
+{\r
+ #if portBYTE_ALIGNMENT == 8\r
+ volatile portDOUBLE dDummy;\r
+ #else\r
+ volatile unsigned long ulDummy;\r
+ #endif \r
+ unsigned char ucHeap[ configTOTAL_HEAP_SIZE ];\r
+} xHeap;\r
+\r
+static size_t xNextFreeByte = ( size_t ) 0;\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvPortMalloc( size_t xWantedSize )\r
+{\r
+void *pvReturn = NULL; \r
+\r
+ /* Ensure that blocks are always aligned to the required number of bytes. */\r
+ #if portBYTE_ALIGNMENT != 1\r
+ if( xWantedSize & portBYTE_ALIGNMENT_MASK )\r
+ {\r
+ /* Byte alignment required. */\r
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\r
+ }\r
+ #endif\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Check there is enough room left for the allocation. */\r
+ if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) &&\r
+ ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */\r
+ {\r
+ /* Return the next free byte then increment the index past this\r
+ block. */\r
+ pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] );\r
+ xNextFreeByte += xWantedSize; \r
+ } \r
+ }\r
+ xTaskResumeAll();\r
+ \r
+ #if( configUSE_MALLOC_FAILED_HOOK == 1 )\r
+ {\r
+ if( pvReturn == NULL )\r
+ {\r
+ extern void vApplicationMallocFailedHook( void );\r
+ vApplicationMallocFailedHook();\r
+ }\r
+ }\r
+ #endif \r
+\r
+ return pvReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortFree( void *pv )\r
+{\r
+ /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c \r
+ for alternative implementations, and the memory management pages of \r
+ http://www.FreeRTOS.org for more information. */\r
+ ( void ) pv;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vPortInitialiseBlocks( void )\r
+{\r
+ /* Only required when static memory is not cleared. */\r
+ xNextFreeByte = ( size_t ) 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+size_t xPortGetFreeHeapSize( void )\r
+{\r
+ return ( configTOTAL_HEAP_SIZE - xNextFreeByte );\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#include <stdlib.h>\r
+#include "FreeRTOS.h"\r
+#include "os_list.h"\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC LIST API documented in list.h\r
+ *----------------------------------------------------------*/\r
+\r
+void vListInitialise( xList *pxList )\r
+{\r
+ /* The list structure contains a list item which is used to mark the\r
+ end of the list. To initialise the list the list end is inserted\r
+ as the only list entry. */\r
+ pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd );\r
+\r
+ /* The list end value is the highest possible value in the list to\r
+ ensure it remains at the end of the list. */\r
+ pxList->xListEnd.xItemValue = portMAX_DELAY;\r
+\r
+ /* The list end next and previous pointers point to itself so we know\r
+ when the list is empty. */\r
+ pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd );\r
+ pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd );\r
+\r
+ pxList->uxNumberOfItems = ( unsigned portBASE_TYPE ) 0U;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInitialiseItem( xListItem *pxItem )\r
+{\r
+ /* Make sure the list item is not recorded as being on a list. */\r
+ pxItem->pvContainer = NULL;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInsertEnd( xList *pxList, xListItem *pxNewListItem )\r
+{\r
+volatile xListItem * pxIndex;\r
+\r
+ /* Insert a new list item into pxList, but rather than sort the list,\r
+ makes the new list item the last item to be removed by a call to\r
+ pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by\r
+ the pxIndex member. */\r
+ pxIndex = pxList->pxIndex;\r
+\r
+ pxNewListItem->pxNext = pxIndex->pxNext;\r
+ pxNewListItem->pxPrevious = pxList->pxIndex;\r
+ pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;\r
+ pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem;\r
+ pxList->pxIndex = ( volatile xListItem * ) pxNewListItem;\r
+\r
+ /* Remember which list the item is in. */\r
+ pxNewListItem->pvContainer = ( void * ) pxList;\r
+\r
+ ( pxList->uxNumberOfItems )++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListInsert( xList *pxList, xListItem *pxNewListItem )\r
+{\r
+volatile xListItem *pxIterator;\r
+portTickType xValueOfInsertion;\r
+\r
+ /* Insert the new list item into the list, sorted in ulListItem order. */\r
+ xValueOfInsertion = pxNewListItem->xItemValue;\r
+\r
+ /* If the list already contains a list item with the same item value then\r
+ the new list item should be placed after it. This ensures that TCB's which\r
+ are stored in ready lists (all of which have the same ulListItem value)\r
+ get an equal share of the CPU. However, if the xItemValue is the same as\r
+ the back marker the iteration loop below will not end. This means we need\r
+ to guard against this by checking the value first and modifying the\r
+ algorithm slightly if necessary. */\r
+ if( xValueOfInsertion == portMAX_DELAY )\r
+ {\r
+ pxIterator = pxList->xListEnd.pxPrevious;\r
+ }\r
+ else\r
+ {\r
+ /* *** NOTE ***********************************************************\r
+ If you find your application is crashing here then likely causes are:\r
+ 1) Stack overflow -\r
+ see http://www.freertos.org/Stacks-and-stack-overflow-checking.html\r
+ 2) Incorrect interrupt priority assignment, especially on Cortex-M3\r
+ parts where numerically high priority values denote low actual\r
+ interrupt priories, which can seem counter intuitive. See\r
+ configMAX_SYSCALL_INTERRUPT_PRIORITY on http://www.freertos.org/a00110.html\r
+ 3) Calling an API function from within a critical section or when\r
+ the scheduler is suspended.\r
+ 4) Using a queue or semaphore before it has been initialised or\r
+ before the scheduler has been started (are interrupts firing\r
+ before vTaskStartScheduler() has been called?).\r
+ See http://www.freertos.org/FAQHelp.html for more tips.\r
+ **********************************************************************/\r
+ \r
+ for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )\r
+ {\r
+ /* There is nothing to do here, we are just iterating to the\r
+ wanted insertion position. */\r
+ }\r
+ }\r
+\r
+ pxNewListItem->pxNext = pxIterator->pxNext;\r
+ pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem;\r
+ pxNewListItem->pxPrevious = pxIterator;\r
+ pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem;\r
+\r
+ /* Remember which list the item is in. This allows fast removal of the\r
+ item later. */\r
+ pxNewListItem->pvContainer = ( void * ) pxList;\r
+\r
+ ( pxList->uxNumberOfItems )++;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vListRemove( xListItem *pxItemToRemove )\r
+{\r
+xList * pxList;\r
+\r
+ pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\r
+ pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\r
+ \r
+ /* The list item knows which list it is in. Obtain the list from the list\r
+ item. */\r
+ pxList = ( xList * ) pxItemToRemove->pvContainer;\r
+\r
+ /* Make sure the index is left pointing to a valid item. */\r
+ if( pxList->pxIndex == pxItemToRemove )\r
+ {\r
+ pxList->pxIndex = pxItemToRemove->pxPrevious;\r
+ }\r
+\r
+ pxItemToRemove->pvContainer = NULL;\r
+ ( pxList->uxNumberOfItems )--;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:\r
+ Atollic AB - Atollic provides professional embedded systems development \r
+ tools for C/C++ development, code analysis and test automation. \r
+ See http://www.atollic.com\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Include Files */\r
+\r
+#include "FreeRTOS.h"\r
+#include "os_task.h"\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Global Vaiables */\r
+\r
+unsigned portLONG ulCriticalNesting = 9999;\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Macros */\r
+\r
+#define portINITIAL_SPSR ((portSTACK_TYPE) 0x1F)\r
+#define portINITIAL_FPSCR ((portSTACK_TYPE) 0x00)\r
+#define portINSTRUCTION_SIZE ((portSTACK_TYPE) 0x04)\r
+#define portNO_CRITICAL_SECTION_NESTING ((portSTACK_TYPE) 0x00)\r
+#define portTHUMB_MODE_BIT ((portSTACK_TYPE) 0x20)\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* pxPortInitialiseStack */\r
+\r
+portSTACK_TYPE * pxPortInitialiseStack(portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters)\r
+{\r
+ portSTACK_TYPE *pxOriginalTOS = pxTopOfStack;\r
+ \r
+ *pxTopOfStack-- = (portSTACK_TYPE) pxCode + portINSTRUCTION_SIZE; \r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0xaaaaaaaa;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) pxOriginalTOS;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x12121212;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x11111111;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x10101010;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x09090909;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x08080808;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x07070707;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x06060606;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x05050505;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x04040404;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x03030303;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x02020202;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x01010101;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) pvParameters;\r
+\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x3F3F3F3F;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x3E3E3E3E;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x3D3D3D3D;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x3C3C3C3C;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x3B3B3B3B;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x3A3A3A3A;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x39393939;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x38383838;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x37373737;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x36363636;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x35353535;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x34343434;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x33333333;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x32323232;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x31313131;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x30303030;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x2F2F2F2F;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x2E2E2E2E;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x2D2D2D2D;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x2C2C2C2C;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x2B2B2B2B;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x2A2A2A2A;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x29292929;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x28282828;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x27272727;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x26262626;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x25252525;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x24242424;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x23232323;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x22222222;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x21212121;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) 0x20202020;\r
+ *pxTopOfStack-- = (portSTACK_TYPE) portINITIAL_FPSCR;\r
+\r
+ *pxTopOfStack = (portSTACK_TYPE) ((_getCPSRValue_() & ~0xFF) | portINITIAL_SPSR);\r
+\r
+ if (((unsigned long) pxCode & 0x01UL) != 0x00)\r
+ {\r
+ *pxTopOfStack |= portTHUMB_MODE_BIT;\r
+ }\r
+\r
+ pxTopOfStack--;\r
+\r
+ *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;\r
+\r
+ return pxTopOfStack;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* prvSetupTimerInterrupt */\r
+\r
+static void prvSetupTimerInterrupt(void)\r
+{\r
+#if (configGENERATE_RUN_TIME_STATS == 1)\r
+ RTI->GCTRL &= ~0x00000001U;\r
+#else\r
+ RTI->GCTRL = 0x00000000U;\r
+#endif\r
+ RTI->TBCTRL = 0x00000000U;\r
+ RTI->COMPCTRL = 0x00000000U;\r
+ RTI->CNT[0U].UCx = 0x00000000U;\r
+ RTI->CNT[0U].FRCx = 0x00000000U;\r
+ RTI->CNT[0U].CPUCx = 0x00000001U;\r
+ RTI->CMP[0U].COMPx = configCPU_CLOCK_HZ / 2 / configTICK_RATE_HZ;\r
+ RTI->CMP[0U].UDCPx = configCPU_CLOCK_HZ / 2 / configTICK_RATE_HZ;\r
+ RTI->INTFLAG = 0x0007000FU;\r
+ RTI->CLEARINT = 0x00070F0FU;\r
+ RTI->SETINT = 0x00000001U;\r
+ RTI->GCTRL |= 0x00000001U;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* vPortStartFirstTask */\r
+\r
+/* vPortStartFirstSTask() is defined in portASM.asm */\r
+extern void vPortStartFirstTask(void);\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* xPortStartScheduler */\r
+\r
+portBASE_TYPE xPortStartScheduler(void)\r
+{\r
+ /* Start the timer that generates the tick ISR. */\r
+ prvSetupTimerInterrupt();\r
+ /* Start the first task. This is done from portASM.asm as ARM mode must be\r
+ used. */\r
+ vPortStartFirstTask(); \r
+ /* Should not get here! */\r
+ return 0;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* vPortEndScheduler */\r
+\r
+void vPortEndScheduler(void)\r
+{\r
+ /* It is unlikely that the ARM port will require this function as there\r
+ is nothing to return to. If this is required - stop the tick ISR then\r
+ return back to main. */\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* vNonPreemptiveTick / vPreemptiveTick */\r
+\r
+#if configUSE_PREEMPTION == 0\r
+\r
+ /* The cooperative scheduler requires a normal IRQ service routine to \r
+ * simply increment the system tick. */\r
+ __interrupt void vNonPreemptiveTick( void ) \r
+ {\r
+ /* clear clock interrupt flag */\r
+ RTI->INTFLAG = 0x00000001;\r
+\r
+ /* Increment the tick count - this may make a delaying task ready\r
+ to run - but a context switch is not performed. */ \r
+ vTaskIncrementTick();\r
+ }\r
+\r
+ #else\r
+\r
+ /*\r
+ **************************************************************************\r
+ * The preemptive scheduler ISR is written in assembler and can be found \r
+ * in the portASM.asm file. This will only get used if portUSE_PREEMPTION\r
+ * is set to 1 in portmacro.h\r
+ ************************************************************************** \r
+ */\r
+ void vPreemptiveTick(void);\r
+\r
+#endif\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* vPortEnterCritical */\r
+\r
+void vPortEnterCritical(void)\r
+{\r
+ /* Disable interrupts as per portDISABLE_INTERRUPTS(); */\r
+ portDISABLE_INTERRUPTS();\r
+ /* Now interrupts are disabled ulCriticalNesting can be accessed \r
+ directly. Increment ulCriticalNesting to keep a count of how many times\r
+ portENTER_CRITICAL() has been called. */\r
+ ulCriticalNesting++;\r
+}\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* vPortExitCritical */\r
+\r
+void vPortExitCritical(void)\r
+{\r
+ if(ulCriticalNesting > 0)\r
+ {\r
+ /* Decrement the nesting count as we are leaving a critical section. */\r
+ ulCriticalNesting--;\r
+\r
+ /* If the nesting level has reached zero then interrupts should be \r
+ re-enabled. */\r
+ if(ulCriticalNesting == 0)\r
+ {\r
+ /* Enable interrupts as per portENABLE_INTERRUPTS(). */\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------*/\r
--- /dev/null
+;/*\r
+; FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+; \r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS tutorial books are available in pdf and paperback. *\r
+; * Complete, revised, and edited pdf reference manuals are also *\r
+; * available. *\r
+; * *\r
+; * Purchasing FreeRTOS documentation will not only help you, by *\r
+; * ensuring you get running as quickly as possible and with an *\r
+; * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+; * the FreeRTOS project to continue with its mission of providing *\r
+; * professional grade, cross platform, de facto standard solutions *\r
+; * for microcontrollers - completely free of charge! *\r
+; * *\r
+; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+; * *\r
+; * Thank you for using FreeRTOS, and thank you for your support! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+; >>>NOTE<<< The modification to the GPL is included to allow you to\r
+; distribute a combined work that includes FreeRTOS without being obliged to\r
+; provide the source code for proprietary components outside of the FreeRTOS\r
+; kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+; more details. You should have received a copy of the GNU General Public\r
+; License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+; can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+; by writing to Richard Barry, contact details for whom are available on the\r
+; FreeRTOS WEB site.\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; http://www.FreeRTOS.org - Documentation, latest information, license and\r
+; contact details.\r
+;\r
+; http://www.SafeRTOS.com - A version that is certified for use in safety\r
+; critical systems.\r
+;\r
+; http://www.OpenRTOS.com - Commercial support, development, porting,\r
+; licensing and training services.\r
+;*/\r
+\r
+ .text\r
+ .arm\r
+\r
+ .copy os_portasm.inc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Start First Task\r
+\r
+ .def vPortStartFirstTask\r
+\r
+ .asmfunc\r
+vPortStartFirstTask\r
+ portRESTORE_CONTEXT\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Yield Processor\r
+\r
+ .def vPortYieldProcessor\r
+ .ref vTaskSwitchContext\r
+\r
+ .asmfunc\r
+vPortYieldProcessor\r
+ add lr, lr, #4\r
+ portSAVE_CONTEXT\r
+ bl vTaskSwitchContext\r
+ portRESTORE_CONTEXT\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Preemptive Tick\r
+\r
+ .def vPreemptiveTick\r
+ .ref vTaskIncrementTick\r
+\r
+ .asmfunc\r
+vPreemptiveTick\r
+ portSAVE_CONTEXT\r
+ stmfd sp!, {r0, r1}\r
+ ; clear interrupt flag\r
+ ldr r0, intFlag\r
+ mov r1, #1\r
+ str r1, [r0]\r
+ bl vTaskIncrementTick\r
+ bl vTaskSwitchContext\r
+ ldmfd sp!, {r0, r1}\r
+ portRESTORE_CONTEXT\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; isr stub\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Port yield\r
+\r
+ .def vPortYield\r
+ \r
+ .asmfunc\r
+vPortYield\r
+ svc #0\r
+ bx lr\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Global Definitions\r
+\r
+ .ref pxCurrentTCB\r
+ .ref ulCriticalNesting\r
+\r
+intFlag .word 0xFFFFFC88\r
+curTCB .word pxCurrentTCB\r
+critNest .word ulCriticalNesting\r
+\r
+ \r
+\r
+;-------------------------------------------------------------------------------\r
+\r
--- /dev/null
+;/*\r
+; FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+; \r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS tutorial books are available in pdf and paperback. *\r
+; * Complete, revised, and edited pdf reference manuals are also *\r
+; * available. *\r
+; * *\r
+; * Purchasing FreeRTOS documentation will not only help you, by *\r
+; * ensuring you get running as quickly as possible and with an *\r
+; * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+; * the FreeRTOS project to continue with its mission of providing *\r
+; * professional grade, cross platform, de facto standard solutions *\r
+; * for microcontrollers - completely free of charge! *\r
+; * *\r
+; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+; * *\r
+; * Thank you for using FreeRTOS, and thank you for your support! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+; >>>NOTE<<< The modification to the GPL is included to allow you to\r
+; distribute a combined work that includes FreeRTOS without being obliged to\r
+; provide the source code for proprietary components outside of the FreeRTOS\r
+; kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+; more details. You should have received a copy of the GNU General Public\r
+; License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+; can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+; by writing to Richard Barry, contact details for whom are available on the\r
+; FreeRTOS WEB site.\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; http://www.FreeRTOS.org - Documentation, latest information, license and\r
+; contact details.\r
+;\r
+; http://www.SafeRTOS.com - A version that is certified for use in safety\r
+; critical systems.\r
+;\r
+; http://www.OpenRTOS.com - Commercial support, development, porting,\r
+; licensing and training services.\r
+;*/\r
+\r
+;\r
+; Save Task Context \r
+;\r
+portSAVE_CONTEXT .macro\r
+ stmfd sp!, {r0}\r
+ stmfd sp, {sp}^\r
+ sub sp, sp, #4\r
+ ldmfd sp!, {r0}\r
+ stmfd r0!, {lr}\r
+ mov lr, r0\r
+ ldmfd sp!, {r0}\r
+ stmfd lr, {r0-lr}^\r
+ sub lr, lr, #0x3C\r
+ fstmdbd lr!, {d0-d15}\r
+ mrs r0, spsr\r
+ fmrx r1, fpscr\r
+ stmfd lr!, {r0,r1}\r
+ ldr r0, critNest\r
+ ldr r0, [r0]\r
+ stmfd lr!, {r0}\r
+ ldr r0, curTCB\r
+ ldr r0, [r0]\r
+ str lr, [r0]\r
+ .endm\r
+\r
+;\r
+; Restore Task Context\r
+;\r
+portRESTORE_CONTEXT .macro\r
+ ldr r0, curTCB\r
+ ldr r0, [r0]\r
+ ldr lr, [r0]\r
+ ldr r0, critNest\r
+ ldmfd lr!, {r1}\r
+ str r1, [r0]\r
+ ldmfd lr!, {r0,r1}\r
+ fldmiad lr!, {d0-d15}\r
+ fmxr fpscr, r1\r
+ msr spsr_csxf, r0\r
+ ldmfd lr, {r0-r14}^\r
+ ldr lr, [lr, #0x3C]\r
+ subs pc, lr, #4\r
+ .endm\r
+\r
+ \r
+\r
+;-------------------------------------------------------------------------------\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers. That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#include "FreeRTOS.h"\r
+#include "os_task.h"\r
+\r
+#if ( configUSE_CO_ROUTINES == 1 )\r
+ #include "os_croutine.h"\r
+#endif\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC LIST API documented in list.h\r
+ *----------------------------------------------------------*/\r
+\r
+/* Constants used with the cRxLock and cTxLock structure members. */\r
+#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 )\r
+#define queueLOCKED_UNMODIFIED ( ( signed portBASE_TYPE ) 0 )\r
+\r
+#define queueERRONEOUS_UNBLOCK ( -1 )\r
+\r
+/* For internal use only. */\r
+#define queueSEND_TO_BACK ( 0 )\r
+#define queueSEND_TO_FRONT ( 1 )\r
+\r
+/* Effectively make a union out of the xQUEUE structure. */\r
+#define pxMutexHolder pcTail\r
+#define uxQueueType pcHead\r
+#define uxRecursiveCallCount pcReadFrom\r
+#define queueQUEUE_IS_MUTEX NULL\r
+\r
+/* Semaphores do not actually store or copy data, so have an items size of\r
+zero. */\r
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portBASE_TYPE ) 0 )\r
+#define queueDONT_BLOCK ( ( portTickType ) 0U )\r
+#define queueMUTEX_GIVE_BLOCK_TIME ( ( portTickType ) 0U )\r
+\r
+/*\r
+ * Definition of the queue used by the scheduler.\r
+ * Items are queued by copy, not reference.\r
+ */\r
+typedef struct QueueDefinition\r
+{\r
+ signed char *pcHead; /*< Points to the beginning of the queue storage area. */\r
+ signed char *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */\r
+\r
+ signed char *pcWriteTo; /*< Points to the free next place in the storage area. */\r
+ signed char *pcReadFrom; /*< Points to the last place that a queued item was read from. */\r
+\r
+ xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */\r
+ xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */\r
+\r
+ volatile unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */\r
+ unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */\r
+ unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */\r
+\r
+ signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */\r
+ signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */\r
+\r
+} xQUEUE;\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Inside this file xQueueHandle is a pointer to a xQUEUE structure.\r
+ * To keep the definition private the API header file defines it as a\r
+ * pointer to void.\r
+ */\r
+typedef xQUEUE * xQueueHandle;\r
+\r
+/*\r
+ * Prototypes for public functions are included here so we don't have to\r
+ * include the API header file (as it defines xQueueHandle differently). These\r
+ * functions are documented in the API header file.\r
+ */\r
+xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+void vQueueDelete( xQueueHandle xQueue ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken ) PRIVILEGED_FUNCTION;\r
+xQueueHandle xQueueCreateMutex( void ) PRIVILEGED_FUNCTION;\r
+xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ) PRIVILEGED_FUNCTION;\r
+portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ) PRIVILEGED_FUNCTION;\r
+portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle xMutex ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Co-routine queue functions differ from task queue functions. Co-routines are\r
+ * an optional component.\r
+ */\r
+#if configUSE_CO_ROUTINES == 1\r
+ signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) PRIVILEGED_FUNCTION;\r
+ signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) PRIVILEGED_FUNCTION;\r
+ signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+ signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) PRIVILEGED_FUNCTION;\r
+#endif\r
+\r
+/*\r
+ * The queue registry is just a means for kernel aware debuggers to locate\r
+ * queue structures. It has no other purpose so is an optional component.\r
+ */\r
+#if configQUEUE_REGISTRY_SIZE > 0\r
+\r
+ /* The type stored within the queue registry array. This allows a name\r
+ to be assigned to each queue making kernel aware debugging a little\r
+ more user friendly. */\r
+ typedef struct QUEUE_REGISTRY_ITEM\r
+ {\r
+ signed char *pcQueueName;\r
+ xQueueHandle xHandle;\r
+ } xQueueRegistryItem;\r
+\r
+ /* The queue registry is simply an array of xQueueRegistryItem structures.\r
+ The pcQueueName member of a structure being NULL is indicative of the\r
+ array position being vacant. */\r
+ xQueueRegistryItem xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];\r
+\r
+ /* Removes a queue from the registry by simply setting the pcQueueName\r
+ member to NULL. */\r
+ static void vQueueUnregisterQueue( xQueueHandle xQueue ) PRIVILEGED_FUNCTION;\r
+ void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcQueueName ) PRIVILEGED_FUNCTION;\r
+#endif\r
+\r
+/*\r
+ * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not\r
+ * prevent an ISR from adding or removing items to the queue, but does prevent\r
+ * an ISR from removing tasks from the queue event lists. If an ISR finds a\r
+ * queue is locked it will instead increment the appropriate queue lock count\r
+ * to indicate that a task may require unblocking. When the queue in unlocked\r
+ * these lock counts are inspected, and the appropriate action taken.\r
+ */\r
+static void prvUnlockQueue( xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Uses a critical section to determine if there is any data in a queue.\r
+ *\r
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.\r
+ */\r
+static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Uses a critical section to determine if there is any space in a queue.\r
+ *\r
+ * @return pdTRUE if there is no space, otherwise pdFALSE;\r
+ */\r
+static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Copies an item into the queue, either at the front of the queue or the\r
+ * back of the queue.\r
+ */\r
+static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Copies an item out of a queue.\r
+ */\r
+static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer ) PRIVILEGED_FUNCTION;\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro to mark a queue as locked. Locking a queue prevents an ISR from\r
+ * accessing the queue event lists.\r
+ */\r
+#define prvLockQueue( pxQueue ) \\r
+ taskENTER_CRITICAL(); \\r
+ { \\r
+ if( ( pxQueue )->xRxLock == queueUNLOCKED ) \\r
+ { \\r
+ ( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED; \\r
+ } \\r
+ if( ( pxQueue )->xTxLock == queueUNLOCKED ) \\r
+ { \\r
+ ( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED; \\r
+ } \\r
+ } \\r
+ taskEXIT_CRITICAL()\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC QUEUE MANAGEMENT API documented in queue.h\r
+ *----------------------------------------------------------*/\r
+\r
+xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize )\r
+{\r
+xQUEUE *pxNewQueue;\r
+size_t xQueueSizeInBytes;\r
+xQueueHandle xReturn = NULL;\r
+\r
+ /* Allocate the new queue structure. */\r
+ if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) );\r
+ if( pxNewQueue != NULL )\r
+ {\r
+ /* Create the list of pointers to queue items. The queue is one byte\r
+ longer than asked for to make wrap checking easier/faster. */\r
+ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1;\r
+\r
+ pxNewQueue->pcHead = ( signed char * ) pvPortMalloc( xQueueSizeInBytes );\r
+ if( pxNewQueue->pcHead != NULL )\r
+ {\r
+ /* Initialise the queue members as described above where the\r
+ queue type is defined. */\r
+ pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize );\r
+ pxNewQueue->uxMessagesWaiting = ( unsigned portBASE_TYPE ) 0U;\r
+ pxNewQueue->pcWriteTo = pxNewQueue->pcHead;\r
+ pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - ( unsigned portBASE_TYPE ) 1U ) * uxItemSize );\r
+ pxNewQueue->uxLength = uxQueueLength;\r
+ pxNewQueue->uxItemSize = uxItemSize;\r
+ pxNewQueue->xRxLock = queueUNLOCKED;\r
+ pxNewQueue->xTxLock = queueUNLOCKED;\r
+\r
+ /* Likewise ensure the event queues start with the correct state. */\r
+ vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );\r
+ vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );\r
+\r
+ traceQUEUE_CREATE( pxNewQueue );\r
+ xReturn = pxNewQueue;\r
+ }\r
+ else\r
+ {\r
+ traceQUEUE_CREATE_FAILED();\r
+ vPortFree( pxNewQueue );\r
+ }\r
+ }\r
+ }\r
+\r
+ configASSERT( xReturn );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_MUTEXES == 1 )\r
+\r
+ xQueueHandle xQueueCreateMutex( void )\r
+ {\r
+ xQUEUE *pxNewQueue;\r
+\r
+ /* Allocate the new queue structure. */\r
+ pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) );\r
+ if( pxNewQueue != NULL )\r
+ {\r
+ /* Information required for priority inheritance. */\r
+ pxNewQueue->pxMutexHolder = NULL;\r
+ pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;\r
+\r
+ /* Queues used as a mutex no data is actually copied into or out\r
+ of the queue. */\r
+ pxNewQueue->pcWriteTo = NULL;\r
+ pxNewQueue->pcReadFrom = NULL;\r
+\r
+ /* Each mutex has a length of 1 (like a binary semaphore) and\r
+ an item size of 0 as nothing is actually copied into or out\r
+ of the mutex. */\r
+ pxNewQueue->uxMessagesWaiting = ( unsigned portBASE_TYPE ) 0U;\r
+ pxNewQueue->uxLength = ( unsigned portBASE_TYPE ) 1U;\r
+ pxNewQueue->uxItemSize = ( unsigned portBASE_TYPE ) 0U;\r
+ pxNewQueue->xRxLock = queueUNLOCKED;\r
+ pxNewQueue->xTxLock = queueUNLOCKED;\r
+\r
+ /* Ensure the event queues start with the correct state. */\r
+ vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );\r
+ vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );\r
+\r
+ /* Start with the semaphore in the expected state. */\r
+ xQueueGenericSend( pxNewQueue, NULL, ( portTickType ) 0U, queueSEND_TO_BACK );\r
+\r
+ traceCREATE_MUTEX( pxNewQueue );\r
+ }\r
+ else\r
+ {\r
+ traceCREATE_MUTEX_FAILED();\r
+ }\r
+\r
+ configASSERT( pxNewQueue );\r
+ return pxNewQueue;\r
+ }\r
+\r
+#endif /* configUSE_MUTEXES */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_RECURSIVE_MUTEXES == 1\r
+\r
+ portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle pxMutex )\r
+ {\r
+ portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxMutex );\r
+\r
+ /* If this is the task that holds the mutex then pxMutexHolder will not\r
+ change outside of this task. If this task does not hold the mutex then\r
+ pxMutexHolder can never coincidentally equal the tasks handle, and as\r
+ this is the only condition we are interested in it does not matter if\r
+ pxMutexHolder is accessed simultaneously by another task. Therefore no\r
+ mutual exclusion is required to test the pxMutexHolder variable. */\r
+ if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() )\r
+ {\r
+ traceGIVE_MUTEX_RECURSIVE( pxMutex );\r
+\r
+ /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to\r
+ the task handle, therefore no underflow check is required. Also,\r
+ uxRecursiveCallCount is only modified by the mutex holder, and as\r
+ there can only be one, no mutual exclusion is required to modify the\r
+ uxRecursiveCallCount member. */\r
+ ( pxMutex->uxRecursiveCallCount )--;\r
+\r
+ /* Have we unwound the call count? */\r
+ if( pxMutex->uxRecursiveCallCount == 0 )\r
+ {\r
+ /* Return the mutex. This will automatically unblock any other\r
+ task that might be waiting to access the mutex. */\r
+ xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ /* We cannot give the mutex because we are not the holder. */\r
+ xReturn = pdFAIL;\r
+\r
+ traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif /* configUSE_RECURSIVE_MUTEXES */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_RECURSIVE_MUTEXES == 1\r
+\r
+ portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle pxMutex, portTickType xBlockTime )\r
+ {\r
+ portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxMutex );\r
+\r
+ /* Comments regarding mutual exclusion as per those within\r
+ xQueueGiveMutexRecursive(). */\r
+\r
+ traceTAKE_MUTEX_RECURSIVE( pxMutex );\r
+\r
+ if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() )\r
+ {\r
+ ( pxMutex->uxRecursiveCallCount )++;\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = xQueueGenericReceive( pxMutex, NULL, xBlockTime, pdFALSE );\r
+\r
+ /* pdPASS will only be returned if we successfully obtained the mutex,\r
+ we may have blocked to reach here. */\r
+ if( xReturn == pdPASS )\r
+ {\r
+ ( pxMutex->uxRecursiveCallCount )++;\r
+ }\r
+ else\r
+ {\r
+ traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif /* configUSE_RECURSIVE_MUTEXES */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_COUNTING_SEMAPHORES == 1\r
+\r
+ xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )\r
+ {\r
+ xQueueHandle pxHandle;\r
+\r
+ pxHandle = xQueueCreate( ( unsigned portBASE_TYPE ) uxCountValue, queueSEMAPHORE_QUEUE_ITEM_LENGTH );\r
+\r
+ if( pxHandle != NULL )\r
+ {\r
+ pxHandle->uxMessagesWaiting = uxInitialCount;\r
+\r
+ traceCREATE_COUNTING_SEMAPHORE();\r
+ }\r
+ else\r
+ {\r
+ traceCREATE_COUNTING_SEMAPHORE_FAILED();\r
+ }\r
+\r
+ configASSERT( pxHandle );\r
+ return pxHandle;\r
+ }\r
+\r
+#endif /* configUSE_COUNTING_SEMAPHORES */\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
+{\r
+signed portBASE_TYPE xEntryTimeSet = pdFALSE;\r
+xTimeOutType xTimeOut;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ /* This function relaxes the coding standard somewhat to allow return\r
+ statements within the function itself. This is done in the interest\r
+ of execution time efficiency. */\r
+ for( ;; )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Is there room on the queue now? To be running we must be\r
+ the highest priority task wanting to access the queue. */\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ traceQUEUE_SEND( pxQueue );\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+\r
+ /* If there was a task waiting for data to arrive on the\r
+ queue then unblock it now. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r
+ {\r
+ /* The unblocked task has a priority higher than\r
+ our own so yield immediately. Yes it is ok to do\r
+ this from within the critical section - the kernel\r
+ takes care of that. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Return to the original privilege level before exiting the\r
+ function. */\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xTicksToWait == ( portTickType ) 0 )\r
+ {\r
+ /* The queue was full and no block time is specified (or\r
+ the block time has expired) so leave now. */\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Return to the original privilege level before exiting\r
+ the function. */\r
+ traceQUEUE_SEND_FAILED( pxQueue );\r
+ return errQUEUE_FULL;\r
+ }\r
+ else if( xEntryTimeSet == pdFALSE )\r
+ {\r
+ /* The queue was full and a block time was specified so\r
+ configure the timeout structure. */\r
+ vTaskSetTimeOutState( &xTimeOut );\r
+ xEntryTimeSet = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Interrupts and other tasks can send to and receive from the queue\r
+ now the critical section has been exited. */\r
+\r
+ vTaskSuspendAll();\r
+ prvLockQueue( pxQueue );\r
+\r
+ /* Update the timeout state to see if it has expired yet. */\r
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+ {\r
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+ {\r
+ traceBLOCKING_ON_QUEUE_SEND( pxQueue );\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r
+\r
+ /* Unlocking the queue means queue events can effect the\r
+ event list. It is possible that interrupts occurring now\r
+ remove this task from the event list again - but as the\r
+ scheduler is suspended the task will go onto the pending\r
+ ready last instead of the actual ready list. */\r
+ prvUnlockQueue( pxQueue );\r
+\r
+ /* Resuming the scheduler will move tasks from the pending\r
+ ready list into the ready list - so it is feasible that this\r
+ task is already in a ready list before it yields - in which\r
+ case the yield will not cause a context switch unless there\r
+ is also a higher priority task in the pending ready list. */\r
+ if( xTaskResumeAll() == pdFALSE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Try again. */\r
+ prvUnlockQueue( pxQueue );\r
+ ( void ) xTaskResumeAll();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The timeout has expired. */\r
+ prvUnlockQueue( pxQueue );\r
+ ( void ) xTaskResumeAll();\r
+\r
+ /* Return to the original privilege level before exiting the\r
+ function. */\r
+ traceQUEUE_SEND_FAILED( pxQueue );\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_ALTERNATIVE_API == 1\r
+\r
+ signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
+ {\r
+ signed portBASE_TYPE xEntryTimeSet = pdFALSE;\r
+ xTimeOutType xTimeOut;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ for( ;; )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Is there room on the queue now? To be running we must be\r
+ the highest priority task wanting to access the queue. */\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ traceQUEUE_SEND( pxQueue );\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+\r
+ /* If there was a task waiting for data to arrive on the\r
+ queue then unblock it now. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )\r
+ {\r
+ /* The unblocked task has a priority higher than\r
+ our own so yield immediately. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+ taskEXIT_CRITICAL();\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xTicksToWait == ( portTickType ) 0 )\r
+ {\r
+ taskEXIT_CRITICAL();\r
+ return errQUEUE_FULL;\r
+ }\r
+ else if( xEntryTimeSet == pdFALSE )\r
+ {\r
+ vTaskSetTimeOutState( &xTimeOut );\r
+ xEntryTimeSet = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+ {\r
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+ {\r
+ traceBLOCKING_ON_QUEUE_SEND( pxQueue );\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ taskEXIT_CRITICAL();\r
+ traceQUEUE_SEND_FAILED( pxQueue );\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+#endif /* configUSE_ALTERNATIVE_API */\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_ALTERNATIVE_API == 1\r
+\r
+ signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
+ {\r
+ signed portBASE_TYPE xEntryTimeSet = pdFALSE;\r
+ xTimeOutType xTimeOut;\r
+ signed char *pcOriginalReadPosition;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ for( ;; )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Remember our read position in case we are just peeking. */\r
+ pcOriginalReadPosition = pxQueue->pcReadFrom;\r
+\r
+ prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+\r
+ if( xJustPeeking == pdFALSE )\r
+ {\r
+ traceQUEUE_RECEIVE( pxQueue );\r
+\r
+ /* We are actually removing data. */\r
+ --( pxQueue->uxMessagesWaiting );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ /* Record the information required to implement\r
+ priority inheritance should it become necessary. */\r
+ pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ traceQUEUE_PEEK( pxQueue );\r
+\r
+ /* We are not removing the data, so reset our read\r
+ pointer. */\r
+ pxQueue->pcReadFrom = pcOriginalReadPosition;\r
+\r
+ /* The data is being left in the queue, so see if there are\r
+ any other tasks waiting for the data. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ /* Tasks that are removed from the event list will get added to\r
+ the pending ready list as the scheduler is still suspended. */\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority than this task. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ taskEXIT_CRITICAL();\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xTicksToWait == ( portTickType ) 0 )\r
+ {\r
+ taskEXIT_CRITICAL();\r
+ traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+ return errQUEUE_EMPTY;\r
+ }\r
+ else if( xEntryTimeSet == pdFALSE )\r
+ {\r
+ vTaskSetTimeOutState( &xTimeOut );\r
+ xEntryTimeSet = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+ {\r
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r
+ {\r
+ traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ portENTER_CRITICAL();\r
+ vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ taskEXIT_CRITICAL();\r
+ traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+ return errQUEUE_EMPTY;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+\r
+#endif /* configUSE_ALTERNATIVE_API */\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+unsigned portBASE_TYPE uxSavedInterruptStatus;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( pxHigherPriorityTaskWoken );\r
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ /* Similar to xQueueGenericSend, except we don't block if there is no room\r
+ in the queue. Also we don't directly wake a task that was blocked on a\r
+ queue read, instead we return a flag to say whether a context switch is\r
+ required or not (i.e. has a task with a higher priority than us been woken\r
+ by this post). */\r
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ traceQUEUE_SEND_FROM_ISR( pxQueue );\r
+\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\r
+\r
+ /* If the queue is locked we do not alter the event list. This will\r
+ be done when the queue is unlocked later. */\r
+ if( pxQueue->xTxLock == queueUNLOCKED )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority so record that a\r
+ context switch is required. */\r
+ *pxHigherPriorityTaskWoken = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Increment the lock count so the task that unlocks the queue\r
+ knows that data was posted while it was locked. */\r
+ ++( pxQueue->xTxLock );\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\r
+ xReturn = errQUEUE_FULL;\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
+{\r
+signed portBASE_TYPE xEntryTimeSet = pdFALSE;\r
+xTimeOutType xTimeOut;\r
+signed char *pcOriginalReadPosition;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ /* This function relaxes the coding standard somewhat to allow return\r
+ statements within the function itself. This is done in the interest\r
+ of execution time efficiency. */\r
+\r
+ for( ;; )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Is there data in the queue now? To be running we must be\r
+ the highest priority task wanting to access the queue. */\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Remember our read position in case we are just peeking. */\r
+ pcOriginalReadPosition = pxQueue->pcReadFrom;\r
+\r
+ prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+\r
+ if( xJustPeeking == pdFALSE )\r
+ {\r
+ traceQUEUE_RECEIVE( pxQueue );\r
+\r
+ /* We are actually removing data. */\r
+ --( pxQueue->uxMessagesWaiting );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ /* Record the information required to implement\r
+ priority inheritance should it become necessary. */\r
+ pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ traceQUEUE_PEEK( pxQueue );\r
+\r
+ /* We are not removing the data, so reset our read\r
+ pointer. */\r
+ pxQueue->pcReadFrom = pcOriginalReadPosition;\r
+\r
+ /* The data is being left in the queue, so see if there are\r
+ any other tasks waiting for the data. */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ /* Tasks that are removed from the event list will get added to\r
+ the pending ready list as the scheduler is still suspended. */\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority than this task. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ taskEXIT_CRITICAL();\r
+ return pdPASS;\r
+ }\r
+ else\r
+ {\r
+ if( xTicksToWait == ( portTickType ) 0 )\r
+ {\r
+ /* The queue was empty and no block time is specified (or\r
+ the block time has expired) so leave now. */\r
+ taskEXIT_CRITICAL();\r
+ traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+ return errQUEUE_EMPTY;\r
+ }\r
+ else if( xEntryTimeSet == pdFALSE )\r
+ {\r
+ /* The queue was empty and a block time was specified so\r
+ configure the timeout structure. */\r
+ vTaskSetTimeOutState( &xTimeOut );\r
+ xEntryTimeSet = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Interrupts and other tasks can send to and receive from the queue\r
+ now the critical section has been exited. */\r
+\r
+ vTaskSuspendAll();\r
+ prvLockQueue( pxQueue );\r
+\r
+ /* Update the timeout state to see if it has expired yet. */\r
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\r
+ {\r
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )\r
+ {\r
+ traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ portENTER_CRITICAL();\r
+ {\r
+ vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );\r
+ }\r
+ portEXIT_CRITICAL();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+ prvUnlockQueue( pxQueue );\r
+ if( xTaskResumeAll() == pdFALSE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Try again. */\r
+ prvUnlockQueue( pxQueue );\r
+ ( void ) xTaskResumeAll();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ prvUnlockQueue( pxQueue );\r
+ ( void ) xTaskResumeAll();\r
+ traceQUEUE_RECEIVE_FAILED( pxQueue );\r
+ return errQUEUE_EMPTY;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+unsigned portBASE_TYPE uxSavedInterruptStatus;\r
+\r
+ configASSERT( pxQueue );\r
+ configASSERT( pxTaskWoken );\r
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( unsigned portBASE_TYPE ) 0U ) ) );\r
+\r
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ {\r
+ /* We cannot block from an ISR, so check there is data available. */\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ traceQUEUE_RECEIVE_FROM_ISR( pxQueue );\r
+\r
+ prvCopyDataFromQueue( pxQueue, pvBuffer );\r
+ --( pxQueue->uxMessagesWaiting );\r
+\r
+ /* If the queue is locked we will not modify the event list. Instead\r
+ we update the lock count so the task that unlocks the queue will know\r
+ that an ISR has removed data while the queue was locked. */\r
+ if( pxQueue->xRxLock == queueUNLOCKED )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority than us so\r
+ force a context switch. */\r
+ *pxTaskWoken = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Increment the lock count so the task that unlocks the queue\r
+ knows that data was removed while it was locked. */\r
+ ++( pxQueue->xRxLock );\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );\r
+ }\r
+ }\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue )\r
+{\r
+unsigned portBASE_TYPE uxReturn;\r
+\r
+ configASSERT( pxQueue );\r
+\r
+ taskENTER_CRITICAL();\r
+ uxReturn = pxQueue->uxMessagesWaiting;\r
+ taskEXIT_CRITICAL();\r
+\r
+ return uxReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue )\r
+{\r
+unsigned portBASE_TYPE uxReturn;\r
+\r
+ configASSERT( pxQueue );\r
+\r
+ uxReturn = pxQueue->uxMessagesWaiting;\r
+\r
+ return uxReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vQueueDelete( xQueueHandle pxQueue )\r
+{\r
+ configASSERT( pxQueue );\r
+\r
+ traceQUEUE_DELETE( pxQueue );\r
+ vQueueUnregisterQueue( pxQueue );\r
+ vPortFree( pxQueue->pcHead );\r
+ vPortFree( pxQueue );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition )\r
+{\r
+ if( pxQueue->uxItemSize == ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\r
+ {\r
+ /* The mutex is no longer being held. */\r
+ vTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );\r
+ pxQueue->pxMutexHolder = NULL;\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ else if( xPosition == queueSEND_TO_BACK )\r
+ {\r
+ memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize );\r
+ pxQueue->pcWriteTo += pxQueue->uxItemSize;\r
+ if( pxQueue->pcWriteTo >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcWriteTo = pxQueue->pcHead;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ memcpy( ( void * ) pxQueue->pcReadFrom, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize );\r
+ pxQueue->pcReadFrom -= pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom < pxQueue->pcHead )\r
+ {\r
+ pxQueue->pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );\r
+ }\r
+ }\r
+\r
+ ++( pxQueue->uxMessagesWaiting );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer )\r
+{\r
+ if( pxQueue->uxQueueType != queueQUEUE_IS_MUTEX )\r
+ {\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvUnlockQueue( xQueueHandle pxQueue )\r
+{\r
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\r
+\r
+ /* The lock counts contains the number of extra data items placed or\r
+ removed from the queue while the queue was locked. When a queue is\r
+ locked items can be added or removed, but the event lists cannot be\r
+ updated. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* See if data was added to the queue while it was locked. */\r
+ while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )\r
+ {\r
+ /* Data was posted while the queue was locked. Are any tasks\r
+ blocked waiting for data to become available? */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ /* Tasks that are removed from the event list will get added to\r
+ the pending ready list as the scheduler is still suspended. */\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The task waiting has a higher priority so record that a\r
+ context switch is required. */\r
+ vTaskMissedYield();\r
+ }\r
+\r
+ --( pxQueue->xTxLock );\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ pxQueue->xTxLock = queueUNLOCKED;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Do the same for the Rx lock. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ vTaskMissedYield();\r
+ }\r
+\r
+ --( pxQueue->xRxLock );\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ pxQueue->xRxLock = queueUNLOCKED;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 );\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxQueue );\r
+ xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength );\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxQueue );\r
+ xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* If the queue is already full we may have to block. A critical section\r
+ is required to prevent an interrupt removing something from the queue\r
+ between the check to see if the queue is full and blocking on the queue. */\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )\r
+ {\r
+ /* The queue is full - do we want to block or just leave without\r
+ posting? */\r
+ if( xTicksToWait > ( portTickType ) 0 )\r
+ {\r
+ /* As this is called from a coroutine we cannot block directly, but\r
+ return indicating that we need to block. */\r
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_BLOCKED;\r
+ }\r
+ else\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ portNOP();\r
+\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ /* There is room in the queue, copy the data into the queue. */\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\r
+ xReturn = pdPASS;\r
+\r
+ /* Were any co-routines waiting for data to become available? */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ /* In this instance the co-routine could be placed directly\r
+ into the ready list as we are within a critical section.\r
+ Instead the same pending ready list mechanism is used as if\r
+ the event were caused from within an interrupt. */\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ /* The co-routine waiting has a higher priority so record\r
+ that a yield might be appropriate. */\r
+ xReturn = errQUEUE_YIELD;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xReturn = errQUEUE_FULL;\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* If the queue is already empty we may have to block. A critical section\r
+ is required to prevent an interrupt adding something to the queue\r
+ between the check to see if the queue is empty and blocking on the queue. */\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* There are no messages in the queue, do we want to block or just\r
+ leave with nothing? */\r
+ if( xTicksToWait > ( portTickType ) 0 )\r
+ {\r
+ /* As this is a co-routine we cannot block directly, but return\r
+ indicating that we need to block. */\r
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_BLOCKED;\r
+ }\r
+ else\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ return errQUEUE_FULL;\r
+ }\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ portNOP();\r
+\r
+ portDISABLE_INTERRUPTS();\r
+ {\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Data is available from the queue. */\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ --( pxQueue->uxMessagesWaiting );\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+\r
+ xReturn = pdPASS;\r
+\r
+ /* Were any co-routines waiting for space to become available? */\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ /* In this instance the co-routine could be placed directly\r
+ into the ready list as we are within a critical section.\r
+ Instead the same pending ready list mechanism is used as if\r
+ the event were caused from within an interrupt. */\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ xReturn = errQUEUE_YIELD;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+ }\r
+ portENABLE_INTERRUPTS();\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken )\r
+{\r
+ /* Cannot block within an ISR so if there is no space on the queue then\r
+ exit without doing anything. */\r
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\r
+ {\r
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\r
+\r
+ /* We only want to wake one co-routine per ISR, so check that a\r
+ co-routine has not already been woken. */\r
+ if( xCoRoutinePreviouslyWoken == pdFALSE )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\r
+ {\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\r
+ {\r
+ return pdTRUE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ return xCoRoutinePreviouslyWoken;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_CO_ROUTINES == 1\r
+signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+\r
+ /* We cannot block from an ISR, so check there is data available. If\r
+ not then just leave without doing anything. */\r
+ if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 )\r
+ {\r
+ /* Copy the data from the queue. */\r
+ pxQueue->pcReadFrom += pxQueue->uxItemSize;\r
+ if( pxQueue->pcReadFrom >= pxQueue->pcTail )\r
+ {\r
+ pxQueue->pcReadFrom = pxQueue->pcHead;\r
+ }\r
+ --( pxQueue->uxMessagesWaiting );\r
+ memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\r
+\r
+ if( ( *pxCoRoutineWoken ) == pdFALSE )\r
+ {\r
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\r
+ {\r
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\r
+ {\r
+ *pxCoRoutineWoken = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ xReturn = pdPASS;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configQUEUE_REGISTRY_SIZE > 0\r
+\r
+ void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcQueueName )\r
+ {\r
+ unsigned portBASE_TYPE ux;\r
+\r
+ /* See if there is an empty space in the registry. A NULL name denotes\r
+ a free slot. */\r
+ for( ux = ( unsigned portBASE_TYPE ) 0U; ux < ( unsigned portBASE_TYPE ) configQUEUE_REGISTRY_SIZE; ux++ )\r
+ {\r
+ if( xQueueRegistry[ ux ].pcQueueName == NULL )\r
+ {\r
+ /* Store the information on this queue. */\r
+ xQueueRegistry[ ux ].pcQueueName = pcQueueName;\r
+ xQueueRegistry[ ux ].xHandle = xQueue;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configQUEUE_REGISTRY_SIZE > 0\r
+\r
+ static void vQueueUnregisterQueue( xQueueHandle xQueue )\r
+ {\r
+ unsigned portBASE_TYPE ux;\r
+\r
+ /* See if the handle of the queue being unregistered in actually in the\r
+ registry. */\r
+ for( ux = ( unsigned portBASE_TYPE ) 0U; ux < ( unsigned portBASE_TYPE ) configQUEUE_REGISTRY_SIZE; ux++ )\r
+ {\r
+ if( xQueueRegistry[ ux ].xHandle == xQueue )\r
+ {\r
+ /* Set the name to NULL to show that this slot if free again. */\r
+ xQueueRegistry[ ux ].pcQueueName = NULL;\r
+ break;\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_TIMERS == 1\r
+\r
+ void vQueueWaitForMessageRestricted( xQueueHandle pxQueue, portTickType xTicksToWait )\r
+ {\r
+ /* This function should not be called by application code hence the\r
+ 'Restricted' in its name. It is not part of the public API. It is\r
+ designed for use by kernel code, and has special calling requirements.\r
+ It can result in vListInsert() being called on a list that can only\r
+ possibly ever have one item in it, so the list will be fast, but even\r
+ so it should be called with the scheduler locked and not from a critical\r
+ section. */\r
+\r
+ /* Only do anything if there are no messages in the queue. This function\r
+ will not actually cause the task to block, just place it on a blocked\r
+ list. It will not block until the scheduler is unlocked - at which\r
+ time a yield will be performed. If an item is added to the queue while\r
+ the queue is locked, and the calling task blocks on the queue, then the\r
+ calling task will be immediately unblocked when the queue is unlocked. */\r
+ prvLockQueue( pxQueue );\r
+ if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ /* There is nothing in the queue, block for the specified period. */\r
+ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\r
+ }\r
+ prvUnlockQueue( pxQueue );\r
+ }\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+ \r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+\r
+#include <stdio.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers. That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#include "FreeRTOS.h"\r
+#include "os_task.h"\r
+#include "os_timer.h"\r
+#include "os_StackMacros.h"\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/*\r
+ * Macro to define the amount of stack available to the idle task.\r
+ */\r
+#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE\r
+\r
+/*\r
+ * Task control block. A task control block (TCB) is allocated to each task,\r
+ * and stores the context of the task.\r
+ */\r
+typedef struct tskTaskControlBlock\r
+{\r
+ volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */\r
+\r
+ #if ( portUSING_MPU_WRAPPERS == 1 )\r
+ xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE STRUCT. */\r
+ #endif \r
+ \r
+ xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */\r
+ xListItem xEventListItem; /*< List item used to place the TCB in event lists. */\r
+ unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */\r
+ portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */\r
+ signed char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */\r
+\r
+ #if ( portSTACK_GROWTH > 0 )\r
+ portSTACK_TYPE *pxEndOfStack; /*< Used for stack overflow checking on architectures where the stack grows up from low memory. */\r
+ #endif\r
+\r
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+ unsigned portBASE_TYPE uxCriticalNesting;\r
+ #endif\r
+\r
+ #if ( configUSE_TRACE_FACILITY == 1 )\r
+ unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */\r
+ #endif\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ unsigned portBASE_TYPE uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */\r
+ #endif\r
+\r
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+ pdTASK_HOOK_CODE pxTaskTag;\r
+ #endif\r
+\r
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+ unsigned long ulRunTimeCounter; /*< Used for calculating how much CPU time each task is utilising. */\r
+ #endif\r
+\r
+} tskTCB;\r
+\r
+\r
+/*\r
+ * Some kernel aware debuggers require data to be viewed to be global, rather\r
+ * than file scope.\r
+ */\r
+#ifdef portREMOVE_STATIC_QUALIFIER\r
+ #define static\r
+#endif\r
+\r
+/*lint -e956 */\r
+PRIVILEGED_DATA tskTCB * volatile pxCurrentTCB = NULL;\r
+\r
+/* Lists for ready and blocked tasks. --------------------*/\r
+\r
+PRIVILEGED_DATA static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */\r
+PRIVILEGED_DATA static xList xDelayedTaskList1; /*< Delayed tasks. */\r
+PRIVILEGED_DATA static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */\r
+PRIVILEGED_DATA static xList * volatile pxDelayedTaskList ; /*< Points to the delayed task list currently being used. */\r
+PRIVILEGED_DATA static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */\r
+PRIVILEGED_DATA static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */\r
+\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ PRIVILEGED_DATA static xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */\r
+ PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0U;\r
+\r
+#endif\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ PRIVILEGED_DATA static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */\r
+\r
+#endif\r
+\r
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+ \r
+ PRIVILEGED_DATA static xTaskHandle xIdleTaskHandle = NULL;\r
+ \r
+#endif\r
+\r
+/* File private variables. --------------------------------*/\r
+PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0U;\r
+PRIVILEGED_DATA static volatile portTickType xTickCount = ( portTickType ) 0U;\r
+PRIVILEGED_DATA static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY;\r
+PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY;\r
+PRIVILEGED_DATA static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE;\r
+PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE;\r
+PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0U;\r
+PRIVILEGED_DATA static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE;\r
+PRIVILEGED_DATA static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0;\r
+PRIVILEGED_DATA static unsigned portBASE_TYPE uxTaskNumber = ( unsigned portBASE_TYPE ) 0U;\r
+PRIVILEGED_DATA static portTickType xNextTaskUnblockTime = ( portTickType ) portMAX_DELAY;\r
+\r
+#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+\r
+ PRIVILEGED_DATA static char pcStatsString[ 50 ] ;\r
+ PRIVILEGED_DATA static unsigned long ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */\r
+ static void prvGenerateRunTimeStatsForTasksInList( const signed char *pcWriteBuffer, xList *pxList, unsigned long ulTotalRunTime ) PRIVILEGED_FUNCTION;\r
+\r
+#endif\r
+\r
+/* Debugging and trace facilities private variables and macros. ------------*/\r
+\r
+/*\r
+ * The value used to fill the stack of a task when the task is created. This\r
+ * is used purely for checking the high water mark for tasks.\r
+ */\r
+#define tskSTACK_FILL_BYTE ( 0xa5U )\r
+\r
+/*\r
+ * Macros used by vListTask to indicate which state a task is in.\r
+ */\r
+#define tskBLOCKED_CHAR ( ( signed char ) 'B' )\r
+#define tskREADY_CHAR ( ( signed char ) 'R' )\r
+#define tskDELETED_CHAR ( ( signed char ) 'D' )\r
+#define tskSUSPENDED_CHAR ( ( signed char ) 'S' )\r
+\r
+/*\r
+ * Macros and private variables used by the trace facility.\r
+ */\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned long ) ( sizeof( unsigned long ) + sizeof( unsigned long ) ) )\r
+ PRIVILEGED_DATA static volatile signed char * volatile pcTraceBuffer;\r
+ PRIVILEGED_DATA static signed char *pcTraceBufferStart;\r
+ PRIVILEGED_DATA static signed char *pcTraceBufferEnd;\r
+ PRIVILEGED_DATA static signed portBASE_TYPE xTracing = pdFALSE;\r
+ static unsigned portBASE_TYPE uxPreviousTask = 255U;\r
+ PRIVILEGED_DATA static char pcStatusString[ 50 ];\r
+\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro that writes a trace of scheduler activity to a buffer. This trace\r
+ * shows which task is running when and is very useful as a debugging tool.\r
+ * As this macro is called each context switch it is a good idea to undefine\r
+ * it if not using the facility.\r
+ */\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ #define vWriteTraceToBuffer() \\r
+ { \\r
+ if( xTracing != pdFALSE ) \\r
+ { \\r
+ if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \\r
+ { \\r
+ if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \\r
+ { \\r
+ uxPreviousTask = pxCurrentTCB->uxTCBNumber; \\r
+ *( unsigned long * ) pcTraceBuffer = ( unsigned long ) xTickCount; \\r
+ pcTraceBuffer += sizeof( unsigned long ); \\r
+ *( unsigned long * ) pcTraceBuffer = ( unsigned long ) uxPreviousTask; \\r
+ pcTraceBuffer += sizeof( unsigned long ); \\r
+ } \\r
+ else \\r
+ { \\r
+ xTracing = pdFALSE; \\r
+ } \\r
+ } \\r
+ } \\r
+ }\r
+\r
+#else\r
+\r
+ #define vWriteTraceToBuffer()\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Place the task represented by pxTCB into the appropriate ready queue for\r
+ * the task. It is inserted at the end of the list. One quirk of this is\r
+ * that if the task being inserted is at the same priority as the currently\r
+ * executing task, then it will only be rescheduled after the currently\r
+ * executing task has been rescheduled.\r
+ */\r
+#define prvAddTaskToReadyQueue( pxTCB ) \\r
+ if( ( pxTCB )->uxPriority > uxTopReadyPriority ) \\r
+ { \\r
+ uxTopReadyPriority = ( pxTCB )->uxPriority; \\r
+ } \\r
+ vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xGenericListItem ) )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Macro that looks at the list of tasks that are currently delayed to see if\r
+ * any require waking.\r
+ *\r
+ * Tasks are stored in the queue in the order of their wake time - meaning\r
+ * once one tasks has been found whose timer has not expired we need not look\r
+ * any further down the list.\r
+ */\r
+#define prvCheckDelayedTasks() \\r
+{ \\r
+portTickType xItemValue; \\r
+ \\r
+ /* Is the tick count greater than or equal to the wake time of the first \\r
+ task referenced from the delayed tasks list? */ \\r
+ if( xTickCount >= xNextTaskUnblockTime ) \\r
+ { \\r
+ for( ;; ) \\r
+ { \\r
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) \\r
+ { \\r
+ /* The delayed list is empty. Set xNextTaskUnblockTime to the \\r
+ maximum possible value so it is extremely unlikely that the \\r
+ if( xTickCount >= xNextTaskUnblockTime ) test will pass next \\r
+ time through. */ \\r
+ xNextTaskUnblockTime = portMAX_DELAY; \\r
+ break; \\r
+ } \\r
+ else \\r
+ { \\r
+ /* The delayed list is not empty, get the value of the item at \\r
+ the head of the delayed list. This is the time at which the \\r
+ task at the head of the delayed list should be removed from \\r
+ the Blocked state. */ \\r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); \\r
+ xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ); \\r
+ \\r
+ if( xTickCount < xItemValue ) \\r
+ { \\r
+ /* It is not time to unblock this item yet, but the item \\r
+ value is the time at which the task at the head of the \\r
+ blocked list should be removed from the Blocked state - \\r
+ so record the item value in xNextTaskUnblockTime. */ \\r
+ xNextTaskUnblockTime = xItemValue; \\r
+ break; \\r
+ } \\r
+ \\r
+ /* It is time to remove the item from the Blocked state. */ \\r
+ vListRemove( &( pxTCB->xGenericListItem ) ); \\r
+ \\r
+ /* Is the task waiting on an event also? */ \\r
+ if( pxTCB->xEventListItem.pvContainer != NULL ) \\r
+ { \\r
+ vListRemove( &( pxTCB->xEventListItem ) ); \\r
+ } \\r
+ prvAddTaskToReadyQueue( pxTCB ); \\r
+ } \\r
+ } \\r
+ } \\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Several functions take an xTaskHandle parameter that can optionally be NULL,\r
+ * where NULL is used to indicate that the handle of the currently executing\r
+ * task should be used in place of the parameter. This macro simply checks to\r
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.\r
+ */\r
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) ( pxHandle ) )\r
+\r
+/* Callback function prototypes. --------------------------*/\r
+extern void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName );\r
+extern void vApplicationTickHook( void );\r
+ \r
+/* File private functions. --------------------------------*/\r
+\r
+/*\r
+ * Utility to ready a TCB for a given task. Mainly just copies the parameters\r
+ * into the TCB structure.\r
+ */\r
+static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed char * const pcName, unsigned portBASE_TYPE uxPriority, const xMemoryRegion * const xRegions, unsigned short usStackDepth ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Utility to ready all the lists used by the scheduler. This is called\r
+ * automatically upon the creation of the first task.\r
+ */\r
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The idle task, which as all tasks is implemented as a never ending loop.\r
+ * The idle task is automatically created and added to the ready lists upon\r
+ * creation of the first user task.\r
+ *\r
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific\r
+ * language extensions. The equivalent prototype for this function is:\r
+ *\r
+ * void prvIdleTask( void *pvParameters );\r
+ *\r
+ */\r
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );\r
+\r
+/*\r
+ * Utility to free all memory allocated by the scheduler to hold a TCB,\r
+ * including the stack pointed to by the TCB.\r
+ *\r
+ * This does not free memory allocated by the task itself (i.e. memory\r
+ * allocated by calls to pvPortMalloc from within the tasks application code).\r
+ */\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ static void prvDeleteTCB( tskTCB *pxTCB ) PRIVILEGED_FUNCTION;\r
+\r
+#endif\r
+\r
+/*\r
+ * Used only by the idle task. This checks to see if anything has been placed\r
+ * in the list of tasks waiting to be deleted. If so the task is cleaned up\r
+ * and its TCB deleted.\r
+ */\r
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The currently executing task is entering the Blocked state. Add the task to\r
+ * either the current or the overflow delayed task list.\r
+ */\r
+static void prvAddCurrentTaskToDelayedList( portTickType xTimeToWake ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Allocates memory from the heap for a TCB and associated stack. Checks the\r
+ * allocation was successful.\r
+ */\r
+static tskTCB *prvAllocateTCBAndStack( unsigned short usStackDepth, portSTACK_TYPE *puxStackBuffer ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Called from vTaskList. vListTasks details all the tasks currently under\r
+ * control of the scheduler. The tasks may be in one of a number of lists.\r
+ * prvListTaskWithinSingleList accepts a list and details the tasks from\r
+ * within just that list.\r
+ *\r
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM\r
+ * NORMAL APPLICATION CODE.\r
+ */\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ static void prvListTaskWithinSingleList( const signed char *pcWriteBuffer, xList *pxList, signed char cStatus ) PRIVILEGED_FUNCTION;\r
+\r
+#endif\r
+\r
+/*\r
+ * When a task is created, the stack of the task is filled with a known value.\r
+ * This function determines the 'high water mark' of the task stack by\r
+ * determining how much of the stack remains at the original preset value.\r
+ */\r
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r
+\r
+ static unsigned short usTaskCheckFreeStackSpace( const unsigned char * pucStackByte ) PRIVILEGED_FUNCTION;\r
+\r
+#endif\r
+\r
+\r
+/*lint +e956 */\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CREATION API documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskGenericCreate( pdTASK_CODE pxTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )\r
+{\r
+signed portBASE_TYPE xReturn;\r
+tskTCB * pxNewTCB;\r
+\r
+ configASSERT( pxTaskCode );\r
+ configASSERT( ( uxPriority < configMAX_PRIORITIES ) );\r
+\r
+ /* Allocate the memory required by the TCB and stack for the new task,\r
+ checking that the allocation was successful. */\r
+ pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );\r
+\r
+ if( pxNewTCB != NULL )\r
+ {\r
+ portSTACK_TYPE *pxTopOfStack;\r
+\r
+ #if( portUSING_MPU_WRAPPERS == 1 )\r
+ /* Should the task be created in privileged mode? */\r
+ portBASE_TYPE xRunPrivileged;\r
+ if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )\r
+ {\r
+ xRunPrivileged = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ xRunPrivileged = pdFALSE;\r
+ }\r
+ uxPriority &= ~portPRIVILEGE_BIT;\r
+ #endif /* portUSING_MPU_WRAPPERS == 1 */\r
+\r
+ /* Calculate the top of stack address. This depends on whether the\r
+ stack grows from high memory to low (as per the 80x86) or visa versa.\r
+ portSTACK_GROWTH is used to make the result positive or negative as\r
+ required by the port. */\r
+ #if( portSTACK_GROWTH < 0 )\r
+ {\r
+ pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( unsigned short ) 1 );\r
+ pxTopOfStack = ( portSTACK_TYPE * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ( portPOINTER_SIZE_TYPE ) ~portBYTE_ALIGNMENT_MASK ) );\r
+\r
+ /* Check the alignment of the calculated top of stack is correct. */\r
+ configASSERT( ( ( ( unsigned long ) pxTopOfStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
+ }\r
+ #else\r
+ {\r
+ pxTopOfStack = pxNewTCB->pxStack;\r
+ \r
+ /* Check the alignment of the stack buffer is correct. */\r
+ configASSERT( ( ( ( unsigned long ) pxNewTCB->pxStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
+\r
+ /* If we want to use stack checking on architectures that use\r
+ a positive stack growth direction then we also need to store the\r
+ other extreme of the stack space. */\r
+ pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 );\r
+ }\r
+ #endif\r
+\r
+ /* Setup the newly allocated TCB with the initial state of the task. */\r
+ prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );\r
+\r
+ /* Initialize the TCB stack to look as if the task was already running,\r
+ but had been interrupted by the scheduler. The return address is set\r
+ to the start of the task function. Once the stack has been initialised\r
+ the top of stack variable is updated. */\r
+ #if( portUSING_MPU_WRAPPERS == 1 )\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\r
+ }\r
+ #else\r
+ {\r
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\r
+ }\r
+ #endif\r
+\r
+ /* Check the alignment of the initialised stack. */\r
+ configASSERT( ( ( ( unsigned long ) pxNewTCB->pxTopOfStack & ( unsigned long ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\r
+\r
+ if( ( void * ) pxCreatedTask != NULL )\r
+ {\r
+ /* Pass the TCB out - in an anonymous way. The calling function/\r
+ task can use this as a handle to delete the task later if\r
+ required.*/\r
+ *pxCreatedTask = ( xTaskHandle ) pxNewTCB;\r
+ }\r
+ \r
+ /* We are going to manipulate the task queues to add this task to a\r
+ ready list, so must make sure no interrupts occur. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ uxCurrentNumberOfTasks++;\r
+ if( pxCurrentTCB == NULL )\r
+ {\r
+ /* There are no other tasks, or all the other tasks are in\r
+ the suspended state - make this the current task. */\r
+ pxCurrentTCB = pxNewTCB;\r
+\r
+ if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 )\r
+ {\r
+ /* This is the first task to be created so do the preliminary\r
+ initialisation required. We will not recover if this call\r
+ fails, but we will report the failure. */\r
+ prvInitialiseTaskLists();\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* If the scheduler is not already running, make this task the\r
+ current task if it is the highest priority task to be created\r
+ so far. */\r
+ if( xSchedulerRunning == pdFALSE )\r
+ {\r
+ if( pxCurrentTCB->uxPriority <= uxPriority )\r
+ {\r
+ pxCurrentTCB = pxNewTCB;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Remember the top priority to make context switching faster. Use\r
+ the priority in pxNewTCB as this has been capped to a valid value. */\r
+ if( pxNewTCB->uxPriority > uxTopUsedPriority )\r
+ {\r
+ uxTopUsedPriority = pxNewTCB->uxPriority;\r
+ }\r
+\r
+ #if ( configUSE_TRACE_FACILITY == 1 )\r
+ {\r
+ /* Add a counter into the TCB for tracing only. */\r
+ pxNewTCB->uxTCBNumber = uxTaskNumber;\r
+ }\r
+ #endif\r
+ uxTaskNumber++;\r
+\r
+ prvAddTaskToReadyQueue( pxNewTCB );\r
+\r
+ xReturn = pdPASS;\r
+ traceTASK_CREATE( pxNewTCB );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ else\r
+ {\r
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\r
+ traceTASK_CREATE_FAILED();\r
+ }\r
+\r
+ if( xReturn == pdPASS )\r
+ {\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ /* If the created task is of a higher priority than the current task\r
+ then it should run now. */\r
+ if( pxCurrentTCB->uxPriority < uxPriority )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ void vTaskDelete( xTaskHandle pxTaskToDelete )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Ensure a yield is performed if the current task is being\r
+ deleted. */\r
+ if( pxTaskToDelete == pxCurrentTCB )\r
+ {\r
+ pxTaskToDelete = NULL;\r
+ }\r
+\r
+ /* If null is passed in here then we are deleting ourselves. */\r
+ pxTCB = prvGetTCBFromHandle( pxTaskToDelete );\r
+\r
+ /* Remove task from the ready list and place in the termination list.\r
+ This will stop the task from be scheduled. The idle task will check\r
+ the termination list and free up any memory allocated by the\r
+ scheduler for the TCB and stack. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Is the task waiting on an event also? */\r
+ if( pxTCB->xEventListItem.pvContainer != NULL )\r
+ {\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ }\r
+\r
+ vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Increment the ucTasksDeleted variable so the idle task knows\r
+ there is a task that has been deleted and that it should therefore\r
+ check the xTasksWaitingTermination list. */\r
+ ++uxTasksDeleted;\r
+\r
+ /* Increment the uxTaskNumberVariable also so kernel aware debuggers\r
+ can detect that the task lists need re-generating. */\r
+ uxTaskNumber++;\r
+\r
+ traceTASK_DELETE( pxTCB );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ /* Force a reschedule if we have just deleted the current task. */\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ if( ( void * ) pxTaskToDelete == NULL )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * TASK CONTROL API documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelayUntil == 1 )\r
+\r
+ void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )\r
+ {\r
+ portTickType xTimeToWake;\r
+ portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE;\r
+\r
+ configASSERT( pxPreviousWakeTime );\r
+ configASSERT( ( xTimeIncrement > 0U ) );\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Generate the tick time at which the task wants to wake. */\r
+ xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\r
+\r
+ if( xTickCount < *pxPreviousWakeTime )\r
+ {\r
+ /* The tick count has overflowed since this function was\r
+ lasted called. In this case the only time we should ever\r
+ actually delay is if the wake time has also overflowed,\r
+ and the wake time is greater than the tick time. When this\r
+ is the case it is as if neither time had overflowed. */\r
+ if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) )\r
+ {\r
+ xShouldDelay = pdTRUE;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The tick time has not overflowed. In this case we will\r
+ delay if either the wake time has overflowed, and/or the\r
+ tick time is less than the wake time. */\r
+ if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) )\r
+ {\r
+ xShouldDelay = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* Update the wake time ready for the next call. */\r
+ *pxPreviousWakeTime = xTimeToWake;\r
+\r
+ if( xShouldDelay != pdFALSE )\r
+ {\r
+ traceTASK_DELAY_UNTIL();\r
+\r
+ /* We must remove ourselves from the ready list before adding\r
+ ourselves to the blocked list as the same list item is used for\r
+ both lists. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ }\r
+ xAlreadyYielded = xTaskResumeAll();\r
+\r
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
+ have put ourselves to sleep. */\r
+ if( xAlreadyYielded == pdFALSE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelay == 1 )\r
+\r
+ void vTaskDelay( portTickType xTicksToDelay )\r
+ {\r
+ portTickType xTimeToWake;\r
+ signed portBASE_TYPE xAlreadyYielded = pdFALSE;\r
+\r
+ /* A delay time of zero just forces a reschedule. */\r
+ if( xTicksToDelay > ( portTickType ) 0U )\r
+ {\r
+ vTaskSuspendAll();\r
+ {\r
+ traceTASK_DELAY();\r
+\r
+ /* A task that is removed from the event list while the\r
+ scheduler is suspended will not get placed in the ready\r
+ list or removed from the blocked list until the scheduler\r
+ is resumed.\r
+\r
+ This task cannot be in an event list as it is the currently\r
+ executing task. */\r
+\r
+ /* Calculate the time to wake - this may overflow but this is\r
+ not a problem. */\r
+ xTimeToWake = xTickCount + xTicksToDelay;\r
+\r
+ /* We must remove ourselves from the ready list before adding\r
+ ourselves to the blocked list as the same list item is used for\r
+ both lists. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ xAlreadyYielded = xTaskResumeAll();\r
+ }\r
+\r
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may\r
+ have put ourselves to sleep. */\r
+ if( xAlreadyYielded == pdFALSE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_uxTaskPriorityGet == 1 )\r
+\r
+ unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask )\r
+ {\r
+ tskTCB *pxTCB;\r
+ unsigned portBASE_TYPE uxReturn;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* If null is passed in here then we are changing the\r
+ priority of the calling function. */\r
+ pxTCB = prvGetTCBFromHandle( pxTask );\r
+ uxReturn = pxTCB->uxPriority;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return uxReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskPrioritySet == 1 )\r
+\r
+ void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )\r
+ {\r
+ tskTCB *pxTCB;\r
+ unsigned portBASE_TYPE uxCurrentPriority;\r
+ portBASE_TYPE xYieldRequired = pdFALSE;\r
+\r
+ configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );\r
+\r
+ /* Ensure the new priority is valid. */\r
+ if( uxNewPriority >= configMAX_PRIORITIES )\r
+ {\r
+ uxNewPriority = configMAX_PRIORITIES - ( unsigned portBASE_TYPE ) 1U;\r
+ }\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( pxTask == pxCurrentTCB )\r
+ {\r
+ pxTask = NULL;\r
+ }\r
+\r
+ /* If null is passed in here then we are changing the\r
+ priority of the calling function. */\r
+ pxTCB = prvGetTCBFromHandle( pxTask );\r
+\r
+ traceTASK_PRIORITY_SET( pxTask, uxNewPriority );\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ uxCurrentPriority = pxTCB->uxBasePriority;\r
+ }\r
+ #else\r
+ {\r
+ uxCurrentPriority = pxTCB->uxPriority;\r
+ }\r
+ #endif\r
+\r
+ if( uxCurrentPriority != uxNewPriority )\r
+ {\r
+ /* The priority change may have readied a task of higher\r
+ priority than the calling task. */\r
+ if( uxNewPriority > uxCurrentPriority )\r
+ {\r
+ if( pxTask != NULL )\r
+ {\r
+ /* The priority of another task is being raised. If we\r
+ were raising the priority of the currently running task\r
+ there would be no need to switch as it must have already\r
+ been the highest priority task. */\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ }\r
+ else if( pxTask == NULL )\r
+ {\r
+ /* Setting our own priority down means there may now be another\r
+ task of higher priority that is ready to execute. */\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+\r
+\r
+\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ /* Only change the priority being used if the task is not\r
+ currently using an inherited priority. */\r
+ if( pxTCB->uxBasePriority == pxTCB->uxPriority )\r
+ {\r
+ pxTCB->uxPriority = uxNewPriority;\r
+ }\r
+\r
+ /* The base priority gets set whatever. */\r
+ pxTCB->uxBasePriority = uxNewPriority;\r
+ }\r
+ #else\r
+ {\r
+ pxTCB->uxPriority = uxNewPriority;\r
+ }\r
+ #endif\r
+\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( configMAX_PRIORITIES - ( portTickType ) uxNewPriority ) );\r
+\r
+ /* If the task is in the blocked or suspended list we need do\r
+ nothing more than change it's priority variable. However, if\r
+ the task is in a ready list it needs to be removed and placed\r
+ in the queue appropriate to its new priority. */\r
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) )\r
+ {\r
+ /* The task is currently in its ready list - remove before adding\r
+ it to it's new ready list. As we are in a critical section we\r
+ can do this even if the scheduler is suspended. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+\r
+ if( xYieldRequired == pdTRUE )\r
+ {\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ void vTaskSuspend( xTaskHandle pxTaskToSuspend )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Ensure a yield is performed if the current task is being\r
+ suspended. */\r
+ if( pxTaskToSuspend == pxCurrentTCB )\r
+ {\r
+ pxTaskToSuspend = NULL;\r
+ }\r
+\r
+ /* If null is passed in here then we are suspending ourselves. */\r
+ pxTCB = prvGetTCBFromHandle( pxTaskToSuspend );\r
+\r
+ traceTASK_SUSPEND( pxTCB );\r
+\r
+ /* Remove task from the ready/delayed list and place in the suspended list. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Is the task waiting on an event also? */\r
+ if( pxTCB->xEventListItem.pvContainer != NULL )\r
+ {\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ }\r
+\r
+ vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ if( ( void * ) pxTaskToSuspend == NULL )\r
+ {\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ /* We have just suspended the current task. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ else\r
+ {\r
+ /* The scheduler is not running, but the task that was pointed\r
+ to by pxCurrentTCB has just been suspended and pxCurrentTCB\r
+ must be adjusted to point to a different task. */\r
+ if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )\r
+ {\r
+ /* No other tasks are ready, so set pxCurrentTCB back to\r
+ NULL so when the next task is created pxCurrentTCB will\r
+ be set to point to it no matter what its relative priority\r
+ is. */\r
+ pxCurrentTCB = NULL;\r
+ }\r
+ else\r
+ {\r
+ vTaskSwitchContext();\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask )\r
+ {\r
+ portBASE_TYPE xReturn = pdFALSE;\r
+ const tskTCB * const pxTCB = ( tskTCB * ) xTask;\r
+\r
+ /* It does not make sense to check if the calling task is suspended. */\r
+ configASSERT( xTask );\r
+\r
+ /* Is the task we are attempting to resume actually in the\r
+ suspended list? */\r
+ if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
+ {\r
+ /* Has the task already been resumed from within an ISR? */\r
+ if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE )\r
+ {\r
+ /* Is it in the suspended list because it is in the\r
+ Suspended state? It is possible to be in the suspended\r
+ list because it is blocked on a task with no timeout\r
+ specified. */\r
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) == pdTRUE )\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskSuspend == 1 )\r
+\r
+ void vTaskResume( xTaskHandle pxTaskToResume )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ /* It does not make sense to resume the calling task. */\r
+ configASSERT( pxTaskToResume );\r
+\r
+ /* Remove the task from whichever list it is currently in, and place\r
+ it in the ready list. */\r
+ pxTCB = ( tskTCB * ) pxTaskToResume;\r
+\r
+ /* The parameter cannot be NULL as it is impossible to resume the\r
+ currently executing task. */\r
+ if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )\r
+ {\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r
+ {\r
+ traceTASK_RESUME( pxTCB );\r
+\r
+ /* As we are in a critical section we can access the ready\r
+ lists even if the scheduler is suspended. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+\r
+ /* We may have just resumed a higher priority task. */\r
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+ {\r
+ /* This yield may not cause the task just resumed to run, but\r
+ will leave the lists in the correct state for the next yield. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+ }\r
+\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\r
+\r
+ portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume )\r
+ {\r
+ portBASE_TYPE xYieldRequired = pdFALSE;\r
+ tskTCB *pxTCB;\r
+\r
+ configASSERT( pxTaskToResume );\r
+\r
+ pxTCB = ( tskTCB * ) pxTaskToResume;\r
+\r
+ if( xTaskIsTaskSuspended( pxTCB ) == pdTRUE )\r
+ {\r
+ traceTASK_RESUME_FROM_ISR( pxTCB );\r
+\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+ else\r
+ {\r
+ /* We cannot access the delayed or ready lists, so will hold this\r
+ task pending until the scheduler is resumed, at which point a\r
+ yield will be performed if necessary. */\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\r
+ }\r
+ }\r
+\r
+ return xYieldRequired;\r
+ }\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC SCHEDULER CONTROL documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+void vTaskStartScheduler( void )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ /* Add the idle task at the lowest priority. */\r
+ #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+ {\r
+ /* Create the idle task, storing its handle in xIdleTaskHandle so it can\r
+ be returned by the xTaskGetIdleTaskHandle() function. */\r
+ xReturn = xTaskCreate( prvIdleTask, ( signed char * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &xIdleTaskHandle );\r
+ }\r
+ #else\r
+ {\r
+ /* Create the idle task without storing its handle. */\r
+ xReturn = xTaskCreate( prvIdleTask, ( signed char * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL );\r
+ }\r
+ #endif\r
+\r
+ #if ( configUSE_TIMERS == 1 )\r
+ {\r
+ if( xReturn == pdPASS )\r
+ {\r
+ xReturn = xTimerCreateTimerTask();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ if( xReturn == pdPASS )\r
+ {\r
+ /* Interrupts are turned off here, to ensure a tick does not occur\r
+ before or during the call to xPortStartScheduler(). The stacks of\r
+ the created tasks contain a status word with interrupts switched on\r
+ so interrupts will automatically get re-enabled when the first task\r
+ starts to run.\r
+\r
+ STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE\r
+ DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ xSchedulerRunning = pdTRUE;\r
+ xTickCount = ( portTickType ) 0U;\r
+\r
+ /* If configGENERATE_RUN_TIME_STATS is defined then the following\r
+ macro must be defined to configure the timer/counter used to generate\r
+ the run time counter time base. */\r
+ portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();\r
+ \r
+ /* Setting up the timer tick is hardware specific and thus in the\r
+ portable interface. */\r
+ if( xPortStartScheduler() != pdFALSE )\r
+ {\r
+ /* Should not reach here as if the scheduler is running the\r
+ function will not return. */\r
+ }\r
+ else\r
+ {\r
+ /* Should only reach here if a task calls xTaskEndScheduler(). */\r
+ }\r
+ }\r
+\r
+ /* This line will only be reached if the kernel could not be started. */\r
+ configASSERT( xReturn );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskEndScheduler( void )\r
+{\r
+ /* Stop the scheduler interrupts and call the portable scheduler end\r
+ routine so the original ISRs can be restored if necessary. The port\r
+ layer must ensure interrupts enable bit is left in the correct state. */\r
+ portDISABLE_INTERRUPTS();\r
+ xSchedulerRunning = pdFALSE;\r
+ vPortEndScheduler();\r
+}\r
+/*----------------------------------------------------------*/\r
+\r
+void vTaskSuspendAll( void )\r
+{\r
+ /* A critical section is not required as the variable is of type\r
+ portBASE_TYPE. */\r
+ ++uxSchedulerSuspended;\r
+}\r
+/*----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskResumeAll( void )\r
+{\r
+register tskTCB *pxTCB;\r
+signed portBASE_TYPE xAlreadyYielded = pdFALSE;\r
+\r
+ /* If uxSchedulerSuspended is zero then this function does not match a\r
+ previous call to vTaskSuspendAll(). */\r
+ configASSERT( uxSchedulerSuspended );\r
+\r
+ /* It is possible that an ISR caused a task to be removed from an event\r
+ list while the scheduler was suspended. If this was the case then the\r
+ removed task will have been added to the xPendingReadyList. Once the\r
+ scheduler has been resumed it is safe to move all the pending ready\r
+ tasks from this list into their appropriate ready list. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ --uxSchedulerSuspended;\r
+\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ portBASE_TYPE xYieldRequired = pdFALSE;\r
+\r
+ /* Move any readied tasks from the pending list into the\r
+ appropriate ready list. */\r
+ while( listLIST_IS_EMPTY( ( xList * ) &xPendingReadyList ) == pdFALSE )\r
+ {\r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) );\r
+ vListRemove( &( pxTCB->xEventListItem ) );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+\r
+ /* If we have moved a task that has a priority higher than\r
+ the current task then we should yield. */\r
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+ {\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ }\r
+\r
+ /* If any ticks occurred while the scheduler was suspended then\r
+ they should be processed now. This ensures the tick count does not\r
+ slip, and that any delayed tasks are resumed at the correct time. */\r
+ if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ vTaskIncrementTick();\r
+ --uxMissedTicks;\r
+ }\r
+\r
+ /* As we have processed some ticks it is appropriate to yield\r
+ to ensure the highest priority task that is ready to run is\r
+ the task actually running. */\r
+ #if configUSE_PREEMPTION == 1\r
+ {\r
+ xYieldRequired = pdTRUE;\r
+ }\r
+ #endif\r
+ }\r
+\r
+ if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) )\r
+ {\r
+ xAlreadyYielded = pdTRUE;\r
+ xMissedYield = pdFALSE;\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xAlreadyYielded;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * PUBLIC TASK UTILITIES documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+\r
+portTickType xTaskGetTickCount( void )\r
+{\r
+portTickType xTicks;\r
+\r
+ /* Critical section required if running on a 16 bit processor. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ xTicks = xTickCount;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xTicks;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portTickType xTaskGetTickCountFromISR( void )\r
+{\r
+portTickType xReturn;\r
+unsigned portBASE_TYPE uxSavedInterruptStatus;\r
+\r
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\r
+ xReturn = xTickCount;\r
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void )\r
+{\r
+ /* A critical section is not required because the variables are of type\r
+ portBASE_TYPE. */\r
+ return uxCurrentNumberOfTasks;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_pcTaskGetTaskName == 1 )\r
+\r
+ signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ /* If null is passed in here then the name of the calling task is being queried. */\r
+ pxTCB = prvGetTCBFromHandle( xTaskToQuery );\r
+ configASSERT( pxTCB );\r
+ return &( pxTCB->pcTaskName[ 0 ] );\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ void vTaskList( signed char *pcWriteBuffer )\r
+ {\r
+ unsigned portBASE_TYPE uxQueue;\r
+\r
+ /* This is a VERY costly function that should be used for debug only.\r
+ It leaves interrupts disabled for a LONG time. */\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Run through all the lists that could potentially contain a TCB and\r
+ report the task name, state and stack high water mark. */\r
+\r
+ *pcWriteBuffer = ( signed char ) 0x00;\r
+ strcat( ( char * ) pcWriteBuffer, ( const char * ) "\r\n" );\r
+\r
+ uxQueue = uxTopUsedPriority + ( unsigned portBASE_TYPE ) 1U;\r
+\r
+ do\r
+ {\r
+ uxQueue--;\r
+\r
+ if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR );\r
+ }\r
+ }while( uxQueue > ( unsigned short ) tskIDLE_PRIORITY );\r
+\r
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR );\r
+ }\r
+\r
+ if( listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR );\r
+ }\r
+\r
+ #if( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ if( listLIST_IS_EMPTY( &xTasksWaitingTermination ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, &xTasksWaitingTermination, tskDELETED_CHAR );\r
+ }\r
+ }\r
+ #endif\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ if( listLIST_IS_EMPTY( &xSuspendedTaskList ) == pdFALSE )\r
+ {\r
+ prvListTaskWithinSingleList( pcWriteBuffer, &xSuspendedTaskList, tskSUSPENDED_CHAR );\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+\r
+#endif\r
+/*----------------------------------------------------------*/\r
+\r
+#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+\r
+ void vTaskGetRunTimeStats( signed char *pcWriteBuffer )\r
+ {\r
+ unsigned portBASE_TYPE uxQueue;\r
+ unsigned long ulTotalRunTime;\r
+\r
+ /* This is a VERY costly function that should be used for debug only.\r
+ It leaves interrupts disabled for a LONG time. */\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\r
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );\r
+ #else\r
+ ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\r
+ #endif\r
+\r
+ /* Divide ulTotalRunTime by 100 to make the percentage caluclations\r
+ simpler in the prvGenerateRunTimeStatsForTasksInList() function. */\r
+ ulTotalRunTime /= 100UL;\r
+ \r
+ /* Run through all the lists that could potentially contain a TCB,\r
+ generating a table of run timer percentages in the provided\r
+ buffer. */\r
+\r
+ *pcWriteBuffer = ( signed char ) 0x00;\r
+ strcat( ( char * ) pcWriteBuffer, ( const char * ) "\r\n" );\r
+\r
+ uxQueue = uxTopUsedPriority + ( unsigned portBASE_TYPE ) 1U;\r
+\r
+ do\r
+ {\r
+ uxQueue--;\r
+\r
+ if( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), ulTotalRunTime );\r
+ }\r
+ }while( uxQueue > ( unsigned short ) tskIDLE_PRIORITY );\r
+\r
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, ulTotalRunTime );\r
+ }\r
+\r
+ if( listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, ulTotalRunTime );\r
+ }\r
+\r
+ #if ( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ if( listLIST_IS_EMPTY( &xTasksWaitingTermination ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, &xTasksWaitingTermination, ulTotalRunTime );\r
+ }\r
+ }\r
+ #endif\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ if( listLIST_IS_EMPTY( &xSuspendedTaskList ) == pdFALSE )\r
+ {\r
+ prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, &xSuspendedTaskList, ulTotalRunTime );\r
+ }\r
+ }\r
+ #endif\r
+ }\r
+ xTaskResumeAll();\r
+ }\r
+\r
+#endif\r
+/*----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ void vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize )\r
+ {\r
+ configASSERT( pcBuffer );\r
+ configASSERT( ulBufferSize );\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ pcTraceBuffer = ( signed char * )pcBuffer;\r
+ pcTraceBufferStart = pcBuffer;\r
+ pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE );\r
+ xTracing = pdTRUE;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+ }\r
+\r
+#endif\r
+/*----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ unsigned long ulTaskEndTrace( void )\r
+ {\r
+ unsigned long ulBufferLength;\r
+\r
+ taskENTER_CRITICAL();\r
+ xTracing = pdFALSE;\r
+ taskEXIT_CRITICAL();\r
+\r
+ ulBufferLength = ( unsigned long ) ( pcTraceBuffer - pcTraceBufferStart );\r
+\r
+ return ulBufferLength;\r
+ }\r
+\r
+#endif\r
+/*----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
+\r
+ xTaskHandle xTaskGetIdleTaskHandle( void )\r
+ {\r
+ /* If xTaskGetIdleTaskHandle() is called before the scheduler has been\r
+ started, then xIdleTaskHandle will be NULL. */\r
+ configASSERT( ( xIdleTaskHandle != NULL ) );\r
+ return xIdleTaskHandle;\r
+ }\r
+ \r
+#endif\r
+\r
+/*-----------------------------------------------------------\r
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\r
+ * documented in task.h\r
+ *----------------------------------------------------------*/\r
+\r
+void vTaskIncrementTick( void )\r
+{\r
+tskTCB * pxTCB;\r
+\r
+ /* Called by the portable layer each time a tick interrupt occurs.\r
+ Increments the tick then checks to see if the new tick value will cause any\r
+ tasks to be unblocked. */\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ ++xTickCount;\r
+ if( xTickCount == ( portTickType ) 0U )\r
+ {\r
+ xList *pxTemp;\r
+\r
+ /* Tick count has overflowed so we need to swap the delay lists.\r
+ If there are any items in pxDelayedTaskList here then there is\r
+ an error! */\r
+ configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );\r
+ \r
+ pxTemp = pxDelayedTaskList;\r
+ pxDelayedTaskList = pxOverflowDelayedTaskList;\r
+ pxOverflowDelayedTaskList = pxTemp;\r
+ xNumOfOverflows++;\r
+ \r
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\r
+ {\r
+ /* The new current delayed list is empty. Set\r
+ xNextTaskUnblockTime to the maximum possible value so it is\r
+ extremely unlikely that the \r
+ if( xTickCount >= xNextTaskUnblockTime ) test will pass until\r
+ there is an item in the delayed list. */\r
+ xNextTaskUnblockTime = portMAX_DELAY;\r
+ }\r
+ else\r
+ {\r
+ /* The new current delayed list is not empty, get the value of\r
+ the item at the head of the delayed list. This is the time at\r
+ which the task at the head of the delayed list should be removed\r
+ from the Blocked state. */\r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );\r
+ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );\r
+ }\r
+ }\r
+\r
+ /* See if this tick has made a timeout expire. */\r
+ prvCheckDelayedTasks();\r
+ }\r
+ else\r
+ {\r
+ ++uxMissedTicks;\r
+\r
+ /* The tick hook gets called at regular intervals, even if the\r
+ scheduler is locked. */\r
+ #if ( configUSE_TICK_HOOK == 1 )\r
+ {\r
+ vApplicationTickHook();\r
+ }\r
+ #endif\r
+ }\r
+\r
+ #if ( configUSE_TICK_HOOK == 1 )\r
+ {\r
+ /* Guard against the tick hook being called when the missed tick\r
+ count is being unwound (when the scheduler is being unlocked. */\r
+ if( uxMissedTicks == ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ vApplicationTickHook();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ traceTASK_INCREMENT_TICK( xTickCount );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+\r
+ void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction )\r
+ {\r
+ tskTCB *xTCB;\r
+\r
+ /* If xTask is NULL then we are setting our own task hook. */\r
+ if( xTask == NULL )\r
+ {\r
+ xTCB = ( tskTCB * ) pxCurrentTCB;\r
+ }\r
+ else\r
+ {\r
+ xTCB = ( tskTCB * ) xTask;\r
+ }\r
+\r
+ /* Save the hook function in the TCB. A critical section is required as\r
+ the value can be accessed from an interrupt. */\r
+ taskENTER_CRITICAL();\r
+ xTCB->pxTaskTag = pxHookFunction;\r
+ taskEXIT_CRITICAL();\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+\r
+ pdTASK_HOOK_CODE xTaskGetApplicationTaskTag( xTaskHandle xTask )\r
+ {\r
+ tskTCB *xTCB;\r
+ pdTASK_HOOK_CODE xReturn;\r
+\r
+ /* If xTask is NULL then we are setting our own task hook. */\r
+ if( xTask == NULL )\r
+ {\r
+ xTCB = ( tskTCB * ) pxCurrentTCB;\r
+ }\r
+ else\r
+ {\r
+ xTCB = ( tskTCB * ) xTask;\r
+ }\r
+\r
+ /* Save the hook function in the TCB. A critical section is required as\r
+ the value can be accessed from an interrupt. */\r
+ taskENTER_CRITICAL();\r
+ xReturn = xTCB->pxTaskTag;\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+\r
+ portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )\r
+ {\r
+ tskTCB *xTCB;\r
+ portBASE_TYPE xReturn;\r
+\r
+ /* If xTask is NULL then we are calling our own task hook. */\r
+ if( xTask == NULL )\r
+ {\r
+ xTCB = ( tskTCB * ) pxCurrentTCB;\r
+ }\r
+ else\r
+ {\r
+ xTCB = ( tskTCB * ) xTask;\r
+ }\r
+\r
+ if( xTCB->pxTaskTag != NULL )\r
+ {\r
+ xReturn = xTCB->pxTaskTag( pvParameter );\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFAIL;\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskSwitchContext( void )\r
+{\r
+ if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ /* The scheduler is currently suspended - do not allow a context\r
+ switch. */\r
+ xMissedYield = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ traceTASK_SWITCHED_OUT();\r
+ \r
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+ {\r
+ unsigned long ulTempCounter;\r
+ \r
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\r
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTempCounter );\r
+ #else\r
+ ulTempCounter = portGET_RUN_TIME_COUNTER_VALUE();\r
+ #endif\r
+ \r
+ /* Add the amount of time the task has been running to the accumulated\r
+ time so far. The time the task started running was stored in\r
+ ulTaskSwitchedInTime. Note that there is no overflow protection here\r
+ so count values are only valid until the timer overflows. Generally\r
+ this will be about 1 hour assuming a 1uS timer increment. */\r
+ pxCurrentTCB->ulRunTimeCounter += ( ulTempCounter - ulTaskSwitchedInTime );\r
+ ulTaskSwitchedInTime = ulTempCounter;\r
+ }\r
+ #endif\r
+ \r
+ taskFIRST_CHECK_FOR_STACK_OVERFLOW();\r
+ taskSECOND_CHECK_FOR_STACK_OVERFLOW();\r
+ \r
+ /* Find the highest priority queue that contains ready tasks. */\r
+ while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) )\r
+ {\r
+ configASSERT( uxTopReadyPriority );\r
+ --uxTopReadyPriority;\r
+ }\r
+ \r
+ /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the\r
+ same priority get an equal share of the processor time. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) );\r
+ \r
+ traceTASK_SWITCHED_IN();\r
+ vWriteTraceToBuffer();\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait )\r
+{\r
+portTickType xTimeToWake;\r
+\r
+ configASSERT( pxEventList );\r
+\r
+ /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE\r
+ SCHEDULER SUSPENDED. */\r
+\r
+ /* Place the event list item of the TCB in the appropriate event list.\r
+ This is placed in the list in priority order so the highest priority task\r
+ is the first to be woken by the event. */\r
+ vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) );\r
+\r
+ /* We must remove ourselves from the ready list before adding ourselves\r
+ to the blocked list as the same list item is used for both lists. We have\r
+ exclusive access to the ready lists as the scheduler is locked. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ if( xTicksToWait == portMAX_DELAY )\r
+ {\r
+ /* Add ourselves to the suspended task list instead of a delayed task\r
+ list to ensure we are not woken by a timing event. We will block\r
+ indefinitely. */\r
+ vListInsertEnd( ( xList * ) &xSuspendedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* Calculate the time at which the task should be woken if the event does\r
+ not occur. This may overflow but this doesn't matter. */\r
+ xTimeToWake = xTickCount + xTicksToWait;\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ }\r
+ #else\r
+ {\r
+ /* Calculate the time at which the task should be woken if the event does\r
+ not occur. This may overflow but this doesn't matter. */\r
+ xTimeToWake = xTickCount + xTicksToWait;\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if configUSE_TIMERS == 1\r
+\r
+ void vTaskPlaceOnEventListRestricted( const xList * const pxEventList, portTickType xTicksToWait )\r
+ {\r
+ portTickType xTimeToWake;\r
+\r
+ configASSERT( pxEventList );\r
+\r
+ /* This function should not be called by application code hence the\r
+ 'Restricted' in its name. It is not part of the public API. It is\r
+ designed for use by kernel code, and has special calling requirements -\r
+ it should be called from a critical section. */\r
+\r
+ \r
+ /* Place the event list item of the TCB in the appropriate event list.\r
+ In this case it is assume that this is the only task that is going to\r
+ be waiting on this event list, so the faster vListInsertEnd() function\r
+ can be used in place of vListInsert. */\r
+ vListInsertEnd( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) );\r
+\r
+ /* We must remove this task from the ready list before adding it to the\r
+ blocked list as the same list item is used for both lists. This\r
+ function is called form a critical section. */\r
+ vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+ /* Calculate the time at which the task should be woken if the event does\r
+ not occur. This may overflow but this doesn't matter. */\r
+ xTimeToWake = xTickCount + xTicksToWait;\r
+ prvAddCurrentTaskToDelayedList( xTimeToWake );\r
+ }\r
+ \r
+#endif /* configUSE_TIMERS */\r
+/*-----------------------------------------------------------*/\r
+\r
+signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList )\r
+{\r
+tskTCB *pxUnblockedTCB;\r
+portBASE_TYPE xReturn;\r
+\r
+ /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE\r
+ SCHEDULER SUSPENDED. It can also be called from within an ISR. */\r
+\r
+ /* The event list is sorted in priority order, so we can remove the\r
+ first in the list, remove the TCB from the delayed list, and add\r
+ it to the ready list.\r
+\r
+ If an event is for a queue that is locked then this function will never\r
+ get called - the lock count on the queue will get modified instead. This\r
+ means we can always expect exclusive access to the event list here.\r
+ \r
+ This function assumes that a check has already been made to ensure that\r
+ pxEventList is not empty. */\r
+ pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\r
+ configASSERT( pxUnblockedTCB );\r
+ vListRemove( &( pxUnblockedTCB->xEventListItem ) );\r
+\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ vListRemove( &( pxUnblockedTCB->xGenericListItem ) );\r
+ prvAddTaskToReadyQueue( pxUnblockedTCB );\r
+ }\r
+ else\r
+ {\r
+ /* We cannot access the delayed or ready lists, so will hold this\r
+ task pending until the scheduler is resumed. */\r
+ vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\r
+ }\r
+\r
+ if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority )\r
+ {\r
+ /* Return true if the task removed from the event list has\r
+ a higher priority than the calling task. This allows\r
+ the calling task to know if it should force a context\r
+ switch now. */\r
+ xReturn = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut )\r
+{\r
+ configASSERT( pxTimeOut );\r
+ pxTimeOut->xOverflowCount = xNumOfOverflows;\r
+ pxTimeOut->xTimeOnEntering = xTickCount;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait )\r
+{\r
+portBASE_TYPE xReturn;\r
+\r
+ configASSERT( pxTimeOut );\r
+ configASSERT( pxTicksToWait );\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is\r
+ the maximum block time then the task should block indefinitely, and\r
+ therefore never time out. */\r
+ if( *pxTicksToWait == portMAX_DELAY )\r
+ {\r
+ xReturn = pdFALSE;\r
+ }\r
+ else /* We are not blocking indefinitely, perform the checks below. */\r
+ #endif\r
+\r
+ if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( ( portTickType ) xTickCount >= ( portTickType ) pxTimeOut->xTimeOnEntering ) )\r
+ {\r
+ /* The tick count is greater than the time at which vTaskSetTimeout()\r
+ was called, but has also overflowed since vTaskSetTimeOut() was called.\r
+ It must have wrapped all the way around and gone past us again. This\r
+ passed since vTaskSetTimeout() was called. */\r
+ xReturn = pdTRUE;\r
+ }\r
+ else if( ( ( portTickType ) ( ( portTickType ) xTickCount - ( portTickType ) pxTimeOut->xTimeOnEntering ) ) < ( portTickType ) *pxTicksToWait )\r
+ {\r
+ /* Not a genuine timeout. Adjust parameters for time remaining. */\r
+ *pxTicksToWait -= ( ( portTickType ) xTickCount - ( portTickType ) pxTimeOut->xTimeOnEntering );\r
+ vTaskSetTimeOutState( pxTimeOut );\r
+ xReturn = pdFALSE;\r
+ }\r
+ else\r
+ {\r
+ xReturn = pdTRUE;\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vTaskMissedYield( void )\r
+{\r
+ xMissedYield = pdTRUE;\r
+}\r
+\r
+/*\r
+ * -----------------------------------------------------------\r
+ * The Idle task.\r
+ * ----------------------------------------------------------\r
+ *\r
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific\r
+ * language extensions. The equivalent prototype for this function is:\r
+ *\r
+ * void prvIdleTask( void *pvParameters );\r
+ *\r
+ */\r
+static portTASK_FUNCTION( prvIdleTask, pvParameters )\r
+{\r
+ /* Stop warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* See if any tasks have been deleted. */\r
+ prvCheckTasksWaitingTermination();\r
+\r
+ #if ( configUSE_PREEMPTION == 0 )\r
+ {\r
+ /* If we are not using preemption we keep forcing a task switch to\r
+ see if any other task has become available. If we are using\r
+ preemption we don't need to do this as any task becoming available\r
+ will automatically get the processor anyway. */\r
+ taskYIELD();\r
+ }\r
+ #endif\r
+\r
+ #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )\r
+ {\r
+ /* When using preemption tasks of equal priority will be\r
+ timesliced. If a task that is sharing the idle priority is ready\r
+ to run then the idle task should yield before the end of the\r
+ timeslice.\r
+\r
+ A critical region is not required here as we are just reading from\r
+ the list, and an occasional incorrect value will not matter. If\r
+ the ready list at the idle priority contains more than one task\r
+ then a task other than the idle task is ready to execute. */\r
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 )\r
+ {\r
+ taskYIELD();\r
+ }\r
+ }\r
+ #endif\r
+\r
+ #if ( configUSE_IDLE_HOOK == 1 )\r
+ {\r
+ extern void vApplicationIdleHook( void );\r
+\r
+ /* Call the user defined function from within the idle task. This\r
+ allows the application designer to add background functionality\r
+ without the overhead of a separate task.\r
+ NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,\r
+ CALL A FUNCTION THAT MIGHT BLOCK. */\r
+ vApplicationIdleHook();\r
+ }\r
+ #endif\r
+ }\r
+} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*-----------------------------------------------------------\r
+ * File private functions documented at the top of the file.\r
+ *----------------------------------------------------------*/\r
+\r
+\r
+\r
+static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed char * const pcName, unsigned portBASE_TYPE uxPriority, const xMemoryRegion * const xRegions, unsigned short usStackDepth )\r
+{\r
+ /* Store the function name in the TCB. */\r
+ #if configMAX_TASK_NAME_LEN > 1\r
+ {\r
+ /* Don't bring strncpy into the build unnecessarily. */\r
+ strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned short ) configMAX_TASK_NAME_LEN );\r
+ }\r
+ #endif\r
+ pxTCB->pcTaskName[ ( unsigned short ) configMAX_TASK_NAME_LEN - ( unsigned short ) 1 ] = ( signed char ) '\0';\r
+\r
+ /* This is used as an array index so must ensure it's not too large. First\r
+ remove the privilege bit if one is present. */\r
+ if( uxPriority >= configMAX_PRIORITIES )\r
+ {\r
+ uxPriority = configMAX_PRIORITIES - ( unsigned portBASE_TYPE ) 1U;\r
+ }\r
+\r
+ pxTCB->uxPriority = uxPriority;\r
+ #if ( configUSE_MUTEXES == 1 )\r
+ {\r
+ pxTCB->uxBasePriority = uxPriority;\r
+ }\r
+ #endif\r
+\r
+ vListInitialiseItem( &( pxTCB->xGenericListItem ) );\r
+ vListInitialiseItem( &( pxTCB->xEventListItem ) );\r
+\r
+ /* Set the pxTCB as a link back from the xListItem. This is so we can get\r
+ back to the containing TCB from a generic item in a list. */\r
+ listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );\r
+\r
+ /* Event lists are always in priority order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority );\r
+ listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );\r
+\r
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+ {\r
+ pxTCB->uxCriticalNesting = ( unsigned portBASE_TYPE ) 0U;\r
+ }\r
+ #endif\r
+\r
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
+ {\r
+ pxTCB->pxTaskTag = NULL;\r
+ }\r
+ #endif\r
+\r
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+ {\r
+ pxTCB->ulRunTimeCounter = 0UL;\r
+ }\r
+ #endif\r
+\r
+ #if ( portUSING_MPU_WRAPPERS == 1 )\r
+ {\r
+ vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth );\r
+ }\r
+ #else\r
+ {\r
+ ( void ) xRegions;\r
+ ( void ) usStackDepth;\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( portUSING_MPU_WRAPPERS == 1 )\r
+\r
+ void vTaskAllocateMPURegions( xTaskHandle xTaskToModify, const xMemoryRegion * const xRegions )\r
+ {\r
+ tskTCB *pxTCB;\r
+ \r
+ if( xTaskToModify == pxCurrentTCB )\r
+ {\r
+ xTaskToModify = NULL;\r
+ }\r
+\r
+ /* If null is passed in here then we are deleting ourselves. */\r
+ pxTCB = prvGetTCBFromHandle( xTaskToModify );\r
+\r
+ vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );\r
+ }\r
+ /*-----------------------------------------------------------*/\r
+#endif\r
+\r
+static void prvInitialiseTaskLists( void )\r
+{\r
+unsigned portBASE_TYPE uxPriority;\r
+\r
+ for( uxPriority = ( unsigned portBASE_TYPE ) 0U; uxPriority < configMAX_PRIORITIES; uxPriority++ )\r
+ {\r
+ vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) );\r
+ }\r
+\r
+ vListInitialise( ( xList * ) &xDelayedTaskList1 );\r
+ vListInitialise( ( xList * ) &xDelayedTaskList2 );\r
+ vListInitialise( ( xList * ) &xPendingReadyList );\r
+\r
+ #if ( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ vListInitialise( ( xList * ) &xTasksWaitingTermination );\r
+ }\r
+ #endif\r
+\r
+ #if ( INCLUDE_vTaskSuspend == 1 )\r
+ {\r
+ vListInitialise( ( xList * ) &xSuspendedTaskList );\r
+ }\r
+ #endif\r
+\r
+ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\r
+ using list2. */\r
+ pxDelayedTaskList = &xDelayedTaskList1;\r
+ pxOverflowDelayedTaskList = &xDelayedTaskList2;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckTasksWaitingTermination( void )\r
+{\r
+ #if ( INCLUDE_vTaskDelete == 1 )\r
+ {\r
+ portBASE_TYPE xListIsEmpty;\r
+\r
+ /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called\r
+ too often in the idle task. */\r
+ if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0U )\r
+ {\r
+ vTaskSuspendAll();\r
+ xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );\r
+ xTaskResumeAll();\r
+\r
+ if( xListIsEmpty == pdFALSE )\r
+ {\r
+ tskTCB *pxTCB;\r
+\r
+ taskENTER_CRITICAL();\r
+ {\r
+ pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) );\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+ --uxCurrentNumberOfTasks;\r
+ --uxTasksDeleted;\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ prvDeleteTCB( pxTCB );\r
+ }\r
+ }\r
+ }\r
+ #endif\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvAddCurrentTaskToDelayedList( portTickType xTimeToWake )\r
+{\r
+ /* The list item will be inserted in wake time order. */\r
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );\r
+\r
+ if( xTimeToWake < xTickCount )\r
+ {\r
+ /* Wake time has overflowed. Place this item in the overflow list. */\r
+ vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+ }\r
+ else\r
+ {\r
+ /* The wake time has not overflowed, so we can use the current block list. */\r
+ vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) );\r
+\r
+ /* If the task entering the blocked state was placed at the head of the\r
+ list of blocked tasks then xNextTaskUnblockTime needs to be updated\r
+ too. */\r
+ if( xTimeToWake < xNextTaskUnblockTime )\r
+ {\r
+ xNextTaskUnblockTime = xTimeToWake;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static tskTCB *prvAllocateTCBAndStack( unsigned short usStackDepth, portSTACK_TYPE *puxStackBuffer )\r
+{\r
+tskTCB *pxNewTCB;\r
+\r
+ /* Allocate space for the TCB. Where the memory comes from depends on\r
+ the implementation of the port malloc function. */\r
+ pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) );\r
+\r
+ if( pxNewTCB != NULL )\r
+ {\r
+ /* Allocate space for the stack used by the task being created.\r
+ The base of the stack memory stored in the TCB so the task can\r
+ be deleted later if required. */\r
+ pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMallocAligned( ( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ), puxStackBuffer );\r
+\r
+ if( pxNewTCB->pxStack == NULL )\r
+ {\r
+ /* Could not allocate the stack. Delete the allocated TCB. */\r
+ vPortFree( pxNewTCB );\r
+ pxNewTCB = NULL;\r
+ }\r
+ else\r
+ {\r
+ /* Just to help debugging. */\r
+ memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( portSTACK_TYPE ) );\r
+ }\r
+ }\r
+\r
+ return pxNewTCB;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_TRACE_FACILITY == 1 )\r
+\r
+ static void prvListTaskWithinSingleList( const signed char *pcWriteBuffer, xList *pxList, signed char cStatus )\r
+ {\r
+ volatile tskTCB *pxNextTCB, *pxFirstTCB;\r
+ unsigned short usStackRemaining;\r
+\r
+ /* Write the details of all the TCB's in pxList into the buffer. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );\r
+ do\r
+ {\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );\r
+ #if ( portSTACK_GROWTH > 0 )\r
+ {\r
+ usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned char * ) pxNextTCB->pxEndOfStack );\r
+ }\r
+ #else\r
+ {\r
+ usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned char * ) pxNextTCB->pxStack );\r
+ }\r
+ #endif \r
+ \r
+ sprintf( pcStatusString, ( char * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber );\r
+ strcat( ( char * ) pcWriteBuffer, ( char * ) pcStatusString );\r
+\r
+ } while( pxNextTCB != pxFirstTCB );\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configGENERATE_RUN_TIME_STATS == 1 )\r
+\r
+ static void prvGenerateRunTimeStatsForTasksInList( const signed char *pcWriteBuffer, xList *pxList, unsigned long ulTotalRunTime )\r
+ {\r
+ volatile tskTCB *pxNextTCB, *pxFirstTCB;\r
+ unsigned long ulStatsAsPercentage;\r
+\r
+ /* Write the run time stats of all the TCB's in pxList into the buffer. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );\r
+ do\r
+ {\r
+ /* Get next TCB in from the list. */\r
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );\r
+\r
+ /* Divide by zero check. */\r
+ if( ulTotalRunTime > 0UL )\r
+ {\r
+ /* Has the task run at all? */\r
+ if( pxNextTCB->ulRunTimeCounter == 0UL )\r
+ {\r
+ /* The task has used no CPU time at all. */\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t0\t\t0%%\r\n", pxNextTCB->pcTaskName );\r
+ }\r
+ else\r
+ {\r
+ /* What percentage of the total run time has the task used?\r
+ This will always be rounded down to the nearest integer.\r
+ ulTotalRunTime has already been divided by 100. */\r
+ ulStatsAsPercentage = pxNextTCB->ulRunTimeCounter / ulTotalRunTime;\r
+\r
+ if( ulStatsAsPercentage > 0UL )\r
+ {\r
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED\r
+ {\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t%lu\t\t%lu%%\r\n", pxNextTCB->pcTaskName, pxNextTCB->ulRunTimeCounter, ulStatsAsPercentage ); \r
+ }\r
+ #else\r
+ {\r
+ /* sizeof( int ) == sizeof( long ) so a smaller\r
+ printf() library can be used. */\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t%u\t\t%u%%\r\n", pxNextTCB->pcTaskName, ( unsigned int ) pxNextTCB->ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );\r
+ }\r
+ #endif\r
+ }\r
+ else\r
+ {\r
+ /* If the percentage is zero here then the task has\r
+ consumed less than 1% of the total run time. */\r
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED\r
+ {\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t%lu\t\t<1%%\r\n", pxNextTCB->pcTaskName, pxNextTCB->ulRunTimeCounter ); \r
+ }\r
+ #else\r
+ {\r
+ /* sizeof( int ) == sizeof( long ) so a smaller\r
+ printf() library can be used. */\r
+ sprintf( pcStatsString, ( char * ) "%s\t\t%u\t\t<1%%\r\n", pxNextTCB->pcTaskName, ( unsigned int ) pxNextTCB->ulRunTimeCounter );\r
+ }\r
+ #endif\r
+ }\r
+ }\r
+\r
+ strcat( ( char * ) pcWriteBuffer, ( char * ) pcStatsString );\r
+ }\r
+\r
+ } while( pxNextTCB != pxFirstTCB );\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )\r
+\r
+ static unsigned short usTaskCheckFreeStackSpace( const unsigned char * pucStackByte )\r
+ {\r
+ register unsigned short usCount = 0U;\r
+\r
+ while( *pucStackByte == tskSTACK_FILL_BYTE )\r
+ {\r
+ pucStackByte -= portSTACK_GROWTH;\r
+ usCount++;\r
+ }\r
+\r
+ usCount /= sizeof( portSTACK_TYPE );\r
+\r
+ return usCount;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
+\r
+ unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask )\r
+ {\r
+ tskTCB *pxTCB;\r
+ unsigned char *pcEndOfStack;\r
+ unsigned portBASE_TYPE uxReturn;\r
+\r
+ pxTCB = prvGetTCBFromHandle( xTask );\r
+\r
+ #if portSTACK_GROWTH < 0\r
+ {\r
+ pcEndOfStack = ( unsigned char * ) pxTCB->pxStack;\r
+ }\r
+ #else\r
+ {\r
+ pcEndOfStack = ( unsigned char * ) pxTCB->pxEndOfStack;\r
+ }\r
+ #endif\r
+\r
+ uxReturn = ( unsigned portBASE_TYPE ) usTaskCheckFreeStackSpace( pcEndOfStack );\r
+\r
+ return uxReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_vTaskDelete == 1 )\r
+\r
+ static void prvDeleteTCB( tskTCB *pxTCB )\r
+ {\r
+ /* Free up the memory allocated by the scheduler for the task. It is up to\r
+ the task to free any memory allocated at the application level. */\r
+ vPortFreeAligned( pxTCB->pxStack );\r
+ vPortFree( pxTCB );\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\r
+\r
+ xTaskHandle xTaskGetCurrentTaskHandle( void )\r
+ {\r
+ xTaskHandle xReturn;\r
+\r
+ /* A critical section is not required as this is not called from\r
+ an interrupt and the current TCB will always be the same for any\r
+ individual execution thread. */\r
+ xReturn = pxCurrentTCB;\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\r
+\r
+ portBASE_TYPE xTaskGetSchedulerState( void )\r
+ {\r
+ portBASE_TYPE xReturn;\r
+\r
+ if( xSchedulerRunning == pdFALSE )\r
+ {\r
+ xReturn = taskSCHEDULER_NOT_STARTED;\r
+ }\r
+ else\r
+ {\r
+ if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE )\r
+ {\r
+ xReturn = taskSCHEDULER_RUNNING;\r
+ }\r
+ else\r
+ {\r
+ xReturn = taskSCHEDULER_SUSPENDED;\r
+ }\r
+ }\r
+\r
+ return xReturn;\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_MUTEXES == 1 )\r
+\r
+ void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder )\r
+ {\r
+ tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder;\r
+\r
+ configASSERT( pxMutexHolder );\r
+\r
+ if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )\r
+ {\r
+ /* Adjust the mutex holder state to account for its new priority. */\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxCurrentTCB->uxPriority );\r
+\r
+ /* If the task being modified is in the ready state it will need to\r
+ be moved in to a new list. */\r
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )\r
+ {\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Inherit the priority before being moved into the new list. */\r
+ pxTCB->uxPriority = pxCurrentTCB->uxPriority;\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+ else\r
+ {\r
+ /* Just inherit the priority. */\r
+ pxTCB->uxPriority = pxCurrentTCB->uxPriority;\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( configUSE_MUTEXES == 1 )\r
+\r
+ void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder )\r
+ {\r
+ tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder;\r
+\r
+ if( pxMutexHolder != NULL )\r
+ {\r
+ if( pxTCB->uxPriority != pxTCB->uxBasePriority )\r
+ {\r
+ /* We must be the running task to be able to give the mutex back.\r
+ Remove ourselves from the ready list we currently appear in. */\r
+ vListRemove( &( pxTCB->xGenericListItem ) );\r
+\r
+ /* Disinherit the priority before adding ourselves into the new\r
+ ready list. */\r
+ pxTCB->uxPriority = pxTCB->uxBasePriority;\r
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxTCB->uxPriority );\r
+ prvAddTaskToReadyQueue( pxTCB );\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+\r
+ void vTaskEnterCritical( void )\r
+ {\r
+ portDISABLE_INTERRUPTS();\r
+\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ ( pxCurrentTCB->uxCriticalNesting )++;\r
+ }\r
+ }\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )\r
+\r
+void vTaskExitCritical( void )\r
+{\r
+ if( xSchedulerRunning != pdFALSE )\r
+ {\r
+ if( pxCurrentTCB->uxCriticalNesting > 0U )\r
+ {\r
+ ( pxCurrentTCB->uxCriticalNesting )--;\r
+\r
+ if( pxCurrentTCB->uxCriticalNesting == 0U )\r
+ {\r
+ portENABLE_INTERRUPTS();\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
+\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS tutorial books are available in pdf and paperback. *\r
+ * Complete, revised, and edited pdf reference manuals are also *\r
+ * available. *\r
+ * *\r
+ * Purchasing FreeRTOS documentation will not only help you, by *\r
+ * ensuring you get running as quickly as possible and with an *\r
+ * in-depth knowledge of how to use FreeRTOS, it will also help *\r
+ * the FreeRTOS project to continue with its mission of providing *\r
+ * professional grade, cross platform, de facto standard solutions *\r
+ * for microcontrollers - completely free of charge! *\r
+ * *\r
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *\r
+ * *\r
+ * Thank you for using FreeRTOS, and thank you for your support! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
+ >>>NOTE<<< The modification to the GPL is included to allow you to\r
+ distribute a combined work that includes FreeRTOS without being obliged to\r
+ provide the source code for proprietary components outside of the FreeRTOS\r
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but\r
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
+ more details. You should have received a copy of the GNU General Public\r
+ License and the FreeRTOS license exception along with FreeRTOS; if not it\r
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
+ by writing to Richard Barry, contact details for whom are available on the\r
+ FreeRTOS WEB site.\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ http://www.FreeRTOS.org - Documentation, latest information, license and\r
+ contact details.\r
+\r
+ http://www.SafeRTOS.com - A version that is certified for use in safety\r
+ critical systems.\r
+\r
+ http://www.OpenRTOS.com - Commercial support, development, porting,\r
+ licensing and training services.\r
+*/\r
+\r
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
+all the API functions to use the MPU wrappers. That should only be done when\r
+task.h is included from an application file. */\r
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+#include "FreeRTOS.h"\r
+#include "os_task.h"\r
+#include "os_queue.h"\r
+#include "os_timer.h"\r
+\r
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
+\r
+/* This entire source file will be skipped if the application is not configured\r
+to include software timer functionality. This #if is closed at the very bottom\r
+of this file. If you want to include software timer functionality then ensure\r
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\r
+#if ( configUSE_TIMERS == 1 )\r
+\r
+/* Misc definitions. */\r
+#define tmrNO_DELAY ( portTickType ) 0U\r
+\r
+/* The definition of the timers themselves. */\r
+typedef struct tmrTimerControl\r
+{\r
+ const signed char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */\r
+ xListItem xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */\r
+ portTickType xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */\r
+ unsigned portBASE_TYPE uxAutoReload; /*<< Set to pdTRUE if the timer should be automatically restarted once expired. Set to pdFALSE if the timer is, in effect, a one shot timer. */\r
+ void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */\r
+ tmrTIMER_CALLBACK pxCallbackFunction; /*<< The function that will be called when the timer expires. */\r
+} xTIMER;\r
+\r
+/* The definition of messages that can be sent and received on the timer\r
+queue. */\r
+typedef struct tmrTimerQueueMessage\r
+{\r
+ portBASE_TYPE xMessageID; /*<< The command being sent to the timer service task. */\r
+ portTickType xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */\r
+ xTIMER * pxTimer; /*<< The timer to which the command will be applied. */\r
+} xTIMER_MESSAGE;\r
+\r
+\r
+/* The list in which active timers are stored. Timers are referenced in expire\r
+time order, with the nearest expiry time at the front of the list. Only the\r
+timer service task is allowed to access xActiveTimerList. */\r
+PRIVILEGED_DATA static xList xActiveTimerList1;\r
+PRIVILEGED_DATA static xList xActiveTimerList2;\r
+PRIVILEGED_DATA static xList *pxCurrentTimerList;\r
+PRIVILEGED_DATA static xList *pxOverflowTimerList;\r
+\r
+/* A queue that is used to send commands to the timer service task. */\r
+PRIVILEGED_DATA static xQueueHandle xTimerQueue = NULL;\r
+\r
+#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+ \r
+ PRIVILEGED_DATA static xTaskHandle xTimerTaskHandle = NULL;\r
+ \r
+#endif\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Initialise the infrastructure used by the timer service task if it has not\r
+ * been initialised already.\r
+ */\r
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The timer service task (daemon). Timer functionality is controlled by this\r
+ * task. Other tasks communicate with the timer service task using the\r
+ * xTimerQueue queue.\r
+ */\r
+static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Called by the timer service task to interpret and process a command it\r
+ * received on the timer queue.\r
+ */\r
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,\r
+ * depending on if the expire time causes a timer counter overflow.\r
+ */\r
+static portBASE_TYPE prvInsertTimerInActiveList( xTIMER *pxTimer, portTickType xNextExpiryTime, portTickType xTimeNow, portTickType xCommandTime ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * An active timer has reached its expire time. Reload the timer if it is an\r
+ * auto reload timer, then call its callback.\r
+ */\r
+static void prvProcessExpiredTimer( portTickType xNextExpireTime, portTickType xTimeNow ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * The tick count has overflowed. Switch the timer lists after ensuring the\r
+ * current timer list does not still reference some timers.\r
+ */\r
+static void prvSwitchTimerLists( portTickType xLastTime ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE\r
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.\r
+ */\r
+static portTickType prvSampleTimeNow( portBASE_TYPE *pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * If the timer list contains any active timers then return the expire time of\r
+ * the timer that will expire first and set *pxListWasEmpty to false. If the\r
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty\r
+ * to pdTRUE.\r
+ */\r
+static portTickType prvGetNextExpireTime( portBASE_TYPE *pxListWasEmpty ) PRIVILEGED_FUNCTION;\r
+\r
+/*\r
+ * If a timer has expired, process it. Otherwise, block the timer service task\r
+ * until either a timer does expire or a command is received.\r
+ */\r
+static void prvProcessTimerOrBlockTask( portTickType xNextExpireTime, portBASE_TYPE xListWasEmpty ) PRIVILEGED_FUNCTION;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xTimerCreateTimerTask( void )\r
+{\r
+portBASE_TYPE xReturn = pdFAIL;\r
+\r
+ /* This function is called when the scheduler is started if\r
+ configUSE_TIMERS is set to 1. Check that the infrastructure used by the\r
+ timer service task has been created/initialised. If timers have already\r
+ been created then the initialisation will already have been performed. */\r
+ prvCheckForValidListAndQueue();\r
+\r
+ if( xTimerQueue != NULL )\r
+ {\r
+ #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+ {\r
+ /* Create the timer task, storing its handle in xTimerTaskHandle so\r
+ it can be returned by the xTimerGetTimerDaemonTaskHandle() function. */\r
+ xReturn = xTaskCreate( prvTimerTask, ( const signed char * ) "Tmr Svc", ( unsigned short ) configTIMER_TASK_STACK_DEPTH, NULL, ( unsigned portBASE_TYPE ) configTIMER_TASK_PRIORITY, &xTimerTaskHandle ); \r
+ }\r
+ #else\r
+ {\r
+ /* Create the timer task without storing its handle. */\r
+ xReturn = xTaskCreate( prvTimerTask, ( const signed char * ) "Tmr Svc", ( unsigned short ) configTIMER_TASK_STACK_DEPTH, NULL, ( unsigned portBASE_TYPE ) configTIMER_TASK_PRIORITY, NULL);\r
+ }\r
+ #endif\r
+ }\r
+\r
+ configASSERT( xReturn );\r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+xTimerHandle xTimerCreate( const signed char *pcTimerName, portTickType xTimerPeriodInTicks, unsigned portBASE_TYPE uxAutoReload, void *pvTimerID, tmrTIMER_CALLBACK pxCallbackFunction )\r
+{\r
+xTIMER *pxNewTimer;\r
+\r
+ /* Allocate the timer structure. */\r
+ if( xTimerPeriodInTicks == ( portTickType ) 0U )\r
+ {\r
+ pxNewTimer = NULL;\r
+ configASSERT( ( xTimerPeriodInTicks > 0 ) );\r
+ }\r
+ else\r
+ {\r
+ pxNewTimer = ( xTIMER * ) pvPortMalloc( sizeof( xTIMER ) );\r
+ if( pxNewTimer != NULL )\r
+ {\r
+ /* Ensure the infrastructure used by the timer service task has been\r
+ created/initialised. */\r
+ prvCheckForValidListAndQueue();\r
+ \r
+ /* Initialise the timer structure members using the function parameters. */\r
+ pxNewTimer->pcTimerName = pcTimerName;\r
+ pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;\r
+ pxNewTimer->uxAutoReload = uxAutoReload;\r
+ pxNewTimer->pvTimerID = pvTimerID;\r
+ pxNewTimer->pxCallbackFunction = pxCallbackFunction;\r
+ vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );\r
+ \r
+ traceTIMER_CREATE( pxNewTimer );\r
+ }\r
+ else\r
+ {\r
+ traceTIMER_CREATE_FAILED();\r
+ }\r
+ }\r
+ \r
+ return ( xTimerHandle ) pxNewTimer;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xTimerGenericCommand( xTimerHandle xTimer, portBASE_TYPE xCommandID, portTickType xOptionalValue, portBASE_TYPE *pxHigherPriorityTaskWoken, portTickType xBlockTime )\r
+{\r
+portBASE_TYPE xReturn = pdFAIL;\r
+xTIMER_MESSAGE xMessage;\r
+\r
+ /* Send a message to the timer service task to perform a particular action\r
+ on a particular timer definition. */\r
+ if( xTimerQueue != NULL )\r
+ {\r
+ /* Send a command to the timer service task to start the xTimer timer. */\r
+ xMessage.xMessageID = xCommandID;\r
+ xMessage.xMessageValue = xOptionalValue;\r
+ xMessage.pxTimer = ( xTIMER * ) xTimer;\r
+\r
+ if( pxHigherPriorityTaskWoken == NULL )\r
+ {\r
+ if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )\r
+ {\r
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xBlockTime );\r
+ }\r
+ else\r
+ {\r
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\r
+ }\r
+ \r
+ traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );\r
+ }\r
+ \r
+ return xReturn;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )\r
+\r
+ xTaskHandle xTimerGetTimerDaemonTaskHandle( void )\r
+ {\r
+ /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been\r
+ started, then xTimerTaskHandle will be NULL. */\r
+ configASSERT( ( xTimerTaskHandle != NULL ) );\r
+ return xTimerTaskHandle;\r
+ }\r
+ \r
+#endif\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvProcessExpiredTimer( portTickType xNextExpireTime, portTickType xTimeNow )\r
+{\r
+xTIMER *pxTimer;\r
+portBASE_TYPE xResult;\r
+\r
+ /* Remove the timer from the list of active timers. A check has already\r
+ been performed to ensure the list is not empty. */\r
+ pxTimer = ( xTIMER * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+ vListRemove( &( pxTimer->xTimerListItem ) );\r
+ traceTIMER_EXPIRED( pxTimer );\r
+\r
+ /* If the timer is an auto reload timer then calculate the next\r
+ expiry time and re-insert the timer in the list of active timers. */\r
+ if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )\r
+ {\r
+ /* This is the only time a timer is inserted into a list using\r
+ a time relative to anything other than the current time. It\r
+ will therefore be inserted into the correct list relative to\r
+ the time this task thinks it is now, even if a command to\r
+ switch lists due to a tick count overflow is already waiting in\r
+ the timer queue. */\r
+ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )\r
+ {\r
+ /* The timer expired before it was added to the active timer\r
+ list. Reload it now. */\r
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xNextExpireTime, NULL, tmrNO_DELAY );\r
+ configASSERT( xResult );\r
+ ( void ) xResult;\r
+ }\r
+ }\r
+\r
+ /* Call the timer callback. */\r
+ pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvTimerTask( void *pvParameters )\r
+{\r
+portTickType xNextExpireTime;\r
+portBASE_TYPE xListWasEmpty;\r
+\r
+ /* Just to avoid compiler warnings. */\r
+ ( void ) pvParameters;\r
+\r
+ for( ;; )\r
+ {\r
+ /* Query the timers list to see if it contains any timers, and if so,\r
+ obtain the time at which the next timer will expire. */\r
+ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );\r
+\r
+ /* If a timer has expired, process it. Otherwise, block this task\r
+ until either a timer does expire, or a command is received. */\r
+ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );\r
+ \r
+ /* Empty the command queue. */\r
+ prvProcessReceivedCommands(); \r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvProcessTimerOrBlockTask( portTickType xNextExpireTime, portBASE_TYPE xListWasEmpty )\r
+{\r
+portTickType xTimeNow;\r
+portBASE_TYPE xTimerListsWereSwitched;\r
+\r
+ vTaskSuspendAll();\r
+ {\r
+ /* Obtain the time now to make an assessment as to whether the timer\r
+ has expired or not. If obtaining the time causes the lists to switch\r
+ then don't process this timer as any timers that remained in the list\r
+ when the lists were switched will have been processed within the\r
+ prvSampelTimeNow() function. */\r
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r
+ if( xTimerListsWereSwitched == pdFALSE )\r
+ {\r
+ /* The tick count has not overflowed, has the timer expired? */\r
+ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )\r
+ {\r
+ xTaskResumeAll();\r
+ prvProcessExpiredTimer( xNextExpireTime, xTimeNow );\r
+ }\r
+ else\r
+ {\r
+ /* The tick count has not overflowed, and the next expire\r
+ time has not been reached yet. This task should therefore\r
+ block to wait for the next expire time or a command to be\r
+ received - whichever comes first. The following line cannot\r
+ be reached unless xNextExpireTime > xTimeNow, except in the\r
+ case when the current timer list is empty. */\r
+ vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ) );\r
+\r
+ if( xTaskResumeAll() == pdFALSE )\r
+ {\r
+ /* Yield to wait for either a command to arrive, or the block time\r
+ to expire. If a command arrived between the critical section being\r
+ exited and this yield then the yield will not cause the task\r
+ to block. */\r
+ portYIELD_WITHIN_API();\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ xTaskResumeAll();\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTickType prvGetNextExpireTime( portBASE_TYPE *pxListWasEmpty )\r
+{\r
+portTickType xNextExpireTime;\r
+\r
+ /* Timers are listed in expiry time order, with the head of the list\r
+ referencing the task that will expire first. Obtain the time at which\r
+ the timer with the nearest expiry time will expire. If there are no\r
+ active timers then just set the next expire time to 0. That will cause\r
+ this task to unblock when the tick count overflows, at which point the\r
+ timer lists will be switched and the next expiry time can be\r
+ re-assessed. */\r
+ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );\r
+ if( *pxListWasEmpty == pdFALSE )\r
+ {\r
+ xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+ }\r
+ else\r
+ {\r
+ /* Ensure the task unblocks when the tick count rolls over. */\r
+ xNextExpireTime = ( portTickType ) 0U;\r
+ }\r
+\r
+ return xNextExpireTime;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portTickType prvSampleTimeNow( portBASE_TYPE *pxTimerListsWereSwitched )\r
+{\r
+portTickType xTimeNow;\r
+static portTickType xLastTime = ( portTickType ) 0U;\r
+\r
+ xTimeNow = xTaskGetTickCount();\r
+ \r
+ if( xTimeNow < xLastTime )\r
+ {\r
+ prvSwitchTimerLists( xLastTime );\r
+ *pxTimerListsWereSwitched = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ *pxTimerListsWereSwitched = pdFALSE;\r
+ }\r
+ \r
+ xLastTime = xTimeNow;\r
+ \r
+ return xTimeNow;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static portBASE_TYPE prvInsertTimerInActiveList( xTIMER *pxTimer, portTickType xNextExpiryTime, portTickType xTimeNow, portTickType xCommandTime )\r
+{\r
+portBASE_TYPE xProcessTimerNow = pdFALSE;\r
+\r
+ listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );\r
+ listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r
+ \r
+ if( xNextExpiryTime <= xTimeNow )\r
+ {\r
+ /* Has the expiry time elapsed between the command to start/reset a\r
+ timer was issued, and the time the command was processed? */\r
+ if( ( ( portTickType ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks )\r
+ {\r
+ /* The time between a command being issued and the command being\r
+ processed actually exceeds the timers period. */\r
+ xProcessTimerNow = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )\r
+ {\r
+ /* If, since the command was issued, the tick count has overflowed\r
+ but the expiry time has not, then the timer must have already passed\r
+ its expiry time and should be processed immediately. */\r
+ xProcessTimerNow = pdTRUE;\r
+ }\r
+ else\r
+ {\r
+ vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r
+ }\r
+ }\r
+\r
+ return xProcessTimerNow;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvProcessReceivedCommands( void )\r
+{\r
+xTIMER_MESSAGE xMessage;\r
+xTIMER *pxTimer;\r
+portBASE_TYPE xTimerListsWereSwitched, xResult;\r
+portTickType xTimeNow;\r
+\r
+ /* In this case the xTimerListsWereSwitched parameter is not used, but it\r
+ must be present in the function call. */\r
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\r
+\r
+ while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL )\r
+ {\r
+ pxTimer = xMessage.pxTimer;\r
+\r
+ /* Is the timer already in a list of active timers? When the command\r
+ is trmCOMMAND_PROCESS_TIMER_OVERFLOW, the timer will be NULL as the\r
+ command is to the task rather than to an individual timer. */\r
+ if( pxTimer != NULL )\r
+ {\r
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )\r
+ {\r
+ /* The timer is in a list, remove it. */\r
+ vListRemove( &( pxTimer->xTimerListItem ) );\r
+ }\r
+ }\r
+\r
+ traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.xMessageValue );\r
+ \r
+ switch( xMessage.xMessageID )\r
+ {\r
+ case tmrCOMMAND_START : \r
+ /* Start or restart a timer. */\r
+ if( prvInsertTimerInActiveList( pxTimer, xMessage.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.xMessageValue ) == pdTRUE )\r
+ {\r
+ /* The timer expired before it was added to the active timer\r
+ list. Process it now. */\r
+ pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );\r
+\r
+ if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )\r
+ {\r
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xMessage.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );\r
+ configASSERT( xResult );\r
+ ( void ) xResult;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case tmrCOMMAND_STOP : \r
+ /* The timer has already been removed from the active list.\r
+ There is nothing to do here. */\r
+ break;\r
+\r
+ case tmrCOMMAND_CHANGE_PERIOD :\r
+ pxTimer->xTimerPeriodInTicks = xMessage.xMessageValue;\r
+ configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );\r
+ prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );\r
+ break;\r
+\r
+ case tmrCOMMAND_DELETE :\r
+ /* The timer has already been removed from the active list,\r
+ just free up the memory. */\r
+ vPortFree( pxTimer );\r
+ break;\r
+\r
+ default : \r
+ /* Don't expect to get here. */\r
+ break;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSwitchTimerLists( portTickType xLastTime )\r
+{\r
+portTickType xNextExpireTime, xReloadTime;\r
+xList *pxTemp;\r
+xTIMER *pxTimer;\r
+portBASE_TYPE xResult;\r
+\r
+ /* Remove compiler warnings if configASSERT() is not defined. */\r
+ ( void ) xLastTime;\r
+ \r
+ /* The tick count has overflowed. The timer lists must be switched.\r
+ If there are any timers still referenced from the current timer list\r
+ then they must have expired and should be processed before the lists\r
+ are switched. */\r
+ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )\r
+ {\r
+ xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+\r
+ /* Remove the timer from the list. */\r
+ pxTimer = ( xTIMER * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );\r
+ vListRemove( &( pxTimer->xTimerListItem ) );\r
+\r
+ /* Execute its callback, then send a command to restart the timer if\r
+ it is an auto-reload timer. It cannot be restarted here as the lists\r
+ have not yet been switched. */\r
+ pxTimer->pxCallbackFunction( ( xTimerHandle ) pxTimer );\r
+\r
+ if( pxTimer->uxAutoReload == ( unsigned portBASE_TYPE ) pdTRUE )\r
+ {\r
+ /* Calculate the reload value, and if the reload value results in\r
+ the timer going into the same timer list then it has already expired\r
+ and the timer should be re-inserted into the current list so it is\r
+ processed again within this loop. Otherwise a command should be sent\r
+ to restart the timer to ensure it is only inserted into a list after\r
+ the lists have been swapped. */\r
+ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );\r
+ if( xReloadTime > xNextExpireTime )\r
+ {\r
+ listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );\r
+ listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\r
+ vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\r
+ }\r
+ else\r
+ {\r
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START, xNextExpireTime, NULL, tmrNO_DELAY );\r
+ configASSERT( xResult );\r
+ ( void ) xResult;\r
+ }\r
+ }\r
+ }\r
+\r
+ pxTemp = pxCurrentTimerList;\r
+ pxCurrentTimerList = pxOverflowTimerList;\r
+ pxOverflowTimerList = pxTemp;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCheckForValidListAndQueue( void )\r
+{\r
+ /* Check that the list from which active timers are referenced, and the\r
+ queue used to communicate with the timer service, have been\r
+ initialised. */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ if( xTimerQueue == NULL )\r
+ {\r
+ vListInitialise( &xActiveTimerList1 );\r
+ vListInitialise( &xActiveTimerList2 );\r
+ pxCurrentTimerList = &xActiveTimerList1;\r
+ pxOverflowTimerList = &xActiveTimerList2;\r
+ xTimerQueue = xQueueCreate( ( unsigned portBASE_TYPE ) configTIMER_QUEUE_LENGTH, sizeof( xTIMER_MESSAGE ) );\r
+ }\r
+ }\r
+ taskEXIT_CRITICAL();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+portBASE_TYPE xTimerIsTimerActive( xTimerHandle xTimer )\r
+{\r
+portBASE_TYPE xTimerIsInActiveList;\r
+xTIMER *pxTimer = ( xTIMER * ) xTimer;\r
+\r
+ /* Is the timer in the list of active timers? */\r
+ taskENTER_CRITICAL();\r
+ {\r
+ /* Checking to see if it is in the NULL list in effect checks to see if\r
+ it is referenced from either the current or the overflow timer lists in\r
+ one go, but the logic has to be reversed, hence the '!'. */\r
+ xTimerIsInActiveList = !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );\r
+ }\r
+ taskEXIT_CRITICAL();\r
+\r
+ return xTimerIsInActiveList;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void *pvTimerGetTimerID( xTimerHandle xTimer )\r
+{\r
+xTIMER *pxTimer = ( xTIMER * ) xTimer;\r
+\r
+ return pxTimer->pvTimerID;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* This entire source file will be skipped if the application is not configured\r
+to include software timer functionality. If you want to include software timer\r
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\r
+#endif /* configUSE_TIMERS == 1 */\r
+\r
--- /dev/null
+/** @file pinmux.c \r
+* @brief PINMUX Driver Implementation File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+/* Include Files */\r
+\r
+#include "pinmux.h"\r
+\r
+#define PINMUX_SET(REG, BALLID, MUX) \\r
+ pinMuxReg->PINMUX##REG## = (pinMuxReg->PINMUX##REG## & PINMUX_BALL_##BALLID##_MASK) | (PINMUX_BALL_##BALLID##_##MUX##)\r
+\r
+#define PINMUX_GATE_EMIF_CLK_ENABLE \\r
+ pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GATE_EMIF_CLK_MASK) | PINMUX_GATE_EMIF_CLK\r
+\r
+#define PINMUX_GIOB_DISABLE_HET2_ENABLE \\r
+ pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_GIOB_DISABLE_HET2_MASK) | PINMUX_GIOB_DISABLE_HET2\r
+ \r
+#define PINMUX_ALT_ADC_TRIGGER_SELECT(num) \\r
+ pinMuxReg->PINMUX30 = (pinMuxReg->PINMUX30 & PINMUX_ALT_ADC_TRIGGER_MASK) | (PINMUX_ALT_ADC_TRIGGER_##num##)\r
+ \r
+#define PINMUX_ETHERNET_SELECT(interface) \\r
+ pinMuxReg->PINMUX29 = (pinMuxReg->PINMUX29 & PINMUX_ETHERNET_MASK) | (PINMUX_ETHERNET_##interface##)\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+void muxInit(void){\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+ /* Enable Pin Muxing */\r
+ kickerReg->KICKER0 = 0x83E70B13;\r
+ kickerReg->KICKER1 = 0x95A4F1E0;\r
+ \r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+ pinMuxReg->PINMUX0 = PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_B2_MIBSPI3NCS_2;\r
+ \r
+ pinMuxReg->PINMUX1 = PINMUX_BALL_E3_HET1_11 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21;\r
+ \r
+ pinMuxReg->PINMUX2 = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_G5_ETMDATA_22 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5;\r
+ \r
+ pinMuxReg->PINMUX3 = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_H3_GIOA_6 | PINMUX_BALL_L5_ETMDATA_24;\r
+ \r
+ pinMuxReg->PINMUX4 = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_V2_HET1_01 | PINMUX_BALL_U1_HET1_03;\r
+ \r
+ pinMuxReg->PINMUX5 = PINMUX_BALL_K18_HET1_0 | PINMUX_BALL_W5_HET1_02 | PINMUX_BALL_V6_HET1_05 | PINMUX_BALL_N5_ETMDATA_26;\r
+ \r
+ pinMuxReg->PINMUX6 = PINMUX_BALL_T1_HET1_07 | PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_V7_HET1_09 | PINMUX_BALL_R5_ETMDATA_28;\r
+ \r
+ pinMuxReg->PINMUX7 = PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_W3_SCIRX | PINMUX_BALL_R7_ETMDATA_30;\r
+ \r
+ pinMuxReg->PINMUX8 = PINMUX_BALL_N2_SCITX | PINMUX_BALL_G3_MIBSPI1NCS_2 | PINMUX_BALL_N1_HET1_15 | PINMUX_BALL_R8_ETMDATA_31;\r
+ \r
+ pinMuxReg->PINMUX9 = PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_W9_MIBSPI3NENA | PINMUX_BALL_V10_MIBSPI3NCS_0 | PINMUX_BALL_J3_MIBSPI1NCS_3;\r
+ \r
+ pinMuxReg->PINMUX10 = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_M15_ETMDATA_18;\r
+ \r
+ pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_P1_HET1_24;\r
+ \r
+ pinMuxReg->PINMUX12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA;\r
+ \r
+ pinMuxReg->PINMUX13 = PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_R2_MIBSPI1NCS_0;\r
+ \r
+ pinMuxReg->PINMUX14 = PINMUX_BALL_E18_HET1_08 | PINMUX_BALL_K19_HET1_28 | PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_D16_EMIF_BA_1;\r
+ \r
+ pinMuxReg->PINMUX15 = PINMUX_BALL_C17_EMIF_ADDR_21 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_D15_EMIF_ADDR_18;\r
+ \r
+ pinMuxReg->PINMUX16 = PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_E12_ETMDATA_13;\r
+ \r
+ pinMuxReg->PINMUX17 = PINMUX_BALL_D19_HET1_10 | PINMUX_BALL_E11_ETMDATA_14 | PINMUX_BALL_B4_HET1_12 | PINMUX_BALL_E9_ETMDATA_08;\r
+ \r
+ pinMuxReg->PINMUX18 = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_C12_EMIF_ADDR_14 | PINMUX_BALL_M2_GIOB_0;\r
+ \r
+ pinMuxReg->PINMUX19 = PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_B11_HET1_30 | PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_E7_ETMDATA_10;\r
+ \r
+ pinMuxReg->PINMUX20 = PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_C9_EMIF_ADDR_11;\r
+ \r
+ pinMuxReg->PINMUX21 = PINMUX_BALL_D5_EMIF_ADDR_1 | PINMUX_BALL_C8_EMIF_ADDR_10 | PINMUX_BALL_C7_EMIF_ADDR_9;\r
+ \r
+ pinMuxReg->PINMUX22 = PINMUX_BALL_D4_EMIF_ADDR_0 | PINMUX_BALL_C5_EMIF_ADDR_7 | PINMUX_BALL_C4_EMIF_ADDR_6 | PINMUX_BALL_E6_ETMDATA_11;\r
+ \r
+ pinMuxReg->PINMUX23 = 0x01010100|\r
+ PINMUX_BALL_C6_EMIF_ADDR_8;\r
+ \r
+ pinMuxReg->PINMUX24 = 0x01010101;\r
+ \r
+ pinMuxReg->PINMUX25 = 0x01010101;\r
+ \r
+ pinMuxReg->PINMUX26 = PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3;\r
+ \r
+ pinMuxReg->PINMUX27 = PINMUX_BALL_E19_MIBSPI5NCS_0 | PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2;\r
+ \r
+ pinMuxReg->PINMUX28 = PINMUX_BALL_G17_MIBSPI5SIMO_3 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;\r
+ \r
+ pinMuxReg->PINMUX29 = PINMUX_BALL_D3_SPI2NENA;\r
+ \r
+\r
+ \r
+ \r
+ PINMUX_ALT_ADC_TRIGGER_SELECT(1);\r
+ PINMUX_ETHERNET_SELECT(RMII);\r
+ \r
+ PINMUX_SET(0,A5,GIOA_0);\r
+ PINMUX_SET(18,A11,HET1_14);\r
+ PINMUX_SET(3,B3,HET1_22);\r
+ PINMUX_SET(1,C2,GIOA_1);\r
+ PINMUX_SET(21,K2,GIOB_1);\r
+ PINMUX_SET(0,W10,GIOB_3);\r
+ \r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+ \r
+ /* Disable Pin Muxing */\r
+ kickerReg->KICKER0 = 0x00000000;\r
+ kickerReg->KICKER1 = 0x00000000;\r
+ \r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+}\r
+\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
--- /dev/null
+/** @file sci.c \r
+* @brief SCI Driver Implementation File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+#include "sci.h"\r
+#include "cmdio_tisci.h"\r
+#include "os_queue.h"\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+/** @struct g_sciTransfer\r
+* @brief Interrupt mode globals\r
+*\r
+*/\r
+struct g_sciTransfer\r
+{\r
+ uint32_t mode;\r
+ uint32_t length;\r
+ uint8_t *data;\r
+} g_sciTransfer[2];\r
+\r
+extern tBuffer outBuffer;\r
+extern tBuffer inBuffer;\r
+static uint32_t receiveError;\r
+static uint32_t sendError;\r
+\r
+\r
+/** @fn void sciInit(void)\r
+* @brief Initializes the SCI Driver\r
+*\r
+* This function initializes the SCI module.\r
+*/\r
+void sciInit(void)\r
+{\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+ /** @b intalise @b SCI */\r
+\r
+ /** - bring SCI out of reset */\r
+ sciREG->GCR0 = 1U;\r
+\r
+ /** - Disable all interrupts */\r
+ sciREG->CLRINT = 0xFFFFFFFFU;\r
+ sciREG->CLRINTLVL = 0xFFFFFFFFU;\r
+\r
+ /** - global control 1 */\r
+ sciREG->GCR1 = (1 << 25) /* enable transmit */\r
+ | (1 << 24) /* enable receive */\r
+ | (1 << 5) /* internal clock (device has no clock pin) */\r
+ | ((2-1) << 4) /* number of stop bits */\r
+ | (0 << 3) /* even parity, otherwise odd */\r
+ | (0 << 2) /* enable parity */\r
+ | (1 << 1); /* asynchronous timing mode */\r
+\r
+ /** - set baudrate */\r
+ sciREG->BAUD = 520; /* baudrate */\r
+\r
+ /** - tranmision length */\r
+ sciREG->LENGTH = 8 - 1; /* length */\r
+\r
+ /** - set SCI pins functional mode */\r
+ sciREG->FUN = (1 << 2) /* tx pin */\r
+ | (1 << 1) /* rx pin */\r
+ | (0); /* clk pin */\r
+\r
+ /** - set SCI pins default output value */\r
+ sciREG->DOUT = (0 << 2) /* tx pin */\r
+ | (0 << 1) /* rx pin */\r
+ | (0); /* clk pin */\r
+\r
+ /** - set SCI pins output direction */\r
+ sciREG->DIR = (1 << 2) /* tx pin */\r
+ | (0 << 1) /* rx pin */\r
+ | (0); /* clk pin */\r
+\r
+ /** - set SCI pins open drain enable */\r
+ sciREG->ODR = (0 << 2) /* tx pin */\r
+ | (0 << 1) /* rx pin */\r
+ | (0); /* clk pin */\r
+\r
+ /** - set SCI pins pullup/pulldown enable */\r
+ sciREG->PD = (0 << 2) /* tx pin */\r
+ | (0 << 1) /* rx pin */\r
+ | (0); /* clk pin */\r
+\r
+ /** - set SCI pins pullup/pulldown select */\r
+ sciREG->PSL = (1 << 2) /* tx pin */\r
+ | (1 << 1) /* rx pin */\r
+ | (1); /* clk pin */\r
+\r
+ /** - set interrupt level */\r
+ sciREG->SETINTLVL = (0 << 26) /* Framing error */\r
+ | (0 << 25) /* Overrun error */\r
+ | (0 << 24) /* Pariry error */\r
+ | (0 << 9) /* Receive */\r
+ | (0 << 8) /* Transmit */\r
+ | (0 << 1) /* Wakeup */\r
+ | (0); /* Break detect */\r
+\r
+ /** - set interrupt enable */\r
+ sciREG->SETINT = (0 << 26) /* Framing error */\r
+ | (0 << 25) /* Overrun error */\r
+ | (0 << 24) /* Pariry error */\r
+ | (1 << 9) /* Receive */\r
+ | (0 << 1) /* Wakeup */\r
+ | (0); /* Break detect */\r
+\r
+ /** - inialise global transfer variables */\r
+ g_sciTransfer[0].mode = 0 << 8;\r
+ g_sciTransfer[0].length = 0;\r
+\r
+ /** - Finaly start SCI */\r
+ sciREG->GCR1 |= (1 << 7);\r
+\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void sciSetFunctional(sciBASE_t *sci, uint32_t port)\r
+* @brief Change functional behavoiur of pins at runtime.\r
+* @param[in] sci - sci module base address\r
+* @param[in] port - Value to write to FUN register\r
+*\r
+* Change the value of the PCFUN register at runtime, this allows to\r
+* dynaimcaly change the functionality of the SCI pins between functional\r
+* and GIO mode.\r
+*/\r
+void sciSetFunctional(sciBASE_t *sci, uint32_t port)\r
+{\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+\r
+ sci->FUN = port;\r
+\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32_t baud)\r
+* @brief Change baudrate at runtime.\r
+* @param[in] sci - sci module base address\r
+* @param[in] baud - baudrate in Hz\r
+*\r
+* Change the SCI baudrate at runtime.\r
+*/\r
+void sciSetBaudrate(sciBASE_t *sci, uint32_t baud)\r
+{\r
+ double vclk = 80.000 * 1000000.0;\r
+ uint32_t f = sci->GCR1 & 2 ? 16 : 1;\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+ sci->BAUD = ((uint32_t)((vclk /(f*baud) + 0.5)) - 1) & 0x00FFFFFF;\r
+\r
+/* USER CODE BEGIN (7) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn int sciIsTxReady(sciBASE_t *sci)\r
+* @brief Check if Tx buffer empty\r
+* @param[in] sci - sci module base address\r
+*\r
+* @return The TX ready flag\r
+*\r
+* Checks to see if the Tx buffer ready flag is set, returns\r
+* 0 is flags not set otherwise will return the Tx flag itself.\r
+*/\r
+int sciIsTxReady(sciBASE_t *sci)\r
+{\r
+/* USER CODE BEGIN (8) */\r
+/* USER CODE END */\r
+\r
+ return sci->FLR & SCI_TX_INT;\r
+}\r
+\r
+\r
+/** @fn void sciSendByte(sciBASE_t *sci, uint8_t byte)\r
+* @brief Send Byte\r
+* @param[in] sci - sci module base address\r
+* @param[in] byte - byte to transfer\r
+*\r
+* Sends a single byte in polling mode, will wait in the\r
+* routine until the transmit buffer is empty before sending\r
+* the byte. Use sciIsTxReady to check for Tx buffer empty\r
+* before calling sciSendByte to avoid waiting.\r
+*/\r
+void sciSendByte(sciBASE_t *sci, uint8_t byte)\r
+{\r
+/* USER CODE BEGIN (9) */\r
+/* USER CODE END */\r
+\r
+ while ((sci->FLR & SCI_TX_INT) == 0) { /* wait */ };\r
+ sci->TD = byte;\r
+\r
+/* USER CODE BEGIN (10) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void sciSend(sciBASE_t *sci, uint32_t length, uint8_t *data)\r
+* @brief Send Data\r
+* @param[in] sci - sci module base address\r
+* @param[in] length - number of data words to transfer\r
+* @param[in] data - pointer to data to send\r
+*\r
+* Send a block of data pointed to by 'data' and 'length' bytes\r
+* long. If interrupts have been enabled the data is sent using\r
+* interrupt mode, otherwise polling mode is used. In interrupt\r
+* mode transmition of the first byte is started and the routine\r
+* returns imediatly, sciSend must not be called again until the\r
+* transfer is complete, when the sciNotification callback will\r
+* be called. In polling mode, sciSend will not return until \r
+* the transfer is complete.\r
+*\r
+* @note if data word is less than 8 bits, then the data must be left\r
+* aligned in the data byte.\r
+*/\r
+void sciSend(sciBASE_t *sci, uint32_t length, uint8_t *data)\r
+{\r
+ int index = sci == sciREG ? 0 : 1;\r
+\r
+/* USER CODE BEGIN (11) */\r
+/* USER CODE END */\r
+\r
+ if ((g_sciTransfer[index].mode & SCI_TX_INT) != 0)\r
+ {\r
+ /* start transmit by sending first byte */\r
+ uint8_t byte;\r
+ if (xQueueReceiveFromISR(outBuffer.buf, (uint8_t *)&byte, NULL) == pdPASS) {\r
+ sci->TD = byte;\r
+ sci->SETINT = SCI_TX_INT;\r
+ }\r
+ else sendError++;\r
+ }\r
+ else\r
+ {\r
+ /* send the data */\r
+ while (length-- > 0)\r
+ {\r
+ while ((sci->FLR & SCI_TX_INT) == 0) { /* wait */ };\r
+ sci->TD = *data++;\r
+ }\r
+ }\r
+\r
+/* USER CODE BEGIN (12) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn int sciIsRxReady(sciBASE_t *sci)\r
+* @brief Check if Rx buffer full\r
+* @param[in] sci - sci module base address\r
+*\r
+* @return The Rx ready flag\r
+*\r
+* Checks to see if the Rx buffer full flag is set, returns\r
+* 0 is flags not set otherwise will return the Rx flag itself.\r
+*/\r
+int sciIsRxReady(sciBASE_t *sci)\r
+{\r
+/* USER CODE BEGIN (13) */\r
+/* USER CODE END */\r
+\r
+ return sci->FLR & SCI_RX_INT;\r
+}\r
+\r
+\r
+/** @fn int sciRxError(sciBASE_t *sci)\r
+* @brief Return Rx Error flags\r
+* @param[in] sci - sci module base address\r
+*\r
+* @return The Rx error flags\r
+*\r
+* Returns the Rx framing, overun and parity errors flags,\r
+* also clears the error flags before returning.\r
+*/\r
+int sciRxError(sciBASE_t *sci)\r
+{\r
+ int status = sci->FLR & (SCI_FE_INT | SCI_OE_INT |SCI_PE_INT);\r
+\r
+/* USER CODE BEGIN (14) */\r
+/* USER CODE END */\r
+\r
+ sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;\r
+ return status;\r
+}\r
+\r
+\r
+/** @fn uint32_t sciReceiveByte(sciBASE_t *sci)\r
+* @brief Receive Byte\r
+* @param[in] sci - sci module base address\r
+*\r
+* @return Received byte\r
+*\r
+* Recieves a single byte in polling mode. If there is\r
+* not a byte in the receive buffer the routine will wait\r
+* until one is received. Use sciIsRxReady to check to\r
+* see if the buffer is full to avoid waiting.\r
+*/\r
+int sciReceiveByte(sciBASE_t *sci)\r
+{\r
+/* USER CODE BEGIN (15) */\r
+/* USER CODE END */\r
+\r
+ while ((sci->FLR & SCI_RX_INT) == 0) { /* wait */ };\r
+\r
+ return sci->RD;\r
+}\r
+\r
+\r
+/** @fn void sciReceive(sciBASE_t *sci, uint32_t length, uint8_t *data)\r
+* @brief Receive Data\r
+* @param[in] sci - sci module base address\r
+* @param[in] length - number of data words to transfer\r
+* @param[in] data - pointer to data buffer\r
+*\r
+* Receive a block of 'length' bytes long and place it into the \r
+* data buffer pointed to by 'data'. If interrupts have been \r
+* enabled the data is received using interrupt mode, otherwise\r
+* polling mode is used. In interrupt mode receive is setup and\r
+* the routine returns imediatly, sciReceive must not be called \r
+* again until the transfer is complete, when the sciNotification \r
+* callback will be called. In polling mode, sciReceive will not\r
+* return until the transfer is complete.\r
+*/\r
+void sciReceive(sciBASE_t *sci, uint32_t length, uint8_t *data)\r
+{\r
+/* USER CODE BEGIN (16) */\r
+/* USER CODE END */\r
+\r
+ if (sci->SETINT & SCI_RX_INT)\r
+ {\r
+ /* clear error flags */\r
+ sci->FLR = SCI_FE_INT | SCI_OE_INT | SCI_PE_INT;\r
+\r
+ }\r
+ else\r
+ { \r
+ while (length-- > 0)\r
+ {\r
+ while ((sci->FLR & SCI_RX_INT) == 0) { /* wait */ };\r
+ *data++ = sci->RD;\r
+ }\r
+ }\r
+/* USER CODE BEGIN (17) */\r
+/* USER CODE END */\r
+}\r
+\r
+/** @fn void sciEnableLoopback(sciBASE_t *sci, Loopbacktype_t Loopbacktype)\r
+* @brief Enable Loopback mode for self test\r
+* @param[in] sci - sci module base address\r
+* @param[in] Loopbacktype - Digital or Analog\r
+*\r
+* This function enables the Loopback mode for self test.\r
+*/\r
+void sciEnableLoopback(sciBASE_t *sci, Loopbacktype_t Loopbacktype)\r
+{\r
+/* USER CODE BEGIN (18) */\r
+/* USER CODE END */\r
+ \r
+ /* Clear Loopback incase enbaled already */\r
+ sci->IODFTCTRL = 0;\r
+ \r
+ /* Enable Loopback either in Analog or Digital Mode */\r
+ sci->IODFTCTRL = 0x00000A00\r
+ | Loopbacktype << 1;\r
+ \r
+/* USER CODE BEGIN (19) */\r
+/* USER CODE END */\r
+}\r
+\r
+/** @fn void sciDisableLoopback(sciBASE_t *sci)\r
+* @brief Enable Loopback mode for self test\r
+* @param[in] sci - sci module base address\r
+*\r
+* This function disable the Loopback mode.\r
+*/\r
+void sciDisableLoopback(sciBASE_t *sci)\r
+{\r
+/* USER CODE BEGIN (20) */\r
+/* USER CODE END */\r
+ \r
+ /* Disable Loopback Mode */\r
+ sci->IODFTCTRL = 0x000005000;\r
+ \r
+/* USER CODE BEGIN (21) */\r
+/* USER CODE END */\r
+}\r
+\r
+/** @fn sciEnableNotification(sciBASE_t *sci, uint32_t flags)\r
+* @brief Enable interrupts\r
+* @param[in] sci - sci module base address\r
+* @param[in] flags - Interrupts to be enabled, can be ored value of:\r
+* SCI_FE_INT - framming error,\r
+* SCI_OE_INT - overrun error,\r
+* SCI_PE_INT - parity error,\r
+* SCI_RX_INT - receive buffer ready,\r
+* SCI_TX_INT - transmit buffer ready,\r
+* SCI_WAKE_INT - wakeup,\r
+* SCI_BREAK_INT - break detect\r
+*/\r
+void sciEnableNotification(sciBASE_t *sci, uint32_t flags)\r
+{\r
+ int index = sci == sciREG ? 0 : 1;\r
+\r
+/* USER CODE BEGIN (22) */\r
+/* USER CODE END */\r
+\r
+ g_sciTransfer[index].mode |= (flags & SCI_TX_INT);\r
+ sci->SETINT = (flags & ~SCI_TX_INT);\r
+\r
+/* USER CODE BEGIN (23) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn sciDisableNotification(sciBASE_t *sci, uint32_t flags)\r
+* @brief Disable interrupts\r
+* @param[in] sci - sci module base address\r
+* @param[in] flags - Interrupts to be disabled, can be ored value of:\r
+* SCI_FE_INT - framming error,\r
+* SCI_OE_INT - overrun error,\r
+* SCI_PE_INT - parity error,\r
+* SCI_RX_INT - receive buffer ready,\r
+* SCI_TX_INT - transmit buffer ready,\r
+* SCI_WAKE_INT - wakeup,\r
+* SCI_BREAK_INT - break detect\r
+*/\r
+void sciDisableNotification(sciBASE_t *sci, uint32_t flags)\r
+{\r
+ int index = sci == sciREG ? 0 : 1;\r
+\r
+/* USER CODE BEGIN (24) */\r
+/* USER CODE END */\r
+\r
+ g_sciTransfer[index].mode &= ~(flags & SCI_TX_INT);\r
+ sci->CLRINT = (flags & ~SCI_TX_INT);\r
+\r
+/* USER CODE BEGIN (25) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void sciHighLevelInterrupt(void)\r
+* @brief Level 0 Interrupt for SCI\r
+*/\r
+#pragma INTERRUPT(sciHighLevelInterrupt, IRQ)\r
+\r
+void sciHighLevelInterrupt(void)\r
+{\r
+ uint32_t vec = sciREG->INTVECT0;\r
+\r
+/* USER CODE BEGIN (26) */\r
+/* USER CODE END */\r
+\r
+ switch (vec)\r
+ {\r
+ case 1:\r
+ sciNotification(sciREG, SCI_WAKE_INT);\r
+ break;\r
+ case 3:\r
+ sciNotification(sciREG, SCI_PE_INT);\r
+ break;\r
+ case 6:\r
+ sciNotification(sciREG, SCI_FE_INT);\r
+ break;\r
+ case 7:\r
+ sciNotification(sciREG, SCI_BREAK_INT);\r
+ break;\r
+ case 9:\r
+ sciNotification(sciREG, SCI_OE_INT);\r
+ break;\r
+\r
+ case 11:\r
+ /* receive */\r
+ { uint32_t byte = sciREG->RD;\r
+ if (xQueueSendFromISR(inBuffer.buf, (void*)&byte, NULL) == errQUEUE_FULL)\r
+ receiveError++;\r
+ sciNotification(sciREG, SCI_RX_INT);\r
+ }\r
+ break;\r
+\r
+ case 12:\r
+ /* transmit */\r
+ {\r
+ uint8_t byte;\r
+ if (xQueueReceiveFromISR(outBuffer.buf, (uint8_t *)&byte, NULL) == pdPASS) {\r
+ sciREG->TD = byte;\r
+ sciNotification(sciREG, SCI_TX_INT);\r
+ }\r
+ else {\r
+ sciREG->CLRINT = SCI_TX_INT;\r
+ }\r
+ break;\r
+ }\r
+\r
+ default:\r
+ /* phantom interrupt, clear flags and return */\r
+ sciREG->FLR = ~sciREG->SETINTLVL & 0x07000303;\r
+ break;\r
+ }\r
+/* USER CODE BEGIN (27) */\r
+/* USER CODE END */\r
+}\r
+\r
+/** @fn void sciLowLevelInterrupt(void)\r
+* @brief Level 1 Interrupt for SCI\r
+*/\r
+#pragma INTERRUPT(sciLowLevelInterrupt, IRQ)\r
+\r
+void sciLowLevelInterrupt(void)\r
+{\r
+ uint32_t vec = sciREG->INTVECT1;\r
+\r
+/* USER CODE BEGIN (28) */\r
+/* USER CODE END */\r
+\r
+ switch (vec)\r
+ {\r
+ case 1:\r
+ sciNotification(sciREG, SCI_WAKE_INT);\r
+ break;\r
+ case 3:\r
+ sciNotification(sciREG, SCI_PE_INT);\r
+ break;\r
+ case 6:\r
+ sciNotification(sciREG, SCI_FE_INT);\r
+ break;\r
+ case 7:\r
+ sciNotification(sciREG, SCI_BREAK_INT);\r
+ break;\r
+ case 9:\r
+ sciNotification(sciREG, SCI_OE_INT);\r
+ break;\r
+\r
+ case 11:\r
+ /* receive */\r
+ { uint32_t byte = sciREG->RD;\r
+ if (xQueueSendFromISR(inBuffer.buf, (void *)&byte, NULL) == errQUEUE_FULL)\r
+ receiveError++;\r
+ sciNotification(sciREG, SCI_RX_INT);\r
+ }\r
+ break;\r
+\r
+ case 12:\r
+ /* transmit */\r
+ {\r
+ uint8_t byte;\r
+ if (xQueueReceiveFromISR(outBuffer.buf, (uint8_t *)&byte, NULL) == pdPASS) {\r
+ sciREG->TD = byte;\r
+ sciNotification(sciREG, SCI_TX_INT);\r
+ }\r
+ else {\r
+ sciREG->CLRINT = SCI_TX_INT;\r
+ }\r
+ }\r
+ break;\r
+\r
+ default:\r
+ /* phantom interrupt, clear flags and return */\r
+ sciREG->FLR = sciREG->SETINTLVL & 0x07000303;\r
+ break;\r
+ }\r
+/* USER CODE BEGIN (29) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+\r
--- /dev/null
+;-------------------------------------------------------------------------------\r
+; sys_core.asm\r
+;\r
+; (c) Texas Instruments 2009-2012, All rights reserved.\r
+;\r
+\r
+ .text\r
+ .arm\r
+\r
+;-------------------------------------------------------------------------------\r
+; Initialize CPU Registers\r
+\r
+ .def _coreInitRegisters_\r
+ .asmfunc\r
+ \r
+\r
+_coreInitRegisters_\r
+\r
+\r
+ ; After reset, the CPU is in the Supervisor mode (M = 10011)\r
+ mov r0, lr\r
+ mov r1, #0x0000\r
+ mov r2, #0x0000\r
+ mov r3, #0x0000\r
+ mov r4, #0x0000\r
+ mov r5, #0x0000\r
+ mov r6, #0x0000\r
+ mov r7, #0x0000\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ mov r13, #0x0000\r
+ mrs r1, cpsr\r
+ msr spsr_cxsf, r1 \r
+ ; Switch to FIQ mode (M = 10001)\r
+ cps #17\r
+ mov lr, r0\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ mrs r1, cpsr\r
+ msr spsr_cxsf, r1 \r
+ ; Switch to IRQ mode (M = 10010)\r
+ cps #18\r
+ mov lr, r0\r
+ mrs r1,cpsr\r
+ msr spsr_cxsf, r1 \r
+ ; Switch to Abort mode (M = 10111)\r
+ cps #23\r
+ mov lr, r0\r
+ mrs r1,cpsr\r
+ msr spsr_cxsf, r1 \r
+ ; Switch to Undefined Instruction Mode (M = 11011)\r
+ cps #27\r
+ mov lr, r0\r
+ mrs r1,cpsr\r
+ msr spsr_cxsf, r1 \r
+ ; Switch back to Supervisor Mode (M = 10011)\r
+ cps #19\r
+\r
+\r
+ mrc p15, #0x00, r2, c1, c0, #0x02\r
+ orr r2, r2, #0xF00000\r
+ mcr p15, #0x00, r2, c1, c0, #0x02\r
+ mov r2, #0x40000000\r
+ fmxr fpexc, r2\r
+\r
+ fmdrr d0, r1, r1\r
+ fmdrr d1, r1, r1\r
+ fmdrr d2, r1, r1\r
+ fmdrr d3, r1, r1\r
+ fmdrr d4, r1, r1\r
+ fmdrr d5, r1, r1\r
+ fmdrr d6, r1, r1\r
+ fmdrr d7, r1, r1\r
+ fmdrr d8, r1, r1\r
+ fmdrr d9, r1, r1\r
+ fmdrr d10, r1, r1\r
+ fmdrr d11, r1, r1\r
+ fmdrr d12, r1, r1\r
+ fmdrr d13, r1, r1\r
+ fmdrr d14, r1, r1\r
+ fmdrr d15, r1, r1\r
+ bl next1\r
+next1\r
+ bl next2\r
+next2\r
+ bl next3\r
+next3\r
+ bl next4\r
+next4\r
+ bx r0\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Initialize Stack Pointers\r
+\r
+ .def _coreInitStackPointer_\r
+ .asmfunc\r
+\r
+_coreInitStackPointer_\r
+\r
+ cps #17\r
+ ldr sp, fiqSp\r
+ cps #18\r
+ ldr sp, irqSp\r
+ cps #23\r
+ ldr sp, abortSp\r
+ cps #27\r
+ ldr sp, undefSp\r
+ cps #31\r
+ ldr sp, userSp\r
+ cps #19\r
+ ldr sp, svcSp\r
+ bx lr\r
+\r
+userSp .word 0x08000000+0x00001000\r
+svcSp .word 0x08000000+0x00001000+0x00000100\r
+fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100\r
+irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100\r
+abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100\r
+undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get CPSR Value\r
+\r
+ .def _getCPSRValue_\r
+ .asmfunc\r
+\r
+_getCPSRValue_\r
+\r
+ mrs r0, CPSR\r
+ bx lr\r
+\r
+ .endasmfunc\r
+ \r
+;-------------------------------------------------------------------------------\r
+; Take CPU to IDLE state\r
+\r
+ .def _gotoCPUIdle_\r
+ .asmfunc\r
+\r
+_gotoCPUIdle_\r
+\r
+ WFI\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ \r
+ .endasmfunc\r
+ \r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable VFP Unit\r
+\r
+ .def _coreEnableVfp_\r
+ .asmfunc\r
+\r
+_coreEnableVfp_\r
+\r
+ mrc p15, #0x00, r0, c1, c0, #0x02\r
+ orr r0, r0, #0xF00000\r
+ mcr p15, #0x00, r0, c1, c0, #0x02\r
+ mov r0, #0x40000000\r
+ fmxr fpexc, r0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Event Bus Export\r
+\r
+ .def _coreEnableEventBusExport_\r
+ .asmfunc\r
+\r
+_coreEnableEventBusExport_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0x00, r0, c9, c12, #0x00\r
+ orr r0, r0, #0x10\r
+ mcr p15, #0x00, r0, c9, c12, #0x00\r
+ ldmfd sp!, {r0}\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable Event Bus Export\r
+\r
+ .def _coreDisableEventBusExport_\r
+ .asmfunc\r
+\r
+_coreDisableEventBusExport_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0x00, r0, c9, c12, #0x00\r
+ bic r0, r0, #0x10\r
+ mcr p15, #0x00, r0, c9, c12, #0x00\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable RAM ECC Support\r
+\r
+ .def _coreEnableRamEcc_\r
+ .asmfunc\r
+\r
+_coreEnableRamEcc_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0x00, r0, c1, c0, #0x01\r
+ orr r0, r0, #0x0C000000\r
+ mcr p15, #0x00, r0, c1, c0, #0x01\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable RAM ECC Support\r
+\r
+ .def _coreDisableRamEcc_\r
+ .asmfunc\r
+\r
+_coreDisableRamEcc_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0x00, r0, c1, c0, #0x01\r
+ bic r0, r0, #0x0C000000\r
+ mcr p15, #0x00, r0, c1, c0, #0x01\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Flash ECC Support\r
+\r
+ .def _coreEnableFlashEcc_\r
+ .asmfunc\r
+\r
+_coreEnableFlashEcc_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0x00, r0, c1, c0, #0x01\r
+ orr r0, r0, #0x02000000\r
+ dmb\r
+ mcr p15, #0x00, r0, c1, c0, #0x01\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable Flash ECC Support\r
+\r
+ .def _coreDisableFlashEcc_\r
+ .asmfunc\r
+\r
+_coreDisableFlashEcc_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0x00, r0, c1, c0, #0x01\r
+ bic r0, r0, #0x02000000\r
+ mcr p15, #0x00, r0, c1, c0, #0x01\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Offset via Vic controller\r
+\r
+ .def _coreEnableIrqVicOffset_\r
+ .asmfunc\r
+\r
+_coreEnableIrqVicOffset_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ orr r0, r0, #0x01000000\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get data fault status register\r
+\r
+ .def _coreGetDataFault_\r
+ .asmfunc\r
+\r
+_coreGetDataFault_\r
+\r
+ mrc p15, #0, r0, c5, c0, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear data fault status register\r
+\r
+ .def _coreClearDataFault_\r
+ .asmfunc\r
+\r
+_coreClearDataFault_\r
+\r
+ stmfd sp!, {r0}\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c5, c0, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get instruction fault status register\r
+\r
+ .def _coreGetInstructionFault_\r
+ .asmfunc\r
+\r
+_coreGetInstructionFault_\r
+\r
+ mrc p15, #0, r0, c5, c0, #1\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear instruction fault status register\r
+\r
+ .def _coreClearInstructionFault_\r
+ .asmfunc\r
+\r
+_coreClearInstructionFault_\r
+\r
+ stmfd sp!, {r0}\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c5, c0, #1\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get data fault address register\r
+\r
+ .def _coreGetDataFaultAddress_\r
+ .asmfunc\r
+\r
+_coreGetDataFaultAddress_\r
+\r
+ mrc p15, #0, r0, c6, c0, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear data fault address register\r
+\r
+ .def _coreClearDataFaultAddress_\r
+ .asmfunc\r
+\r
+_coreClearDataFaultAddress_\r
+\r
+ stmfd sp!, {r0}\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c6, c0, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get instruction fault address register\r
+\r
+ .def _coreGetInstructionFaultAddress_\r
+ .asmfunc\r
+\r
+_coreGetInstructionFaultAddress_\r
+\r
+ mrc p15, #0, r0, c6, c0, #2\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear instruction fault address register\r
+\r
+ .def _coreClearInstructionFaultAddress_\r
+ .asmfunc\r
+\r
+_coreClearInstructionFaultAddress_\r
+\r
+ stmfd sp!, {r0}\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c6, c0, #2\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get auxiliary data fault status register\r
+\r
+ .def _coreGetAuxiliaryDataFault_\r
+ .asmfunc\r
+\r
+_coreGetAuxiliaryDataFault_\r
+\r
+ mrc p15, #0, r0, c5, c1, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear auxiliary data fault status register\r
+\r
+ .def _coreClearAuxiliaryDataFault_\r
+ .asmfunc\r
+\r
+_coreClearAuxiliaryDataFault_\r
+\r
+ stmfd sp!, {r0}\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c5, c1, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get auxiliary instruction fault status register\r
+\r
+ .def _coreGetAuxiliaryInstructionFault_\r
+ .asmfunc\r
+\r
+_coreGetAuxiliaryInstructionFault_\r
+\r
+ mrc p15, #0, r0, c5, c1, #1\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear auxiliary instruction fault status register\r
+\r
+ .def _coreClearAuxiliaryInstructionFault_\r
+ .asmfunc\r
+\r
+_coreClearAuxiliaryInstructionFault_\r
+\r
+ stmfd sp!, {r0}\r
+ mov r0, #0\r
+ mrc p15, #0, r0, c5, c1, #1\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable interrupts - R4 IRQ & FIQ\r
+\r
+ .def _disable_interrupt_\r
+ .asmfunc\r
+ \r
+_disable_interrupt_\r
+\r
+ cpsid if\r
+ bx lr\r
+ \r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable FIQ interrupt\r
+\r
+ .def _disable_FIQ_interrupt_\r
+ .asmfunc\r
+ \r
+_disable_FIQ_interrupt_\r
+\r
+ cpsid f\r
+ bx lr\r
+ \r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable FIQ interrupt\r
+\r
+ .def _disable_IRQ_interrupt_ \r
+ .asmfunc\r
+ \r
+_disable_IRQ_interrupt_\r
+\r
+ cpsid i\r
+ bx lr\r
+ \r
+ .endasmfunc\r
+ \r
+;-------------------------------------------------------------------------------\r
+; Enable interrupts - R4 IRQ & FIQ\r
+\r
+ .def _enable_interrupt_\r
+ .asmfunc\r
+\r
+_enable_interrupt_\r
+\r
+ cpsie if\r
+ bx lr\r
+ \r
+ .endasmfunc\r
+\r
+ \r
+;-------------------------------------------------------------------------------\r
+; Clear ESM CCM errorss\r
+\r
+ .def _esmCcmErrorsClear_\r
+ .asmfunc\r
+\r
+_esmCcmErrorsClear_\r
+\r
+ stmfd sp!, {r0-r2} \r
+ ldr r0, ESMSR1_REG ; load the ESMSR1 status register address\r
+ ldr r2, ESMSR1_ERR_CLR\r
+ str r2, [r0] ; clear the ESMSR1 register\r
+\r
+ ldr r0, ESMSR2_REG ; load the ESMSR2 status register address\r
+ ldr r2, ESMSR2_ERR_CLR\r
+ str r2, [r0] ; clear the ESMSR2 register\r
+\r
+ ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address\r
+ ldr r2, ESMSSR2_ERR_CLR\r
+ str r2, [r0] ; clear the ESMSSR2 register\r
+\r
+ ldr r0, ESMKEY_REG ; load the ESMKEY register address\r
+ mov r2, #0x5 ; load R2 with 0x5\r
+ str r2, [r0] ; clear the ESMKEY register\r
+\r
+ ldr r0, VIM_INTREQ ; load the INTREQ register address\r
+ ldr r2, VIM_INT_CLR\r
+ str r2, [r0] ; clear the INTREQ register\r
+ ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address\r
+ ldr r2, CCMR4_ERR_CLR\r
+ str r2, [r0] ; clear the CCMR4 status register\r
+ ldmfd sp!, {r0-r2} \r
+ bx lr\r
+\r
+ESMSR1_REG .word 0xFFFFF518\r
+ESMSR2_REG .word 0xFFFFF51C\r
+ESMSR3_REG .word 0xFFFFF520\r
+ESMKEY_REG .word 0xFFFFF538\r
+ESMSSR2_REG .word 0xFFFFF53C\r
+CCMR4_STAT_REG .word 0xFFFFF600\r
+ERR_CLR_WRD .word 0xFFFFFFFF\r
+CCMR4_ERR_CLR .word 0x00010000\r
+ESMSR1_ERR_CLR .word 0x80000000\r
+ESMSR2_ERR_CLR .word 0x00000004\r
+ESMSSR2_ERR_CLR .word 0x00000004\r
+VIM_INT_CLR .word 0x00000001\r
+VIM_INTREQ .word 0xFFFFFE20\r
+\r
+ .endasmfunc \r
+ \r
+\r
+;-------------------------------------------------------------------------------\r
+; C++ construct table pointers\r
+\r
+ .def __TI_PINIT_Base, __TI_PINIT_Limit\r
+ .weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit\r
+\r
+__TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base\r
+__TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit\r
+\r
+ \r
+\r
+;-------------------------------------------------------------------------------\r
+\r
--- /dev/null
+;-------------------------------------------------------------------------------\r
+; sys_intvecs.asm\r
+;\r
+; (c) Texas Instruments 2009-2012, All rights reserved.\r
+;\r
+\r
+ .sect ".intvecs"\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; import reference for interrupt routines\r
+\r
+ .ref _c_int00\r
+ .ref vPortYieldProcessor\r
+ .ref _dabort\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; interrupt vectors\r
+\r
+ b _c_int00\r
+undefEntry\r
+ b undefEntry\r
+ b vPortYieldProcessor\r
+prefetchEntry\r
+ b prefetchEntry\r
+ b _dabort\r
+reservedEntry\r
+ b reservedEntry\r
+ ldr pc,[pc,#-0x1b0]\r
+ ldr pc,[pc,#-0x1b0]\r
+\r
+ \r
+;-------------------------------------------------------------------------------\r
--- /dev/null
+/*----------------------------------------------------------------------------*/\r
+/* sys_link.cmd */\r
+/* */\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+/* */\r
+\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Linker Settings */\r
+\r
+--retain="*(.intvecs)"\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Memory Map */\r
+\r
+MEMORY\r
+{\r
+ VECTORS (X) : origin=0x00000000 length=0x00000020\r
+ FLASH0 (RX) : origin=0x00000020 length=0x0017FFE0\r
+ FLASH1 (RX) : origin=0x00180000 length=0x00180000\r
+ STACKS (RW) : origin=0x08000000 length=0x00001500\r
+ RAM (RW) : origin=0x08001500 length=0x00026B00\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+}\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Section Configuration */\r
+\r
+SECTIONS\r
+{\r
+ .intvecs : {} > VECTORS\r
+ .text : {} > FLASH0 | FLASH1\r
+ .const : {} > FLASH0 | FLASH1\r
+ .cinit : {} > FLASH0 | FLASH1\r
+ .pinit : {} > FLASH0 | FLASH1\r
+ .bss : {} > RAM\r
+ .data : {} > RAM\r
+\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+}\r
+\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Misc */\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
--- /dev/null
+/** @file sys_main.c \r
+* @brief Application main file\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+* This file contains an empty main function,\r
+* which can be used for the application.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+/* Include Files */\r
+\r
+#include "sys_common.h"\r
+#include "system.h"\r
+\r
+/* USER CODE BEGIN (1) */\r
+#include "cmd_proc_freertos_tms570.h"\r
+#include "FreeRTOS.h"\r
+#include "os_task.h"\r
+/* USER CODE END */\r
+\r
+\r
+/** @fn void main(void)\r
+* @brief Application main function\r
+* @note This function is empty by default.\r
+*\r
+* This function is called after startup.\r
+* The user can use this function to implement the application.\r
+*/\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+\r
+\r
+void main(void)\r
+ {\r
+/* USER CODE BEGIN (3) */\r
+ sciInit();\r
+ initCmdProc(1, (uint8_t*)"\r\nType commands\r\n", (uint8_t *)"--> ");\r
+ _enable_IRQ();\r
+\r
+ vTaskStartScheduler();\r
+ //We should never get here\r
+ while(1) ;\r
+\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
--- /dev/null
+;-------------------------------------------------------------------------------\r
+; sys_mpu.asm\r
+;\r
+; (c) Texas Instruments 2012, All rights reserved.\r
+;\r
+\r
+ .text\r
+ .arm\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Initalize Mpu\r
+\r
+ .def _mpuInit_\r
+ .asmfunc\r
+\r
+_mpuInit_\r
+ stmfd sp!, {r0}\r
+ ; Disable mpu\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ bic r0, r0, #1\r
+ dsb\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ isb\r
+ ; Disable background region\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ bic r0, r0, #0x20000\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ ; Setup region 1\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r1Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0008\r
+ orr r0, r0, #0x1000\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1)) \r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 2\r
+ mov r0, #1\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r2Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0008\r
+ orr r0, r0, #0x0600\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region \r
+ mov r0, #2\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r3Base\r
+ mcr p15, #0, r0, c6, c1, #0 \r
+ mov r0, #0x0008\r
+ orr r0, r0, #0x0300\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 4\r
+ mov r0, #3\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r4Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0008\r
+ orr r0, r0, #0x0300\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x11 << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 5\r
+ mov r0, #4\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r5Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0000\r
+ orr r0, r0, #0x0300\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x19 << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 6\r
+ mov r0, #5\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r6Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0000\r
+ orr r0, r0, #0x0300\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 7\r
+ mov r0, #6\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r7Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0008\r
+ orr r0, r0, #0x1200\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 8\r
+ mov r0, #7\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r8Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0010\r
+ orr r0, r0, #0x1300\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 9\r
+ mov r0, #8\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r9Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0010\r
+ orr r0, r0, #0x1300\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x08 << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 10\r
+ mov r0, #9\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r10Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0010\r
+ orr r0, r0, #0x1300\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x17 << 1) + (1))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 11\r
+ mov r0, #10\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r11Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0008\r
+ orr r0, r0, #0x1100\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x0A << 1) + (0))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ ; Setup region 12\r
+ mov r0, #11\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ ldr r0, r12Base\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ mov r0, #0x0008\r
+ orr r0, r0, #0x1300\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (0))\r
+ mcr p15, #0, r0, c6, c1, #2\r
+\r
+\r
+ ; Enable mpu background region\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ orr r0, r0, #0x20000\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ ; Enable mpu\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ orr r0, r0, #1\r
+ dsb\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ isb\r
+ ldmfd sp!, {r0}\r
+ bx lr\r
+\r
+r1Base .word 0x00000000 \r
+r2Base .word 0x00000000 \r
+r3Base .word 0x08000000 \r
+r4Base .word 0x08400000 \r
+r5Base .word 0x60000000 \r
+r6Base .word 0x80000000 \r
+r7Base .word 0xF0000000 \r
+r8Base .word 0xFC000000 \r
+r9Base .word 0xFE000000 \r
+r10Base .word 0xFF000000 \r
+r11Base .word 0x08001000 \r
+r12Base .word 0x20000000 \r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Mpu\r
+\r
+ .def _mpuEnable_\r
+ .asmfunc\r
+\r
+_mpuEnable_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ orr r0, r0, #1\r
+ dsb\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ isb\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable Mpu\r
+\r
+ .def _mpuDisable_\r
+ .asmfunc\r
+\r
+_mpuDisable_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ bic r0, r0, #1\r
+ dsb\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ isb\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Mpu background region\r
+\r
+ .def _mpuEnableBackgroundRegion_\r
+ .asmfunc\r
+\r
+_mpuEnableBackgroundRegion_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ orr r0, r0, #0x20000\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable Mpu background region\r
+\r
+ .def _mpuDisableBackgroundRegion_\r
+ .asmfunc\r
+\r
+_mpuDisableBackgroundRegion_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ bic r0, r0, #0x20000\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ ldmfd sp!, {r0}\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Returns number of implemented Mpu regions\r
+\r
+ .def _mpuGetNumberOfRegions_\r
+ .asmfunc\r
+\r
+_mpuGetNumberOfRegions_\r
+\r
+ mrc p15, #0, r0, c0, c0, #4\r
+ uxtb r0, r0, ROR #8\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Returns the type of the implemented mpu regions\r
+\r
+ .def _mpuAreRegionsSeparate_\r
+ .asmfunc\r
+\r
+_mpuAreRegionsSeparate_\r
+\r
+ mrc p15, #0, r0, c0, c0, #4\r
+ uxtb r0, r0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Set mpu region number\r
+\r
+ .def _mpuSetRegion_\r
+ .asmfunc\r
+\r
+_mpuSetRegion_\r
+\r
+ mcr p15, #0, r0, c6, c2, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get mpu region number\r
+\r
+ .def _mpuGetRegion_\r
+ .asmfunc\r
+\r
+_mpuGetRegion_\r
+\r
+ mrc p15, #0, r0, c6, c2, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Set base address\r
+\r
+ .def _mpuSetRegionBaseAddress_\r
+ .asmfunc\r
+\r
+_mpuSetRegionBaseAddress_\r
+\r
+ mcr p15, #0, r0, c6, c1, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get base address\r
+\r
+ .def _mpuGetRegionBaseAddress_\r
+ .asmfunc\r
+\r
+_mpuGetRegionBaseAddress_\r
+\r
+ mrc p15, #0, r0, c6, c1, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Set type and permission\r
+\r
+ .def _mpuSetRegionTypeAndPermission_\r
+ .asmfunc\r
+\r
+_mpuSetRegionTypeAndPermission_\r
+\r
+ orr r0, r0, r1\r
+ mcr p15, #0, r0, c6, c1, #4\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get type\r
+\r
+ .def _mpuGetRegionType_\r
+ .asmfunc\r
+\r
+_mpuGetRegionType_\r
+\r
+ mrc p15, #0, r0, c6, c1, #4\r
+ bic r0, r0, #0xFF00\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get permission\r
+\r
+ .def _mpuGetRegionPermission_\r
+ .asmfunc\r
+\r
+_mpuGetRegionPermission_\r
+\r
+ mrc p15, #0, r0, c6, c1, #4\r
+ bic r0, r0, #0xFF\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Set region size register value\r
+\r
+ .def _mpuSetRegionSizeRegister_\r
+ .asmfunc\r
+\r
+_mpuSetRegionSizeRegister_\r
+\r
+ mcr p15, #0, r0, c6, c1, #2\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+ \r
+\r
+;-------------------------------------------------------------------------------\r
+\r
--- /dev/null
+/** @file sys_phantom.c \r
+* @brief Phantom Interrupt Source File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+* This file contains:\r
+* - Phantom Interrupt Handler\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Phantom Interrupt Handler */\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+#pragma INTERRUPT(phantomInterrupt, IRQ)\r
+\r
+void phantomInterrupt(void)\r
+{\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+}\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
--- /dev/null
+;-------------------------------------------------------------------------------\r
+; sys_pmu.asm\r
+;\r
+; (c) Texas Instruments 2012, All rights reserved.\r
+;\r
+\r
+ .text\r
+ .arm\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Initialize Pmu\r
+; Note: It will reset all counters\r
+\r
+ .def _pmuInit_\r
+ .asmfunc\r
+\r
+_pmuInit_\r
+\r
+ stmfd sp!, {r0}\r
+ ; set control register\r
+ mrc p15, #0, r0, c9, c12, #0 \r
+ orr r0, r0, #(1 << 4) + 6 + 1\r
+ mcr p15, #0, r0, c9, c12, #0\r
+ ; clear flags\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c9, c12, #3 \r
+ ; select counter 0 event\r
+ mcr p15, #0, r0, c9, c12, #5 ; select counter\r
+ mov r0, #0x11\r
+ mcr p15, #0, r0, c9, c13, #1 ; select event\r
+ ; select counter 1 event\r
+ mov r0, #1\r
+ mcr p15, #0, r0, c9, c12, #5 ; select counter\r
+ mov r0, #0x11\r
+ mcr p15, #0, r0, c9, c13, #1 ; select event\r
+ ; select counter 2 event\r
+ mov r0, #2\r
+ mcr p15, #0, r0, c9, c12, #5 ; select counter\r
+ mov r0, #0x11\r
+ mcr p15, #0, r0, c9, c13, #1 ; select event\r
+ ldmfd sp!, {r0}\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Counters Global [Cycle, Event [0..2]]\r
+; Note: It will reset all counters\r
+\r
+ .def _pmuEnableCountersGlobal_\r
+ .asmfunc\r
+\r
+_pmuEnableCountersGlobal_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c9, c12, #0 \r
+ orr r0, r0, #7\r
+ mcr p15, #0, r0, c9, c12, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable Counters Global [Cycle, Event [0..2]]\r
+\r
+ .def _pmuDisableCountersGlobal_\r
+ .asmfunc\r
+\r
+_pmuDisableCountersGlobal_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c9, c12, #0 \r
+ bic r0, r0, #1\r
+ mcr p15, #0, r0, c9, c12, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Reset Cycle Counter\r
+\r
+ .def _pmuResetCycleCounter_\r
+ .asmfunc\r
+\r
+_pmuResetCycleCounter_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c9, c12, #0 \r
+ orr r0, r0, #4\r
+ mcr p15, #0, r0, c9, c12, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Reset Event Counters [0..2]\r
+\r
+ .def _pmuResetEventCounters_\r
+ .asmfunc\r
+\r
+_pmuResetEventCounters_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c9, c12, #0 \r
+ orr r0, r0, #2\r
+ mcr p15, #0, r0, c9, c12, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Reset Cycle Counter abd Event Counters [0..2]\r
+\r
+ .def _pmuResetCounters_\r
+ .asmfunc\r
+\r
+_pmuResetCounters_\r
+\r
+ stmfd sp!, {r0}\r
+ mrc p15, #0, r0, c9, c12, #0 \r
+ orr r0, r0, #6\r
+ mcr p15, #0, r0, c9, c12, #0\r
+ ldmfd sp!, {r0} \r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Start Counters [Cycle, 0..2]\r
+\r
+ .def _pmuStartCounters_\r
+ .asmfunc\r
+\r
+_pmuStartCounters_\r
+\r
+ mcr p15, #0, r0, c9, c12, #1\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Stop Counters [Cycle, 0..2]\r
+\r
+ .def _pmuStopCounters_\r
+ .asmfunc\r
+\r
+_pmuStopCounters_\r
+\r
+ mcr p15, #0, r0, c9, c12, #2\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Set Count event\r
+\r
+ .def _pmuSetCountEvent_\r
+ .asmfunc\r
+\r
+_pmuSetCountEvent_\r
+ \r
+ lsr r0, r0, #1\r
+ mcr p15, #0, r0, c9, c12, #5 ; select counter\r
+ mcr p15, #0, r1, c9, c13, #1 ; select event\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get Cycle Count\r
+\r
+ .def _pmuGetCycleCount_\r
+ .asmfunc\r
+\r
+_pmuGetCycleCount_\r
+\r
+ mrc p15, #0, r0, c9, c13, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get Event Counter Count Value\r
+\r
+ .def _pmuGetEventCount_\r
+ .asmfunc\r
+\r
+_pmuGetEventCount_\r
+\r
+ lsr r0, r0, #1\r
+ mcr p15, #0, r0, c9, c12, #5 ; select counter\r
+ mrc p15, #0, r0, c9, c13, #2 ; read event counter\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get Overflow Flags\r
+\r
+ .def _pmuGetOverflow_\r
+ .asmfunc\r
+\r
+_pmuGetOverflow_\r
+\r
+ mrc p15, #0, r0, c9, c12, #3 ; read overflow\r
+ mov r1, #0\r
+ mcr p15, #0, r1, c9, c12, #3 ; clear flags\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+ \r
+\r
+;-------------------------------------------------------------------------------\r
+\r
--- /dev/null
+/** @file sys_selftest.c \r
+* @brief Selftest Source File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+* This file contains:\r
+* - Selftest API's\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+#include "sys_selftest.h"\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+/** @fn void ccmSelfCheck(void)\r
+* @brief CCM module self check Driver\r
+*\r
+* This function self checks the CCM module.\r
+*/\r
+void ccmSelfCheck(void)\r
+{\r
+ /* Run a diagnostic check on the CCM-R4F module */\r
+ /* This step ensures that the CCM-R4F can actually indicate an error */\r
+\r
+ /* Configure CCM in self-test mode */\r
+ CCMKEYR = 0x6; \r
+ /* Wait for CCM self-test to complete */\r
+ while ((CCMSR & 0x100) != 0x100);\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+ \r
+ /* Check if there was an error during the self-test */\r
+ if ((CCMSR & 0x1) == 0x1)\r
+ {\r
+ /* STE is set */\r
+ ccmFail(0); \r
+ }\r
+ else\r
+ {\r
+ /* Check CCM-R4 self-test error flag by itself (without compare error) */\r
+ \r
+ /* Configure CCM in self-test error-forcing mode */\r
+ CCMKEYR = 0xF; \r
+ if ((esmREG->ESTATUS1[0] & 0x80000000) != 0x80000000)\r
+ {\r
+ /* ESM flag is not set */\r
+ ccmFail(1); \r
+ }\r
+ else\r
+ {\r
+ /* clear ESM group1 channel 31 flag */\r
+ esmREG->ESTATUS1[0] = 0x80000000; \r
+ \r
+ /* Configure CCM in error-forcing mode */\r
+ CCMKEYR = 0x9;\r
+ \r
+ /* check if compare error flag is set */\r
+ if ((esmREG->ESTATUS1[1] & 0x4) != 0x4)\r
+ {\r
+ /* ESM flag is not set */\r
+ ccmFail(2);\r
+ }\r
+ else\r
+ {\r
+ /* clear ESM group2 channel 2 flag */ \r
+ esmREG->ESTATUS1[1] = 0x4;\r
+ \r
+ /* clear ESM group2 shadow status flag */\r
+ esmREG->ESTATUS5EMU = 0x4; \r
+ \r
+ /* ESM self-test error needs to also be cleared */\r
+ esmREG->ESTATUS1[0] = 0x80000000; \r
+ \r
+ /* Clear CCM-R4 CMPE flag */\r
+ CCMSR = 0x00010000;\r
+\r
+ /* Return CCM-R4 to lock-step mode */\r
+ CCMKEYR = 0x0;\r
+ \r
+ /* The nERROR pin will become inactive once the LTC counter expires */\r
+ esmREG->KEY = 0x5; \r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+/** @fn void ccmFail(unsigned int x)\r
+* @brief CCM module fail service routine\r
+*\r
+* This function is called if CCM module selftest fail.\r
+*/\r
+void ccmFail(unsigned int x)\r
+{\r
+ if (x == 0)\r
+ {\r
+ /* CCM-R4 is not able to flag a compare error in self-test mode.\r
+ * Lock-step operation cannot be verified.\r
+ */\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+ }\r
+ else if (x == 1)\r
+ {\r
+ /* CCM-R4 self-test error flag is not set in ESM register.\r
+ * Could be due to a connection issue inside the part.\r
+ */\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+ }\r
+ else if (x == 2)\r
+ {\r
+ /* CCM-R4 compare error flag is not set in ESM.\r
+ * Lock-step operation cannot be verified.\r
+ */\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+ }\r
+}\r
+\r
+/** @fn void _memoryInit_(unsigned int ram)\r
+* @brief Memory Initialization Driver\r
+*\r
+* This function is called to perform Memory initialization of selected RAM's.\r
+*/\r
+void _memoryInit_(unsigned int ram)\r
+{\r
+ /* Enable Memory Hardware Initialization */\r
+ systemREG1->MINITGCR = 0xA; \r
+ \r
+ /* Enable Memory Hardware Initialization for selected RAM's */\r
+ systemREG1->MSINENA = ram;\r
+ \r
+ /* Wait until Memory Hardware Initialization complete */\r
+ while( systemREG1->MSTCGSTAT & 0x00000100 != 1);\r
+ \r
+ /* Disable Memory Hardware Initialization */\r
+ systemREG1->MINITGCR = 0xA; \r
+}\r
+\r
+/** @fn void stcSelfCheck(void)\r
+* @brief STC module self check Driver\r
+*\r
+* This function is called to perform STC module self check.\r
+*/\r
+void stcSelfCheck(void)\r
+{\r
+ volatile int i = 0;\r
+\r
+ /* Run a diagnostic check on the CPU self-test controller */\r
+ /* First set up the STC clock divider as STC is only supported up to 90MHz */\r
+ \r
+ /* STC clock is now normal mode CPU clock frequency/2 = 180MHz/2 */\r
+ systemREG2->STCCLKDIV = 0x01000000; \r
+ \r
+ /* Select one test interval, restart self-test next time, 0x00010001 */\r
+ stcREG->STCGCR0 = 0x00010001; \r
+ \r
+ /* Enable comparator self-check and stuck-at-0 fault insertion in CPU, 0x1A */\r
+ stcREG->STCSCSCR = 0x1A; \r
+ \r
+ /* Maximum time-out period */\r
+ stcREG->STCTPR = 0xFFFFFFFF; \r
+\r
+ /* wait for 16 VBUS clock cycles at least */\r
+ for (i=0; i<16; i++); \r
+\r
+ /* Enable self-test */\r
+ stcREG->STCGCR1 = 0xA; \r
+ \r
+ /* wait for 16 VBUS clock cycles at least */\r
+ for (i=0; i<16; i++); \r
+\r
+/* USER CODE BEGIN (7) */\r
+/* USER CODE END */\r
+ \r
+ /* Idle the CPU so that the self-test can start */\r
+ _gotoCPUIdle_();\r
+\r
+}\r
+\r
+/** @fn void cpuSelfTest(unsigned int no_of_intervals, unsigned int max_timeout, boolean_t restart_test)\r
+* @brief CPU self test Driver\r
+* @param[in] no_of_intervals - Number of Test Intervals to be \r
+* @param[in] max_timeout - Maximun Timeout to complete selected test Intervals\r
+* @param[in] restart_test - Restart the test from Interval 0 or Continue from where it stopped.\r
+*\r
+* This function is called to perfrom CPU self test using STC module.\r
+*/\r
+void cpuSelfTest(unsigned int no_of_intervals, unsigned int max_timeout, boolean_t restart_test)\r
+{\r
+ volatile int i = 0;\r
+\r
+/* USER CODE BEGIN (8) */\r
+/* USER CODE END */\r
+ \r
+ /* Run specified no of test intervals starting from interval 0 */\r
+ /* Start test from interval 0 or continue the test. */ \r
+ stcREG->STCGCR0 = no_of_intervals << 16 \r
+ | (unsigned int) restart_test; \r
+ \r
+ /* Configure Maximum time-out period */\r
+ stcREG->STCTPR = max_timeout; \r
+ \r
+ /* wait for 16 VBUS clock cycles at least */\r
+ for (i=0; i<16; i++); \r
+\r
+ /* Enable self-test */\r
+ stcREG->STCGCR1 = 0xA; \r
+\r
+/* USER CODE BEGIN (9) */\r
+/* USER CODE END */\r
+ /* Idle the CPU so that the self-test can start */\r
+ \r
+ _gotoCPUIdle_();\r
+ \r
+}\r
+\r
+/** @fn void pbistSelfCheck(void)\r
+* @brief PBIST self test Driver\r
+*\r
+* This function is called to perfrom PBIST self test.\r
+*/\r
+void pbistSelfCheck(void)\r
+{\r
+ int i = 0;\r
+ /* Run a diagnostic check on the memory self-test controller */\r
+ /* First set up the PBIST ROM clock as this clock frequency is limited to 90MHz */\r
+ \r
+ /* PBIST ROM clock frequency = HCLK frequency /2 */\r
+ systemREG1->MSTGCR |= 0x00000100; \r
+ \r
+ /* Enable PBIST controller */\r
+ systemREG1->MSINENA = 0x1; \r
+ \r
+ /* clear MSTGENA field */\r
+ systemREG1->MSTGCR &= ~(0xF); \r
+ \r
+ /* Enable PBIST self-test */\r
+ systemREG1->MSTGCR |= 0xA; \r
+ \r
+ /* software loop to wait at least 32 VCLK cycles */\r
+ for (i = 0; i < 32; i++); \r
+\r
+/* USER CODE BEGIN (10) */\r
+/* USER CODE END */\r
+ \r
+ /* Enable PBIST clocks and ROM clock */\r
+ pbistREG->PACT = 0x3; \r
+ \r
+ /* Select algo#3, march13n to be run */\r
+ pbistREG->ALGO = 0x00000004; \r
+ \r
+ /* Select RAM Group 1, which is actually the PBIST ROM */\r
+ pbistREG->RINFOL = 0x1; \r
+ \r
+ /* ROM contents will not override ALGO and RINFOx settings */\r
+ pbistREG->OVER = 0x0; \r
+ \r
+ /* Algorithm code is loaded from ROM */\r
+ pbistREG->ROM = 0x3; \r
+ \r
+ /* Start PBIST */\r
+ pbistREG->DLR = 0x14; \r
+ \r
+ /* wait until memory self-test done is indicated */\r
+ while ((systemREG1->MSTCGSTAT & 0x1) != 0x1); \r
+ \r
+ /* Check for the failure */\r
+ if (((pbistREG->FSRF0 & 0x1) != 0x1) & ((pbistREG->FSRF1 & 0x1) != 0x1))\r
+ {\r
+ /* no failure was indicated even if the march13n algorithm was run on a ROM */\r
+ pbistSelfCheckFail();\r
+/* USER CODE BEGIN (11) */\r
+/* USER CODE END */\r
+ }\r
+ else \r
+ {\r
+ /* PBIST self-check has passed */\r
+ \r
+ /* Disable PBIST clocks and ROM clock */\r
+ pbistREG->PACT = 0x0; \r
+ \r
+ /* Disable PBIST */\r
+ systemREG1->MSTGCR &= ~(0xF); \r
+ systemREG1->MSTGCR |= 0x5;\r
+ \r
+/* USER CODE BEGIN (12) */\r
+/* USER CODE END */\r
+ }\r
+}\r
+\r
+/** @fn void pbistSelfCheckFail(void)\r
+* @brief PBIST self test Driver failure service routine\r
+*\r
+* This function is called on PBIST self test failure.\r
+*/\r
+void pbistSelfCheckFail(void)\r
+{\r
+ /* The PBIST controller is not capable of reporting a failure.\r
+ * PBIST cannot be used to verify memory integrity.\r
+ * Need custom handler here.\r
+ */\r
+}\r
+\r
+/** @fn void pbistRun(unsigned int raminfoL, unsigned int algomask)\r
+* @brief CPU self test Driver\r
+* @param[in] raminfoL - Select the list of RAM to be tested.\r
+* @param[in] algomask - Select the list of Algorithm to be run.\r
+*\r
+* This function performs Memory Built-in Self test using PBIST module.\r
+*/\r
+void pbistRun(unsigned int raminfoL, unsigned int algomask)\r
+{\r
+ int i = 0;\r
+ \r
+ /* PBIST ROM clock frequency = HCLK frequency /2 */\r
+ systemREG1->MSTGCR |= 0x00000100; \r
+ \r
+ /* Enable PBIST controller */\r
+ systemREG1->MSINENA = 0x1; \r
+ \r
+ /* clear MSTGENA field */\r
+ systemREG1->MSTGCR &= ~(0xF); \r
+ \r
+ /* Enable PBIST self-test */\r
+ systemREG1->MSTGCR |= 0xA; \r
+ \r
+ /* software loop to wait at least 32 VCLK cycles */\r
+ for (i = 0; i < 32; i++); \r
+\r
+/* USER CODE BEGIN (13) */\r
+/* USER CODE END */\r
+ \r
+ /* Enable PBIST clocks and ROM clock */\r
+ pbistREG->PACT = 0x3; \r
+ \r
+ /* Select all algorithms to be tested */\r
+ pbistREG->ALGO = algomask; \r
+ \r
+ /* Select RAM groups */\r
+ pbistREG->RINFOL = raminfoL; \r
+ \r
+ /* Select all RAM groups */\r
+ pbistREG->RINFOU = 0x00000000; \r
+ \r
+ /* ROM contents will not override RINFOx settings */\r
+ pbistREG->OVER = 0x0; \r
+ \r
+ /* Algorithm code is loaded from ROM */\r
+ pbistREG->ROM = 0x3; \r
+ \r
+ /* Start PBIST */\r
+ pbistREG->DLR = 0x14; \r
+}\r
+\r
+/** @fn void pbistStop(void)\r
+* @brief Routine to stop PBIST test enabled.\r
+*\r
+* This function is called to stop PBIST after test is performed.\r
+*/\r
+void pbistStop(void)\r
+{\r
+/* USER CODE BEGIN (14) */\r
+/* USER CODE END */\r
+ /* disable pbist clocks and ROM clock */\r
+ pbistREG->PACT = 0x0; \r
+ systemREG1->MSTGCR &= ~(0xF);\r
+ systemREG1->MSTGCR |= 0x5;\r
+}\r
+\r
+/** @fn boolean_t pbistIsTestCompleted(void)\r
+* @brief Checks to see if the PBIST test is completed.\r
+* @return 1 if PBIST test completed, otherwise 0.\r
+*\r
+* Checks to see if the PBIST test is completed.\r
+*/\r
+boolean_t pbistIsTestCompleted(void)\r
+{\r
+/* USER CODE BEGIN (15) */\r
+/* USER CODE END */\r
+\r
+ return ((systemREG1->MSTCGSTAT & 0x1) != 0);\r
+}\r
+\r
+/** @fn boolean_t pbistIsTestPassed(void)\r
+* @brief Checks to see if the PBIST test is completed sucessfully.\r
+* @return 1 if PBIST test passed, otherwise 0.\r
+*\r
+* Checks to see if the PBIST test is completed sucessfully.\r
+*/\r
+boolean_t pbistIsTestPassed(void)\r
+{\r
+/* USER CODE BEGIN (16) */\r
+/* USER CODE END */\r
+\r
+ return ((pbistREG->FSRF0 || pbistREG->FSRF1) == 0);\r
+}\r
+\r
+/** @fn boolean_t pbistPortTestStatus(uint32_t port)\r
+* @brief Checks to see if the PBIST Port test is completed sucessfully.\r
+* @param[in] port - Select the port to get the status.\r
+* @return 1 if PBIST Port test completed sucessfully, otherwise 0.\r
+*\r
+* Checks to see if the selected PBIST Port test is completed sucessfully.\r
+*/\r
+boolean_t pbistPortTestStatus(uint32_t port)\r
+{\r
+ boolean_t status;\r
+/* USER CODE BEGIN (17) */\r
+/* USER CODE END */\r
+\r
+ if(port == PBIST_PORT0)\r
+ {\r
+ status = (pbistREG->FSRF0 == 0);\r
+ }\r
+ else\r
+ {\r
+ status = (pbistREG->FSRF1 == 0); \r
+ }\r
+ \r
+ return status;\r
+}\r
+\r
+/** @fn void efcCheck(void)\r
+* @brief EFUSE module self check Driver\r
+*\r
+* This function self checks the EFSUE module.\r
+*/\r
+void efcCheck(void)\r
+{\r
+ unsigned int efcStatus = 0;\r
+\r
+/* USER CODE BEGIN (18) */\r
+/* USER CODE END */\r
+ \r
+ /* read the EFC Error Status Register */\r
+ efcStatus = efcREG->ERROR; \r
+\r
+/* USER CODE BEGIN (19) */\r
+/* USER CODE END */\r
+ \r
+ if (efcStatus == 0x0)\r
+ {\r
+ /* run stuck-at-zero test and check if it passed */\r
+ if (efcStuckZeroTest()) \r
+ {\r
+ /* start EFC ECC logic self-test */\r
+ efcSelfTest(); \r
+ }\r
+ else\r
+ {\r
+ /* EFC output is stuck-at-zero, device operation unreliable */\r
+ efcClass2Error(); \r
+ }\r
+ }\r
+ /* EFC Error Register is not zero */\r
+ else \r
+ {\r
+ /* one-bit error detected during autoload */\r
+ if (efcStatus == 0x15) \r
+ {\r
+ /* start EFC ECC logic self-test */\r
+ efcSelfTest(); \r
+ }\r
+ else\r
+ {\r
+ /* Some other EFC error was detected */\r
+ efcClass2Error(); \r
+ }\r
+ }\r
+}\r
+\r
+/** @fn boolean_t efcStuckZeroTest(void)\r
+* @brief Checks to see if the EFUSE Stuck at zero test is completed sucessfully.\r
+* @return 1 if EFUSE Stuck at zero test completed, otherwise 0.\r
+*\r
+* Checks to see if the EFUSE Stuck at zero test is completed sucessfully.\r
+*/\r
+boolean_t efcStuckZeroTest(void)\r
+{\r
+ boolean_t result = FALSE;\r
+ unsigned int error_checks = EFC_INSTRUCTION_INFO_EN | \r
+ EFC_INSTRUCTION_ERROR_EN | \r
+ EFC_AUTOLOAD_ERROR_EN | \r
+ EFC_SELF_TEST_ERROR_EN ;\r
+ \r
+ /* configure the output enable for auto load error , instruction info,\r
+ instruction error, and self test error using boundary register \r
+ and drive values one across all the errors */\r
+ efcREG->BOUNDARY = (OUTPUT_ENABLE | error_checks);\r
+ \r
+ /* Read from the pin register. This register holds the current values \r
+ of above errors. This value should be 0x5c00.If not at least one of\r
+ the above errors is stuck at 0. */\r
+ if ((efcREG->PINS & 0x5C00) == 0x5C00)\r
+ {\r
+ /* check if the ESM group1 channels 40 is set and group3 channel 2 is set */\r
+ if (((esmREG->ESTATUS4[0] & 0x200) == 0x200) & ((esmREG->ESTATUS1[2] & 0x2) == 0x2))\r
+ {\r
+ /* stuck-at-zero test passed */\r
+ result = TRUE; \r
+ }\r
+ }\r
+ \r
+ /* put the pins back low */\r
+ efcREG->BOUNDARY = OUTPUT_ENABLE;\r
+ \r
+ /* clear group1 flags */\r
+ esmREG->ESTATUS4[0] = 0x300;\r
+ \r
+ /* clear group3 flag */\r
+ esmREG->ESTATUS1[2] = 0x2; \r
+ \r
+ /* The nERROR pin will become inactive once the LTC counter expires */\r
+ esmREG->KEY = 0x5; \r
+\r
+ return result;\r
+}\r
+\r
+/** @fn void efcSelfTest(void)\r
+* @brief EFUSE module self check Driver\r
+*\r
+* This function self checks the EFSUE module.\r
+*/\r
+void efcSelfTest(void)\r
+{\r
+ /* configure self-test cycles */\r
+ efcREG->SELF_TEST_CYCLES = 0x258;\r
+ \r
+ /* configure self-test signature */\r
+ efcREG->SELF_TEST_SIGN = 0x5362F97F;\r
+ \r
+ /* configure boundary register to start ECC self-test */\r
+ efcREG->BOUNDARY = 0x0000200F;\r
+}\r
+\r
+/** @fn boolean_t checkefcSelfTest(void)\r
+* @brief EFUSE module self check Driver\r
+*\r
+* This function self checks the EFSUE module.\r
+*/\r
+boolean_t checkefcSelfTest(void)\r
+{\r
+ boolean_t result = FALSE;\r
+ \r
+ /* wait until EFC self-test is done */\r
+ while(!(efcREG->PINS & EFC_SELF_TEST_DONE));\r
+ \r
+ /* check if EFC self-test error occurred */\r
+ if (!(efcREG->PINS & EFC_SELF_TEST_ERROR) & !(efcREG->ERROR & SELF_TEST_ERROR))\r
+ {\r
+ /* check if EFC self-test error is set */\r
+ if ((esmREG->ESTATUS4[0] & 0x100) != 0x100) \r
+ {\r
+ result = TRUE;\r
+ }\r
+ }\r
+ return result;\r
+}\r
+\r
+/** @fn void efcClass1Error(void)\r
+* @brief EFUSE Class1 Error service routine\r
+*\r
+* This function is called if EFC ECC logic self-test.\r
+*/\r
+void efcClass1Error(void)\r
+{\r
+ /* Autoload error was detected during device power-up, and device operation is not reliable. */\r
+ while(1);\r
+}\r
+\r
+/** @fn void efcClass2Error(void)\r
+* @brief EFUSE Class2 Error service routine\r
+*\r
+* This function is called if EFC output is stuck-at-zero.\r
+*/\r
+void efcClass2Error(void)\r
+{\r
+ /* The ECC logic inside the eFuse controller is not operational. Device operation is not reliable. */\r
+ while(1);\r
+}\r
+\r
+/** @fn void fmcBus2Check(void)\r
+* @brief Self Check Flash Bus2 Interface\r
+*\r
+* This function self checks Flash Bus2 Interface\r
+*/\r
+void fmcBus2Check(void)\r
+{\r
+ /* enable ECC logic inside FMC */\r
+ flashWREG->FEDACCTRL1 = 0x000A060A; \r
+\r
+ if (esmREG->ESTATUS1[0] & 0x40)\r
+ {\r
+ /* a 1-bit error was detected during flash OTP read by flash module\r
+ run a self-check on ECC logic inside FMC */\r
+ \r
+ /* clear ESM group1 channel 6 flag */\r
+ esmREG->ESTATUS1[0] = 0x40; \r
+ \r
+ fmcECCcheck();\r
+ }\r
+ \r
+ /* no 2-bit or 1-bit error detected during power-up */\r
+ else \r
+ {\r
+ fmcECCcheck();\r
+ }\r
+}\r
+\r
+/** @fn void fmcECCcheck(void)\r
+* @brief Check Flash ECC Single Bit and multi Bit errors detection logic.\r
+*\r
+* This function Checks Flash ECC Single Bit and multi Bit errors detection logic.\r
+*/\r
+void fmcECCcheck(void)\r
+{\r
+ volatile unsigned int otpread;\r
+ volatile unsigned int temp;\r
+\r
+ /* read location with deliberate 1-bit error */\r
+ otpread = flash1bitError; \r
+ if (esmREG->ESTATUS1[0] & 0x40)\r
+ {\r
+ /* 1-bit failure was indicated and corrected */\r
+ flashWREG->FEDACSTATUS = 0x00010006;\r
+ \r
+ /* clear ESM group1 channel 6 flag */\r
+ esmREG->ESTATUS1[0] = 0x40; \r
+ \r
+ /* read location with deliberate 2-bit error */\r
+ otpread = flash2bitError; \r
+ if (esmREG->ESTATUS1[2] & 0x80)\r
+ {\r
+ /* 2-bit failure was detected correctly */\r
+ temp = flashWREG->FUNCERRADD;\r
+ flashWREG->FEDACSTATUS = 0x00020100;\r
+ \r
+ /* clear ESM group3 channel 7 */\r
+ esmREG->ESTATUS1[2] = 0x80; \r
+ \r
+ /* The nERROR pin will become inactive once the LTC counter expires */\r
+ esmREG->KEY = 0x5; \r
+\r
+ }\r
+ else\r
+ {\r
+ /* ECC logic inside FMC cannot detect 2-bit error */\r
+ fmcClass2Error(); \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* ECC logic inside FMC cannot detect 1-bit error */\r
+ fmcClass2Error(); \r
+ }\r
+}\r
+\r
+/** @fn void fmcClass1Error(void)\r
+* @brief Flash Multi bit ECC error service routine detected during reset configuration.\r
+*\r
+* This function is called if Flash Multi bit ECC error detected during reset configuration.\r
+*/\r
+void fmcClass1Error(void)\r
+{\r
+ /* there was a multi-bit error detected during the reset configuration word read from the OTP */\r
+ /* This affects the device power domains, endianness, and exception handling ISA */\r
+ /* Device operation is not reliable. */\r
+ while(1);\r
+}\r
+\r
+/** @fn void fmcClass2Error(void)\r
+* @brief Flash OTP or EEPROM read Multi bit ECC error service routine\r
+*\r
+* This function is called if Flash OTP or EEPROM read Multi bit ECC error detected.\r
+*/\r
+void fmcClass2Error(void)\r
+{\r
+ /* The ECC logic inside FMC used to protect against 1-bit and 2-bit errors in OTP and EEPROM banks */\r
+ /* is not operational. Device operation is not reliable. */\r
+ while(1);\r
+}\r
+\r
+/** @fn void checkB0RAMECC(void)\r
+* @brief Check TCRAM1 ECC error detection logic.\r
+*\r
+* This function checks TCRAM1 ECC error detection logic.\r
+*/\r
+void checkB0RAMECC(void)\r
+{\r
+ volatile unsigned int ramread = 0;\r
+\r
+ /* enable writes to ECC RAM, enable ECC error response */\r
+ tcram1REG->RAMCTRL = 0x0005010A; \r
+ tcram2REG->RAMCTRL = 0x0005010A;\r
+\r
+ /* the first 1-bit error will cause an error response */\r
+ tcram1REG->RAMTHRESHOLD = 0x1; \r
+ tcram2REG->RAMTHRESHOLD = 0x1;\r
+\r
+ /* allow SERR to be reported to ESM */\r
+ tcram1REG->RAMINTCTRL = 0x1; \r
+ tcram2REG->RAMINTCTRL = 0x1;\r
+ \r
+ /* cause a 1-bit ECC error */\r
+ tcramA1bitError ^= 0x1; \r
+ \r
+ /* disable writes to ECC RAM */\r
+ tcram1REG->RAMCTRL = 0x0005000A; \r
+ tcram2REG->RAMCTRL = 0x0005000A;\r
+\r
+ /* read from location with 1-bit ECC error */\r
+ ramread = tcramA1bit; \r
+ \r
+ /* SERR not set in TCRAM1 or TCRAM2 modules */\r
+ if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1))) \r
+ {\r
+ /* TCRAM module does not reflect 1-bit error reported by CPU */\r
+ tcramClass2Error(); \r
+ }\r
+ else\r
+ {\r
+ /* clear SERR flag */\r
+ tcram1REG->RAMERRSTATUS = 0x1; \r
+ tcram2REG->RAMERRSTATUS = 0x1;\r
+ \r
+ /* clear status flags for ESM group1 channels 26 and 28 */\r
+ esmREG->ESTATUS1[0] = 0x14000000; \r
+ }\r
+\r
+ /* enable writes to ECC RAM, enable ECC error response */\r
+ tcram1REG->RAMCTRL = 0x0005010A; \r
+ tcram2REG->RAMCTRL = 0x0005010A;\r
+\r
+ /* cause a 2-bit ECC error */\r
+ tcramA2bitError ^= 0x3; \r
+ ramread = tcram1REG->RAMCTRL;\r
+ ramread = tcram2REG->RAMCTRL;\r
+\r
+ /* read from location with 2-bit ECC error this will cause a data abort to be generated */\r
+ ramread = tcramA2bit; \r
+}\r
+\r
+/** @fn void checkB1RAMECC(void)\r
+* @brief Check TCRAM2 ECC error detection logic.\r
+*\r
+* This function checks TCRAM2 ECC error detection logic.\r
+*/\r
+void checkB1RAMECC(void)\r
+{\r
+ volatile unsigned int ramread = 0;\r
+\r
+ /* enable writes to ECC RAM, enable ECC error response */\r
+ tcram1REG->RAMCTRL = 0x0005010A; \r
+ tcram2REG->RAMCTRL = 0x0005010A;\r
+ \r
+ /* the first 1-bit error will cause an error response */\r
+ tcram1REG->RAMTHRESHOLD = 0x1; \r
+ tcram2REG->RAMTHRESHOLD = 0x1;\r
+\r
+ /* allow SERR to be reported to ESM */\r
+ tcram1REG->RAMINTCTRL = 0x1; \r
+ tcram2REG->RAMINTCTRL = 0x1;\r
+\r
+ /* cause a 1-bit ECC error */\r
+ tcramB1bitError ^= 0x1; \r
+ \r
+ /* disable writes to ECC RAM */\r
+ tcram1REG->RAMCTRL = 0x0005000A; \r
+ tcram2REG->RAMCTRL = 0x0005000A;\r
+\r
+ /* read from location with 1-bit ECC error */\r
+ ramread = tcramB1bit; \r
+ \r
+ /* SERR not set in TCRAM1 or TCRAM2 modules */\r
+ if (!((tcram1REG->RAMERRSTATUS & 1) || (tcram2REG->RAMERRSTATUS & 1))) \r
+ {\r
+ /* TCRAM module does not reflect 1-bit error reported by CPU */\r
+ tcramClass2Error(); \r
+ }\r
+ else\r
+ {\r
+ /* clear SERR flag */\r
+ tcram1REG->RAMERRSTATUS = 0x1; \r
+ tcram2REG->RAMERRSTATUS = 0x1;\r
+ \r
+ /* clear status flags for ESM group1 channels 26 and 28 */\r
+ esmREG->ESTATUS1[0] = 0x14000000; \r
+ }\r
+\r
+ /* enable writes to ECC RAM, enable ECC error response */\r
+ tcram1REG->RAMCTRL = 0x0005010A; \r
+ tcram2REG->RAMCTRL = 0x0005010A;\r
+ \r
+ /* cause a 2-bit ECC error */\r
+ tcramB2bitError ^= 0x3; \r
+ \r
+ /* disable writes to ECC RAM */\r
+ tcram1REG->RAMCTRL = 0x0005000A; \r
+ tcram2REG->RAMCTRL = 0x0005000A;\r
+}\r
+\r
+/** @fn void tcramClass1Error(void)\r
+* @brief Error service routine called if TCRAM module cannot capture 2-bit error.\r
+*\r
+* Error service routine called if TCRAM module cannot respond to 2-bit error.\r
+*/\r
+void tcramClass1Error(void)\r
+{\r
+ /* TCRAM module is not capable of responding to 2-bit error indicated by CPU.\r
+ * Device operation is not reliable and not recommended.\r
+ */\r
+ while(1);\r
+}\r
+\r
+/** @fn void tcramClass2Error(void)\r
+* @brief Error service routine called if TCRAM module cannot capture 1-bit error.\r
+*\r
+* Error service routine called if TCRAM module cannot respond to 1-bit error.\r
+*/\r
+void tcramClass2Error(void)\r
+{\r
+ /* TCRAM module is not capable of responding to 1-bit error indicated by CPU.\r
+ * Device operation is possible, but is prone to future multi-bit errors not being detected.\r
+ * Need custom handler here instead of the infinite loop.\r
+ */\r
+ while(1);\r
+}\r
+\r
+/** @fn void checkFlashECC(void)\r
+* @brief Check Flash ECC error detection logic.\r
+*\r
+* This function checks Flash ECC error detection logic.\r
+*/\r
+void checkFlashECC(void)\r
+{\r
+ /* Routine to check operation of ECC logic inside CPU for accesses to program flash */\r
+ volatile unsigned int flashread = 0;\r
+\r
+ /* Flash Module ECC Response enabled */\r
+ flashWREG->FEDACCTRL1 = 0x000A060A; \r
+ \r
+ /* Enable diagnostic mode and select diag mode 7 */\r
+ flashWREG->FDIAGCTRL = 0x00050007; \r
+ \r
+ /* Select ECC diagnostic mode, single-bit to be corrupted */\r
+ flashWREG->FPAROVR = 0x00005401; \r
+ \r
+ /* Set the trigger for the diagnostic mode */\r
+ flashWREG->FDIAGCTRL |= 0x01000000; \r
+ \r
+ /* read a flash location from the mirrored memory map */\r
+ flashread = flashBadECC; \r
+ \r
+ /* disable diagnostic mode */\r
+ flashWREG->FDIAGCTRL = 0x000A0007; \r
+\r
+ /* this will have caused a single-bit error to be generated and corrected by CPU */\r
+ /* single-bit error not captured in flash module */\r
+ if (!(flashWREG->FEDACSTATUS & 0x2)) \r
+ {\r
+ flashClass2Error();\r
+ }\r
+ else\r
+ {\r
+ /* clear single-bit error flag */\r
+ flashWREG->FEDACSTATUS = 0x2; \r
+\r
+ /* clear ESM flag */\r
+ esmREG->ESTATUS1[0] = 0x40; \r
+\r
+ /* Enable diagnostic mode and select diag mode 7 */\r
+ flashWREG->FDIAGCTRL = 0x00050007; \r
+ \r
+ /* Select ECC diagnostic mode, two bits of ECC to be corrupted */\r
+ flashWREG->FPAROVR = 0x00005A03; \r
+ \r
+ /* Set the trigger for the diagnostic mode */\r
+ flashWREG->FDIAGCTRL |= 0x01000000; \r
+\r
+ /* read from flash location from mirrored memory map this will cause a data abort */\r
+ flashread = flashBadECC; \r
+ }\r
+\r
+}\r
+\r
+/** @fn void flashClass1Error(void)\r
+* @brief Error service routine called if Flash module cannot capture 2-bit error.\r
+*\r
+* Error service routine called if Flash module cannot capture 2-bit error.\r
+*/\r
+void flashClass1Error(void)\r
+{\r
+ /* Flash module not able to capture 2-bit error from CPU.\r
+ * Device operation not reliable.\r
+ */\r
+ while(1);\r
+\r
+}\r
+\r
+/** @fn void flashClass2Error(void)\r
+* @brief Error service routine called if Flash module cannot capture 1-bit error.\r
+*\r
+* Error service routine called if Flash module cannot capture 1-bit error.\r
+*/\r
+void flashClass2Error(void)\r
+{\r
+ /* Flash module not able to capture 1-bit error from CPU.\r
+ * Device operation possible if this weakness in diagnostic is okay.\r
+ */\r
+}\r
+\r
+/** @fn void custom_dabort(void)\r
+* @brief Custom Data abort routine for the application.\r
+*\r
+* Custom Data abort routine for the application.\r
+*/\r
+void custom_dabort(void)\r
+{\r
+ /* Need custom data abort handler here.\r
+ * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC logic.\r
+ */\r
+}\r
+\r
+/** @fn void stcSelfCheckFail(void)\r
+* @brief STC Self test check fail service routine\r
+*\r
+* This function is called if STC Self test check fail.\r
+*/\r
+void stcSelfCheckFail(void)\r
+{\r
+ /* CPU self-test controller's own self-test failed.\r
+ * It is not possible to verify that STC is capable of indicating a CPU self-test error.\r
+ * It is not recommended to continue operation.\r
+ */\r
+ while(1);\r
+}\r
+\r
+/** @fn void cpuSelfTestFail(void)\r
+* @brief CPU Self test check fail service routine\r
+*\r
+* This function is called if CPU Self test check fail.\r
+*/\r
+void cpuSelfTestFail(void)\r
+{\r
+ /* CPU self-test has failed.\r
+ * CPU operation is not reliable.\r
+ */\r
+ while(1);\r
+}\r
+\r
+\r
+/** @fn void vimParityCheck(void)\r
+* @brief Routine to check VIM RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check VIM RAM parity error detection and signaling mechanism\r
+*/\r
+void vimParityCheck(void)\r
+{\r
+ volatile unsigned int vimramread = 0;\r
+\r
+ /* Enable parity checking and parity test mode */\r
+ VIM_PARCTL = 0x0000010A;\r
+ \r
+ /* flip a bit in the VIM RAM parity location */\r
+ VIMRAMPARLOC ^= 0x1; \r
+ \r
+ /* disable parity test mode */\r
+ VIM_PARCTL = 0x0000000A; \r
+\r
+ /* cause parity error */\r
+ vimramread = VIMRAMLOC; \r
+ \r
+ /* check if ESM group1 channel 15 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x8000)) \r
+ {\r
+ /* VIM RAM parity error was not flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop. */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear VIM RAM parity error flag in VIM */\r
+ VIM_PARFLG = 0x1; \r
+ \r
+ /* clear ESM group1 channel 15 flag */\r
+ esmREG->ESTATUS1[0] = 0x8000; \r
+ }\r
+}\r
+\r
+/** @fn void dmaParityCheck(void)\r
+* @brief Routine to check DMA control packet RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check DMA control packet RAM parity error detection and signaling mechanism\r
+*/\r
+void dmaParityCheck(void)\r
+{\r
+ volatile unsigned int dmaread = 0;\r
+\r
+ /* Enable parity checking and parity test mode */\r
+ DMA_PARCR = 0x0000010A; \r
+ \r
+ /* Flip a bit in DMA RAM parity location */\r
+ DMARAMPARLOC ^= 0x1; \r
+ \r
+ /* Disable parity test mode */\r
+ DMA_PARCR = 0x0000000A; \r
+ \r
+ /* Cause parity error */\r
+ dmaread = DMARAMLOC; \r
+ \r
+ /* Check if ESM group1 channel 3 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x8)) \r
+ {\r
+ /* DMA RAM parity error was not flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop. */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear DMA parity error flag in DMA */\r
+ DMA_PARADDR = 0x01000000; \r
+ \r
+ /* clear ESM group1 channel 3 flag */\r
+ esmREG->ESTATUS1[0] = 0x8; \r
+ }\r
+\r
+}\r
+\r
+/** @fn void het1ParityCheck(void)\r
+* @brief Routine to check HET1 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check HET1 RAM parity error detection and signaling mechanism\r
+*/\r
+void het1ParityCheck(void)\r
+{\r
+ volatile unsigned int nhetread = 0;\r
+\r
+ /* Set TEST mode and enable parity checking */\r
+ hetREG1->PCREG = 0x0000010A; \r
+ \r
+ /* flip parity bit */\r
+ NHET1RAMPARLOC ^= 0x1; \r
+ \r
+ /* Disable TEST mode */\r
+ hetREG1->PCREG = 0x0000000A; \r
+\r
+ /* read to cause parity error */\r
+ nhetread = NHET1RAMLOC; \r
+\r
+ /* check if ESM group1 channel 7 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x80)) \r
+ {\r
+ /* NHET1 RAM parity error was not flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop. */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear ESM group1 channel 7 flag */\r
+ esmREG->ESTATUS1[0] = 0x80; \r
+ }\r
+}\r
+\r
+/** @fn void htu1ParityCheck(void)\r
+* @brief Routine to check HTU1 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check HTU1 RAM parity error detection and signaling mechanism\r
+*/\r
+void htu1ParityCheck(void)\r
+{\r
+ volatile unsigned int hturead = 0;\r
+ /* Enable parity and TEST mode */\r
+ htuREG1->PCR = 0x0000010A; \r
+ \r
+ /* flip parity bit */ \r
+ HTU1PARLOC ^= 0x1; \r
+ \r
+ /* Disable parity RAM test mode */\r
+ htuREG1->PCR = 0x0000000A; \r
+ \r
+ /* read to cause parity error */\r
+ hturead = HTU1RAMLOC; \r
+ \r
+ /* check if ESM group1 channel 8 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x100)) \r
+ {\r
+ /* HTU1 RAM parity error was not flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop. */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* Clear HTU parity error flag */\r
+ htuREG1->PAR = 0x00010000; \r
+ esmREG->ESTATUS1[0] = 0x100;\r
+ }\r
+}\r
+\r
+/** @fn void het2ParityCheck(void)\r
+* @brief Routine to check HET2 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check HET2 RAM parity error detection and signaling mechanism\r
+*/\r
+void het2ParityCheck(void)\r
+{\r
+ volatile unsigned int nhetread = 0;\r
+ \r
+ /* Set TEST mode and enable parity checking */\r
+ hetREG2->PCREG = 0x0000010A; \r
+ \r
+ /* flip parity bit */\r
+ NHET2RAMPARLOC ^= 0x1; \r
+ \r
+ /* Disable TEST mode */\r
+ hetREG2->PCREG = 0x0000000A; \r
+\r
+ /* read to cause parity error */\r
+ nhetread = NHET2RAMLOC; \r
+\r
+ /* check if ESM group1 channel 7 or 34 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x80) && !(esmREG->ESTATUS4[0] & 0x4)) \r
+ {\r
+ /* NHET2 RAM parity error was not flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop. */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear ESM group1 channel 7 flag */\r
+ esmREG->ESTATUS1[0] = 0x80; \r
+ \r
+ /* clear ESM group1 channel 34 flag */\r
+ esmREG->ESTATUS4[0] = 0x4; \r
+ }\r
+}\r
+\r
+/** @fn void htu2ParityCheck(void)\r
+* @brief Routine to check HTU2 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check HTU2 RAM parity error detection and signaling mechanism\r
+*/\r
+void htu2ParityCheck(void)\r
+{\r
+ volatile unsigned int hturead = 0;\r
+\r
+ /* Enable parity and TEST mode */\r
+ htuREG2->PCR = 0x0000010A; \r
+ \r
+ /* flip parity bit */\r
+ HTU2PARLOC ^= 0x1; \r
+ \r
+ /* Disable parity RAM test mode */\r
+ htuREG2->PCR = 0x0000000A; \r
+\r
+ /* read to cause parity error */\r
+ hturead = HTU2RAMLOC; \r
+\r
+ /* check if ESM group1 channel 8 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x100)) \r
+ {\r
+ /* HTU2 RAM parity error was not flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop. */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* Clear HTU parity error flag */\r
+ htuREG2->PAR = 0x00010000; \r
+ esmREG->ESTATUS1[0] = 0x100;\r
+ }\r
+}\r
+\r
+/** @fn void adc1ParityCheck(void)\r
+* @brief Routine to check ADC1 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check ADC1 RAM parity error detection and signaling mechanism\r
+*/\r
+void adc1ParityCheck(void)\r
+{\r
+ volatile unsigned int adcramread = 0;\r
+\r
+ /* Set the TEST bit in the PARCR and enable parity checking */\r
+ adcREG1->PARCR = 0x10A; \r
+ \r
+ /* Invert the parity bits inside the ADC1 RAM's first location */\r
+ adcPARRAM1 = ~(adcPARRAM1); \r
+\r
+ /* clear the TEST bit */\r
+ adcREG1->PARCR = 0x00A; \r
+\r
+ /* This read is expected to trigger a parity error */\r
+ adcramread = adcRAM1; \r
+\r
+ /* Check for ESM group1 channel 19 to be flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x80000)) \r
+ {\r
+ /* no ADC1 RAM parity error was flagged to ESM */\r
+ /* Need custom routine to handle this failure instead of the infinite loop */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear ADC1 RAM parity error flag */\r
+ esmREG->ESTATUS1[0] = 0x80000; \r
+ }\r
+}\r
+\r
+/** @fn void adc2ParityCheck(void)\r
+* @brief Routine to check ADC2 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check ADC2 RAM parity error detection and signaling mechanism\r
+*/\r
+void adc2ParityCheck(void)\r
+{\r
+ volatile unsigned int adcramread = 0;\r
+\r
+ /* Set the TEST bit in the PARCR and enable parity checking */\r
+ adcREG2->PARCR = 0x10A; \r
+ \r
+ /* Invert the parity bits inside the ADC2 RAM's first location */\r
+ adcPARRAM2 = ~(adcPARRAM2); \r
+\r
+ /* clear the TEST bit */\r
+ adcREG2->PARCR = 0x00A; \r
+\r
+ /* This read is expected to trigger a parity error */\r
+ adcramread = adcRAM2; \r
+\r
+ /* Check for ESM group1 channel 1 to be flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x2)) \r
+ {\r
+ /* no ADC2 RAM parity error was flagged to ESM */\r
+ /* Need custom routine to handle this failure instead of the infinite loop */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear ADC2 RAM parity error flag */ \r
+ esmREG->ESTATUS1[0] = 0x2; \r
+ }\r
+}\r
+\r
+/** @fn void can1ParityCheck(void)\r
+* @brief Routine to check CAN1 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check CAN1 RAM parity error detection and signaling mechanism\r
+*/\r
+void can1ParityCheck(void)\r
+{\r
+ volatile unsigned int canread = 0;\r
+\r
+ /* Disable parity, init mode, TEST mode */\r
+ canREG1->CTL = 0x00001481; \r
+ \r
+ /* Enable RAM Direct Access mode */\r
+ canREG1->TEST = 0x00000200; \r
+\r
+ /* flip the parity bit */\r
+ canPARRAM1 ^= 0x00001000; \r
+\r
+ /* Enable parity, disable init, still TEST mode */\r
+ canREG1->CTL = 0x00002880; \r
+\r
+ /* Read location with parity error */\r
+ canread = canRAM1; \r
+\r
+ /* check if ESM group1 channel 21 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x00200000)) \r
+ {\r
+ /* No DCAN1 RAM parity error was flagged to ESM */\r
+ /* Need custom routine to handle this failure instead of the infinite loop */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear ESM group1 channel 21 flag */\r
+ esmREG->ESTATUS1[0] = 0x00200000; \r
+ \r
+ /* disable TEST mode */\r
+ canREG1->CTL = 0x00002800; \r
+ }\r
+}\r
+\r
+/** @fn void can2ParityCheck(void)\r
+* @brief Routine to check CAN2 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check CAN2 RAM parity error detection and signaling mechanism\r
+*/\r
+void can2ParityCheck(void)\r
+{\r
+ volatile unsigned int canread = 0;\r
+\r
+ /* Disable parity, init mode, TEST mode */\r
+ canREG2->CTL = 0x00001481; \r
+\r
+ /* Enable RAM Direct Access mode */ \r
+ canREG2->TEST = 0x00000200; \r
+\r
+ /* flip the parity bit */\r
+ canPARRAM2 ^= 0x00001000; \r
+\r
+ /* Enable parity, disable init, still TEST mode */\r
+ canREG2->CTL = 0x00002880; \r
+\r
+ /* Read location with parity error */\r
+ canread = canRAM2; \r
+ \r
+ /* check if ESM group1 channel 23 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x00800000)) \r
+ {\r
+ /* No DCAN2 RAM parity error was flagged to ESM */\r
+ /* Need custom routine to handle this failure instead of the infinite loop */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear ESM group1 channel 23 flag */\r
+ esmREG->ESTATUS1[0] = 0x00800000; \r
+ \r
+ /* disable TEST mode */\r
+ canREG2->CTL = 0x00002800; \r
+ }\r
+}\r
+\r
+/** @fn void can3ParityCheck(void)\r
+* @brief Routine to check CAN3 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check CAN3 RAM parity error detection and signaling mechanism\r
+*/\r
+void can3ParityCheck(void)\r
+{\r
+ volatile unsigned int canread = 0;\r
+\r
+ /* Disable parity, init mode, TEST mode */\r
+ canREG3->CTL = 0x00001481; \r
+\r
+ /* Enable RAM Direct Access mode */ \r
+ canREG3->TEST = 0x00000200; \r
+\r
+ /* flip the parity bit */\r
+ canPARRAM3 ^= 0x00001000; \r
+\r
+ /* Enable parity, disable init, still TEST mode */\r
+ canREG3->CTL = 0x00002880; \r
+\r
+ /* Read location with parity error */\r
+ canread = canRAM3; \r
+\r
+ /* check if ESM group1 channel 22 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x00400000)) \r
+ {\r
+ /* No DCAN3 RAM parity error was flagged to ESM */\r
+ /* Need custom routine to handle this failure instead of the infinite loop */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear ESM group1 channel 22 flag */\r
+ esmREG->ESTATUS1[0] = 0x00400000; \r
+ \r
+ /* disable TEST mode */\r
+ canREG3->CTL = 0x00002800; \r
+ }\r
+}\r
+\r
+/** @fn void mibspi1ParityCheck(void)\r
+* @brief Routine to check MIBSPI1 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check MIBSPI1 RAM parity error detection and signaling mechanism\r
+*/\r
+void mibspi1ParityCheck(void)\r
+{\r
+ volatile unsigned int spiread = 0;\r
+\r
+ /* enable multi-buffered mode */\r
+ mibspiREG1->MIBSPIE = 0x1; \r
+\r
+ /* enable parity error detection */\r
+ mibspiREG1->EDEN = 0xA; \r
+ \r
+ /* enable parity test mode */\r
+ mibspiREG1->PTESTEN = 1; \r
+ \r
+ /* flip bit 0 of the parity location */\r
+ mibspiPARRAM1 ^= 0x1; \r
+\r
+ /* disable parity test mode */\r
+ mibspiREG1->PTESTEN = 0; \r
+\r
+ /* read from MibSPI1 RAM to cause parity error */\r
+ spiread = *(unsigned int *) mibspiRAM1; \r
+\r
+ /* check if ESM group1 channel 17 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x20000)) \r
+ {\r
+ /* No MibSPI1 RAM parity error was flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear parity error flags */\r
+ mibspiREG1->UERRSTAT = 0x3; \r
+ \r
+ /* clear ESM group1 channel 17 flag */\r
+ esmREG->ESTATUS1[0] = 0x20000; \r
+ \r
+ /* enable parity test mode */\r
+ mibspiREG1->PTESTEN = 1; \r
+ \r
+ /* Revert back to correct data, flip bit 0 of the parity location */\r
+ mibspiPARRAM1 ^= 0x1; \r
+ \r
+ /* disable parity test mode */\r
+ mibspiREG1->PTESTEN = 0; \r
+ }\r
+}\r
+\r
+/** @fn void mibspi3ParityCheck(void)\r
+* @brief Routine to check MIBSPI3 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check MIBSPI3 RAM parity error detection and signaling mechanism\r
+*/\r
+void mibspi3ParityCheck(void)\r
+{\r
+ volatile unsigned int spiread = 0;\r
+\r
+ /* enable multi-buffered mode */\r
+ mibspiREG3->MIBSPIE = 0x1; \r
+\r
+ /* enable parity test mode */\r
+ mibspiREG3->PTESTEN = 1; \r
+ \r
+ /* flip bit 0 of the parity location */\r
+ mibspiPARRAM3 ^= 0x1; \r
+\r
+ /* enable parity error detection */\r
+ mibspiREG3->EDEN = 0xA; \r
+ \r
+ /* disable parity test mode */\r
+ mibspiREG3->PTESTEN = 0; \r
+\r
+ /* read from MibSPI3 RAM to cause parity error */\r
+ spiread = *(unsigned int *) mibspiRAM3; \r
+\r
+ /* check if ESM group1 channel 18 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x40000)) \r
+ {\r
+ /* No MibSPI3 RAM parity error was flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear parity error flags */\r
+ mibspiREG3->UERRSTAT = 0x3; \r
+ \r
+ /* clear ESM group1 channel 18 flag */\r
+ esmREG->ESTATUS1[0] = 0x40000; \r
+ \r
+ /* enable parity test mode */\r
+ mibspiREG3->PTESTEN = 1; \r
+ \r
+ /* Revert back to correct data, flip bit 0 of the parity location */\r
+ mibspiPARRAM3 ^= 0x1; \r
+ \r
+ /* disable parity test mode */\r
+ mibspiREG3->PTESTEN = 0; \r
+ }\r
+}\r
+\r
+/** @fn void mibspi5ParityCheck(void)\r
+* @brief Routine to check MIBSPI5 RAM parity error detection and signaling mechanism\r
+*\r
+* Routine to check MIBSPI5 RAM parity error detection and signaling mechanism\r
+*/\r
+void mibspi5ParityCheck(void)\r
+{\r
+ volatile unsigned int spiread = 0;\r
+\r
+ /* enable multi-buffered mode */\r
+ mibspiREG5->MIBSPIE = 0x1; \r
+\r
+ /* enable parity test mode */\r
+ mibspiREG5->PTESTEN = 1; \r
+ \r
+ /* flip bit 0 of the parity location */ \r
+ mibspiPARRAM5 ^= 0x1; \r
+\r
+ /* enable parity error detection */\r
+ mibspiREG5->EDEN = 0xA; \r
+ \r
+ /* disable parity test mode */\r
+ mibspiREG5->PTESTEN = 0; \r
+\r
+ /* read from MibSPI5 RAM to cause parity error */\r
+ spiread = *(unsigned int *) mibspiRAM5; \r
+\r
+ /* check if ESM group1 channel 24 is flagged */\r
+ if (!(esmREG->ESTATUS1[0] & 0x01000000))\r
+ {\r
+ /* No MibSPI5 RAM parity error was flagged to ESM. */\r
+ /* Need custom routine to handle this failure instead of the infinite loop */\r
+ while(1);\r
+ }\r
+ else\r
+ {\r
+ /* clear parity error flags */\r
+ mibspiREG5->UERRSTAT = 0x3; \r
+ \r
+ /* clear ESM group1 channel 24 flag */\r
+ esmREG->ESTATUS1[0] = 0x01000000; \r
+ \r
+ /* enable parity test mode */\r
+ mibspiREG5->PTESTEN = 1; \r
+ \r
+ /* Revert back to correct data, flip bit 0 of the parity location */\r
+ mibspiPARRAM5 ^= 0x1; \r
+ \r
+ /* disable parity test mode */\r
+ mibspiREG5->PTESTEN = 0; \r
+ }\r
+}\r
--- /dev/null
+/** @file sys_startup.c \r
+* @brief Startup Source File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+* This file contains:\r
+* - Include Files\r
+* - Type Definitions\r
+* - External Functions\r
+* - VIM RAM Setup\r
+* - Startup Routine\r
+* .\r
+* which are relevant for the Startup.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Include Files */\r
+\r
+#include "sys_common.h"\r
+#include "system.h"\r
+#include "sys_vim.h"\r
+#include "sys_core.h"\r
+#include "sys_selftest.h"\r
+#include "esm.h"\r
+#include "mibspi.h"\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Type Definitions */\r
+\r
+typedef void (*handler_fptr)(const uint8_t *in, uint8_t *out);\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+\r
+/* External Functions */\r
+\r
+#pragma WEAK(__TI_Handler_Table_Base)\r
+#pragma WEAK(__TI_Handler_Table_Limit)\r
+#pragma WEAK(__TI_CINIT_Base)\r
+#pragma WEAK(__TI_CINIT_Limit)\r
+\r
+extern uint32_t __TI_Handler_Table_Base;\r
+extern uint32_t __TI_Handler_Table_Limit;\r
+extern uint32_t __TI_CINIT_Base;\r
+extern uint32_t __TI_CINIT_Limit;\r
+extern uint32_t __TI_PINIT_Base;\r
+extern uint32_t __TI_PINIT_Limit;\r
+extern uint32_t * __binit__;\r
+\r
+extern void main(void);\r
+extern void exit(void);\r
+\r
+extern void muxInit(void);\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Vim Ram Definition */\r
+/** @struct vimRam\r
+* @brief Vim Ram Definition\r
+*\r
+* This type is used to access the Vim Ram.\r
+*/\r
+/** @typedef vimRAM_t\r
+* @brief Vim Ram Type Definition\r
+*\r
+* This type is used to access the Vim Ram.\r
+*/\r
+typedef volatile struct vimRam\r
+{\r
+ t_isrFuncPTR ISR[VIM_CHANNELS + 1];\r
+} vimRAM_t;\r
+\r
+#define vimRAM ((vimRAM_t *)0xFFF82000U)\r
+\r
+static const t_isrFuncPTR s_vim_init[] =\r
+{\r
+ &phantomInterrupt,\r
+ &esmHighInterrupt,\r
+ &phantomInterrupt,\r
+ &vPreemptiveTick,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &sciHighLevelInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+ &phantomInterrupt,\r
+};\r
+\r
+\r
+/* Startup Routine */\r
+\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+\r
+#pragma INTERRUPT(_c_int00, RESET)\r
+\r
+void _c_int00()\r
+{\r
+ \r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+\r
+ /* Initialize Core Registers to avoid CCM Error */\r
+ _coreInitRegisters_();\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+ /* Initialize Stack Pointers */\r
+ _coreInitStackPointer_();\r
+\r
+/* USER CODE BEGIN (7) */\r
+/* USER CODE END */\r
+\r
+ /* Implement work-around for CCM-R4 issue on silicon revision A */\r
+ if (DEVICE_ID_REV == 0x802AAD05)\r
+ {\r
+ _esmCcmErrorsClear_();\r
+ }\r
+ \r
+/* USER CODE BEGIN (8) */\r
+/* USER CODE END */\r
+\r
+ /* Enable response to ECC errors indicated by CPU for accesses to flash */\r
+ flashWREG->FEDACCTRL1 = 0x000A060A;\r
+\r
+ /* Enable CPU Event Export */\r
+ /* This allows the CPU to signal any single-bit or double-bit errors detected\r
+ * by its ECC logic for accesses to program flash or data RAM.\r
+ */\r
+ _coreEnableEventBusExport_();\r
+ \r
+ /* Enable CPU ECC checking for ATCM (flash accesses) */\r
+ _coreEnableFlashEcc_();\r
+\r
+/* USER CODE BEGIN (9) */\r
+/* USER CODE END */\r
+\r
+ /* Reset handler: the following instructions read from the system exception status register\r
+ * to identify the cause of the CPU reset.\r
+ */\r
+\r
+ /* check for power-on reset condition */\r
+ if ((SYS_EXCEPTION & POWERON_RESET) != 0)\r
+ {\r
+/* USER CODE BEGIN (10) */\r
+/* USER CODE END */\r
+ \r
+ /* clear all reset status flags */\r
+ SYS_EXCEPTION = 0xFFFF;\r
+\r
+/* USER CODE BEGIN (11) */\r
+/* USER CODE END */\r
+\r
+ /* continue with normal start-up sequence */\r
+ }\r
+ else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0)\r
+ {\r
+ /* Reset caused due to oscillator failure.\r
+ Add user code here to handle oscillator failure */\r
+\r
+/* USER CODE BEGIN (12) */\r
+/* USER CODE END */\r
+ }\r
+ else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0 )\r
+ {\r
+ /* Reset caused due \r
+ * 1) windowed watchdog violation - Add user code here to handle watchdog violation.\r
+ * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS\r
+ */\r
+ /* Check the WatchDog Status register */\r
+ if(WATCHDOG_STATUS != 0U)\r
+ {\r
+ /* Add user code here to handle watchdog violation. */ \r
+/* USER CODE BEGIN (13) */\r
+/* USER CODE END */\r
+\r
+ /* Clear the Watchdog reset flag in Exception Status register */ \r
+ SYS_EXCEPTION = WATCHDOG_RESET;\r
+ \r
+/* USER CODE BEGIN (14) */\r
+/* USER CODE END */\r
+ }\r
+ else\r
+ {\r
+ /* Clear the ICEPICK reset flag in Exception Status register */ \r
+ SYS_EXCEPTION = ICEPICK_RESET;\r
+/* USER CODE BEGIN (15) */\r
+/* USER CODE END */\r
+ }\r
+ }\r
+ else if ((SYS_EXCEPTION & CPU_RESET) !=0 )\r
+ {\r
+ /* Reset caused due to CPU reset.\r
+ CPU reset can be caused by CPU self-test completion, or\r
+ by toggling the "CPU RESET" bit of the CPU Reset Control Register. */\r
+\r
+/* USER CODE BEGIN (16) */\r
+/* USER CODE END */\r
+\r
+ /* clear all reset status flags */\r
+ SYS_EXCEPTION = CPU_RESET;\r
+\r
+/* USER CODE BEGIN (17) */\r
+/* USER CODE END */\r
+\r
+ }\r
+ else if ((SYS_EXCEPTION & SW_RESET) != 0)\r
+ {\r
+ /* Reset caused due to software reset.\r
+ Add user code to handle software reset. */\r
+\r
+/* USER CODE BEGIN (18) */\r
+/* USER CODE END */\r
+ }\r
+ else\r
+ {\r
+ /* Reset caused by nRST being driven low externally.\r
+ Add user code to handle external reset. */\r
+\r
+/* USER CODE BEGIN (19) */\r
+/* USER CODE END */\r
+ }\r
+\r
+ /* Check if there were ESM group3 errors during power-up.\r
+ * These could occur during eFuse auto-load or during reads from flash OTP\r
+ * during power-up. Device operation is not reliable and not recommended\r
+ * in this case.\r
+ * An ESM group3 error only drives the nERROR pin low. An external circuit\r
+ * that monitors the nERROR pin must take the appropriate action to ensure that\r
+ * the system is placed in a safe state, as determined by the application.\r
+ */\r
+ if (esmREG->ESTATUS1[2])\r
+ {\r
+/* USER CODE BEGIN (20) */\r
+/* USER CODE END */\r
+ while(1);\r
+ }\r
+\r
+/* USER CODE BEGIN (21) */\r
+/* USER CODE END */\r
+\r
+ /* Initialize System - Clock, Flash settings with Efuse self check */\r
+ systemInit();\r
+\r
+\r
+/* USER CODE BEGIN (24) */\r
+/* USER CODE END */\r
+\r
+ /* Run a diagnostic check on the memory self-test controller.\r
+ * This function chooses a RAM test algorithm and runs it on an on-chip ROM.\r
+ * The memory self-test is expected to fail. The function ensures that the PBIST controller\r
+ * is capable of detecting and indicating a memory self-test failure.\r
+ */\r
+ pbistSelfCheck();\r
+\r
+/* USER CODE BEGIN (26) */\r
+/* USER CODE END */\r
+\r
+\r
+ /* Run PBIST on CPU RAM.\r
+ * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.\r
+ * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the\r
+ * device datasheet.\r
+ */\r
+ pbistRun(0x08300020, /* ESRAM Single Port PBIST */\r
+ PBIST_March13N_SP);\r
+\r
+/* USER CODE BEGIN (27) */\r
+/* USER CODE END */\r
+\r
+ /* Wait for PBIST for CPU RAM to be completed */\r
+ while(!pbistIsTestCompleted());\r
+\r
+/* USER CODE BEGIN (28) */\r
+/* USER CODE END */\r
+\r
+ /* Check if CPU RAM passed the self-test */\r
+ if( pbistIsTestPassed() != TRUE)\r
+ {\r
+ /* CPU RAM failed the self-test.\r
+ * Need custom handler to check the memory failure\r
+ * and to take the appropriate next step.\r
+ */\r
+ if(pbistPortTestStatus(PBIST_PORT0) != TRUE)\r
+ {\r
+ memoryPort0TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA0, pbistREG->FSRDL0);\r
+ }\r
+ else if(pbistPortTestStatus(PBIST_PORT1) != TRUE)\r
+ {\r
+ memoryPort1TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA1, pbistREG->FSRDL1);\r
+ }\r
+ else\r
+ {\r
+ while(1);\r
+ }\r
+ }\r
+\r
+/* USER CODE BEGIN (29) */\r
+/* USER CODE END */\r
+\r
+ /* Disable PBIST clocks and disable memory self-test mode */\r
+ pbistStop();\r
+\r
+/* USER CODE BEGIN (30) */\r
+/* USER CODE END */\r
+\r
+ /* Initialize CPU RAM.\r
+ * This function uses the system module's hardware for auto-initialization of memories and their\r
+ * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.\r
+ * Hence the value 0x1 passed to the function.\r
+ * This function will initialize the entire CPU RAM and the corresponding ECC locations.\r
+ */\r
+ _memoryInit_(0x1);\r
+\r
+/* USER CODE BEGIN (31) */\r
+/* USER CODE END */\r
+ \r
+ /* Enable ECC checking for TCRAM accesses.\r
+ * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.\r
+ */\r
+ _coreEnableRamEcc_();\r
+\r
+/* USER CODE BEGIN (32) */\r
+/* USER CODE END */\r
+\r
+ /* Start PBIST on all dual-port memories */\r
+ pbistRun( 0x00000000 /* EMAC Dual Port PBIST */\r
+ | 0x00000000 /* USB Dual Port PBIST for RMx / Reserved for TMS570x */ \r
+ | 0x00000800 /* DMA Dual Port PBIST */\r
+ | 0x00000200 /* VIM Dual Port PBIST */\r
+ | 0x00000040 /* MIBSPI1 Dual Port PBIST */\r
+ | 0x00000080 /* MIBSPI3 Dual Port PBIST */\r
+ | 0x00000100 /* MIBSPI5 Dual Port PBIST */\r
+ | 0x00000004 /* CAN1 Dual Port PBIST */\r
+ | 0x00000008 /* CAN2 Dual Port PBIST */\r
+ | 0x00000010 /* CAN3 Dual Port PBIST */\r
+ | 0x00000400 /* ADC1 Dual Port PBIST */\r
+ | 0x00020000 /* ADC2 Dual Port PBIST */\r
+ | 0x00001000 /* HET1 Dual Port PBIST */\r
+ | 0x00040000 /* HET2 Dual Port PBIST */\r
+ | 0x00002000 /* HTU1 Dual Port PBIST */\r
+ | 0x00080000 /* HTU2 Dual Port PBIST */\r
+ | 0x00004000 /* RTP Dual Port PBIST */\r
+ | 0x00000000 /* FTU Dual Port PBIST for TMS570x / Reserved for RMx */\r
+ | 0x00008000 /* FRAY Dual Port PBIST for TMS570x / Reserved for RMx */\r
+ , PBIST_March13N_DP);\r
+\r
+/* USER CODE BEGIN (33) */\r
+/* USER CODE END */\r
+\r
+\r
+ /* Test the CPU ECC mechanism for RAM accesses.\r
+ * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses\r
+ * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error\r
+ * in the ECC causes a data abort exception. The data abort handler is written to look for\r
+ * deliberately caused exception and to return the code execution to the instruction\r
+ * following the one that caused the abort.\r
+ */\r
+ checkB0RAMECC();\r
+ tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */\r
+ tcram2REG->RAMCTRL &= ~(0x00000100);\r
+\r
+ checkB1RAMECC();\r
+ tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */\r
+ tcram2REG->RAMCTRL &= ~(0x00000100);\r
+\r
+/* USER CODE BEGIN (34) */\r
+/* USER CODE END */\r
+\r
+\r
+ /* Test the CPU ECC mechanism for Flash accesses.\r
+ * The checkFlashECC function uses the flash interface module's diagnostic mode 7\r
+ * to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit\r
+ * error on reading from flash causes a data abort exception.\r
+ * The data abort handler is written to look for deliberately caused exception and\r
+ * to return the code execution to the instruction following the one that was aborted.\r
+ *\r
+ */\r
+ checkFlashECC();\r
+ flashWREG->FDIAGCTRL = 0x000A0007; /* disable flash diagnostic mode */\r
+\r
+/* USER CODE BEGIN (35) */\r
+/* USER CODE END */\r
+\r
+/* USER CODE BEGIN (36) */\r
+/* USER CODE END */\r
+\r
+ /* Wait for PBIST for CPU RAM to be completed */\r
+ while(!pbistIsTestCompleted());\r
+\r
+/* USER CODE BEGIN (37) */\r
+/* USER CODE END */\r
+\r
+ /* Check if CPU RAM passed the self-test */\r
+ if( pbistIsTestPassed() != TRUE)\r
+ {\r
+\r
+/* USER CODE BEGIN (38) */\r
+/* USER CODE END */\r
+\r
+ /* CPU RAM failed the self-test.\r
+ * Need custom handler to check the memory failure\r
+ * and to take the appropriate next step.\r
+ */\r
+ if(pbistPortTestStatus(PBIST_PORT0) != TRUE)\r
+ {\r
+ memoryPort0TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA0, pbistREG->FSRDL0);\r
+ }\r
+ else if(pbistPortTestStatus(PBIST_PORT1) != TRUE)\r
+ {\r
+ memoryPort1TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA1, pbistREG->FSRDL1);\r
+ }\r
+ else\r
+ {\r
+ while(1);\r
+ }\r
+ }\r
+\r
+/* USER CODE BEGIN (39) */\r
+/* USER CODE END */\r
+\r
+ /* Disable PBIST clocks and disable memory self-test mode */\r
+ pbistStop();\r
+\r
+\r
+/* USER CODE BEGIN (45) */\r
+/* USER CODE END */\r
+\r
+ /* Release the MibSPI1 modules from local reset.\r
+ * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.\r
+ */\r
+ mibspiREG1->GCR0 = 0x1;\r
+ \r
+ /* Release the MibSPI3 modules from local reset.\r
+ * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.\r
+ */\r
+ mibspiREG3->GCR0 = 0x1;\r
+ \r
+ /* Release the MibSPI5 modules from local reset.\r
+ * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.\r
+ */\r
+ mibspiREG5->GCR0 = 0x1;\r
+ \r
+/* USER CODE BEGIN (46) */\r
+/* USER CODE END */\r
+\r
+ /* Initialize all on-chip SRAMs except for MibSPIx RAMs\r
+ * The MibSPIx modules have their own auto-initialization mechanism which is triggered\r
+ * as soon as the modules are brought out of local reset.\r
+ */\r
+ /* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.\r
+ */\r
+ _memoryInit_( 1 << 1 /* DMA Memory Init */\r
+ | 1 << 2 /* VIM Memory Init */\r
+ | 1 << 5 /* CAN1 Memory Init */\r
+ | 1 << 6 /* CAN2 Memory Init */\r
+ | 1 << 10 /* CAN3 Memory Init */\r
+ | 1 << 8 /* ADC1 Memory Init */\r
+ | 1 << 14 /* ADC2 Memory Init */\r
+ | 1 << 3 /* HET1 Memory Init */\r
+ | 1 << 4 /* HTU1 Memory Init */\r
+ | 1 << 15 /* HET2 Memory Init */\r
+ | 1 << 16 /* HTU2 Memory Init */\r
+ | 0 << 13); /* Reserved for RMx Family / FTU Memory Init for TMS570x Family */\r
+\r
+ /* Test the parity protection mechanism for peripheral RAMs\r
+ * The following memories have parity protection that needs to be checked:\r
+ * VIM, DMA, ADC1, ADC2, NHET1, NHET2, HTU1, HTU2, FlexRay, FTU,\r
+ * MibSPI1, MibSPI3, MibSPI5, DCAN1, DCAN2, DCAN3 based on user selection\r
+ */\r
+\r
+/* USER CODE BEGIN (47) */\r
+/* USER CODE END */\r
+ \r
+ het1ParityCheck();\r
+ \r
+/* USER CODE BEGIN (48) */\r
+/* USER CODE END */\r
+\r
+ htu1ParityCheck();\r
+ \r
+/* USER CODE BEGIN (49) */\r
+/* USER CODE END */\r
+\r
+ het2ParityCheck();\r
+ \r
+/* USER CODE BEGIN (50) */\r
+/* USER CODE END */\r
+\r
+ htu2ParityCheck();\r
+ \r
+/* USER CODE BEGIN (51) */\r
+/* USER CODE END */\r
+\r
+ adc1ParityCheck();\r
+ \r
+/* USER CODE BEGIN (52) */\r
+/* USER CODE END */\r
+\r
+ adc2ParityCheck();\r
+ \r
+/* USER CODE BEGIN (53) */\r
+/* USER CODE END */\r
+\r
+ can1ParityCheck();\r
+ \r
+/* USER CODE BEGIN (54) */\r
+/* USER CODE END */\r
+\r
+ can2ParityCheck();\r
+ \r
+/* USER CODE BEGIN (55) */\r
+/* USER CODE END */\r
+\r
+ can3ParityCheck();\r
+ \r
+/* USER CODE BEGIN (56) */\r
+/* USER CODE END */\r
+\r
+ vimParityCheck();\r
+ \r
+/* USER CODE BEGIN (57) */\r
+/* USER CODE END */\r
+\r
+ dmaParityCheck();\r
+\r
+\r
+/* USER CODE BEGIN (58) */\r
+/* USER CODE END */\r
+\r
+ while (mibspiREG1->BUFINIT); /* wait for MibSPI1 RAM to complete initialization */\r
+ while (mibspiREG3->BUFINIT); /* wait for MibSPI3 RAM to complete initialization */ \r
+ while (mibspiREG5->BUFINIT); /* wait for MibSPI5 RAM to complete initialization */\r
+\r
+/* USER CODE BEGIN (59) */\r
+/* USER CODE END */\r
+\r
+ mibspi1ParityCheck();\r
+ \r
+/* USER CODE BEGIN (60) */\r
+/* USER CODE END */\r
+\r
+ mibspi3ParityCheck();\r
+ \r
+/* USER CODE BEGIN (61) */\r
+/* USER CODE END */\r
+ \r
+ mibspi5ParityCheck();\r
+ \r
+\r
+/* USER CODE BEGIN (62) */\r
+/* USER CODE END */\r
+ \r
+\r
+/* USER CODE BEGIN (63) */\r
+/* USER CODE END */\r
+\r
+ \r
+ /* Initialize VIM table */\r
+ {\r
+ uint32_t i;\r
+\r
+ for (i = 0; i < (VIM_CHANNELS + 1); i++)\r
+ {\r
+ vimRAM->ISR[i] = s_vim_init[i];\r
+ }\r
+ }\r
+\r
+ /* set IRQ/FIQ priorities */\r
+ vimREG->FIRQPR0 = SYS_FIQ\r
+ | (SYS_FIQ << 1U)\r
+ | (SYS_IRQ << 2U)\r
+ | (SYS_IRQ << 3U)\r
+ | (SYS_IRQ << 4U)\r
+ | (SYS_IRQ << 5U)\r
+ | (SYS_IRQ << 6U)\r
+ | (SYS_IRQ << 7U)\r
+ | (SYS_IRQ << 8U)\r
+ | (SYS_IRQ << 9U)\r
+ | (SYS_IRQ << 10U)\r
+ | (SYS_IRQ << 11U)\r
+ | (SYS_IRQ << 12U)\r
+ | (SYS_IRQ << 13U)\r
+ | (SYS_IRQ << 14U)\r
+ | (SYS_IRQ << 15U)\r
+ | (SYS_IRQ << 16U)\r
+ | (SYS_IRQ << 17U)\r
+ | (SYS_IRQ << 18U)\r
+ | (SYS_IRQ << 19U)\r
+ | (SYS_IRQ << 20U)\r
+ | (SYS_IRQ << 21U)\r
+ | (SYS_IRQ << 22U)\r
+ | (SYS_IRQ << 23U)\r
+ | (SYS_IRQ << 24U)\r
+ | (SYS_IRQ << 25U)\r
+ | (SYS_IRQ << 26U)\r
+ | (SYS_IRQ << 27U)\r
+ | (SYS_IRQ << 28U)\r
+ | (SYS_IRQ << 29U)\r
+ | (SYS_IRQ << 30U)\r
+ | (SYS_IRQ << 31U);\r
+\r
+ vimREG->FIRQPR1 = SYS_IRQ\r
+ | (SYS_IRQ << 1U)\r
+ | (SYS_IRQ << 2U)\r
+ | (SYS_IRQ << 3U)\r
+ | (SYS_IRQ << 4U)\r
+ | (SYS_IRQ << 5U)\r
+ | (SYS_IRQ << 6U)\r
+ | (SYS_IRQ << 7U)\r
+ | (SYS_IRQ << 8U)\r
+ | (SYS_IRQ << 9U)\r
+ | (SYS_IRQ << 10U)\r
+ | (SYS_IRQ << 11U)\r
+ | (SYS_IRQ << 12U)\r
+ | (SYS_IRQ << 13U)\r
+ | (SYS_IRQ << 14U)\r
+ | (SYS_IRQ << 15U)\r
+ | (SYS_IRQ << 16U)\r
+ | (SYS_IRQ << 17U)\r
+ | (SYS_IRQ << 18U)\r
+ | (SYS_IRQ << 19U)\r
+ | (SYS_IRQ << 20U)\r
+ | (SYS_IRQ << 21U)\r
+ | (SYS_IRQ << 22U)\r
+ | (SYS_IRQ << 23U)\r
+ | (SYS_IRQ << 24U)\r
+ | (SYS_IRQ << 25U)\r
+ | (SYS_IRQ << 26U)\r
+ | (SYS_IRQ << 27U)\r
+ | (SYS_IRQ << 28U)\r
+ | (SYS_IRQ << 29U)\r
+ | (SYS_IRQ << 30U)\r
+ | (SYS_IRQ << 31U);\r
+\r
+\r
+ vimREG->FIRQPR2 = SYS_IRQ\r
+ | (SYS_IRQ << 1U)\r
+ | (SYS_IRQ << 2U)\r
+ | (SYS_IRQ << 3U)\r
+ | (SYS_IRQ << 4U)\r
+ | (SYS_IRQ << 5U)\r
+ | (SYS_IRQ << 6U)\r
+ | (SYS_IRQ << 7U)\r
+ | (SYS_IRQ << 8U)\r
+ | (SYS_IRQ << 9U)\r
+ | (SYS_IRQ << 10U)\r
+ | (SYS_IRQ << 11U)\r
+ | (SYS_IRQ << 12U)\r
+ | (SYS_IRQ << 13U)\r
+ | (SYS_IRQ << 14U)\r
+ | (SYS_IRQ << 15U)\r
+ | (SYS_IRQ << 16U)\r
+ | (SYS_IRQ << 17U)\r
+ | (SYS_IRQ << 18U)\r
+ | (SYS_IRQ << 19U)\r
+ | (SYS_IRQ << 20U)\r
+ | (SYS_IRQ << 21U)\r
+ | (SYS_IRQ << 22U)\r
+ | (SYS_IRQ << 23U)\r
+ | (SYS_IRQ << 24U)\r
+ | (SYS_IRQ << 25U)\r
+ | (SYS_IRQ << 26U)\r
+ | (SYS_IRQ << 27U)\r
+ | (SYS_IRQ << 28U)\r
+ | (SYS_IRQ << 29U)\r
+ | (SYS_IRQ << 30U)\r
+ | (SYS_IRQ << 31U);\r
+\r
+ vimREG->FIRQPR3 = SYS_IRQ\r
+ | (SYS_IRQ << 1U)\r
+ | (SYS_IRQ << 2U)\r
+ | (SYS_IRQ << 3U)\r
+ | (SYS_IRQ << 4U)\r
+ | (SYS_IRQ << 5U)\r
+ | (SYS_IRQ << 6U)\r
+ | (SYS_IRQ << 7U)\r
+ | (SYS_IRQ << 8U)\r
+ | (SYS_IRQ << 9U)\r
+ | (SYS_IRQ << 10U)\r
+ | (SYS_IRQ << 11U)\r
+ | (SYS_IRQ << 12U)\r
+ | (SYS_IRQ << 13U)\r
+ | (SYS_IRQ << 14U)\r
+ | (SYS_IRQ << 15U)\r
+ | (SYS_IRQ << 16U)\r
+ | (SYS_IRQ << 17U)\r
+ | (SYS_IRQ << 18U)\r
+ | (SYS_IRQ << 19U)\r
+ | (SYS_IRQ << 20U)\r
+ | (SYS_IRQ << 21U)\r
+ | (SYS_IRQ << 22U)\r
+ | (SYS_IRQ << 23U)\r
+ | (SYS_IRQ << 24U)\r
+ | (SYS_IRQ << 25U)\r
+ | (SYS_IRQ << 26U)\r
+ | (SYS_IRQ << 27U)\r
+ | (SYS_IRQ << 28U)\r
+ | (SYS_IRQ << 29U)\r
+ | (SYS_IRQ << 30U)\r
+ | (SYS_IRQ << 31U);\r
+\r
+ \r
+ /* enable interrupts */\r
+ vimREG->REQMASKSET0 = 1U\r
+ | (1U << 1U)\r
+ | (1U << 2U)\r
+ | (0U << 3U)\r
+ | (0U << 4U)\r
+ | (0U << 5U)\r
+ | (0U << 6U)\r
+ | (0U << 7U)\r
+ | (0U << 8U)\r
+ | (0U << 9U)\r
+ | (0U << 10U)\r
+ | (0U << 11U)\r
+ | (0U << 12U)\r
+ | (0U << 13U)\r
+ | (0U << 14U)\r
+ | (0U << 15U)\r
+ | (0U << 16U)\r
+ | (0U << 17U)\r
+ | (0U << 18U)\r
+ | (0U << 19U)\r
+ | (0U << 20U)\r
+ | (0U << 21U)\r
+ | (0U << 22U)\r
+ | (0U << 23U)\r
+ | (0U << 24U)\r
+ | (0U << 25U)\r
+ | (0U << 26U)\r
+ | (0U << 27U)\r
+ | (0U << 28U)\r
+ | (0U << 29U)\r
+ | (0U << 30U)\r
+ | (0U << 31U);\r
+\r
+ vimREG->REQMASKSET1 = 0U\r
+ | (0U << 1U)\r
+ | (0U << 2U)\r
+ | (0U << 3U)\r
+ | (0U << 4U)\r
+ | (0U << 5U)\r
+ | (0U << 6U)\r
+ | (0U << 7U)\r
+ | (0U << 8U)\r
+ | (0U << 9U)\r
+ | (0U << 10U)\r
+ | (0U << 11U)\r
+ | (0U << 12U)\r
+ | (0U << 13U)\r
+ | (0U << 14U)\r
+ | (0U << 15U)\r
+ | (0U << 16U)\r
+ | (0U << 17U)\r
+ | (0U << 18U)\r
+ | (0U << 19U)\r
+ | (0U << 20U)\r
+ | (0U << 21U)\r
+ | (0U << 22U)\r
+ | (0U << 23U)\r
+ | (0U << 24U)\r
+ | (0U << 25U)\r
+ | (0U << 26U)\r
+ | (0U << 27U)\r
+ | (0U << 28U)\r
+ | (0U << 29U)\r
+ | (0U << 30U)\r
+ | (0U << 31U);\r
+\r
+ vimREG->REQMASKSET2 = 1U\r
+ | (0U << 1U)\r
+ | (0U << 2U)\r
+ | (0U << 3U)\r
+ | (0U << 4U)\r
+ | (0U << 5U)\r
+ | (0U << 6U)\r
+ | (0U << 7U)\r
+ | (0U << 8U)\r
+ | (0U << 9U)\r
+ | (0U << 10U)\r
+ | (0U << 11U)\r
+ | (0U << 12U)\r
+ | (0U << 13U)\r
+ | (0U << 14U)\r
+ | (0U << 15U)\r
+ | (0U << 16U)\r
+ | (0U << 17U)\r
+ | (0U << 18U)\r
+ | (0U << 19U)\r
+ | (0U << 20U)\r
+ | (0U << 21U)\r
+ | (0U << 22U)\r
+ | (0U << 23U)\r
+ | (0U << 24U)\r
+ | (0U << 25U)\r
+ | (0U << 26U)\r
+ | (0U << 27U)\r
+ | (0U << 28U)\r
+ | (0U << 29U)\r
+ | (0U << 30U)\r
+ | (0U << 31U);\r
+ \r
+ vimREG->REQMASKSET3 = 0U\r
+ | (0U << 1U)\r
+ | (0U << 2U)\r
+ | (0U << 3U)\r
+ | (0U << 4U)\r
+ | (0U << 5U)\r
+ | (0U << 6U)\r
+ | (0U << 7U)\r
+ | (0U << 8U)\r
+ | (0U << 9U)\r
+ | (0U << 10U)\r
+ | (0U << 11U)\r
+ | (0U << 12U)\r
+ | (0U << 13U)\r
+ | (0U << 14U)\r
+ | (0U << 15U)\r
+ | (0U << 16U)\r
+ | (0U << 17U)\r
+ | (0U << 18U)\r
+ | (0U << 19U)\r
+ | (0U << 20U)\r
+ | (0U << 21U)\r
+ | (0U << 22U)\r
+ | (0U << 23U)\r
+ | (0U << 24U)\r
+ | (0U << 25U)\r
+ | (0U << 26U)\r
+ | (0U << 27U)\r
+ | (0U << 28U)\r
+ | (0U << 29U)\r
+ | (0U << 30U)\r
+ | (0U << 31U); \r
+\r
+/* USER CODE BEGIN (64) */\r
+/* USER CODE END */\r
+\r
+ /* Configure system response to error conditions signaled to the ESM group1 */\r
+ /* This function can be configured from the ESM tab of HALCoGen */\r
+ esmInit();\r
+\r
+ /* initalise copy table */\r
+ if ((uint32_t *)&__binit__ != (uint32_t *)0xFFFFFFFFU)\r
+ {\r
+ extern void copy_in(void *binit);\r
+ copy_in((void *)&__binit__);\r
+ }\r
+\r
+ /* initalise the C global variables */\r
+ if (&__TI_Handler_Table_Base < &__TI_Handler_Table_Limit)\r
+ {\r
+ uint8_t **tablePtr = (uint8_t **)&__TI_CINIT_Base;\r
+ uint8_t **tableLimit = (uint8_t **)&__TI_CINIT_Limit;\r
+\r
+ while (tablePtr < tableLimit)\r
+ {\r
+ uint8_t *loadAdr = *tablePtr++;\r
+ uint8_t *runAdr = *tablePtr++;\r
+ uint8_t idx = *loadAdr++;\r
+ handler_fptr handler = (handler_fptr)(&__TI_Handler_Table_Base)[idx];\r
+\r
+ (*handler)((const uint8_t *)loadAdr, runAdr);\r
+ }\r
+ }\r
+\r
+ /* initalise contructors */\r
+ if (__TI_PINIT_Base < __TI_PINIT_Limit)\r
+ {\r
+ void (**p0)() = (void *)__TI_PINIT_Base;\r
+\r
+ while ((uint32_t)p0 < __TI_PINIT_Limit)\r
+ {\r
+ void (*p)() = *p0++;\r
+ p();\r
+ }\r
+ }\r
+\r
+/* USER CODE BEGIN (65) */\r
+/* USER CODE END */\r
+ \r
+ /* call the application */\r
+ main();\r
+\r
+/* USER CODE BEGIN (66) */\r
+/* USER CODE END */\r
+\r
+ exit();\r
+/* USER CODE BEGIN (67) */\r
+/* USER CODE END */\r
+}\r
+\r
+/* USER CODE BEGIN (68) */\r
+/* USER CODE END */\r
--- /dev/null
+/** @file system.c \r
+* @brief System Driver Source File\r
+* @date 15.Mar.2012\r
+* @version 03.01.00\r
+*\r
+* This file contains:\r
+* - API Funcions\r
+* .\r
+* which are relevant for the System driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009-2012, All rights reserved. */\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* Include Files */\r
+\r
+#include "system.h"\r
+#include "sys_selftest.h"\r
+#include "pinmux.h"\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+/** @fn void systemInit(void)\r
+* @brief Initializes System Driver\r
+*\r
+* This function initializes the System driver.\r
+*\r
+*/\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+void setupPLL(void)\r
+{\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+ /** - Configure PLL control registers */\r
+ /** @b Initialize @b Pll1: */\r
+\r
+ /** - Setup pll control register 1:\r
+ * - Setup reset on oscillator slip \r
+ * - Setup bypass on pll slip\r
+ * - setup Pll output clock divider to max before Lock\r
+ * - Setup reset on oscillator fail\r
+ * - Setup reference clock divider \r
+ * - Setup Pll multiplier \r
+ */\r
+ systemREG1->PLLCTL1 = 0x00000000U \r
+ | 0x20000000U \r
+ | ((0x1F)<< 24U) \r
+ | 0x00000000U \r
+ | ((6U - 1U)<< 16U) \r
+ | ((120U - 1U)<< 8U);\r
+\r
+ /** - Setup pll control register 2\r
+ * - Enable/Disable frequency modulation\r
+ * - Setup spreading rate\r
+ * - Setup bandwidth adjustment\r
+ * - Setup internal Pll output divider\r
+ * - Setup spreading amount\r
+ */\r
+ systemREG1->PLLCTL2 = 0x00000000U\r
+ | (255U << 22U)\r
+ | (7U << 12U)\r
+ | ((2U - 1U)<< 9U)\r
+ | 61U;\r
+\r
+ /** @b Initialize @b Pll2: */\r
+\r
+ /** - Setup pll2 control register :\r
+ * - setup Pll output clock divider to max before Lock\r
+ * - Setup reference clock divider \r
+ * - Setup internal Pll output divider\r
+ * - Setup Pll multiplier \r
+ */\r
+ systemREG2->PLLCTL3 = ((2U - 1U) << 29U)\r
+ | ((0x1F)<< 24U) \r
+ | ((6U - 1U)<< 16U) \r
+ | ((120U - 1U) << 8U);\r
+ \r
+ /** - Enable PLL(s) to start up or Lock */\r
+ systemREG1->CSDIS = 0x00000000U \r
+ | 0x00000000U \r
+ | 0x00000008U \r
+ | 0x00000080U \r
+ | 0x00000000U \r
+ | 0x00000000U \r
+ | 0x00000000U;\r
+}\r
+\r
+void trimLPO(void)\r
+{\r
+\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+\r
+ /** @b Initialize Lpo: */\r
+ /** Load TRIM values from OTP if present else load user defined values */\r
+ if(LPO_TRIM_VALUE != 0xFFFF)\r
+ {\r
+ \r
+ systemREG1->LPOMONCTL = (1U << 24U)\r
+ | LPO_TRIM_VALUE;\r
+ }\r
+ else\r
+ {\r
+\r
+ systemREG1->LPOMONCTL = (1U << 24U)\r
+ | (16U << 8U)\r
+ | 8U;\r
+ }\r
+\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+void setupFlash(void)\r
+{\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+ /** - Setup flash read mode, address wait states and data wait states */\r
+ flashWREG->FRDCNTL = 0x00000000U \r
+ | (3U << 8U) \r
+ | (1U << 4U) \r
+ | 1U;\r
+\r
+ /** - Setup flash access wait states for bank 7 */\r
+ FSM_WR_ENA = 0x5;\r
+ EEPROM_CONFIG = 0x00030002;\r
+\r
+ /** - Disable write access to flash state machine registers */\r
+ FSM_WR_ENA = 0xA;\r
+\r
+ /** - Setup flash bank power modes */\r
+ flashWREG->FBFALLBACK = 0x00000000\r
+ | (SYS_ACTIVE << 14U) \r
+ | (SYS_SLEEP << 12U) \r
+ | (SYS_SLEEP << 10U) \r
+ | (SYS_SLEEP << 8U) \r
+ | (SYS_SLEEP << 6U) \r
+ | (SYS_SLEEP << 4U) \r
+ | (SYS_ACTIVE << 2U) \r
+ | SYS_ACTIVE;\r
+\r
+/* USER CODE BEGIN (7) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+void periphInit(void)\r
+{\r
+\r
+/* USER CODE BEGIN (8) */\r
+/* USER CODE END */\r
+\r
+ /** - Disable Peripherals before peripheral powerup*/\r
+ systemREG1->PENA = 0U;\r
+\r
+ /** - Release peripherals from reset and enable clocks to all peripherals */\r
+ /** - Power-up all peripharals */\r
+ pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;\r
+\r
+ /** - Enable Peripherals */\r
+ systemREG1->PENA = 1U;\r
+ \r
+/* USER CODE BEGIN (9) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+void mapClocks(void)\r
+{\r
+ \r
+/* USER CODE BEGIN (10) */\r
+/* USER CODE END */\r
+\r
+ /** @b Initialize @b Clock @b Tree: */\r
+ /** - Diable / Enable clock domain */\r
+ systemREG1->CDDIS= (FALSE << 4 ) /* AVCLK 1 OFF */\r
+ |(FALSE << 5 ) /* AVCLK 2 OFF */\r
+ |(FALSE << 8 ) /* VCLK3 OFF */\r
+ |(FALSE << 10) /* AVCLK 3 OFF */\r
+ |(FALSE << 11); /* AVCLK 4 OFF */\r
+\r
+ /** - Wait for until clocks are locked */\r
+ while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF))\r
+ {\r
+ }\r
+\r
+/* USER CODE BEGIN (11) */\r
+/* USER CODE END */\r
+\r
+ /* Now the PLLs are locked and the PLL outputs can be sped up */\r
+ /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */\r
+ systemREG1->PLLCTL1 = (systemREG1->PLLCTL1 & 0xE0FFFFFF)|((1U - 1U)<< 24U);\r
+ systemREG2->PLLCTL3 = (systemREG2->PLLCTL3 & 0xE0FFFFFF)|((1U - 1U)<< 24U);\r
+ \r
+ /** - Map device clock domains to desired sources and configure top-level dividers */\r
+ /** - All clock domains are working off the default clock sources until now */\r
+ /** - The below assignments can be easily modified using the HALCoGen GUI */\r
+ \r
+ /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */\r
+ systemREG1->GHVSRC = (SYS_PLL1 << 24U) \r
+ | (SYS_PLL1 << 16U) \r
+ | SYS_PLL1;\r
+ \r
+ /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */\r
+ systemREG1->VCLKR = 1U;\r
+ systemREG1->VCLK2R = 1U;\r
+ systemREG2->VCLK3R = 1U;\r
+\r
+/* USER CODE BEGIN (12) */\r
+/* USER CODE END */\r
+ \r
+ /** - Setup RTICLK1 and RTICLK2 clocks */\r
+ systemREG1->RCLKSRC = (1U << 24U)\r
+ | (SYS_VCLK << 16U) \r
+ | (1U << 8U) \r
+ | SYS_VCLK;\r
+\r
+ /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */\r
+ systemREG1->VCLKASRC = (SYS_VCLK << 8U)\r
+ | SYS_VCLK;\r
+\r
+ systemREG2->VCLKACON1 = (1U << 24) \r
+ | 1 << 20U \r
+ | (SYS_VCLK << 16)\r
+ | (1U << 8)\r
+ | 1 << 4U \r
+ | SYS_VCLK;\r
+\r
+/* USER CODE BEGIN (13) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+void systemInit(void)\r
+{\r
+/* USER CODE BEGIN (14) */\r
+/* USER CODE END */\r
+\r
+ /* Configure PLL control registers and enable PLLs.\r
+ * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.\r
+ * This initialization sequence performs all the tasks that are not\r
+ * required to be done at full application speed while the PLL locks.\r
+ */\r
+ setupPLL();\r
+ \r
+/* USER CODE BEGIN (15) */\r
+/* USER CODE END */\r
+\r
+ /* Run eFuse controller start-up checks and start eFuse controller ECC self-test.\r
+ * This includes a check for the eFuse controller error outputs to be stuck-at-zero.\r
+ */\r
+ efcCheck();\r
+ \r
+/* USER CODE BEGIN (16) */\r
+/* USER CODE END */\r
+ \r
+ /* Enable clocks to peripherals and release peripheral reset */\r
+ periphInit();\r
+\r
+/* USER CODE BEGIN (17) */\r
+/* USER CODE END */\r
+\r
+ /* Configure device-level multiplexing and I/O multiplexing */\r
+ muxInit();\r
+ \r
+/* USER CODE BEGIN (18) */\r
+/* USER CODE END */\r
+\r
+ /* Wait for eFuse controller self-test to complete and check results */\r
+ if (!checkefcSelfTest()) /* eFuse controller ECC logic self-test failed */\r
+ {\r
+ efcClass2Error(); /* device operation is not reliable */\r
+ }\r
+ \r
+/* USER CODE BEGIN (19) */\r
+/* USER CODE END */\r
+\r
+ /** - Set up flash address and data wait states based on the target CPU clock frequency\r
+ * The number of address and data wait states for the target CPU clock frequency are specified\r
+ * in the specific part's datasheet.\r
+ */\r
+ setupFlash();\r
+\r
+/* USER CODE BEGIN (20) */\r
+/* USER CODE END */\r
+\r
+ /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */\r
+ trimLPO();\r
+\r
+/* USER CODE BEGIN (21) */\r
+/* USER CODE END */\r
+\r
+ /** - Check if there was an ESM error from FMC OTP read during power-up */\r
+ fmcBus2Check();\r
+ \r
+/* USER CODE BEGIN (22) */\r
+/* USER CODE END */\r
+\r
+ /** - Wait for PLLs to start up and map clock domains to desired clock sources */\r
+ mapClocks();\r
+\r
+/* USER CODE BEGIN (23) */\r
+/* USER CODE END */\r
+\r
+ /** - set ECLK pins functional mode */\r
+ systemREG1->SYSPC1 = 0U;\r
+\r
+ /** - set ECLK pins default output value */\r
+ systemREG1->SYSPC4 = 0U;\r
+\r
+ /** - set ECLK pins output direction */\r
+ systemREG1->SYSPC2 = 1U;\r
+\r
+ /** - set ECLK pins open drain enable */\r
+ systemREG1->SYSPC7 = 0U;\r
+\r
+ /** - set ECLK pins pullup/pulldown enable */\r
+ systemREG1->SYSPC8 = 0U; \r
+\r
+ /** - set ECLK pins pullup/pulldown select */\r
+ systemREG1->SYSPC9 = 1U;\r
+\r
+ /** - Setup ECLK */\r
+ systemREG1->ECPCNTL = (0U << 24U)\r
+ | (0U << 23U)\r
+ | ((8U - 1U) & 0xFFFFU);\r
+\r
+/* USER CODE BEGIN (24) */\r
+/* USER CODE END */\r
+}\r
+\r
+void systemPowerDown(uint32_t mode)\r
+{\r
+\r
+/* USER CODE BEGIN (25) */\r
+/* USER CODE END */\r
+\r
+ /* Disable clock sources */\r
+ systemREG1->CSDISSET = mode & 0x000000FFU;\r
+\r
+ /* Disable clock domains */\r
+ systemREG1->CDDIS = (mode >> 8U) & 0x00000FFFU;\r
+\r
+ /* Idle CPU */\r
+ asm(" wfi");\r
+\r
+/* USER CODE BEGIN (26) */\r
+/* USER CODE END */\r
+\r
+}\r
+\r
+/* USER CODE BEGIN (27) */\r
+/* USER CODE END */\r
projects / pes-rpp / rpp-test-sw.git / commitdiff