1 ;-------------------------------------------------------------------------------
\r
4 ; (c) Texas Instruments 2009-2012, All rights reserved.
\r
10 ;-------------------------------------------------------------------------------
\r
11 ; Initialize CPU Registers
\r
13 .def _coreInitRegisters_
\r
20 ; After reset, the CPU is in the Supervisor mode (M = 10011)
\r
37 ; Switch to FIQ mode (M = 10001)
\r
47 ; Switch to IRQ mode (M = 10010)
\r
52 ; Switch to Abort mode (M = 10111)
\r
57 ; Switch to Undefined Instruction Mode (M = 11011)
\r
62 ; Switch back to Supervisor Mode (M = 10011)
\r
66 mrc p15, #0x00, r2, c1, c0, #0x02
\r
67 orr r2, r2, #0xF00000
\r
68 mcr p15, #0x00, r2, c1, c0, #0x02
\r
101 ;-------------------------------------------------------------------------------
\r
102 ; Initialize Stack Pointers
\r
104 .def _coreInitStackPointer_
\r
107 _coreInitStackPointer_
\r
123 userSp .word 0x08000000+0x00001000
\r
124 svcSp .word 0x08000000+0x00001000+0x00000100
\r
125 fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100
\r
126 irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100
\r
127 abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100
\r
128 undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100
\r
132 ;-------------------------------------------------------------------------------
\r
135 .def _getCPSRValue_
\r
145 ;-------------------------------------------------------------------------------
\r
146 ; Take CPU to IDLE state
\r
162 ;-------------------------------------------------------------------------------
\r
165 .def _coreEnableVfp_
\r
170 mrc p15, #0x00, r0, c1, c0, #0x02
\r
171 orr r0, r0, #0xF00000
\r
172 mcr p15, #0x00, r0, c1, c0, #0x02
\r
173 mov r0, #0x40000000
\r
179 ;-------------------------------------------------------------------------------
\r
180 ; Enable Event Bus Export
\r
182 .def _coreEnableEventBusExport_
\r
185 _coreEnableEventBusExport_
\r
188 mrc p15, #0x00, r0, c9, c12, #0x00
\r
190 mcr p15, #0x00, r0, c9, c12, #0x00
\r
197 ;-------------------------------------------------------------------------------
\r
198 ; Disable Event Bus Export
\r
200 .def _coreDisableEventBusExport_
\r
203 _coreDisableEventBusExport_
\r
206 mrc p15, #0x00, r0, c9, c12, #0x00
\r
208 mcr p15, #0x00, r0, c9, c12, #0x00
\r
215 ;-------------------------------------------------------------------------------
\r
216 ; Enable RAM ECC Support
\r
218 .def _coreEnableRamEcc_
\r
224 mrc p15, #0x00, r0, c1, c0, #0x01
\r
225 orr r0, r0, #0x0C000000
\r
226 mcr p15, #0x00, r0, c1, c0, #0x01
\r
233 ;-------------------------------------------------------------------------------
\r
234 ; Disable RAM ECC Support
\r
236 .def _coreDisableRamEcc_
\r
239 _coreDisableRamEcc_
\r
242 mrc p15, #0x00, r0, c1, c0, #0x01
\r
243 bic r0, r0, #0x0C000000
\r
244 mcr p15, #0x00, r0, c1, c0, #0x01
\r
251 ;-------------------------------------------------------------------------------
\r
252 ; Enable Flash ECC Support
\r
254 .def _coreEnableFlashEcc_
\r
257 _coreEnableFlashEcc_
\r
260 mrc p15, #0x00, r0, c1, c0, #0x01
\r
261 orr r0, r0, #0x02000000
\r
263 mcr p15, #0x00, r0, c1, c0, #0x01
\r
270 ;-------------------------------------------------------------------------------
\r
271 ; Disable Flash ECC Support
\r
273 .def _coreDisableFlashEcc_
\r
276 _coreDisableFlashEcc_
\r
279 mrc p15, #0x00, r0, c1, c0, #0x01
\r
280 bic r0, r0, #0x02000000
\r
281 mcr p15, #0x00, r0, c1, c0, #0x01
\r
288 ;-------------------------------------------------------------------------------
\r
289 ; Enable Offset via Vic controller
\r
291 .def _coreEnableIrqVicOffset_
\r
294 _coreEnableIrqVicOffset_
\r
297 mrc p15, #0, r0, c1, c0, #0
\r
298 orr r0, r0, #0x01000000
\r
299 mcr p15, #0, r0, c1, c0, #0
\r
306 ;-------------------------------------------------------------------------------
\r
307 ; Get data fault status register
\r
309 .def _coreGetDataFault_
\r
314 mrc p15, #0, r0, c5, c0, #0
\r
320 ;-------------------------------------------------------------------------------
\r
321 ; Clear data fault status register
\r
323 .def _coreClearDataFault_
\r
326 _coreClearDataFault_
\r
330 mcr p15, #0, r0, c5, c0, #0
\r
337 ;-------------------------------------------------------------------------------
\r
338 ; Get instruction fault status register
\r
340 .def _coreGetInstructionFault_
\r
343 _coreGetInstructionFault_
\r
345 mrc p15, #0, r0, c5, c0, #1
\r
351 ;-------------------------------------------------------------------------------
\r
352 ; Clear instruction fault status register
\r
354 .def _coreClearInstructionFault_
\r
357 _coreClearInstructionFault_
\r
361 mcr p15, #0, r0, c5, c0, #1
\r
368 ;-------------------------------------------------------------------------------
\r
369 ; Get data fault address register
\r
371 .def _coreGetDataFaultAddress_
\r
374 _coreGetDataFaultAddress_
\r
376 mrc p15, #0, r0, c6, c0, #0
\r
382 ;-------------------------------------------------------------------------------
\r
383 ; Clear data fault address register
\r
385 .def _coreClearDataFaultAddress_
\r
388 _coreClearDataFaultAddress_
\r
392 mcr p15, #0, r0, c6, c0, #0
\r
399 ;-------------------------------------------------------------------------------
\r
400 ; Get instruction fault address register
\r
402 .def _coreGetInstructionFaultAddress_
\r
405 _coreGetInstructionFaultAddress_
\r
407 mrc p15, #0, r0, c6, c0, #2
\r
413 ;-------------------------------------------------------------------------------
\r
414 ; Clear instruction fault address register
\r
416 .def _coreClearInstructionFaultAddress_
\r
419 _coreClearInstructionFaultAddress_
\r
423 mcr p15, #0, r0, c6, c0, #2
\r
430 ;-------------------------------------------------------------------------------
\r
431 ; Get auxiliary data fault status register
\r
433 .def _coreGetAuxiliaryDataFault_
\r
436 _coreGetAuxiliaryDataFault_
\r
438 mrc p15, #0, r0, c5, c1, #0
\r
444 ;-------------------------------------------------------------------------------
\r
445 ; Clear auxiliary data fault status register
\r
447 .def _coreClearAuxiliaryDataFault_
\r
450 _coreClearAuxiliaryDataFault_
\r
454 mcr p15, #0, r0, c5, c1, #0
\r
461 ;-------------------------------------------------------------------------------
\r
462 ; Get auxiliary instruction fault status register
\r
464 .def _coreGetAuxiliaryInstructionFault_
\r
467 _coreGetAuxiliaryInstructionFault_
\r
469 mrc p15, #0, r0, c5, c1, #1
\r
474 ;-------------------------------------------------------------------------------
\r
475 ; Clear auxiliary instruction fault status register
\r
477 .def _coreClearAuxiliaryInstructionFault_
\r
480 _coreClearAuxiliaryInstructionFault_
\r
484 mrc p15, #0, r0, c5, c1, #1
\r
490 ;-------------------------------------------------------------------------------
\r
491 ; Disable interrupts - R4 IRQ & FIQ
\r
493 .def _disable_interrupt_
\r
496 _disable_interrupt_
\r
503 ;-------------------------------------------------------------------------------
\r
504 ; Disable FIQ interrupt
\r
506 .def _disable_FIQ_interrupt_
\r
509 _disable_FIQ_interrupt_
\r
516 ;-------------------------------------------------------------------------------
\r
517 ; Disable FIQ interrupt
\r
519 .def _disable_IRQ_interrupt_
\r
522 _disable_IRQ_interrupt_
\r
529 ;-------------------------------------------------------------------------------
\r
530 ; Enable interrupts - R4 IRQ & FIQ
\r
532 .def _enable_interrupt_
\r
543 ;-------------------------------------------------------------------------------
\r
544 ; Clear ESM CCM errorss
\r
546 .def _esmCcmErrorsClear_
\r
549 _esmCcmErrorsClear_
\r
551 stmfd sp!, {r0-r2}
\r
552 ldr r0, ESMSR1_REG ; load the ESMSR1 status register address
\r
553 ldr r2, ESMSR1_ERR_CLR
\r
554 str r2, [r0] ; clear the ESMSR1 register
\r
556 ldr r0, ESMSR2_REG ; load the ESMSR2 status register address
\r
557 ldr r2, ESMSR2_ERR_CLR
\r
558 str r2, [r0] ; clear the ESMSR2 register
\r
560 ldr r0, ESMSSR2_REG ; load the ESMSSR2 status register address
\r
561 ldr r2, ESMSSR2_ERR_CLR
\r
562 str r2, [r0] ; clear the ESMSSR2 register
\r
564 ldr r0, ESMKEY_REG ; load the ESMKEY register address
\r
565 mov r2, #0x5 ; load R2 with 0x5
\r
566 str r2, [r0] ; clear the ESMKEY register
\r
568 ldr r0, VIM_INTREQ ; load the INTREQ register address
\r
569 ldr r2, VIM_INT_CLR
\r
570 str r2, [r0] ; clear the INTREQ register
\r
571 ldr r0, CCMR4_STAT_REG ; load the CCMR4 status register address
\r
572 ldr r2, CCMR4_ERR_CLR
\r
573 str r2, [r0] ; clear the CCMR4 status register
\r
574 ldmfd sp!, {r0-r2}
\r
577 ESMSR1_REG .word 0xFFFFF518
\r
578 ESMSR2_REG .word 0xFFFFF51C
\r
579 ESMSR3_REG .word 0xFFFFF520
\r
580 ESMKEY_REG .word 0xFFFFF538
\r
581 ESMSSR2_REG .word 0xFFFFF53C
\r
582 CCMR4_STAT_REG .word 0xFFFFF600
\r
583 ERR_CLR_WRD .word 0xFFFFFFFF
\r
584 CCMR4_ERR_CLR .word 0x00010000
\r
585 ESMSR1_ERR_CLR .word 0x80000000
\r
586 ESMSR2_ERR_CLR .word 0x00000004
\r
587 ESMSSR2_ERR_CLR .word 0x00000004
\r
588 VIM_INT_CLR .word 0x00000001
\r
589 VIM_INTREQ .word 0xFFFFFE20
\r
594 ;-------------------------------------------------------------------------------
\r
595 ; C++ construct table pointers
\r
597 .def __TI_PINIT_Base, __TI_PINIT_Limit
\r
598 .weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit
\r
600 __TI_PINIT_Base .long SHT$$INIT_ARRAY$$Base
\r
601 __TI_PINIT_Limit .long SHT$$INIT_ARRAY$$Limit
\r
605 ;-------------------------------------------------------------------------------
\r