2 * @brief DMM Driver Definition File
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8 /* (c) Texas Instruments 2009-2012, All rights reserved. */
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14 #include "sys_common.h"
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19 * @brief DMM Base Register Definition
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21 * This structure is used to access the DMM module egisters.
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23 /** @typedef dmmBASE_t
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24 * @brief DMM Register Frame Type Definition
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26 * This type is used to access the DMM Registers.
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29 typedef volatile struct dmmBase
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31 uint32_t GLBCTRL; /**< 0x0000: Global control register 0 */
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32 uint32_t INTSET; /**< 0x0004: DMM Interrupt Set Register */
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33 uint32_t INTCLR; /**< 0x0008: DMM Interrupt Clear Register */
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34 uint32_t INTLVL; /**< 0x000C: DMM Interrupt Level Register */
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35 uint32_t INTFLG; /**< 0x0010: DMM Interrupt Flag Register */
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36 uint32_t OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */
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37 uint32_t OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */
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38 uint32_t DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */
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39 uint32_t DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */
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40 uint32_t DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */
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41 uint32_t INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */
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42 uint32_t DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */
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43 uint32_t DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */
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44 uint32_t DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */
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45 uint32_t DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */
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46 uint32_t DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */
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47 uint32_t DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */
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48 uint32_t DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */
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49 uint32_t DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */
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50 uint32_t DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */
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51 uint32_t DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */
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52 uint32_t DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */
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53 uint32_t DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */
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54 uint32_t DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */
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55 uint32_t DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */
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56 uint32_t DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */
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57 uint32_t DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */
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58 uint32_t PC0; /**< 0x006C: DMM Pin Control 0 */
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59 uint32_t PC1; /**< 0x0070: DMM Pin Control 1 */
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60 uint32_t PC2; /**< 0x0074: DMM Pin Control 2 */
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61 uint32_t PC3; /**< 0x0078: DMM Pin Control 3 */
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62 uint32_t PC4; /**< 0x007C: DMM Pin Control 4 */
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63 uint32_t PC5; /**< 0x0080: DMM Pin Control 5 */
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64 uint32_t PC6; /**< 0x0084: DMM Pin Control 6 */
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65 uint32_t PC7; /**< 0x0088: DMM Pin Control 7 */
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66 uint32_t PC8; /**< 0x008C: DMM Pin Control 8 */
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71 * @brief DMM Register Frame Pointer
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73 * This pointer is used by the DMM driver to access the DMM module registers.
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75 #define dmmREG ((dmmBASE_t *)0xFFFFF700U)
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78 * @brief DMM Port Register Pointer
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80 * Pointer used by the GIO driver to access I/O PORT of DMM
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81 * (use the GIO drivers to access the port pins).
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83 #define dmmPORT ((gioPORT_t *)0xFFFFF738U)
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86 /* DMM Interface Functions */
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