]> rtime.felk.cvut.cz Git - pes-rpp/rpp-test-sw.git/blob - include/htu.h
Rewritten for using one task and direct usage of interrupts
[pes-rpp/rpp-test-sw.git] / include / htu.h
1 /** @file htu.h\r
2 *   @brief HTU Driver Definition File\r
3 *   @date 15.Mar.2012\r
4 *   @version 03.01.00\r
5 *   \r
6 */\r
7 \r
8 /* (c) Texas Instruments 2009-2012, All rights reserved. */\r
9 \r
10 \r
11 #ifndef __HTU_H__\r
12 #define __HTU_H__\r
13 \r
14 /* HTU General Definitions */\r
15 \r
16 /** @struct htuBase\r
17 *   @brief HTU Base Register Definition\r
18 *\r
19 *   This structure is used to access the HTU module egisters.\r
20 */\r
21 /** @typedef stcBASE_t\r
22 *   @brief HTU Register Frame Type Definition\r
23 *\r
24 *   This type is used to access the HTU Registers.\r
25 */\r
26 typedef volatile struct htuBase\r
27 {\r
28     uint32_t GC;                                // 0x00\r
29     uint32_t CPENA;                             // 0x04\r
30     uint32_t BUSY0;                             // 0x08\r
31     uint32_t BUSY1;                             // 0x0C\r
32     uint32_t BUSY2;                             // 0x10\r
33     uint32_t BUSY3;                             // 0x14\r
34         uint32_t ACPE;                          // 0x18\r
35     uint32_t : 32;                              // 0x1C\r
36     uint32_t RLBECTRL;                  // 0x20\r
37     uint32_t BFINTS;                    // 0x24\r
38     uint32_t BFINTC;                    // 0x28\r
39     uint32_t INTMAP;                    // 0x2C\r
40     uint32_t : 32;                              // 0x30\r
41     uint32_t INTOFF0;                   // 0x34\r
42     uint32_t INTOFF1;                   // 0x38\r
43     uint32_t BIM;                               // 0x3C\r
44     uint32_t RLOSTFL;                   // 0x40\r
45     uint32_t BFINTFL;                   // 0x44\r
46     uint32_t BERINTFL;                  // 0x48\r
47     uint32_t MP1S;                              // 0x4C\r
48     uint32_t MP1E;                              // 0x50\r
49     uint32_t DCTRL;                             // 0x54\r
50     uint32_t WPR;                               // 0x58\r
51     uint32_t WMR;                               // 0x5C\r
52     uint32_t ID;                                // 0x60\r
53     uint32_t PCR;                               // 0x64\r
54     uint32_t PAR;                               // 0x68\r
55     uint32_t : 32;                              // 0x6C\r
56     uint32_t MPCS;                              // 0x70\r
57     uint32_t MP0S;                              // 0x74\r
58     uint32_t MP0E;                              // 0x78\r
59 } htuBASE_t;\r
60 \r
61 typedef volatile struct htudcp\r
62 {\r
63     uint32_t IFADDRA;                   // 0x00\r
64     uint32_t IFADDRB;                   // 0x04\r
65     uint32_t IHADDRCT;                  // 0x08\r
66     uint32_t ITCOUNT;                   // 0x0C\r
67 } htudcp_t;\r
68 \r
69 typedef volatile struct htucdcp\r
70 {\r
71     uint32_t CFADDRA;                   // 0x100\r
72     uint32_t CFADDRB;                   // 0x104\r
73     uint32_t CFCOUNT;                   // 0x108\r
74 } htucdcp_t;\r
75 \r
76 #define htuREG1   ((htuBASE_t *)0xFFF7A400U)\r
77 #define htuREG2   ((htuBASE_t *)0xFFF7A500U)\r
78 \r
79 #define htuDCP1   ((htudcp_t *)0xFF4E0000U)\r
80 #define htuDCP2   ((htudcp_t *)0xFF4C0000U)\r
81 \r
82 #define htuCDCP1   ((htucdcp_t *)0xFF4E0100U)\r
83 #define htuCDCP2   ((htucdcp_t *)0xFF4C0100U)\r
84 \r
85 #define HTU1PARLOC              (*(unsigned int *)0xFF4E0200U)\r
86 #define HTU2PARLOC              (*(unsigned int *)0xFF4C0200U)\r
87 \r
88 #define HTU1RAMLOC              (*(unsigned int *)0xFF4E0000U)\r
89 #define HTU2RAMLOC              (*(unsigned int *)0xFF4C0000U)\r
90 \r
91 #endif\r