From: Vladimir Burian <buriavl2@fel.cvut.cz>
Date: Sat, 22 Jan 2011 22:41:13 +0000 (+0100)
Subject: Clear of FIFO overflow flag capability added.
X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/uart.git/commitdiff_plain/6e4653e1cd81d552ee2a1b20fb73df26119b78ac

Clear of FIFO overflow flag capability added.
---

diff --git a/fifo.vhd b/fifo.vhd
index 99abce7..04213f1 100644
--- a/fifo.vhd
+++ b/fifo.vhd
@@ -12,6 +12,7 @@ entity fifo is
     reset    : in  std_logic;
     we       : in  std_logic;
     re       : in  std_logic;
+    clear_ow : in  std_logic;
     d_in     : in  std_logic_vector (7 downto 0);
     d_out    : out std_logic_vector (7 downto 0);
     full     : out std_logic;
@@ -57,6 +58,10 @@ begin
           length <= length + 1;
         end if;
       end if;
+      
+      if (clear_ow = '1') then
+        overflow <= '0';
+      end if;
     end if;
   end process;
 
diff --git a/uart.vhd b/uart.vhd
index fe5714f..a599908 100644
--- a/uart.vhd
+++ b/uart.vhd
@@ -75,6 +75,7 @@ architecture dataflow of uart is
       reset    : in  std_logic;
       we       : in  std_logic;
       re       : in  std_logic;
+      clear_ow : in  std_logic;
       d_in     : in  std_logic_vector (7 downto 0);
       d_out    : out std_logic_vector (7 downto 0);
       full     : out std_logic;
@@ -160,6 +161,7 @@ begin
     reset    => puc,
     we       => tx_fifo_we,
     re       => tx_fifo_re,
+    clear_ow => '0',
     d_in     => per_din (7 downto 0),
     d_out    => tx_data,
     full     => open,