2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
15 d_in : in std_logic_vector (7 downto 0);
16 d_out : out std_logic_vector (7 downto 0);
18 hfull : out std_logic;
19 empty : out std_logic;
20 overflow : out std_logic
24 --------------------------------------------------------------------------------
26 architecture behavioral of fifo is
28 subtype mem_addr_t is std_logic_vector (width-1 downto 0);
29 type mem_t is array (3 downto 0) of std_logic_vector (7 downto 0);
31 signal memory : mem_t;
33 signal read_addr : mem_addr_t;
34 signal write_addr : mem_addr_t;
36 signal length : std_logic_vector (width downto 0);
38 signal full_s : std_logic;
40 --------------------------------------------------------------------------------
47 length <= (others => '0');
50 elsif (rising_edge(clk)) then
51 if ((re = '1') and (we = '0')) then
53 elsif ((re = '0') and (we = '1')) then
54 if (full_s = '1') then
67 read_addr <= (others => '0');
68 write_addr <= (others => '0');
70 elsif (rising_edge(clk)) then
72 read_addr <= read_addr + 1;
76 write_addr <= write_addr + 1;
77 memory (conv_integer(write_addr)) <= d_in;
79 if (full_s = '1') then
80 read_addr <= read_addr + 1;
86 --------------------------------------------------------------------------------
88 d_out <= memory (conv_integer(read_addr));
90 full_s <= '1' when (length >= 2**width) else '0';
93 hfull <= '1' when (length >= 2**(width-1)) else '0';
94 empty <= '1' when (length = 0) else '0';