]> rtime.felk.cvut.cz Git - zynq/linux.git/log
zynq/linux.git
5 years agospi: spi-xilinx: Added workaround when startup block is enabled
Sai Krishna Potthuri [Wed, 27 Mar 2019 09:25:03 +0000 (14:55 +0530)]
spi: spi-xilinx: Added workaround when startup block is enabled

In AXI SPI when the startup block is enabled in the hardware
STARTUP block don't provide clock as soon as SPI provides command,
first command fails. So to overcome this issue added a workaround
to perform a dummy Read Id if startup block is enabled in the
hardware.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodt-bindings: Added optional property xlnx,startup-block
Sai Krishna Potthuri [Wed, 27 Mar 2019 09:25:02 +0000 (14:55 +0530)]
dt-bindings: Added optional property xlnx,startup-block

This patch adds optional property xlnx,startup-block
to indicate STARTUP block enable or disable.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agohwmon: pmbus: Add DT wiring for ti,tps544b25
Michal Simek [Mon, 4 Mar 2019 12:51:05 +0000 (13:51 +0100)]
hwmon: pmbus: Add DT wiring for ti,tps544b25

This should be enough for DT wiring to get generic functionality.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: phy: dp83867: Add support for 6-wire mode in SGMII configuration
Radhey Shyam Pandey [Tue, 26 Mar 2019 14:01:32 +0000 (19:31 +0530)]
net: phy: dp83867: Add support for 6-wire mode in SGMII configuration

SGMII interface is capable of working as a 4-wire or 6-wire SGMII
interface. Default is 4-wire mode. Read DT "ti,6-wire-mode" property
to program SGMIICTL1[SGMII_TYPE] 6-wire mode.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodt-bindings: phy: dp83867: Add documentation for SGMII 6-wire mode
Radhey Shyam Pandey [Tue, 26 Mar 2019 14:01:31 +0000 (19:31 +0530)]
dt-bindings: phy: dp83867: Add documentation for SGMII 6-wire mode

Add documentation for optional "ti,6-wire-mode" property which can be
used to program SGMII 6-wire mode configuration.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agov4l: xilinx: scd: Enable 10 bit formats support for memory based IP
Satish Kumar Nagireddy [Tue, 26 Mar 2019 18:26:32 +0000 (11:26 -0700)]
v4l: xilinx: scd: Enable 10 bit formats support for memory based IP

This patch enables 10bit format support in driver. This will configure
the 8bit or 10bit video format in IP based on media bus format set by
the application.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agov4l: xilinx: vpss-csc: Use 10bit media bus codes
Satish Kumar Nagireddy [Tue, 26 Mar 2019 18:26:31 +0000 (11:26 -0700)]
v4l: xilinx: vpss-csc: Use 10bit media bus codes

This patch enables driver to use new YUV 10bit media bus codes.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agov4l: xilinx: tpg: Use 10bit media bus codes
Satish Kumar Nagireddy [Tue, 26 Mar 2019 18:26:30 +0000 (11:26 -0700)]
v4l: xilinx: tpg: Use 10bit media bus codes

This patch enables driver to use new YUV 10bit media bus codes.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agov4l: xilinx: vpss-scaler: Use 10bit media bus codes
Satish Kumar Nagireddy [Tue, 26 Mar 2019 18:26:29 +0000 (11:26 -0700)]
v4l: xilinx: vpss-scaler: Use 10bit media bus codes

This patch enables driver to use new YUV 10bit media bus codes.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agov4l: xilinx: vip: Use correct media bus code for RGB 10bit format
Satish Kumar Nagireddy [Tue, 26 Mar 2019 18:26:28 +0000 (11:26 -0700)]
v4l: xilinx: vip: Use correct media bus code for RGB 10bit format

This patch uses the correct media bus code for RGB 10bit pixel format.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: xilinx: use only 4 words in return payload
Rajan Vaja [Wed, 27 Mar 2019 13:45:10 +0000 (06:45 -0700)]
firmware: xilinx: use only 4 words in return payload

Firmware supports only 4 words in return payload. So use
only 4 words from payload data.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: zynqmp: Remove double empty line
Michal Simek [Wed, 27 Mar 2019 13:19:40 +0000 (14:19 +0100)]
firmware: zynqmp: Remove double empty line

Trivial change found by mainline sync.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: zynqmp: Fix enum value usage
Michal Simek [Wed, 27 Mar 2019 11:58:17 +0000 (12:58 +0100)]
firmware: zynqmp: Fix enum value usage

This way it would not then indicate that START is
actual reset line.

Reported-by: Vesa Jaaskelainen <dachaac@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: zynqmp: Remove unused enum values
Michal Simek [Wed, 27 Mar 2019 11:53:03 +0000 (12:53 +0100)]
firmware: zynqmp: Remove unused enum values

They are not used anywhere in the code that's why remove them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: zynqmp: Sync location with mainline
Michal Simek [Wed, 27 Mar 2019 11:33:15 +0000 (12:33 +0100)]
firmware: zynqmp: Sync location with mainline

Trivial change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: zynqmp: Sync location of get_chipid
Michal Simek [Wed, 27 Mar 2019 09:07:57 +0000 (10:07 +0100)]
firmware: zynqmp: Sync location of get_chipid

Sync with mainline.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomtd: devices: m25p80: Sync driver with mainline
Michal Simek [Wed, 27 Mar 2019 08:19:23 +0000 (09:19 +0100)]
mtd: devices: m25p80: Sync driver with mainline

Just coding style changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomedia: uvcvideo: Sync with mainline
Michal Simek [Wed, 27 Mar 2019 08:01:24 +0000 (09:01 +0100)]
media: uvcvideo: Sync with mainline

Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agousb: dwc3: Remove unused dwc3_set_phydata() function
Michal Simek [Wed, 27 Mar 2019 06:33:39 +0000 (07:33 +0100)]
usb: dwc3: Remove unused dwc3_set_phydata() function

There is no reason to keep this in our tree if it is unused.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Update Micrel PHY details on zc1275 and zc1285
Harini Katakam [Sat, 23 Mar 2019 07:12:31 +0000 (12:42 +0530)]
arm64: zynqmp: Update Micrel PHY details on zc1275 and zc1285

The FMC card AES-FMC-NETW1-G is the necessary to support ethernet
on zc1275 and zc1285 boards. No previous PHYs/FMCs will be supported
on this HW. So update the phy address to 1 and necessary skew values.

Also remove PL IP related nodes and parameters that DTG generates.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Modify the ethernet node for zc1285 revA
Venkatesh Yadav Abbarapu [Fri, 22 Mar 2019 04:02:49 +0000 (09:32 +0530)]
arm64: zynqmp: Modify the ethernet node for zc1285 revA

Removing the gmiitorgmii node, as this is generated by the
DTG.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: zynqmp: Add support for zc1285
Michal Simek [Tue, 5 Mar 2019 14:14:43 +0000 (15:14 +0100)]
arm64: zynqmp: Add support for zc1285

zc1285 is the same as zc1275 but it is using Avnet FMC
http://www.ultrazed.org/product/network-fmc-module

Unfortunatelly not everything is connected now that's why this is only
describing system which Xilinx is using.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: deprecate eth_change_mtu, remove usage
Jarod Wilson [Sat, 23 Mar 2019 10:26:07 +0000 (15:56 +0530)]
net: deprecate eth_change_mtu, remove usage

With centralized MTU checking, there's nothing productive done by
eth_change_mtu that isn't already done in dev_set_mtu, so mark it as
deprecated and remove all usage of it in the kernel. All callers have been
audited for calls to alloc_etherdev* or ether_setup directly, which means
they all have a valid dev->min_mtu and dev->max_mtu. Now eth_change_mtu
prints out a netdev_warn about being deprecated, for the benefit of
out-of-tree drivers that might be utilizing it.

Of note, dvb_net.c actually had dev->mtu = 4096, while using
eth_change_mtu, meaning that if you ever tried changing it's mtu, you
couldn't set it above 1500 anymore. It's now getting dev->max_mtu also set
to 4096 to remedy that.

v2: fix up lantiq_etop, missed breakage due to drive not compiling on x86

CC: netdev@vger.kernel.org
Signed-off-by: Jarod Wilson <jarod@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: macb: Sync macb_config usage with mainline
Harini Katakam [Sat, 23 Mar 2019 10:26:06 +0000 (15:56 +0530)]
net: macb: Sync macb_config usage with mainline

Sync macb_config default init and clk_init with mainline.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: ethernet: macb: use phydev from struct net_device
Philippe Reynes [Sat, 23 Mar 2019 10:26:05 +0000 (15:56 +0530)]
net: ethernet: macb: use phydev from struct net_device

The private structure contain a pointer to phydev, but the structure
net_device already contain such pointer. So we can remove the pointer
phydev in the private structure, and update the driver to use the
one contained in struct net_device.

Rebased on xilinx tree.

Signed-off-by: Philippe Reynes <tremyfr@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Harini Katakam <harini.katakam@xilix.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodmaengine: xilinx_dma: Remove axidma multichannel mode support
Radhey Shyam Pandey [Fri, 22 Mar 2019 16:25:41 +0000 (21:55 +0530)]
dmaengine: xilinx_dma: Remove axidma multichannel mode support

The AXI DMA multichannel support is deprecated in the IP and it is no
longer actively supported. For multichannel support, refer to the AXI
multichannel direct memory access IP product guide(PG228). So it is
decided to remove it's complete support from the driver. Just to
highlight that this patch intentionally breaks backward compatibility.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodt-bindings: dmaengine: xilinx_dma: Remove axidma multichannel support
Radhey Shyam Pandey [Fri, 22 Mar 2019 16:25:40 +0000 (21:55 +0530)]
dt-bindings: dmaengine: xilinx_dma: Remove axidma multichannel support

The AXI DMA multichannel support is deprecated in the IP and it is no
longer actively supported. For multichannel support, refer to the AXI
multichannel direct memory access IP product guide(PG228). So it is
decided to remove it's complete support from the driver. Inline with
it remove axidma multichannel optional properties i.e xlnx,mcdma and
dma-channels from the binding description. Just to highlight that this
patch intentionally breaks backward compatibility.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomtd: devices: m25p80: update the driver
Naga Sureshkumar Relli [Sat, 23 Mar 2019 06:17:04 +0000 (11:47 +0530)]
mtd: devices: m25p80: update the driver

There are changes between xilinx 4.19 kernel m25p80.c and mainline
4.19 kernel m25p80.c. This was happened due to merge. so update the
drver. This update includes below commits from mainline

00a5762 mtd: m25p80: Remove unneeded m25p->command field
4a3e85f mtd: devices: m25p80: Make sure the buffer passed in op is DMA-able
138f5dc mtd: m25p80: add support of SPI 1-2-2 and 1-4-4 protocols
b02b17f mtd: m25p80: Call spi_mem_get_name() to let controller set a
     custom name
1e07392 mtd: devices: m25p80: Use spi_mem_set_drvdata() instead of
      spi_set_drvdata()

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agov4l: xilinx: vip: Add scaling and padding factor for XY10
Satish Kumar Nagireddy [Fri, 22 Mar 2019 22:05:14 +0000 (15:05 -0700)]
v4l: xilinx: vip: Add scaling and padding factor for XY10

This patch adds scaling and padding factors for stride calculation
of XY10 pixel format.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agov4l: xilinx: vip: Add YUV 10bit media bus formats
Satish Kumar Nagireddy [Fri, 22 Mar 2019 22:05:13 +0000 (15:05 -0700)]
v4l: xilinx: vip: Add YUV 10bit media bus formats

This patch introduces separate media bus formats for each 10bit pixel
formats. This way v4l2 subdev applications can differentiate between
8bit and 10bit formats.

YUV420 10bit -> MEDIA_BUS_FMT_VYYUYY10_4X20
YUV422 10bit -> MEDIA_BUS_FMT_UYVY10_1X20
YUV444 10bit -> MEDIA_BUS_FMT_VUY10_1X30

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomedia: v4l: Add YUV 10bit media bus format
Satish Kumar Nagireddy [Fri, 22 Mar 2019 22:05:12 +0000 (15:05 -0700)]
media: v4l: Add YUV 10bit media bus format

This patch adds new media bus formats for YUV420 10bit and YUV444 10bit.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agov4l: xilinx: scd: Fix video format configuration for YUV420
Satish Kumar Nagireddy [Mon, 18 Mar 2019 18:35:55 +0000 (11:35 -0700)]
v4l: xilinx: scd: Fix video format configuration for YUV420

In the current implementation streaming based driver, the video format
value for YUV420 is programmed wrongly. This patch programs it correctly
according to PG322.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomtd: rawnand: arasan: Add support for writes with out WAITRDY instruction
Naga Sureshkumar Relli [Fri, 22 Mar 2019 10:45:33 +0000 (16:15 +0530)]
mtd: rawnand: arasan: Add support for writes with out WAITRDY instruction

Some of the nand write patterns executes with out WAITRDY instruction.
This is found when running mtd_nandbiterrs test.

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: can: xilinx_can: fix chip_start failure with invalid bus
Appana Durga Kedareswara rao [Fri, 22 Mar 2019 12:47:30 +0000 (18:17 +0530)]
net: can: xilinx_can: fix chip_start failure with invalid bus

Currently the xilinx_can xcan_chip_start() function, called from
.ndo_open() and via CAN_MODE_START (bus-off restart), waits for the SR
register to show the wanted operating state, with a 1 sec timeout.

However, that register bit will only be set once the HW has observed 11
consecutive recessive bits (BusIdle) on the bus.

If the bus will not see the 11 bits (e.g. it is stuck dominant), the
function will timeout and return an error.
If this was done as part of a scheduled restart from bus-off, the
interface will stay in bus-off state forever even if the bus recovers
later.
If this was done during interface .ndo_open(), the interface will stay
down.

According to M_CAN and FLEXCAN documentation they also wait for 11
consecutive recessive bits, but their drivers do not seem to wait for
that.

To make the behavior consistent, modify xilinx_can to also not wait for
the synchronization to complete.

The only way for users to know for sure that the bus has been joined
successfully is to see successfully received or transmitted frames. That
does not seem optimal, but it is consistent with other drivers and we
should have a properly working restart-ms with xilinx_can.

Tested on ZynqMP with Xilinx CAN-FD 2.0.

Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: xilinx: axiethernet: Fix axiethernet register description
Radhey Shyam Pandey [Wed, 20 Mar 2019 10:13:29 +0000 (15:43 +0530)]
net: xilinx: axiethernet: Fix axiethernet register description

Rename axiethernet register description to be inline with product guide
register names. It also corrects TEMAC interrupt controller offsets and
removes obsolete registers and bitmasks. There is no major functional
impact since the modified offsets are only used in ethtool get_regs and
not in any programming sequence.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoremoteproc: zynqmp_r5: allow kick not to pass message
Wendy Liang [Tue, 19 Mar 2019 12:01:26 +0000 (05:01 -0700)]
remoteproc: zynqmp_r5: allow kick not to pass message

Allow remoteproc kick not to write to IPI buffer. As remotperoc has
sysfs API to allow userspace to kick r5, it is possible to just raise
interrupt but not write data. Otherwise, it will take more time
to kick remoteproc, as it will need to copy the data to the IPI
buffer.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agospi: Increase the spi time out
Naga Sureshkumar Relli [Thu, 21 Mar 2019 07:24:18 +0000 (12:54 +0530)]
spi: Increase the spi time out

SPI subsystem default time out tolerance for a transfer to be complete
is 100ms. This works well on ZynqMP and Zynq platforms because on these
hardwares QSPI and SPI runs at 100MHz. But on versal emulation platform,
QSPI and SPI runs at 25MHz and core runs at 2.16MHz.
so the wait time should be increased to accommodate that clock, when
using DMA or IO. Otherwise we will get transfer time outs. Hence
increase the transfer time out tolerance.
Based on various testings this tolerance is increased from 200 to 1000.

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomtd: rawnand: Apply nand_reset() only to TOSHIBA parts
Naga Sureshkumar Relli [Fri, 22 Mar 2019 05:39:21 +0000 (11:09 +0530)]
mtd: rawnand: Apply nand_reset() only to TOSHIBA parts

While writing oob, flash chips like TOSHIBA will clear the whole data
page, if there is no nand_reset(). So limit this reset only to these
parts.
We can still go without checking the jedec_id, but arasan_nand driver
does not support setup_data_interface() hook to initialize the flash
timings during reset. arasan_nand driver is not supporting this hook
because the NAND subsystem is not supporting NVDDR modes. so by adding
this check we can support SDR, NVDDR modes in arasan.
And to support this jedec id check, added new jedec_id variable to
struct onfi_params. This is needed until NAND subsystem supports NVDDR
modes.

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: macb: Add NULL check for PCLK and HCLK
Harini Katakam [Fri, 22 Mar 2019 05:20:00 +0000 (10:50 +0530)]
net: macb: Add NULL check for PCLK and HCLK

Both PCLK and HCLK are "required" clocks according to macb devicetree
documentation. There is a chance that devm_clk_get doesn't return a
negative error but just a NULL clock structure instead. In such a case
the driver proceeds as usual and uses pclk value 0 to calculate MDC
divisor which is incorrect. Hence fix the same in clock initialization.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoarm64: dts: zynqmp: Add missing interrupt-names property for dwc3_1 node
Anurag Kumar Vulisha [Tue, 19 Mar 2019 16:03:33 +0000 (16:03 +0000)]
arm64: dts: zynqmp: Add missing interrupt-names property for dwc3_1 node

This patch adds the missing "interrupt-names" property into
dwc3_1 node

Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: can: xilinx_can: Fix incorrect assignment of bittiming_const for canfd
Appana Durga Kedareswara rao [Tue, 19 Mar 2019 08:58:26 +0000 (14:28 +0530)]
net: can: xilinx_can: Fix incorrect assignment of bittiming_const for canfd

commit 9e5f1b2 ("can: xilinx_can: add support for Xilinx CAN FD core")
had wrong assignment of bittiming_const for axi canfd, It should point to
xcan_bittiming_const_canfd structure instead of xcan_bittiming_const_can.

This patch fixes this issue.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: xilinx: Sync positions with mainline
Michal Simek [Wed, 20 Mar 2019 14:04:10 +0000 (15:04 +0100)]
firmware: xilinx: Sync positions with mainline

For easier comparison sync possition of zynqmp_pm_get_chipid and
zynqmp_pm_request_ack.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: xilinx: Sync kernel-doc format with mainline
Michal Simek [Thu, 21 Mar 2019 15:10:09 +0000 (16:10 +0100)]
firmware: xilinx: Sync kernel-doc format with mainline

Adding () is permitted now in kernel-doc format. Sync it with driver
version what it is in mainline.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: xilinx: Remove additional empty line
Michal Simek [Thu, 21 Mar 2019 15:10:05 +0000 (16:10 +0100)]
firmware: xilinx: Remove additional empty line

Trivial fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoxilinx: soc: Remove unused power.h
Michal Simek [Thu, 21 Mar 2019 15:10:00 +0000 (16:10 +0100)]
xilinx: soc: Remove unused power.h

There is no code which includes this file.
Both macros are alread available here:
include/linux/firmware/xlnx-zynqmp.h

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodt-bindings: nand: Remove duplicated dt binding for arasan_nfc
Michal Simek [Thu, 21 Mar 2019 15:09:56 +0000 (16:09 +0100)]
dt-bindings: nand: Remove duplicated dt binding for arasan_nfc

Documentation/devicetree/bindings/mtd/arasan_nand.txt

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodt-bindings: Fix position of xlnx,int-clock-stable-broken property
Michal Simek [Thu, 21 Mar 2019 15:02:39 +0000 (16:02 +0100)]
dt-bindings: Fix position of xlnx,int-clock-stable-broken property

The patch:
"dt-bindings: mmc: broken clock stable indicator on arasan controllers"
(sha1: 26c312281336b55eba01ea1e7b85740d383076c6)
Was adding it as generic optional property not optional property just
for xlnx,zynqmp-8.9a.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodoc: xilinx: Update eemi.txt based on mainline
Michal Simek [Thu, 21 Mar 2019 15:02:29 +0000 (16:02 +0100)]
doc: xilinx: Update eemi.txt based on mainline

Sync with mainline submission.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofpga: zynqmp: Use SPDX license header
Michal Simek [Wed, 20 Mar 2019 09:01:08 +0000 (10:01 +0100)]
fpga: zynqmp: Use SPDX license header

Reflect changes done by mainline submission.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomemory: pl353: Sync headers with mainline
Michal Simek [Wed, 20 Mar 2019 08:59:57 +0000 (09:59 +0100)]
memory: pl353: Sync headers with mainline

There are small chagnes in mailine which should be reflected in this
tree too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: xilinx: Remove unused GGS/PGGS macros
Michal Simek [Wed, 20 Mar 2019 08:58:53 +0000 (09:58 +0100)]
firmware: xilinx: Remove unused GGS/PGGS macros

Remove unused macros from header file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoARM: zynq: Convert to using %pOFn instead of device_node.name
Rob Herring [Tue, 28 Aug 2018 01:52:04 +0000 (20:52 -0500)]
ARM: zynq: Convert to using %pOFn instead of device_node.name

In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agocan: xilinx: defer the probe if clock is not found
Venkatesh Yadav Abbarapu [Thu, 25 Jan 2018 12:34:38 +0000 (18:04 +0530)]
can: xilinx: defer the probe if clock is not found

It's not always the case that clock is already available when can
driver get probed at the first time, e.g. the clock is provided by
clock wizard which may be probed after can driver. So let's defer
the probe when devm_clk_get() call fails and give it chance to
try later.

Signed-off-by: Venkatesh Yadav Abbarapu <vabbarap@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: xilinx: fix debugfs write handler
Jann Horn [Mon, 18 Feb 2019 21:43:09 +0000 (22:43 +0100)]
firmware: xilinx: fix debugfs write handler

 - Userspace wants to write a string with `len` bytes, not counting the
   terminating NULL, so we should allocate `len+1` bytes. It looks like the
   current code relied on having a nullbyte directly behind `kern_buff`,
   which happens to work reliably as long as `len` isn't one of the kmalloc
   size classes.
 - strncpy_from_user() is completely wrong here; userspace is giving us a
   (not necessarily null-terminated) buffer and its length.
   strncpy_from_user() is for cases in which we don't know the length.
 - Don't let broken userspace allocate arbitrarily big kmalloc allocations.

Just use memdup_user_nul(), which is designed precisely for things like
this.

Signed-off-by: Jann Horn <jannh@google.com>
Acked-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: xilinx: axiethernet: Increase TX and RX BD count
Radhey Shyam Pandey [Mon, 18 Mar 2019 13:07:05 +0000 (18:37 +0530)]
net: xilinx: axiethernet: Increase TX and RX BD count

Increase DMA buffer descriptor(BD) count to ensure that even in high
load we always get a free BD in the transmit and receive path.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: xilinx: axiethernet: Check for queue full in transmit path
Radhey Shyam Pandey [Mon, 18 Mar 2019 13:07:04 +0000 (18:37 +0530)]
net: xilinx: axiethernet: Check for queue full in transmit path

As per DMA programming sequence, software must not resubmit a BD which
is already under the hardware control else results are undefined. In
iperf3 stress testing, we observed intermittent zero bandwidth and DMA
IP going into stall state. To fix this behavior, in the transmit path
add a check for queue space before adding new BD elements.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: can: xilinx_can: Fix kernel doc warnings
Appana Durga Kedareswara rao [Mon, 18 Mar 2019 07:41:17 +0000 (13:11 +0530)]
net: can: xilinx_can: Fix kernel doc warnings

This patch fixes below kernel doc warnings
warning: Function parameter or member 'priv' not described in
'xcan_write_frame'
warning: Function parameter or member 'skb' not described in
'xcan_start_xmit_fifo'
warning: Function parameter or member 'ndev' not described in
'xcan_start_xmit_fifo'
warning: Function parameter or member 'skb' not described in
'xcan_start_xmit_mailbox'
warning: Function parameter or member 'ndev' not described in
'xcan_start_xmit_mailbox'
warning: Function parameter or member 'priv' not described in
'xcan_rx_fifo_get_next_frame'

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: can: xilinx_can: Add SPDX license
Appana Durga Kedareswara rao [Mon, 18 Mar 2019 07:41:16 +0000 (13:11 +0530)]
net: can: xilinx_can: Add SPDX license

Update driver to have SPDX identifiers.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: can: xilinx_can: Add support for CANFD FD frames
Appana Durga Kedareswara rao [Mon, 18 Mar 2019 07:41:15 +0000 (13:11 +0530)]
net: can: xilinx_can: Add support for CANFD FD frames

CANFD IP supports both CAN and CAN FD frames,
Existing driver supports only CAN frames, This patch
adds support for CAN FD frames.

Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: can: xilinx_can: Add cantype parameter in xcan_devtype_data struct
Appana Durga Kedareswara rao [Mon, 18 Mar 2019 07:41:14 +0000 (13:11 +0530)]
net: can: xilinx_can: Add cantype parameter in xcan_devtype_data struct

To differentiate between different CAN IP's this patch adds
cantype enum variable in the xcan_devtype_data structure

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: can: xilinx_can: Fix flags field initialization for axi can
Appana Durga Kedareswara rao [Mon, 18 Mar 2019 07:41:13 +0000 (13:11 +0530)]
net: can: xilinx_can: Fix flags field initialization for axi can

AXI CAN IP supports tx fifo empty feature, this patch updates the flags
field for the same.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: can: xilinx_can: Fix style issues
Appana Durga Kedareswara rao [Mon, 18 Mar 2019 07:41:12 +0000 (13:11 +0530)]
net: can: xilinx_can: Fix style issues

This patch fixes below checkpatch warnings and checks in the driver.

CHECK: Alignment should match open parenthesis
+       void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
+                       u32 val);

CHECK: Alignment should match open parenthesis
+static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
+                       u32 val)

CHECK: Alignment should match open parenthesis
+static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
+                       u32 val)

CHECK: Alignment should match open parenthesis
+       netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
+                       priv->read_reg(priv, XCAN_BRPR_OFFSET),

CHECK: Alignment should match open parenthesis
+                       netdev_warn(ndev,
+                               "timed out for correct mode\n");

CHECK: Alignment should match open parenthesis
+       netdev_dbg(ndev, "status:#x%08x\n",
+                       priv->read_reg(priv, XCAN_SR_OFFSET));

CHECK: spaces preferred around that '-' (ctx:VxV)
+                       (CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
                                        ^

CHECK: Alignment should match open parenthesis
+       netdev_dbg(ndev, "%s: error status register:0x%x\n",
+                       __func__, priv->read_reg(priv, XCAN_ESR_OFFSET));

WARNING: line over 80 characters
+                       offset = XCAN_RXMSG_2_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);

WARNING: line over 80 characters
+                       offset = XCAN_RXMSG_FRAME_OFFSET(fsr & XCAN_FSR_RI_MASK);

WARNING: line over 80 characters
+               while ((isr & XCAN_IXR_TXOK_MASK) && !WARN_ON(++retries == 100)) {

WARNING: line over 80 characters
+                       priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);

CHECK: Alignment should match open parenthesis
+               netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
+                               __func__, ret);

CHECK: Alignment should match open parenthesis
+       ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
+                       ndev->name, ndev);

CHECK: Alignment should match open parenthesis
+static int xcan_get_berr_counter(const struct net_device *ndev,
+                                       struct can_berr_counter *bec)

CHECK: Alignment should match open parenthesis
+               netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
+                               __func__, ret);

CHECK: Please don't use multiple blank lines
+
+

CHECK: Alignment should match open parenthesis
+               netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
+                       __func__, ret);`

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Acked-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoremoteproc: zynqmp_r5: ack IPI before checking vrings
Wendy Liang [Sun, 17 Mar 2019 10:47:56 +0000 (03:47 -0700)]
remoteproc: zynqmp_r5: ack IPI before checking vrings

If we ack IPI interrupt after checking vrings, it is
possible to miss some IPI interrupts. Ack the IPI
interrupts before checking the vrings to make sure
no IPI interrupts are missed.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agomtd: spi-nor: Added support for ISSI Serial NOR Flash
Amit Kumar Mahapatra [Fri, 15 Mar 2019 15:08:22 +0000 (20:38 +0530)]
mtd: spi-nor: Added support for ISSI Serial NOR Flash

For ISSI flash connected in dual parallel mode, the stripe
was getting enabled while writing configuration data to the
flashes.

So the configuration register of only one of the two flashes
was getting updated.

Due to this flash read/write operation was failing in dual
parallel mode.

This patch fixed the issue by disabling stripe while writing
configuration data to the flash in dual parallel mode.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agousb: dwc3: route lpd usb traffic through CCI path for making SMMU work
Anurag Kumar Vulisha [Fri, 15 Mar 2019 11:27:41 +0000 (11:27 +0000)]
usb: dwc3: route lpd usb traffic through CCI path for making SMMU work

usb dma traffic by default takes the direct DDR path from LPD switch.
Since SMMU is present before CCI, the usb dma traffic needs to be
routed to take the CCI path for making SMMU work. This can be done
by enabling "coherency" in usb.

This patch modifies the code to enable coherency in usb for below
mentioned cases

1. To route usb dma transactions through CCI path for coherency. This is
   done when "dma-coherent" property is added into dwc3 dts node.
2. To route usb dma transactions through CCI path to make SMMU work with
   usb dma. This is done when "dwc->dev->iommu_group" is populated
   (iommu_group is only populated when sucessfull smmu comtext for usb is
   created).

Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: macb: Check for SKBTX_HW_TSTAMP in macb driver
Paul Thomas [Thu, 14 Mar 2019 10:11:33 +0000 (15:41 +0530)]
net: macb: Check for SKBTX_HW_TSTAMP in macb driver

Make sure SKBTX_HW_TSTAMP (i.e. SOF_TIMESTAMPING_TX_HARDWARE) has
been enabled for this skb. This is a common practice in handling TX
timestamp. It fixes the issue where normal socks that aren't
expecting a timestamp will not wake up on select.

Fixed if statement, modified commit description and tested.
- Harini

Signed-off-by: Paul Thomas <pthomas8589@gmail.com>
Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: macb: Optimize reading HW timestamp
Harini Katakam [Thu, 14 Mar 2019 10:11:32 +0000 (15:41 +0530)]
net: macb: Optimize reading HW timestamp

The seconds input from BD (6 bits) just needs to be ORed with the
upper bits from timer in this function. Avoid +/- operations every
single time. Check for seconds rollover at BIT 5 and subtract the
overhead only in that case.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: macb: Fix SUBNS increment and increase resolution
Harini Katakam [Thu, 14 Mar 2019 10:11:31 +0000 (15:41 +0530)]
net: macb: Fix SUBNS increment and increase resolution

The subns increment register has 24 bits as follows:
RegBit[15:0] = Subns[23:8]; RegBit[31:24] = Subns[7:0]

Fix the same in the driver and increase sub ns resolution to the
best capable, 24 bits.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: macb: Add separate definition for PPM fraction
Harini Katakam [Thu, 14 Mar 2019 10:11:30 +0000 (15:41 +0530)]
net: macb: Add separate definition for PPM fraction

The scaled ppm parameter passed to _adjfine() contains a 16 bit
fraction. This just happens to be the same as SUBNSINCR_SIZE now.
Hence define this separately.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agonet: xilinx: axiethernet: Fix code checker warnings
Radhey Shyam Pandey [Thu, 14 Mar 2019 08:46:03 +0000 (14:16 +0530)]
net: xilinx: axiethernet: Fix code checker warnings

Remove map_dma_q_irq() redundant definition and also reduce the scope of
axienet_queue_xmit function. This patch fixes below sparse warnings.

drivers/net/ethernet/xilinx/xilinx_axienet_main.c: At top level:
drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1004:5: warning: no previous
prototype for ‘axienet_queue_xmit’ [-Wmissing-prototypes]
int axienet_queue_xmit(struct sk_buff *skb, struct net_device *ndev,
u16 map)
     ^~~~~~~~~~~~~~~~~~
drivers/net/ethernet/xilinx/xilinx_axienet_main.c:1471:5: warning: no previous
prototype for ‘map_dma_q_irq’ [-Wmissing-prototypes]
int map_dma_q_irq(int irq, struct axienet_local *lp)

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodt-bindings: net: xilinx_axienet: Correct "xlnx,include-dre" binding description
Radhey Shyam Pandey [Thu, 14 Mar 2019 08:46:02 +0000 (14:16 +0530)]
dt-bindings: net: xilinx_axienet: Correct "xlnx,include-dre" binding description

Inline with driver implementation, document "xlnx,include-dre" as a DMA
node optional property.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoremoteproc: zynqmp_r5: update peek remote
Wendy Liang [Thu, 14 Mar 2019 07:09:24 +0000 (00:09 -0700)]
remoteproc: zynqmp_r5: update peek remote

Update the peek remote operation to sync with the remoteproc
header change.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoremoteproc: sysfs: add attribute to get remote message
Wendy Liang [Thu, 14 Mar 2019 07:09:23 +0000 (00:09 -0700)]
remoteproc: sysfs: add attribute to get remote message

Add sysfs device file attribute to get message from remote.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoremoteproc: returns message for peek remote kick function
Wendy Liang [Thu, 14 Mar 2019 07:09:22 +0000 (00:09 -0700)]
remoteproc: returns message for peek remote kick function

Update the peek remote kick API to also return the message
from remote.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoremoteproc: sysfs: allow kick to pass small data
Wendy Liang [Thu, 14 Mar 2019 07:09:21 +0000 (00:09 -0700)]
remoteproc: sysfs: allow kick to pass small data

Allow kick to pass small data. The size of the data to pass by sysfs
kick depends on the kick rproc operation implementation. For now, the
size is sizeof(int).

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoremoteproc: zynqmp_r5: send vqid with kick
Wendy Liang [Thu, 14 Mar 2019 07:09:20 +0000 (00:09 -0700)]
remoteproc: zynqmp_r5: send vqid with kick

Enable the kick function to send vqid.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agoUSB: gadget: f_hid: fix deadlock in f_hidg_write()
Anurag Kumar Vulisha [Thu, 14 Mar 2019 11:45:20 +0000 (11:45 +0000)]
USB: gadget: f_hid: fix deadlock in f_hidg_write()

In f_hidg_write() the write_spinlock is acquired before calling
usb_ep_queue() which causes a deadlock when dummy_hcd is being used.
This is because dummy_queue() callbacks into f_hidg_req_complete() which
tries to acquire the same spinlock. This is (part of) the backtrace when
the deadlock occurs:

  0xffffffffc06b1410 in f_hidg_req_complete
  0xffffffffc06a590a in usb_gadget_giveback_request
  0xffffffffc06cfff2 in dummy_queue
  0xffffffffc06a4b96 in usb_ep_queue
  0xffffffffc06b1eb6 in f_hidg_write
  0xffffffff8127730b in __vfs_write
  0xffffffff812774d1 in vfs_write
  0xffffffff81277725 in SYSC_write

Fix this by releasing the write_spinlock before calling usb_ep_queue()

Signed-off-by: Radoslav Gerganov <rgerganov@vmware.com>
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agofirmware: zynqmp: Fix feature check response
Rajan Vaja [Wed, 13 Mar 2019 17:28:01 +0000 (10:28 -0700)]
firmware: zynqmp: Fix feature check response

Actual response of feature check API is stored in
index 1 of response. Data at index 0 represents
status of API not response.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
5 years agodrm: xlnx: scaler: Add max width and height properties
Vishal Sagar [Thu, 14 Mar 2019 10:56:00 +0000 (03:56 -0700)]
drm: xlnx: scaler: Add max width and height properties

This patch adds support to parse xlnx,max-width and xlnx,max-height from
the device tree node and save the maximum dimensions. This breaks
backward compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodt-bindings: display: xlnx: Add max width and height as mandatory properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:59 +0000 (03:55 -0700)]
dt-bindings: display: xlnx: Add max width and height as mandatory properties

The patch adds xlnx,max-width and xlnx,max-height mandatory device tree
properties. This breaks backward compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodrm: xlnx: csc: Add max width and height dt properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:58 +0000 (03:55 -0700)]
drm: xlnx: csc: Add max width and height dt properties

This patch gets the maximum width and height of frame from the device
tree properties xlnx,max-width and xlnx,max-height. This breaks backward
compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodt-bindings: display: xlnx: vpss-csc: Add max width and height properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:57 +0000 (03:55 -0700)]
dt-bindings: display: xlnx: vpss-csc: Add max width and height properties

This patch adds xlnx,max-width and xlnx,max-height mandatory dt
properties for the VPSS as CSC. This breaks backward compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agov4l: xilinx: vpss-scaler: Make max width and height mandatory properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:56 +0000 (03:55 -0700)]
v4l: xilinx: vpss-scaler: Make max width and height mandatory properties

This patch makes the xlnx,max-width and xlnx,max-height as mandatory dt
properties. This breaks backward compatibility and a warning message is
hence added.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodt-bindings: media: vpss-scaler: Make max width and height mandatory properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:55 +0000 (03:55 -0700)]
dt-bindings: media: vpss-scaler: Make max width and height mandatory properties

This patch makes xlnx,max-width and xlnx,max-height as mandatory dt
properties. This breaks backward compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agov4l: xilinx-vpss-csc: Make max width and height mandatory properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:54 +0000 (03:55 -0700)]
v4l: xilinx-vpss-csc: Make max width and height mandatory properties

This patch makes xlnx,max-width and xlnx,max-height as mandatory
properties. This breaks backward compatibility and a warning message is
added.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodt-bindings: media: vpss-csc: Make max width and height mandatory properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:53 +0000 (03:55 -0700)]
dt-bindings: media: vpss-csc: Make max width and height mandatory properties

This patch makes the xlnx,max-width and xlnx,max-height mandatory dt
properties. This breaks backward compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodmaengine: xilinx: frmbuf: Make max-width and max-height mandatory properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:52 +0000 (03:55 -0700)]
dmaengine: xilinx: frmbuf: Make max-width and max-height mandatory properties

This patch makes the xlnx,max-width and xlnx,max-height mandatory
properties in the device tree node. Since this breaks backward
compatibility, a warning message is added.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodt-bindings: dma: xilinx_frmbuf: Make max-width and max-height as mandatory properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:51 +0000 (03:55 -0700)]
dt-bindings: dma: xilinx_frmbuf: Make max-width and max-height as mandatory properties

This patch makes xlnx,max-width and xlnx,max-height as mandatory
properties. This breaks backward compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agov4l: xilinx-gamma: Make max-width and max-height mandatory dt properties
Vishal Sagar [Thu, 14 Mar 2019 10:55:50 +0000 (03:55 -0700)]
v4l: xilinx-gamma: Make max-width and max-height mandatory dt properties

This patch makes the xlnx,max-width and xlnx,max-height mandatory dt
properties. As this breaks backward compatibility, a warning message is
also added.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodt-bindings: media: xilinx: vpss-csc: Make max width, height mandatory
Vishal Sagar [Thu, 14 Mar 2019 10:55:49 +0000 (03:55 -0700)]
dt-bindings: media: xilinx: vpss-csc: Make max width, height mandatory

This patch makes the xlnx,max-width and xlnx,max-height dt properties as
mandatory. This breaks backward compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agov4l: xilinx-demosaic: Make max width and height properties mandatory
Vishal Sagar [Thu, 14 Mar 2019 10:55:48 +0000 (03:55 -0700)]
v4l: xilinx-demosaic: Make max width and height properties mandatory

This patch makes xlnx,max-width and xlnx,max-height dt properties
mandatory. It breaks backward compatibility and has a warning message
for this.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodt-bindings: media: xilinx: demosaic: Make max width, height mandatory
Vishal Sagar [Thu, 14 Mar 2019 10:55:47 +0000 (03:55 -0700)]
dt-bindings: media: xilinx: demosaic: Make max width, height mandatory

This patch makes the xlnx,max-width and xlnx,max-height dt properties
mandatory and breaks backwards compatibility.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agomedia: xilinx: tpg: Add support for v8.0
Vishal Sagar [Thu, 14 Mar 2019 10:02:58 +0000 (03:02 -0700)]
media: xilinx: tpg: Add support for v8.0

Adds support for the v8.0 compatible string. Now the hls flag is set if
the compatible string is not v5.0. This patch makes the xlnx,max-height
and xlnx,max-width as mandatory properties. It also fixes the enum
format.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodt-bindings: media: xilinx: tpg: Update for v8.0
Vishal Sagar [Thu, 14 Mar 2019 10:02:57 +0000 (03:02 -0700)]
dt-bindings: media: xilinx: tpg: Update for v8.0

Update the bindings for v8.0 of IP by introducing new compatible string.
Make xlnx,max-width and xlnx,max-height as mandatory v8.0 onwards.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agov4l: xilinx: dma: Add YUV 12bit and 16bit format support
Satish Kumar Nagireddy [Wed, 13 Mar 2019 23:50:54 +0000 (16:50 -0700)]
v4l: xilinx: dma: Add YUV 12bit and 16bit format support

This patch adds support for below formats:
 - YUV 420 12bit
 - YUV 420 16bit
 - YUV 422 12bit
 - YUV 422 16bit
 - Y_Only 12bit
 - Y_Only 16bit
 - Rename pixel format for Y_Only 10bit as V4L2_PIX_FMT_XY10

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agomedia: v4l2-ioctl: Add YUV 12bit and 16bit pixel formats
Satish Kumar Nagireddy [Wed, 13 Mar 2019 23:50:53 +0000 (16:50 -0700)]
media: v4l2-ioctl: Add YUV 12bit and 16bit pixel formats

This patch adds YUV 12bit and 16bit pixel formats.

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agomedia: v4l: Add YUV 12bit and 16bit media bus formats
Satish Kumar Nagireddy [Wed, 13 Mar 2019 23:50:52 +0000 (16:50 -0700)]
media: v4l: Add YUV 12bit and 16bit media bus formats

This patch adds media bus formats for below pixel formats:
 - YUV 420 12bit
 - YUV 420 16bit
 - YUV 422 16bit
 - Y_Only 16bit

Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodrm: xlnx: dsi: Fix the drm property creation
Vishal Sagar [Wed, 13 Mar 2019 06:39:42 +0000 (23:39 -0700)]
drm: xlnx: dsi: Fix the drm property creation

The DRM_MODE_PROP_PENDING flag is getting deprecated in 4.19 kernel.
So clear this flag to fix the drm property creation logic.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agodrm: xlnx: zynqmp_dp: Fix DP aux related issues
Rohit Visavalia [Tue, 12 Mar 2019 14:04:59 +0000 (07:04 -0700)]
drm: xlnx: zynqmp_dp: Fix DP aux related issues

drm_dp_dpcd_read() uses zynqmp_dp_aux_transfer(), and
zynqmp_dp_aux_transfer() needs DP status as connected to generate
aux transactions. Then add retry for drm_dp_dpcd_read(), as it can
fail on first attempt, for example, with DP to HDMI adapter.

Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
5 years agoarm64: dts: zynqmp: Add optional gpio phy reset properties
Harini Katakam [Wed, 13 Mar 2019 14:11:19 +0000 (19:41 +0530)]
arm64: dts: zynqmp: Add optional gpio phy reset properties

Add gpio phy reset via I2C expander TCA6416 on board ZCU102.
A warning call trace is observer in probe when this reset is called
from context that can sleep. Keep this commented until that is
resolved in phylib.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>