update

git-svn-id: http://svn.tudos.org/repos/oc/tudos/trunk@19 d050ee49-bd90-4346-b210-929a50b99cfc

diff --git a/kernel/fiasco/src/Modules.amd64 b/kernel/fiasco/src/Modules.amd64
index 063a959c6d2029470af868ca598567ebd76cd461..373abc1a56f7272c41224977e3c5a44861f0a8fe 100644 (file)
--- a/kernel/fiasco/src/Modules.amd64
+++ b/kernel/fiasco/src/Modules.amd64
@@ -30,7 +30,7 @@ PREPROCESS_PARTS-$(CONFIG_SERIAL)            += serial 16550
 PREPROCESS_PARTS-$(CONFIG_WATCHDOG)          += watchdog
 PREPROCESS_PARTS-$(CONFIG_PERF_CNT)          += perf_cnt
 PREPROCESS_PARTS-$(CONFIG_IO_PROT)           += io
 PREPROCESS_PARTS-$(CONFIG_WATCHDOG)          += watchdog
 PREPROCESS_PARTS-$(CONFIG_PERF_CNT)          += perf_cnt
 PREPROCESS_PARTS-$(CONFIG_IO_PROT)           += io

-PREPROCESS_PARTS-$(CONFIG_CPU_VIRT)          += svm
+PREPROCESS_PARTS-$(CONFIG_CPU_VIRT)          += svm vmx

 PREPROCESS_PARTS-$(CONFIG_SCHED_FIXED_PRIO)  += sched_fixed_prio
 PREPROCESS_PARTS-$(CONFIG_SCHED_WFQ)         += sched_wfq
 PREPROCESS_PARTS-$(CONFIG_SCHED_FP_WFQ)      += sched_fp_wfq
 PREPROCESS_PARTS-$(CONFIG_SCHED_FIXED_PRIO)  += sched_fixed_prio
 PREPROCESS_PARTS-$(CONFIG_SCHED_WFQ)         += sched_wfq
 PREPROCESS_PARTS-$(CONFIG_SCHED_FP_WFQ)      += sched_fp_wfq


@@ -119,8 +119,7 @@ INTERFACES_KERNEL   := cpu_mask rcupdate pages kobject_mapdb \
                           buddy_alloc vkey kdb_ke prio_list ipi timer_irq \
                           scheduler clock vm_factory \
 
                           buddy_alloc vkey kdb_ke prio_list ipi timer_irq \
                           scheduler clock vm_factory \
 

-
-INTERFACES_KERNEL-$(CONFIG_CPU_VIRT) += svm vm vm_svm
+INTERFACES_KERNEL-$(CONFIG_CPU_VIRT) += svm vmx vm vm_svm vm_vmx

 
 PREPROCESS_PARTS       += ulock
 INTERFACES_KERNEL      += u_semaphore
 
 PREPROCESS_PARTS       += ulock
 INTERFACES_KERNEL      += u_semaphore


@@ -257,7 +256,7 @@ ASSRC_KERNEL                := entry.S entry-native.S shortcut.S
 
 ASSRC_KERNEL-$(CONFIG_KIP_SYSCALLS_ABS) += sys_call_page-asm.S
 ASSRC_KERNEL-$(CONFIG_MP)               += tramp-mp.S entry-mp.S
 
 ASSRC_KERNEL-$(CONFIG_KIP_SYSCALLS_ABS) += sys_call_page-asm.S
 ASSRC_KERNEL-$(CONFIG_MP)               += tramp-mp.S entry-mp.S

-ASSRC_KERNEL-$(CONFIG_CPU_VIRT)         += vm_svm_asm.S
+ASSRC_KERNEL-$(CONFIG_CPU_VIRT)         += vm_svm_asm.S vm_vmx_asm.S

 ASSRC_KERNEL                            += $(ASSRC_KERNEL-y)
 
 NOOPT                  += $(filter jdb%,\
 ASSRC_KERNEL                            += $(ASSRC_KERNEL-y)
 
 NOOPT                  += $(filter jdb%,\

diff --git a/kernel/fiasco/src/Modules.ia32 b/kernel/fiasco/src/Modules.ia32
index b34209f7def03ecd65345db619fe312c51556801..5fe944994c82f4c19004c79d5a029fe16209457a 100644 (file)
--- a/kernel/fiasco/src/Modules.ia32
+++ b/kernel/fiasco/src/Modules.ia32
@@ -30,7 +30,7 @@ PREPROCESS_PARTS-$(CONFIG_SERIAL)            += serial 16550
 PREPROCESS_PARTS-$(CONFIG_WATCHDOG)          += watchdog
 PREPROCESS_PARTS-$(CONFIG_PERF_CNT)          += perf_cnt
 PREPROCESS_PARTS-$(CONFIG_IO_PROT)           += io
 PREPROCESS_PARTS-$(CONFIG_WATCHDOG)          += watchdog
 PREPROCESS_PARTS-$(CONFIG_PERF_CNT)          += perf_cnt
 PREPROCESS_PARTS-$(CONFIG_IO_PROT)           += io

-PREPROCESS_PARTS-$(CONFIG_CPU_VIRT)          += svm
+PREPROCESS_PARTS-$(CONFIG_CPU_VIRT)          += svm vmx

 PREPROCESS_PARTS-$(CONFIG_SCHED_FIXED_PRIO)  += sched_fixed_prio
 PREPROCESS_PARTS-$(CONFIG_SCHED_WFQ)         += sched_wfq
 PREPROCESS_PARTS-$(CONFIG_SCHED_FP_WFQ)      += sched_fp_wfq
 PREPROCESS_PARTS-$(CONFIG_SCHED_FIXED_PRIO)  += sched_fixed_prio
 PREPROCESS_PARTS-$(CONFIG_SCHED_WFQ)         += sched_wfq
 PREPROCESS_PARTS-$(CONFIG_SCHED_FP_WFQ)      += sched_fp_wfq


@@ -122,7 +122,7 @@ INTERFACES_KERNEL   := cpu_mask rcupdate pages kobject_mapdb \
                           scheduler clock vm_factory \
                           sys_call_page
 
                           scheduler clock vm_factory \
                           sys_call_page
 

-INTERFACES_KERNEL-$(CONFIG_CPU_VIRT) += svm vm vm_svm
+INTERFACES_KERNEL-$(CONFIG_CPU_VIRT) += svm vmx vm vm_svm vm_vmx

 
 PREPROCESS_PARTS       += ulock
 INTERFACES_KERNEL      += u_semaphore
 
 PREPROCESS_PARTS       += ulock
 INTERFACES_KERNEL      += u_semaphore


@@ -257,7 +257,7 @@ CXXSRC_KERNEL               := kernel_panic.cc libc_backend_lock.cc
 ASSRC_KERNEL           := entry.S entry-native.S sys_call_page-asm.S
 
 ASSRC_KERNEL-$(CONFIG_MP)               += tramp-mp.S entry-mp.S
 ASSRC_KERNEL           := entry.S entry-native.S sys_call_page-asm.S
 
 ASSRC_KERNEL-$(CONFIG_MP)               += tramp-mp.S entry-mp.S

-ASSRC_KERNEL-$(CONFIG_CPU_VIRT)         += vm_svm_asm.S
+ASSRC_KERNEL-$(CONFIG_CPU_VIRT)         += vm_svm_asm.S vm_vmx_asm.S

 ASSRC_KERNEL                            += $(ASSRC_KERNEL-y)
 
 NOOPT                  += $(filter jdb%,\
 ASSRC_KERNEL                            += $(ASSRC_KERNEL-y)
 
 NOOPT                  += $(filter jdb%,\

diff --git a/kernel/fiasco/src/abi/virt-ia32-amd64.cpp b/kernel/fiasco/src/abi/virt-ia32-amd64.cpp
index dcf1d8098f32f03d9d8776077abe41a19d9e3914..f9c3755868b5264c97662a50b74bf0b9e89eed85 100644 (file)
--- a/kernel/fiasco/src/abi/virt-ia32-amd64.cpp
+++ b/kernel/fiasco/src/abi/virt-ia32-amd64.cpp
@@ -145,4 +145,3 @@ struct Vmcb
   Vmcb_control_area control_area;
   Vmcb_state_save_area state_save_area;
 } __attribute__((packed));
   Vmcb_control_area control_area;
   Vmcb_state_save_area state_save_area;
 } __attribute__((packed));

-

diff --git a/kernel/fiasco/src/drivers/amd64/processor-amd64.cpp b/kernel/fiasco/src/drivers/amd64/processor-amd64.cpp
index 3ea94dc6b4b0b7d5c088f1672c855643ac5c7922..07d87b4aa90f00681fa5273105122510027184f0 100644 (file)
--- a/kernel/fiasco/src/drivers/amd64/processor-amd64.cpp
+++ b/kernel/fiasco/src/drivers/amd64/processor-amd64.cpp
@@ -32,7 +32,7 @@ void Proc::stack_pointer(Mword sp)
 }
 
 IMPLEMENT static inline
 }
 
 IMPLEMENT static inline

-Mword Proc::program_counter ()
+Mword ALWAYS_INLINE Proc::program_counter()

 {
   Mword pc;
   asm volatile ("call 1f ; 1: pop %0" : "=r"(pc));
 {
   Mword pc;
   asm volatile ("call 1f ; 1: pop %0" : "=r"(pc));

diff --git a/kernel/fiasco/src/drivers/amd64/reset-amd64.cpp b/kernel/fiasco/src/drivers/amd64/reset-amd64.cpp
index 5ab684e01e0b10432237f8626218c802d0fdf0fa..9b075f683127fc227ba456c422b550258c0735d4 100644 (file)
--- a/kernel/fiasco/src/drivers/amd64/reset-amd64.cpp
+++ b/kernel/fiasco/src/drivers/amd64/reset-amd64.cpp
@@ -1,3 +1,17 @@
+IMPLEMENTATION[amd64 && vmx]:
+
+static void
+virt_off()
+{
+  asm volatile("vmxoff");
+}
+
+IMPLEMENTATION[amd64 && !vmx]:
+
+static void
+virt_off()
+{}
+

 IMPLEMENTATION[amd64]:
 
 #include "io.h"
 IMPLEMENTATION[amd64]:
 
 #include "io.h"


@@ -7,6 +21,8 @@ IMPLEMENTATION[amd64]:
 void __attribute__ ((noreturn))
 pc_reset()
 {
 void __attribute__ ((noreturn))
 pc_reset()
 {

+  virt_off();
+

   // i8042: store the next byte at port 0x60 as command byte
   while (Io::in8 (0x64) & 0x2)
     ;
   // i8042: store the next byte at port 0x60 as command byte
   while (Io::in8 (0x64) & 0x2)
     ;

diff --git a/kernel/fiasco/src/drivers/ia32/reset-ia32.cpp b/kernel/fiasco/src/drivers/ia32/reset-ia32.cpp
index ba73aaf1ad72a29c4361b147c783a53d1d3689ea..d0509e4d73d9e0061811afe63da48467f55531f0 100644 (file)
--- a/kernel/fiasco/src/drivers/ia32/reset-ia32.cpp
+++ b/kernel/fiasco/src/drivers/ia32/reset-ia32.cpp
@@ -1,3 +1,17 @@
+IMPLEMENTATION[ia32 && vmx]:
+
+static void
+virt_off()
+{
+  asm volatile("vmxoff");
+}
+
+IMPLEMENTATION[ia32 && !vmx]:
+
+static void
+virt_off()
+{}
+

 IMPLEMENTATION[ia32]:
 
 #include "io.h"
 IMPLEMENTATION[ia32]:
 
 #include "io.h"


@@ -7,6 +21,8 @@ IMPLEMENTATION[ia32]:
 void __attribute__ ((noreturn))
 pc_reset()
 {
 void __attribute__ ((noreturn))
 pc_reset()
 {

+  virt_off();
+

   // i8042: store the next byte at port 0x60 as command byte
   while (Io::in8 (0x64) & 0x2)
     ;
   // i8042: store the next byte at port 0x60 as command byte
   while (Io::in8 (0x64) & 0x2)
     ;

diff --git a/kernel/fiasco/src/jdb/jdb_thread_list.cpp b/kernel/fiasco/src/jdb/jdb_thread_list.cpp
index a5df9e82f4c2926a7f8b2bb40cdb1a24748f57f9..117fe5fd6b3e1a6ea6303128ac8190fe9be7f80a 100644 (file)
--- a/kernel/fiasco/src/jdb/jdb_thread_list.cpp
+++ b/kernel/fiasco/src/jdb/jdb_thread_list.cpp
@@ -643,10 +643,14 @@ Jdb_thread_list::list_threads(Thread *t_start, char pr)
   unsigned y, y_max;
   Thread *t, *t_current = t_start;
 
   unsigned y, y_max;
   Thread *t, *t_current = t_start;
 

-
-  // enqueue current, which may not be in the ready list due to lazy queueing
-  if (!t_current->in_ready_list())
-    t_current->ready_enqueue();
+    {
+      // Hm, we are in JDB, however we have to make the assertion in
+      // ready_enqueue happy.
+      Lock_guard<Cpu_lock> g(&cpu_lock);
+      // enqueue current, which may not be in the ready list due to lazy queueing
+      if (!t_current->in_ready_list())
+        t_current->ready_enqueue();
+    }

 
   Jdb::clear_screen();
   show_header();
 
   Jdb::clear_screen();
   show_header();

diff --git a/kernel/fiasco/src/kern/app_cpu_thread.cpp b/kernel/fiasco/src/kern/app_cpu_thread.cpp
index f722161d24bb70e592e6bdd6acc080a81a7e79b1..1c7a16ba60ad2518e6c681438ce3a7ebb152350b 100644 (file)
--- a/kernel/fiasco/src/kern/app_cpu_thread.cpp
+++ b/kernel/fiasco/src/kern/app_cpu_thread.cpp
@@ -61,6 +61,8 @@ App_cpu_thread::bootstrap()
 
   Timer::enable();
 
 
   Timer::enable();
 

+  Per_cpu_data::run_late_ctors(cpu());
+

   cpu_lock.clear();
 
   printf("CPU[%u]: goes to idle loop\n", cpu());
   cpu_lock.clear();
 
   printf("CPU[%u]: goes to idle loop\n", cpu());

diff --git a/kernel/fiasco/src/kern/arm/ivt.S b/kernel/fiasco/src/kern/arm/ivt.S
index 7de812a66b1c7ef5ea337b3254a3e8706a5e08fb..8c4c0bb3944dfe2cc0a0df1c280a210a1a3a1423 100644 (file)
--- a/kernel/fiasco/src/kern/arm/ivt.S
+++ b/kernel/fiasco/src/kern/arm/ivt.S
@@ -215,7 +215,7 @@
        stmdb   sp!, {r0 - r12}
        CONTEXT_OF      r1, sp
        RESET_THREAD_CANCEL_AT r1       @ sets r0 to state 
        stmdb   sp!, {r0 - r12}
        CONTEXT_OF      r1, sp
        RESET_THREAD_CANCEL_AT r1       @ sets r0 to state 

-       tst     r0, #0x10000
+       tst     r0, #0x810000

        bne     alien_syscall
        ldr     r0, [sp, #RF(SVC_LR, 13*4)]     @ read exception PC from stack (km_lr)
        adr     r1, sys_call_table
        bne     alien_syscall
        ldr     r0, [sp, #RF(SVC_LR, 13*4)]     @ read exception PC from stack (km_lr)
        adr     r1, sys_call_table

diff --git a/kernel/fiasco/src/kern/context-vcpu.cpp b/kernel/fiasco/src/kern/context-vcpu.cpp
index c322bc9f31da59cb9a3cead6f35a223ebf13cd77..d7fc367de1248daba603dba1ddc1d5fedeeca3e5 100644 (file)
--- a/kernel/fiasco/src/kern/context-vcpu.cpp
+++ b/kernel/fiasco/src/kern/context-vcpu.cpp
@@ -67,9 +67,7 @@ Context::vcpu_enter_kernel_mode()
       if (state() & Thread_vcpu_user_mode)
        {
          vcpu_state()->_sp = vcpu_state()->_entry_sp;
       if (state() & Thread_vcpu_user_mode)
        {
          vcpu_state()->_sp = vcpu_state()->_entry_sp;

-         state_del_dirty(  Thread_vcpu_user_mode
-                          | Thread_vcpu_fpu_disabled
-                          | Thread_alien);
+         state_del_dirty(Thread_vcpu_user_mode | Thread_vcpu_fpu_disabled);

 
          if (current() == this)
            {
 
          if (current() == this)
            {

diff --git a/kernel/fiasco/src/kern/context.cpp b/kernel/fiasco/src/kern/context.cpp
index edffc28c77fa4d9224f33e84776306147db443e6..0983e9b4a6b7f540d255dc864587c289a293aec0 100644 (file)
--- a/kernel/fiasco/src/kern/context.cpp
+++ b/kernel/fiasco/src/kern/context.cpp
@@ -1943,7 +1943,7 @@ Context::handle_global_requests()
 
 PUBLIC
 bool
 
 PUBLIC
 bool

-Context::enqueue_drq(Drq *rq, Drq::Exec_mode exec)
+Context::enqueue_drq(Drq *rq, Drq::Exec_mode /*exec*/)

 {
   assert_kdb (cpu_lock.test());
   // printf("CPU[%2u:%p]: Context::enqueue_request(this=%p, src=%p, func=%p, arg=%p)\n", current_cpu(), current(), this, src, func,arg);
 {
   assert_kdb (cpu_lock.test());
   // printf("CPU[%2u:%p]: Context::enqueue_request(this=%p, src=%p, func=%p, arg=%p)\n", current_cpu(), current(), this, src, func,arg);

diff --git a/kernel/fiasco/src/kern/factory.cpp b/kernel/fiasco/src/kern/factory.cpp
index e75fa2cbc82149b50d8470c32975de7839068dd3..92c1469acd9c02ae8256427a393cb1c05db63c6a 100644 (file)
--- a/kernel/fiasco/src/kern/factory.cpp
+++ b/kernel/fiasco/src/kern/factory.cpp
@@ -280,7 +280,7 @@ Factory::kinvoke(L4_obj_ref ref, Mword rights, Syscall_frame *f,
 
 
 //----------------------------------------------------------------------------
 
 
 //----------------------------------------------------------------------------

-IMPLEMENTATION [svm]:
+IMPLEMENTATION [svm || vmx]:

 
 #include "vm_factory.h"
 
 
 #include "vm_factory.h"
 


@@ -314,7 +314,7 @@ Factory::new_vm(Utcb const *)
 }
 
 //----------------------------------------------------------------------------
 }
 
 //----------------------------------------------------------------------------

-IMPLEMENTATION [!svm && !tz]:
+IMPLEMENTATION [!svm && !tz && !vmx]:

 
 PRIVATE inline NOEXPORT
 Kobject_iface *
 
 PRIVATE inline NOEXPORT
 Kobject_iface *

diff --git a/kernel/fiasco/src/kern/ia32/32/entry-native.S b/kernel/fiasco/src/kern/ia32/32/entry-native.S
index be9694f6fd6505b60e54c5de41be8bed4a8725cc..69b85204a1dbe96ab2613b026c2d06be67f69ae2 100644 (file)
--- a/kernel/fiasco/src/kern/ia32/32/entry-native.S
+++ b/kernel/fiasco/src/kern/ia32/32/entry-native.S
@@ -199,7 +199,7 @@ entry_sys_fast_ipc_log:
        pushl   %ecx
 
        ESP_TO_TCB_AT %ebx
        pushl   %ecx
 
        ESP_TO_TCB_AT %ebx

-       testl   $Thread_alien, OFS__THREAD__STATE (%ebx)
+       testl   $Thread_alien_or_vcpu_user, OFS__THREAD__STATE (%ebx)

        jnz     alien_sys_fast_ipc_log
        RESET_THREAD_CANCEL_AT %ebx
        call    *syscall_table
        jnz     alien_sys_fast_ipc_log
        RESET_THREAD_CANCEL_AT %ebx
        call    *syscall_table


@@ -253,7 +253,7 @@ entry_sys_fast_ipc_c:
        pushl   %edx
        pushl   %ecx                            /* save ecx */
        ESP_TO_TCB_AT %ebx
        pushl   %edx
        pushl   %ecx                            /* save ecx */
        ESP_TO_TCB_AT %ebx

-       testl   $Thread_alien, OFS__THREAD__STATE (%ebx)
+       testl   $Thread_alien_or_vcpu_user, OFS__THREAD__STATE (%ebx)

        jnz     alien_sys_fast_ipc_c
        RESET_THREAD_CANCEL_AT %ebx
        call    ipc_short_cut_wrapper
        jnz     alien_sys_fast_ipc_c
        RESET_THREAD_CANCEL_AT %ebx
        call    ipc_short_cut_wrapper

diff --git a/kernel/fiasco/src/kern/ia32/32/entry.S b/kernel/fiasco/src/kern/ia32/32/entry.S
index 7de397f9260c2fcd1ce6f4979b1d57efa2ae544e..018dbf90d80f377a17902d52fae4087656bde2a5 100644 (file)
--- a/kernel/fiasco/src/kern/ia32/32/entry.S
+++ b/kernel/fiasco/src/kern/ia32/32/entry.S
@@ -492,7 +492,7 @@ entry_sys_ipc_c:
        pushl   %eax
        SAVE_STATE
        ESP_TO_TCB_AT %ebx
        pushl   %eax
        SAVE_STATE
        ESP_TO_TCB_AT %ebx

-       testl   $Thread_alien, OFS__THREAD__STATE (%ebx)
+       testl   $Thread_alien_or_vcpu_user, OFS__THREAD__STATE (%ebx)

        jnz     alien_sys_ipc_c
        RESET_THREAD_CANCEL_AT %ebx
        call    sys_ipc_wrapper //ipc_short_cut_wrapper
        jnz     alien_sys_ipc_c
        RESET_THREAD_CANCEL_AT %ebx
        call    sys_ipc_wrapper //ipc_short_cut_wrapper


@@ -514,7 +514,7 @@ entry_sys_ipc_log:
        pushl   %eax
        SAVE_STATE
        ESP_TO_TCB_AT %ebx
        pushl   %eax
        SAVE_STATE
        ESP_TO_TCB_AT %ebx

-       testl   $Thread_alien, OFS__THREAD__STATE (%ebx)
+       testl   $Thread_alien_or_vcpu_user, OFS__THREAD__STATE (%ebx)

        jnz     alien_sys_ipc_log
        RESET_THREAD_CANCEL_AT %ebx
        call    *syscall_table
        jnz     alien_sys_ipc_log
        RESET_THREAD_CANCEL_AT %ebx
        call    *syscall_table


@@ -550,7 +550,7 @@ all_syscalls:
        SAVE_STATE                                              ;\
        cld
        ESP_TO_TCB_AT %ebx
        SAVE_STATE                                              ;\
        cld
        ESP_TO_TCB_AT %ebx

-       testl   $Thread_alien, OFS__THREAD__STATE (%ebx)
+       testl   $Thread_alien_or_vcpu_user, OFS__THREAD__STATE (%ebx)

        jnz     alien_sys_call
        RESET_THREAD_CANCEL_AT %ebx
        call    *(%eax)                 /* interrupts enabled in wrappers */
        jnz     alien_sys_call
        RESET_THREAD_CANCEL_AT %ebx
        call    *(%eax)                 /* interrupts enabled in wrappers */

diff --git a/kernel/fiasco/src/kern/ia32/32/vm_vmx_asm.S b/kernel/fiasco/src/kern/ia32/32/vm_vmx_asm.S
new file mode 100644 (file)
index 0000000..1fd9f9c
--- /dev/null
+++ b/kernel/fiasco/src/kern/ia32/32/vm_vmx_asm.S
@@ -0,0 +1,76 @@
+/**
+ * Function resume_vm_vmx, arguments:
+ *  - eax: Pointer to registers (layout specific...)
+ */
+       .p2align(4)
+       .globl resume_vm_vmx
+       .globl vm_vmx_exit_vec
+resume_vm_vmx:
+       // save callee saved regs
+       push    %edi
+       push    %esi
+       push    %ebx
+       push    %ebp
+       push    %ds
+       push    %es
+       push    %gs
+       push    %fs
+
+       push    %eax            // store pointer to register struct
+       mov     $0x6c14, %eax   // save esp in vmcs
+       vmwrite %esp, %eax
+       mov     (%esp), %esp
+
+       // load guest GPs
+       pop     %eax
+       pop     %edx
+       pop     %ecx
+       pop     %ebx
+       pop     %ebp
+       pop     %esi
+       pop     %edi
+
+       vmresume
+       jnz     1f
+       vmlaunch
+1: // error path
+       mov     $0x6c14, %eax
+       vmread  %eax, %esp
+       pushf
+       pop     %eax
+       add     $20, %esp      // pushed regs pointer and gs+fs+ds+es
+       pop     %ebp
+       pop     %ebx
+       pop     %esi
+       pop     %edi
+       ret
+
+vm_vmx_exit_vec:
+       push    %eax
+       mov     4(%esp), %eax   // get previously saved register struct pointer
+
+       // eax is saved below
+       mov     %edx, 4(%eax)   // save guest GP registers
+       mov     %ecx, 8(%eax)
+       mov     %ebx, 12(%eax)
+       mov     %ebp, 16(%eax)
+       mov     %esi, 20(%eax)
+       mov     %edi, 24(%eax)
+
+       pop     %ecx            // guest EAX to ECX
+       mov     %ecx, 0(%eax)
+
+       add     $4, %esp        // adjust stack after regs pointer push on stack
+       
+       // restore callee saved registers
+       pop     %fs
+       pop     %gs
+       pop     %es
+       pop     %ds
+       pop     %ebp
+       pop     %ebx
+       pop     %esi
+       pop     %edi
+
+       xor     %eax, %eax
+       ret

diff --git a/kernel/fiasco/src/kern/ia32/64/vm_vmx_asm.S b/kernel/fiasco/src/kern/ia32/64/vm_vmx_asm.S
new file mode 100644 (file)
index 0000000..69ffed0
--- /dev/null
+++ b/kernel/fiasco/src/kern/ia32/64/vm_vmx_asm.S
@@ -0,0 +1,96 @@
+/**
+ * Function resume_vm_vmx, arguments:
+ *  - rdi: Pointer to registers (layout specific...)
+ */
+       .p2align(4)
+       .globl resume_vm_vmx
+       .globl vm_vmx_exit_vec
+resume_vm_vmx:
+       // save callee saved regs
+       push    %rbx
+       push    %r12
+       push    %r13
+       push    %r14
+       push    %r15
+       push    %rbp
+       push    %gs
+       push    %fs
+
+       push    %rdi               // store pointer to register struct
+       mov     $0x6c14, %eax      // save rsp in vmcs
+       vmwrite %rsp, %rax
+       mov     (%rsp), %rsp
+
+       // load guest GP registers
+       pop     %rax
+       pop     %rsi
+       pop     %rdx
+       pop     %rcx
+       pop     %rdi
+       pop     %r8
+       pop     %r9
+       pop     %rbx
+       pop     %rbp
+       pop     %r10
+       pop     %r11
+       pop     %r12
+       pop     %r13
+       pop     %r14
+       pop     %r15
+
+       vmresume
+       jnz 1f
+       vmlaunch
+1:     // error path
+       mov     $0x6c14, %eax
+       vmread  %rax, %rsp
+       pushf
+       pop     %rax
+       add     $24, %rsp        // pushed regs pointer and gs+fs
+       pop     %rbp
+       pop     %r15
+       pop     %r14
+       pop     %r13
+       pop     %r12
+       pop     %rbx
+       ret
+
+vm_vmx_exit_vec:
+       push    %rdi
+       mov     8(%rsp), %rdi     // get previously saved register struct pointer
+
+       // save guest GP registers
+       mov     %rax,   0(%rdi)
+       mov     %rsi,   8(%rdi)
+       mov     %rdx,  16(%rdi)
+       mov     %rcx,  24(%rdi)
+       // rdi is saved below
+       mov     %r8,   40(%rdi)
+       mov     %r9,   48(%rdi)
+       mov     %rbx,  56(%rdi)
+       mov     %rbp,  64(%rdi)
+       mov     %r10,  72(%rdi)
+       mov     %r11,  80(%rdi)
+       mov     %r12,  88(%rdi)
+       mov     %r13,  96(%rdi)
+       mov     %r14, 104(%rdi)
+       mov     %r15, 112(%rdi)
+
+       pop     %rax               // pop previously pushed guest rdi
+       mov     %rax,  32(%rdi)
+
+       add     $8, %rsp           // adjust stack after regs pointer push on stack
+
+        // restore callee saved registers
+       pop     %fs
+       pop     %gs
+       pop     %rbp
+       pop     %r15
+       pop     %r14
+       pop     %r13
+       pop     %r12
+       pop     %rbx
+
+       xor     %rax, %rax
+       ret
+

diff --git a/kernel/fiasco/src/kern/ia32/asm.h b/kernel/fiasco/src/kern/ia32/asm.h
index a939d6585ebf870c0dd1c9edaf1c6e8a74d50222..84a1105feb0c6356611a8046c315658d95307129 100644 (file)
--- a/kernel/fiasco/src/kern/ia32/asm.h
+++ b/kernel/fiasco/src/kern/ia32/asm.h
@@ -41,10 +41,10 @@
        .previous
 1:
 
        .previous
 1:
 

-       // check for the right thread state 
+       // check for the right thread state

        // (cancel and fpu_owner might also be set)
        movl    OFS__THREAD__STATE(%ebx), %edx
        // (cancel and fpu_owner might also be set)
        movl    OFS__THREAD__STATE(%ebx), %edx

-       andl    $~(Thread_cancel | Thread_fpu_owner | Thread_alien | Thread_dis_alien), %edx
+       andl    $~(Thread_cancel | Thread_fpu_owner | Thread_alien_or_vcpu_user | Thread_dis_alien), %edx

        cmpl    $(Thread_ready), %edx
        jne     1f
        .text   1
        cmpl    $(Thread_ready), %edx
        jne     1f
        .text   1

diff --git a/kernel/fiasco/src/kern/ia32/cpu-ia32.cpp b/kernel/fiasco/src/kern/ia32/cpu-ia32.cpp
index 07d468d053bd9c95799cdd873eb03439bb030b37..b9856674f4665d95b4abe9a41731dc18f1201a3d 100644 (file)
--- a/kernel/fiasco/src/kern/ia32/cpu-ia32.cpp
+++ b/kernel/fiasco/src/kern/ia32/cpu-ia32.cpp
@@ -1520,10 +1520,10 @@ Cpu::init()
 
   // reset time stamp counter (better for debugging)
   if ((features() & FEAT_TSC) && can_wrmsr())
 
   // reset time stamp counter (better for debugging)
   if ((features() & FEAT_TSC) && can_wrmsr())

-    wrmsr(0, 0, 0x10);
+    wrmsr(0, 0, MSR_TSC);

 
   if ((features() & FEAT_PAT) && can_wrmsr())
 
   if ((features() & FEAT_PAT) && can_wrmsr())

-    wrmsr(0x00010406, 0x00070406, 0x277);
+    wrmsr(0x00010406, 0x00070406, MSR_PAT);

 
   print_errata();
 }
 
   print_errata();
 }

diff --git a/kernel/fiasco/src/kern/ia32/shortcut.h b/kernel/fiasco/src/kern/ia32/shortcut.h
index a66e825dce4c092a578e89112ebae90a0f7cb958..4eaff71ad315e7d86cb0e63f1ee4cab8a7a796f5 100644 (file)
--- a/kernel/fiasco/src/kern/ia32/shortcut.h
+++ b/kernel/fiasco/src/kern/ia32/shortcut.h
@@ -16,7 +16,7 @@
 #define Thread_delayed_deadline                0x2000
 #define Thread_delayed_ipc             0x4000
 #define Thread_fpu_owner               0x8000
 #define Thread_delayed_deadline                0x2000
 #define Thread_delayed_ipc             0x4000
 #define Thread_fpu_owner               0x8000

-#define Thread_alien                   0x10000
+#define Thread_alien_or_vcpu_user      0x810000

 #define Thread_dis_alien               0x20000
 #define Thread_transfer_in_progress     0x80000
 
 #define Thread_dis_alien               0x20000
 #define Thread_transfer_in_progress     0x80000
 

diff --git a/kernel/fiasco/src/kern/ia32/vm_factory-ia32.cpp b/kernel/fiasco/src/kern/ia32/vm_factory-ia32.cpp
index 7e8a57f681444d6ebecf0b88922a76da1c87dfa0..8bbaa6dcc8caf85e91c1c29f499cec87eaf3ccfe 100644 (file)
--- a/kernel/fiasco/src/kern/ia32/vm_factory-ia32.cpp
+++ b/kernel/fiasco/src/kern/ia32/vm_factory-ia32.cpp
@@ -1,8 +1,10 @@
-IMPLEMENTATION [svm]:
+IMPLEMENTATION [vmx && svm]:

 
 #include "ram_quota.h"
 #include "svm.h"
 #include "vm_svm.h"
 
 #include "ram_quota.h"
 #include "svm.h"
 #include "vm_svm.h"

+#include "vmx.h"
+#include "vm_vmx.h"

 
 PRIVATE static inline
 template< typename VM >
 
 PRIVATE static inline
 template< typename VM >


@@ -27,11 +29,13 @@ Vm_factory::create(Ram_quota *quota)
 {
   if (Svm::cpus.cpu(current_cpu()).svm_enabled())
     return allocate<Vm_svm>(quota);
 {
   if (Svm::cpus.cpu(current_cpu()).svm_enabled())
     return allocate<Vm_svm>(quota);

+  if (Vmx::cpus.cpu(current_cpu()).vmx_enabled())
+    return allocate<Vm_vmx>(quota);

 
   return 0;
 }
 
 
   return 0;
 }
 

-IMPLEMENTATION [!svm]:
+IMPLEMENTATION [!(vmx && svm)]:

 
 IMPLEMENT
 Vm *
 
 IMPLEMENT
 Vm *

diff --git a/kernel/fiasco/src/kern/ia32/vm_svm.cpp b/kernel/fiasco/src/kern/ia32/vm_svm.cpp
index 0b96d0546ae35d0c4ffec220c59b9808bd7ae083..bba22bdfc8053c4b856ad9614905f260040de513 100644 (file)
--- a/kernel/fiasco/src/kern/ia32/vm_svm.cpp
+++ b/kernel/fiasco/src/kern/ia32/vm_svm.cpp
@@ -395,7 +395,7 @@ Vm_svm::sys_vm_run(Syscall_frame *f, Utcb *utcb)
       return commit_result(-L4_err::EInval);
     }
 
       return commit_result(-L4_err::EInval);
     }
 

-  if (EXPECT_FALSE(tag.words() < 1 + Svm::Gpregs_words))
+  if (EXPECT_FALSE(tag.words() < 2 + Svm::Gpregs_words))

     {
       WARN("svm: Invalid message length\n");
       return commit_result(-L4_err::EInval);
     {
       WARN("svm: Invalid message length\n");
       return commit_result(-L4_err::EInval);


@@ -652,7 +652,7 @@ Vm_svm::sys_vm_run(Syscall_frame *f, Utcb *utcb)
     Cpu::set_cr4(cr4 & ~CR4_PGE);
 #endif
 
     Cpu::set_cr4(cr4 & ~CR4_PGE);
 #endif
 

-  resume_vm_svm(kernel_vmcb_pa, &utcb->values[1]);
+  resume_vm_svm(kernel_vmcb_pa, &utcb->values[2]);

 
 
 #if 0
 
 
 #if 0

diff --git a/kernel/fiasco/src/kern/ia32/vm_vmx.cpp b/kernel/fiasco/src/kern/ia32/vm_vmx.cpp
new file mode 100644 (file)
index 0000000..a0b594d
--- /dev/null
+++ b/kernel/fiasco/src/kern/ia32/vm_vmx.cpp
@@ -0,0 +1,575 @@
+INTERFACE [vmx]:
+
+#include "config.h"
+#include "per_cpu_data.h"
+#include "vm.h"
+#include "vmx.h"
+
+class Vmcs;
+
+class Vm_vmx : public Vm
+{
+private:
+  static unsigned long resume_vm_vmx(Mword *regs)
+    asm("resume_vm_vmx") __attribute__((__regparm__(3)));
+
+  enum
+  {
+    EFER_LME = 1 << 8,
+    EFER_LMA = 1 << 10,
+  };
+
+};
+
+//----------------------------------------------------------------------------
+IMPLEMENTATION [vmx]:
+
+#include "context.h"
+#include "mem_space.h"
+#include "fpu.h"
+#include "ref_ptr.h"
+#include "thread.h" // XXX: circular dep, move this out here!
+#include "thread_state.h" // XXX: circular dep, move this out here!
+#include "virt.h"
+#include "idt.h"
+
+
+PUBLIC
+Vm_vmx::Vm_vmx(Ram_quota *q)
+  : Vm(q)
+{}
+
+PUBLIC inline
+void *
+Vm_vmx::operator new (size_t size, void *p)
+{
+  assert (size == sizeof (Vm_vmx));
+  return p;
+}
+
+PUBLIC
+void
+Vm_vmx::operator delete (void *ptr)
+{
+  Vm_vmx *t = reinterpret_cast<Vm_vmx*>(ptr);
+  allocator<Vm_vmx>()->q_free(t->ram_quota(), ptr);
+}
+
+
+
+
+PRIVATE static inline
+void *
+Vm_vmx::field_offset(void *vmcs, unsigned field)
+{
+  return (void *)((char *)vmcs
+                          + ((field >> 13) * 4 + ((field >> 10) & 3) + 1) * 0x80);
+}
+
+PRIVATE static inline
+unsigned
+Vm_vmx::field_width(unsigned field)
+{
+  static const char widths[4] = { 2, 8, 4, sizeof(Mword) };
+  return widths[field >> 13];
+}
+
+
+PRIVATE inline
+template<typename T>
+Vmx_info::Flags<T>
+Vm_vmx::load(unsigned field, void *vmcs, Vmx_info::Bit_defs<T> const &m)
+{
+  T res = m.apply(read<T>(vmcs, field));
+  Vmx::vmwrite(field, res);
+  return Vmx_info::Flags<T>(res);
+}
+
+PRIVATE inline
+void
+Vm_vmx::load(unsigned field_first, unsigned field_last, void *vmcs)
+{
+  for (; field_first <= field_last; field_first += 2)
+    load(field_first, vmcs);
+}
+
+PRIVATE inline static
+template< typename T >
+T
+Vm_vmx::_internal_read(void *vmcs, unsigned field)
+{
+  vmcs = field_offset(vmcs, field);
+  return *((T *)vmcs + ((field >> 1) & 0xff));
+}
+
+PRIVATE inline static
+template< typename T >
+void
+Vm_vmx::_internal_write(void *vmcs, unsigned field, T value)
+{
+  vmcs = field_offset(vmcs, field);
+  *((T*)vmcs + ((field >> 1) & 0xff)) = value;
+}
+
+PRIVATE inline
+void
+Vm_vmx::load(unsigned field, void *vmcs)
+{
+  switch (field >> 13)
+    {
+    case 0: Vmx::vmwrite(field, _internal_read<Unsigned16>(vmcs, field)); break;
+    case 1: Vmx::vmwrite(field, _internal_read<Unsigned64>(vmcs, field)); break;
+    case 2: Vmx::vmwrite(field, _internal_read<Unsigned32>(vmcs, field)); break;
+    case 3: Vmx::vmwrite(field, _internal_read<Mword>(vmcs, field)); break;
+    }
+}
+
+PRIVATE inline
+void
+Vm_vmx::store(unsigned field, void *vmcs)
+{
+  switch (field >> 13)
+    {
+    case 0: _internal_write(vmcs, field, Vmx::vmread<Unsigned16>(field)); break;
+    case 1: _internal_write(vmcs, field, Vmx::vmread<Unsigned64>(field)); break;
+    case 2: _internal_write(vmcs, field, Vmx::vmread<Unsigned32>(field)); break;
+    case 3: _internal_write(vmcs, field, Vmx::vmread<Mword>(field)); break;
+    }
+}
+
+PRIVATE inline
+void
+Vm_vmx::store(unsigned field_first, unsigned field_last, void *vmcs)
+{
+  for (; field_first <= field_last; field_first += 2)
+    store(field_first, vmcs);
+}
+
+PRIVATE inline static
+template< typename T >
+void
+Vm_vmx::write(void *vmcs, unsigned field, T value)
+{
+  switch (field >> 13)
+    {
+    case 0: _internal_write(vmcs, field, (Unsigned16)value); break;
+    case 1: _internal_write(vmcs, field, (Unsigned64)value); break;
+    case 2: _internal_write(vmcs, field, (Unsigned32)value); break;
+    case 3: _internal_write(vmcs, field, (Mword)value); break;
+    }
+}
+
+PRIVATE inline static
+template< typename T >
+T
+Vm_vmx::read(void *vmcs, unsigned field)
+{
+  switch (field >> 13)
+    {
+    case 0: return _internal_read<Unsigned16>(vmcs, field);
+    case 1: return _internal_read<Unsigned64>(vmcs, field);
+    case 2: return _internal_read<Unsigned32>(vmcs, field);
+    case 3: return _internal_read<Mword>(vmcs, field);
+    }
+  return 0;
+}
+
+
+PRIVATE
+void
+Vm_vmx::load_guest_state(unsigned cpu, void *src)
+{
+  Vmx &vmx = Vmx::cpus.cpu(cpu);
+
+  // read VM-entry controls, apply filter and keep for later
+  Vmx_info::Flags<Unsigned32> entry_ctls
+    = load<Unsigned32>(Vmx::F_entry_ctls, src, vmx.info.entry_ctls);
+
+  Vmx_info::Flags<Unsigned32> pinbased_ctls
+    = load<Unsigned32>(Vmx::F_pin_based_ctls, src, vmx.info.pinbased_ctls);
+
+  Vmx_info::Flags<Unsigned32> procbased_ctls
+    = load<Unsigned32>(Vmx::F_proc_based_ctls, src, vmx.info.procbased_ctls);
+
+  Vmx_info::Flags<Unsigned32> procbased_ctls_2;
+  if (procbased_ctls.test(Vmx::PRB1_enable_proc_based_ctls_2))
+    procbased_ctls_2 = load<Unsigned32>(Vmx::F_proc_based_ctls_2, src, vmx.info.procbased_ctls2);
+  else
+    procbased_ctls_2 = Vmx_info::Flags<Unsigned32>(0);
+
+  load<Unsigned32>(Vmx::F_exit_ctls, src, vmx.info.exit_ctls);
+
+  // write 16-bit fields
+  load(0x800, 0x80e, src);
+
+  // write 64-bit fields
+  load(0x2802, src);
+
+  // check if the following bits are allowed to be set in entry_ctls
+  if (entry_ctls.test(14)) // PAT load requested
+    load(0x2804, src);
+
+  if (entry_ctls.test(15)) // EFER load requested
+    load(0x2806, src);
+
+  if (entry_ctls.test(13)) // IA32_PERF_GLOBAL_CTRL load requested
+    load(0x2808, src);
+
+  // complete *beep*, this is Fiasco.OC internal state
+#if 0
+  if (vmx.has_ept())
+    load(0x280a, 0x2810, src);
+#endif
+
+  // write 32-bit fields
+  load(0x4800, 0x482a, src);
+
+  if (pinbased_ctls.test(6)) // activate vmx-preemption timer
+    load(0x482e, src);
+
+  // write natural-width fields
+  load<Mword>(0x6800, src, vmx.info.cr0_defs);
+
+  if (sizeof(long) > sizeof(int))
+    {
+      if (read<Mword>(src, 0x2806) & EFER_LME)
+        Vmx::vmwrite(0x6802, (Mword)mem_space()->phys_dir());
+      else
+       WARN("VMX: No, not possible\n");
+    }
+  else
+    {
+      // for 32bit we can just load the Vm pdbr
+      Vmx::vmwrite(0x6802, (Mword)mem_space()->phys_dir());
+    }
+
+  load<Mword>(0x6804, src, vmx.info.cr4_defs);
+  load(0x6806, 0x6826, src);
+
+  // VPID must be virtualized in Fiasco
+#if 0
+  if (procbased_ctls_2 & Vmx::PB2_enable_vpid)
+    load(Vmx::F_vpid, src);
+#endif
+
+  // currently io-bitmaps are unsupported
+  // currently msr-bitmaps are unsupported
+
+  // load(0x200C, src); for SMM virtualization
+  load(Vmx::F_tsc_offset, src);
+
+  // no virtual APIC yet, and has to be managed in kernel somehow
+#if 0
+  if (procbased_ctls.test(Vmx::PRB1_tpr_shadow))
+    load(0x2012, src);
+#endif
+
+  if (procbased_ctls_2.test(Vmx::PRB2_virtualize_apic))
+    load(Vmx::F_apic_access_addr, src);
+
+  // exception bit map and pf error-code stuff
+  load(0x4004, 0x4008, src);
+
+  // vm entry control stuff
+  Unsigned32 irq_info = read<Unsigned32>(src, Vmx::F_entry_int_info);
+  if (irq_info & (1UL << 31))
+    {
+      // do event injection
+
+      // load error code, if required
+      if (irq_info & (1UL << 11))
+       load(Vmx::F_entry_exc_error_code, src);
+
+      // types, that require an insn length have bit 10 set (type 4, 5, and 6)
+      if (irq_info & (1UL << 10))
+       load(Vmx::F_entry_insn_len, src);
+
+      Vmx::vmwrite(Vmx::F_entry_int_info, irq_info);
+    }
+
+  // hm, we have to check for sanitizing the cr0 and cr4 shadow stuff
+  load(0x6000, 0x6006, src);
+
+  // no cr3 target values supported
+}
+
+
+PRIVATE
+void
+Vm_vmx::store_guest_state(unsigned cpu, void *dest)
+{
+  // read 16-bit fields
+  store(0x800, 0x80e, dest);
+
+  // read 64-bit fields
+  store(0x2802, dest);
+
+  Vmx_info &vmx_info = Vmx::cpus.cpu(cpu).info;
+  Vmx_info::Flags<Unsigned32> exit_ctls
+    = Vmx_info::Flags<Unsigned32>(vmx_info.exit_ctls.apply(read<Unsigned32>(dest, Vmx::F_exit_ctls)));
+
+  if (exit_ctls.test(18)) store(Vmx::F_guest_pat, dest);
+  if (exit_ctls.test(20)) store(Vmx::F_guest_efer, dest);
+  if (exit_ctls.test(22)) store(Vmx::F_preempt_timer, dest);
+
+  // EPT and PAE handling missing
+#if 0
+  if (Vmx::cpus.cpu(cpu).has_ept())
+    store(0x280a, 0x2810, dest);
+#endif
+
+  // read 32-bit fields
+  store(0x4800, 0x4826, dest);
+
+  // sysenter msr is not saved here, because we trap all msr accesses right now
+#if 0
+  store(0x482a, dest);
+  store(0x6824, 0x6826, dest);
+#endif
+
+  // read natural-width fields
+  store(0x6800, dest);
+  // skip cr3
+  store(0x6804, 0x6822, dest);
+}
+
+#if 0
+PRIVATE
+void
+Vm_vmx::copy_execution_control_back(unsigned cpu, void *dest)
+{
+  Vmx &v = Vmx::cpus.cpu(cpu);
+  // read 16-bit fields
+  if (v.has_vpid())
+    store(0, dest);
+
+  // read 64-bit fields
+  store(0x2000, 0x2002, dest);
+  store(0x200c, dest);
+  store(0x2010, dest);
+
+  Unsigned64 msr = Vmx::cpus.cpu(cpu).info._procbased_ctls; // IA32_VMX_PROCBASED_CTLS
+  if (msr & (1ULL<<53))
+    store(0x2012, dest);
+
+  if (vmread<Unsigned32>(0x4002) & (1 << 31))
+    {
+      msr = Vmx::cpus.cpu(cpu).info._procbased_ctls2; // IA32_VMX_PROCBASED_CTLS2
+      if (msr & (1ULL << 32))
+       store(0x2014, dest);
+    }
+
+  if (v.has_ept())
+    store(0x201a, dest);
+
+  // read 32-bit fields
+  store(0x4000, 0x4004, dest);
+  store(0x401e, dest);
+
+  // read natural-width fields
+  store(0x6000, 0x600e, dest);
+}
+
+PRIVATE
+void
+Vm_vmx::copy_exit_control_back(unsigned ,void *dest)
+{
+  // read 64-bit fields
+  store(0x2006, 0x2008, dest);
+
+  // read 32-bit fields
+  store(0x400c, 0x4010, dest);
+}
+
+PRIVATE
+void
+Vm_vmx::copy_entry_control_back(unsigned, void *dest)
+{
+  // read 64-bit fields
+  store(0x200a, dest);
+
+  // read 32-bit fields
+  store(0x4012, 0x401a, dest);
+}
+#endif
+
+PRIVATE
+void
+Vm_vmx::store_exit_info(unsigned cpu, void *dest)
+{
+  (void)cpu;
+  // read 64-bit fields, HM EPT pf stuff
+#if 0
+  if (Vmx::cpus.cpu(cpu).has_ept())
+    store(0x2400, dest);
+#endif
+
+  // clear the valid bit in Vm-entry interruption information
+    {
+      Unsigned32 tmp = read<Unsigned32>(dest, Vmx::F_entry_int_info);
+      if (tmp & (1UL << 31))
+       write(dest, Vmx::F_entry_int_info, tmp & ~((Unsigned32)1 << 31));
+    }
+
+  // read 32-bit fields
+  store(0x4400, 0x440e, dest);
+
+  // read natural-width fields
+  store(0x6400, 0x640a, dest);
+}
+
+PRIVATE
+void
+Vm_vmx::dump(void *v, unsigned f, unsigned t)
+{
+  for (; f <= t; f += 2)
+    printf("%04x: VMCS: %16lx   V: %16lx\n",
+          f, Vmx::vmread<Mword>(f), read<Mword>(v, f));
+}
+
+PRIVATE
+void
+Vm_vmx::dump_state(void *v)
+{
+  dump(v, 0x0800, 0x080e);
+  dump(v, 0x0c00, 0x0c0c);
+  dump(v, 0x2000, 0x201a);
+  dump(v, 0x2800, 0x2810);
+  dump(v, 0x2c00, 0x2804);
+  dump(v, 0x4000, 0x4022);
+  dump(v, 0x4400, 0x4420);
+  dump(v, 0x4800, 0x482a);
+  dump(v, 0x6800, 0x6826);
+  dump(v, 0x6c00, 0x6c16);
+}
+
+PUBLIC
+L4_msg_tag
+Vm_vmx::sys_vm_run(Syscall_frame *f, Utcb *utcb)
+{
+  assert (cpu_lock.test());
+
+  /* these 4 must not use ldt entries */
+  assert (!(Cpu::get_cs() & (1 << 2)));
+  assert (!(Cpu::get_ss() & (1 << 2)));
+  assert (!(Cpu::get_ds() & (1 << 2)));
+  assert (!(Cpu::get_es() & (1 << 2)));
+
+  unsigned cpu = current_cpu();
+  Vmx &v = Vmx::cpus.cpu(cpu);
+
+  L4_msg_tag const &tag = f->tag();
+
+  if(!v.vmx_enabled())
+    {
+      WARN("VMX: not supported/enabled\n");
+      return commit_result(-L4_err::EInval);
+    }
+
+  if (EXPECT_FALSE(tag.words() < 1 + Vmx::Gpregs_words))
+    {
+      WARN("VMX: Invalid message length\n");
+      return commit_result(-L4_err::EInval);
+    }
+
+  L4_snd_item_iter vmcs_item(utcb, tag.words());
+
+  if (EXPECT_FALSE(!tag.items() || !vmcs_item.next()))
+    return commit_result(-L4_err::EInval);
+
+  L4_fpage vmcs_fpage(vmcs_item.get()->d);
+
+  if (EXPECT_FALSE(!vmcs_fpage.is_mempage()))
+    {
+      WARN("VMX: Fpage invalid\n");
+      return commit_error(utcb, L4_error::Overflow);
+    }
+
+  if (EXPECT_FALSE(vmcs_fpage.order() < 12))
+    return commit_result(-L4_err::EInval);
+
+
+  void *vmcs_s = (void *)(Virt_addr(vmcs_fpage.mem_address()).value());
+
+  Mem_space::Phys_addr phys_vmcs;
+  Mem_space::Size size;
+  bool resident;
+  unsigned int page_attribs;
+
+  Mem_space *const curr_mem_space = current()->space()->mem_space();
+  resident = curr_mem_space->v_lookup(Virt_addr(vmcs_s), &phys_vmcs, &size, &page_attribs);
+
+  if (EXPECT_FALSE(!resident))
+    {
+      WARN("VMX: VMCS invalid\n");
+      return commit_result(-L4_err::EInval);
+    }
+
+  // XXX:
+  // This generates a circular dep between thread<->task, this cries for a
+  // new abstraction...
+  if (!(current()->state() & Thread_fpu_owner))
+    {
+      if (EXPECT_FALSE(!current_thread()->switchin_fpu()))
+        {
+          WARN("VMX: switchin_fpu failed\n");
+          return commit_result(-L4_err::EInval);
+        }
+    }
+
+#if 0
+  if (EXPECT_FALSE(read<Unsigned32>(vmcs_s, 0x201a) != 0)) // EPT POINTER
+    {
+      WARN("VMX: no nested paging available\n");
+      return commit_result(-L4_err::EInval);
+    }
+#endif
+
+  // increment our refcount, and drop it at the end automatically
+  Ref_ptr<Vm_vmx> pin_myself(this);
+
+  // set volatile host state
+  Vmx::vmwrite<Mword>(Vmx::F_host_cr3, Cpu::get_pdbr()); // host_area.cr3
+
+  load_guest_state(cpu, vmcs_s);
+
+  Unsigned16 ldt = Cpu::get_ldt();
+
+  // set guest CR2
+  asm volatile("mov %0, %%cr2" : : "r" (read<Mword>(vmcs_s, Vmx::F_guest_cr2)));
+
+  unsigned long ret = resume_vm_vmx(&utcb->values[1]);
+  if (EXPECT_FALSE(ret & 0x40))
+    return commit_result(-L4_err::EInval);
+
+  // save guest cr2
+    {
+      Mword cpu_cr2;
+      asm volatile("mov %%cr2, %0" : "=r" (cpu_cr2));
+      write(vmcs_s, Vmx::F_guest_cr2, cpu_cr2);
+    }
+
+  Cpu::set_ldt(ldt);
+
+  // reload TSS, we use I/O bitmaps
+  // ... do this lazy ...
+  {
+    // clear busy flag
+    Gdt_entry *e = &(*Cpu::cpus.cpu(cpu).get_gdt())[Gdt::gdt_tss / 8];
+    e->access &= ~(1 << 1);
+    asm volatile("" : : "m" (*e));
+    Cpu::set_tr(Gdt::gdt_tss);
+  }
+
+  store_guest_state(cpu, vmcs_s);
+  store_exit_info(cpu, vmcs_s);
+
+  return commit_result(L4_error::None);
+}
+
+PUBLIC
+void
+Vm_vmx::invoke(L4_obj_ref obj, Mword rights, Syscall_frame *f, Utcb *utcb)
+{
+  vm_invoke<Vm_vmx>(obj, rights, f, utcb);
+}

diff --git a/kernel/fiasco/src/kern/ia32/vmx.cpp b/kernel/fiasco/src/kern/ia32/vmx.cpp
new file mode 100644 (file)
index 0000000..c815447
--- /dev/null
+++ b/kernel/fiasco/src/kern/ia32/vmx.cpp
@@ -0,0 +1,559 @@
+INTERFACE [vmx]:
+
+#include "per_cpu_data.h"
+#include <cstdio>
+
+class Vmx_info
+{
+public:
+  static bool nested_paging() { return false; }
+
+  template<typename T>
+  class Bit_defs
+  {
+  protected:
+    T _or;
+    T _and;
+
+  public:
+    Bit_defs() {}
+    Bit_defs(T _or, T _and) : _or(_or), _and(_and) {}
+#if 0
+    template<typename T2>
+    explicit Bit_defs(Bit_defs<T2> const &o)
+    : _or(o.must_be_one()), _and(o.may_be_one()) {}
+#endif
+    T must_be_one() const { return _or; }
+    T may_be_one() const { return _and; }
+
+  private:
+    void enforce_bits(T m, bool value = true)
+    {
+      if (value)
+       _or |= m;
+      else
+       _and &= ~m;
+    }
+
+    bool allowed_bits(T m, bool value = true) const
+    {
+      if (value)
+       return _and & m;
+      else
+       return !(_or & m);
+    }
+
+  public:
+    void enforce(unsigned char bit, bool value = true)
+    { enforce_bits((T)1 << (T)bit, value); }
+
+    bool allowed(unsigned char bit, bool value = true) const
+    { return allowed_bits((T)1 << (T)bit, value); }
+
+    T apply(T v) const { return (v | _or) & _and; }
+
+    void print(char const *name) const
+    {
+      if (sizeof(T) <= 4)
+       printf("%20s = %8x %8x\n", name, (unsigned)_and, (unsigned)_or);
+      else if (sizeof(T) <= 8)
+       printf("%20s = %16llx %16llx\n", name, (unsigned long long)_and, (unsigned long long)_or);
+    }
+  };
+
+  class Bit_defs_32 : public Bit_defs<Unsigned32>
+  {
+  public:
+    Bit_defs_32() {}
+    Bit_defs_32(Unsigned64 v) : Bit_defs<Unsigned32>(v, v >> 32) {}
+  };
+
+  typedef Bit_defs<Unsigned64> Bit_defs_64;
+
+  template<typename T>
+  class Flags
+  {
+  public:
+    Flags() {}
+    explicit Flags(T v) : _f(v) {}
+
+    T test(unsigned char bit) const { return _f & ((T)1 << (T)bit); }
+  private:
+    T _f;
+  };
+
+  Unsigned64 basic;
+
+  Bit_defs_32 pinbased_ctls;
+  Bit_defs_32 procbased_ctls;
+
+  Bit_defs_32 exit_ctls;
+  Bit_defs_32 entry_ctls;
+  Unsigned64 misc;
+
+  Bit_defs<Mword> cr0_defs;
+  Bit_defs<Mword> cr4_defs;
+  Bit_defs_32 procbased_ctls2;
+
+  Unsigned64 ept_vpid_cap;
+  Unsigned64 true_pinbased_ctls;
+  Unsigned64 true_procbased_ctls;
+  Unsigned64 true_exit_ctls;
+  Unsigned64 true_entry_ctls;
+};
+
+INTERFACE:
+
+class Vmx
+{
+public:
+  enum Vmcs_fields
+  {
+    F_vpid               = 0x0,
+
+    F_host_es_selector   = 0x0c00,
+    F_host_cs_selector   = 0x0c02,
+    F_host_ss_selector   = 0x0c04,
+    F_host_ds_selector   = 0x0c06,
+    F_host_fs_selector   = 0x0c08,
+    F_host_gs_selector   = 0x0c0a,
+    F_host_tr_selector   = 0x0c0c,
+
+    F_tsc_offset         = 0x2010,
+    F_apic_access_addr   = 0x2014,
+
+    F_guest_pat          = 0x2804,
+    F_guest_efer         = 0x2806,
+
+    F_host_ia32_pat              = 0x2c00,
+    F_host_ia32_efer             = 0x2c02,
+    F_host_ia32_perf_global_ctrl = 0x2c04,
+
+
+    F_pin_based_ctls     = 0x4000,
+    F_proc_based_ctls    = 0x4002,
+
+    F_cr3_target_cnt     = 0x400a,
+    F_exit_ctls          = 0x400c,
+    F_exit_msr_store_cnt = 0x400e,
+    F_exit_msr_load_cnt  = 0x4010,
+    F_entry_ctls         = 0x4012,
+    F_entry_msr_load_cnt = 0x4014,
+    F_entry_int_info     = 0x4016,
+    F_entry_exc_error_code = 0x4018,
+    F_entry_insn_len     = 0x401a,
+    F_proc_based_ctls_2  = 0x401e,
+
+    F_preempt_timer      = 0x482e,
+
+    F_host_sysenter_cs   = 0x4c00,
+
+    F_guest_cr2          = 0x6830,
+
+    F_host_cr0           = 0x6c00,
+    F_host_cr3           = 0x6c02,
+    F_host_cr4           = 0x6c04,
+    F_host_fs_base       = 0x6c06,
+    F_host_gs_base       = 0x6c08,
+    F_host_tr_base       = 0x6c0a,
+    F_host_gdtr_base     = 0x6c0c,
+    F_host_idtr_base     = 0x6c0e,
+    F_host_sysenter_esp  = 0x6c10,
+    F_host_sysenter_eip  = 0x6c12,
+    F_host_rip           = 0x6c16,
+  };
+
+  enum Pin_based_ctls
+  {
+    PIB_ext_int_exit = 0,
+    PIB_nmi_exit     = 3,
+  };
+
+  enum Primary_proc_based_ctls
+  {
+    PRB1_tpr_shadow               = 21,
+    PRB1_unconditional_io_exit    = 24,
+    PRB1_use_io_bitmaps           = 25,
+    PRB1_use_msr_bitmaps          = 28,
+    PRB1_enable_proc_based_ctls_2 = 31,
+  };
+
+  enum Secondary_proc_based_ctls
+  {
+    PRB2_virtualize_apic = 0,
+    PRB2_enable_ept      = 1,
+    PRB2_enable_vpid     = 5,
+  };
+
+};
+
+INTERFACE [vmx]:
+
+#include "virt.h"
+#include "cpu_lock.h"
+
+class Vmx_info;
+
+EXTENSION class Vmx
+{
+public:
+  static Per_cpu<Vmx> cpus;
+  Vmx_info info;
+private:
+  void *_vmxon;
+  bool _vmx_enabled;
+  bool _has_vpid;
+  Unsigned64 _vmxon_base_pa;
+  void *_kernel_vmcs;
+  Unsigned64 _kernel_vmcs_pa;
+};
+
+class Vmx_info_msr
+{
+private:
+  Unsigned64 _data;
+};
+
+//-----------------------------------------------------------------------------
+INTERFACE [vmx && ia32]:
+
+EXTENSION class Vmx
+{
+public:
+  enum { Gpregs_words = 11 };
+};
+
+//-----------------------------------------------------------------------------
+INTERFACE [vmx && amd64]:
+
+EXTENSION class Vmx
+{
+public:
+  enum { Gpregs_words = 19 };
+};
+
+
+// -----------------------------------------------------------------------
+IMPLEMENTATION[vmx]:
+
+#include "cpu.h"
+#include "kmem.h"
+#include "l4_types.h"
+#include <cstring>
+#include "idt.h"
+
+Per_cpu<Vmx> DEFINE_PER_CPU_LATE Vmx::cpus(true);
+
+PUBLIC
+void
+Vmx_info::init()
+{
+  basic = Cpu::rdmsr(0x480);
+  pinbased_ctls = Cpu::rdmsr(0x481);
+  procbased_ctls = Cpu::rdmsr(0x482);
+  exit_ctls = Cpu::rdmsr(0x483);
+  entry_ctls = Cpu::rdmsr(0x484);
+  misc = Cpu::rdmsr(0x485);
+
+  cr0_defs = Bit_defs<Mword>(Cpu::rdmsr(0x486), Cpu::rdmsr(0x487));
+  cr4_defs = Bit_defs<Mword>(Cpu::rdmsr(0x488), Cpu::rdmsr(0x489));
+
+  if (basic & (1ULL << 55))
+    {
+      true_pinbased_ctls = Cpu::rdmsr(0x48d);
+      true_procbased_ctls = Cpu::rdmsr(0x48e);
+      true_exit_ctls = Cpu::rdmsr(0x48f);
+      true_entry_ctls = Cpu::rdmsr(0x490);
+    }
+
+  if (0)
+    dump("as read from hardware");
+
+  pinbased_ctls.enforce(Vmx::PIB_ext_int_exit);
+  pinbased_ctls.enforce(Vmx::PIB_nmi_exit);
+
+
+  // currently we IO-passthrough is missing, disable I/O bitmaps and enforce
+  // unconditional io exiting
+  procbased_ctls.enforce(Vmx::PRB1_use_io_bitmaps, false);
+  procbased_ctls.enforce(Vmx::PRB1_unconditional_io_exit);
+
+  // virtual APIC not yet supported
+  procbased_ctls.enforce(Vmx::PRB1_tpr_shadow, false);
+
+  if (procbased_ctls.allowed(31))
+    {
+      procbased_ctls2 = Cpu::rdmsr(0x48b);
+      if (procbased_ctls2.allowed(1))
+       ept_vpid_cap = Cpu::rdmsr(0x48c);
+
+      // we disable VPID so far, need to handle virtualize it in Fiasco,
+      // as done for AMDs ASIDs
+      procbased_ctls2.enforce(Vmx::PRB2_enable_vpid, false);
+
+      // no EPT support yet
+      procbased_ctls2.enforce(Vmx::PRB2_enable_ept, false);
+    }
+  else
+    procbased_ctls2 = 0;
+
+  // never automatically ack interrupts on exit
+  exit_ctls.enforce(15, false);
+
+  // host-state is 64bit or not
+  exit_ctls.enforce(9, sizeof(long) > sizeof(int));
+
+  if (!nested_paging()) // needs to be per VM
+    {
+      // always enable paging
+      cr0_defs.enforce(31);
+      // always PE
+      cr0_defs.enforce(0);
+      cr4_defs.enforce(4); // PSE
+
+      // enforce PAE on 64bit, and disallow it on 32bit
+      cr4_defs.enforce(5, sizeof(long) > sizeof(int));
+    }
+
+  if (0)
+    dump("as modified");
+}
+
+PUBLIC
+void
+Vmx_info::dump(const char *tag) const
+{
+  printf("VMX MSRs %s:\n", tag);
+  printf("basic                = %16llx\n", basic);
+  pinbased_ctls.print("pinbased_ctls");
+  procbased_ctls.print("procbased_ctls");
+  exit_ctls.print("exit_ctls");
+  entry_ctls.print("entry_ctls");
+  printf("misc                 = %16llx\n", misc);
+  cr0_defs.print("cr0_fixed");
+  cr4_defs.print("cr4_fixed");
+  procbased_ctls2.print("procbased_ctls2");
+  printf("ept_vpid_cap         = %16llx\n", ept_vpid_cap);
+  printf("true_pinbased_ctls   = %16llx\n", true_pinbased_ctls);
+  printf("true_procbased_ctls  = %16llx\n", true_procbased_ctls);
+  printf("true_exit_ctls       = %16llx\n", true_exit_ctls);
+  printf("true_entry_ctls      = %16llx\n", true_entry_ctls);
+}
+
+PRIVATE static inline
+Mword
+Vmx::vmread_insn(Mword field)
+{
+  Mword val;
+  asm volatile("vmread %1, %0" : "=r" (val) : "r" (field));
+  return val;
+}
+
+PUBLIC static inline NEEDS[Vmx::vmread_insn]
+template< typename T >
+T
+Vmx::vmread(Mword field)
+{
+  if (sizeof(T) <= sizeof(Mword))
+    return vmread_insn(field);
+
+  return vmread_insn(field) | ((Unsigned64)vmread_insn(field + 1) << 32);
+}
+
+PUBLIC static inline
+template< typename T >
+void
+Vmx::vmwrite(Mword field, T value)
+{
+  Mword err;
+  asm volatile("vmwrite %1, %2; pushf; pop %0" : "=r" (err) : "r" ((Mword)value), "r" (field));
+  if (EXPECT_FALSE(err & 0x41))
+    printf("FAILED vmwrite(%lx): field=%04lx with value %llx\n", err, field, (Unsigned64)value);
+  if (sizeof(T) > sizeof(Mword))
+    asm volatile("vmwrite %0, %1" : : "r" ((Unsigned64)value >> 32), "r" (field + 1));
+}
+
+PUBLIC
+Vmx::Vmx(unsigned cpu)
+  : _vmx_enabled(false), _has_vpid(false)
+{
+  Cpu &c = Cpu::cpus.cpu(cpu);
+  if (!c.vmx())
+    {
+      printf("VMX: Not supported\n");
+      return;
+    }
+
+  printf("VMX: Enabling\n");
+
+  // check whether vmx is enabled by BIOS
+  Unsigned64 feature = 0;
+  feature = Cpu::rdmsr(0x3a);
+
+  // vmxon outside SMX allowed?
+  if (!(feature & 0x4))
+    {
+      printf("VMX: CPU has VMX support but it is disabled\n");
+      return;
+    }
+
+  // check whether lock bit is set otherwise vmxon
+  // will cause a general-protection exception
+  if (!(feature & 0x1))
+    {
+      printf("VMX: Cannot enable VMX, lock bit not set\n");
+      return;
+    }
+
+  info.init();
+
+  // check for EPT support
+  if (info.procbased_ctls2.allowed(1))
+    printf("VMX:  EPT supported\n");
+  else
+    printf("VMX:  No EPT available\n");
+
+  // check for vpid support
+  if (info.procbased_ctls2.allowed(5))
+    _has_vpid = true;
+
+  c.set_cr4(c.get_cr4() | (1 << 13)); // set CR4.VMXE to 1
+
+  // if NE bit is not set vmxon will fail
+  c.set_cr0(c.get_cr0() | (1 << 5));
+
+  enum
+  {
+    Vmcs_size = 0x1000, // actual size may be different
+  };
+
+  Unsigned32 vmcs_size = ((info.basic & (0x1fffULL << 32)) >> 32);
+
+  if (vmcs_size > Vmcs_size)
+    {
+      printf("VMX: VMCS size of %d bytes not supported\n", vmcs_size);
+      return;
+    }
+
+  // allocate a 4kb region for kernel vmcs
+  check(_kernel_vmcs = Mapped_allocator::allocator()->alloc(12));
+  _kernel_vmcs_pa = Kmem::virt_to_phys(_kernel_vmcs);
+  // clean vmcs
+  memset(_kernel_vmcs, 0, vmcs_size);
+  // init vmcs with revision identifier
+  *(int *)_kernel_vmcs = (info.basic & 0xFFFFFFFF);
+
+  // allocate a 4kb aligned region for VMXON
+  check(_vmxon = Mapped_allocator::allocator()->alloc(12));
+
+  _vmxon_base_pa = Kmem::virt_to_phys(_vmxon);
+
+  // init vmxon region with vmcs revision identifier
+  // which is stored in the lower 32 bits of MSR 0x480
+  *(unsigned *)_vmxon = (info.basic & 0xFFFFFFFF);
+
+  // enable vmx operation
+  asm volatile("vmxon %0" : :"m"(_vmxon_base_pa):);
+  _vmx_enabled = true;
+
+  printf("VMX: initialized\n");
+
+  Mword eflags;
+  asm volatile("vmclear %1 \n\t"
+              "pushf      \n\t"
+              "pop %0     \n\t" : "=r"(eflags) : "m"(_kernel_vmcs_pa):);
+  if (eflags & 0x41)
+    panic("VMX: vmclear: VMFailInvalid, vmcs pointer not valid\n");
+
+  // make kernel vmcs current
+  asm volatile("vmptrld %1 \n\t"
+              "pushf      \n\t"
+              "pop %0     \n\t" : "=r"(eflags) : "m"(_kernel_vmcs_pa):);
+
+  if (eflags & 0x41)
+    panic("VMX: vmptrld: VMFailInvalid, vmcs pointer not valid\n");
+
+  extern char entry_sys_fast_ipc_c[];
+  extern char vm_vmx_exit_vec[];
+
+  vmwrite(F_host_es_selector, GDT_DATA_KERNEL);
+  vmwrite(F_host_cs_selector, GDT_CODE_KERNEL);
+  vmwrite(F_host_ss_selector, GDT_DATA_KERNEL);
+  vmwrite(F_host_ds_selector, GDT_DATA_KERNEL);
+
+  Unsigned16 tr = c.get_tr();
+  vmwrite(F_host_tr_selector, tr);
+
+  vmwrite(F_host_tr_base, ((*c.get_gdt())[tr / 8]).base());
+  vmwrite(F_host_rip, vm_vmx_exit_vec);
+  vmwrite<Mword>(F_host_sysenter_cs, Gdt::gdt_code_kernel);
+  vmwrite(F_host_sysenter_esp, &c.kernel_sp());
+  vmwrite(F_host_sysenter_eip, entry_sys_fast_ipc_c);
+
+  if (c.features() & FEAT_PAT && info.exit_ctls.allowed(19))
+    vmwrite(F_host_ia32_pat, Cpu::rdmsr(MSR_PAT));
+  else
+    {
+      // We have no proper PAT support, so disallow PAT load store for
+      // guest too
+      info.exit_ctls.enforce(18, false);
+      info.entry_ctls.enforce(14, false);
+    }
+
+  if (info.exit_ctls.allowed(21)) // Load IA32_EFER
+    vmwrite(F_host_ia32_efer, Cpu::rdmsr(MSR_EFER));
+  else
+    {
+      // We have no EFER load for host, so disallow EFER load store for
+      // guest too
+      info.exit_ctls.enforce(20, false);
+      info.entry_ctls.enforce(15, false);
+    }
+
+  if (info.exit_ctls.allowed(12))
+    vmwrite(F_host_ia32_perf_global_ctrl, Cpu::rdmsr(0x199));
+  else
+    // do not allow Load IA32_PERF_GLOBAL_CTRL on entry
+    info.entry_ctls.enforce(13, false);
+
+  vmwrite(F_host_cr0, info.cr0_defs.apply(Cpu::get_cr0()));
+  vmwrite(F_host_cr4, info.cr4_defs.apply(Cpu::get_cr4()));
+
+  Pseudo_descriptor pseudo;
+  c.get_gdt()->get(&pseudo);
+
+  vmwrite(F_host_gdtr_base, pseudo.base());
+
+  Idt::get(&pseudo);
+  vmwrite(F_host_idtr_base, pseudo.base());
+
+  // init static guest area stuff
+  vmwrite(0x2800, ~0ULL); // link pointer
+  vmwrite(F_cr3_target_cnt, 0);
+
+  // MSR load / store disbaled
+  vmwrite(F_exit_msr_load_cnt, 0);
+  vmwrite(F_exit_msr_store_cnt, 0);
+  vmwrite(F_entry_msr_load_cnt, 0);
+
+}
+
+PUBLIC
+void *
+Vmx::kernel_vmcs() const
+{ return _kernel_vmcs; }
+
+PUBLIC
+Address
+Vmx::kernel_vmcs_pa() const
+{ return _kernel_vmcs_pa; }
+
+PUBLIC
+bool
+Vmx::vmx_enabled() const
+{ return _vmx_enabled; }
+
+PUBLIC
+bool
+Vmx::has_vpid() const
+{ return _has_vpid; }

diff --git a/kernel/fiasco/src/kern/kernel_thread.cpp b/kernel/fiasco/src/kern/kernel_thread.cpp
index 10ddfbed7e889a2fcb6ad187f31972916ef2f28f..dee8b99081c79f266c91111358bdd6d52784b7f2 100644 (file)
--- a/kernel/fiasco/src/kern/kernel_thread.cpp
+++ b/kernel/fiasco/src/kern/kernel_thread.cpp
@@ -83,6 +83,8 @@ Kernel_thread::bootstrap()
 
   bootstrap_arch();
 
 
   bootstrap_arch();
 

+  Per_cpu_data::run_late_ctors(0);
+

   Proc::sti();
   printf("Calibrating timer loop... ");
   // Init delay loop, needs working timer interrupt
   Proc::sti();
   printf("Calibrating timer loop... ");
   // Init delay loop, needs working timer interrupt

diff --git a/kernel/fiasco/src/kern/obj_space-virt.cpp b/kernel/fiasco/src/kern/obj_space-virt.cpp
index cad2b8c4ea0de05b92aab38ec2d1875bc72f66c4..09f04a65678bd8137498371c925f5447693c668f 100644 (file)
--- a/kernel/fiasco/src/kern/obj_space-virt.cpp
+++ b/kernel/fiasco/src/kern/obj_space-virt.cpp
@@ -41,7 +41,9 @@ inline NEEDS["mem_space.h", "mem_layout.h", Generic_obj_space::cap_virt]
 typename Generic_obj_space<SPACE>::Entry *
 Generic_obj_space<SPACE>::alien_lookup(Address index)
 {
 typename Generic_obj_space<SPACE>::Entry *
 Generic_obj_space<SPACE>::alien_lookup(Address index)
 {

-  Address phys = Address(mem_space()->virt_to_phys((Address)cap_virt(index)));
+  Mem_space *ms = mem_space();
+
+  Address phys = Address(ms->virt_to_phys((Address)cap_virt(index)));

   if (EXPECT_FALSE(phys == ~0UL))
     return 0;
 
   if (EXPECT_FALSE(phys == ~0UL))
     return 0;
 


@@ -106,6 +108,10 @@ PRIVATE template< typename SPACE >
 void
 Generic_obj_space<SPACE>::caps_free()
 {
 void
 Generic_obj_space<SPACE>::caps_free()
 {

+  Mem_space *ms = mem_space();
+  if (EXPECT_FALSE(!ms || !ms->dir()))
+    return;
+

   Mapped_allocator *a = Mapped_allocator::allocator();
   for (unsigned long i = 0; i < map_max_address().value();
        i += Caps_per_page)
   Mapped_allocator *a = Mapped_allocator::allocator();
   for (unsigned long i = 0; i < map_max_address().value();
        i += Caps_per_page)


@@ -114,7 +120,7 @@ Generic_obj_space<SPACE>::caps_free()
       if (!c)
        continue;
 
       if (!c)
        continue;
 

-      Address cp = Address(mem_space()->virt_to_phys(Address(c)));
+      Address cp = Address(ms->virt_to_phys(Address(c)));

       assert_kdb (cp != ~0UL);
       void *cv = (void*)Mem_layout::phys_to_pmem(cp);
       remove_dbg_info(cv);
       assert_kdb (cp != ~0UL);
       void *cv = (void*)Mem_layout::phys_to_pmem(cp);
       remove_dbg_info(cv);


@@ -122,9 +128,9 @@ Generic_obj_space<SPACE>::caps_free()
       a->q_unaligned_free(ram_quota(), Config::PAGE_SIZE, cv);
     }
 #if defined (CONFIG_ARM)
       a->q_unaligned_free(ram_quota(), Config::PAGE_SIZE, cv);
     }
 #if defined (CONFIG_ARM)

-  mem_space()->dir()->free_page_tables((void*)Mem_layout::Caps_start, (void*)Mem_layout::Caps_end);
+  ms->dir()->free_page_tables((void*)Mem_layout::Caps_start, (void*)Mem_layout::Caps_end);

 #else
 #else

-  mem_space()->dir()->Pdir::alloc_cast<Mem_space_q_alloc>()
+  ms->dir()->Pdir::alloc_cast<Mem_space_q_alloc>()

     ->destroy(Virt_addr(Mem_layout::Caps_start),
               Virt_addr(Mem_layout::Caps_end), Pdir::Depth - 1,
               Mem_space_q_alloc(ram_quota(), Mapped_allocator::allocator()));
     ->destroy(Virt_addr(Mem_layout::Caps_start),
               Virt_addr(Mem_layout::Caps_end), Pdir::Depth - 1,
               Mem_space_q_alloc(ram_quota(), Mapped_allocator::allocator()));

diff --git a/kernel/fiasco/src/kern/per_cpu_data.cpp b/kernel/fiasco/src/kern/per_cpu_data.cpp
index 41f41e9f7e170dea30a98301934244778793fb7d..d9262c720a4c6edeb722498dcee20347b55b9cf4 100644 (file)
--- a/kernel/fiasco/src/kern/per_cpu_data.cpp
+++ b/kernel/fiasco/src/kern/per_cpu_data.cpp
@@ -4,6 +4,7 @@ INTERFACE:
 
 #define DEFINE_PER_CPU_P(p) __attribute__((section(".per_cpu.data"),init_priority(0xfffe - p)))
 #define DEFINE_PER_CPU      DEFINE_PER_CPU_P(9)
 
 #define DEFINE_PER_CPU_P(p) __attribute__((section(".per_cpu.data"),init_priority(0xfffe - p)))
 #define DEFINE_PER_CPU      DEFINE_PER_CPU_P(9)

+#define DEFINE_PER_CPU_LATE DEFINE_PER_CPU_P(19)

 
 class Mapped_allocator;
 
 
 class Mapped_allocator;
 


@@ -12,6 +13,7 @@ class Per_cpu_data
 public:
   static void init_ctors(Mapped_allocator *a);
   static void run_ctors(unsigned cpu);
 public:
   static void init_ctors(Mapped_allocator *a);
   static void run_ctors(unsigned cpu);

+  static void run_late_ctors(unsigned cpu);

   static bool valid(unsigned cpu);
 };
 
   static bool valid(unsigned cpu);
 };
 


@@ -75,6 +77,12 @@ Per_cpu<T>::Per_cpu(bool) : _d(0)
 IMPLEMENT
 void
 Per_cpu_data::init_ctors(Mapped_allocator *)
 IMPLEMENT
 void
 Per_cpu_data::init_ctors(Mapped_allocator *)

+{
+}
+
+IMPLEMENT inline
+void
+Per_cpu_data::run_ctors(unsigned)

 {
   typedef void (*ctor)(void);
   extern ctor __PER_CPU_CTORS_LIST__[];
 {
   typedef void (*ctor)(void);
   extern ctor __PER_CPU_CTORS_LIST__[];


@@ -88,8 +96,17 @@ Per_cpu_data::init_ctors(Mapped_allocator *)
 
 IMPLEMENT inline
 void
 
 IMPLEMENT inline
 void

-Per_cpu_data::run_ctors(unsigned)
-{}
+Per_cpu_data::run_late_ctors(unsigned)
+{
+  typedef void (*ctor)(void);
+  extern ctor __PER_CPU_LATE_CTORS_LIST__[];
+  extern ctor __PER_CPU_LATE_CTORS_END__[];
+  for (unsigned i = __PER_CPU_LATE_CTORS_LIST__ - __PER_CPU_LATE_CTORS_END__; i > 0; --i)
+    {
+      //printf("Per_cpu: init ctor %u (%p)\n", i-1, &__PER_CPU_LATE_CTORS_END__[i-1]);
+      __PER_CPU_LATE_CTORS_END__[i-1]();
+    }
+}

 
 
 //---------------------------------------------------------------------------
 
 
 //---------------------------------------------------------------------------


@@ -130,6 +147,7 @@ private:
   };
 protected:
   static long _offsets[Config::Max_num_cpus] asm ("PER_CPU_OFFSETS");
   };
 protected:
   static long _offsets[Config::Max_num_cpus] asm ("PER_CPU_OFFSETS");

+  static unsigned late_ctor_start;

   static Ctor_vector ctors;
   static Mapped_allocator *alloc;
 };
   static Ctor_vector ctors;
   static Mapped_allocator *alloc;
 };


@@ -142,6 +160,7 @@ IMPLEMENTATION [mp]:
 #include <cstring>
 
 long Per_cpu_data::_offsets[Config::Max_num_cpus];
 #include <cstring>
 
 long Per_cpu_data::_offsets[Config::Max_num_cpus];

+unsigned Per_cpu_data::late_ctor_start;

 Per_cpu_data::Ctor_vector Per_cpu_data::ctors INIT_PRIORITY(EARLY_INIT_PRIO);
 Mapped_allocator *Per_cpu_data::alloc;
 
 Per_cpu_data::Ctor_vector Per_cpu_data::ctors INIT_PRIORITY(EARLY_INIT_PRIO);
 Mapped_allocator *Per_cpu_data::alloc;
 


@@ -222,15 +241,7 @@ IMPLEMENT
 void
 Per_cpu_data::init_ctors(Mapped_allocator *a)
 {
 void
 Per_cpu_data::init_ctors(Mapped_allocator *a)
 {

-  typedef void (*ctor)(void);
-  extern ctor __PER_CPU_CTORS_LIST__[];
-  extern ctor __PER_CPU_CTORS_END__[];

   alloc = a;
   alloc = a;

-  for (unsigned i = __PER_CPU_CTORS_LIST__ - __PER_CPU_CTORS_END__; i > 0; --i)
-    {
-      //printf("Per_cpu: init ctor %u (%p)\n", i-1, &__PER_CPU_CTORS_END__[i-1]);
-      __PER_CPU_CTORS_END__[i-1]();
-    }

 
   for (unsigned i = 0; i < Config::Max_num_cpus; ++i)
     _offsets[i] = -1;
 
   for (unsigned i = 0; i < Config::Max_num_cpus; ++i)
     _offsets[i] = -1;


@@ -241,10 +252,42 @@ void
 Per_cpu_data::run_ctors(unsigned cpu)
 {
   if (cpu == 0)
 Per_cpu_data::run_ctors(unsigned cpu)
 {
   if (cpu == 0)

-    return;
+    {
+      typedef void (*ctor)(void);
+      extern ctor __PER_CPU_CTORS_LIST__[];
+      extern ctor __PER_CPU_CTORS_END__[];
+      for (unsigned i = __PER_CPU_CTORS_LIST__ - __PER_CPU_CTORS_END__; i > 0; --i)
+       {
+         //printf("Per_cpu: init ctor %u (%p)\n", i-1, &__PER_CPU_CTORS_END__[i-1]);
+         __PER_CPU_CTORS_END__[i-1]();
+       }
+
+      late_ctor_start = ctors.len();
+      return;
+    }

 
 

-  unsigned c = ctors.len();
-  for (unsigned i = 0; i < c; ++i)
+  for (unsigned i = 0; i < late_ctor_start; ++i)

     ctors[i].func(ctors[i].base, cpu);
 }
 
     ctors[i].func(ctors[i].base, cpu);
 }
 

+IMPLEMENT inline
+void
+Per_cpu_data::run_late_ctors(unsigned cpu)
+{
+  if (cpu == 0)
+    {
+      typedef void (*ctor)(void);
+      extern ctor __PER_CPU_LATE_CTORS_LIST__[];
+      extern ctor __PER_CPU_LATE_CTORS_END__[];
+      for (unsigned i = __PER_CPU_LATE_CTORS_LIST__ - __PER_CPU_LATE_CTORS_END__; i > 0; --i)
+       {
+         //printf("Per_cpu: init ctor %u (%p)\n", i-1, &__PER_CPU_LATE_CTORS_END__[i-1]);
+         __PER_CPU_LATE_CTORS_END__[i-1]();
+       }
+      return;
+    }
+
+  unsigned c = ctors.len();
+  for (unsigned i = late_ctor_start; i < c; ++i)
+    ctors[i].func(ctors[i].base, cpu);
+}

diff --git a/kernel/fiasco/src/kern/regdefs.h b/kernel/fiasco/src/kern/regdefs.h
index 504540d3938ce8c488a727b83ccc6ae0c06260eb..19b094f3cfb2a7e931a269351a9af7d4369f665e 100644 (file)
--- a/kernel/fiasco/src/kern/regdefs.h
+++ b/kernel/fiasco/src/kern/regdefs.h
@@ -117,6 +117,7 @@
 #define PF_ERR_USERADDR 0x80000000      // PF: In User Address Space
 
 // Model Specific Registers
 #define PF_ERR_USERADDR 0x80000000      // PF: In User Address Space
 
 // Model Specific Registers

+#define MSR_TSC              0x010      // Time Stamp Counter

 #define MSR_SYSENTER_CS      0x174      // Kernel Code Segment
 #define MSR_SYSENTER_ESP     0x175      // Kernel Syscall Entry
 #define MSR_SYSENTER_EIP     0x176      // Kernel Stack Pointer
 #define MSR_SYSENTER_CS      0x174      // Kernel Code Segment
 #define MSR_SYSENTER_ESP     0x175      // Kernel Syscall Entry
 #define MSR_SYSENTER_EIP     0x176      // Kernel Stack Pointer


@@ -132,6 +133,7 @@
 #define MSR_LASTBRANCHTOIP   0x1dc      // (P6)
 #define MSR_LASTINTFROMIP    0x1dd      // (P6)
 #define MSR_LASTINTTOIP      0x1de      // (P6)
 #define MSR_LASTBRANCHTOIP   0x1dc      // (P6)
 #define MSR_LASTINTFROMIP    0x1dd      // (P6)
 #define MSR_LASTINTTOIP      0x1de      // (P6)

+#define MSR_PAT              0x277      // PAT

 
 // AMD64 Model Specific Registers
 #define MSR_EFER        0xc0000080      // Extended Feature Enable Register
 
 // AMD64 Model Specific Registers
 #define MSR_EFER        0xc0000080      // Extended Feature Enable Register

diff --git a/kernel/fiasco/src/kern/task.cpp b/kernel/fiasco/src/kern/task.cpp
index e4b29cb5559916c7aaa1a94d0a0db6917f65c5e6..6ec363de78607041eeb4d8423033b8013523ed56 100644 (file)
--- a/kernel/fiasco/src/kern/task.cpp
+++ b/kernel/fiasco/src/kern/task.cpp
@@ -174,7 +174,7 @@ IMPLEMENT
 void
 Task::free_utcbs()
 {
 void
 Task::free_utcbs()
 {

-  if (!kern_utcb_area())
+  if (EXPECT_FALSE(!kern_utcb_area() || !mem_space() || !mem_space()->dir()))

     return;
 
   Mapped_allocator * const alloc = Mapped_allocator::allocator();
     return;
 
   Mapped_allocator * const alloc = Mapped_allocator::allocator();

diff --git a/kernel/fiasco/src/kern/thread-vcpu.cpp b/kernel/fiasco/src/kern/thread-vcpu.cpp
index 1ad498cc2ffbb6290cd1761927dc721a7fb8da5d..0809209ec5e129cdef028d7973f4e5b266254c49 100644 (file)
--- a/kernel/fiasco/src/kern/thread-vcpu.cpp
+++ b/kernel/fiasco/src/kern/thread-vcpu.cpp
@@ -135,7 +135,7 @@ Thread::sys_vcpu_resume(L4_msg_tag const &tag, Utcb *utcb)
 
       vcpu_state()->state |= Vcpu_state::F_traps | Vcpu_state::F_exceptions
                              | Vcpu_state::F_debug_exc;
 
       vcpu_state()->state |= Vcpu_state::F_traps | Vcpu_state::F_exceptions
                              | Vcpu_state::F_debug_exc;

-      state_add_dirty(Thread_vcpu_user_mode | Thread_alien);
+      state_add_dirty(Thread_vcpu_user_mode);

 
       if (!(vcpu_state()->state & Vcpu_state::F_fpu_enabled))
        {
 
       if (!(vcpu_state()->state & Vcpu_state::F_fpu_enabled))
        {

diff --git a/kernel/fiasco/src/kern/ux/usermode.cpp b/kernel/fiasco/src/kern/ux/usermode.cpp
index 254c0542986dca9cd712c8c31a74477bb652f59d..059808ee890e9126ebf791489155a16cc9a4d0d4 100644 (file)
--- a/kernel/fiasco/src/kern/ux/usermode.cpp
+++ b/kernel/fiasco/src/kern/ux/usermode.cpp
@@ -304,7 +304,7 @@ Usermode::user_exception (unsigned _cpu, pid_t pid, struct ucontext *context,
        * instructions in the syscall page.
        */
       if (EXPECT_FALSE((t->state() & (Thread_alien | Thread_dis_alien))
        * instructions in the syscall page.
        */
       if (EXPECT_FALSE((t->state() & (Thread_alien | Thread_dis_alien))

-                       == Thread_alien))
+                       == Thread_alien || t->state() & Thread_vcpu_user_mode))

         regs->eip += 2;
       else
         {
         regs->eip += 2;
       else
         {

diff --git a/kernel/fiasco/src/kernel.amd64.ld b/kernel/fiasco/src/kernel.amd64.ld
index cb64b1457e95748ff7326b49c4b3673251264cfe..4ef2054654f8019d7005184bba44569c5374d8f3 100644 (file)
--- a/kernel/fiasco/src/kernel.amd64.ld
+++ b/kernel/fiasco/src/kernel.amd64.ld
@@ -122,6 +122,19 @@ SECTIONS {
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 

+    __PER_CPU_LATE_CTORS_END__ = .;
+    KEEP (*(.ctors.00020))
+    KEEP (*(.ctors.00019))
+    KEEP (*(.ctors.00018))
+    KEEP (*(.ctors.00017))
+    KEEP (*(.ctors.00016))
+    KEEP (*(.ctors.00015))
+    KEEP (*(.ctors.00014))
+    KEEP (*(.ctors.00013))
+    KEEP (*(.ctors.00012))
+    KEEP (*(.ctors.00011))
+    __PER_CPU_LATE_CTORS_LIST__ = .;
+

     __CTOR_END__ = .;
     CONSTRUCTORS
     KEEP (*(.ctors))
     __CTOR_END__ = .;
     CONSTRUCTORS
     KEEP (*(.ctors))

diff --git a/kernel/fiasco/src/kernel.arm.ld b/kernel/fiasco/src/kernel.arm.ld
index c629433889edd0effb162313622322778606d875..3706a6e1068c599f923e4e79ec1cf60ce5f80db7 100644 (file)
--- a/kernel/fiasco/src/kernel.arm.ld
+++ b/kernel/fiasco/src/kernel.arm.ld
@@ -137,6 +137,19 @@ SECTIONS {
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 

+    __PER_CPU_LATE_CTORS_END__ = .;
+    KEEP (*(.ctors.00020))
+    KEEP (*(.ctors.00019))
+    KEEP (*(.ctors.00018))
+    KEEP (*(.ctors.00017))
+    KEEP (*(.ctors.00016))
+    KEEP (*(.ctors.00015))
+    KEEP (*(.ctors.00014))
+    KEEP (*(.ctors.00013))
+    KEEP (*(.ctors.00012))
+    KEEP (*(.ctors.00011))
+    __PER_CPU_LATE_CTORS_LIST__ = .;
+

     __CTOR_END__ = .;
     CONSTRUCTORS
     KEEP (*(.ctors))
     __CTOR_END__ = .;
     CONSTRUCTORS
     KEEP (*(.ctors))

diff --git a/kernel/fiasco/src/kernel.ia32.ld b/kernel/fiasco/src/kernel.ia32.ld
index 09b49d4a521bd1c12d4e293e733200bba59fc217..91d6ab4e22cb004978235376d2ad05d031c8148e 100644 (file)
--- a/kernel/fiasco/src/kernel.ia32.ld
+++ b/kernel/fiasco/src/kernel.ia32.ld
@@ -113,6 +113,19 @@ SECTIONS {
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 

+    __PER_CPU_LATE_CTORS_END__ = .;
+    KEEP (*(.ctors.00020))
+    KEEP (*(.ctors.00019))
+    KEEP (*(.ctors.00018))
+    KEEP (*(.ctors.00017))
+    KEEP (*(.ctors.00016))
+    KEEP (*(.ctors.00015))
+    KEEP (*(.ctors.00014))
+    KEEP (*(.ctors.00013))
+    KEEP (*(.ctors.00012))
+    KEEP (*(.ctors.00011))
+    __PER_CPU_LATE_CTORS_LIST__ = .;
+

     __CTOR_END__ = .;
     CONSTRUCTORS
     KEEP (*(.ctors))
     __CTOR_END__ = .;
     CONSTRUCTORS
     KEEP (*(.ctors))

diff --git a/kernel/fiasco/src/kernel.ppc32.ld b/kernel/fiasco/src/kernel.ppc32.ld
index adca26216fc854952df9b1c7e4035a30530822b5..95b63a439d4ec4af4df62f2ebced066ebb6b7f33 100644 (file)
--- a/kernel/fiasco/src/kernel.ppc32.ld
+++ b/kernel/fiasco/src/kernel.ppc32.ld
@@ -79,6 +79,7 @@ SECTIONS {
        are traversed from end to start, therefore the *_END__ symbols
        precede the *_LIST__ symbols. */
     . = ALIGN(8);
        are traversed from end to start, therefore the *_END__ symbols
        precede the *_LIST__ symbols. */
     . = ALIGN(8);

+

     __PER_CPU_CTORS_END__ = .;
     KEEP (*(.ctors.00010))
     KEEP (*(.ctors.00009))
     __PER_CPU_CTORS_END__ = .;
     KEEP (*(.ctors.00010))
     KEEP (*(.ctors.00009))


@@ -92,6 +93,19 @@ SECTIONS {
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 

+    __PER_CPU_LATE_CTORS_END__ = .;
+    KEEP (*(.ctors.00020))
+    KEEP (*(.ctors.00019))
+    KEEP (*(.ctors.00018))
+    KEEP (*(.ctors.00017))
+    KEEP (*(.ctors.00016))
+    KEEP (*(.ctors.00015))
+    KEEP (*(.ctors.00014))
+    KEEP (*(.ctors.00013))
+    KEEP (*(.ctors.00012))
+    KEEP (*(.ctors.00011))
+    __PER_CPU_LATE_CTORS_LIST__ = .;
+

     __CTOR_END__ = .;
     CONSTRUCTORS
     KEEP (*(.ctors))
     __CTOR_END__ = .;
     CONSTRUCTORS
     KEEP (*(.ctors))

diff --git a/kernel/fiasco/src/kernel.ux.ld b/kernel/fiasco/src/kernel.ux.ld
index 72782296cab86db82faed7ba6cc82f169b8973c6..498139501528f6f9598bdec29b89ca6f3ff1383a 100644 (file)
--- a/kernel/fiasco/src/kernel.ux.ld
+++ b/kernel/fiasco/src/kernel.ux.ld
@@ -88,6 +88,19 @@ SECTIONS {
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 
     KEEP (*(.ctors.00001))
     __PER_CPU_CTORS_LIST__ = .;
 

+    __PER_CPU_LATE_CTORS_END__ = .;
+    KEEP (*(.ctors.00020))
+    KEEP (*(.ctors.00019))
+    KEEP (*(.ctors.00018))
+    KEEP (*(.ctors.00017))
+    KEEP (*(.ctors.00016))
+    KEEP (*(.ctors.00015))
+    KEEP (*(.ctors.00014))
+    KEEP (*(.ctors.00013))
+    KEEP (*(.ctors.00012))
+    KEEP (*(.ctors.00011))
+    __PER_CPU_LATE_CTORS_LIST__ = .;
+

     . = ALIGN(4);
     PROVIDE (_log_table = .);
     /*
     . = ALIGN(4);
     PROVIDE (_log_table = .);
     /*

diff --git a/l4/Makefile b/l4/Makefile
index aab5e2c8b19f54fedbc806c9d9a96be63d85118a..5edd04a1a8cccd6956a563176212a9f658f213a6 100644 (file)
--- a/l4/Makefile
+++ b/l4/Makefile
@@ -227,7 +227,7 @@ Makeconf.bid.local-helper:
                <$(CONFIG_MK_REAL).tmp >>$(CONFIG_MK_REAL).tmp2
        $(VERBOSE)echo -e 'include $(call absfilename,$(CONFIG_MK_INDEP))' >>$(CONFIG_MK_REAL).tmp2
        $(VERBOSE)if [ -e "$(CONFIG_MK_REAL)" ]; then                        \
                <$(CONFIG_MK_REAL).tmp >>$(CONFIG_MK_REAL).tmp2
        $(VERBOSE)echo -e 'include $(call absfilename,$(CONFIG_MK_INDEP))' >>$(CONFIG_MK_REAL).tmp2
        $(VERBOSE)if [ -e "$(CONFIG_MK_REAL)" ]; then                        \

-                   diff --brief $(CONFIG_MK_REAL) $(CONFIG_MK_REAL).tmp2 || \
+                   diff --brief -I ^COLOR_TERMINAL $(CONFIG_MK_REAL) $(CONFIG_MK_REAL).tmp2 || \

                      mv $(CONFIG_MK_REAL).tmp2 $(CONFIG_MK_REAL);           \
                  else                                                       \
                    mv $(CONFIG_MK_REAL).tmp2 $(CONFIG_MK_REAL);             \
                      mv $(CONFIG_MK_REAL).tmp2 $(CONFIG_MK_REAL);           \
                  else                                                       \
                    mv $(CONFIG_MK_REAL).tmp2 $(CONFIG_MK_REAL);             \

diff --git a/l4/pkg/ankh/include/client-c.h b/l4/pkg/ankh/include/client-c.h
index 9b1c2ab43b1782d4b93af0758a6346fd48ff6364..2dea2488b9f357740c147061cc41e99b97cba7b3 100644 (file)
--- a/l4/pkg/ankh/include/client-c.h
+++ b/l4/pkg/ankh/include/client-c.h
@@ -63,11 +63,17 @@ L4_CV int l4ankh_prepare_recv(l4_cap_idx_t owner) L4_NOTHROW;
 //      two different versions -- FIX
 /*
  * Receive data, block if buffer empty.
 //      two different versions -- FIX
 /*
  * Receive data, block if buffer empty.

+ *
+ * Note: size is an in/out parameter. Specifies the maximum space available in
+ *       the buffer upon call. Returns the used size.

  */
 L4_CV int l4ankh_recv_blocking(char *buffer, unsigned *size) L4_NOTHROW;
 
 /*
  * Receive data, return error if none available
  */
 L4_CV int l4ankh_recv_blocking(char *buffer, unsigned *size) L4_NOTHROW;
 
 /*
  * Receive data, return error if none available

+ *
+ * Note: size is an in/out parameter. Specifies the maximum space available in
+ *       the buffer upon call. Returns the used size.

  */
 L4_CV int l4ankh_recv_nonblocking(char *buffer, unsigned *size) L4_NOTHROW;
 
  */
 L4_CV int l4ankh_recv_nonblocking(char *buffer, unsigned *size) L4_NOTHROW;
 

diff --git a/l4/pkg/bootstrap/server/src/ARCH-amd64/boot32/boot_kernel.c b/l4/pkg/bootstrap/server/src/ARCH-amd64/boot32/boot_kernel.c
index f7b6e1492e70926ffb6aa93620d6771b23dbea73..0ba4b3a8bca86f2e81b2075d25fa1b0577879215 100644 (file)
--- a/l4/pkg/bootstrap/server/src/ARCH-amd64/boot32/boot_kernel.c
+++ b/l4/pkg/bootstrap/server/src/ARCH-amd64/boot32/boot_kernel.c
@@ -41,7 +41,7 @@ bootstrap (l4util_mb_info_t *mbi, unsigned int flag, char *rm_pointer)
   } far_ptr;
   l4_uint64_t mem_upper;
 
   } far_ptr;
   l4_uint64_t mem_upper;
 

-  // setup stuff for base_paging_init() 
+  // setup stuff for base_paging_init()

   base_cpu_setup();
 
 #ifdef REALMODE_LOADING
   base_cpu_setup();
 
 #ifdef REALMODE_LOADING


@@ -60,8 +60,8 @@ bootstrap (l4util_mb_info_t *mbi, unsigned int flag, char *rm_pointer)
   printf("Loading 64bit part...\n");
   // switch from 32 Bit compatibility mode to 64 Bit mode
   far_ptr.cs    = KERNEL_CS_64;
   printf("Loading 64bit part...\n");
   // switch from 32 Bit compatibility mode to 64 Bit mode
   far_ptr.cs    = KERNEL_CS_64;

-  far_ptr.start = load_elf(&_binary_bootstrap64_bin_start, 
-                          &vma_start, &vma_end);
+  far_ptr.start = load_elf(&_binary_bootstrap64_bin_start,
+                           &vma_start, &vma_end);

 
   asm volatile("ljmp *(%4)"
                 :: "D"(mbi), "S"(flag), "d"(rm_pointer),
 
   asm volatile("ljmp *(%4)"
                 :: "D"(mbi), "S"(flag), "d"(rm_pointer),

diff --git a/l4/pkg/bootstrap/server/src/ARCH-amd64/boot32/load_elf.c b/l4/pkg/bootstrap/server/src/ARCH-amd64/boot32/load_elf.c
index 9f7c39282551581b8da843f43a71e5c0f1541b35..f81fd63504cd65d0a5ec0700aacd150e650e0890 100644 (file)
--- a/l4/pkg/bootstrap/server/src/ARCH-amd64/boot32/load_elf.c
+++ b/l4/pkg/bootstrap/server/src/ARCH-amd64/boot32/load_elf.c
@@ -14,6 +14,22 @@
 #include <l4/util/elf.h>
 #include "load_elf.h"
 
 #include <l4/util/elf.h>
 #include "load_elf.h"
 

+extern char _image_start;
+extern char _image_end;
+
+static void check_overlap(unsigned long s, unsigned long e)
+{
+  if (   (unsigned long)&_image_end >= s
+      && (unsigned long)&_image_start <= e)
+    {
+      printf("Overwrite: ELF-PH: %lx - %lx, bootstrap loader: %lx - %lx\n",
+             s, e, (unsigned long)&_image_start, (unsigned long)&_image_end);
+      printf("Change your 'modaddr' setting.\n");
+      while (1)
+        ;
+    }
+}
+

 l4_uint32_t
 load_elf (void *elf, l4_uint32_t *vma_start, l4_uint32_t *vma_end)
 {
 l4_uint32_t
 load_elf (void *elf, l4_uint32_t *vma_start, l4_uint32_t *vma_end)
 {


@@ -23,23 +39,29 @@ load_elf (void *elf, l4_uint32_t *vma_start, l4_uint32_t *vma_end)
   l4_uint32_t _vma_start = ~0, _vma_end = 0;
   int i;
 
   l4_uint32_t _vma_start = ~0, _vma_end = 0;
   int i;
 

-  for (i = 0; i < eh->e_phnum; i++, ph++) {
-    if (ph->p_type != PT_LOAD)
-      continue;
+  for (i = 0; i < eh->e_phnum; i++, ph++)
+    {
+      if (ph->p_type != PT_LOAD)
+        continue;
+
+      if (ph->p_vaddr < _vma_start)
+        _vma_start = ph->p_vaddr;
+
+      if (ph->p_vaddr + ph->p_memsz > _vma_end)
+        _vma_end = ph->p_vaddr + ph->p_memsz;

 
 

-    if (ph->p_vaddr < _vma_start)
-      _vma_start = ph->p_vaddr;
-    
-    if (ph->p_vaddr + ph->p_memsz > _vma_end)
-      _vma_end = ph->p_vaddr + ph->p_memsz;
+      check_overlap(ph->p_paddr, ph->p_paddr + ph->p_filesz);

 
 

-    memcpy ((void*)((Elf32_Addr)ph->p_paddr), 
-           _elf + ph->p_offset, ph->p_filesz);
+      memcpy((void*)((Elf32_Addr)ph->p_paddr),
+             _elf + ph->p_offset, ph->p_filesz);

 
 

-    if (ph->p_filesz < ph->p_memsz)
-      memset ((void*) ((Elf32_Addr)(ph->p_paddr + ph->p_filesz)), 0,
-                                    ph->p_memsz - ph->p_filesz);
-  }
+      if (ph->p_filesz < ph->p_memsz)
+        {
+          check_overlap(ph->p_paddr + ph->p_filesz, ph->p_paddr + ph->p_memsz);
+          memset((void*)((Elf32_Addr)(ph->p_paddr + ph->p_filesz)), 0,
+                 ph->p_memsz - ph->p_filesz);
+        }
+    }

 
   if (vma_start)
     *vma_start = _vma_start;
 
   if (vma_start)
     *vma_start = _vma_start;

diff --git a/l4/pkg/bootstrap/server/src/Make.rules b/l4/pkg/bootstrap/server/src/Make.rules
index a237d1b5822341a6eb176f8a0a4bed63a77d1437..d7deb11dcc276e59f71a4144d5af734626e925c3 100644 (file)
--- a/l4/pkg/bootstrap/server/src/Make.rules
+++ b/l4/pkg/bootstrap/server/src/Make.rules
@@ -163,9 +163,18 @@ REDO_TEXT_CMD = echo "$(ENTRY) '$(COMPRESS)' '$(RAM_SIZE_MB)' '$(PLATFORM_TYPE)'
 
 ifneq ($(ENTRY),)
 
 
 ifneq ($(ENTRY),)
 

-INSTALL_TARGET = $(BOOTSTRAP_ELF_NAME) bootstrap_$(ENTRY_FN) bootstrap_$(ENTRY_FN).elf
+INSTALL_TARGET  = $(BOOTSTRAP_ELF_NAME) bootstrap_$(ENTRY_FN) bootstrap_$(ENTRY_FN).elf
+ifeq ($(ARCH),amd64)
+INSTALL_TARGET += bootstrap32.elf
+BOOTSTRAP_LINK_SOURCE = bootstrap32.elf
+else
+BOOTSTRAP_LINK_SOURCE = $(BOOTSTRAP_ELF_NAME)
+endif

 
 

-bootstrap_$(ENTRY_FN).elf: $(BOOTSTRAP_ELF_NAME)
+bootstrap_$(ENTRY_FN): $(BOOTSTRAP_LINK_SOURCE)
+       $(VERBOSE)$(LN) -f $< $@
+
+bootstrap_$(ENTRY_FN).elf: $(BOOTSTRAP_LINK_SOURCE)

        $(VERBOSE)$(LN) -f $< $@
 
 bootstrap_$(ENTRY_FN).raw: bootstrap.raw
        $(VERBOSE)$(LN) -f $< $@
 
 bootstrap_$(ENTRY_FN).raw: bootstrap.raw


@@ -220,7 +229,7 @@ $(IMAGES_DIR)/Makefile: $(SRC_DIR)/Make.rules
        $(VERBOSE)$(ECHO) "     \$$(MAKE) -C .. image E=\"\$$@\"" >> $@
 else
   INSTALL_TARGET = bootstrap
        $(VERBOSE)$(ECHO) "     \$$(MAKE) -C .. image E=\"\$$@\"" >> $@
 else
   INSTALL_TARGET = bootstrap

-endif
+endif # ENTRY

 
 ifneq ($(REALMODE_LOADING),0)
 LOADER_MBI      = 1
 
 ifneq ($(REALMODE_LOADING),0)
 LOADER_MBI      = 1


@@ -246,10 +255,6 @@ ifneq ($(RAM_SIZE_MB),)
 CPPFLAGS       += -DRAM_SIZE_MB=$(RAM_SIZE_MB)
 endif
 
 CPPFLAGS       += -DRAM_SIZE_MB=$(RAM_SIZE_MB)
 endif
 

-ifeq ($(ARCH),amd64)
-all:: $(OBJ_DIR)/ARCH-amd64/libc32/OBJ-$(ARCH)_$(CPU)/libc32.a
-endif
-

 CXXFLAGS += -fno-rtti -fno-exceptions
 CXXFLAGS += $(call checkcxx,-fno-threadsafe-statics)
 
 CXXFLAGS += -fno-rtti -fno-exceptions
 CXXFLAGS += $(call checkcxx,-fno-threadsafe-statics)
 


@@ -379,13 +384,16 @@ CFLAGS32  := $(filter-out -m64, $(CFLAGS)) -m32
 $(OBJ_DIR)/ARCH-amd64/libc32/OBJ-$(ARCH)_$(CPU)/libc32.a: FORCE
        $(VERBOSE)$(MAKE) O=$(OBJ_BASE) -C $(SRC_DIR)/ARCH-amd64/libc32
 
 $(OBJ_DIR)/ARCH-amd64/libc32/OBJ-$(ARCH)_$(CPU)/libc32.a: FORCE
        $(VERBOSE)$(MAKE) O=$(OBJ_BASE) -C $(SRC_DIR)/ARCH-amd64/libc32
 

-bootstrap: $(OBJ32) bootstrap32.bin $(OBJ_DIR)/ARCH-amd64/libc32/OBJ-$(ARCH)_$(CPU)/libc32.a
+bootstrap32.elf: $(OBJ32) bootstrap32.bin $(OBJ_DIR)/ARCH-amd64/libc32/OBJ-$(ARCH)_$(CPU)/libc32.a

        @$(LINK_MESSAGE)
        $(VERBOSE)$(CC32) -o $@ -nostdlib -static \
          -Wl,-T,$(SRC_DIR)/ARCH-amd64/boot32/bootstrap32.ld,--gc-sections $^ -lgcc
        $(VERBOSE)chmod 755 $@
 
        @$(LINK_MESSAGE)
        $(VERBOSE)$(CC32) -o $@ -nostdlib -static \
          -Wl,-T,$(SRC_DIR)/ARCH-amd64/boot32/bootstrap32.ld,--gc-sections $^ -lgcc
        $(VERBOSE)chmod 755 $@
 

-bootstrap32.bin: $(TARGET)
+bootstrap: bootstrap32.elf
+       $(VERBOSE)$(LN) -f $^ $@
+
+bootstrap32.bin: $(BOOTSTRAP_ELF_NAME)

        @$(GEN_MESSAGE)
        $(VERBOSE)$(OBJCOPY) -S $< bootstrap64.bin
        $(VERBOSE)chmod -x bootstrap64.bin
        @$(GEN_MESSAGE)
        $(VERBOSE)$(OBJCOPY) -S $< bootstrap64.bin
        $(VERBOSE)chmod -x bootstrap64.bin


@@ -409,6 +417,3 @@ else
 bootstrap: $(BOOTSTRAP_ELF_NAME)
        $(VERBOSE)$(LN) -f $^ $@
 endif
 bootstrap: $(BOOTSTRAP_ELF_NAME)
        $(VERBOSE)$(LN) -f $^ $@
 endif

-
-bootstrap_$(ENTRY_FN): $(BOOTSTRAP_ELF_NAME)
-       $(VERBOSE)$(LN) -f $^ $@

diff --git a/l4/pkg/bootstrap/server/src/startup.cc b/l4/pkg/bootstrap/server/src/startup.cc
index 99505a0519ea8b4e8cc9897261164701f63e4047..bdf52ecfd0375cc98ffc1992fae05aca605f7d94 100644 (file)
--- a/l4/pkg/bootstrap/server/src/startup.cc
+++ b/l4/pkg/bootstrap/server/src/startup.cc
@@ -926,19 +926,31 @@ init_pc_serial(l4util_mb_info_t *mbi)
 #if defined(ARCH_x86) || defined(ARCH_amd64)
   const char *s;
   int comport = -1;
 #if defined(ARCH_x86) || defined(ARCH_amd64)
   const char *s;
   int comport = -1;

+  int pci = 0;

 
   if ((s = check_arg(mbi, "-comport")))
 
   if ((s = check_arg(mbi, "-comport")))

-    comport = strtoul(s + 9, 0, 0);
+    {
+      char const *a = s + 9;
+      if (!strncmp(a, "pci:", 4))
+       {
+         pci = 1;
+         a = a + 4;
+       }
+    
+      comport = strtoul(a, 0, 0);
+    }

 
   if (check_arg(mbi, "-serial"))
     {
 
   if (check_arg(mbi, "-serial"))
     {

-      if (0)
+      if (pci)

         {
         {

-          extern unsigned long search_pci_serial_devs(bool scan_only);
-          unsigned long port;
-          if (comport == -1
-              && (port = search_pci_serial_devs(false)))
+          extern unsigned long search_pci_serial_devs(int port_idx, bool scan_only);
+          if (unsigned long port = search_pci_serial_devs(comport, true))

             comport = port;
             comport = port;

+         else
+           comport = -1;
+
+         printf("PCI IO port = %lx\n", comport);

         }
 
       if (comport == -1)
         }
 
       if (comport == -1)

diff --git a/l4/pkg/bootstrap/server/src/support_x86_pc.cc b/l4/pkg/bootstrap/server/src/support_x86_pc.cc
index fedfbddce8ee14db68a3186dc201b3518caa8a95..c9193976b175578710923211a675612df2e1f186 100644 (file)
--- a/l4/pkg/bootstrap/server/src/support_x86_pc.cc
+++ b/l4/pkg/bootstrap/server/src/support_x86_pc.cc
@@ -264,19 +264,61 @@ static void pci_enable_io(unsigned char bus, l4_uint32_t dev,
 
 #include <stdio.h>
 
 
 #include <stdio.h>
 

-static bool pci_handle_serial_dev(unsigned char bus, l4_uint32_t dev,
-                                  l4_uint32_t subdev, bool scan_only)
+namespace {
+
+struct Resource
+{
+  enum Type { NO_BAR, IO_BAR, MEM_BAR };
+  Type type;
+  unsigned long base;
+  unsigned long len;
+  Resource() : type(NO_BAR) {}
+};
+
+enum { NUM_BARS = 6 };
+
+struct Serial_board
+{
+  int num_ports;
+  int first_bar;
+  bool port_per_bar;
+  Resource bars[NUM_BARS];
+
+  unsigned long get_port(int idx)
+  {
+    if (idx >= num_ports)
+      return 0;
+
+    if (port_per_bar)
+      return bars[first_bar + idx].base;
+
+    return bars[first_bar].base + 8 * idx;
+  }
+};
+
+
+}
+
+static
+int pci_handle_serial_dev(unsigned char bus, l4_uint32_t dev,
+                          l4_uint32_t subdev, bool scan_only,
+                          Serial_board *board)

 {
   bool dev_enabled = false;
 
 {
   bool dev_enabled = false;
 

+

   // read bars
   // read bars

-  for (int bar = 0; bar < 6; ++bar)
+  int num_iobars = 0;
+  int num_membars = 0;
+  int first_port = -1;
+  for (int bar = 0; bar < NUM_BARS; ++bar)

     {
       int a = 0x10 + bar * 4;
 
       unsigned v = pci_read(bus, dev, subdev, a, 32);
       pci_write(bus, dev, subdev, a, ~0U, 32);
       unsigned x = pci_read(bus, dev, subdev, a, 32);
     {
       int a = 0x10 + bar * 4;
 
       unsigned v = pci_read(bus, dev, subdev, a, 32);
       pci_write(bus, dev, subdev, a, ~0U, 32);
       unsigned x = pci_read(bus, dev, subdev, a, 32);

+      pci_write(bus, dev, subdev, a, v, 32);

 
       if (!v)
         continue;
 
       if (!v)
         continue;


@@ -286,6 +328,58 @@ static bool pci_handle_serial_dev(unsigned char bus, l4_uint32_t dev,
         if ((x >> s) & 1)
           break;
 
         if ((x >> s) & 1)
           break;
 

+      board->bars[bar].base = v & ~3UL;
+      board->bars[bar].len = 1 << s;
+      board->bars[bar].type = (v & 1) ? Resource::IO_BAR : Resource::MEM_BAR;
+
+      if (scan_only)
+       printf("BAR%d: %04x (sz=%d)\n", bar, v & ~3, 1 << s);
+
+      switch (board->bars[bar].type)
+       {
+       case Resource::IO_BAR:
+         ++num_iobars;
+         if (first_port == -1)
+           first_port = bar;
+         break;
+       case Resource::MEM_BAR:
+         ++num_membars;
+         break;
+       default:
+         break;
+       }
+    }
+
+  if (num_membars <= 1 && num_iobars == 1)
+    {
+      board->first_bar = first_port;
+      board->num_ports = board->bars[first_port].len / 8;
+      board->port_per_bar = false;
+      pci_enable_io(bus, dev, subdev);
+      return 1;
+    }
+
+
+  board->num_ports = 0;
+  board->first_bar = -1;
+
+  for (int bar = 0; bar < NUM_BARS; ++bar)
+    {
+      if (board->bars[bar].type == Resource::IO_BAR && board->bars[bar].len == 8
+         && (board->first_bar == -1
+             || (board->first_bar + board->num_ports) == bar))
+       {
+         ++board->num_ports;
+         if (board->first_bar == -1)
+           board->first_bar = bar;
+       }
+    }
+
+  board->port_per_bar = true;
+  return board->num_ports;
+
+#if 0
+

       // for now we only take IO-BARs of size 8
       if (v & 1)
         {
       // for now we only take IO-BARs of size 8
       if (v & 1)
         {


@@ -311,10 +405,11 @@ static bool pci_handle_serial_dev(unsigned char bus, l4_uint32_t dev,
         if (scan_only)
           printf("BAR%d: %08x (sz=%d)\n", bar, v & ~0xf, 1 << s);
     }
         if (scan_only)
           printf("BAR%d: %08x (sz=%d)\n", bar, v & ~0xf, 1 << s);
     }

-  return false;
+  return 0;
+#endif

 }
 
 }
 

-unsigned long search_pci_serial_devs(bool scan_only)
+static unsigned long _search_pci_serial_devs(Serial_board *board, bool scan_only)

 {
   l4_umword_t bus, buses, dev;
 
 {
   l4_umword_t bus, buses, dev;
 


@@ -348,7 +443,7 @@ unsigned long search_pci_serial_devs(bool scan_only)
 
               if (classcode == 7 && subclass == 0)
                 if (unsigned long port = pci_handle_serial_dev(bus, dev,
 
               if (classcode == 7 && subclass == 0)
                 if (unsigned long port = pci_handle_serial_dev(bus, dev,

-                                                               subdev, scan_only))
+                                                               subdev, scan_only, board))

                   return port;
             }
         }
                   return port;
             }
         }


@@ -356,6 +451,15 @@ unsigned long search_pci_serial_devs(bool scan_only)
   return 0;
 }
 
   return 0;
 }
 

+unsigned long search_pci_serial_devs(int port_idx, bool scan_only)
+{
+  Serial_board board;
+  if (!_search_pci_serial_devs(&board, scan_only))
+    return 0;
+
+  return board.get_port(port_idx);
+}
+

 namespace {
 
 class Platform_x86 : public Platform_base
 namespace {
 
 class Platform_x86 : public Platform_base

diff --git a/l4/pkg/examples/clntsrv/clntsrv.cfg b/l4/pkg/examples/clntsrv/clntsrv.cfg
index 48959665098936a8b3b6facb9c025e95c4b9cf77..bb2ae50fa56d75c2386ac21cb98ba8eaf3b5e55f 100644 (file)
--- a/l4/pkg/examples/clntsrv/clntsrv.cfg
+++ b/l4/pkg/examples/clntsrv/clntsrv.cfg
@@ -6,23 +6,16 @@ require("L4");
 -- Some shortcut for less typing
 local ld = L4.default_loader;
 
 -- Some shortcut for less typing
 local ld = L4.default_loader;
 

--- Name space for the server program, giving access to the full rom name
--- space. The server will register the name 'calc_server'.
-local ns_clntsrv_server = ld:create_namespace({
-    rom = L4.Env.names:q("rom");
-    calc_server = "";
-  });
+-- Channel for the two programs to talk to each other.
+local calc_server = ld:new_channel();

 
 

--- The server program, using the 'ns_clntsrv_server' name space. Note that
--- the name space is read-write so that the server can register its name.
-ld:start({ ns = ns_clntsrv_server:rw(),
+-- The server program, getting the channel in server mode.
+ld:start({ caps = { calc_server = calc_server:svr() },

            log = { "server", "blue" } },
         "rom/ex_clntsrv-server");
 
            log = { "server", "blue" } },
         "rom/ex_clntsrv-server");
 

--- The client program. The name space is constructed inline and links to the
--- 'calc_server' entry from the server name space so that it is able to find
--- it. The 'rom' name space is automatically added.
--- The client will be started with a green log output.
-ld:start({ ns = { calc_server = ns_clntsrv_server:l("calc_server") },
+-- The client program, getting the 'calc_server' channel to be able to talk
+-- to the server. The client will be started with a green log output.
+ld:start({ caps = { calc_server = calc_server },

            log = { "client", "green" } },
          "rom/ex_clntsrv-client");
            log = { "client", "green" } },
          "rom/ex_clntsrv-client");

diff --git a/l4/pkg/examples/libs/l4re/streammap/client.cc b/l4/pkg/examples/libs/l4re/streammap/client.cc
index 14a993b3c721f77b6669bb0bdef0fa9dc9a11997..40c6439032368898c7204352dbef336f9ab07b7e 100644 (file)
--- a/l4/pkg/examples/libs/l4re/streammap/client.cc
+++ b/l4/pkg/examples/libs/l4re/streammap/client.cc
@@ -48,7 +48,7 @@ int
 main()
 {
 
 main()
 {
 

-  L4::Cap<void> server = L4Re::Env::env()->get_cap<void>("smap_server");
+  L4::Cap<void> server = L4Re::Env::env()->get_cap<void>("smap");

   if (!server.is_valid())
     {
       printf("Could not get capability slot!\n");
   if (!server.is_valid())
     {
       printf("Could not get capability slot!\n");

diff --git a/l4/pkg/examples/libs/l4re/streammap/server.cc b/l4/pkg/examples/libs/l4re/streammap/server.cc
index 646b505368f7a4ece39aa10fd8c8e7938b4cd159..3e5200dcc7d6dda807459a6af7ab41ee210ef731 100644 (file)
--- a/l4/pkg/examples/libs/l4re/streammap/server.cc
+++ b/l4/pkg/examples/libs/l4re/streammap/server.cc
@@ -63,7 +63,7 @@ main()
   static Smap_server smap;
 
   // Register server
   static Smap_server smap;
 
   // Register server

-  if (!server.registry()->register_obj(&smap, "smap_server").is_valid())
+  if (!server.registry()->register_obj(&smap, "smap").is_valid())

     {
       printf("Could not register my service, read-only namespace?\n");
       return 1;
     {
       printf("Could not register my service, read-only namespace?\n");
       return 1;

diff --git a/l4/pkg/examples/libs/l4re/streammap/streammap.cfg b/l4/pkg/examples/libs/l4re/streammap/streammap.cfg
index c9adceffd4bf6962b17be4f1f594d65548f3773c..be224a5be0fff83eb907f5dd29460d6ad2927e11 100644 (file)
--- a/l4/pkg/examples/libs/l4re/streammap/streammap.cfg
+++ b/l4/pkg/examples/libs/l4re/streammap/streammap.cfg
@@ -3,26 +3,19 @@
 -- Include L4 functionality
 require("L4");
 
 -- Include L4 functionality
 require("L4");
 

--- Name space for the server program, giving access to the full 'rom' name
--- space. The server will register the name 'smap_server'.
-local ns_smap_server = L4.default_loader:create_namespace({
-  rom = L4.Env.names:q("rom");
-  smap_server = "placeholder";
-});
+-- Channel for the communication between the server and the client.
+local smap_channel = L4.default_loader:new_channel();

 
 

--- The server program, using the 'ns_smap_server' name space in writable
+-- The server program, using the 'smap' channel in server

 -- mode. The log prefix will be 'server', colored yellow.
 -- mode. The log prefix will be 'server', colored yellow.

-L4.default_loader:start({ ns = ns_smap_server:rw(),
+L4.default_loader:start({ caps = { smap = smap_channel:svr() },

                           log = { "server", "yellow" }},
                         "rom/ex_smap-server");
 
 
 -- The client program.
                           log = { "server", "yellow" }},
                         "rom/ex_smap-server");
 
 
 -- The client program.

--- The name space for the client program is constructed inline and giving
--- access to the full 'rom' name space. The 'smap_server' name points to
--- the name that will be registered in the 'ns_smap_server' name space,
--- i.e. the client is able to find the server.
+-- It is given the 'smap' channel to be able to talk to the server. 

 -- The log prefix will be 'client', colored green.
 -- The log prefix will be 'client', colored green.

-L4.default_loader:start({ ns = { smap_server = ns_smap_server:l("smap_server") },
+L4.default_loader:start({ caps = { smap = smap_channel },

                           log = { "client", "green" } },
                         "rom/ex_smap-client");
                           log = { "client", "green" } },
                         "rom/ex_smap-client");

diff --git a/l4/pkg/examples/sys/vmtest/main.c b/l4/pkg/examples/sys/vmtest/main.c
index 87327f8a407211125021a0e639d2dd19539a3da4..ec102b68e67c64e75f64036d0784666edde34b1d 100644 (file)
--- a/l4/pkg/examples/sys/vmtest/main.c
+++ b/l4/pkg/examples/sys/vmtest/main.c
@@ -28,7 +28,7 @@ static unsigned long vmcb[1024] __attribute__((aligned(4096)));
 static unsigned long idt[32 * 2] __attribute__((aligned(4096)));
 static unsigned long gdt[32 * 2] __attribute__((aligned(4096)));
 
 static unsigned long idt[32 * 2] __attribute__((aligned(4096)));
 static unsigned long gdt[32 * 2] __attribute__((aligned(4096)));
 

-static void init_vmcb(struct l4_vm_svm_vmcb *vmcb_s)
+static void init_vmcb(l4_vm_svm_vmcb_t *vmcb_s)

 {
 
   vmcb_s->control_area.np_enable = 1;
 {
 
   vmcb_s->control_area.np_enable = 1;


@@ -149,8 +149,8 @@ static void run_test(int np_available)
       exit(1);
     }
 
       exit(1);
     }
 

-  struct l4_vm_svm_vmcb *vmcb_s = (struct l4_vm_svm_vmcb *) vmcb;
-  struct l4_vm_svm_gpregs gpregs =
+  l4_vm_svm_vmcb_t *vmcb_s = (l4_vm_svm_vmcb_t *)vmcb;
+  l4_vm_gpregs_t gpregs =

     { .edx = 1,
       .ecx = 2,
       .ebx = 3,
     { .edx = 1,
       .ecx = 2,
       .ebx = 3,


@@ -303,10 +303,13 @@ static void run_test(int np_available)
 
       old_rip = vmcb_s->state_save_area.rip;
 
 
       old_rip = vmcb_s->state_save_area.rip;
 

-      tag = l4_vm_run_svm(vm_task,l4_fpage((unsigned long)vmcb, 12, 0), &gpregs);
+
+      *l4_vm_gpregs() = gpregs;
+      tag = l4_vm_run(vm_task, l4_fpage((unsigned long)vmcb, 12, 0));

       if (l4_error(tag))
        printf("vm-run failed: %s (%ld)\n",
                l4sys_errtostr(l4_error(tag)), l4_error(tag));
       if (l4_error(tag))
        printf("vm-run failed: %s (%ld)\n",
                l4sys_errtostr(l4_error(tag)), l4_error(tag));

+      gpregs = *l4_vm_gpregs();

 
       printf("iteration=%d, exit code=%llx, rip=%llx -> %llx\n",
              i, vmcb_s->control_area.exitcode,
 
       printf("iteration=%d, exit code=%llx, rip=%llx -> %llx\n",
              i, vmcb_s->control_area.exitcode,

diff --git a/l4/pkg/io/server/src/vicu.cc b/l4/pkg/io/server/src/vicu.cc
index 8ce9d4f5457fd734cc6e73e0551ded36a957754b..4a891bf1487d38a3a210b124a3a4097402f70343 100644 (file)
--- a/l4/pkg/io/server/src/vicu.cc
+++ b/l4/pkg/io/server/src/vicu.cc
@@ -155,7 +155,7 @@ Sw_icu::dispatch(l4_umword_t /*obj*/, L4::Ipc_iostream &ios)
   l4_umword_t op, irqn;
   L4::Snd_fpage irqc;
   l4_msgtag_t tag;
   l4_umword_t op, irqn;
   L4::Snd_fpage irqc;
   l4_msgtag_t tag;

-  ios >> tag >> op >> irqn >> irqc;
+  ios >> tag >> op >> irqn;

 
   if (tag.label() != L4_PROTO_IRQ)
     return -L4_EBADPROTO;
 
   if (tag.label() != L4_PROTO_IRQ)
     return -L4_EBADPROTO;


@@ -245,7 +245,7 @@ Sw_icu::Real_irq_pin::unmask()
   if (n & 0x80)
     n = (n - 0x80) | L4::Icu::F_msi;
 
   if (n & 0x80)
     n = (n - 0x80) | L4::Icu::F_msi;
 

-  system_icu()->icu->unmask(n, 0, L4_IPC_NEVER);
+  system_icu()->icu->unmask(n);

   return -L4_EINVAL;
 }
 
   return -L4_EINVAL;
 }
 

diff --git a/l4/pkg/l4sys/include/ARCH-amd64/vm b/l4/pkg/l4sys/include/ARCH-amd64/vm
index b0eadcf977f22fb199fba0481d22a59c3448af0c..50324b8038a5223312d1194f4bb60c5ddacf4d53 100644 (file)
--- a/l4/pkg/l4sys/include/ARCH-amd64/vm
+++ b/l4/pkg/l4sys/include/ARCH-amd64/vm
@@ -22,4 +22,4 @@
  */
 
 #pragma once
  */
 
 #pragma once

-#include <l4/sys/__vm-svm>
+#include <l4/sys/__vm>

diff --git a/l4/pkg/l4sys/include/ARCH-amd64/vm.h b/l4/pkg/l4sys/include/ARCH-amd64/vm.h
index 4d4df5bbb135b4203f257d1b7758f787056d7a5b..a25fa2f405a234d3d2270215473aa84dd6ba8499 100644 (file)
--- a/l4/pkg/l4sys/include/ARCH-amd64/vm.h
+++ b/l4/pkg/l4sys/include/ARCH-amd64/vm.h
@@ -26,11 +26,12 @@
 #include <l4/sys/types.h>
 
 /**
 #include <l4/sys/types.h>
 
 /**

- * \brief General purpose regisers for SVM, x86-64
- * \ingroup l4_vm_svm_api
+ * \brief General purpose regisers, x86-64
+ * \ingroup l4_vm_api

  */
  */

-struct l4_vm_svm_gpregs
+typedef struct l4_vm_gpregs_t

 {
 {

+  l4_umword_t rax;

   l4_umword_t rsi;
   l4_umword_t rdx;
   l4_umword_t rcx;
   l4_umword_t rsi;
   l4_umword_t rdx;
   l4_umword_t rcx;


@@ -49,8 +50,8 @@ struct l4_vm_svm_gpregs
   l4_umword_t dr1;
   l4_umword_t dr2;
   l4_umword_t dr3;
   l4_umword_t dr1;
   l4_umword_t dr2;
   l4_umword_t dr3;

-};
+} l4_vm_gpregs_t;

 
 

-#include <l4/sys/__vm-svm.h>
+#include <l4/sys/__vm.h>

 
 #endif /* ! __INCLUDE__ARCH_X86__VM_H__ */
 
 #endif /* ! __INCLUDE__ARCH_X86__VM_H__ */

diff --git a/l4/pkg/l4sys/include/ARCH-x86/vm b/l4/pkg/l4sys/include/ARCH-x86/vm
index b0eadcf977f22fb199fba0481d22a59c3448af0c..50324b8038a5223312d1194f4bb60c5ddacf4d53 100644 (file)
--- a/l4/pkg/l4sys/include/ARCH-x86/vm
+++ b/l4/pkg/l4sys/include/ARCH-x86/vm
@@ -22,4 +22,4 @@
  */
 
 #pragma once
  */
 
 #pragma once

-#include <l4/sys/__vm-svm>
+#include <l4/sys/__vm>

diff --git a/l4/pkg/l4sys/include/ARCH-x86/vm.h b/l4/pkg/l4sys/include/ARCH-x86/vm.h
index 1419e2376b86576b4c04a4f38cad411d31b56133..1eb8164f61c76dcc608fcb72fa98bc1c439dce98 100644 (file)
--- a/l4/pkg/l4sys/include/ARCH-x86/vm.h
+++ b/l4/pkg/l4sys/include/ARCH-x86/vm.h
@@ -27,11 +27,13 @@
 #include <l4/sys/types.h>
 
 /**
 #include <l4/sys/types.h>
 
 /**

- * \brief General purpose regisers for SVM, x86-32
- * \ingroup l4_vm_svm_api
+ * \brief General purpose regisers, x86-32
+ * \ingroup l4_vm_api

  */
  */

-struct l4_vm_svm_gpregs
+
+typedef struct l4_vm_gpregs_t

 {
 {

+  l4_umword_t eax; // Ignored with SVM

   l4_umword_t edx;
   l4_umword_t ecx;
   l4_umword_t ebx;
   l4_umword_t edx;
   l4_umword_t ecx;
   l4_umword_t ebx;


@@ -42,8 +44,8 @@ struct l4_vm_svm_gpregs
   l4_umword_t dr1;
   l4_umword_t dr2;
   l4_umword_t dr3;
   l4_umword_t dr1;
   l4_umword_t dr2;
   l4_umword_t dr3;

-};
+} l4_vm_gpregs_t;

 
 

-#include <l4/sys/__vm-svm.h>
+#include <l4/sys/__vm.h>

 
 #endif /* ! __INCLUDE__ARCH_X86__VM_H__ */
 
 #endif /* ! __INCLUDE__ARCH_X86__VM_H__ */

diff --git a/l4/pkg/l4sys/include/Makefile b/l4/pkg/l4sys/include/Makefile
index f14f2d4acde8548eef7d3eab8a5aa0e356b02432..996a12b1ec05399b4dfd2b35b13fb844a5f82e13 100644 (file)
--- a/l4/pkg/l4sys/include/Makefile
+++ b/l4/pkg/l4sys/include/Makefile
@@ -4,7 +4,7 @@ L4DIR           ?= $(PKGDIR)/../..
 PKGNAME                = sys
 EXTRA_TARGET   += capability kip task factory irq icu semaphore thread vcon \
                    smart_capability scheduler meta typeinfo_svr ipc_gate \
 PKGNAME                = sys
 EXTRA_TARGET   += capability kip task factory irq icu semaphore thread vcon \
                    smart_capability scheduler meta typeinfo_svr ipc_gate \

-                  __vm-svm ARCH-x86/vm ARCH-amd64/vm ARCH-arm/vm
+                   __vm ARCH-x86/vm ARCH-amd64/vm ARCH-arm/vm

 
 include $(L4DIR)/mk/include.mk
 
 
 include $(L4DIR)/mk/include.mk
 

diff --git a/l4/pkg/l4sys/include/__vm b/l4/pkg/l4sys/include/__vm
new file mode 100644 (file)
index 0000000..fc165e2
--- /dev/null
+++ b/l4/pkg/l4sys/include/__vm
@@ -0,0 +1,61 @@
+// vi:ft=cpp
+/**
+ * \file
+ * \brief X86 virtualization interface
+ */
+/*
+ * (c) 2008-2010 Adam Lackorzynski <adam@os.inf.tu-dresden.de>,
+ *               Alexander Warg <warg@os.inf.tu-dresden.de>
+ *     economic rights: Technische Universität Dresden (Germany)
+ *
+ * This file is part of TUD:OS and distributed under the terms of the
+ * GNU General Public License 2.
+ * Please see the COPYING-GPL-2 file for details.
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ */
+
+#pragma once
+
+#include <l4/sys/vm.h>
+#include <l4/sys/task>
+
+namespace L4 {
+
+/**
+ * \brief Virtual machine.
+ * \ingroup l4_vm_api
+ */
+class Vm : public Kobject_t<Vm, Task, L4_PROTO_VM>
+{
+protected:
+  Vm();
+
+private:
+  Vm(Vm const &);
+  void operator = (Vm const &);
+
+public:
+  /**
+   * \copydoc l4_vm_gpregs()
+   */
+  static l4_vm_gpregs_t *gpregs(l4_utcb_t *u = l4_utcb()) throw()
+  { return l4_vm_gpregs_u(u); }
+
+  /**
+   * \copydoc l4_vm_run()
+   * \note \a dst_task is the implicit \a this pointer.
+   */
+   l4_msgtag_t run(l4_fpage_t const &vmcb_fpage,
+                       l4_utcb_t *utcb = l4_utcb()) throw()
+   { return l4_vm_run_u(cap(), vmcb_fpage, utcb); }
+};
+
+};

diff --git a/l4/pkg/l4sys/include/__vm-svm.h b/l4/pkg/l4sys/include/__vm-svm.h
index 677daa5d45a19361463589f6b9a4445d58b0a735..5cb81da25bd05f5ec07aaa9efa6d49c9525b2692 100644 (file)
--- a/l4/pkg/l4sys/include/__vm-svm.h
+++ b/l4/pkg/l4sys/include/__vm-svm.h
@@ -37,7 +37,7 @@
  * \brief VMCB structure for SVM VMs
  * \ingroup l4_vm_svm_api
  */
  * \brief VMCB structure for SVM VMs
  * \ingroup l4_vm_svm_api
  */

-struct l4_vm_svm_vmcb_control_area
+typedef struct l4_vm_svm_vmcb_control_area

 {
   l4_uint16_t intercept_rd_crX;
   l4_uint16_t intercept_wr_crX;
 {
   l4_uint16_t intercept_rd_crX;
   l4_uint16_t intercept_wr_crX;


@@ -71,25 +71,25 @@ struct l4_vm_svm_vmcb_control_area
   l4_uint64_t lbr_virtualization_enable;
 
   l4_uint8_t _reserved2[832];
   l4_uint64_t lbr_virtualization_enable;
 
   l4_uint8_t _reserved2[832];

-} __attribute__((packed));
+} __attribute__((packed)) l4_vm_svm_vmcb_control_area_t;

 
 /**
  * \brief State save area segment selector struct
  * \ingroup l4_vm_svm_api
  */
 
 /**
  * \brief State save area segment selector struct
  * \ingroup l4_vm_svm_api
  */

-struct l4_vm_svm_vmcb_state_save_area_seg
+typedef struct l4_vm_svm_vmcb_state_save_area_seg

 {
   l4_uint16_t selector;
   l4_uint16_t attrib;
   l4_uint32_t limit;
   l4_uint64_t base;
 {
   l4_uint16_t selector;
   l4_uint16_t attrib;
   l4_uint32_t limit;
   l4_uint64_t base;

-} __attribute__((packed));
+} __attribute__((packed)) l4_vm_svm_vmcb_state_save_area_seg_t;

 
 /**
  * \brief State save area structure for SVM VMs
  * \ingroup l4_vm_svm_api
  */
 
 /**
  * \brief State save area structure for SVM VMs
  * \ingroup l4_vm_svm_api
  */

-struct l4_vm_svm_vmcb_state_save_area
+typedef struct l4_vm_svm_vmcb_state_save_area

 {
   struct l4_vm_svm_vmcb_state_save_area_seg es;
   struct l4_vm_svm_vmcb_state_save_area_seg cs;
 {
   struct l4_vm_svm_vmcb_state_save_area_seg es;
   struct l4_vm_svm_vmcb_state_save_area_seg cs;


@@ -147,80 +147,15 @@ struct l4_vm_svm_vmcb_state_save_area
   l4_uint64_t last_excpto;
 
   l4_uint8_t _reserved6[2408];
   l4_uint64_t last_excpto;
 
   l4_uint8_t _reserved6[2408];

-} __attribute__((packed));
+} __attribute__((packed)) l4_vm_svm_vmcb_state_save_area_t;

 
 
 /**
  * \brief Control structure for SVM VMs
  * \ingroup l4_vm_svm_api
  */
 
 
 /**
  * \brief Control structure for SVM VMs
  * \ingroup l4_vm_svm_api
  */

-struct l4_vm_svm_vmcb
+typedef struct l4_vm_svm_vmcb_t

 {
 {

-  struct l4_vm_svm_vmcb_control_area    control_area;
-  struct l4_vm_svm_vmcb_state_save_area state_save_area;
-};
-
-/**
- * \brief Run a VM
- * \ingroup l4_vm_svm_api
- *
- * \param vm         Capability selector for VM
- * \param vmcb_fpage VMCB
- * \param gpregs     General purpose registers
- *
- * \note SVM only for now
- */
-L4_INLINE l4_msgtag_t
-l4_vm_run_svm(l4_cap_idx_t vm, l4_fpage_t vmcb_fpage,
-              struct l4_vm_svm_gpregs *gpregs) L4_NOTHROW;
-
-/**
- * \internal
- * \ingroup l4_vm_svm_api
- */
-L4_INLINE l4_msgtag_t
-l4_vm_run_svm_u(l4_cap_idx_t vm_task, l4_fpage_t const vmcb_fpage,
-                struct l4_vm_svm_gpregs *gpregs, l4_utcb_t *u) L4_NOTHROW;
-
-
-/**
- * \internal
- * \brief Operations on task objects.
- * \ingroup l4_vm_svm_api
- */
-enum
-{
-  L4_VM_RUN_OP    = L4_TASK_VM_OPS + 0    /* Run a VM */
-};
-
-
-/****** Implementations ****************/
-
-L4_INLINE l4_msgtag_t
-l4_vm_run_svm_u(l4_cap_idx_t vm_task, l4_fpage_t const vmcb_fpage,
-                struct l4_vm_svm_gpregs *gpregs, l4_utcb_t *u) L4_NOTHROW
-{
-  l4_msgtag_t tag;
-  l4_msg_regs_t *v = l4_utcb_mr_u(u);
-  enum { GPREGS_WORDS = sizeof(*gpregs) / sizeof(l4_umword_t), };
-  v->mr[0]  = L4_VM_RUN_OP;
-
-  __builtin_memcpy(&v->mr[1], gpregs, sizeof(*gpregs));
-  v->mr[1 + GPREGS_WORDS] = l4_map_control(0, 0, 0);
-  v->mr[2 + GPREGS_WORDS] = vmcb_fpage.raw;
-
-  tag = l4_ipc_call(vm_task, u,
-                    l4_msgtag(L4_PROTO_TASK, 1 + GPREGS_WORDS, 1, 0),
-                    L4_IPC_NEVER);
-
-  __builtin_memcpy(gpregs, &v->mr[1], sizeof(*gpregs));
-
-  return tag;
-}
-
-L4_INLINE l4_msgtag_t
-l4_vm_run_svm(l4_cap_idx_t task, l4_fpage_t vmcb_fpage,
-              struct l4_vm_svm_gpregs *gpregs) L4_NOTHROW
-{
-  return l4_vm_run_svm_u(task, vmcb_fpage, gpregs, l4_utcb());
-}
+  l4_vm_svm_vmcb_control_area_t    control_area;
+  l4_vm_svm_vmcb_state_save_area_t state_save_area;
+} l4_vm_svm_vmcb_t;

diff --git a/l4/pkg/l4sys/include/__vm-vmx.h b/l4/pkg/l4sys/include/__vm-vmx.h
new file mode 100644 (file)
index 0000000..0358bfa
--- /dev/null
+++ b/l4/pkg/l4sys/include/__vm-vmx.h
@@ -0,0 +1,73 @@
+/**
+ * \internal
+ * \file
+ * \brief X86 virtualization interface.
+ */
+/*
+ * (c) 2010 Adam Lackorzynski <adam@os.inf.tu-dresden.de>,
+ *          Alexander Warg <warg@os.inf.tu-dresden.de>
+ *     economic rights: Technische Universität Dresden (Germany)
+ *
+ * This file is part of TUD:OS and distributed under the terms of the
+ * GNU General Public License 2.
+ * Please see the COPYING-GPL-2 file for details.
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ */
+#pragma once
+
+/**
+ * \defgroup l4_vm_vmx_api VM API for VMX
+ * \brief Virtual machine API for VMX.
+ * \ingroup l4_vm_api
+ */
+
+
+/**
+ * \brief Additional VMCS fields.
+ * \ingroup l4_vm_vmx_api
+ */
+enum
+{
+  L4_VM_VMX_VMCS_CR2              = 0x6830,
+};
+
+/**
+ * \brief Return length in bytes of a VMCS field.
+ * \ingroup l4_vm_vmx_api
+ *
+ * \param field  Field number.
+ * \return Width of field in bytes.
+ */
+L4_INLINE
+unsigned
+l4_vm_vmx_field_len(unsigned field)
+{
+  static const char widths[4] = { 2, 8, 4, sizeof(l4_umword_t) };
+  return widths[field >> 13];
+}
+
+/**
+ * \brief Get pointer into VMCS.
+ * \ingroup l4_vm_vmx_api
+ *
+ * \param vmcs   Pointer to VMCS buffer.
+ * \param field  Field number.
+ *
+ * \param Pointer to field in the VMCS.
+ */
+L4_INLINE
+void *
+l4_vm_vmx_field_ptr(void *vmcs, unsigned field)
+{
+  return (void *)((char *)vmcs
+                          + ((field >> 13) * 4 + ((field >> 10) & 3) + 1) * 0x80
+                          + l4_vm_vmx_field_len(field) * ((field >> 1) & 0xff));
+}

diff --git a/l4/pkg/l4sys/include/__vm.h b/l4/pkg/l4sys/include/__vm.h
new file mode 100644 (file)
index 0000000..b67f406
--- /dev/null
+++ b/l4/pkg/l4sys/include/__vm.h
@@ -0,0 +1,129 @@
+/**
+ * \internal
+ * \file
+ * \brief X86 virtualization interface.
+ */
+/*
+ * (c) 2008-2010 Adam Lackorzynski <adam@os.inf.tu-dresden.de>,
+ *               Alexander Warg <warg@os.inf.tu-dresden.de>
+ *     economic rights: Technische Universität Dresden (Germany)
+ *
+ * This file is part of TUD:OS and distributed under the terms of the
+ * GNU General Public License 2.
+ * Please see the COPYING-GPL-2 file for details.
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ */
+#pragma once
+
+#include <l4/sys/__vm-svm.h>
+#include <l4/sys/__vm-vmx.h>
+
+/**
+ * \group Return location where to store GP-regs.
+ * \ingroup l4_vm_api
+ *
+ * \return Location of GP-regs.
+ * \see l4_vm_run
+ *
+ * Note that the function returns a location within the UTCB, i.e. between
+ * calling this function and l4_vm_run() the UTCB must not be used.
+ */
+L4_INLINE
+l4_vm_gpregs_t *
+l4_vm_gpregs(void) L4_NOTHROW;
+
+/**
+ * \internal
+ * \ingroup l4_vm_api
+ */
+L4_INLINE
+l4_vm_gpregs_t *
+l4_vm_gpregs_u(l4_utcb_t *u) L4_NOTHROW;
+
+/**
+ * \brief Run a VM
+ * \ingroup l4_vm_api
+ *
+ * \param vm         Capability selector for VM
+ * \param vmcb_fpage VMCB
+ * \param gpregs     General purpose registers
+ *
+ * The general purpose registers are stored in the UTCB before calling this
+ * function with the function l4_vm_gpregs().
+ */
+L4_INLINE l4_msgtag_t
+l4_vm_run(l4_cap_idx_t vm, l4_fpage_t vmcx_fpage) L4_NOTHROW;
+
+/**
+ * \internal
+ * \ingroup l4_vm_api
+ */
+L4_INLINE l4_msgtag_t
+l4_vm_run_u(l4_cap_idx_t vm_task, l4_fpage_t const vmcb_fpage,
+            l4_utcb_t *u) L4_NOTHROW;
+
+
+/**
+ * \internal
+ * \brief Operations on task objects.
+ * \ingroup l4_vm_api
+ */
+enum
+{
+  L4_VM_RUN_OP    = L4_TASK_VM_OPS + 0    /* Run a VM */
+};
+
+
+/****** Implementations ****************/
+
+L4_INLINE
+l4_vm_gpregs_t *
+l4_vm_gpregs_u(l4_utcb_t *u) L4_NOTHROW
+{
+  union cast
+  {
+    l4_vm_gpregs_t r;
+    l4_umword_t a[sizeof(l4_vm_gpregs_t) / sizeof(l4_umword_t)];
+  };
+  return &((union cast *)&l4_utcb_mr_u(u)->mr[1])->r;
+}
+
+L4_INLINE l4_msgtag_t
+l4_vm_run_u(l4_cap_idx_t vm_task, l4_fpage_t const vmcx_fpage,
+            l4_utcb_t *u) L4_NOTHROW
+{
+  l4_msgtag_t tag;
+  l4_msg_regs_t *v = l4_utcb_mr_u(u);
+  enum { GPREGS_WORDS = sizeof(l4_vm_gpregs_t) / sizeof(l4_umword_t) };
+  v->mr[0]  = L4_VM_RUN_OP;
+
+  v->mr[1 + GPREGS_WORDS] = l4_map_control(0, 0, 0);
+  v->mr[2 + GPREGS_WORDS] = vmcx_fpage.raw;
+
+  tag = l4_ipc_call(vm_task, u,
+                    l4_msgtag(L4_PROTO_TASK, 1 + GPREGS_WORDS, 1, 0),
+                    L4_IPC_NEVER);
+
+  return tag;
+}
+
+L4_INLINE
+l4_vm_gpregs_t *
+l4_vm_gpregs(void) L4_NOTHROW
+{
+  return l4_vm_gpregs_u(l4_utcb());
+}
+
+L4_INLINE l4_msgtag_t
+l4_vm_run(l4_cap_idx_t task, l4_fpage_t vmcx_fpage) L4_NOTHROW
+{
+  return l4_vm_run_u(task, vmcx_fpage, l4_utcb());
+}

diff --git a/l4/pkg/l4sys/include/icu.h b/l4/pkg/l4sys/include/icu.h
index 2b3f4e1176026b7d85ab4ce396616a608553607b..907feb5dfa7a626dcbd89c1ea51a83ce7d206701 100644 (file)
--- a/l4/pkg/l4sys/include/icu.h
+++ b/l4/pkg/l4sys/include/icu.h
@@ -183,6 +183,17 @@ L4_INLINE l4_msgtag_t
 l4_icu_unbind_u(l4_cap_idx_t icu, unsigned irqnum, l4_cap_idx_t irq,
                 l4_utcb_t *utcb) L4_NOTHROW;
 
 l4_icu_unbind_u(l4_cap_idx_t icu, unsigned irqnum, l4_cap_idx_t irq,
                 l4_utcb_t *utcb) L4_NOTHROW;
 

+/**
+ * \brief Set mode of interrupt.
+ * \ingroup l4_icu_api
+ *
+ * \param  icu     ICU to use.
+ * \param  irqnum  IRQ vector at the ICU.
+ * \param  mode    Mode, see L4_irq_flow_type.
+ * \return Syscall return tag
+ *
+ * \ingroup l4_icu_api
+ */

 L4_INLINE l4_msgtag_t
 l4_icu_set_mode(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t mode) L4_NOTHROW;
 
 L4_INLINE l4_msgtag_t
 l4_icu_set_mode(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t mode) L4_NOTHROW;
 


@@ -232,14 +243,48 @@ l4_icu_msi_info_u(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *msg,
                   l4_utcb_t *utcb) L4_NOTHROW;
 
 
                   l4_utcb_t *utcb) L4_NOTHROW;
 
 

+/**
+ * \brief Unmask an IRQ vector.
+ * \ingroup l4_icu_api
+ *
+ * \param icu    ICU to use.
+ * \param irqnum IRQ vector at the ICU.
+ * \param label  If non-NULL the function also waits for the next message.
+ * \param to     Timeout for message to ICU, if unsure use L4_IPC_NEVER.
+ * \return Syscall return tag
+ */

 L4_INLINE l4_msgtag_t
 l4_icu_unmask(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
               l4_timeout_t to) L4_NOTHROW;
 
 L4_INLINE l4_msgtag_t
 l4_icu_unmask(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
               l4_timeout_t to) L4_NOTHROW;
 

+/**
+ * \internal
+ */
+L4_INLINE l4_msgtag_t
+l4_icu_unmask_u(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
+                l4_timeout_t to, l4_utcb_t *utcb) L4_NOTHROW;
+
+/**
+ * \brief Mask an IRQ vector.
+ * \ingroup l4_icu_api
+ *
+ * \param icu    ICU to use.
+ * \param irqnum IRQ vector at the ICU.
+ * \param label  If non-NULL the function also waits for the next message.
+ * \param to     Timeout for message to ICU, if unsure use L4_IPC_NEVER.
+ * \return Syscall return tag
+ */

 L4_INLINE l4_msgtag_t
 l4_icu_mask(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
             l4_timeout_t to) L4_NOTHROW;
 
 L4_INLINE l4_msgtag_t
 l4_icu_mask(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
             l4_timeout_t to) L4_NOTHROW;
 

+/**
+ * \internal
+ */
+L4_INLINE l4_msgtag_t
+l4_icu_mask_u(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
+              l4_timeout_t to, l4_utcb_t *utcb) L4_NOTHROW;
+

 /**
  * \internal
  */
 /**
  * \internal
  */


@@ -310,6 +355,43 @@ l4_icu_msi_info_u(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *msg,
   return res;
 }
 
   return res;
 }
 

+L4_INLINE l4_msgtag_t
+l4_icu_set_mode_u(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t mode,
+                  l4_utcb_t *utcb) L4_NOTHROW
+{
+  l4_msg_regs_t *mr = l4_utcb_mr_u(utcb);
+  mr->mr[0] = L4_ICU_OP_SET_MODE;
+  mr->mr[1] = irqnum;
+  mr->mr[2] = mode;
+  return l4_ipc_call(icu, utcb, l4_msgtag(L4_PROTO_IRQ, 3, 0, 0), L4_IPC_NEVER);
+}
+
+L4_INLINE l4_msgtag_t
+l4_icu_control_u(l4_cap_idx_t icu, unsigned irqnum, unsigned op,
+                 l4_umword_t *label, l4_timeout_t to,
+                 l4_utcb_t *utcb) L4_NOTHROW
+{
+  l4_msg_regs_t *m = l4_utcb_mr_u(utcb);
+  m->mr[0] = L4_ICU_OP_UNMASK + op;
+  m->mr[1] = irqnum;
+  if (label)
+    return l4_ipc_send_and_wait(icu, utcb, l4_msgtag(L4_PROTO_IRQ, 2, 0, 0),
+                                label, to);
+  else
+    return l4_ipc_send(icu, utcb, l4_msgtag(L4_PROTO_IRQ, 2, 0, 0), to);
+}
+
+L4_INLINE l4_msgtag_t
+l4_icu_mask_u(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
+              l4_timeout_t to, l4_utcb_t *utcb) L4_NOTHROW
+{ return l4_icu_control_u(icu, irqnum, L4_ICU_CTL_MASK, label, to, utcb); }
+
+L4_INLINE l4_msgtag_t
+l4_icu_unmask_u(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
+                l4_timeout_t to, l4_utcb_t *utcb) L4_NOTHROW
+{ return l4_icu_control_u(icu, irqnum, L4_ICU_CTL_UNMASK, label, to, utcb); }
+
+

 
 
 L4_INLINE l4_msgtag_t
 
 
 L4_INLINE l4_msgtag_t


@@ -328,24 +410,6 @@ L4_INLINE l4_msgtag_t
 l4_icu_msi_info(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *msg) L4_NOTHROW
 { return l4_icu_msi_info_u(icu, irqnum, msg, l4_utcb()); }
 
 l4_icu_msi_info(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *msg) L4_NOTHROW
 { return l4_icu_msi_info_u(icu, irqnum, msg, l4_utcb()); }
 

-/**
- * \internal
- */
-L4_INLINE l4_msgtag_t
-l4_icu_control_u(l4_cap_idx_t icu, unsigned irqnum, unsigned op,
-                 l4_umword_t *label, l4_timeout_t to,
-                 l4_utcb_t *utcb) L4_NOTHROW
-{
-  l4_msg_regs_t *m = l4_utcb_mr_u(utcb);
-  m->mr[0] = L4_ICU_OP_UNMASK + op;
-  m->mr[1] = irqnum;
-  if (label)
-    return l4_ipc_send_and_wait(icu, utcb, l4_msgtag(L4_PROTO_IRQ, 2, 0, 0),
-                                label, to);
-  else
-    return l4_ipc_send(icu, utcb, l4_msgtag(L4_PROTO_IRQ, 2, 0, 0), to);
-}
-

 L4_INLINE l4_msgtag_t
 l4_icu_unmask(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
               l4_timeout_t to) L4_NOTHROW
 L4_INLINE l4_msgtag_t
 l4_icu_unmask(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
               l4_timeout_t to) L4_NOTHROW


@@ -356,20 +420,8 @@ l4_icu_mask(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t *label,
             l4_timeout_t to) L4_NOTHROW
 { return l4_icu_control_u(icu, irqnum, L4_ICU_CTL_MASK, label, to, l4_utcb()); }
 
             l4_timeout_t to) L4_NOTHROW
 { return l4_icu_control_u(icu, irqnum, L4_ICU_CTL_MASK, label, to, l4_utcb()); }
 

-L4_INLINE l4_msgtag_t
-l4_icu_set_mode_u(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t mode,
-                  l4_utcb_t *utcb) L4_NOTHROW
-{
-  l4_msg_regs_t *mr = l4_utcb_mr_u(utcb);
-  mr->mr[0] = L4_ICU_OP_SET_MODE;
-  mr->mr[1] = irqnum;
-  mr->mr[2] = mode;
-  return l4_ipc_call(icu, utcb, l4_msgtag(L4_PROTO_IRQ, 3, 0, 0), L4_IPC_NEVER);
-}
-

 L4_INLINE l4_msgtag_t
 l4_icu_set_mode(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t mode) L4_NOTHROW
 {
   return l4_icu_set_mode_u(icu, irqnum, mode, l4_utcb());
 }
 L4_INLINE l4_msgtag_t
 l4_icu_set_mode(l4_cap_idx_t icu, unsigned irqnum, l4_umword_t mode) L4_NOTHROW
 {
   return l4_icu_set_mode_u(icu, irqnum, mode, l4_utcb());
 }

-

diff --git a/l4/pkg/l4sys/include/ipc.h b/l4/pkg/l4sys/include/ipc.h
index aeb17d156af6a743ec4cf50ae6c355534a95a78e..a8bed1bbc7891e7312b131d051fb89f376f382ac 100644 (file)
--- a/l4/pkg/l4sys/include/ipc.h
+++ b/l4/pkg/l4sys/include/ipc.h
@@ -121,18 +121,12 @@ enum l4_ipc_tcr_error_t
   L4_IPC_SEABORTED        = 0x0e, /**< Send operation aborted.
                                    **  \ingroup l4_ipc_api
                                    **/
   L4_IPC_SEABORTED        = 0x0e, /**< Send operation aborted.
                                    **  \ingroup l4_ipc_api
                                    **/

-  L4_IPC_REMSGCUT         = 0x09, /**< Cut receive message. (due to
-                                   **  (a) message buffer is too small,
-                                   **  (b) not enough strings are accepted,
-                                   **  (c) at least one string buffer is too
-                                   **      small)
+  L4_IPC_REMSGCUT         = 0x09, /**< Cut receive message, due to
+                                   **  message buffer is too small.

                                    **  \ingroup l4_ipc_api
                                    **/
                                    **  \ingroup l4_ipc_api
                                    **/

-  L4_IPC_SEMSGCUT         = 0x08, /**< Cut send message. (due to
-                                   **  (a) message buffer is too small,
-                                   **  (b) not enough strings are accepted,
-                                   **  (c) at least one string buffer is too
-                                   **      small)
+  L4_IPC_SEMSGCUT         = 0x08, /**< Cut send message. due to
+                                   **  message buffer is too small,

                                    **  \ingroup l4_ipc_api
                                    **/
 };
                                    **  \ingroup l4_ipc_api
                                    **/
 };

diff --git a/l4/pkg/l4sys/include/irq b/l4/pkg/l4sys/include/irq
index d18997a91d9df868a5b88f07b51b1ef94e46c24d..5ca2c5dd95446408fa4e50664f05734965e1ed7f 100644 (file)
--- a/l4/pkg/l4sys/include/irq
+++ b/l4/pkg/l4sys/include/irq
@@ -186,14 +186,37 @@ public:
                        l4_utcb_t *utcb = l4_utcb()) throw()
   { return l4_icu_msi_info_u(cap(), irqnum, msg, utcb); }
 
                        l4_utcb_t *utcb = l4_utcb()) throw()
   { return l4_icu_msi_info_u(cap(), irqnum, msg, utcb); }
 

+  /**
+   * \internal
+   */

   l4_msgtag_t control(unsigned irqnum, unsigned op, l4_umword_t *label,
                       l4_timeout_t to, l4_utcb_t *utcb = l4_utcb()) throw()
   { return l4_icu_control_u(cap(), irqnum, op, label, to, utcb); }
 
   l4_msgtag_t control(unsigned irqnum, unsigned op, l4_umword_t *label,
                       l4_timeout_t to, l4_utcb_t *utcb = l4_utcb()) throw()
   { return l4_icu_control_u(cap(), irqnum, op, label, to, utcb); }
 

-  l4_msgtag_t mask(unsigned irqnum, l4_umword_t *label, l4_timeout_t to,
+  /**
+   * \copydoc l4_icu_mask()
+   * \note \a the icu argument is the implicit \a this pointer.
+   */
+  l4_msgtag_t mask(unsigned irqnum,
+                   l4_umword_t *label = 0,
+                   l4_timeout_t to = L4_IPC_NEVER,

                    l4_utcb_t *utcb = l4_utcb()) throw()
                    l4_utcb_t *utcb = l4_utcb()) throw()

-  { return l4_icu_control_u(cap(), irqnum, L4_ICU_CTL_MASK, label, to, utcb); }
+  { return l4_icu_mask_u(cap(), irqnum, label, to, utcb); }

 
 

+  /**
+   * \copydoc l4_icu_unmask()
+   * \note \a the icu argument is the implicit \a this pointer.
+   */
+  l4_msgtag_t unmask(unsigned irqnum,
+                     l4_umword_t *label = 0,
+                     l4_timeout_t to = L4_IPC_NEVER,
+                     l4_utcb_t *utcb = l4_utcb()) throw()
+  { return l4_icu_unmask_u(cap(), irqnum, label, to, utcb); }
+
+  /**
+   * \copydoc l4_icu_set_mode()
+   * \note \a the icu argument is the implicit \a this pointer.
+   */

   l4_msgtag_t set_mode(unsigned irqnum, l4_umword_t mode,
                        l4_utcb_t *utcb = l4_utcb()) throw()
   { return l4_icu_set_mode_u(cap(), irqnum, mode, utcb); }
   l4_msgtag_t set_mode(unsigned irqnum, l4_umword_t mode,
                        l4_utcb_t *utcb = l4_utcb()) throw()
   { return l4_icu_set_mode_u(cap(), irqnum, mode, utcb); }

diff --git a/l4/pkg/l4sys/include/irq.h b/l4/pkg/l4sys/include/irq.h
index 418ede63a684d6746968fcd211108d5275dae11a..acefab980fcb3d57f2d32546be630ebee8097fb6 100644 (file)
--- a/l4/pkg/l4sys/include/irq.h
+++ b/l4/pkg/l4sys/include/irq.h
@@ -47,15 +47,6 @@
  *
  */
 
  *
  */
 

-
-enum L4_irq_op
-{
-  L4_IRQ_OP_ATTACH    = 1,
-  L4_IRQ_OP_TRIGGER   = 2,
-  L4_IRQ_OP_CHAIN     = 3,
-  L4_IRQ_OP_EOI       = 4,
-};
-

 /**
  * \brief Attach to an interrupt source.
  * \ingroup l4_irq_api
 /**
  * \brief Attach to an interrupt source.
  * \ingroup l4_irq_api


@@ -204,6 +195,17 @@ l4_irq_unmask(l4_cap_idx_t irq) L4_NOTHROW;
 L4_INLINE l4_msgtag_t
 l4_irq_unmask_u(l4_cap_idx_t irq, l4_utcb_t *utcb) L4_NOTHROW;
 
 L4_INLINE l4_msgtag_t
 l4_irq_unmask_u(l4_cap_idx_t irq, l4_utcb_t *utcb) L4_NOTHROW;
 

+/**
+ * \internal
+ */
+enum L4_irq_op
+{
+  L4_IRQ_OP_ATTACH    = 1,
+  L4_IRQ_OP_TRIGGER   = 2,
+  L4_IRQ_OP_CHAIN     = 3,
+  L4_IRQ_OP_EOI       = 4,
+};
+

 /**************************************************************************
  * Implementations
  */
 /**************************************************************************
  * Implementations
  */

diff --git a/l4/pkg/l4sys/include/scheduler.h b/l4/pkg/l4sys/include/scheduler.h
index d0e6502d2e3e708494d852b2487ade60cb664171..e2384776d1ec095b7b8de584e1feecafdf409638 100644 (file)
--- a/l4/pkg/l4sys/include/scheduler.h
+++ b/l4/pkg/l4sys/include/scheduler.h
@@ -194,7 +194,7 @@ l4_scheduler_is_online_u(l4_cap_idx_t scheduler, l4_umword_t cpu,
  * \hideinitializer
  * \internal
  */
  * \hideinitializer
  * \internal
  */

-enum L4_cpu_ops
+enum L4_scheduler_ops

 {
   L4_SCHEDULER_INFO_OP       = 0UL, /**< Query infos about the scheduler */
   L4_SCHEDULER_RUN_THREAD_OP = 1UL, /**< Run a thread on this scheduler */
 {
   L4_SCHEDULER_INFO_OP       = 0UL, /**< Query infos about the scheduler */
   L4_SCHEDULER_RUN_THREAD_OP = 1UL, /**< Run a thread on this scheduler */

diff --git a/l4/pkg/libpng/include/l4png_wrap.h b/l4/pkg/libpng/include/l4png_wrap.h
index db620a56fa94d2feae82ab7ff66928530ca87390..45320cfad6956aaf6803d1a33c71f3ef34d1c868 100644 (file)
--- a/l4/pkg/libpng/include/l4png_wrap.h
+++ b/l4/pkg/libpng/include/l4png_wrap.h
@@ -1,6 +1,10 @@
 #ifndef __L4PNG_WRAP_H__
 #define __L4PNG_WRAP_H__
 
 #ifndef __L4PNG_WRAP_H__
 #define __L4PNG_WRAP_H__
 

+#include <sys/cdefs.h>
+
+__BEGIN_DECLS
+

 #define ARGB_BUF_TO_SMALL -2
 #define ENOPNG -3;
 #define EDAMAGEDPNG -4;
 #define ARGB_BUF_TO_SMALL -2
 #define ENOPNG -3;
 #define EDAMAGEDPNG -4;


@@ -24,4 +28,6 @@ int png_convert_RGB16bit_file(const char *filename, void *argb_buf,
                              unsigned argb_max_size,
                              int line_offset);
 
                              unsigned argb_max_size,
                              int line_offset);
 

+__END_DECLS
+

 #endif /* ! __L4PNG_WRAP_H__ */
 #endif /* ! __L4PNG_WRAP_H__ */

diff --git a/l4/pkg/ned/doc/tutorial.lua b/l4/pkg/ned/doc/tutorial.lua
index 22edefab9b825d26d4e356f0b5755feba38829cc..5962e579ba14fe323a29b47d97d55059ca3118d6 100644 (file)
--- a/l4/pkg/ned/doc/tutorial.lua
+++ b/l4/pkg/ned/doc/tutorial.lua
@@ -4,12 +4,11 @@ Tutorial lua script for Ned
 ===========================
 
 Firstly we have a set of definitions available. Some come from 'ned.lua'
 ===========================
 
 Firstly we have a set of definitions available. Some come from 'ned.lua'

-and others from the C++ bindings within Ned. The whole L4 stuff is in the
-lua module "L4" (use require("L4")).
-The L4 module classes and functions to cope with L4 capabilities and
-their invocation.  A set of constants and access to the L4Re environment of
-the running program.  And a set of classes to start L4 applications and
-composing their name spaces.
+embedded script and others from the C++ bindings within Ned. The whole L4
+functionality is in the lua module "L4" (use require("L4")).
+The L4 module classes and functions cope with L4 capabilities and
+their invocations, provice a set of constants and access to the L4Re environment of
+the running program.  Finally, of course it can also start L4 applications.

 
 L4 Capabilities
 ===============
 
 L4 Capabilities
 ===============


@@ -25,9 +24,9 @@ L4.cast(type, cap)
 Returns a cap transformed to a capability of the given type, whereas type
 is either the fully qualified C++ name of the class encapsulating the object
 or the L4 protocol ID assigned to all L4Re and L4 system objects.
 Returns a cap transformed to a capability of the given type, whereas type
 is either the fully qualified C++ name of the class encapsulating the object
 or the L4 protocol ID assigned to all L4Re and L4 system objects.

-If the type is unknown than nil is returned.
+If the type is unknown then nil is returned.

 
 

-Generic capabilities provide the methods:
+Generic capabilities provide the following methods:

 
 is_valid()
 
 
 is_valid()
 


@@ -109,12 +108,18 @@ L4 and L4Re objects.
   Log
   Scheduler
 
   Log
   Scheduler
 

+The L4.Info table contains the following functions:
+
+  Kip.str()   The banner string found in the kernel info page
+  arch()      Architecture name, such as: x86, amd64, arm, ppc32
+  platform()  Platform name, such as: pc, ux, realview, beagleboard
+

 
 Support for starting L4 programs
 ================================
 
 The L4 module defines two classes that are useful for starting l4 applications.
 
 Support for starting L4 programs
 ================================
 
 The L4 module defines two classes that are useful for starting l4 applications.

-The class L4.Loader that encapsulates a fairly high level policy for
+The class L4.Loader that encapsulates a fairly high level policy

 that is useful for starting a whole set of processes. And the class L4.App_env
 that encapsulates a more fine-grained policy.
 
 that is useful for starting a whole set of processes. And the class L4.App_env
 that encapsulates a more fine-grained policy.
 


@@ -122,16 +127,16 @@ L4.Loader
 ---------
 
 The class L4.Loader encapsulates the policy for starting programs with the
 ---------
 
 The class L4.Loader encapsulates the policy for starting programs with the

-basic building blocks for the application comming from a dedicated loader,
-such as Moe or a Loader instance.  These building blocks are a region map (Rm),
-a name space, a scheduler, a memory allocator, and a logging facility.
+basic building blocks for the application coming from a dedicated loader,
+such as Moe or a Loader instance. These building blocks are a region map (Rm),
+a scheduler, a memory allocator, and a logging facility.

 A L4.Loader object is typically used to start multiple applications. There
 is a L4.default_loader instance of L4.Loader that uses the L4.Env.mem_alloc
 factory of the current Ned instance to create the objects for a new program.
 However you may also use a more restricted factory for applications and
 A L4.Loader object is typically used to start multiple applications. There
 is a L4.default_loader instance of L4.Loader that uses the L4.Env.mem_alloc
 factory of the current Ned instance to create the objects for a new program.
 However you may also use a more restricted factory for applications and

-instanciate a loader for them.  The L4.Loader objects can already be used
-to start a program with L4.Loader:start(app_spec, cmd, ...).  Where app_spec
-is a table containing some parameters for the new application. cmd is the
+instantiate a loader for them.  The L4.Loader objects can already be used
+to start a program with L4.Loader:start(app_spec, cmd, ...). Where app_spec
+is a table containing parameters for the new application. cmd is the

 command to run and the remaining arguments are the command-line options for
 the application.
 
 command to run and the remaining arguments are the command-line options for
 the application.
 


@@ -142,33 +147,54 @@ L4.default_loader:start({}, "rom/hello");
 local _doc = [==[
 
 This statement does the following:
 local _doc = [==[
 
 This statement does the following:

- 1. create a new name space for the application
- 2. put L4.Env.names:query("rom") into the new name space (thus shares Ned's
-    'rom' directory with the new program.
+ 1. Create a new environment for the application
+ 2. Add the rom name-space into the new environment (thus shares Ned's
+    'rom' directory with the new program).

  3. Creates all the building blocks for the new process and starts the
     'l4re' support kernel in the new process which in turn start's 'rom/hello'
     in the new process.
 
 Using the app_spec parameter you can modify the behavior in two ways. There are
  3. Creates all the building blocks for the new process and starts the
     'l4re' support kernel in the new process which in turn start's 'rom/hello'
     in the new process.
 
 Using the app_spec parameter you can modify the behavior in two ways. There are

-two supported options 'ns' for providing a more usefull non-empty name space
-for the application. And 'log' for modifying the logger tag and color.
+two supported options 'caps' for providing more capabilities for the
+application. And 'log' for modifying the logger tag and color.

 
 ]==]
 
 
 ]==]
 

-local my_ns = {
-  fb = L4.Env.names:query("vesa");
+local my_caps = {
+  fb = L4.Env.vesa;

 };
 
 };
 

-L4.default_loader:start({ns = my_ns, log = {"APP", "blue"}}, "rom/hello");
+L4.default_loader:start({caps = my_caps, log = {"APP", "blue"}}, "rom/hello");

 
 local _doc = [==[
 
 
 local _doc = [==[
 

-This snippet creates a name-space template (my_ns) and uses it for the
+This snippet creates a caps template (my_caps) and uses it for the

 new process and also sets user-defined log tags.  The L4.Loader:start method,
 new process and also sets user-defined log tags.  The L4.Loader:start method,

-however, automatically adds the 'rom' directory to the name space if not
-already specified in the template.
+however, automatically adds the 'rom' directory to the caps environment if
+not already specified in the template.
+
+Environment variables may be given as a table in the third argument to
+start. Argument to the program are given space separated after the program
+name within a single string.
+
+]==]
+
+L4.default_loader:start({}, "rom/program arg1 " .. arg2, { LD_DEBUG = 1 });
+
+local _doc = [==[
+
+L4.default_loader:startv is a variant of the start function that takes the
+arguments of the program as a single argument each. If the last argument to
+startv is a table it is interpreted as environment variables for the program.
+The above example would translate to:
+
+]==]
+
+L4.default_loader:startv({}, "rom/program", "arg1", arg2, { LD_DEBUG = 1 });
+
+local _doc = [==[

 
 

-To use create a new L4.Loader instance you may use a generic factory for all
+To create a new L4.Loader instance you may use a generic factory for all

 building blocks or set individual factories.
 
 ]==]
 building blocks or set individual factories.
 
 ]==]

diff --git a/l4/pkg/sqlite/lib/README b/l4/pkg/sqlite/lib/README
index 1df330bba292d87a33333e3a79483fa0c8240050..6922e2302abacd62aaa6c2e1ecf8a55744393d94 100644 (file)
--- a/l4/pkg/sqlite/lib/README
+++ b/l4/pkg/sqlite/lib/README
@@ -1,4 +1,4 @@
 
 
 The contrib directory contains the unmodified contents of
 
 
 The contrib directory contains the unmodified contents of

-sqlite-amalgamation-3.7.0.1.tar.gz
+sqlite-amalgamation-3.7.2.tar.gz

diff --git a/l4/pkg/sqlite/lib/contrib/configure b/l4/pkg/sqlite/lib/contrib/configure
index 809d5730302dd8db0dca60e34cb932bf62e7afdd..2a168eccbef4aa6f95c9c136757e0b11a07ea2cf 100755 (executable)
--- a/l4/pkg/sqlite/lib/contrib/configure
+++ b/l4/pkg/sqlite/lib/contrib/configure
@@ -1,6 +1,6 @@
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.

-# Generated by GNU Autoconf 2.62 for sqlite 3.7.0.1.
+# Generated by GNU Autoconf 2.62 for sqlite 3.7.2.

 #
 # Report bugs to <http://www.sqlite.org>.
 #
 #
 # Report bugs to <http://www.sqlite.org>.
 #


@@ -750,8 +750,8 @@ SHELL=${CONFIG_SHELL-/bin/sh}
 # Identity of this package.
 PACKAGE_NAME='sqlite'
 PACKAGE_TARNAME='sqlite'
 # Identity of this package.
 PACKAGE_NAME='sqlite'
 PACKAGE_TARNAME='sqlite'

-PACKAGE_VERSION='3.7.0.1'
-PACKAGE_STRING='sqlite 3.7.0.1'
+PACKAGE_VERSION='3.7.2'
+PACKAGE_STRING='sqlite 3.7.2'

 PACKAGE_BUGREPORT='http://www.sqlite.org'
 
 ac_unique_file="sqlite3.c"
 PACKAGE_BUGREPORT='http://www.sqlite.org'
 
 ac_unique_file="sqlite3.c"


@@ -1480,7 +1480,7 @@ if test "$ac_init_help" = "long"; then
   # Omit some internal or obsolete options to make the list less imposing.
   # This message is too long to be a string in the A/UX 3.1 sh.
   cat <<_ACEOF
   # Omit some internal or obsolete options to make the list less imposing.
   # This message is too long to be a string in the A/UX 3.1 sh.
   cat <<_ACEOF

-\`configure' configures sqlite 3.7.0.1 to adapt to many kinds of systems.
+\`configure' configures sqlite 3.7.2 to adapt to many kinds of systems.

 
 Usage: $0 [OPTION]... [VAR=VALUE]...
 
 
 Usage: $0 [OPTION]... [VAR=VALUE]...
 


@@ -1550,7 +1550,7 @@ fi
 
 if test -n "$ac_init_help"; then
   case $ac_init_help in
 
 if test -n "$ac_init_help"; then
   case $ac_init_help in

-     short | recursive ) echo "Configuration of sqlite 3.7.0.1:";;
+     short | recursive ) echo "Configuration of sqlite 3.7.2:";;

    esac
   cat <<\_ACEOF
 
    esac
   cat <<\_ACEOF
 


@@ -1660,7 +1660,7 @@ fi
 test -n "$ac_init_help" && exit $ac_status
 if $ac_init_version; then
   cat <<\_ACEOF
 test -n "$ac_init_help" && exit $ac_status
 if $ac_init_version; then
   cat <<\_ACEOF

-sqlite configure 3.7.0.1
+sqlite configure 3.7.2

 generated by GNU Autoconf 2.62
 
 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
 generated by GNU Autoconf 2.62
 
 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,


@@ -1674,7 +1674,7 @@ cat >config.log <<_ACEOF
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
 
 This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
 

-It was created by sqlite $as_me 3.7.0.1, which was
+It was created by sqlite $as_me 3.7.2, which was

 generated by GNU Autoconf 2.62.  Invocation command line was
 
   $ $0 $@
 generated by GNU Autoconf 2.62.  Invocation command line was
 
   $ $0 $@


@@ -2371,7 +2371,7 @@ fi
 
 # Define the identity of the package.
  PACKAGE='sqlite'
 
 # Define the identity of the package.
  PACKAGE='sqlite'

- VERSION='3.7.0.1'
+ VERSION='3.7.2'

 
 
 cat >>confdefs.h <<_ACEOF
 
 
 cat >>confdefs.h <<_ACEOF


@@ -20759,7 +20759,7 @@ return tgetent ();
   return 0;
 }
 _ACEOF
   return 0;
 }
 _ACEOF

-for ac_lib in '' curses; do
+for ac_lib in '' curses ncurses ncursesw; do

   if test -z "$ac_lib"; then
     ac_res="none required"
   else
   if test -z "$ac_lib"; then
     ac_res="none required"
   else


@@ -21733,7 +21733,7 @@ exec 6>&1
 # report actual input values of CONFIG_FILES etc. instead of their
 # values after options handling.
 ac_log="
 # report actual input values of CONFIG_FILES etc. instead of their
 # values after options handling.
 ac_log="

-This file was extended by sqlite $as_me 3.7.0.1, which was
+This file was extended by sqlite $as_me 3.7.2, which was

 generated by GNU Autoconf 2.62.  Invocation command line was
 
   CONFIG_FILES    = $CONFIG_FILES
 generated by GNU Autoconf 2.62.  Invocation command line was
 
   CONFIG_FILES    = $CONFIG_FILES


@@ -21780,7 +21780,7 @@ Report bugs to <bug-autoconf@gnu.org>."
 _ACEOF
 cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
 ac_cs_version="\\
 _ACEOF
 cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
 ac_cs_version="\\

-sqlite config.status 3.7.0.1
+sqlite config.status 3.7.2

 configured by $0, generated by GNU Autoconf 2.62,
   with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
 
 configured by $0, generated by GNU Autoconf 2.62,
   with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
 

diff --git a/l4/pkg/sqlite/lib/contrib/configure.ac b/l4/pkg/sqlite/lib/contrib/configure.ac
index 95af2c17f31b18f9c0b0327caff7c64c36e26d53..74983118138df04b9a99241243fd56501bbff512 100644 (file)
--- a/l4/pkg/sqlite/lib/contrib/configure.ac
+++ b/l4/pkg/sqlite/lib/contrib/configure.ac
@@ -8,7 +8,7 @@
 #
 
 AC_PREREQ(2.61)
 #
 
 AC_PREREQ(2.61)

-AC_INIT(sqlite, 3.7.0.1, http://www.sqlite.org)
+AC_INIT(sqlite, 3.7.2, http://www.sqlite.org)

 AC_CONFIG_SRCDIR([sqlite3.c])
 
 # Use automake.
 AC_CONFIG_SRCDIR([sqlite3.c])
 
 # Use automake.


@@ -37,7 +37,7 @@ AC_ARG_ENABLE(readline, [AS_HELP_STRING(
 if test x"$enable_readline" != xno ; then
   sLIBS=$LIBS
   LIBS=""
 if test x"$enable_readline" != xno ; then
   sLIBS=$LIBS
   LIBS=""

-  AC_SEARCH_LIBS(tgetent, curses, [], [])
+  AC_SEARCH_LIBS(tgetent, curses ncurses ncursesw, [], [])

   AC_SEARCH_LIBS(readline, readline, [], [enable_readline=no])
   AC_CHECK_FUNCS(readline, [], [])
   READLINE_LIBS=$LIBS
   AC_SEARCH_LIBS(readline, readline, [], [enable_readline=no])
   AC_CHECK_FUNCS(readline, [], [])
   READLINE_LIBS=$LIBS

diff --git a/l4/pkg/sqlite/lib/contrib/shell.c b/l4/pkg/sqlite/lib/contrib/shell.c
index 23099b94a40852b01dfa8afda9d46e2706640d02..c5aa40cf299cbebc673f04e99983a12f08e696d7 100644 (file)
--- a/l4/pkg/sqlite/lib/contrib/shell.c
+++ b/l4/pkg/sqlite/lib/contrib/shell.c
@@ -398,6 +398,7 @@ struct previous_mode_data {
 struct callback_data {
   sqlite3 *db;           /* The database */
   int echoOn;            /* True to echo input commands */
 struct callback_data {
   sqlite3 *db;           /* The database */
   int echoOn;            /* True to echo input commands */

+  int statsOn;           /* True to display memory stats before each finalize */

   int cnt;               /* Number of records displayed so far */
   FILE *out;             /* Write results here */
   int mode;              /* An output mode setting */
   int cnt;               /* Number of records displayed so far */
   FILE *out;             /* Write results here */
   int mode;              /* An output mode setting */


@@ -961,6 +962,86 @@ static char *save_err_msg(
   return zErrMsg;
 }
 
   return zErrMsg;
 }
 

+/*
+** Display memory stats.
+*/
+static int display_stats(
+  sqlite3 *db,                /* Database to query */
+  struct callback_data *pArg, /* Pointer to struct callback_data */
+  int bReset                  /* True to reset the stats */
+){
+  int iCur;
+  int iHiwtr;
+
+  if( pArg && pArg->out ){
+    
+    iHiwtr = iCur = -1;
+    sqlite3_status(SQLITE_STATUS_MEMORY_USED, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Memory Used:                         %d (max %d) bytes\n", iCur, iHiwtr);
+    iHiwtr = iCur = -1;
+    sqlite3_status(SQLITE_STATUS_MALLOC_COUNT, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Number of Allocations:               %d (max %d)\n", iCur, iHiwtr);
+/*
+** Not currently used by the CLI.
+**    iHiwtr = iCur = -1;
+**    sqlite3_status(SQLITE_STATUS_PAGECACHE_USED, &iCur, &iHiwtr, bReset);
+**    fprintf(pArg->out, "Number of Pcache Pages Used:         %d (max %d) pages\n", iCur, iHiwtr);
+*/
+    iHiwtr = iCur = -1;
+    sqlite3_status(SQLITE_STATUS_PAGECACHE_OVERFLOW, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Number of Pcache Overflow Bytes:     %d (max %d) bytes\n", iCur, iHiwtr);
+/*
+** Not currently used by the CLI.
+**    iHiwtr = iCur = -1;
+**    sqlite3_status(SQLITE_STATUS_SCRATCH_USED, &iCur, &iHiwtr, bReset);
+**    fprintf(pArg->out, "Number of Scratch Allocations Used:  %d (max %d)\n", iCur, iHiwtr);
+*/
+    iHiwtr = iCur = -1;
+    sqlite3_status(SQLITE_STATUS_SCRATCH_OVERFLOW, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Number of Scratch Overflow Bytes:    %d (max %d) bytes\n", iCur, iHiwtr);
+    iHiwtr = iCur = -1;
+    sqlite3_status(SQLITE_STATUS_MALLOC_SIZE, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Largest Allocation:                  %d bytes\n", iHiwtr);
+    iHiwtr = iCur = -1;
+    sqlite3_status(SQLITE_STATUS_PAGECACHE_SIZE, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Largest Pcache Allocation:           %d bytes\n", iHiwtr);
+    iHiwtr = iCur = -1;
+    sqlite3_status(SQLITE_STATUS_SCRATCH_SIZE, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Largest Scratch Allocation:          %d bytes\n", iHiwtr);
+#ifdef YYTRACKMAXSTACKDEPTH
+    iHiwtr = iCur = -1;
+    sqlite3_status(SQLITE_STATUS_PARSER_STACK, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Deepest Parser Stack:                %d (max %d)\n", iCur, iHiwtr);
+#endif
+  }
+
+  if( pArg && pArg->out && db ){
+    iHiwtr = iCur = -1;
+    sqlite3_db_status(db, SQLITE_DBSTATUS_LOOKASIDE_USED, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Lookaside Slots Used:                %d (max %d)\n", iCur, iHiwtr);
+    iHiwtr = iCur = -1;
+    sqlite3_db_status(db, SQLITE_DBSTATUS_CACHE_USED, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Pager Heap Usage:                    %d bytes\n", iCur); 
+    iHiwtr = iCur = -1;
+    sqlite3_db_status(db, SQLITE_DBSTATUS_SCHEMA_USED, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Schema Heap Usage:                   %d bytes\n", iCur); 
+    iHiwtr = iCur = -1;
+    sqlite3_db_status(db, SQLITE_DBSTATUS_STMT_USED, &iCur, &iHiwtr, bReset);
+    fprintf(pArg->out, "Statement Heap/Lookaside Usage:      %d bytes\n", iCur); 
+  }
+
+  if( pArg && pArg->out && db && pArg->pStmt ){
+    iCur = sqlite3_stmt_status(pArg->pStmt, SQLITE_STMTSTATUS_FULLSCAN_STEP, bReset);
+    fprintf(pArg->out, "Fullscan Steps:                      %d\n", iCur);
+    iCur = sqlite3_stmt_status(pArg->pStmt, SQLITE_STMTSTATUS_SORT, bReset);
+    fprintf(pArg->out, "Sort Operations:                     %d\n", iCur);
+    iCur = sqlite3_stmt_status(pArg->pStmt, SQLITE_STMTSTATUS_AUTOINDEX, bReset);
+    fprintf(pArg->out, "Autoindex Inserts:                   %d\n", iCur);
+  }
+
+  return 0;
+}
+

 /*
 ** Execute a statement or set of statements.  Print 
 ** any result rows/columns depending on the current mode 
 /*
 ** Execute a statement or set of statements.  Print 
 ** any result rows/columns depending on the current mode 


@@ -1000,10 +1081,16 @@ static int shell_exec(
         continue;
       }
 
         continue;
       }
 

+      /* save off the prepared statment handle and reset row count */
+      if( pArg ){
+        pArg->pStmt = pStmt;
+        pArg->cnt = 0;
+      }
+

       /* echo the sql statement if echo on */
       /* echo the sql statement if echo on */

-      if( pArg->echoOn ){
+      if( pArg && pArg->echoOn ){

         const char *zStmtSql = sqlite3_sql(pStmt);
         const char *zStmtSql = sqlite3_sql(pStmt);

-        fprintf(pArg->out,"%s\n", zStmtSql ? zStmtSql : zSql);
+        fprintf(pArg->out, "%s\n", zStmtSql ? zStmtSql : zSql);

       }
 
       /* perform the first step.  this will tell us if we
       }
 
       /* perform the first step.  this will tell us if we


@@ -1029,11 +1116,6 @@ static int shell_exec(
             for(i=0; i<nCol; i++){
               azCols[i] = (char *)sqlite3_column_name(pStmt, i);
             }
             for(i=0; i<nCol; i++){
               azCols[i] = (char *)sqlite3_column_name(pStmt, i);
             }

-            /* save off the prepared statment handle and reset row count */
-            if( pArg ){
-              pArg->pStmt = pStmt;
-              pArg->cnt = 0;
-            }

             do{
               /* extract the data and data types */
               for(i=0; i<nCol; i++){
             do{
               /* extract the data and data types */
               for(i=0; i<nCol; i++){


@@ -1056,9 +1138,6 @@ static int shell_exec(
               }
             } while( SQLITE_ROW == rc );
             sqlite3_free(pData);
               }
             } while( SQLITE_ROW == rc );
             sqlite3_free(pData);

-            if( pArg ){
-              pArg->pStmt = NULL;
-            }

           }
         }else{
           do{
           }
         }else{
           do{


@@ -1067,6 +1146,11 @@ static int shell_exec(
         }
       }
 
         }
       }
 

+      /* print usage stats if stats on */
+      if( pArg && pArg->statsOn ){
+        display_stats(db, pArg, 0);
+      }
+

       /* Finalize the statement just executed. If this fails, save a 
       ** copy of the error message. Otherwise, set zSql to point to the
       ** next statement to execute. */
       /* Finalize the statement just executed. If this fails, save a 
       ** copy of the error message. Otherwise, set zSql to point to the
       ** next statement to execute. */


@@ -1077,6 +1161,11 @@ static int shell_exec(
       }else if( pzErrMsg ){
         *pzErrMsg = save_err_msg(db);
       }
       }else if( pzErrMsg ){
         *pzErrMsg = save_err_msg(db);
       }

+
+      /* clear saved stmt handle */
+      if( pArg ){
+        pArg->pStmt = NULL;
+      }

     }
   } /* end while */
 
     }
   } /* end while */
 


@@ -1256,6 +1345,7 @@ static char zHelp[] =
   "                         LIKE pattern TABLE.\n"
   ".separator STRING      Change separator used by output mode and .import\n"
   ".show                  Show the current values for various settings\n"
   "                         LIKE pattern TABLE.\n"
   ".separator STRING      Change separator used by output mode and .import\n"
   ".show                  Show the current values for various settings\n"

+  ".stats ON|OFF          Turn stats on or off\n"

   ".tables ?TABLE?        List names of tables\n"
   "                         If TABLE specified, only list tables matching\n"
   "                         LIKE pattern TABLE.\n"
   ".tables ?TABLE?        List names of tables\n"
   "                         If TABLE specified, only list tables matching\n"
   "                         LIKE pattern TABLE.\n"


@@ -2001,6 +2091,7 @@ static int do_meta_command(char *zLine, struct callback_data *p){
     fprintf(p->out,"%9.9s: ", "separator");
       output_c_string(p->out, p->separator);
       fprintf(p->out, "\n");
     fprintf(p->out,"%9.9s: ", "separator");
       output_c_string(p->out, p->separator);
       fprintf(p->out, "\n");

+    fprintf(p->out,"%9.9s: %s\n","stats", p->statsOn ? "on" : "off");

     fprintf(p->out,"%9.9s: ","width");
     for (i=0;i<(int)ArraySize(p->colWidth) && p->colWidth[i] != 0;i++) {
       fprintf(p->out,"%d ",p->colWidth[i]);
     fprintf(p->out,"%9.9s: ","width");
     for (i=0;i<(int)ArraySize(p->colWidth) && p->colWidth[i] != 0;i++) {
       fprintf(p->out,"%d ",p->colWidth[i]);


@@ -2008,6 +2099,10 @@ static int do_meta_command(char *zLine, struct callback_data *p){
     fprintf(p->out,"\n");
   }else
 
     fprintf(p->out,"\n");
   }else
 

+  if( c=='s' && strncmp(azArg[0], "stats", n)==0 && nArg>1 && nArg<3 ){
+    p->statsOn = booleanValue(azArg[1]);
+  }else
+

   if( c=='t' && n>1 && strncmp(azArg[0], "tables", n)==0 && nArg<3 ){
     char **azResult;
     int nRow;
   if( c=='t' && n>1 && strncmp(azArg[0], "tables", n)==0 && nArg<3 ){
     char **azResult;
     int nRow;


@@ -2391,6 +2486,7 @@ static const char zOptions[] =
   "   -line                set output mode to 'line'\n"
   "   -list                set output mode to 'list'\n"
   "   -separator 'x'       set output field separator (|)\n"
   "   -line                set output mode to 'line'\n"
   "   -list                set output mode to 'list'\n"
   "   -separator 'x'       set output field separator (|)\n"

+  "   -stats               print memory stats before each finalize\n"

   "   -nullvalue 'text'    set text string for NULL values\n"
   "   -version             show SQLite version\n"
 ;
   "   -nullvalue 'text'    set text string for NULL values\n"
   "   -version             show SQLite version\n"
 ;


@@ -2555,6 +2651,8 @@ int main(int argc, char **argv){
       data.showHeader = 0;
     }else if( strcmp(z,"-echo")==0 ){
       data.echoOn = 1;
       data.showHeader = 0;
     }else if( strcmp(z,"-echo")==0 ){
       data.echoOn = 1;

+    }else if( strcmp(z,"-stats")==0 ){
+      data.statsOn = 1;

     }else if( strcmp(z,"-bail")==0 ){
       bail_on_error = 1;
     }else if( strcmp(z,"-version")==0 ){
     }else if( strcmp(z,"-bail")==0 ){
       bail_on_error = 1;
     }else if( strcmp(z,"-version")==0 ){

diff --git a/l4/pkg/sqlite/lib/contrib/sqlite3.c b/l4/pkg/sqlite/lib/contrib/sqlite3.c
index 53dcf4f81abd4846161f22bb1b57dba85461e1d0..695de181093be3b81530dc71530f270f12854db1 100644 (file)
--- a/l4/pkg/sqlite/lib/contrib/sqlite3.c
+++ b/l4/pkg/sqlite/lib/contrib/sqlite3.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 ** This file is an amalgamation of many separate C source files from SQLite
 /******************************************************************************
 ** This file is an amalgamation of many separate C source files from SQLite

-** version 3.7.0.1.  By combining all the individual C code files into this 
+** version 3.7.2.  By combining all the individual C code files into this 

 ** single large file, the entire code can be compiled as a one translation
 ** unit.  This allows many compilers to do optimizations that would not be
 ** possible if the files were compiled separately.  Performance improvements
 ** single large file, the entire code can be compiled as a one translation
 ** unit.  This allows many compilers to do optimizations that would not be
 ** possible if the files were compiled separately.  Performance improvements


@@ -215,20 +215,21 @@
 # define SQLITE_MAX_VARIABLE_NUMBER 999
 #endif
 
 # define SQLITE_MAX_VARIABLE_NUMBER 999
 #endif
 

-/* Maximum page size.  The upper bound on this value is 32768.  This a limit
-** imposed by the necessity of storing the value in a 2-byte unsigned integer
-** and the fact that the page size must be a power of 2.
+/* Maximum page size.  The upper bound on this value is 65536.  This a limit
+** imposed by the use of 16-bit offsets within each page.

 **
 **

-** If this limit is changed, then the compiled library is technically
-** incompatible with an SQLite library compiled with a different limit. If
-** a process operating on a database with a page-size of 65536 bytes 
-** crashes, then an instance of SQLite compiled with the default page-size 
-** limit will not be able to rollback the aborted transaction. This could
-** lead to database corruption.
+** Earlier versions of SQLite allowed the user to change this value at
+** compile time. This is no longer permitted, on the grounds that it creates
+** a library that is technically incompatible with an SQLite library 
+** compiled with a different limit. If a process operating on a database 
+** with a page-size of 65536 bytes crashes, then an instance of SQLite 
+** compiled with the default page-size limit will not be able to rollback 
+** the aborted transaction. This could lead to database corruption.

 */
 */

-#ifndef SQLITE_MAX_PAGE_SIZE
-# define SQLITE_MAX_PAGE_SIZE 32768
+#ifdef SQLITE_MAX_PAGE_SIZE
+# undef SQLITE_MAX_PAGE_SIZE

 #endif
 #endif

+#define SQLITE_MAX_PAGE_SIZE 65536

 
 
 /*
 
 
 /*


@@ -633,7 +634,7 @@ extern "C" {
 **
 ** Since version 3.6.18, SQLite source code has been stored in the
 ** <a href="http://www.fossil-scm.org/">Fossil configuration management
 **
 ** Since version 3.6.18, SQLite source code has been stored in the
 ** <a href="http://www.fossil-scm.org/">Fossil configuration management

-** system</a>.  ^The SQLITE_SOURCE_ID macro evalutes to
+** system</a>.  ^The SQLITE_SOURCE_ID macro evaluates to

 ** a string which identifies a particular check-in of SQLite
 ** within its configuration management system.  ^The SQLITE_SOURCE_ID
 ** string contains the date and time of the check-in (UTC) and an SHA1
 ** a string which identifies a particular check-in of SQLite
 ** within its configuration management system.  ^The SQLITE_SOURCE_ID
 ** string contains the date and time of the check-in (UTC) and an SHA1


@@ -643,9 +644,9 @@ extern "C" {
 ** [sqlite3_libversion_number()], [sqlite3_sourceid()],
 ** [sqlite_version()] and [sqlite_source_id()].
 */
 ** [sqlite3_libversion_number()], [sqlite3_sourceid()],
 ** [sqlite_version()] and [sqlite_source_id()].
 */

-#define SQLITE_VERSION        "3.7.0.1"
-#define SQLITE_VERSION_NUMBER 3007000
-#define SQLITE_SOURCE_ID      "2010-08-04 12:31:11 042a1abb030a0711386add7eb6e10832cc8b0f57"
+#define SQLITE_VERSION        "3.7.2"
+#define SQLITE_VERSION_NUMBER 3007002
+#define SQLITE_SOURCE_ID      "2010-08-23 18:52:01 42537b60566f288167f1b5864a5435986838e3a3"

 
 /*
 ** CAPI3REF: Run-Time Library Version Numbers
 
 /*
 ** CAPI3REF: Run-Time Library Version Numbers


@@ -690,7 +691,7 @@ SQLITE_API int sqlite3_libversion_number(void);
 ** compile time.  ^The SQLITE_ prefix may be omitted from the 
 ** option name passed to sqlite3_compileoption_used().  
 **
 ** compile time.  ^The SQLITE_ prefix may be omitted from the 
 ** option name passed to sqlite3_compileoption_used().  
 **

-** ^The sqlite3_compileoption_get() function allows interating
+** ^The sqlite3_compileoption_get() function allows iterating

 ** over the list of options that were defined at compile time by
 ** returning the N-th compile time option string.  ^If N is out of range,
 ** sqlite3_compileoption_get() returns a NULL pointer.  ^The SQLITE_ 
 ** over the list of options that were defined at compile time by
 ** returning the N-th compile time option string.  ^If N is out of range,
 ** sqlite3_compileoption_get() returns a NULL pointer.  ^The SQLITE_ 


@@ -698,7 +699,7 @@ SQLITE_API int sqlite3_libversion_number(void);
 ** sqlite3_compileoption_get().
 **
 ** ^Support for the diagnostic functions sqlite3_compileoption_used()
 ** sqlite3_compileoption_get().
 **
 ** ^Support for the diagnostic functions sqlite3_compileoption_used()

-** and sqlite3_compileoption_get() may be omitted by specifing the 
+** and sqlite3_compileoption_get() may be omitted by specifying the 

 ** [SQLITE_OMIT_COMPILEOPTION_DIAGS] option at compile time.
 **
 ** See also: SQL functions [sqlite_compileoption_used()] and
 ** [SQLITE_OMIT_COMPILEOPTION_DIAGS] option at compile time.
 **
 ** See also: SQL functions [sqlite_compileoption_used()] and


@@ -804,7 +805,7 @@ typedef sqlite_uint64 sqlite3_uint64;
 **
 ** ^The sqlite3_close() routine is the destructor for the [sqlite3] object.
 ** ^Calls to sqlite3_close() return SQLITE_OK if the [sqlite3] object is
 **
 ** ^The sqlite3_close() routine is the destructor for the [sqlite3] object.
 ** ^Calls to sqlite3_close() return SQLITE_OK if the [sqlite3] object is

-** successfullly destroyed and all associated resources are deallocated.
+** successfully destroyed and all associated resources are deallocated.

 **
 ** Applications must [sqlite3_finalize | finalize] all [prepared statements]
 ** and [sqlite3_blob_close | close] all [BLOB handles] associated with
 **
 ** Applications must [sqlite3_finalize | finalize] all [prepared statements]
 ** and [sqlite3_blob_close | close] all [BLOB handles] associated with


@@ -1231,12 +1232,21 @@ struct sqlite3_io_methods {
 ** is often close.  The underlying VFS might choose to preallocate database
 ** file space based on this hint in order to help writes to the database
 ** file run faster.
 ** is often close.  The underlying VFS might choose to preallocate database
 ** file space based on this hint in order to help writes to the database
 ** file run faster.

+**
+** The [SQLITE_FCNTL_CHUNK_SIZE] opcode is used to request that the VFS
+** extends and truncates the database file in chunks of a size specified
+** by the user. The fourth argument to [sqlite3_file_control()] should 
+** point to an integer (type int) containing the new chunk-size to use
+** for the nominated database. Allocating database file space in large
+** chunks (say 1MB at a time), may reduce file-system fragmentation and
+** improve performance on some systems.

 */
 #define SQLITE_FCNTL_LOCKSTATE        1
 #define SQLITE_GET_LOCKPROXYFILE      2
 #define SQLITE_SET_LOCKPROXYFILE      3
 #define SQLITE_LAST_ERRNO             4
 #define SQLITE_FCNTL_SIZE_HINT        5
 */
 #define SQLITE_FCNTL_LOCKSTATE        1
 #define SQLITE_GET_LOCKPROXYFILE      2
 #define SQLITE_SET_LOCKPROXYFILE      3
 #define SQLITE_LAST_ERRNO             4
 #define SQLITE_FCNTL_SIZE_HINT        5

+#define SQLITE_FCNTL_CHUNK_SIZE       6

 
 /*
 ** CAPI3REF: Mutex Handle
 
 /*
 ** CAPI3REF: Mutex Handle


@@ -2712,7 +2722,13 @@ SQLITE_API int sqlite3_set_authorizer(
 ** ^The callback function registered by sqlite3_profile() is invoked
 ** as each SQL statement finishes.  ^The profile callback contains
 ** the original statement text and an estimate of wall-clock time
 ** ^The callback function registered by sqlite3_profile() is invoked
 ** as each SQL statement finishes.  ^The profile callback contains
 ** the original statement text and an estimate of wall-clock time

-** of how long that statement took to run.
+** of how long that statement took to run.  ^The profile callback
+** time is in units of nanoseconds, however the current implementation
+** is only capable of millisecond resolution so the six least significant
+** digits in the time are meaningless.  Future versions of SQLite
+** might provide greater resolution on the profiler callback.  The
+** sqlite3_profile() function is considered experimental and is
+** subject to change in future versions of SQLite.

 */
 SQLITE_API void *sqlite3_trace(sqlite3*, void(*xTrace)(void*,const char*), void*);
 SQLITE_API SQLITE_EXPERIMENTAL void *sqlite3_profile(sqlite3*,
 */
 SQLITE_API void *sqlite3_trace(sqlite3*, void(*xTrace)(void*,const char*), void*);
 SQLITE_API SQLITE_EXPERIMENTAL void *sqlite3_profile(sqlite3*,


@@ -3193,7 +3209,7 @@ typedef struct sqlite3_context sqlite3_context;
 ** </ul>
 **
 ** In the templates above, NNN represents an integer literal,
 ** </ul>
 **
 ** In the templates above, NNN represents an integer literal,

-** and VVV represents an alphanumeric identifer.)^  ^The values of these
+** and VVV represents an alphanumeric identifier.)^  ^The values of these

 ** parameters (also called "host parameter names" or "SQL parameters")
 ** can be set using the sqlite3_bind_*() routines defined here.
 **
 ** parameters (also called "host parameter names" or "SQL parameters")
 ** can be set using the sqlite3_bind_*() routines defined here.
 **


@@ -3972,7 +3988,7 @@ SQLITE_API int sqlite3_value_numeric_type(sqlite3_value*);
 /*
 ** CAPI3REF: Obtain Aggregate Function Context
 **
 /*
 ** CAPI3REF: Obtain Aggregate Function Context
 **

-** Implementions of aggregate SQL functions use this
+** Implementations of aggregate SQL functions use this

 ** routine to allocate memory for storing their state.
 **
 ** ^The first time the sqlite3_aggregate_context(C,N) routine is called 
 ** routine to allocate memory for storing their state.
 **
 ** ^The first time the sqlite3_aggregate_context(C,N) routine is called 


@@ -4244,7 +4260,7 @@ SQLITE_API void sqlite3_result_zeroblob(sqlite3_context*, int n);
 **
 ** A pointer to the user supplied routine must be passed as the fifth
 ** argument.  ^If it is NULL, this is the same as deleting the collation
 **
 ** A pointer to the user supplied routine must be passed as the fifth
 ** argument.  ^If it is NULL, this is the same as deleting the collation

-** sequence (so that SQLite cannot call it anymore).
+** sequence (so that SQLite cannot call it any more).

 ** ^Each time the application supplied function is invoked, it is passed
 ** as its first parameter a copy of the void* passed as the fourth argument
 ** to sqlite3_create_collation() or sqlite3_create_collation16().
 ** ^Each time the application supplied function is invoked, it is passed
 ** as its first parameter a copy of the void* passed as the fourth argument
 ** to sqlite3_create_collation() or sqlite3_create_collation16().


@@ -4861,7 +4877,8 @@ struct sqlite3_module {
 ** CAPI3REF: Virtual Table Indexing Information
 ** KEYWORDS: sqlite3_index_info
 **
 ** CAPI3REF: Virtual Table Indexing Information
 ** KEYWORDS: sqlite3_index_info
 **

-** The sqlite3_index_info structure and its substructures is used to
+** The sqlite3_index_info structure and its substructures is used as part
+** of the [virtual table] interface to

 ** pass information into and receive the reply from the [xBestIndex]
 ** method of a [virtual table module].  The fields under **Inputs** are the
 ** inputs to xBestIndex and are read-only.  xBestIndex inserts its
 ** pass information into and receive the reply from the [xBestIndex]
 ** method of a [virtual table module].  The fields under **Inputs** are the
 ** inputs to xBestIndex and are read-only.  xBestIndex inserts its


@@ -4869,10 +4886,12 @@ struct sqlite3_module {
 **
 ** ^(The aConstraint[] array records WHERE clause constraints of the form:
 **
 **
 ** ^(The aConstraint[] array records WHERE clause constraints of the form:
 **

-** <pre>column OP expr</pre>
+** <blockquote>column OP expr</blockquote>

 **
 ** where OP is =, &lt;, &lt;=, &gt;, or &gt;=.)^  ^(The particular operator is
 **
 ** where OP is =, &lt;, &lt;=, &gt;, or &gt;=.)^  ^(The particular operator is

-** stored in aConstraint[].op.)^  ^(The index of the column is stored in
+** stored in aConstraint[].op using one of the
+** [SQLITE_INDEX_CONSTRAINT_EQ | SQLITE_INDEX_CONSTRAINT_ values].)^
+** ^(The index of the column is stored in

 ** aConstraint[].iColumn.)^  ^(aConstraint[].usable is TRUE if the
 ** expr on the right-hand side can be evaluated (and thus the constraint
 ** is usable) and false if it cannot.)^
 ** aConstraint[].iColumn.)^  ^(aConstraint[].usable is TRUE if the
 ** expr on the right-hand side can be evaluated (and thus the constraint
 ** is usable) and false if it cannot.)^


@@ -4932,6 +4951,15 @@ struct sqlite3_index_info {
   int orderByConsumed;       /* True if output is already ordered */
   double estimatedCost;      /* Estimated cost of using this index */
 };
   int orderByConsumed;       /* True if output is already ordered */
   double estimatedCost;      /* Estimated cost of using this index */
 };

+
+/*
+** CAPI3REF: Virtual Table Constraint Operator Codes
+**
+** These macros defined the allowed values for the
+** [sqlite3_index_info].aConstraint[].op field.  Each value represents
+** an operator that is part of a constraint term in the wHERE clause of
+** a query that uses a [virtual table].
+*/

 #define SQLITE_INDEX_CONSTRAINT_EQ    2
 #define SQLITE_INDEX_CONSTRAINT_GT    4
 #define SQLITE_INDEX_CONSTRAINT_LE    8
 #define SQLITE_INDEX_CONSTRAINT_EQ    2
 #define SQLITE_INDEX_CONSTRAINT_GT    4
 #define SQLITE_INDEX_CONSTRAINT_LE    8


@@ -5450,7 +5478,7 @@ SQLITE_API void sqlite3_mutex_leave(sqlite3_mutex*);
 ** it is passed a NULL pointer).
 **
 ** The xMutexInit() method must be threadsafe.  ^It must be harmless to
 ** it is passed a NULL pointer).
 **
 ** The xMutexInit() method must be threadsafe.  ^It must be harmless to

-** invoke xMutexInit() mutiple times within the same process and without
+** invoke xMutexInit() multiple times within the same process and without

 ** intervening calls to xMutexEnd().  Second and subsequent calls to
 ** xMutexInit() must be no-ops.
 **
 ** intervening calls to xMutexEnd().  Second and subsequent calls to
 ** xMutexInit() must be no-ops.
 **


@@ -5620,7 +5648,7 @@ SQLITE_API int sqlite3_test_control(int op, ...);
 ** CAPI3REF: SQLite Runtime Status
 **
 ** ^This interface is used to retrieve runtime status information
 ** CAPI3REF: SQLite Runtime Status
 **
 ** ^This interface is used to retrieve runtime status information

-** about the preformance of SQLite, and optionally to reset various
+** about the performance of SQLite, and optionally to reset various

 ** highwater marks.  ^The first argument is an integer code for
 ** the specific parameter to measure.  ^(Recognized integer codes
 ** are of the form [SQLITE_STATUS_MEMORY_USED | SQLITE_STATUS_...].)^
 ** highwater marks.  ^The first argument is an integer code for
 ** the specific parameter to measure.  ^(Recognized integer codes
 ** are of the form [SQLITE_STATUS_MEMORY_USED | SQLITE_STATUS_...].)^


@@ -5672,6 +5700,9 @@ SQLITE_API int sqlite3_status(int op, int *pCurrent, int *pHighwater, int resetF
 ** *pHighwater parameter to [sqlite3_status()] is of interest.  
 ** The value written into the *pCurrent parameter is undefined.</dd>)^
 **
 ** *pHighwater parameter to [sqlite3_status()] is of interest.  
 ** The value written into the *pCurrent parameter is undefined.</dd>)^
 **

+** ^(<dt>SQLITE_STATUS_MALLOC_COUNT</dt>
+** <dd>This parameter records the number of separate memory allocations.</dd>)^
+**

 ** ^(<dt>SQLITE_STATUS_PAGECACHE_USED</dt>
 ** <dd>This parameter returns the number of pages used out of the
 ** [pagecache memory allocator] that was configured using 
 ** ^(<dt>SQLITE_STATUS_PAGECACHE_USED</dt>
 ** <dd>This parameter returns the number of pages used out of the
 ** [pagecache memory allocator] that was configured using 


@@ -5733,6 +5764,7 @@ SQLITE_API int sqlite3_status(int op, int *pCurrent, int *pHighwater, int resetF
 #define SQLITE_STATUS_PARSER_STACK         6
 #define SQLITE_STATUS_PAGECACHE_SIZE       7
 #define SQLITE_STATUS_SCRATCH_SIZE         8
 #define SQLITE_STATUS_PARSER_STACK         6
 #define SQLITE_STATUS_PAGECACHE_SIZE       7
 #define SQLITE_STATUS_SCRATCH_SIZE         8

+#define SQLITE_STATUS_MALLOC_COUNT         9

 
 /*
 ** CAPI3REF: Database Connection Status
 
 /*
 ** CAPI3REF: Database Connection Status


@@ -5742,7 +5774,7 @@ SQLITE_API int sqlite3_status(int op, int *pCurrent, int *pHighwater, int resetF
 ** database connection object to be interrogated.  ^The second argument
 ** is an integer constant, taken from the set of
 ** [SQLITE_DBSTATUS_LOOKASIDE_USED | SQLITE_DBSTATUS_*] macros, that
 ** database connection object to be interrogated.  ^The second argument
 ** is an integer constant, taken from the set of
 ** [SQLITE_DBSTATUS_LOOKASIDE_USED | SQLITE_DBSTATUS_*] macros, that

-** determiness the parameter to interrogate.  The set of 
+** determines the parameter to interrogate.  The set of 

 ** [SQLITE_DBSTATUS_LOOKASIDE_USED | SQLITE_DBSTATUS_*] macros is likely
 ** to grow in future releases of SQLite.
 **
 ** [SQLITE_DBSTATUS_LOOKASIDE_USED | SQLITE_DBSTATUS_*] macros is likely
 ** to grow in future releases of SQLite.
 **


@@ -5772,16 +5804,33 @@ SQLITE_API int sqlite3_db_status(sqlite3*, int op, int *pCur, int *pHiwtr, int r
 ** <dd>This parameter returns the number of lookaside memory slots currently
 ** checked out.</dd>)^
 **
 ** <dd>This parameter returns the number of lookaside memory slots currently
 ** checked out.</dd>)^
 **

-** <dt>SQLITE_DBSTATUS_CACHE_USED</dt>
-** <dd>^This parameter returns the approximate number of of bytes of heap
-** memory used by all pager caches associated with the database connection.
+** ^(<dt>SQLITE_DBSTATUS_CACHE_USED</dt>
+** <dd>This parameter returns the approximate number of of bytes of heap
+** memory used by all pager caches associated with the database connection.)^

 ** ^The highwater mark associated with SQLITE_DBSTATUS_CACHE_USED is always 0.
 ** ^The highwater mark associated with SQLITE_DBSTATUS_CACHE_USED is always 0.

+**
+** ^(<dt>SQLITE_DBSTATUS_SCHEMA_USED</dt>
+** <dd>This parameter returns the approximate number of of bytes of heap
+** memory used to store the schema for all databases associated
+** with the connection - main, temp, and any [ATTACH]-ed databases.)^ 
+** ^The full amount of memory used by the schemas is reported, even if the
+** schema memory is shared with other database connections due to
+** [shared cache mode] being enabled.
+** ^The highwater mark associated with SQLITE_DBSTATUS_SCHEMA_USED is always 0.
+**
+** ^(<dt>SQLITE_DBSTATUS_STMT_USED</dt>
+** <dd>This parameter returns the approximate number of of bytes of heap
+** and lookaside memory used by all prepared statements associated with
+** the database connection.)^
+** ^The highwater mark associated with SQLITE_DBSTATUS_STMT_USED is always 0.

 ** </dd>
 ** </dl>
 */
 #define SQLITE_DBSTATUS_LOOKASIDE_USED     0
 #define SQLITE_DBSTATUS_CACHE_USED         1
 ** </dd>
 ** </dl>
 */
 #define SQLITE_DBSTATUS_LOOKASIDE_USED     0
 #define SQLITE_DBSTATUS_CACHE_USED         1

-#define SQLITE_DBSTATUS_MAX                1   /* Largest defined DBSTATUS */
+#define SQLITE_DBSTATUS_SCHEMA_USED        2
+#define SQLITE_DBSTATUS_STMT_USED          3
+#define SQLITE_DBSTATUS_MAX                3   /* Largest defined DBSTATUS */

 
 
 /*
 
 
 /*


@@ -6147,7 +6196,7 @@ typedef struct sqlite3_backup sqlite3_backup;
 **
 ** ^Each call to sqlite3_backup_step() sets two values inside
 ** the [sqlite3_backup] object: the number of pages still to be backed
 **
 ** ^Each call to sqlite3_backup_step() sets two values inside
 ** the [sqlite3_backup] object: the number of pages still to be backed

-** up and the total number of pages in the source databae file.
+** up and the total number of pages in the source database file.

 ** The sqlite3_backup_remaining() and sqlite3_backup_pagecount() interfaces
 ** retrieve these two values, respectively.
 **
 ** The sqlite3_backup_remaining() and sqlite3_backup_pagecount() interfaces
 ** retrieve these two values, respectively.
 **


@@ -6243,7 +6292,7 @@ SQLITE_API int sqlite3_backup_pagecount(sqlite3_backup *p);
 ** blocked connection already has a registered unlock-notify callback,
 ** then the new callback replaces the old.)^ ^If sqlite3_unlock_notify() is
 ** called with a NULL pointer as its second argument, then any existing
 ** blocked connection already has a registered unlock-notify callback,
 ** then the new callback replaces the old.)^ ^If sqlite3_unlock_notify() is
 ** called with a NULL pointer as its second argument, then any existing

-** unlock-notify callback is cancelled. ^The blocked connections 
+** unlock-notify callback is canceled. ^The blocked connections 

 ** unlock-notify callback may also be canceled by closing the blocked
 ** connection using [sqlite3_close()].
 **
 ** unlock-notify callback may also be canceled by closing the blocked
 ** connection using [sqlite3_close()].
 **


@@ -6325,7 +6374,7 @@ SQLITE_API int sqlite3_unlock_notify(
 **
 ** ^The [sqlite3_strnicmp()] API allows applications and extensions to
 ** compare the contents of two buffers containing UTF-8 strings in a
 **
 ** ^The [sqlite3_strnicmp()] API allows applications and extensions to
 ** compare the contents of two buffers containing UTF-8 strings in a

-** case-indendent fashion, using the same definition of case independence 
+** case-independent fashion, using the same definition of case independence 

 ** that SQLite uses internally when comparing identifiers.
 */
 SQLITE_API int sqlite3_strnicmp(const char *, const char *, int);
 ** that SQLite uses internally when comparing identifiers.
 */
 SQLITE_API int sqlite3_strnicmp(const char *, const char *, int);


@@ -7259,6 +7308,10 @@ SQLITE_PRIVATE int sqlite3BtreeCursorInfo(BtCursor*, int*, int);
 SQLITE_PRIVATE void sqlite3BtreeCursorList(Btree*);
 #endif
 
 SQLITE_PRIVATE void sqlite3BtreeCursorList(Btree*);
 #endif
 

+#ifndef SQLITE_OMIT_WAL
+SQLITE_PRIVATE   int sqlite3BtreeCheckpoint(Btree*);
+#endif
+

 /*
 ** If we are not using shared cache, then there is no need to
 ** use mutexes to access the BtShared structures.  So make the
 /*
 ** If we are not using shared cache, then there is no need to
 ** use mutexes to access the BtShared structures.  So make the


@@ -7388,8 +7441,8 @@ struct SubProgram {
   int nOp;                      /* Elements in aOp[] */
   int nMem;                     /* Number of memory cells required */
   int nCsr;                     /* Number of cursors required */
   int nOp;                      /* Elements in aOp[] */
   int nMem;                     /* Number of memory cells required */
   int nCsr;                     /* Number of cursors required */

-  int nRef;                     /* Number of pointers to this structure */

   void *token;                  /* id that may be used to recursive triggers */
   void *token;                  /* id that may be used to recursive triggers */

+  SubProgram *pNext;            /* Next sub-program already visited */

 };
 
 /*
 };
 
 /*


@@ -7677,6 +7730,7 @@ SQLITE_PRIVATE VdbeOp *sqlite3VdbeGetOp(Vdbe*, int);
 SQLITE_PRIVATE int sqlite3VdbeMakeLabel(Vdbe*);
 SQLITE_PRIVATE void sqlite3VdbeRunOnlyOnce(Vdbe*);
 SQLITE_PRIVATE void sqlite3VdbeDelete(Vdbe*);
 SQLITE_PRIVATE int sqlite3VdbeMakeLabel(Vdbe*);
 SQLITE_PRIVATE void sqlite3VdbeRunOnlyOnce(Vdbe*);
 SQLITE_PRIVATE void sqlite3VdbeDelete(Vdbe*);

+SQLITE_PRIVATE void sqlite3VdbeDeleteObject(sqlite3*,Vdbe*);

 SQLITE_PRIVATE void sqlite3VdbeMakeReady(Vdbe*,int,int,int,int,int,int);
 SQLITE_PRIVATE int sqlite3VdbeFinalize(Vdbe*);
 SQLITE_PRIVATE void sqlite3VdbeResolveLabel(Vdbe*, int);
 SQLITE_PRIVATE void sqlite3VdbeMakeReady(Vdbe*,int,int,int,int,int,int);
 SQLITE_PRIVATE int sqlite3VdbeFinalize(Vdbe*);
 SQLITE_PRIVATE void sqlite3VdbeResolveLabel(Vdbe*, int);


@@ -7694,7 +7748,6 @@ SQLITE_PRIVATE sqlite3 *sqlite3VdbeDb(Vdbe*);
 SQLITE_PRIVATE void sqlite3VdbeSetSql(Vdbe*, const char *z, int n, int);
 SQLITE_PRIVATE void sqlite3VdbeSwap(Vdbe*,Vdbe*);
 SQLITE_PRIVATE VdbeOp *sqlite3VdbeTakeOpArray(Vdbe*, int*, int*);
 SQLITE_PRIVATE void sqlite3VdbeSetSql(Vdbe*, const char *z, int n, int);
 SQLITE_PRIVATE void sqlite3VdbeSwap(Vdbe*,Vdbe*);
 SQLITE_PRIVATE VdbeOp *sqlite3VdbeTakeOpArray(Vdbe*, int*, int*);

-SQLITE_PRIVATE void sqlite3VdbeProgramDelete(sqlite3 *, SubProgram *, int);

 SQLITE_PRIVATE sqlite3_value *sqlite3VdbeGetValue(Vdbe*, int, u8);
 SQLITE_PRIVATE void sqlite3VdbeSetVarmask(Vdbe*, int);
 #ifndef SQLITE_OMIT_TRACE
 SQLITE_PRIVATE sqlite3_value *sqlite3VdbeGetValue(Vdbe*, int, u8);
 SQLITE_PRIVATE void sqlite3VdbeSetVarmask(Vdbe*, int);
 #ifndef SQLITE_OMIT_TRACE


@@ -7705,6 +7758,10 @@ SQLITE_PRIVATE UnpackedRecord *sqlite3VdbeRecordUnpack(KeyInfo*,int,const void*,
 SQLITE_PRIVATE void sqlite3VdbeDeleteUnpackedRecord(UnpackedRecord*);
 SQLITE_PRIVATE int sqlite3VdbeRecordCompare(int,const void*,UnpackedRecord*);
 
 SQLITE_PRIVATE void sqlite3VdbeDeleteUnpackedRecord(UnpackedRecord*);
 SQLITE_PRIVATE int sqlite3VdbeRecordCompare(int,const void*,UnpackedRecord*);
 

+#ifndef SQLITE_OMIT_TRIGGER
+SQLITE_PRIVATE void sqlite3VdbeLinkSubProgram(Vdbe *, SubProgram *);
+#endif
+

 
 #ifndef NDEBUG
 SQLITE_PRIVATE   void sqlite3VdbeComment(Vdbe*, const char*, ...);
 
 #ifndef NDEBUG
 SQLITE_PRIVATE   void sqlite3VdbeComment(Vdbe*, const char*, ...);


@@ -7823,7 +7880,7 @@ SQLITE_PRIVATE int sqlite3PagerReadFileheader(Pager*, int, unsigned char*);
 
 /* Functions used to configure a Pager object. */
 SQLITE_PRIVATE void sqlite3PagerSetBusyhandler(Pager*, int(*)(void *), void *);
 
 /* Functions used to configure a Pager object. */
 SQLITE_PRIVATE void sqlite3PagerSetBusyhandler(Pager*, int(*)(void *), void *);

-SQLITE_PRIVATE int sqlite3PagerSetPagesize(Pager*, u16*, int);
+SQLITE_PRIVATE int sqlite3PagerSetPagesize(Pager*, u32*, int);

 SQLITE_PRIVATE int sqlite3PagerMaxPageCount(Pager*, int);
 SQLITE_PRIVATE void sqlite3PagerSetCachesize(Pager*, int);
 SQLITE_PRIVATE void sqlite3PagerSetSafetyLevel(Pager*,int,int);
 SQLITE_PRIVATE int sqlite3PagerMaxPageCount(Pager*, int);
 SQLITE_PRIVATE void sqlite3PagerSetCachesize(Pager*, int);
 SQLITE_PRIVATE void sqlite3PagerSetSafetyLevel(Pager*,int,int);


@@ -7850,9 +7907,10 @@ SQLITE_PRIVATE void *sqlite3PagerGetData(DbPage *);
 SQLITE_PRIVATE void *sqlite3PagerGetExtra(DbPage *); 
 
 /* Functions used to manage pager transactions and savepoints. */
 SQLITE_PRIVATE void *sqlite3PagerGetExtra(DbPage *); 
 
 /* Functions used to manage pager transactions and savepoints. */

-SQLITE_PRIVATE int sqlite3PagerPagecount(Pager*, int*);
+SQLITE_PRIVATE void sqlite3PagerPagecount(Pager*, int*);

 SQLITE_PRIVATE int sqlite3PagerBegin(Pager*, int exFlag, int);
 SQLITE_PRIVATE int sqlite3PagerCommitPhaseOne(Pager*,const char *zMaster, int);
 SQLITE_PRIVATE int sqlite3PagerBegin(Pager*, int exFlag, int);
 SQLITE_PRIVATE int sqlite3PagerCommitPhaseOne(Pager*,const char *zMaster, int);

+SQLITE_PRIVATE int sqlite3PagerExclusiveLock(Pager*);

 SQLITE_PRIVATE int sqlite3PagerSync(Pager *pPager);
 SQLITE_PRIVATE int sqlite3PagerCommitPhaseTwo(Pager*);
 SQLITE_PRIVATE int sqlite3PagerRollback(Pager*);
 SQLITE_PRIVATE int sqlite3PagerSync(Pager *pPager);
 SQLITE_PRIVATE int sqlite3PagerCommitPhaseTwo(Pager*);
 SQLITE_PRIVATE int sqlite3PagerRollback(Pager*);


@@ -8444,14 +8502,6 @@ struct Db {
 
 /*
 ** An instance of the following structure stores a database schema.
 
 /*
 ** An instance of the following structure stores a database schema.

-**
-** If there are no virtual tables configured in this schema, the
-** Schema.db variable is set to NULL. After the first virtual table
-** has been added, it is set to point to the database connection 
-** used to create the connection. Once a virtual table has been
-** added to the Schema structure and the Schema.db variable populated, 
-** only that database connection may use the Schema to prepare 
-** statements.

 */
 struct Schema {
   int schema_cookie;   /* Database schema version number for this file */
 */
 struct Schema {
   int schema_cookie;   /* Database schema version number for this file */


@@ -8464,9 +8514,6 @@ struct Schema {
   u8 enc;              /* Text encoding used by this database */
   u16 flags;           /* Flags associated with this schema */
   int cache_size;      /* Number of pages to use in the cache */
   u8 enc;              /* Text encoding used by this database */
   u16 flags;           /* Flags associated with this schema */
   int cache_size;      /* Number of pages to use in the cache */

-#ifndef SQLITE_OMIT_VIRTUALTABLE
-  sqlite3 *db;         /* "Owner" connection. See comment above */
-#endif

 };
 
 /*
 };
 
 /*


@@ -8654,6 +8701,7 @@ struct sqlite3 {
   int nStatement;               /* Number of nested statement-transactions  */
   u8 isTransactionSavepoint;    /* True if the outermost savepoint is a TS */
   i64 nDeferredCons;            /* Net deferred constraints this transaction. */
   int nStatement;               /* Number of nested statement-transactions  */
   u8 isTransactionSavepoint;    /* True if the outermost savepoint is a TS */
   i64 nDeferredCons;            /* Net deferred constraints this transaction. */

+  int *pnBytesFreed;            /* If not NULL, increment this in DbFree() */

 
 #ifdef SQLITE_ENABLE_UNLOCK_NOTIFY
   /* The following variables are all protected by the STATIC_MASTER 
 
 #ifdef SQLITE_ENABLE_UNLOCK_NOTIFY
   /* The following variables are all protected by the STATIC_MASTER 


@@ -9011,7 +9059,6 @@ struct VTable {
 ** of a SELECT statement.
 */
 struct Table {
 ** of a SELECT statement.
 */
 struct Table {

-  sqlite3 *dbMem;      /* DB connection used for lookaside allocations. */

   char *zName;         /* Name of the table or view */
   int iPKey;           /* If not negative, use aCol[iPKey] as the primary key */
   int nCol;            /* Number of columns in this table */
   char *zName;         /* Name of the table or view */
   int iPKey;           /* If not negative, use aCol[iPKey] as the primary key */
   int nCol;            /* Number of columns in this table */


@@ -9148,9 +9195,9 @@ struct FKey {
 */
 struct KeyInfo {
   sqlite3 *db;        /* The database connection */
 */
 struct KeyInfo {
   sqlite3 *db;        /* The database connection */

-  u8 enc;             /* Text encoding - one of the TEXT_Utf* values */
+  u8 enc;             /* Text encoding - one of the SQLITE_UTF* values */

   u16 nField;         /* Number of entries in aColl[] */
   u16 nField;         /* Number of entries in aColl[] */

-  u8 *aSortOrder;     /* If defined an aSortOrder[i] is true, sort DESC */
+  u8 *aSortOrder;     /* Sort order for each column.  May be NULL */

   CollSeq *aColl[1];  /* Collating sequence for each term of the key */
 };
 
   CollSeq *aColl[1];  /* Collating sequence for each term of the key */
 };
 


@@ -10120,7 +10167,7 @@ struct StrAccum {
   int  nAlloc;         /* Amount of space allocated in zText */
   int  mxAlloc;        /* Maximum allowed string length */
   u8   mallocFailed;   /* Becomes true if any memory allocation fails */
   int  nAlloc;         /* Amount of space allocated in zText */
   int  mxAlloc;        /* Maximum allowed string length */
   u8   mallocFailed;   /* Becomes true if any memory allocation fails */

-  u8   useMalloc;      /* True if zText is enlargeable using realloc */
+  u8   useMalloc;      /* 0: none,  1: sqlite3DbMalloc,  2: sqlite3_malloc */

   u8   tooBig;         /* Becomes true if string size exceeds limits */
 };
 
   u8   tooBig;         /* Becomes true if string size exceeds limits */
 };
 


@@ -10418,7 +10465,7 @@ SQLITE_PRIVATE   int sqlite3ViewGetColumnNames(Parse*,Table*);
 #endif
 
 SQLITE_PRIVATE void sqlite3DropTable(Parse*, SrcList*, int, int);
 #endif
 
 SQLITE_PRIVATE void sqlite3DropTable(Parse*, SrcList*, int, int);

-SQLITE_PRIVATE void sqlite3DeleteTable(Table*);
+SQLITE_PRIVATE void sqlite3DeleteTable(sqlite3*, Table*);

 #ifndef SQLITE_OMIT_AUTOINCREMENT
 SQLITE_PRIVATE   void sqlite3AutoincrementBegin(Parse *pParse);
 SQLITE_PRIVATE   void sqlite3AutoincrementEnd(Parse *pParse);
 #ifndef SQLITE_OMIT_AUTOINCREMENT
 SQLITE_PRIVATE   void sqlite3AutoincrementBegin(Parse *pParse);
 SQLITE_PRIVATE   void sqlite3AutoincrementEnd(Parse *pParse);


@@ -10652,7 +10699,8 @@ SQLITE_PRIVATE int sqlite3ReadSchema(Parse *pParse);
 SQLITE_PRIVATE CollSeq *sqlite3FindCollSeq(sqlite3*,u8 enc, const char*,int);
 SQLITE_PRIVATE CollSeq *sqlite3LocateCollSeq(Parse *pParse, const char*zName);
 SQLITE_PRIVATE CollSeq *sqlite3ExprCollSeq(Parse *pParse, Expr *pExpr);
 SQLITE_PRIVATE CollSeq *sqlite3FindCollSeq(sqlite3*,u8 enc, const char*,int);
 SQLITE_PRIVATE CollSeq *sqlite3LocateCollSeq(Parse *pParse, const char*zName);
 SQLITE_PRIVATE CollSeq *sqlite3ExprCollSeq(Parse *pParse, Expr *pExpr);

-SQLITE_PRIVATE Expr *sqlite3ExprSetColl(Parse *pParse, Expr *, Token *);
+SQLITE_PRIVATE Expr *sqlite3ExprSetColl(Expr*, CollSeq*);
+SQLITE_PRIVATE Expr *sqlite3ExprSetCollByToken(Parse *pParse, Expr*, Token*);

 SQLITE_PRIVATE int sqlite3CheckCollSeq(Parse *, CollSeq *);
 SQLITE_PRIVATE int sqlite3CheckObjectName(Parse *, const char *);
 SQLITE_PRIVATE void sqlite3VdbeSetChanges(sqlite3 *, int);
 SQLITE_PRIVATE int sqlite3CheckCollSeq(Parse *, CollSeq *);
 SQLITE_PRIVATE int sqlite3CheckObjectName(Parse *, const char *);
 SQLITE_PRIVATE void sqlite3VdbeSetChanges(sqlite3 *, int);


@@ -10702,7 +10750,7 @@ SQLITE_PRIVATE int sqlite3InvokeBusyHandler(BusyHandler*);
 SQLITE_PRIVATE int sqlite3FindDb(sqlite3*, Token*);
 SQLITE_PRIVATE int sqlite3FindDbName(sqlite3 *, const char *);
 SQLITE_PRIVATE int sqlite3AnalysisLoad(sqlite3*,int iDB);
 SQLITE_PRIVATE int sqlite3FindDb(sqlite3*, Token*);
 SQLITE_PRIVATE int sqlite3FindDbName(sqlite3 *, const char *);
 SQLITE_PRIVATE int sqlite3AnalysisLoad(sqlite3*,int iDB);

-SQLITE_PRIVATE void sqlite3DeleteIndexSamples(Index*);
+SQLITE_PRIVATE void sqlite3DeleteIndexSamples(sqlite3*,Index*);

 SQLITE_PRIVATE void sqlite3DefaultRowEst(Index*);
 SQLITE_PRIVATE void sqlite3RegisterLikeFunctions(sqlite3*, int);
 SQLITE_PRIVATE int sqlite3IsLikeFunction(sqlite3*,Expr*,int*,char*);
 SQLITE_PRIVATE void sqlite3DefaultRowEst(Index*);
 SQLITE_PRIVATE void sqlite3RegisterLikeFunctions(sqlite3*, int);
 SQLITE_PRIVATE int sqlite3IsLikeFunction(sqlite3*,Expr*,int*,char*);


@@ -10764,7 +10812,7 @@ SQLITE_PRIVATE   int sqlite3Utf8To8(unsigned char*);
 #  define sqlite3VtabUnlock(X)
 #  define sqlite3VtabUnlockList(X)
 #else
 #  define sqlite3VtabUnlock(X)
 #  define sqlite3VtabUnlockList(X)
 #else

-SQLITE_PRIVATE    void sqlite3VtabClear(Table*);
+SQLITE_PRIVATE    void sqlite3VtabClear(sqlite3 *db, Table*);

 SQLITE_PRIVATE    int sqlite3VtabSync(sqlite3 *db, char **);
 SQLITE_PRIVATE    int sqlite3VtabRollback(sqlite3 *db);
 SQLITE_PRIVATE    int sqlite3VtabCommit(sqlite3 *db);
 SQLITE_PRIVATE    int sqlite3VtabSync(sqlite3 *db, char **);
 SQLITE_PRIVATE    int sqlite3VtabRollback(sqlite3 *db);
 SQLITE_PRIVATE    int sqlite3VtabCommit(sqlite3 *db);


@@ -10817,9 +10865,9 @@ SQLITE_PRIVATE   FKey *sqlite3FkReferences(Table *);
   #define sqlite3FkRequired(a,b,c,d) 0
 #endif
 #ifndef SQLITE_OMIT_FOREIGN_KEY
   #define sqlite3FkRequired(a,b,c,d) 0
 #endif
 #ifndef SQLITE_OMIT_FOREIGN_KEY

-SQLITE_PRIVATE   void sqlite3FkDelete(Table*);
+SQLITE_PRIVATE   void sqlite3FkDelete(sqlite3 *, Table*);

 #else
 #else

-  #define sqlite3FkDelete(a)
+  #define sqlite3FkDelete(a,b)

 #endif
 
 
 #endif
 
 


@@ -10912,17 +10960,18 @@ SQLITE_PRIVATE void (*sqlite3IoTrace)(const char*,...);
 ** sqlite3MemdebugHasType() returns true if any of the bits in its second
 ** argument match the type set by the previous sqlite3MemdebugSetType().
 ** sqlite3MemdebugHasType() is intended for use inside assert() statements.
 ** sqlite3MemdebugHasType() returns true if any of the bits in its second
 ** argument match the type set by the previous sqlite3MemdebugSetType().
 ** sqlite3MemdebugHasType() is intended for use inside assert() statements.

-** For example:

 **
 **

-**     assert( sqlite3MemdebugHasType(p, MEMTYPE_HEAP) );
+** sqlite3MemdebugNoType() returns true if none of the bits in its second
+** argument match the type set by the previous sqlite3MemdebugSetType().

 **
 ** Perhaps the most important point is the difference between MEMTYPE_HEAP
 **
 ** Perhaps the most important point is the difference between MEMTYPE_HEAP

-** and MEMTYPE_DB.  If an allocation is MEMTYPE_DB, that means it might have
-** been allocated by lookaside, except the allocation was too large or
-** lookaside was already full.  It is important to verify that allocations
-** that might have been satisfied by lookaside are not passed back to 
-** non-lookaside free() routines.  Asserts such as the example above are
-** placed on the non-lookaside free() routines to verify this constraint. 
+** and MEMTYPE_LOOKASIDE.  If an allocation is MEMTYPE_LOOKASIDE, that means
+** it might have been allocated by lookaside, except the allocation was
+** too large or lookaside was already full.  It is important to verify
+** that allocations that might have been satisfied by lookaside are not
+** passed back to non-lookaside free() routines.  Asserts such as the
+** example above are placed on the non-lookaside free() routines to verify
+** this constraint. 

 **
 ** All of this is no-op for a production build.  It only comes into
 ** play when the SQLITE_MEMDEBUG compile-time option is used.
 **
 ** All of this is no-op for a production build.  It only comes into
 ** play when the SQLITE_MEMDEBUG compile-time option is used.


@@ -10930,14 +10979,17 @@ SQLITE_PRIVATE void (*sqlite3IoTrace)(const char*,...);
 #ifdef SQLITE_MEMDEBUG
 SQLITE_PRIVATE   void sqlite3MemdebugSetType(void*,u8);
 SQLITE_PRIVATE   int sqlite3MemdebugHasType(void*,u8);
 #ifdef SQLITE_MEMDEBUG
 SQLITE_PRIVATE   void sqlite3MemdebugSetType(void*,u8);
 SQLITE_PRIVATE   int sqlite3MemdebugHasType(void*,u8);

+SQLITE_PRIVATE   int sqlite3MemdebugNoType(void*,u8);

 #else
 # define sqlite3MemdebugSetType(X,Y)  /* no-op */
 # define sqlite3MemdebugHasType(X,Y)  1
 #else
 # define sqlite3MemdebugSetType(X,Y)  /* no-op */
 # define sqlite3MemdebugHasType(X,Y)  1

+# define sqlite3MemdebugNoType(X,Y)   1

 #endif
 #endif

-#define MEMTYPE_HEAP     0x01    /* General heap allocations */
-#define MEMTYPE_DB       0x02    /* Associated with a database connection */
-#define MEMTYPE_SCRATCH  0x04    /* Scratch allocations */
-#define MEMTYPE_PCACHE   0x08    /* Page cache allocations */
+#define MEMTYPE_HEAP       0x01  /* General heap allocations */
+#define MEMTYPE_LOOKASIDE  0x02  /* Might have been lookaside memory */
+#define MEMTYPE_SCRATCH    0x04  /* Scratch allocations */
+#define MEMTYPE_PCACHE     0x08  /* Page cache allocations */
+#define MEMTYPE_DB         0x10  /* Uses sqlite3DbMalloc, not sqlite_malloc */

 
 #endif /* _SQLITEINT_H_ */
 
 
 #endif /* _SQLITEINT_H_ */
 


@@ -11568,14 +11620,438 @@ SQLITE_API const char *sqlite3_compileoption_get(int N){
 ** This module implements the sqlite3_status() interface and related
 ** functionality.
 */
 ** This module implements the sqlite3_status() interface and related
 ** functionality.
 */

+/************** Include vdbeInt.h in the middle of status.c ******************/
+/************** Begin file vdbeInt.h *****************************************/
+/*
+** 2003 September 6
+**
+** The author disclaims copyright to this source code.  In place of
+** a legal notice, here is a blessing:
+**
+**    May you do good and not evil.
+**    May you find forgiveness for yourself and forgive others.
+**    May you share freely, never taking more than you give.
+**
+*************************************************************************
+** This is the header file for information that is private to the
+** VDBE.  This information used to all be at the top of the single
+** source code file "vdbe.c".  When that file became too big (over
+** 6000 lines long) it was split up into several smaller files and
+** this header information was factored out.
+*/
+#ifndef _VDBEINT_H_
+#define _VDBEINT_H_
+
+/*
+** SQL is translated into a sequence of instructions to be
+** executed by a virtual machine.  Each instruction is an instance
+** of the following structure.
+*/
+typedef struct VdbeOp Op;
+
+/*
+** Boolean values
+*/
+typedef unsigned char Bool;
+
+/*
+** A cursor is a pointer into a single BTree within a database file.
+** The cursor can seek to a BTree entry with a particular key, or
+** loop over all entries of the Btree.  You can also insert new BTree
+** entries or retrieve the key or data from the entry that the cursor
+** is currently pointing to.
+** 
+** Every cursor that the virtual machine has open is represented by an
+** instance of the following structure.
+**
+** If the VdbeCursor.isTriggerRow flag is set it means that this cursor is
+** really a single row that represents the NEW or OLD pseudo-table of
+** a row trigger.  The data for the row is stored in VdbeCursor.pData and
+** the rowid is in VdbeCursor.iKey.
+*/
+struct VdbeCursor {
+  BtCursor *pCursor;    /* The cursor structure of the backend */
+  int iDb;              /* Index of cursor database in db->aDb[] (or -1) */
+  i64 lastRowid;        /* Last rowid from a Next or NextIdx operation */
+  Bool zeroed;          /* True if zeroed out and ready for reuse */
+  Bool rowidIsValid;    /* True if lastRowid is valid */
+  Bool atFirst;         /* True if pointing to first entry */
+  Bool useRandomRowid;  /* Generate new record numbers semi-randomly */
+  Bool nullRow;         /* True if pointing to a row with no data */
+  Bool deferredMoveto;  /* A call to sqlite3BtreeMoveto() is needed */
+  Bool isTable;         /* True if a table requiring integer keys */
+  Bool isIndex;         /* True if an index containing keys only - no data */
+  i64 movetoTarget;     /* Argument to the deferred sqlite3BtreeMoveto() */
+  Btree *pBt;           /* Separate file holding temporary table */
+  int pseudoTableReg;   /* Register holding pseudotable content. */
+  KeyInfo *pKeyInfo;    /* Info about index keys needed by index cursors */
+  int nField;           /* Number of fields in the header */
+  i64 seqCount;         /* Sequence counter */
+  sqlite3_vtab_cursor *pVtabCursor;  /* The cursor for a virtual table */
+  const sqlite3_module *pModule;     /* Module for cursor pVtabCursor */
+
+  /* Result of last sqlite3BtreeMoveto() done by an OP_NotExists or 
+  ** OP_IsUnique opcode on this cursor. */
+  int seekResult;
+
+  /* Cached information about the header for the data record that the
+  ** cursor is currently pointing to.  Only valid if cacheStatus matches
+  ** Vdbe.cacheCtr.  Vdbe.cacheCtr will never take on the value of
+  ** CACHE_STALE and so setting cacheStatus=CACHE_STALE guarantees that
+  ** the cache is out of date.
+  **
+  ** aRow might point to (ephemeral) data for the current row, or it might
+  ** be NULL.
+  */
+  u32 cacheStatus;      /* Cache is valid if this matches Vdbe.cacheCtr */
+  int payloadSize;      /* Total number of bytes in the record */
+  u32 *aType;           /* Type values for all entries in the record */
+  u32 *aOffset;         /* Cached offsets to the start of each columns data */
+  u8 *aRow;             /* Data for the current row, if all on one page */
+};
+typedef struct VdbeCursor VdbeCursor;
+
+/*
+** When a sub-program is executed (OP_Program), a structure of this type
+** is allocated to store the current value of the program counter, as
+** well as the current memory cell array and various other frame specific
+** values stored in the Vdbe struct. When the sub-program is finished, 
+** these values are copied back to the Vdbe from the VdbeFrame structure,
+** restoring the state of the VM to as it was before the sub-program
+** began executing.
+**
+** Frames are stored in a linked list headed at Vdbe.pParent. Vdbe.pParent
+** is the parent of the current frame, or zero if the current frame
+** is the main Vdbe program.
+*/
+typedef struct VdbeFrame VdbeFrame;
+struct VdbeFrame {
+  Vdbe *v;                /* VM this frame belongs to */
+  int pc;                 /* Program Counter */
+  Op *aOp;                /* Program instructions */
+  int nOp;                /* Size of aOp array */
+  Mem *aMem;              /* Array of memory cells */
+  int nMem;               /* Number of entries in aMem */
+  VdbeCursor **apCsr;     /* Element of Vdbe cursors */
+  u16 nCursor;            /* Number of entries in apCsr */
+  void *token;            /* Copy of SubProgram.token */
+  int nChildMem;          /* Number of memory cells for child frame */
+  int nChildCsr;          /* Number of cursors for child frame */
+  i64 lastRowid;          /* Last insert rowid (sqlite3.lastRowid) */
+  int nChange;            /* Statement changes (Vdbe.nChanges)     */
+  VdbeFrame *pParent;     /* Parent of this frame */
+};
+
+#define VdbeFrameMem(p) ((Mem *)&((u8 *)p)[ROUND8(sizeof(VdbeFrame))])
+
+/*
+** A value for VdbeCursor.cacheValid that means the cache is always invalid.
+*/
+#define CACHE_STALE 0
+
+/*
+** Internally, the vdbe manipulates nearly all SQL values as Mem
+** structures. Each Mem struct may cache multiple representations (string,
+** integer etc.) of the same value.  A value (and therefore Mem structure)
+** has the following properties:
+**
+** Each value has a manifest type. The manifest type of the value stored
+** in a Mem struct is returned by the MemType(Mem*) macro. The type is
+** one of SQLITE_NULL, SQLITE_INTEGER, SQLITE_REAL, SQLITE_TEXT or
+** SQLITE_BLOB.
+*/
+struct Mem {
+  union {
+    i64 i;              /* Integer value. */
+    int nZero;          /* Used when bit MEM_Zero is set in flags */
+    FuncDef *pDef;      /* Used only when flags==MEM_Agg */
+    RowSet *pRowSet;    /* Used only when flags==MEM_RowSet */
+    VdbeFrame *pFrame;  /* Used when flags==MEM_Frame */
+  } u;
+  double r;           /* Real value */
+  sqlite3 *db;        /* The associated database connection */
+  char *z;            /* String or BLOB value */
+  int n;              /* Number of characters in string value, excluding '\0' */
+  u16 flags;          /* Some combination of MEM_Null, MEM_Str, MEM_Dyn, etc. */
+  u8  type;           /* One of SQLITE_NULL, SQLITE_TEXT, SQLITE_INTEGER, etc */
+  u8  enc;            /* SQLITE_UTF8, SQLITE_UTF16BE, SQLITE_UTF16LE */
+  void (*xDel)(void *);  /* If not null, call this function to delete Mem.z */
+  char *zMalloc;      /* Dynamic buffer allocated by sqlite3_malloc() */
+};
+
+/* One or more of the following flags are set to indicate the validOK
+** representations of the value stored in the Mem struct.
+**
+** If the MEM_Null flag is set, then the value is an SQL NULL value.
+** No other flags may be set in this case.
+**
+** If the MEM_Str flag is set then Mem.z points at a string representation.
+** Usually this is encoded in the same unicode encoding as the main
+** database (see below for exceptions). If the MEM_Term flag is also
+** set, then the string is nul terminated. The MEM_Int and MEM_Real 
+** flags may coexist with the MEM_Str flag.
+**
+** Multiple of these values can appear in Mem.flags.  But only one
+** at a time can appear in Mem.type.
+*/
+#define MEM_Null      0x0001   /* Value is NULL */
+#define MEM_Str       0x0002   /* Value is a string */
+#define MEM_Int       0x0004   /* Value is an integer */
+#define MEM_Real      0x0008   /* Value is a real number */
+#define MEM_Blob      0x0010   /* Value is a BLOB */
+#define MEM_RowSet    0x0020   /* Value is a RowSet object */
+#define MEM_Frame     0x0040   /* Value is a VdbeFrame object */
+#define MEM_TypeMask  0x00ff   /* Mask of type bits */
+
+/* Whenever Mem contains a valid string or blob representation, one of
+** the following flags must be set to determine the memory management
+** policy for Mem.z.  The MEM_Term flag tells us whether or not the
+** string is \000 or \u0000 terminated
+*/
+#define MEM_Term      0x0200   /* String rep is nul terminated */
+#define MEM_Dyn       0x0400   /* Need to call sqliteFree() on Mem.z */
+#define MEM_Static    0x0800   /* Mem.z points to a static string */
+#define MEM_Ephem     0x1000   /* Mem.z points to an ephemeral string */
+#define MEM_Agg       0x2000   /* Mem.z points to an agg function context */
+#define MEM_Zero      0x4000   /* Mem.i contains count of 0s appended to blob */
+
+#ifdef SQLITE_OMIT_INCRBLOB
+  #undef MEM_Zero
+  #define MEM_Zero 0x0000
+#endif
+
+
+/*
+** Clear any existing type flags from a Mem and replace them with f
+*/
+#define MemSetTypeFlag(p, f) \
+   ((p)->flags = ((p)->flags&~(MEM_TypeMask|MEM_Zero))|f)
+
+
+/* A VdbeFunc is just a FuncDef (defined in sqliteInt.h) that contains
+** additional information about auxiliary information bound to arguments
+** of the function.  This is used to implement the sqlite3_get_auxdata()
+** and sqlite3_set_auxdata() APIs.  The "auxdata" is some auxiliary data
+** that can be associated with a constant argument to a function.  This
+** allows functions such as "regexp" to compile their constant regular
+** expression argument once and reused the compiled code for multiple
+** invocations.
+*/
+struct VdbeFunc {
+  FuncDef *pFunc;               /* The definition of the function */
+  int nAux;                     /* Number of entries allocated for apAux[] */
+  struct AuxData {
+    void *pAux;                   /* Aux data for the i-th argument */
+    void (*xDelete)(void *);      /* Destructor for the aux data */
+  } apAux[1];                   /* One slot for each function argument */
+};
+
+/*
+** The "context" argument for a installable function.  A pointer to an
+** instance of this structure is the first argument to the routines used
+** implement the SQL functions.
+**
+** There is a typedef for this structure in sqlite.h.  So all routines,
+** even the public interface to SQLite, can use a pointer to this structure.
+** But this file is the only place where the internal details of this
+** structure are known.
+**
+** This structure is defined inside of vdbeInt.h because it uses substructures
+** (Mem) which are only defined there.
+*/
+struct sqlite3_context {
+  FuncDef *pFunc;       /* Pointer to function information.  MUST BE FIRST */
+  VdbeFunc *pVdbeFunc;  /* Auxilary data, if created. */
+  Mem s;                /* The return value is stored here */
+  Mem *pMem;            /* Memory cell used to store aggregate context */
+  int isError;          /* Error code returned by the function. */
+  CollSeq *pColl;       /* Collating sequence */
+};
+
+/*
+** A Set structure is used for quick testing to see if a value
+** is part of a small set.  Sets are used to implement code like
+** this:
+**            x.y IN ('hi','hoo','hum')
+*/
+typedef struct Set Set;
+struct Set {
+  Hash hash;             /* A set is just a hash table */
+  HashElem *prev;        /* Previously accessed hash elemen */
+};
+
+/*
+** An instance of the virtual machine.  This structure contains the complete
+** state of the virtual machine.
+**
+** The "sqlite3_stmt" structure pointer that is returned by sqlite3_compile()
+** is really a pointer to an instance of this structure.
+**
+** The Vdbe.inVtabMethod variable is set to non-zero for the duration of
+** any virtual table method invocations made by the vdbe program. It is
+** set to 2 for xDestroy method calls and 1 for all other methods. This
+** variable is used for two purposes: to allow xDestroy methods to execute
+** "DROP TABLE" statements and to prevent some nasty side effects of
+** malloc failure when SQLite is invoked recursively by a virtual table 
+** method function.
+*/
+struct Vdbe {
+  sqlite3 *db;            /* The database connection that owns this statement */
+  Vdbe *pPrev,*pNext;     /* Linked list of VDBEs with the same Vdbe.db */
+  int nOp;                /* Number of instructions in the program */
+  int nOpAlloc;           /* Number of slots allocated for aOp[] */
+  Op *aOp;                /* Space to hold the virtual machine's program */
+  int nLabel;             /* Number of labels used */
+  int nLabelAlloc;        /* Number of slots allocated in aLabel[] */
+  int *aLabel;            /* Space to hold the labels */
+  Mem **apArg;            /* Arguments to currently executing user function */
+  Mem *aColName;          /* Column names to return */
+  Mem *pResultSet;        /* Pointer to an array of results */
+  u16 nResColumn;         /* Number of columns in one row of the result set */
+  u16 nCursor;            /* Number of slots in apCsr[] */
+  VdbeCursor **apCsr;     /* One element of this array for each open cursor */
+  u8 errorAction;         /* Recovery action to do in case of an error */
+  u8 okVar;               /* True if azVar[] has been initialized */
+  ynVar nVar;             /* Number of entries in aVar[] */
+  Mem *aVar;              /* Values for the OP_Variable opcode. */
+  char **azVar;           /* Name of variables */
+  u32 magic;              /* Magic number for sanity checking */
+  int nMem;               /* Number of memory locations currently allocated */
+  Mem *aMem;              /* The memory locations */
+  u32 cacheCtr;           /* VdbeCursor row cache generation counter */
+  int pc;                 /* The program counter */
+  int rc;                 /* Value to return */
+  char *zErrMsg;          /* Error message written here */
+  u8 explain;             /* True if EXPLAIN present on SQL command */
+  u8 changeCntOn;         /* True to update the change-counter */
+  u8 expired;             /* True if the VM needs to be recompiled */
+  u8 runOnlyOnce;         /* Automatically expire on reset */
+  u8 minWriteFileFormat;  /* Minimum file format for writable database files */
+  u8 inVtabMethod;        /* See comments above */
+  u8 usesStmtJournal;     /* True if uses a statement journal */
+  u8 readOnly;            /* True for read-only statements */
+  u8 isPrepareV2;         /* True if prepared with prepare_v2() */
+  int nChange;            /* Number of db changes made since last reset */
+  int btreeMask;          /* Bitmask of db->aDb[] entries referenced */
+  i64 startTime;          /* Time when query started - used for profiling */
+  BtreeMutexArray aMutex; /* An array of Btree used here and needing locks */
+  int aCounter[3];        /* Counters used by sqlite3_stmt_status() */
+  char *zSql;             /* Text of the SQL statement that generated this */
+  void *pFree;            /* Free this when deleting the vdbe */
+  i64 nFkConstraint;      /* Number of imm. FK constraints this VM */
+  i64 nStmtDefCons;       /* Number of def. constraints when stmt started */
+  int iStatement;         /* Statement number (or 0 if has not opened stmt) */
+#ifdef SQLITE_DEBUG
+  FILE *trace;            /* Write an execution trace here, if not NULL */
+#endif
+  VdbeFrame *pFrame;      /* Parent frame */
+  int nFrame;             /* Number of frames in pFrame list */
+  u32 expmask;            /* Binding to these vars invalidates VM */
+  SubProgram *pProgram;   /* Linked list of all sub-programs used by VM */
+};
+
+/*
+** The following are allowed values for Vdbe.magic
+*/
+#define VDBE_MAGIC_INIT     0x26bceaa5    /* Building a VDBE program */
+#define VDBE_MAGIC_RUN      0xbdf20da3    /* VDBE is ready to execute */
+#define VDBE_MAGIC_HALT     0x519c2973    /* VDBE has completed execution */
+#define VDBE_MAGIC_DEAD     0xb606c3c8    /* The VDBE has been deallocated */
+
+/*
+** Function prototypes
+*/
+SQLITE_PRIVATE void sqlite3VdbeFreeCursor(Vdbe *, VdbeCursor*);
+void sqliteVdbePopStack(Vdbe*,int);
+SQLITE_PRIVATE int sqlite3VdbeCursorMoveto(VdbeCursor*);
+#if defined(SQLITE_DEBUG) || defined(VDBE_PROFILE)
+SQLITE_PRIVATE void sqlite3VdbePrintOp(FILE*, int, Op*);
+#endif
+SQLITE_PRIVATE u32 sqlite3VdbeSerialTypeLen(u32);
+SQLITE_PRIVATE u32 sqlite3VdbeSerialType(Mem*, int);
+SQLITE_PRIVATE u32 sqlite3VdbeSerialPut(unsigned char*, int, Mem*, int);
+SQLITE_PRIVATE u32 sqlite3VdbeSerialGet(const unsigned char*, u32, Mem*);
+SQLITE_PRIVATE void sqlite3VdbeDeleteAuxData(VdbeFunc*, int);
+
+int sqlite2BtreeKeyCompare(BtCursor *, const void *, int, int, int *);
+SQLITE_PRIVATE int sqlite3VdbeIdxKeyCompare(VdbeCursor*,UnpackedRecord*,int*);
+SQLITE_PRIVATE int sqlite3VdbeIdxRowid(sqlite3*, BtCursor *, i64 *);
+SQLITE_PRIVATE int sqlite3MemCompare(const Mem*, const Mem*, const CollSeq*);
+SQLITE_PRIVATE int sqlite3VdbeExec(Vdbe*);
+SQLITE_PRIVATE int sqlite3VdbeList(Vdbe*);
+SQLITE_PRIVATE int sqlite3VdbeHalt(Vdbe*);
+SQLITE_PRIVATE int sqlite3VdbeChangeEncoding(Mem *, int);
+SQLITE_PRIVATE int sqlite3VdbeMemTooBig(Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemCopy(Mem*, const Mem*);
+SQLITE_PRIVATE void sqlite3VdbeMemShallowCopy(Mem*, const Mem*, int);
+SQLITE_PRIVATE void sqlite3VdbeMemMove(Mem*, Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemNulTerminate(Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemSetStr(Mem*, const char*, int, u8, void(*)(void*));
+SQLITE_PRIVATE void sqlite3VdbeMemSetInt64(Mem*, i64);
+#ifdef SQLITE_OMIT_FLOATING_POINT
+# define sqlite3VdbeMemSetDouble sqlite3VdbeMemSetInt64
+#else
+SQLITE_PRIVATE   void sqlite3VdbeMemSetDouble(Mem*, double);
+#endif
+SQLITE_PRIVATE void sqlite3VdbeMemSetNull(Mem*);
+SQLITE_PRIVATE void sqlite3VdbeMemSetZeroBlob(Mem*,int);
+SQLITE_PRIVATE void sqlite3VdbeMemSetRowSet(Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemMakeWriteable(Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemStringify(Mem*, int);
+SQLITE_PRIVATE i64 sqlite3VdbeIntValue(Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemIntegerify(Mem*);
+SQLITE_PRIVATE double sqlite3VdbeRealValue(Mem*);
+SQLITE_PRIVATE void sqlite3VdbeIntegerAffinity(Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemRealify(Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemNumerify(Mem*);
+SQLITE_PRIVATE int sqlite3VdbeMemFromBtree(BtCursor*,int,int,int,Mem*);
+SQLITE_PRIVATE void sqlite3VdbeMemRelease(Mem *p);
+SQLITE_PRIVATE void sqlite3VdbeMemReleaseExternal(Mem *p);
+SQLITE_PRIVATE int sqlite3VdbeMemFinalize(Mem*, FuncDef*);
+SQLITE_PRIVATE const char *sqlite3OpcodeName(int);
+SQLITE_PRIVATE int sqlite3VdbeMemGrow(Mem *pMem, int n, int preserve);
+SQLITE_PRIVATE int sqlite3VdbeCloseStatement(Vdbe *, int);
+SQLITE_PRIVATE void sqlite3VdbeFrameDelete(VdbeFrame*);
+SQLITE_PRIVATE int sqlite3VdbeFrameRestore(VdbeFrame *);
+SQLITE_PRIVATE void sqlite3VdbeMemStoreType(Mem *pMem);
+
+#ifndef SQLITE_OMIT_FOREIGN_KEY
+SQLITE_PRIVATE int sqlite3VdbeCheckFk(Vdbe *, int);
+#else
+# define sqlite3VdbeCheckFk(p,i) 0
+#endif
+
+#ifndef SQLITE_OMIT_SHARED_CACHE
+SQLITE_PRIVATE void sqlite3VdbeMutexArrayEnter(Vdbe *p);
+#else
+# define sqlite3VdbeMutexArrayEnter(p)
+#endif
+
+SQLITE_PRIVATE int sqlite3VdbeMemTranslate(Mem*, u8);
+#ifdef SQLITE_DEBUG
+SQLITE_PRIVATE   void sqlite3VdbePrintSql(Vdbe*);
+SQLITE_PRIVATE   void sqlite3VdbeMemPrettyPrint(Mem *pMem, char *zBuf);
+#endif
+SQLITE_PRIVATE int sqlite3VdbeMemHandleBom(Mem *pMem);
+
+#ifndef SQLITE_OMIT_INCRBLOB
+SQLITE_PRIVATE   int sqlite3VdbeMemExpandBlob(Mem *);
+#else
+  #define sqlite3VdbeMemExpandBlob(x) SQLITE_OK
+#endif
+
+#endif /* !defined(_VDBEINT_H_) */
+
+/************** End of vdbeInt.h *********************************************/
+/************** Continuing where we left off in status.c *********************/

 
 /*
 ** Variables in which to record status information.
 */
 typedef struct sqlite3StatType sqlite3StatType;
 static SQLITE_WSD struct sqlite3StatType {
 
 /*
 ** Variables in which to record status information.
 */
 typedef struct sqlite3StatType sqlite3StatType;
 static SQLITE_WSD struct sqlite3StatType {

-  int nowValue[9];         /* Current value */
-  int mxValue[9];          /* Maximum value */
+  int nowValue[10];         /* Current value */
+  int mxValue[10];          /* Maximum value */

 } sqlite3Stat = { {0,}, {0,} };
 
 
 } sqlite3Stat = { {0,}, {0,} };
 
 


@@ -11657,6 +12133,8 @@ SQLITE_API int sqlite3_db_status(
   int *pHighwater,      /* Write high-water mark here */
   int resetFlag         /* Reset high-water mark if true */
 ){
   int *pHighwater,      /* Write high-water mark here */
   int resetFlag         /* Reset high-water mark if true */
 ){

+  int rc = SQLITE_OK;   /* Return code */
+  sqlite3_mutex_enter(db->mutex);

   switch( op ){
     case SQLITE_DBSTATUS_LOOKASIDE_USED: {
       *pCurrent = db->lookaside.nOut;
   switch( op ){
     case SQLITE_DBSTATUS_LOOKASIDE_USED: {
       *pCurrent = db->lookaside.nOut;


@@ -11675,6 +12153,7 @@ SQLITE_API int sqlite3_db_status(
     case SQLITE_DBSTATUS_CACHE_USED: {
       int totalUsed = 0;
       int i;
     case SQLITE_DBSTATUS_CACHE_USED: {
       int totalUsed = 0;
       int i;

+      sqlite3BtreeEnterAll(db);

       for(i=0; i<db->nDb; i++){
         Btree *pBt = db->aDb[i].pBt;
         if( pBt ){
       for(i=0; i<db->nDb; i++){
         Btree *pBt = db->aDb[i].pBt;
         if( pBt ){


@@ -11682,15 +12161,80 @@ SQLITE_API int sqlite3_db_status(
           totalUsed += sqlite3PagerMemUsed(pPager);
         }
       }
           totalUsed += sqlite3PagerMemUsed(pPager);
         }
       }

+      sqlite3BtreeLeaveAll(db);

       *pCurrent = totalUsed;
       *pHighwater = 0;
       break;
     }
       *pCurrent = totalUsed;
       *pHighwater = 0;
       break;
     }

+
+    /*
+    ** *pCurrent gets an accurate estimate of the amount of memory used
+    ** to store the schema for all databases (main, temp, and any ATTACHed
+    ** databases.  *pHighwater is set to zero.
+    */
+    case SQLITE_DBSTATUS_SCHEMA_USED: {
+      int i;                      /* Used to iterate through schemas */
+      int nByte = 0;              /* Used to accumulate return value */
+
+      db->pnBytesFreed = &nByte;
+      for(i=0; i<db->nDb; i++){
+        Schema *pSchema = db->aDb[i].pSchema;
+        if( ALWAYS(pSchema!=0) ){
+          HashElem *p;
+
+          nByte += sqlite3GlobalConfig.m.xRoundup(sizeof(HashElem)) * (
+              pSchema->tblHash.count 
+            + pSchema->trigHash.count
+            + pSchema->idxHash.count
+            + pSchema->fkeyHash.count
+          );
+          nByte += sqlite3MallocSize(pSchema->tblHash.ht);
+          nByte += sqlite3MallocSize(pSchema->trigHash.ht);
+          nByte += sqlite3MallocSize(pSchema->idxHash.ht);
+          nByte += sqlite3MallocSize(pSchema->fkeyHash.ht);
+
+          for(p=sqliteHashFirst(&pSchema->trigHash); p; p=sqliteHashNext(p)){
+            sqlite3DeleteTrigger(db, (Trigger*)sqliteHashData(p));
+          }
+          for(p=sqliteHashFirst(&pSchema->tblHash); p; p=sqliteHashNext(p)){
+            sqlite3DeleteTable(db, (Table *)sqliteHashData(p));
+          }
+        }
+      }
+      db->pnBytesFreed = 0;
+
+      *pHighwater = 0;
+      *pCurrent = nByte;
+      break;
+    }
+
+    /*
+    ** *pCurrent gets an accurate estimate of the amount of memory used
+    ** to store all prepared statements.
+    ** *pHighwater is set to zero.
+    */
+    case SQLITE_DBSTATUS_STMT_USED: {
+      struct Vdbe *pVdbe;         /* Used to iterate through VMs */
+      int nByte = 0;              /* Used to accumulate return value */
+
+      db->pnBytesFreed = &nByte;
+      for(pVdbe=db->pVdbe; pVdbe; pVdbe=pVdbe->pNext){
+        sqlite3VdbeDeleteObject(db, pVdbe);
+      }
+      db->pnBytesFreed = 0;
+
+      *pHighwater = 0;
+      *pCurrent = nByte;
+
+      break;
+    }
+

     default: {
     default: {

-      return SQLITE_ERROR;
+      rc = SQLITE_ERROR;

     }
   }
     }
   }

-  return SQLITE_OK;
+  sqlite3_mutex_leave(db->mutex);
+  return rc;

 }
 
 /************** End of status.c **********************************************/
 }
 
 /************** End of status.c **********************************************/


@@ -13799,7 +14343,7 @@ SQLITE_PRIVATE void sqlite3MemSetDefault(void){
 ** Set the "type" of an allocation.
 */
 SQLITE_PRIVATE void sqlite3MemdebugSetType(void *p, u8 eType){
 ** Set the "type" of an allocation.
 */
 SQLITE_PRIVATE void sqlite3MemdebugSetType(void *p, u8 eType){

-  if( p ){
+  if( p && sqlite3GlobalConfig.m.xMalloc==sqlite3MemMalloc ){

     struct MemBlockHdr *pHdr;
     pHdr = sqlite3MemsysGetHeader(p);
     assert( pHdr->iForeGuard==FOREGUARD );
     struct MemBlockHdr *pHdr;
     pHdr = sqlite3MemsysGetHeader(p);
     assert( pHdr->iForeGuard==FOREGUARD );


@@ -13818,23 +14362,38 @@ SQLITE_PRIVATE void sqlite3MemdebugSetType(void *p, u8 eType){
 */
 SQLITE_PRIVATE int sqlite3MemdebugHasType(void *p, u8 eType){
   int rc = 1;
 */
 SQLITE_PRIVATE int sqlite3MemdebugHasType(void *p, u8 eType){
   int rc = 1;

-  if( p ){
+  if( p && sqlite3GlobalConfig.m.xMalloc==sqlite3MemMalloc ){

     struct MemBlockHdr *pHdr;
     pHdr = sqlite3MemsysGetHeader(p);
     assert( pHdr->iForeGuard==FOREGUARD );         /* Allocation is valid */
     struct MemBlockHdr *pHdr;
     pHdr = sqlite3MemsysGetHeader(p);
     assert( pHdr->iForeGuard==FOREGUARD );         /* Allocation is valid */

-    assert( (pHdr->eType & (pHdr->eType-1))==0 );  /* Only one type bit set */

     if( (pHdr->eType&eType)==0 ){
     if( (pHdr->eType&eType)==0 ){

-      void **pBt;
-      pBt = (void**)pHdr;
-      pBt -= pHdr->nBacktraceSlots;
-      backtrace_symbols_fd(pBt, pHdr->nBacktrace, fileno(stderr));
-      fprintf(stderr, "\n");

       rc = 0;
     }
   }
   return rc;
 }
       rc = 0;
     }
   }
   return rc;
 }

- 
+
+/*
+** Return TRUE if the mask of type in eType matches no bits of the type of the
+** allocation p.  Also return true if p==NULL.
+**
+** This routine is designed for use within an assert() statement, to
+** verify the type of an allocation.  For example:
+**
+**     assert( sqlite3MemdebugNoType(p, MEMTYPE_DB) );
+*/
+SQLITE_PRIVATE int sqlite3MemdebugNoType(void *p, u8 eType){
+  int rc = 1;
+  if( p && sqlite3GlobalConfig.m.xMalloc==sqlite3MemMalloc ){
+    struct MemBlockHdr *pHdr;
+    pHdr = sqlite3MemsysGetHeader(p);
+    assert( pHdr->iForeGuard==FOREGUARD );         /* Allocation is valid */
+    if( (pHdr->eType&eType)!=0 ){
+      rc = 0;
+    }
+  }
+  return rc;
+}

 
 /*
 ** Set the number of backtrace levels kept for each allocation.
 
 /*
 ** Set the number of backtrace levels kept for each allocation.


@@ -16077,6 +16636,7 @@ static void pthreadMutexEnter(sqlite3_mutex *p){
   */
   pthread_mutex_lock(&p->mutex);
 #if SQLITE_MUTEX_NREF
   */
   pthread_mutex_lock(&p->mutex);
 #if SQLITE_MUTEX_NREF

+  assert( p->nRef>0 || p->owner==0 );

   p->owner = pthread_self();
   p->nRef++;
 #endif
   p->owner = pthread_self();
   p->nRef++;
 #endif


@@ -16149,6 +16709,7 @@ static void pthreadMutexLeave(sqlite3_mutex *p){
   assert( pthreadMutexHeld(p) );
 #if SQLITE_MUTEX_NREF
   p->nRef--;
   assert( pthreadMutexHeld(p) );
 #if SQLITE_MUTEX_NREF
   p->nRef--;

+  if( p->nRef==0 ) p->owner = 0;

 #endif
   assert( p->nRef==0 || p->id==SQLITE_MUTEX_RECURSIVE );
 
 #endif
   assert( p->nRef==0 || p->id==SQLITE_MUTEX_RECURSIVE );
 


@@ -16413,7 +16974,7 @@ static sqlite3_mutex *winMutexAlloc(int iType){
 */
 static void winMutexFree(sqlite3_mutex *p){
   assert( p );
 */
 static void winMutexFree(sqlite3_mutex *p){
   assert( p );

-  assert( p->nRef==0 );
+  assert( p->nRef==0 && p->owner==0 );

   assert( p->id==SQLITE_MUTEX_FAST || p->id==SQLITE_MUTEX_RECURSIVE );
   DeleteCriticalSection(&p->mutex);
   sqlite3_free(p);
   assert( p->id==SQLITE_MUTEX_FAST || p->id==SQLITE_MUTEX_RECURSIVE );
   DeleteCriticalSection(&p->mutex);
   sqlite3_free(p);


@@ -16437,6 +16998,7 @@ static void winMutexEnter(sqlite3_mutex *p){
 #endif
   EnterCriticalSection(&p->mutex);
 #ifdef SQLITE_DEBUG
 #endif
   EnterCriticalSection(&p->mutex);
 #ifdef SQLITE_DEBUG

+  assert( p->nRef>0 || p->owner==0 );

   p->owner = tid; 
   p->nRef++;
   if( p->trace ){
   p->owner = tid; 
   p->nRef++;
   if( p->trace ){


@@ -16490,6 +17052,7 @@ static void winMutexLeave(sqlite3_mutex *p){
   assert( p->nRef>0 );
   assert( p->owner==tid );
   p->nRef--;
   assert( p->nRef>0 );
   assert( p->owner==tid );
   p->nRef--;

+  if( p->nRef==0 ) p->owner = 0;

   assert( p->nRef==0 || p->id==SQLITE_MUTEX_RECURSIVE );
 #endif
   LeaveCriticalSection(&p->mutex);
   assert( p->nRef==0 || p->id==SQLITE_MUTEX_RECURSIVE );
 #endif
   LeaveCriticalSection(&p->mutex);


@@ -16775,6 +17338,7 @@ static int mallocWithAlarm(int n, void **pp){
   if( p ){
     nFull = sqlite3MallocSize(p);
     sqlite3StatusAdd(SQLITE_STATUS_MEMORY_USED, nFull);
   if( p ){
     nFull = sqlite3MallocSize(p);
     sqlite3StatusAdd(SQLITE_STATUS_MEMORY_USED, nFull);

+    sqlite3StatusAdd(SQLITE_STATUS_MALLOC_COUNT, 1);

   }
   *pp = p;
   return nFull;
   }
   *pp = p;
   return nFull;


@@ -16892,12 +17456,14 @@ SQLITE_PRIVATE void sqlite3ScratchFree(void *p){
            || p<sqlite3GlobalConfig.pScratch
            || p>=(void*)mem0.aScratchFree ){
       assert( sqlite3MemdebugHasType(p, MEMTYPE_SCRATCH) );
            || p<sqlite3GlobalConfig.pScratch
            || p>=(void*)mem0.aScratchFree ){
       assert( sqlite3MemdebugHasType(p, MEMTYPE_SCRATCH) );

+      assert( sqlite3MemdebugNoType(p, ~MEMTYPE_SCRATCH) );

       sqlite3MemdebugSetType(p, MEMTYPE_HEAP);
       if( sqlite3GlobalConfig.bMemstat ){
         int iSize = sqlite3MallocSize(p);
         sqlite3_mutex_enter(mem0.mutex);
         sqlite3StatusAdd(SQLITE_STATUS_SCRATCH_OVERFLOW, -iSize);
         sqlite3StatusAdd(SQLITE_STATUS_MEMORY_USED, -iSize);
       sqlite3MemdebugSetType(p, MEMTYPE_HEAP);
       if( sqlite3GlobalConfig.bMemstat ){
         int iSize = sqlite3MallocSize(p);
         sqlite3_mutex_enter(mem0.mutex);
         sqlite3StatusAdd(SQLITE_STATUS_SCRATCH_OVERFLOW, -iSize);
         sqlite3StatusAdd(SQLITE_STATUS_MEMORY_USED, -iSize);

+        sqlite3StatusAdd(SQLITE_STATUS_MALLOC_COUNT, -1);

         sqlite3GlobalConfig.m.xFree(p);
         sqlite3_mutex_leave(mem0.mutex);
       }else{
         sqlite3GlobalConfig.m.xFree(p);
         sqlite3_mutex_leave(mem0.mutex);
       }else{


@@ -16932,7 +17498,7 @@ SQLITE_PRIVATE void sqlite3ScratchFree(void *p){
 */
 #ifndef SQLITE_OMIT_LOOKASIDE
 static int isLookaside(sqlite3 *db, void *p){
 */
 #ifndef SQLITE_OMIT_LOOKASIDE
 static int isLookaside(sqlite3 *db, void *p){

-  return db && p && p>=db->lookaside.pStart && p<db->lookaside.pEnd;
+  return p && p>=db->lookaside.pStart && p<db->lookaside.pEnd;

 }
 #else
 #define isLookaside(A,B) 0
 }
 #else
 #define isLookaside(A,B) 0


@@ -16944,15 +17510,17 @@ static int isLookaside(sqlite3 *db, void *p){
 */
 SQLITE_PRIVATE int sqlite3MallocSize(void *p){
   assert( sqlite3MemdebugHasType(p, MEMTYPE_HEAP) );
 */
 SQLITE_PRIVATE int sqlite3MallocSize(void *p){
   assert( sqlite3MemdebugHasType(p, MEMTYPE_HEAP) );

+  assert( sqlite3MemdebugNoType(p, MEMTYPE_DB) );

   return sqlite3GlobalConfig.m.xSize(p);
 }
 SQLITE_PRIVATE int sqlite3DbMallocSize(sqlite3 *db, void *p){
   assert( db==0 || sqlite3_mutex_held(db->mutex) );
   return sqlite3GlobalConfig.m.xSize(p);
 }
 SQLITE_PRIVATE int sqlite3DbMallocSize(sqlite3 *db, void *p){
   assert( db==0 || sqlite3_mutex_held(db->mutex) );

-  if( isLookaside(db, p) ){
+  if( db && isLookaside(db, p) ){

     return db->lookaside.sz;
   }else{
     return db->lookaside.sz;
   }else{

-    assert( sqlite3MemdebugHasType(p,
-             db ? (MEMTYPE_DB|MEMTYPE_HEAP) : MEMTYPE_HEAP) );
+    assert( sqlite3MemdebugHasType(p, MEMTYPE_DB) );
+    assert( sqlite3MemdebugHasType(p, MEMTYPE_LOOKASIDE|MEMTYPE_HEAP) );
+    assert( db!=0 || sqlite3MemdebugNoType(p, MEMTYPE_LOOKASIDE) );

     return sqlite3GlobalConfig.m.xSize(p);
   }
 }
     return sqlite3GlobalConfig.m.xSize(p);
   }
 }


@@ -16962,10 +17530,12 @@ SQLITE_PRIVATE int sqlite3DbMallocSize(sqlite3 *db, void *p){
 */
 SQLITE_API void sqlite3_free(void *p){
   if( p==0 ) return;
 */
 SQLITE_API void sqlite3_free(void *p){
   if( p==0 ) return;

+  assert( sqlite3MemdebugNoType(p, MEMTYPE_DB) );

   assert( sqlite3MemdebugHasType(p, MEMTYPE_HEAP) );
   if( sqlite3GlobalConfig.bMemstat ){
     sqlite3_mutex_enter(mem0.mutex);
     sqlite3StatusAdd(SQLITE_STATUS_MEMORY_USED, -sqlite3MallocSize(p));
   assert( sqlite3MemdebugHasType(p, MEMTYPE_HEAP) );
   if( sqlite3GlobalConfig.bMemstat ){
     sqlite3_mutex_enter(mem0.mutex);
     sqlite3StatusAdd(SQLITE_STATUS_MEMORY_USED, -sqlite3MallocSize(p));

+    sqlite3StatusAdd(SQLITE_STATUS_MALLOC_COUNT, -1);

     sqlite3GlobalConfig.m.xFree(p);
     sqlite3_mutex_leave(mem0.mutex);
   }else{
     sqlite3GlobalConfig.m.xFree(p);
     sqlite3_mutex_leave(mem0.mutex);
   }else{


@@ -16979,16 +17549,24 @@ SQLITE_API void sqlite3_free(void *p){
 */
 SQLITE_PRIVATE void sqlite3DbFree(sqlite3 *db, void *p){
   assert( db==0 || sqlite3_mutex_held(db->mutex) );
 */
 SQLITE_PRIVATE void sqlite3DbFree(sqlite3 *db, void *p){
   assert( db==0 || sqlite3_mutex_held(db->mutex) );

-  if( isLookaside(db, p) ){
-    LookasideSlot *pBuf = (LookasideSlot*)p;
-    pBuf->pNext = db->lookaside.pFree;
-    db->lookaside.pFree = pBuf;
-    db->lookaside.nOut--;
-  }else{
-    assert( sqlite3MemdebugHasType(p, MEMTYPE_DB|MEMTYPE_HEAP) );
-    sqlite3MemdebugSetType(p, MEMTYPE_HEAP);
-    sqlite3_free(p);
+  if( db ){
+    if( db->pnBytesFreed ){
+      *db->pnBytesFreed += sqlite3DbMallocSize(db, p);
+      return;
+    }
+    if( isLookaside(db, p) ){
+      LookasideSlot *pBuf = (LookasideSlot*)p;
+      pBuf->pNext = db->lookaside.pFree;
+      db->lookaside.pFree = pBuf;
+      db->lookaside.nOut--;
+      return;
+    }

   }
   }

+  assert( sqlite3MemdebugHasType(p, MEMTYPE_DB) );
+  assert( sqlite3MemdebugHasType(p, MEMTYPE_LOOKASIDE|MEMTYPE_HEAP) );
+  assert( db!=0 || sqlite3MemdebugNoType(p, MEMTYPE_LOOKASIDE) );
+  sqlite3MemdebugSetType(p, MEMTYPE_HEAP);
+  sqlite3_free(p);

 }
 
 /*
 }
 
 /*


@@ -17020,6 +17598,7 @@ SQLITE_PRIVATE void *sqlite3Realloc(void *pOld, int nBytes){
       sqlite3MallocAlarm(nNew-nOld);
     }
     assert( sqlite3MemdebugHasType(pOld, MEMTYPE_HEAP) );
       sqlite3MallocAlarm(nNew-nOld);
     }
     assert( sqlite3MemdebugHasType(pOld, MEMTYPE_HEAP) );

+    assert( sqlite3MemdebugNoType(pOld, ~MEMTYPE_HEAP) );

     pNew = sqlite3GlobalConfig.m.xRealloc(pOld, nNew);
     if( pNew==0 && mem0.alarmCallback ){
       sqlite3MallocAlarm(nBytes);
     pNew = sqlite3GlobalConfig.m.xRealloc(pOld, nNew);
     if( pNew==0 && mem0.alarmCallback ){
       sqlite3MallocAlarm(nBytes);


@@ -17092,6 +17671,7 @@ SQLITE_PRIVATE void *sqlite3DbMallocZero(sqlite3 *db, int n){
 SQLITE_PRIVATE void *sqlite3DbMallocRaw(sqlite3 *db, int n){
   void *p;
   assert( db==0 || sqlite3_mutex_held(db->mutex) );
 SQLITE_PRIVATE void *sqlite3DbMallocRaw(sqlite3 *db, int n){
   void *p;
   assert( db==0 || sqlite3_mutex_held(db->mutex) );

+  assert( db==0 || db->pnBytesFreed==0 );

 #ifndef SQLITE_OMIT_LOOKASIDE
   if( db ){
     LookasideSlot *pBuf;
 #ifndef SQLITE_OMIT_LOOKASIDE
   if( db ){
     LookasideSlot *pBuf;


@@ -17117,8 +17697,8 @@ SQLITE_PRIVATE void *sqlite3DbMallocRaw(sqlite3 *db, int n){
   if( !p && db ){
     db->mallocFailed = 1;
   }
   if( !p && db ){
     db->mallocFailed = 1;
   }

-  sqlite3MemdebugSetType(p,
-            (db && db->lookaside.bEnabled) ? MEMTYPE_DB : MEMTYPE_HEAP);
+  sqlite3MemdebugSetType(p, MEMTYPE_DB |
+         ((db && db->lookaside.bEnabled) ? MEMTYPE_LOOKASIDE : MEMTYPE_HEAP));

   return p;
 }
 
   return p;
 }
 


@@ -17144,14 +17724,16 @@ SQLITE_PRIVATE void *sqlite3DbRealloc(sqlite3 *db, void *p, int n){
         sqlite3DbFree(db, p);
       }
     }else{
         sqlite3DbFree(db, p);
       }
     }else{

-      assert( sqlite3MemdebugHasType(p, MEMTYPE_DB|MEMTYPE_HEAP) );
+      assert( sqlite3MemdebugHasType(p, MEMTYPE_DB) );
+      assert( sqlite3MemdebugHasType(p, MEMTYPE_LOOKASIDE|MEMTYPE_HEAP) );

       sqlite3MemdebugSetType(p, MEMTYPE_HEAP);
       pNew = sqlite3_realloc(p, n);
       if( !pNew ){
       sqlite3MemdebugSetType(p, MEMTYPE_HEAP);
       pNew = sqlite3_realloc(p, n);
       if( !pNew ){

+        sqlite3MemdebugSetType(p, MEMTYPE_DB|MEMTYPE_HEAP);

         db->mallocFailed = 1;
       }
         db->mallocFailed = 1;
       }

-      sqlite3MemdebugSetType(pNew,
-            db->lookaside.bEnabled ? MEMTYPE_DB : MEMTYPE_HEAP);
+      sqlite3MemdebugSetType(pNew, MEMTYPE_DB | 
+            (db->lookaside.bEnabled ? MEMTYPE_LOOKASIDE : MEMTYPE_HEAP));

     }
   }
   return pNew;
     }
   }
   return pNew;


@@ -18024,7 +18606,11 @@ SQLITE_PRIVATE void sqlite3StrAccumAppend(StrAccum *p, const char *z, int N){
       }else{
         p->nAlloc = (int)szNew;
       }
       }else{
         p->nAlloc = (int)szNew;
       }

-      zNew = sqlite3DbMallocRaw(p->db, p->nAlloc );
+      if( p->useMalloc==1 ){
+        zNew = sqlite3DbMallocRaw(p->db, p->nAlloc );
+      }else{
+        zNew = sqlite3_malloc(p->nAlloc);
+      }

       if( zNew ){
         memcpy(zNew, p->zText, p->nChar);
         sqlite3StrAccumReset(p);
       if( zNew ){
         memcpy(zNew, p->zText, p->nChar);
         sqlite3StrAccumReset(p);


@@ -18049,7 +18635,11 @@ SQLITE_PRIVATE char *sqlite3StrAccumFinish(StrAccum *p){
   if( p->zText ){
     p->zText[p->nChar] = 0;
     if( p->useMalloc && p->zText==p->zBase ){
   if( p->zText ){
     p->zText[p->nChar] = 0;
     if( p->useMalloc && p->zText==p->zBase ){

-      p->zText = sqlite3DbMallocRaw(p->db, p->nChar+1 );
+      if( p->useMalloc==1 ){
+        p->zText = sqlite3DbMallocRaw(p->db, p->nChar+1 );
+      }else{
+        p->zText = sqlite3_malloc(p->nChar+1);
+      }

       if( p->zText ){
         memcpy(p->zText, p->zBase, p->nChar+1);
       }else{
       if( p->zText ){
         memcpy(p->zText, p->zBase, p->nChar+1);
       }else{


@@ -18065,7 +18655,11 @@ SQLITE_PRIVATE char *sqlite3StrAccumFinish(StrAccum *p){
 */
 SQLITE_PRIVATE void sqlite3StrAccumReset(StrAccum *p){
   if( p->zText!=p->zBase ){
 */
 SQLITE_PRIVATE void sqlite3StrAccumReset(StrAccum *p){
   if( p->zText!=p->zBase ){

-    sqlite3DbFree(p->db, p->zText);
+    if( p->useMalloc==1 ){
+      sqlite3DbFree(p->db, p->zText);
+    }else{
+      sqlite3_free(p->zText);
+    }

   }
   p->zText = 0;
 }
   }
   p->zText = 0;
 }


@@ -18147,6 +18741,7 @@ SQLITE_API char *sqlite3_vmprintf(const char *zFormat, va_list ap){
   if( sqlite3_initialize() ) return 0;
 #endif
   sqlite3StrAccumInit(&acc, zBase, sizeof(zBase), SQLITE_MAX_LENGTH);
   if( sqlite3_initialize() ) return 0;
 #endif
   sqlite3StrAccumInit(&acc, zBase, sizeof(zBase), SQLITE_MAX_LENGTH);

+  acc.useMalloc = 2;

   sqlite3VXPrintf(&acc, 0, zFormat, ap);
   z = sqlite3StrAccumFinish(&acc);
   return z;
   sqlite3VXPrintf(&acc, 0, zFormat, ap);
   z = sqlite3StrAccumFinish(&acc);
   return z;


@@ -18440,429 +19035,6 @@ SQLITE_PRIVATE void sqlite3PrngResetState(void){
 **     0xfe 0xff   big-endian utf-16 follows
 **
 */
 **     0xfe 0xff   big-endian utf-16 follows
 **
 */

-/************** Include vdbeInt.h in the middle of utf.c *********************/
-/************** Begin file vdbeInt.h *****************************************/
-/*
-** 2003 September 6
-**
-** The author disclaims copyright to this source code.  In place of
-** a legal notice, here is a blessing:
-**
-**    May you do good and not evil.
-**    May you find forgiveness for yourself and forgive others.
-**    May you share freely, never taking more than you give.
-**
-*************************************************************************
-** This is the header file for information that is private to the
-** VDBE.  This information used to all be at the top of the single
-** source code file "vdbe.c".  When that file became too big (over
-** 6000 lines long) it was split up into several smaller files and
-** this header information was factored out.
-*/
-#ifndef _VDBEINT_H_
-#define _VDBEINT_H_
-
-/*
-** SQL is translated into a sequence of instructions to be
-** executed by a virtual machine.  Each instruction is an instance
-** of the following structure.
-*/
-typedef struct VdbeOp Op;
-
-/*
-** Boolean values
-*/
-typedef unsigned char Bool;
-
-/*
-** A cursor is a pointer into a single BTree within a database file.
-** The cursor can seek to a BTree entry with a particular key, or
-** loop over all entries of the Btree.  You can also insert new BTree
-** entries or retrieve the key or data from the entry that the cursor
-** is currently pointing to.
-** 
-** Every cursor that the virtual machine has open is represented by an
-** instance of the following structure.
-**
-** If the VdbeCursor.isTriggerRow flag is set it means that this cursor is
-** really a single row that represents the NEW or OLD pseudo-table of
-** a row trigger.  The data for the row is stored in VdbeCursor.pData and
-** the rowid is in VdbeCursor.iKey.
-*/
-struct VdbeCursor {
-  BtCursor *pCursor;    /* The cursor structure of the backend */
-  int iDb;              /* Index of cursor database in db->aDb[] (or -1) */
-  i64 lastRowid;        /* Last rowid from a Next or NextIdx operation */
-  Bool zeroed;          /* True if zeroed out and ready for reuse */
-  Bool rowidIsValid;    /* True if lastRowid is valid */
-  Bool atFirst;         /* True if pointing to first entry */
-  Bool useRandomRowid;  /* Generate new record numbers semi-randomly */
-  Bool nullRow;         /* True if pointing to a row with no data */
-  Bool deferredMoveto;  /* A call to sqlite3BtreeMoveto() is needed */
-  Bool isTable;         /* True if a table requiring integer keys */
-  Bool isIndex;         /* True if an index containing keys only - no data */
-  i64 movetoTarget;     /* Argument to the deferred sqlite3BtreeMoveto() */
-  Btree *pBt;           /* Separate file holding temporary table */
-  int pseudoTableReg;   /* Register holding pseudotable content. */
-  KeyInfo *pKeyInfo;    /* Info about index keys needed by index cursors */
-  int nField;           /* Number of fields in the header */
-  i64 seqCount;         /* Sequence counter */
-  sqlite3_vtab_cursor *pVtabCursor;  /* The cursor for a virtual table */
-  const sqlite3_module *pModule;     /* Module for cursor pVtabCursor */
-
-  /* Result of last sqlite3BtreeMoveto() done by an OP_NotExists or 
-  ** OP_IsUnique opcode on this cursor. */
-  int seekResult;
-
-  /* Cached information about the header for the data record that the
-  ** cursor is currently pointing to.  Only valid if cacheStatus matches
-  ** Vdbe.cacheCtr.  Vdbe.cacheCtr will never take on the value of
-  ** CACHE_STALE and so setting cacheStatus=CACHE_STALE guarantees that
-  ** the cache is out of date.
-  **
-  ** aRow might point to (ephemeral) data for the current row, or it might
-  ** be NULL.
-  */
-  u32 cacheStatus;      /* Cache is valid if this matches Vdbe.cacheCtr */
-  int payloadSize;      /* Total number of bytes in the record */
-  u32 *aType;           /* Type values for all entries in the record */
-  u32 *aOffset;         /* Cached offsets to the start of each columns data */
-  u8 *aRow;             /* Data for the current row, if all on one page */
-};
-typedef struct VdbeCursor VdbeCursor;
-
-/*
-** When a sub-program is executed (OP_Program), a structure of this type
-** is allocated to store the current value of the program counter, as
-** well as the current memory cell array and various other frame specific
-** values stored in the Vdbe struct. When the sub-program is finished, 
-** these values are copied back to the Vdbe from the VdbeFrame structure,
-** restoring the state of the VM to as it was before the sub-program
-** began executing.
-**
-** Frames are stored in a linked list headed at Vdbe.pParent. Vdbe.pParent
-** is the parent of the current frame, or zero if the current frame
-** is the main Vdbe program.
-*/
-typedef struct VdbeFrame VdbeFrame;
-struct VdbeFrame {
-  Vdbe *v;                /* VM this frame belongs to */
-  int pc;                 /* Program Counter */
-  Op *aOp;                /* Program instructions */
-  int nOp;                /* Size of aOp array */
-  Mem *aMem;              /* Array of memory cells */
-  int nMem;               /* Number of entries in aMem */
-  VdbeCursor **apCsr;     /* Element of Vdbe cursors */
-  u16 nCursor;            /* Number of entries in apCsr */
-  void *token;            /* Copy of SubProgram.token */
-  int nChildMem;          /* Number of memory cells for child frame */
-  int nChildCsr;          /* Number of cursors for child frame */
-  i64 lastRowid;          /* Last insert rowid (sqlite3.lastRowid) */
-  int nChange;            /* Statement changes (Vdbe.nChanges)     */
-  VdbeFrame *pParent;     /* Parent of this frame */
-};
-
-#define VdbeFrameMem(p) ((Mem *)&((u8 *)p)[ROUND8(sizeof(VdbeFrame))])
-
-/*
-** A value for VdbeCursor.cacheValid that means the cache is always invalid.
-*/
-#define CACHE_STALE 0
-
-/*
-** Internally, the vdbe manipulates nearly all SQL values as Mem
-** structures. Each Mem struct may cache multiple representations (string,
-** integer etc.) of the same value.  A value (and therefore Mem structure)
-** has the following properties:
-**
-** Each value has a manifest type. The manifest type of the value stored
-** in a Mem struct is returned by the MemType(Mem*) macro. The type is
-** one of SQLITE_NULL, SQLITE_INTEGER, SQLITE_REAL, SQLITE_TEXT or
-** SQLITE_BLOB.
-*/
-struct Mem {
-  union {
-    i64 i;              /* Integer value. */
-    int nZero;          /* Used when bit MEM_Zero is set in flags */
-    FuncDef *pDef;      /* Used only when flags==MEM_Agg */
-    RowSet *pRowSet;    /* Used only when flags==MEM_RowSet */
-    VdbeFrame *pFrame;  /* Used when flags==MEM_Frame */
-  } u;
-  double r;           /* Real value */
-  sqlite3 *db;        /* The associated database connection */
-  char *z;            /* String or BLOB value */
-  int n;              /* Number of characters in string value, excluding '\0' */
-  u16 flags;          /* Some combination of MEM_Null, MEM_Str, MEM_Dyn, etc. */
-  u8  type;           /* One of SQLITE_NULL, SQLITE_TEXT, SQLITE_INTEGER, etc */
-  u8  enc;            /* SQLITE_UTF8, SQLITE_UTF16BE, SQLITE_UTF16LE */
-  void (*xDel)(void *);  /* If not null, call this function to delete Mem.z */
-  char *zMalloc;      /* Dynamic buffer allocated by sqlite3_malloc() */
-};
-
-/* One or more of the following flags are set to indicate the validOK
-** representations of the value stored in the Mem struct.
-**
-** If the MEM_Null flag is set, then the value is an SQL NULL value.
-** No other flags may be set in this case.
-**
-** If the MEM_Str flag is set then Mem.z points at a string representation.
-** Usually this is encoded in the same unicode encoding as the main
-** database (see below for exceptions). If the MEM_Term flag is also
-** set, then the string is nul terminated. The MEM_Int and MEM_Real 
-** flags may coexist with the MEM_Str flag.
-**
-** Multiple of these values can appear in Mem.flags.  But only one
-** at a time can appear in Mem.type.
-*/
-#define MEM_Null      0x0001   /* Value is NULL */
-#define MEM_Str       0x0002   /* Value is a string */
-#define MEM_Int       0x0004   /* Value is an integer */
-#define MEM_Real      0x0008   /* Value is a real number */
-#define MEM_Blob      0x0010   /* Value is a BLOB */
-#define MEM_RowSet    0x0020   /* Value is a RowSet object */
-#define MEM_Frame     0x0040   /* Value is a VdbeFrame object */
-#define MEM_TypeMask  0x00ff   /* Mask of type bits */
-
-/* Whenever Mem contains a valid string or blob representation, one of
-** the following flags must be set to determine the memory management
-** policy for Mem.z.  The MEM_Term flag tells us whether or not the
-** string is \000 or \u0000 terminated
-*/
-#define MEM_Term      0x0200   /* String rep is nul terminated */
-#define MEM_Dyn       0x0400   /* Need to call sqliteFree() on Mem.z */
-#define MEM_Static    0x0800   /* Mem.z points to a static string */
-#define MEM_Ephem     0x1000   /* Mem.z points to an ephemeral string */
-#define MEM_Agg       0x2000   /* Mem.z points to an agg function context */
-#define MEM_Zero      0x4000   /* Mem.i contains count of 0s appended to blob */
-
-#ifdef SQLITE_OMIT_INCRBLOB
-  #undef MEM_Zero
-  #define MEM_Zero 0x0000
-#endif
-
-
-/*
-** Clear any existing type flags from a Mem and replace them with f
-*/
-#define MemSetTypeFlag(p, f) \
-   ((p)->flags = ((p)->flags&~(MEM_TypeMask|MEM_Zero))|f)
-
-
-/* A VdbeFunc is just a FuncDef (defined in sqliteInt.h) that contains
-** additional information about auxiliary information bound to arguments
-** of the function.  This is used to implement the sqlite3_get_auxdata()
-** and sqlite3_set_auxdata() APIs.  The "auxdata" is some auxiliary data
-** that can be associated with a constant argument to a function.  This
-** allows functions such as "regexp" to compile their constant regular
-** expression argument once and reused the compiled code for multiple
-** invocations.
-*/
-struct VdbeFunc {
-  FuncDef *pFunc;               /* The definition of the function */
-  int nAux;                     /* Number of entries allocated for apAux[] */
-  struct AuxData {
-    void *pAux;                   /* Aux data for the i-th argument */
-    void (*xDelete)(void *);      /* Destructor for the aux data */
-  } apAux[1];                   /* One slot for each function argument */
-};
-
-/*
-** The "context" argument for a installable function.  A pointer to an
-** instance of this structure is the first argument to the routines used
-** implement the SQL functions.
-**
-** There is a typedef for this structure in sqlite.h.  So all routines,
-** even the public interface to SQLite, can use a pointer to this structure.
-** But this file is the only place where the internal details of this
-** structure are known.
-**
-** This structure is defined inside of vdbeInt.h because it uses substructures
-** (Mem) which are only defined there.
-*/
-struct sqlite3_context {
-  FuncDef *pFunc;       /* Pointer to function information.  MUST BE FIRST */
-  VdbeFunc *pVdbeFunc;  /* Auxilary data, if created. */
-  Mem s;                /* The return value is stored here */
-  Mem *pMem;            /* Memory cell used to store aggregate context */
-  int isError;          /* Error code returned by the function. */
-  CollSeq *pColl;       /* Collating sequence */
-};
-
-/*
-** A Set structure is used for quick testing to see if a value
-** is part of a small set.  Sets are used to implement code like
-** this:
-**            x.y IN ('hi','hoo','hum')
-*/
-typedef struct Set Set;
-struct Set {
-  Hash hash;             /* A set is just a hash table */
-  HashElem *prev;        /* Previously accessed hash elemen */
-};
-
-/*
-** An instance of the virtual machine.  This structure contains the complete
-** state of the virtual machine.
-**
-** The "sqlite3_stmt" structure pointer that is returned by sqlite3_compile()
-** is really a pointer to an instance of this structure.
-**
-** The Vdbe.inVtabMethod variable is set to non-zero for the duration of
-** any virtual table method invocations made by the vdbe program. It is
-** set to 2 for xDestroy method calls and 1 for all other methods. This
-** variable is used for two purposes: to allow xDestroy methods to execute
-** "DROP TABLE" statements and to prevent some nasty side effects of
-** malloc failure when SQLite is invoked recursively by a virtual table 
-** method function.
-*/
-struct Vdbe {
-  sqlite3 *db;            /* The database connection that owns this statement */
-  Vdbe *pPrev,*pNext;     /* Linked list of VDBEs with the same Vdbe.db */
-  int nOp;                /* Number of instructions in the program */
-  int nOpAlloc;           /* Number of slots allocated for aOp[] */
-  Op *aOp;                /* Space to hold the virtual machine's program */
-  int nLabel;             /* Number of labels used */
-  int nLabelAlloc;        /* Number of slots allocated in aLabel[] */
-  int *aLabel;            /* Space to hold the labels */
-  Mem **apArg;            /* Arguments to currently executing user function */
-  Mem *aColName;          /* Column names to return */
-  Mem *pResultSet;        /* Pointer to an array of results */
-  u16 nResColumn;         /* Number of columns in one row of the result set */
-  u16 nCursor;            /* Number of slots in apCsr[] */
-  VdbeCursor **apCsr;     /* One element of this array for each open cursor */
-  u8 errorAction;         /* Recovery action to do in case of an error */
-  u8 okVar;               /* True if azVar[] has been initialized */
-  ynVar nVar;             /* Number of entries in aVar[] */
-  Mem *aVar;              /* Values for the OP_Variable opcode. */
-  char **azVar;           /* Name of variables */
-  u32 magic;              /* Magic number for sanity checking */
-  int nMem;               /* Number of memory locations currently allocated */
-  Mem *aMem;              /* The memory locations */
-  u32 cacheCtr;           /* VdbeCursor row cache generation counter */
-  int pc;                 /* The program counter */
-  int rc;                 /* Value to return */
-  char *zErrMsg;          /* Error message written here */
-  u8 explain;             /* True if EXPLAIN present on SQL command */
-  u8 changeCntOn;         /* True to update the change-counter */
-  u8 expired;             /* True if the VM needs to be recompiled */
-  u8 runOnlyOnce;         /* Automatically expire on reset */
-  u8 minWriteFileFormat;  /* Minimum file format for writable database files */
-  u8 inVtabMethod;        /* See comments above */
-  u8 usesStmtJournal;     /* True if uses a statement journal */
-  u8 readOnly;            /* True for read-only statements */
-  u8 isPrepareV2;         /* True if prepared with prepare_v2() */
-  int nChange;            /* Number of db changes made since last reset */
-  int btreeMask;          /* Bitmask of db->aDb[] entries referenced */
-  i64 startTime;          /* Time when query started - used for profiling */
-  BtreeMutexArray aMutex; /* An array of Btree used here and needing locks */
-  int aCounter[3];        /* Counters used by sqlite3_stmt_status() */
-  char *zSql;             /* Text of the SQL statement that generated this */
-  void *pFree;            /* Free this when deleting the vdbe */
-  i64 nFkConstraint;      /* Number of imm. FK constraints this VM */
-  i64 nStmtDefCons;       /* Number of def. constraints when stmt started */
-  int iStatement;         /* Statement number (or 0 if has not opened stmt) */
-#ifdef SQLITE_DEBUG
-  FILE *trace;            /* Write an execution trace here, if not NULL */
-#endif
-  VdbeFrame *pFrame;      /* Parent frame */
-  int nFrame;             /* Number of frames in pFrame list */
-  u32 expmask;            /* Binding to these vars invalidates VM */
-};
-
-/*
-** The following are allowed values for Vdbe.magic
-*/
-#define VDBE_MAGIC_INIT     0x26bceaa5    /* Building a VDBE program */
-#define VDBE_MAGIC_RUN      0xbdf20da3    /* VDBE is ready to execute */
-#define VDBE_MAGIC_HALT     0x519c2973    /* VDBE has completed execution */
-#define VDBE_MAGIC_DEAD     0xb606c3c8    /* The VDBE has been deallocated */
-
-/*
-** Function prototypes
-*/
-SQLITE_PRIVATE void sqlite3VdbeFreeCursor(Vdbe *, VdbeCursor*);
-void sqliteVdbePopStack(Vdbe*,int);
-SQLITE_PRIVATE int sqlite3VdbeCursorMoveto(VdbeCursor*);
-#if defined(SQLITE_DEBUG) || defined(VDBE_PROFILE)
-SQLITE_PRIVATE void sqlite3VdbePrintOp(FILE*, int, Op*);
-#endif
-SQLITE_PRIVATE u32 sqlite3VdbeSerialTypeLen(u32);
-SQLITE_PRIVATE u32 sqlite3VdbeSerialType(Mem*, int);
-SQLITE_PRIVATE u32 sqlite3VdbeSerialPut(unsigned char*, int, Mem*, int);
-SQLITE_PRIVATE u32 sqlite3VdbeSerialGet(const unsigned char*, u32, Mem*);
-SQLITE_PRIVATE void sqlite3VdbeDeleteAuxData(VdbeFunc*, int);
-
-int sqlite2BtreeKeyCompare(BtCursor *, const void *, int, int, int *);
-SQLITE_PRIVATE int sqlite3VdbeIdxKeyCompare(VdbeCursor*,UnpackedRecord*,int*);
-SQLITE_PRIVATE int sqlite3VdbeIdxRowid(sqlite3*, BtCursor *, i64 *);
-SQLITE_PRIVATE int sqlite3MemCompare(const Mem*, const Mem*, const CollSeq*);
-SQLITE_PRIVATE int sqlite3VdbeExec(Vdbe*);
-SQLITE_PRIVATE int sqlite3VdbeList(Vdbe*);
-SQLITE_PRIVATE int sqlite3VdbeHalt(Vdbe*);
-SQLITE_PRIVATE int sqlite3VdbeChangeEncoding(Mem *, int);
-SQLITE_PRIVATE int sqlite3VdbeMemTooBig(Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemCopy(Mem*, const Mem*);
-SQLITE_PRIVATE void sqlite3VdbeMemShallowCopy(Mem*, const Mem*, int);
-SQLITE_PRIVATE void sqlite3VdbeMemMove(Mem*, Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemNulTerminate(Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemSetStr(Mem*, const char*, int, u8, void(*)(void*));
-SQLITE_PRIVATE void sqlite3VdbeMemSetInt64(Mem*, i64);
-#ifdef SQLITE_OMIT_FLOATING_POINT
-# define sqlite3VdbeMemSetDouble sqlite3VdbeMemSetInt64
-#else
-SQLITE_PRIVATE   void sqlite3VdbeMemSetDouble(Mem*, double);
-#endif
-SQLITE_PRIVATE void sqlite3VdbeMemSetNull(Mem*);
-SQLITE_PRIVATE void sqlite3VdbeMemSetZeroBlob(Mem*,int);
-SQLITE_PRIVATE void sqlite3VdbeMemSetRowSet(Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemMakeWriteable(Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemStringify(Mem*, int);
-SQLITE_PRIVATE i64 sqlite3VdbeIntValue(Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemIntegerify(Mem*);
-SQLITE_PRIVATE double sqlite3VdbeRealValue(Mem*);
-SQLITE_PRIVATE void sqlite3VdbeIntegerAffinity(Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemRealify(Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemNumerify(Mem*);
-SQLITE_PRIVATE int sqlite3VdbeMemFromBtree(BtCursor*,int,int,int,Mem*);
-SQLITE_PRIVATE void sqlite3VdbeMemRelease(Mem *p);
-SQLITE_PRIVATE void sqlite3VdbeMemReleaseExternal(Mem *p);
-SQLITE_PRIVATE int sqlite3VdbeMemFinalize(Mem*, FuncDef*);
-SQLITE_PRIVATE const char *sqlite3OpcodeName(int);
-SQLITE_PRIVATE int sqlite3VdbeMemGrow(Mem *pMem, int n, int preserve);
-SQLITE_PRIVATE int sqlite3VdbeCloseStatement(Vdbe *, int);
-SQLITE_PRIVATE void sqlite3VdbeFrameDelete(VdbeFrame*);
-SQLITE_PRIVATE int sqlite3VdbeFrameRestore(VdbeFrame *);
-SQLITE_PRIVATE void sqlite3VdbeMemStoreType(Mem *pMem);
-
-#ifndef SQLITE_OMIT_FOREIGN_KEY
-SQLITE_PRIVATE int sqlite3VdbeCheckFk(Vdbe *, int);
-#else
-# define sqlite3VdbeCheckFk(p,i) 0
-#endif
-
-#ifndef SQLITE_OMIT_SHARED_CACHE
-SQLITE_PRIVATE void sqlite3VdbeMutexArrayEnter(Vdbe *p);
-#else
-# define sqlite3VdbeMutexArrayEnter(p)
-#endif
-
-SQLITE_PRIVATE int sqlite3VdbeMemTranslate(Mem*, u8);
-#ifdef SQLITE_DEBUG
-SQLITE_PRIVATE   void sqlite3VdbePrintSql(Vdbe*);
-SQLITE_PRIVATE   void sqlite3VdbeMemPrettyPrint(Mem *pMem, char *zBuf);
-#endif
-SQLITE_PRIVATE int sqlite3VdbeMemHandleBom(Mem *pMem);
-
-#ifndef SQLITE_OMIT_INCRBLOB
-SQLITE_PRIVATE   int sqlite3VdbeMemExpandBlob(Mem *);
-#else
-  #define sqlite3VdbeMemExpandBlob(x) SQLITE_OK
-#endif
-
-#endif /* !defined(_VDBEINT_H_) */
-
-/************** End of vdbeInt.h *********************************************/
-/************** Continuing where we left off in utf.c ************************/

 
 #ifndef SQLITE_AMALGAMATION
 /*
 
 #ifndef SQLITE_AMALGAMATION
 /*


@@ -22453,6 +22625,7 @@ struct unixFile {
   int fileFlags;                      /* Miscellanous flags */
   const char *zPath;                  /* Name of the file */
   unixShm *pShm;                      /* Shared memory segment information */
   int fileFlags;                      /* Miscellanous flags */
   const char *zPath;                  /* Name of the file */
   unixShm *pShm;                      /* Shared memory segment information */

+  int szChunk;                        /* Configured by FCNTL_CHUNK_SIZE */

 #if SQLITE_ENABLE_LOCKING_STYLE
   int openFlags;                      /* The flags specified at open() */
 #endif
 #if SQLITE_ENABLE_LOCKING_STYLE
   int openFlags;                      /* The flags specified at open() */
 #endif


@@ -25211,6 +25384,7 @@ static int unixWrite(
   }
   SimulateIOError(( wrote=(-1), amt=1 ));
   SimulateDiskfullError(( wrote=0, amt=1 ));
   }
   SimulateIOError(( wrote=(-1), amt=1 ));
   SimulateDiskfullError(( wrote=0, amt=1 ));

+

   if( amt>0 ){
     if( wrote<0 ){
       /* lastErrno set by seekAndWrite */
   if( amt>0 ){
     if( wrote<0 ){
       /* lastErrno set by seekAndWrite */


@@ -25220,6 +25394,7 @@ static int unixWrite(
       return SQLITE_FULL;
     }
   }
       return SQLITE_FULL;
     }
   }

+

   return SQLITE_OK;
 }
 
   return SQLITE_OK;
 }
 


@@ -25421,12 +25596,23 @@ static int unixSync(sqlite3_file *id, int flags){
 ** Truncate an open file to a specified size
 */
 static int unixTruncate(sqlite3_file *id, i64 nByte){
 ** Truncate an open file to a specified size
 */
 static int unixTruncate(sqlite3_file *id, i64 nByte){

+  unixFile *pFile = (unixFile *)id;

   int rc;
   int rc;

-  assert( id );
+  assert( pFile );

   SimulateIOError( return SQLITE_IOERR_TRUNCATE );
   SimulateIOError( return SQLITE_IOERR_TRUNCATE );

-  rc = ftruncate(((unixFile*)id)->h, (off_t)nByte);
+
+  /* If the user has configured a chunk-size for this file, truncate the
+  ** file so that it consists of an integer number of chunks (i.e. the
+  ** actual file size after the operation may be larger than the requested
+  ** size).
+  */
+  if( pFile->szChunk ){
+    nByte = ((nByte + pFile->szChunk - 1)/pFile->szChunk) * pFile->szChunk;
+  }
+
+  rc = ftruncate(pFile->h, (off_t)nByte);

   if( rc ){
   if( rc ){

-    ((unixFile*)id)->lastErrno = errno;
+    pFile->lastErrno = errno;

     return SQLITE_IOERR_TRUNCATE;
   }else{
 #ifndef NDEBUG
     return SQLITE_IOERR_TRUNCATE;
   }else{
 #ifndef NDEBUG


@@ -25437,8 +25623,8 @@ static int unixTruncate(sqlite3_file *id, i64 nByte){
     ** when restoring a database using the backup API from a zero-length
     ** source.
     */
     ** when restoring a database using the backup API from a zero-length
     ** source.
     */

-    if( ((unixFile*)id)->inNormalWrite && nByte==0 ){
-      ((unixFile*)id)->transCntrChng = 1;
+    if( pFile->inNormalWrite && nByte==0 ){
+      pFile->transCntrChng = 1;

     }
 #endif
 
     }
 #endif
 


@@ -25481,6 +25667,54 @@ static int unixFileSize(sqlite3_file *id, i64 *pSize){
 static int proxyFileControl(sqlite3_file*,int,void*);
 #endif
 
 static int proxyFileControl(sqlite3_file*,int,void*);
 #endif
 

+/* 
+** This function is called to handle the SQLITE_FCNTL_SIZE_HINT 
+** file-control operation.
+**
+** If the user has configured a chunk-size for this file, it could be
+** that the file needs to be extended at this point. Otherwise, the
+** SQLITE_FCNTL_SIZE_HINT operation is a no-op for Unix.
+*/
+static int fcntlSizeHint(unixFile *pFile, i64 nByte){
+  if( pFile->szChunk ){
+    i64 nSize;                    /* Required file size */
+    struct stat buf;              /* Used to hold return values of fstat() */
+   
+    if( fstat(pFile->h, &buf) ) return SQLITE_IOERR_FSTAT;
+
+    nSize = ((nByte+pFile->szChunk-1) / pFile->szChunk) * pFile->szChunk;
+    if( nSize>(i64)buf.st_size ){
+#if defined(HAVE_POSIX_FALLOCATE) && HAVE_POSIX_FALLOCATE
+      if( posix_fallocate(pFile->h, buf.st_size, nSize-buf.st_size) ){
+        return SQLITE_IOERR_WRITE;
+      }
+#else
+      /* If the OS does not have posix_fallocate(), fake it. First use
+      ** ftruncate() to set the file size, then write a single byte to
+      ** the last byte in each block within the extended region. This
+      ** is the same technique used by glibc to implement posix_fallocate()
+      ** on systems that do not have a real fallocate() system call.
+      */
+      int nBlk = buf.st_blksize;  /* File-system block size */
+      i64 iWrite;                 /* Next offset to write to */
+      int nWrite;                 /* Return value from seekAndWrite() */
+
+      if( ftruncate(pFile->h, nSize) ){
+        pFile->lastErrno = errno;
+        return SQLITE_IOERR_TRUNCATE;
+      }
+      iWrite = ((buf.st_size + 2*nBlk - 1)/nBlk)*nBlk-1;
+      do {
+        nWrite = seekAndWrite(pFile, iWrite, "", 1);
+        iWrite += nBlk;
+      } while( nWrite==1 && iWrite<nSize );
+      if( nWrite!=1 ) return SQLITE_IOERR_WRITE;
+#endif
+    }
+  }
+
+  return SQLITE_OK;
+}

 
 /*
 ** Information and control of an open file handle.
 
 /*
 ** Information and control of an open file handle.


@@ -25495,14 +25729,13 @@ static int unixFileControl(sqlite3_file *id, int op, void *pArg){
       *(int*)pArg = ((unixFile*)id)->lastErrno;
       return SQLITE_OK;
     }
       *(int*)pArg = ((unixFile*)id)->lastErrno;
       return SQLITE_OK;
     }

-    case SQLITE_FCNTL_SIZE_HINT: {
-#if 0 /* No performance advantage seen on Linux */
-      sqlite3_int64 szFile = *(sqlite3_int64*)pArg;
-      unixFile *pFile = (unixFile*)id;
-      ftruncate(pFile->h, szFile);
-#endif
+    case SQLITE_FCNTL_CHUNK_SIZE: {
+      ((unixFile*)id)->szChunk = *(int *)pArg;

       return SQLITE_OK;
     }
       return SQLITE_OK;
     }

+    case SQLITE_FCNTL_SIZE_HINT: {
+      return fcntlSizeHint((unixFile *)id, *(i64 *)pArg);
+    }

 #ifndef NDEBUG
     /* The pager calls this method to signal that it has done
     ** a rollback and that the database is therefore unchanged and
 #ifndef NDEBUG
     /* The pager calls this method to signal that it has done
     ** a rollback and that the database is therefore unchanged and


@@ -28366,7 +28599,7 @@ static int proxyTransformUnixFile(unixFile *pFile, const char *path) {
       pCtx->conchFile->pMethod->xClose((sqlite3_file *)pCtx->conchFile);
       sqlite3_free(pCtx->conchFile);
     }
       pCtx->conchFile->pMethod->xClose((sqlite3_file *)pCtx->conchFile);
       sqlite3_free(pCtx->conchFile);
     }

-    sqlite3_free(pCtx->lockProxyPath);
+    sqlite3DbFree(0, pCtx->lockProxyPath);

     sqlite3_free(pCtx->conchFilePath); 
     sqlite3_free(pCtx);
   }
     sqlite3_free(pCtx->conchFilePath); 
     sqlite3_free(pCtx);
   }


@@ -28557,9 +28790,9 @@ static int proxyClose(sqlite3_file *id) {
       if( rc ) return rc;
       sqlite3_free(conchFile);
     }
       if( rc ) return rc;
       sqlite3_free(conchFile);
     }

-    sqlite3_free(pCtx->lockProxyPath);
+    sqlite3DbFree(0, pCtx->lockProxyPath);

     sqlite3_free(pCtx->conchFilePath);
     sqlite3_free(pCtx->conchFilePath);

-    sqlite3_free(pCtx->dbPath);
+    sqlite3DbFree(0, pCtx->dbPath);

     /* restore the original locking context and pMethod then close it */
     pFile->lockingContext = pCtx->oldLockingContext;
     pFile->pMethod = pCtx->pOldMethod;
     /* restore the original locking context and pMethod then close it */
     pFile->lockingContext = pCtx->oldLockingContext;
     pFile->pMethod = pCtx->pOldMethod;


@@ -29005,6 +29238,7 @@ struct winFile {
   DWORD sectorSize;       /* Sector size of the device file is on */
   winShm *pShm;           /* Instance of shared memory on this file */
   const char *zPath;      /* Full pathname of this file */
   DWORD sectorSize;       /* Sector size of the device file is on */
   winShm *pShm;           /* Instance of shared memory on this file */
   const char *zPath;      /* Full pathname of this file */

+  int szChunk;            /* Chunk size configured by FCNTL_CHUNK_SIZE */

 #if SQLITE_OS_WINCE
   WCHAR *zDeleteOnClose;  /* Name of file to delete when closing */
   HANDLE hMutex;          /* Mutex used to control access to shared lock */  
 #if SQLITE_OS_WINCE
   WCHAR *zDeleteOnClose;  /* Name of file to delete when closing */
   HANDLE hMutex;          /* Mutex used to control access to shared lock */  


@@ -29516,6 +29750,42 @@ static BOOL winceLockFileEx(
 ** by the sqlite3_io_methods object.
 ******************************************************************************/
 
 ** by the sqlite3_io_methods object.
 ******************************************************************************/
 

+/*
+** Some microsoft compilers lack this definition.
+*/
+#ifndef INVALID_SET_FILE_POINTER
+# define INVALID_SET_FILE_POINTER ((DWORD)-1)
+#endif
+
+/*
+** Move the current position of the file handle passed as the first 
+** argument to offset iOffset within the file. If successful, return 0. 
+** Otherwise, set pFile->lastErrno and return non-zero.
+*/
+static int seekWinFile(winFile *pFile, sqlite3_int64 iOffset){
+  LONG upperBits;                 /* Most sig. 32 bits of new offset */
+  LONG lowerBits;                 /* Least sig. 32 bits of new offset */
+  DWORD dwRet;                    /* Value returned by SetFilePointer() */
+
+  upperBits = (LONG)((iOffset>>32) & 0x7fffffff);
+  lowerBits = (LONG)(iOffset & 0xffffffff);
+
+  /* API oddity: If successful, SetFilePointer() returns a dword 
+  ** containing the lower 32-bits of the new file-offset. Or, if it fails,
+  ** it returns INVALID_SET_FILE_POINTER. However according to MSDN, 
+  ** INVALID_SET_FILE_POINTER may also be a valid new offset. So to determine 
+  ** whether an error has actually occured, it is also necessary to call 
+  ** GetLastError().
+  */
+  dwRet = SetFilePointer(pFile->h, lowerBits, &upperBits, FILE_BEGIN);
+  if( (dwRet==INVALID_SET_FILE_POINTER && GetLastError()!=NO_ERROR) ){
+    pFile->lastErrno = GetLastError();
+    return 1;
+  }
+
+  return 0;
+}
+

 /*
 ** Close a file.
 **
 /*
 ** Close a file.
 **


@@ -29558,13 +29828,6 @@ static int winClose(sqlite3_file *id){
   return rc ? SQLITE_OK : SQLITE_IOERR;
 }
 
   return rc ? SQLITE_OK : SQLITE_IOERR;
 }
 

-/*
-** Some microsoft compilers lack this definition.
-*/
-#ifndef INVALID_SET_FILE_POINTER
-# define INVALID_SET_FILE_POINTER ((DWORD)-1)
-#endif
-

 /*
 ** Read data from a file into a buffer.  Return SQLITE_OK if all
 ** bytes were read successfully and SQLITE_IOERR if anything goes
 /*
 ** Read data from a file into a buffer.  Return SQLITE_OK if all
 ** bytes were read successfully and SQLITE_IOERR if anything goes


@@ -29576,32 +29839,27 @@ static int winRead(
   int amt,                   /* Number of bytes to read */
   sqlite3_int64 offset       /* Begin reading at this offset */
 ){
   int amt,                   /* Number of bytes to read */
   sqlite3_int64 offset       /* Begin reading at this offset */
 ){

-  LONG upperBits = (LONG)((offset>>32) & 0x7fffffff);
-  LONG lowerBits = (LONG)(offset & 0xffffffff);
-  DWORD rc;
-  winFile *pFile = (winFile*)id;
-  DWORD error;
-  DWORD got;
+  winFile *pFile = (winFile*)id;  /* file handle */
+  DWORD nRead;                    /* Number of bytes actually read from file */

 
   assert( id!=0 );
   SimulateIOError(return SQLITE_IOERR_READ);
   OSTRACE(("READ %d lock=%d\n", pFile->h, pFile->locktype));
 
   assert( id!=0 );
   SimulateIOError(return SQLITE_IOERR_READ);
   OSTRACE(("READ %d lock=%d\n", pFile->h, pFile->locktype));

-  rc = SetFilePointer(pFile->h, lowerBits, &upperBits, FILE_BEGIN);
-  if( rc==INVALID_SET_FILE_POINTER && (error=GetLastError())!=NO_ERROR ){
-    pFile->lastErrno = error;
+
+  if( seekWinFile(pFile, offset) ){

     return SQLITE_FULL;
   }
     return SQLITE_FULL;
   }

-  if( !ReadFile(pFile->h, pBuf, amt, &got, 0) ){
+  if( !ReadFile(pFile->h, pBuf, amt, &nRead, 0) ){

     pFile->lastErrno = GetLastError();
     return SQLITE_IOERR_READ;
   }
     pFile->lastErrno = GetLastError();
     return SQLITE_IOERR_READ;
   }

-  if( got==(DWORD)amt ){
-    return SQLITE_OK;
-  }else{
+  if( nRead<(DWORD)amt ){

     /* Unread parts of the buffer must be zero-filled */
     /* Unread parts of the buffer must be zero-filled */

-    memset(&((char*)pBuf)[got], 0, amt-got);
+    memset(&((char*)pBuf)[nRead], 0, amt-nRead);

     return SQLITE_IOERR_SHORT_READ;
   }
     return SQLITE_IOERR_SHORT_READ;
   }

+
+  return SQLITE_OK;

 }
 
 /*
 }
 
 /*


@@ -29609,47 +29867,42 @@ static int winRead(
 ** or some other error code on failure.
 */
 static int winWrite(
 ** or some other error code on failure.
 */
 static int winWrite(

-  sqlite3_file *id,         /* File to write into */
-  const void *pBuf,         /* The bytes to be written */
-  int amt,                  /* Number of bytes to write */
-  sqlite3_int64 offset      /* Offset into the file to begin writing at */
+  sqlite3_file *id,               /* File to write into */
+  const void *pBuf,               /* The bytes to be written */
+  int amt,                        /* Number of bytes to write */
+  sqlite3_int64 offset            /* Offset into the file to begin writing at */

 ){
 ){

-  LONG upperBits = (LONG)((offset>>32) & 0x7fffffff);
-  LONG lowerBits = (LONG)(offset & 0xffffffff);
-  DWORD rc;
-  winFile *pFile = (winFile*)id;
-  DWORD error;
-  DWORD wrote = 0;
+  int rc;                         /* True if error has occured, else false */
+  winFile *pFile = (winFile*)id;  /* File handle */

 
 

-  assert( id!=0 );
+  assert( amt>0 );
+  assert( pFile );

   SimulateIOError(return SQLITE_IOERR_WRITE);
   SimulateDiskfullError(return SQLITE_FULL);
   SimulateIOError(return SQLITE_IOERR_WRITE);
   SimulateDiskfullError(return SQLITE_FULL);

+

   OSTRACE(("WRITE %d lock=%d\n", pFile->h, pFile->locktype));
   OSTRACE(("WRITE %d lock=%d\n", pFile->h, pFile->locktype));

-  rc = SetFilePointer(pFile->h, lowerBits, &upperBits, FILE_BEGIN);
-  if( rc==INVALID_SET_FILE_POINTER && (error=GetLastError())!=NO_ERROR ){
-    pFile->lastErrno = error;
-    if( pFile->lastErrno==ERROR_HANDLE_DISK_FULL ){
-      return SQLITE_FULL;
-    }else{
-      return SQLITE_IOERR_WRITE;
+
+  rc = seekWinFile(pFile, offset);
+  if( rc==0 ){
+    u8 *aRem = (u8 *)pBuf;        /* Data yet to be written */
+    int nRem = amt;               /* Number of bytes yet to be written */
+    DWORD nWrite;                 /* Bytes written by each WriteFile() call */
+
+    while( nRem>0 && WriteFile(pFile->h, aRem, nRem, &nWrite, 0) && nWrite>0 ){
+      aRem += nWrite;
+      nRem -= nWrite;
+    }
+    if( nRem>0 ){
+      pFile->lastErrno = GetLastError();
+      rc = 1;

     }
   }
     }
   }

-  assert( amt>0 );
-  while(
-     amt>0
-     && (rc = WriteFile(pFile->h, pBuf, amt, &wrote, 0))!=0
-     && wrote>0
-  ){
-    amt -= wrote;
-    pBuf = &((char*)pBuf)[wrote];
-  }
-  if( !rc || amt>(int)wrote ){
-    pFile->lastErrno = GetLastError();
+
+  if( rc ){

     if( pFile->lastErrno==ERROR_HANDLE_DISK_FULL ){
       return SQLITE_FULL;
     if( pFile->lastErrno==ERROR_HANDLE_DISK_FULL ){
       return SQLITE_FULL;

-    }else{
-      return SQLITE_IOERR_WRITE;

     }
     }

+    return SQLITE_IOERR_WRITE;

   }
   return SQLITE_OK;
 }
   }
   return SQLITE_OK;
 }


@@ -29658,26 +29911,32 @@ static int winWrite(
 ** Truncate an open file to a specified size
 */
 static int winTruncate(sqlite3_file *id, sqlite3_int64 nByte){
 ** Truncate an open file to a specified size
 */
 static int winTruncate(sqlite3_file *id, sqlite3_int64 nByte){

-  LONG upperBits = (LONG)((nByte>>32) & 0x7fffffff);
-  LONG lowerBits = (LONG)(nByte & 0xffffffff);
-  DWORD dwRet;
-  winFile *pFile = (winFile*)id;
-  DWORD error;
-  int rc = SQLITE_OK;
+  winFile *pFile = (winFile*)id;  /* File handle object */
+  int rc = SQLITE_OK;             /* Return code for this function */
+
+  assert( pFile );

 
 

-  assert( id!=0 );

   OSTRACE(("TRUNCATE %d %lld\n", pFile->h, nByte));
   SimulateIOError(return SQLITE_IOERR_TRUNCATE);
   OSTRACE(("TRUNCATE %d %lld\n", pFile->h, nByte));
   SimulateIOError(return SQLITE_IOERR_TRUNCATE);

-  dwRet = SetFilePointer(pFile->h, lowerBits, &upperBits, FILE_BEGIN);
-  if( dwRet==INVALID_SET_FILE_POINTER && (error=GetLastError())!=NO_ERROR ){
-    pFile->lastErrno = error;
+
+  /* If the user has configured a chunk-size for this file, truncate the
+  ** file so that it consists of an integer number of chunks (i.e. the
+  ** actual file size after the operation may be larger than the requested
+  ** size).
+  */
+  if( pFile->szChunk ){
+    nByte = ((nByte + pFile->szChunk - 1)/pFile->szChunk) * pFile->szChunk;
+  }
+
+  /* SetEndOfFile() returns non-zero when successful, or zero when it fails. */
+  if( seekWinFile(pFile, nByte) ){

     rc = SQLITE_IOERR_TRUNCATE;
     rc = SQLITE_IOERR_TRUNCATE;

-  /* SetEndOfFile will fail if nByte is negative */
-  }else if( !SetEndOfFile(pFile->h) ){
+  }else if( 0==SetEndOfFile(pFile->h) ){

     pFile->lastErrno = GetLastError();
     rc = SQLITE_IOERR_TRUNCATE;
   }
     pFile->lastErrno = GetLastError();
     rc = SQLITE_IOERR_TRUNCATE;
   }

-  OSTRACE(("TRUNCATE %d %lld %s\n", pFile->h, nByte, rc==SQLITE_OK ? "ok" : "failed"));
+
+  OSTRACE(("TRUNCATE %d %lld %s\n", pFile->h, nByte, rc ? "failed" : "ok"));

   return rc;
 }
 
   return rc;
 }
 


@@ -30042,6 +30301,10 @@ static int winFileControl(sqlite3_file *id, int op, void *pArg){
       *(int*)pArg = (int)((winFile*)id)->lastErrno;
       return SQLITE_OK;
     }
       *(int*)pArg = (int)((winFile*)id)->lastErrno;
       return SQLITE_OK;
     }

+    case SQLITE_FCNTL_CHUNK_SIZE: {
+      ((winFile*)id)->szChunk = *(int *)pArg;
+      return SQLITE_OK;
+    }

     case SQLITE_FCNTL_SIZE_HINT: {
       sqlite3_int64 sz = *(sqlite3_int64*)pArg;
       SimulateIOErrorBenign(1);
     case SQLITE_FCNTL_SIZE_HINT: {
       sqlite3_int64 sz = *(sqlite3_int64*)pArg;
       SimulateIOErrorBenign(1);


@@ -31593,7 +31856,7 @@ SQLITE_API int sqlite3_os_end(void){
 */
 
 /* Size of the Bitvec structure in bytes. */
 */
 
 /* Size of the Bitvec structure in bytes. */

-#define BITVEC_SZ        (sizeof(void*)*128)  /* 512 on 32bit.  1024 on 64bit */
+#define BITVEC_SZ        512

 
 /* Round the union size down to the nearest pointer boundary, since that's how 
 ** it will be aligned within the Bitvec struct. */
 
 /* Round the union size down to the nearest pointer boundary, since that's how 
 ** it will be aligned within the Bitvec struct. */


@@ -32703,11 +32966,11 @@ SQLITE_PRIVATE void sqlite3PCacheBufferSetup(void *pBuf, int sz, int n){
 static void *pcache1Alloc(int nByte){
   void *p;
   assert( sqlite3_mutex_held(pcache1.mutex) );
 static void *pcache1Alloc(int nByte){
   void *p;
   assert( sqlite3_mutex_held(pcache1.mutex) );

+  sqlite3StatusSet(SQLITE_STATUS_PAGECACHE_SIZE, nByte);

   if( nByte<=pcache1.szSlot && pcache1.pFree ){
     assert( pcache1.isInit );
     p = (PgHdr1 *)pcache1.pFree;
     pcache1.pFree = pcache1.pFree->pNext;
   if( nByte<=pcache1.szSlot && pcache1.pFree ){
     assert( pcache1.isInit );
     p = (PgHdr1 *)pcache1.pFree;
     pcache1.pFree = pcache1.pFree->pNext;

-    sqlite3StatusSet(SQLITE_STATUS_PAGECACHE_SIZE, nByte);

     sqlite3StatusAdd(SQLITE_STATUS_PAGECACHE_USED, 1);
   }else{
 
     sqlite3StatusAdd(SQLITE_STATUS_PAGECACHE_USED, 1);
   }else{
 


@@ -32751,6 +33014,25 @@ static void pcache1Free(void *p){
   }
 }
 
   }
 }
 

+#ifdef SQLITE_ENABLE_MEMORY_MANAGEMENT
+/*
+** Return the size of a pache allocation
+*/
+static int pcache1MemSize(void *p){
+  assert( sqlite3_mutex_held(pcache1.mutex) );
+  if( p>=pcache1.pStart && p<pcache1.pEnd ){
+    return pcache1.szSlot;
+  }else{
+    int iSize;
+    assert( sqlite3MemdebugHasType(p, MEMTYPE_PCACHE) );
+    sqlite3MemdebugSetType(p, MEMTYPE_HEAP);
+    iSize = sqlite3MallocSize(p);
+    sqlite3MemdebugSetType(p, MEMTYPE_PCACHE);
+    return iSize;
+  }
+}
+#endif /* SQLITE_ENABLE_MEMORY_MANAGEMENT */
+

 /*
 ** Allocate a new page object initially associated with cache pCache.
 */
 /*
 ** Allocate a new page object initially associated with cache pCache.
 */


@@ -33299,7 +33581,7 @@ SQLITE_PRIVATE int sqlite3PcacheReleaseMemory(int nReq){
     PgHdr1 *p;
     pcache1EnterMutex();
     while( (nReq<0 || nFree<nReq) && (p=pcache1.pLruTail) ){
     PgHdr1 *p;
     pcache1EnterMutex();
     while( (nReq<0 || nFree<nReq) && (p=pcache1.pLruTail) ){

-      nFree += sqlite3MallocSize(PGHDR1_TO_PAGE(p));
+      nFree += pcache1MemSize(PGHDR1_TO_PAGE(p));

       pcache1PinPage(p);
       pcache1RemoveFromHash(p);
       pcache1FreePage(p);
       pcache1PinPage(p);
       pcache1RemoveFromHash(p);
       pcache1FreePage(p);


@@ -33808,7 +34090,7 @@ SQLITE_PRIVATE int sqlite3RowSetTest(RowSet *pRowSet, u8 iBatch, sqlite3_int64 i
 # define sqlite3WalBeginReadTransaction(y,z)   0
 # define sqlite3WalEndReadTransaction(z)
 # define sqlite3WalRead(v,w,x,y,z)             0
 # define sqlite3WalBeginReadTransaction(y,z)   0
 # define sqlite3WalEndReadTransaction(z)
 # define sqlite3WalRead(v,w,x,y,z)             0

-# define sqlite3WalDbsize(y,z)
+# define sqlite3WalDbsize(y)                   0

 # define sqlite3WalBeginWriteTransaction(y)    0
 # define sqlite3WalEndWriteTransaction(x)      0
 # define sqlite3WalUndo(x,y,z)                 0
 # define sqlite3WalBeginWriteTransaction(y)    0
 # define sqlite3WalEndWriteTransaction(x)      0
 # define sqlite3WalUndo(x,y,z)                 0


@@ -33844,9 +34126,8 @@ SQLITE_PRIVATE void sqlite3WalEndReadTransaction(Wal *pWal);
 /* Read a page from the write-ahead log, if it is present. */
 SQLITE_PRIVATE int sqlite3WalRead(Wal *pWal, Pgno pgno, int *pInWal, int nOut, u8 *pOut);
 
 /* Read a page from the write-ahead log, if it is present. */
 SQLITE_PRIVATE int sqlite3WalRead(Wal *pWal, Pgno pgno, int *pInWal, int nOut, u8 *pOut);
 

-/* Return the size of the database as it existed at the beginning
-** of the snapshot */
-SQLITE_PRIVATE void sqlite3WalDbsize(Wal *pWal, Pgno *pPgno);
+/* If the WAL is not empty, return the size of the database. */
+SQLITE_PRIVATE Pgno sqlite3WalDbsize(Wal *pWal);

 
 /* Obtain or release the WRITER lock. */
 SQLITE_PRIVATE int sqlite3WalBeginWriteTransaction(Wal *pWal);
 
 /* Obtain or release the WRITER lock. */
 SQLITE_PRIVATE int sqlite3WalBeginWriteTransaction(Wal *pWal);


@@ -33892,8 +34173,12 @@ SQLITE_PRIVATE int sqlite3WalExclusiveMode(Wal *pWal, int op);
 /************** End of wal.h *************************************************/
 /************** Continuing where we left off in pager.c **********************/
 
 /************** End of wal.h *************************************************/
 /************** Continuing where we left off in pager.c **********************/
 

-/*
-******************** NOTES ON THE DESIGN OF THE PAGER ************************
+
+/******************* NOTES ON THE DESIGN OF THE PAGER ************************
+**
+** This comment block describes invariants that hold when using a rollback
+** journal.  These invariants do not apply for journal_mode=WAL,
+** journal_mode=MEMORY, or journal_mode=OFF.

 **
 ** Within this comment block, a page is deemed to have been synced
 ** automatically as soon as it is written when PRAGMA synchronous=OFF.
 **
 ** Within this comment block, a page is deemed to have been synced
 ** automatically as soon as it is written when PRAGMA synchronous=OFF.


@@ -33927,7 +34212,7 @@ SQLITE_PRIVATE int sqlite3WalExclusiveMode(Wal *pWal, int op);
 **     transaction.
 ** 
 ** (3) Writes to the database file are an integer multiple of the page size
 **     transaction.
 ** 
 ** (3) Writes to the database file are an integer multiple of the page size

-**     in length and are aligned to a page boundary.
+**     in length and are aligned on a page boundary.

 ** 
 ** (4) Reads from the database file are either aligned on a page boundary and
 **     an integer multiple of the page size in length or are taken from the
 ** 
 ** (4) Reads from the database file are either aligned on a page boundary and
 **     an integer multiple of the page size in length or are taken from the


@@ -33958,7 +34243,8 @@ SQLITE_PRIVATE int sqlite3WalExclusiveMode(Wal *pWal, int op);
 ** 
 ** (9) Whenever the database file is modified, at least one bit in the range
 **     of bytes from 24 through 39 inclusive will be changed prior to releasing
 ** 
 ** (9) Whenever the database file is modified, at least one bit in the range
 **     of bytes from 24 through 39 inclusive will be changed prior to releasing

-**     the EXCLUSIVE lock.
+**     the EXCLUSIVE lock, thus signaling other connections on the same
+**     database to flush their caches.

 **
 ** (10) The pattern of bits in bytes 24 through 39 shall not repeat in less
 **      than one billion transactions.
 **
 ** (10) The pattern of bits in bytes 24 through 39 shall not repeat in less
 **      than one billion transactions.


@@ -33971,7 +34257,8 @@ SQLITE_PRIVATE int sqlite3WalExclusiveMode(Wal *pWal, int op);
 **
 ** (13) A SHARED lock is held on the database file while reading any
 **      content out of the database file.
 **
 ** (13) A SHARED lock is held on the database file while reading any
 **      content out of the database file.

-*/
+**
+******************************************************************************/

 
 /*
 ** Macros for troubleshooting.  Normally turned off
 
 /*
 ** Macros for troubleshooting.  Normally turned off


@@ -33996,58 +34283,279 @@ int sqlite3PagerTrace=1;  /* True to enable tracing */
 #define FILEHANDLEID(fd) ((int)fd)
 
 /*
 #define FILEHANDLEID(fd) ((int)fd)
 
 /*

-** The page cache as a whole is always in one of the following
-** states:
-**
-**   PAGER_UNLOCK        The page cache is not currently reading or 
-**                       writing the database file.  There is no
-**                       data held in memory.  This is the initial
-**                       state.
-**
-**   PAGER_SHARED        The page cache is reading the database.
-**                       Writing is not permitted.  There can be
-**                       multiple readers accessing the same database
-**                       file at the same time.
-**
-**   PAGER_RESERVED      This process has reserved the database for writing
-**                       but has not yet made any changes.  Only one process
-**                       at a time can reserve the database.  The original
-**                       database file has not been modified so other
-**                       processes may still be reading the on-disk
-**                       database file.
-**
-**   PAGER_EXCLUSIVE     The page cache is writing the database.
-**                       Access is exclusive.  No other processes or
-**                       threads can be reading or writing while one
-**                       process is writing.
-**
-**   PAGER_SYNCED        The pager moves to this state from PAGER_EXCLUSIVE
-**                       after all dirty pages have been written to the
-**                       database file and the file has been synced to
-**                       disk. All that remains to do is to remove or
-**                       truncate the journal file and the transaction 
-**                       will be committed.
-**
-** The page cache comes up in PAGER_UNLOCK.  The first time a
-** sqlite3PagerGet() occurs, the state transitions to PAGER_SHARED.
-** After all pages have been released using sqlite_page_unref(),
-** the state transitions back to PAGER_UNLOCK.  The first time
-** that sqlite3PagerWrite() is called, the state transitions to
-** PAGER_RESERVED.  (Note that sqlite3PagerWrite() can only be
-** called on an outstanding page which means that the pager must
-** be in PAGER_SHARED before it transitions to PAGER_RESERVED.)
-** PAGER_RESERVED means that there is an open rollback journal.
-** The transition to PAGER_EXCLUSIVE occurs before any changes
-** are made to the database file, though writes to the rollback
-** journal occurs with just PAGER_RESERVED.  After an sqlite3PagerRollback()
-** or sqlite3PagerCommitPhaseTwo(), the state can go back to PAGER_SHARED,
-** or it can stay at PAGER_EXCLUSIVE if we are in exclusive access mode.
-*/
-#define PAGER_UNLOCK      0
-#define PAGER_SHARED      1   /* same as SHARED_LOCK */
-#define PAGER_RESERVED    2   /* same as RESERVED_LOCK */
-#define PAGER_EXCLUSIVE   4   /* same as EXCLUSIVE_LOCK */
-#define PAGER_SYNCED      5
+** The Pager.eState variable stores the current 'state' of a pager. A
+** pager may be in any one of the seven states shown in the following
+** state diagram.
+**
+**                            OPEN <------+------+
+**                              |         |      |
+**                              V         |      |
+**               +---------> READER-------+      |
+**               |              |                |
+**               |              V                |
+**               |<-------WRITER_LOCKED------> ERROR
+**               |              |                ^  
+**               |              V                |
+**               |<------WRITER_CACHEMOD-------->|
+**               |              |                |
+**               |              V                |
+**               |<-------WRITER_DBMOD---------->|
+**               |              |                |
+**               |              V                |
+**               +<------WRITER_FINISHED-------->+
+**
+**
+** List of state transitions and the C [function] that performs each:
+** 
+**   OPEN              -> READER              [sqlite3PagerSharedLock]
+**   READER            -> OPEN                [pager_unlock]
+**
+**   READER            -> WRITER_LOCKED       [sqlite3PagerBegin]
+**   WRITER_LOCKED     -> WRITER_CACHEMOD     [pager_open_journal]
+**   WRITER_CACHEMOD   -> WRITER_DBMOD        [syncJournal]
+**   WRITER_DBMOD      -> WRITER_FINISHED     [sqlite3PagerCommitPhaseOne]
+**   WRITER_***        -> READER              [pager_end_transaction]
+**
+**   WRITER_***        -> ERROR               [pager_error]
+**   ERROR             -> OPEN                [pager_unlock]
+** 
+**
+**  OPEN:
+**
+**    The pager starts up in this state. Nothing is guaranteed in this
+**    state - the file may or may not be locked and the database size is
+**    unknown. The database may not be read or written.
+**
+**    * No read or write transaction is active.
+**    * Any lock, or no lock at all, may be held on the database file.
+**    * The dbSize, dbOrigSize and dbFileSize variables may not be trusted.
+**
+**  READER:
+**
+**    In this state all the requirements for reading the database in 
+**    rollback (non-WAL) mode are met. Unless the pager is (or recently
+**    was) in exclusive-locking mode, a user-level read transaction is 
+**    open. The database size is known in this state.
+**
+**    A connection running with locking_mode=normal enters this state when
+**    it opens a read-transaction on the database and returns to state
+**    OPEN after the read-transaction is completed. However a connection
+**    running in locking_mode=exclusive (including temp databases) remains in
+**    this state even after the read-transaction is closed. The only way
+**    a locking_mode=exclusive connection can transition from READER to OPEN
+**    is via the ERROR state (see below).
+** 
+**    * A read transaction may be active (but a write-transaction cannot).
+**    * A SHARED or greater lock is held on the database file.
+**    * The dbSize variable may be trusted (even if a user-level read 
+**      transaction is not active). The dbOrigSize and dbFileSize variables
+**      may not be trusted at this point.
+**    * If the database is a WAL database, then the WAL connection is open.
+**    * Even if a read-transaction is not open, it is guaranteed that 
+**      there is no hot-journal in the file-system.
+**
+**  WRITER_LOCKED:
+**
+**    The pager moves to this state from READER when a write-transaction
+**    is first opened on the database. In WRITER_LOCKED state, all locks 
+**    required to start a write-transaction are held, but no actual 
+**    modifications to the cache or database have taken place.
+**
+**    In rollback mode, a RESERVED or (if the transaction was opened with 
+**    BEGIN EXCLUSIVE) EXCLUSIVE lock is obtained on the database file when
+**    moving to this state, but the journal file is not written to or opened 
+**    to in this state. If the transaction is committed or rolled back while 
+**    in WRITER_LOCKED state, all that is required is to unlock the database 
+**    file.
+**
+**    IN WAL mode, WalBeginWriteTransaction() is called to lock the log file.
+**    If the connection is running with locking_mode=exclusive, an attempt
+**    is made to obtain an EXCLUSIVE lock on the database file.
+**
+**    * A write transaction is active.
+**    * If the connection is open in rollback-mode, a RESERVED or greater 
+**      lock is held on the database file.
+**    * If the connection is open in WAL-mode, a WAL write transaction
+**      is open (i.e. sqlite3WalBeginWriteTransaction() has been successfully
+**      called).
+**    * The dbSize, dbOrigSize and dbFileSize variables are all valid.
+**    * The contents of the pager cache have not been modified.
+**    * The journal file may or may not be open.
+**    * Nothing (not even the first header) has been written to the journal.
+**
+**  WRITER_CACHEMOD:
+**
+**    A pager moves from WRITER_LOCKED state to this state when a page is
+**    first modified by the upper layer. In rollback mode the journal file
+**    is opened (if it is not already open) and a header written to the
+**    start of it. The database file on disk has not been modified.
+**
+**    * A write transaction is active.
+**    * A RESERVED or greater lock is held on the database file.
+**    * The journal file is open and the first header has been written 
+**      to it, but the header has not been synced to disk.
+**    * The contents of the page cache have been modified.
+**
+**  WRITER_DBMOD:
+**
+**    The pager transitions from WRITER_CACHEMOD into WRITER_DBMOD state
+**    when it modifies the contents of the database file. WAL connections
+**    never enter this state (since they do not modify the database file,
+**    just the log file).
+**
+**    * A write transaction is active.
+**    * An EXCLUSIVE or greater lock is held on the database file.
+**    * The journal file is open and the first header has been written 
+**      and synced to disk.
+**    * The contents of the page cache have been modified (and possibly
+**      written to disk).
+**
+**  WRITER_FINISHED:
+**
+**    It is not possible for a WAL connection to enter this state.
+**
+**    A rollback-mode pager changes to WRITER_FINISHED state from WRITER_DBMOD
+**    state after the entire transaction has been successfully written into the
+**    database file. In this state the transaction may be committed simply
+**    by finalizing the journal file. Once in WRITER_FINISHED state, it is 
+**    not possible to modify the database further. At this point, the upper 
+**    layer must either commit or rollback the transaction.
+**
+**    * A write transaction is active.
+**    * An EXCLUSIVE or greater lock is held on the database file.
+**    * All writing and syncing of journal and database data has finished.
+**      If no error occured, all that remains is to finalize the journal to
+**      commit the transaction. If an error did occur, the caller will need
+**      to rollback the transaction. 
+**
+**  ERROR:
+**
+**    The ERROR state is entered when an IO or disk-full error (including
+**    SQLITE_IOERR_NOMEM) occurs at a point in the code that makes it 
+**    difficult to be sure that the in-memory pager state (cache contents, 
+**    db size etc.) are consistent with the contents of the file-system.
+**
+**    Temporary pager files may enter the ERROR state, but in-memory pagers
+**    cannot.
+**
+**    For example, if an IO error occurs while performing a rollback, 
+**    the contents of the page-cache may be left in an inconsistent state.
+**    At this point it would be dangerous to change back to READER state
+**    (as usually happens after a rollback). Any subsequent readers might
+**    report database corruption (due to the inconsistent cache), and if
+**    they upgrade to writers, they may inadvertently corrupt the database
+**    file. To avoid this hazard, the pager switches into the ERROR state
+**    instead of READER following such an error.
+**
+**    Once it has entered the ERROR state, any attempt to use the pager
+**    to read or write data returns an error. Eventually, once all 
+**    outstanding transactions have been abandoned, the pager is able to
+**    transition back to OPEN state, discarding the contents of the 
+**    page-cache and any other in-memory state at the same time. Everything
+**    is reloaded from disk (and, if necessary, hot-journal rollback peformed)
+**    when a read-transaction is next opened on the pager (transitioning
+**    the pager into READER state). At that point the system has recovered 
+**    from the error.
+**
+**    Specifically, the pager jumps into the ERROR state if:
+**
+**      1. An error occurs while attempting a rollback. This happens in
+**         function sqlite3PagerRollback().
+**
+**      2. An error occurs while attempting to finalize a journal file
+**         following a commit in function sqlite3PagerCommitPhaseTwo().
+**
+**      3. An error occurs while attempting to write to the journal or
+**         database file in function pagerStress() in order to free up
+**         memory.
+**
+**    In other cases, the error is returned to the b-tree layer. The b-tree
+**    layer then attempts a rollback operation. If the error condition 
+**    persists, the pager enters the ERROR state via condition (1) above.
+**
+**    Condition (3) is necessary because it can be triggered by a read-only
+**    statement executed within a transaction. In this case, if the error
+**    code were simply returned to the user, the b-tree layer would not
+**    automatically attempt a rollback, as it assumes that an error in a
+**    read-only statement cannot leave the pager in an internally inconsistent 
+**    state.
+**
+**    * The Pager.errCode variable is set to something other than SQLITE_OK.
+**    * There are one or more outstanding references to pages (after the
+**      last reference is dropped the pager should move back to OPEN state).
+**    * The pager is not an in-memory pager.
+**    
+**
+** Notes:
+**
+**   * A pager is never in WRITER_DBMOD or WRITER_FINISHED state if the
+**     connection is open in WAL mode. A WAL connection is always in one
+**     of the first four states.
+**
+**   * Normally, a connection open in exclusive mode is never in PAGER_OPEN
+**     state. There are two exceptions: immediately after exclusive-mode has
+**     been turned on (and before any read or write transactions are 
+**     executed), and when the pager is leaving the "error state".
+**
+**   * See also: assert_pager_state().
+*/
+#define PAGER_OPEN                  0
+#define PAGER_READER                1
+#define PAGER_WRITER_LOCKED         2
+#define PAGER_WRITER_CACHEMOD       3
+#define PAGER_WRITER_DBMOD          4
+#define PAGER_WRITER_FINISHED       5
+#define PAGER_ERROR                 6
+
+/*
+** The Pager.eLock variable is almost always set to one of the 
+** following locking-states, according to the lock currently held on
+** the database file: NO_LOCK, SHARED_LOCK, RESERVED_LOCK or EXCLUSIVE_LOCK.
+** This variable is kept up to date as locks are taken and released by
+** the pagerLockDb() and pagerUnlockDb() wrappers.
+**
+** If the VFS xLock() or xUnlock() returns an error other than SQLITE_BUSY
+** (i.e. one of the SQLITE_IOERR subtypes), it is not clear whether or not
+** the operation was successful. In these circumstances pagerLockDb() and
+** pagerUnlockDb() take a conservative approach - eLock is always updated
+** when unlocking the file, and only updated when locking the file if the
+** VFS call is successful. This way, the Pager.eLock variable may be set
+** to a less exclusive (lower) value than the lock that is actually held
+** at the system level, but it is never set to a more exclusive value.
+**
+** This is usually safe. If an xUnlock fails or appears to fail, there may 
+** be a few redundant xLock() calls or a lock may be held for longer than
+** required, but nothing really goes wrong.
+**
+** The exception is when the database file is unlocked as the pager moves
+** from ERROR to OPEN state. At this point there may be a hot-journal file 
+** in the file-system that needs to be rolled back (as part of a OPEN->SHARED
+** transition, by the same pager or any other). If the call to xUnlock()
+** fails at this point and the pager is left holding an EXCLUSIVE lock, this
+** can confuse the call to xCheckReservedLock() call made later as part
+** of hot-journal detection.
+**
+** xCheckReservedLock() is defined as returning true "if there is a RESERVED 
+** lock held by this process or any others". So xCheckReservedLock may 
+** return true because the caller itself is holding an EXCLUSIVE lock (but
+** doesn't know it because of a previous error in xUnlock). If this happens
+** a hot-journal may be mistaken for a journal being created by an active
+** transaction in another process, causing SQLite to read from the database
+** without rolling it back.
+**
+** To work around this, if a call to xUnlock() fails when unlocking the
+** database in the ERROR state, Pager.eLock is set to UNKNOWN_LOCK. It
+** is only changed back to a real locking state after a successful call
+** to xLock(EXCLUSIVE). Also, the code to do the OPEN->SHARED state transition
+** omits the check for a hot-journal if Pager.eLock is set to UNKNOWN_LOCK 
+** lock. Instead, it assumes a hot-journal exists and obtains an EXCLUSIVE
+** lock on the database file before attempting to roll it back. See function
+** PagerSharedLock() for more detail.
+**
+** Pager.eLock may only be set to UNKNOWN_LOCK when the pager is in 
+** PAGER_OPEN state.
+*/
+#define UNKNOWN_LOCK                (EXCLUSIVE_LOCK+1)

 
 /*
 ** A macro used for invoking the codec if there is one
 
 /*
 ** A macro used for invoking the codec if there is one


@@ -34097,33 +34605,28 @@ struct PagerSavepoint {
 };
 
 /*
 };
 
 /*

-** A open page cache is an instance of the following structure.
+** A open page cache is an instance of struct Pager. A description of
+** some of the more important member variables follows:

 **
 **

-** errCode
+** eState

 **
 **

-**   Pager.errCode may be set to SQLITE_IOERR, SQLITE_CORRUPT, or
-**   or SQLITE_FULL. Once one of the first three errors occurs, it persists
-**   and is returned as the result of every major pager API call.  The
-**   SQLITE_FULL return code is slightly different. It persists only until the
-**   next successful rollback is performed on the pager cache. Also,
-**   SQLITE_FULL does not affect the sqlite3PagerGet() and sqlite3PagerLookup()
-**   APIs, they may still be used successfully.
-**
-** dbSizeValid, dbSize, dbOrigSize, dbFileSize
-**
-**   Managing the size of the database file in pages is a little complicated.
-**   The variable Pager.dbSize contains the number of pages that the database
-**   image currently contains. As the database image grows or shrinks this
-**   variable is updated. The variable Pager.dbFileSize contains the number
-**   of pages in the database file. This may be different from Pager.dbSize
-**   if some pages have been appended to the database image but not yet written
-**   out from the cache to the actual file on disk. Or if the image has been
-**   truncated by an incremental-vacuum operation. The Pager.dbOrigSize variable
-**   contains the number of pages in the database image when the current
-**   transaction was opened. The contents of all three of these variables is
-**   only guaranteed to be correct if the boolean Pager.dbSizeValid is true.
-**
-**   TODO: Under what conditions is dbSizeValid set? Cleared?
+**   The current 'state' of the pager object. See the comment and state
+**   diagram above for a description of the pager state.
+**
+** eLock
+**
+**   For a real on-disk database, the current lock held on the database file -
+**   NO_LOCK, SHARED_LOCK, RESERVED_LOCK or EXCLUSIVE_LOCK.
+**
+**   For a temporary or in-memory database (neither of which require any
+**   locks), this variable is always set to EXCLUSIVE_LOCK. Since such
+**   databases always have Pager.exclusiveMode==1, this tricks the pager
+**   logic into thinking that it already has all the locks it will ever
+**   need (and no reason to release them).
+**
+**   In some (obscure) circumstances, this variable may also be set to
+**   UNKNOWN_LOCK. See the comment above the #define of UNKNOWN_LOCK for
+**   details.

 **
 ** changeCountDone
 **
 **
 ** changeCountDone
 **


@@ -34142,67 +34645,123 @@ struct PagerSavepoint {
 **   need only update the change-counter once, for the first transaction
 **   committed.
 **
 **   need only update the change-counter once, for the first transaction
 **   committed.
 **

-** dbModified
-**
-**   The dbModified flag is set whenever a database page is dirtied.
-**   It is cleared at the end of each transaction.
-**
-**   It is used when committing or otherwise ending a transaction. If
-**   the dbModified flag is clear then less work has to be done.
-**
-** journalStarted
-**
-**   This flag is set whenever the the main journal is opened and
-**   initialized
-**
-**   The point of this flag is that it must be set after the 
-**   first journal header in a journal file has been synced to disk.
-**   After this has happened, new pages appended to the database 
-**   do not need the PGHDR_NEED_SYNC flag set, as they do not need
-**   to wait for a journal sync before they can be written out to
-**   the database file (see function pager_write()).
-**   

 ** setMaster
 **
 ** setMaster
 **

-**   This variable is used to ensure that the master journal file name
-**   (if any) is only written into the journal file once.
-**
-**   When committing a transaction, the master journal file name (if any)
-**   may be written into the journal file while the pager is still in
-**   PAGER_RESERVED state (see CommitPhaseOne() for the action). It
-**   then attempts to upgrade to an exclusive lock. If this attempt
-**   fails, then SQLITE_BUSY may be returned to the user and the user
-**   may attempt to commit the transaction again later (calling
-**   CommitPhaseOne() again). This flag is used to ensure that the 
-**   master journal name is only written to the journal file the first
-**   time CommitPhaseOne() is called.
+**   When PagerCommitPhaseOne() is called to commit a transaction, it may
+**   (or may not) specify a master-journal name to be written into the 
+**   journal file before it is synced to disk.
+**
+**   Whether or not a journal file contains a master-journal pointer affects 
+**   the way in which the journal file is finalized after the transaction is 
+**   committed or rolled back when running in "journal_mode=PERSIST" mode.
+**   If a journal file does not contain a master-journal pointer, it is
+**   finalized by overwriting the first journal header with zeroes. If
+**   it does contain a master-journal pointer the journal file is finalized 
+**   by truncating it to zero bytes, just as if the connection were 
+**   running in "journal_mode=truncate" mode.
+**
+**   Journal files that contain master journal pointers cannot be finalized
+**   simply by overwriting the first journal-header with zeroes, as the
+**   master journal pointer could interfere with hot-journal rollback of any
+**   subsequently interrupted transaction that reuses the journal file.
+**
+**   The flag is cleared as soon as the journal file is finalized (either
+**   by PagerCommitPhaseTwo or PagerRollback). If an IO error prevents the
+**   journal file from being successfully finalized, the setMaster flag
+**   is cleared anyway (and the pager will move to ERROR state).

 **
 ** doNotSpill, doNotSyncSpill
 **
 **
 ** doNotSpill, doNotSyncSpill
 **

-**   When enabled, cache spills are prohibited.  The doNotSpill variable
-**   inhibits all cache spill and doNotSyncSpill inhibits those spills that
-**   would require a journal sync.  The doNotSyncSpill is set and cleared 
-**   by sqlite3PagerWrite() in order to prevent a journal sync from happening 
-**   in between the journalling of two pages on the same sector.  The
-**   doNotSpill value set to prevent pagerStress() from trying to use
-**   the journal during a rollback.
-**
-** needSync
+**   These two boolean variables control the behaviour of cache-spills
+**   (calls made by the pcache module to the pagerStress() routine to
+**   write cached data to the file-system in order to free up memory).

 **
 **

-**   TODO: It might be easier to set this variable in writeJournalHdr()
-**   and writeMasterJournal() only. Change its meaning to "unsynced data
-**   has been written to the journal".
+**   When doNotSpill is non-zero, writing to the database from pagerStress()
+**   is disabled altogether. This is done in a very obscure case that
+**   comes up during savepoint rollback that requires the pcache module
+**   to allocate a new page to prevent the journal file from being written
+**   while it is being traversed by code in pager_playback().
+** 
+**   If doNotSyncSpill is non-zero, writing to the database from pagerStress()
+**   is permitted, but syncing the journal file is not. This flag is set
+**   by sqlite3PagerWrite() when the file-system sector-size is larger than
+**   the database page-size in order to prevent a journal sync from happening 
+**   in between the journalling of two pages on the same sector. 

 **
 ** subjInMemory
 **
 **   This is a boolean variable. If true, then any required sub-journal
 **   is opened as an in-memory journal file. If false, then in-memory
 **   sub-journals are only used for in-memory pager files.
 **
 ** subjInMemory
 **
 **   This is a boolean variable. If true, then any required sub-journal
 **   is opened as an in-memory journal file. If false, then in-memory
 **   sub-journals are only used for in-memory pager files.

+**
+**   This variable is updated by the upper layer each time a new 
+**   write-transaction is opened.
+**
+** dbSize, dbOrigSize, dbFileSize
+**
+**   Variable dbSize is set to the number of pages in the database file.
+**   It is valid in PAGER_READER and higher states (all states except for
+**   OPEN and ERROR). 
+**
+**   dbSize is set based on the size of the database file, which may be 
+**   larger than the size of the database (the value stored at offset
+**   28 of the database header by the btree). If the size of the file
+**   is not an integer multiple of the page-size, the value stored in
+**   dbSize is rounded down (i.e. a 5KB file with 2K page-size has dbSize==2).
+**   Except, any file that is greater than 0 bytes in size is considered
+**   to have at least one page. (i.e. a 1KB file with 2K page-size leads
+**   to dbSize==1).
+**
+**   During a write-transaction, if pages with page-numbers greater than
+**   dbSize are modified in the cache, dbSize is updated accordingly.
+**   Similarly, if the database is truncated using PagerTruncateImage(), 
+**   dbSize is updated.
+**
+**   Variables dbOrigSize and dbFileSize are valid in states 
+**   PAGER_WRITER_LOCKED and higher. dbOrigSize is a copy of the dbSize
+**   variable at the start of the transaction. It is used during rollback,
+**   and to determine whether or not pages need to be journalled before
+**   being modified.
+**
+**   Throughout a write-transaction, dbFileSize contains the size of
+**   the file on disk in pages. It is set to a copy of dbSize when the
+**   write-transaction is first opened, and updated when VFS calls are made
+**   to write or truncate the database file on disk. 
+**
+**   The only reason the dbFileSize variable is required is to suppress 
+**   unnecessary calls to xTruncate() after committing a transaction. If, 
+**   when a transaction is committed, the dbFileSize variable indicates 
+**   that the database file is larger than the database image (Pager.dbSize), 
+**   pager_truncate() is called. The pager_truncate() call uses xFilesize()
+**   to measure the database file on disk, and then truncates it if required.
+**   dbFileSize is not used when rolling back a transaction. In this case
+**   pager_truncate() is called unconditionally (which means there may be
+**   a call to xFilesize() that is not strictly required). In either case,
+**   pager_truncate() may cause the file to become smaller or larger.
+**
+** dbHintSize
+**
+**   The dbHintSize variable is used to limit the number of calls made to
+**   the VFS xFileControl(FCNTL_SIZE_HINT) method. 
+**
+**   dbHintSize is set to a copy of the dbSize variable when a
+**   write-transaction is opened (at the same time as dbFileSize and
+**   dbOrigSize). If the xFileControl(FCNTL_SIZE_HINT) method is called,
+**   dbHintSize is increased to the number of pages that correspond to the
+**   size-hint passed to the method call. See pager_write_pagelist() for 
+**   details.
+**
+** errCode
+**
+**   The Pager.errCode variable is only ever used in PAGER_ERROR state. It
+**   is set to zero in all other states. In PAGER_ERROR state, Pager.errCode 
+**   is always set to SQLITE_FULL, SQLITE_IOERR or one of the SQLITE_IOERR_XXX 
+**   sub-codes.

 */
 struct Pager {
   sqlite3_vfs *pVfs;          /* OS functions to use for IO */
   u8 exclusiveMode;           /* Boolean. True if locking_mode==EXCLUSIVE */
 */
 struct Pager {
   sqlite3_vfs *pVfs;          /* OS functions to use for IO */
   u8 exclusiveMode;           /* Boolean. True if locking_mode==EXCLUSIVE */

-  u8 journalMode;             /* On of the PAGER_JOURNALMODE_* values */
+  u8 journalMode;             /* One of the PAGER_JOURNALMODE_* values */

   u8 useJournal;              /* Use a rollback journal on this file */
   u8 noReadlock;              /* Do not bother to obtain readlocks */
   u8 noSync;                  /* Do not sync the journal if true */
   u8 useJournal;              /* Use a rollback journal on this file */
   u8 noReadlock;              /* Do not bother to obtain readlocks */
   u8 noSync;                  /* Do not sync the journal if true */


@@ -34212,30 +34771,26 @@ struct Pager {
   u8 readOnly;                /* True for a read-only database */
   u8 memDb;                   /* True to inhibit all file I/O */
 
   u8 readOnly;                /* True for a read-only database */
   u8 memDb;                   /* True to inhibit all file I/O */
 

-  /* The following block contains those class members that are dynamically
-  ** modified during normal operations. The other variables in this structure
-  ** are either constant throughout the lifetime of the pager, or else
-  ** used to store configuration parameters that affect the way the pager 
-  ** operates.
-  **
-  ** The 'state' variable is described in more detail along with the
-  ** descriptions of the values it may take - PAGER_UNLOCK etc. Many of the
-  ** other variables in this block are described in the comment directly 
-  ** above this class definition.
-  */
-  u8 state;                   /* PAGER_UNLOCK, _SHARED, _RESERVED, etc. */
-  u8 dbModified;              /* True if there are any changes to the Db */
-  u8 needSync;                /* True if an fsync() is needed on the journal */
-  u8 journalStarted;          /* True if header of journal is synced */
+  /**************************************************************************
+  ** The following block contains those class members that change during
+  ** routine opertion.  Class members not in this block are either fixed
+  ** when the pager is first created or else only change when there is a
+  ** significant mode change (such as changing the page_size, locking_mode,
+  ** or the journal_mode).  From another view, these class members describe
+  ** the "state" of the pager, while other class members describe the
+  ** "configuration" of the pager.
+  */
+  u8 eState;                  /* Pager state (OPEN, READER, WRITER_LOCKED..) */
+  u8 eLock;                   /* Current lock held on database file */

   u8 changeCountDone;         /* Set after incrementing the change-counter */
   u8 setMaster;               /* True if a m-j name has been written to jrnl */
   u8 doNotSpill;              /* Do not spill the cache when non-zero */
   u8 doNotSyncSpill;          /* Do not do a spill that requires jrnl sync */
   u8 changeCountDone;         /* Set after incrementing the change-counter */
   u8 setMaster;               /* True if a m-j name has been written to jrnl */
   u8 doNotSpill;              /* Do not spill the cache when non-zero */
   u8 doNotSyncSpill;          /* Do not do a spill that requires jrnl sync */

-  u8 dbSizeValid;             /* Set when dbSize is correct */

   u8 subjInMemory;            /* True to use in-memory sub-journals */
   Pgno dbSize;                /* Number of pages in the database */
   Pgno dbOrigSize;            /* dbSize before the current transaction */
   Pgno dbFileSize;            /* Number of pages in the database file */
   u8 subjInMemory;            /* True to use in-memory sub-journals */
   Pgno dbSize;                /* Number of pages in the database */
   Pgno dbOrigSize;            /* dbSize before the current transaction */
   Pgno dbFileSize;            /* Number of pages in the database file */

+  Pgno dbHintSize;            /* Value passed to FCNTL_SIZE_HINT call */

   int errCode;                /* One of several kinds of errors */
   int nRec;                   /* Pages journalled since last j-header written */
   u32 cksumInit;              /* Quasi-random value added to every checksum */
   int errCode;                /* One of several kinds of errors */
   int nRec;                   /* Pages journalled since last j-header written */
   u32 cksumInit;              /* Quasi-random value added to every checksum */


@@ -34246,17 +34801,21 @@ struct Pager {
   sqlite3_file *sjfd;         /* File descriptor for sub-journal */
   i64 journalOff;             /* Current write offset in the journal file */
   i64 journalHdr;             /* Byte offset to previous journal header */
   sqlite3_file *sjfd;         /* File descriptor for sub-journal */
   i64 journalOff;             /* Current write offset in the journal file */
   i64 journalHdr;             /* Byte offset to previous journal header */

-  i64 journalSizeLimit;       /* Size limit for persistent journal files */
+  sqlite3_backup *pBackup;    /* Pointer to list of ongoing backup processes */

   PagerSavepoint *aSavepoint; /* Array of active savepoints */
   int nSavepoint;             /* Number of elements in aSavepoint[] */
   char dbFileVers[16];        /* Changes whenever database file changes */
   PagerSavepoint *aSavepoint; /* Array of active savepoints */
   int nSavepoint;             /* Number of elements in aSavepoint[] */
   char dbFileVers[16];        /* Changes whenever database file changes */

-  u32 sectorSize;             /* Assumed sector size during rollback */
+  /*
+  ** End of the routinely-changing class members
+  ***************************************************************************/

 
   u16 nExtra;                 /* Add this many bytes to each in-memory page */
   i16 nReserve;               /* Number of unused bytes at end of each page */
   u32 vfsFlags;               /* Flags for sqlite3_vfs.xOpen() */
 
   u16 nExtra;                 /* Add this many bytes to each in-memory page */
   i16 nReserve;               /* Number of unused bytes at end of each page */
   u32 vfsFlags;               /* Flags for sqlite3_vfs.xOpen() */

+  u32 sectorSize;             /* Assumed sector size during rollback */

   int pageSize;               /* Number of bytes in a page */
   Pgno mxPgno;                /* Maximum allowed size of the database */
   int pageSize;               /* Number of bytes in a page */
   Pgno mxPgno;                /* Maximum allowed size of the database */

+  i64 journalSizeLimit;       /* Size limit for persistent journal files */

   char *zFilename;            /* Name of the database file */
   char *zJournal;             /* Name of the journal file */
   int (*xBusyHandler)(void*); /* Function to call when busy */
   char *zFilename;            /* Name of the database file */
   char *zJournal;             /* Name of the journal file */
   int (*xBusyHandler)(void*); /* Function to call when busy */


@@ -34274,7 +34833,6 @@ struct Pager {
 #endif
   char *pTmpSpace;            /* Pager.pageSize bytes of space for tmp use */
   PCache *pPCache;            /* Pointer to page cache object */
 #endif
   char *pTmpSpace;            /* Pager.pageSize bytes of space for tmp use */
   PCache *pPCache;            /* Pointer to page cache object */

-  sqlite3_backup *pBackup;    /* Pointer to list of ongoing backup processes */

 #ifndef SQLITE_OMIT_WAL
   Wal *pWal;                  /* Write-ahead log used by "journal_mode=wal" */
   char *zWal;                 /* File name for write-ahead log */
 #ifndef SQLITE_OMIT_WAL
   Wal *pWal;                  /* Write-ahead log used by "journal_mode=wal" */
   char *zWal;                 /* File name for write-ahead log */


@@ -34353,22 +34911,221 @@ static const unsigned char aJournalMagic[] = {
 */
 #define PAGER_MAX_PGNO 2147483647
 
 */
 #define PAGER_MAX_PGNO 2147483647
 

+/*
+** The argument to this macro is a file descriptor (type sqlite3_file*).
+** Return 0 if it is not open, or non-zero (but not 1) if it is.
+**
+** This is so that expressions can be written as:
+**
+**   if( isOpen(pPager->jfd) ){ ...
+**
+** instead of
+**
+**   if( pPager->jfd->pMethods ){ ...
+*/
+#define isOpen(pFd) ((pFd)->pMethods)
+
+/*
+** Return true if this pager uses a write-ahead log instead of the usual
+** rollback journal. Otherwise false.
+*/
+#ifndef SQLITE_OMIT_WAL
+static int pagerUseWal(Pager *pPager){
+  return (pPager->pWal!=0);
+}
+#else
+# define pagerUseWal(x) 0
+# define pagerRollbackWal(x) 0
+# define pagerWalFrames(v,w,x,y,z) 0
+# define pagerOpenWalIfPresent(z) SQLITE_OK
+# define pagerBeginReadTransaction(z) SQLITE_OK
+#endif
+

 #ifndef NDEBUG 
 /*
 ** Usage:
 **
 **   assert( assert_pager_state(pPager) );
 #ifndef NDEBUG 
 /*
 ** Usage:
 **
 **   assert( assert_pager_state(pPager) );

+**
+** This function runs many asserts to try to find inconsistencies in
+** the internal state of the Pager object.

 */
 */

-static int assert_pager_state(Pager *pPager){
+static int assert_pager_state(Pager *p){
+  Pager *pPager = p;

 
 

-  /* A temp-file is always in PAGER_EXCLUSIVE or PAGER_SYNCED state. */
-  assert( pPager->tempFile==0 || pPager->state>=PAGER_EXCLUSIVE );
+  /* State must be valid. */
+  assert( p->eState==PAGER_OPEN
+       || p->eState==PAGER_READER
+       || p->eState==PAGER_WRITER_LOCKED
+       || p->eState==PAGER_WRITER_CACHEMOD
+       || p->eState==PAGER_WRITER_DBMOD
+       || p->eState==PAGER_WRITER_FINISHED
+       || p->eState==PAGER_ERROR
+  );

 
 

-  /* The changeCountDone flag is always set for temp-files */
-  assert( pPager->tempFile==0 || pPager->changeCountDone );
+  /* Regardless of the current state, a temp-file connection always behaves
+  ** as if it has an exclusive lock on the database file. It never updates
+  ** the change-counter field, so the changeCountDone flag is always set.
+  */
+  assert( p->tempFile==0 || p->eLock==EXCLUSIVE_LOCK );
+  assert( p->tempFile==0 || pPager->changeCountDone );
+
+  /* If the useJournal flag is clear, the journal-mode must be "OFF". 
+  ** And if the journal-mode is "OFF", the journal file must not be open.
+  */
+  assert( p->journalMode==PAGER_JOURNALMODE_OFF || p->useJournal );
+  assert( p->journalMode!=PAGER_JOURNALMODE_OFF || !isOpen(p->jfd) );
+
+  /* Check that MEMDB implies noSync. And an in-memory journal. Since 
+  ** this means an in-memory pager performs no IO at all, it cannot encounter 
+  ** either SQLITE_IOERR or SQLITE_FULL during rollback or while finalizing 
+  ** a journal file. (although the in-memory journal implementation may 
+  ** return SQLITE_IOERR_NOMEM while the journal file is being written). It 
+  ** is therefore not possible for an in-memory pager to enter the ERROR 
+  ** state.
+  */
+  if( MEMDB ){
+    assert( p->noSync );
+    assert( p->journalMode==PAGER_JOURNALMODE_OFF 
+         || p->journalMode==PAGER_JOURNALMODE_MEMORY 
+    );
+    assert( p->eState!=PAGER_ERROR && p->eState!=PAGER_OPEN );
+    assert( pagerUseWal(p)==0 );
+  }
+
+  /* If changeCountDone is set, a RESERVED lock or greater must be held
+  ** on the file.
+  */
+  assert( pPager->changeCountDone==0 || pPager->eLock>=RESERVED_LOCK );
+  assert( p->eLock!=PENDING_LOCK );
+
+  switch( p->eState ){
+    case PAGER_OPEN:
+      assert( !MEMDB );
+      assert( pPager->errCode==SQLITE_OK );
+      assert( sqlite3PcacheRefCount(pPager->pPCache)==0 || pPager->tempFile );
+      break;
+
+    case PAGER_READER:
+      assert( pPager->errCode==SQLITE_OK );
+      assert( p->eLock!=UNKNOWN_LOCK );
+      assert( p->eLock>=SHARED_LOCK || p->noReadlock );
+      break;
+
+    case PAGER_WRITER_LOCKED:
+      assert( p->eLock!=UNKNOWN_LOCK );
+      assert( pPager->errCode==SQLITE_OK );
+      if( !pagerUseWal(pPager) ){
+        assert( p->eLock>=RESERVED_LOCK );
+      }
+      assert( pPager->dbSize==pPager->dbOrigSize );
+      assert( pPager->dbOrigSize==pPager->dbFileSize );
+      assert( pPager->dbOrigSize==pPager->dbHintSize );
+      assert( pPager->setMaster==0 );
+      break;
+
+    case PAGER_WRITER_CACHEMOD:
+      assert( p->eLock!=UNKNOWN_LOCK );
+      assert( pPager->errCode==SQLITE_OK );
+      if( !pagerUseWal(pPager) ){
+        /* It is possible that if journal_mode=wal here that neither the
+        ** journal file nor the WAL file are open. This happens during
+        ** a rollback transaction that switches from journal_mode=off
+        ** to journal_mode=wal.
+        */
+        assert( p->eLock>=RESERVED_LOCK );
+        assert( isOpen(p->jfd) 
+             || p->journalMode==PAGER_JOURNALMODE_OFF 
+             || p->journalMode==PAGER_JOURNALMODE_WAL 
+        );
+      }
+      assert( pPager->dbOrigSize==pPager->dbFileSize );
+      assert( pPager->dbOrigSize==pPager->dbHintSize );
+      break;
+
+    case PAGER_WRITER_DBMOD:
+      assert( p->eLock==EXCLUSIVE_LOCK );
+      assert( pPager->errCode==SQLITE_OK );
+      assert( !pagerUseWal(pPager) );
+      assert( p->eLock>=EXCLUSIVE_LOCK );
+      assert( isOpen(p->jfd) 
+           || p->journalMode==PAGER_JOURNALMODE_OFF 
+           || p->journalMode==PAGER_JOURNALMODE_WAL 
+      );
+      assert( pPager->dbOrigSize<=pPager->dbHintSize );
+      break;
+
+    case PAGER_WRITER_FINISHED:
+      assert( p->eLock==EXCLUSIVE_LOCK );
+      assert( pPager->errCode==SQLITE_OK );
+      assert( !pagerUseWal(pPager) );
+      assert( isOpen(p->jfd) 
+           || p->journalMode==PAGER_JOURNALMODE_OFF 
+           || p->journalMode==PAGER_JOURNALMODE_WAL 
+      );
+      break;
+
+    case PAGER_ERROR:
+      /* There must be at least one outstanding reference to the pager if
+      ** in ERROR state. Otherwise the pager should have already dropped
+      ** back to OPEN state.
+      */
+      assert( pPager->errCode!=SQLITE_OK );
+      assert( sqlite3PcacheRefCount(pPager->pPCache)>0 );
+      break;
+  }

 
   return 1;
 }
 
   return 1;
 }

+
+/*
+** Return a pointer to a human readable string in a static buffer
+** containing the state of the Pager object passed as an argument. This
+** is intended to be used within debuggers. For example, as an alternative
+** to "print *pPager" in gdb:
+**
+** (gdb) printf "%s", print_pager_state(pPager)
+*/
+static char *print_pager_state(Pager *p){
+  static char zRet[1024];
+
+  sqlite3_snprintf(1024, zRet,
+      "Filename:      %s\n"
+      "State:         %s errCode=%d\n"
+      "Lock:          %s\n"
+      "Locking mode:  locking_mode=%s\n"
+      "Journal mode:  journal_mode=%s\n"
+      "Backing store: tempFile=%d memDb=%d useJournal=%d\n"
+      "Journal:       journalOff=%lld journalHdr=%lld\n"
+      "Size:          dbsize=%d dbOrigSize=%d dbFileSize=%d\n"
+      , p->zFilename
+      , p->eState==PAGER_OPEN            ? "OPEN" :
+        p->eState==PAGER_READER          ? "READER" :
+        p->eState==PAGER_WRITER_LOCKED   ? "WRITER_LOCKED" :
+        p->eState==PAGER_WRITER_CACHEMOD ? "WRITER_CACHEMOD" :
+        p->eState==PAGER_WRITER_DBMOD    ? "WRITER_DBMOD" :
+        p->eState==PAGER_WRITER_FINISHED ? "WRITER_FINISHED" :
+        p->eState==PAGER_ERROR           ? "ERROR" : "?error?"
+      , (int)p->errCode
+      , p->eLock==NO_LOCK         ? "NO_LOCK" :
+        p->eLock==RESERVED_LOCK   ? "RESERVED" :
+        p->eLock==EXCLUSIVE_LOCK  ? "EXCLUSIVE" :
+        p->eLock==SHARED_LOCK     ? "SHARED" :
+        p->eLock==UNKNOWN_LOCK    ? "UNKNOWN" : "?error?"
+      , p->exclusiveMode ? "exclusive" : "normal"
+      , p->journalMode==PAGER_JOURNALMODE_MEMORY   ? "memory" :
+        p->journalMode==PAGER_JOURNALMODE_OFF      ? "off" :
+        p->journalMode==PAGER_JOURNALMODE_DELETE   ? "delete" :
+        p->journalMode==PAGER_JOURNALMODE_PERSIST  ? "persist" :
+        p->journalMode==PAGER_JOURNALMODE_TRUNCATE ? "truncate" :
+        p->journalMode==PAGER_JOURNALMODE_WAL      ? "wal" : "?error?"
+      , (int)p->tempFile, (int)p->memDb, (int)p->useJournal
+      , p->journalOff, p->journalHdr
+      , (int)p->dbSize, (int)p->dbOrigSize, (int)p->dbFileSize
+  );
+
+  return zRet;
+}

 #endif
 
 /*
 #endif
 
 /*


@@ -34421,6 +35178,7 @@ static int read32bits(sqlite3_file *fd, i64 offset, u32 *pRes){
 */
 #define put32bits(A,B)  sqlite3Put4byte((u8*)A,B)
 
 */
 #define put32bits(A,B)  sqlite3Put4byte((u8*)A,B)
 

+

 /*
 ** Write a 32-bit integer into the given file descriptor.  Return SQLITE_OK
 ** on success or an error code is something goes wrong.
 /*
 ** Write a 32-bit integer into the given file descriptor.  Return SQLITE_OK
 ** on success or an error code is something goes wrong.


@@ -34432,27 +35190,53 @@ static int write32bits(sqlite3_file *fd, i64 offset, u32 val){
 }
 
 /*
 }
 
 /*

-** The argument to this macro is a file descriptor (type sqlite3_file*).
-** Return 0 if it is not open, or non-zero (but not 1) if it is.
-**
-** This is so that expressions can be written as:
-**
-**   if( isOpen(pPager->jfd) ){ ...
+** Unlock the database file to level eLock, which must be either NO_LOCK
+** or SHARED_LOCK. Regardless of whether or not the call to xUnlock()
+** succeeds, set the Pager.eLock variable to match the (attempted) new lock.

 **
 **

-** instead of
-**
-**   if( pPager->jfd->pMethods ){ ...
+** Except, if Pager.eLock is set to UNKNOWN_LOCK when this function is
+** called, do not modify it. See the comment above the #define of 
+** UNKNOWN_LOCK for an explanation of this.

 */
 */

-#define isOpen(pFd) ((pFd)->pMethods)
+static int pagerUnlockDb(Pager *pPager, int eLock){
+  int rc = SQLITE_OK;
+
+  assert( !pPager->exclusiveMode );
+  assert( eLock==NO_LOCK || eLock==SHARED_LOCK );
+  assert( eLock!=NO_LOCK || pagerUseWal(pPager)==0 );
+  if( isOpen(pPager->fd) ){
+    assert( pPager->eLock>=eLock );
+    rc = sqlite3OsUnlock(pPager->fd, eLock);
+    if( pPager->eLock!=UNKNOWN_LOCK ){
+      pPager->eLock = (u8)eLock;
+    }
+    IOTRACE(("UNLOCK %p %d\n", pPager, eLock))
+  }
+  return rc;
+}

 
 /*
 
 /*

-** If file pFd is open, call sqlite3OsUnlock() on it.
+** Lock the database file to level eLock, which must be either SHARED_LOCK,
+** RESERVED_LOCK or EXCLUSIVE_LOCK. If the caller is successful, set the
+** Pager.eLock variable to the new locking state. 
+**
+** Except, if Pager.eLock is set to UNKNOWN_LOCK when this function is 
+** called, do not modify it unless the new locking state is EXCLUSIVE_LOCK. 
+** See the comment above the #define of UNKNOWN_LOCK for an explanation 
+** of this.

 */
 */

-static int osUnlock(sqlite3_file *pFd, int eLock){
-  if( !isOpen(pFd) ){
-    return SQLITE_OK;
+static int pagerLockDb(Pager *pPager, int eLock){
+  int rc = SQLITE_OK;
+
+  assert( eLock==SHARED_LOCK || eLock==RESERVED_LOCK || eLock==EXCLUSIVE_LOCK );
+  if( pPager->eLock<eLock || pPager->eLock==UNKNOWN_LOCK ){
+    rc = sqlite3OsLock(pPager->fd, eLock);
+    if( rc==SQLITE_OK && (pPager->eLock!=UNKNOWN_LOCK||eLock==EXCLUSIVE_LOCK) ){
+      pPager->eLock = (u8)eLock;
+      IOTRACE(("LOCK %p %d\n", pPager, eLock))
+    }

   }
   }

-  return sqlite3OsUnlock(pFd, eLock);
+  return rc;

 }
 
 /*
 }
 
 /*


@@ -34528,13 +35312,14 @@ static void pager_set_pagehash(PgHdr *pPage){
 #define CHECK_PAGE(x) checkPage(x)
 static void checkPage(PgHdr *pPg){
   Pager *pPager = pPg->pPager;
 #define CHECK_PAGE(x) checkPage(x)
 static void checkPage(PgHdr *pPg){
   Pager *pPager = pPg->pPager;

-  assert( !pPg->pageHash || pPager->errCode
-      || (pPg->flags&PGHDR_DIRTY) || pPg->pageHash==pager_pagehash(pPg) );
+  assert( pPager->eState!=PAGER_ERROR );
+  assert( (pPg->flags&PGHDR_DIRTY) || pPg->pageHash==pager_pagehash(pPg) );

 }
 
 #else
 #define pager_datahash(X,Y)  0
 #define pager_pagehash(X)  0
 }
 
 #else
 #define pager_datahash(X,Y)  0
 #define pager_pagehash(X)  0

+#define pager_set_pagehash(X)

 #define CHECK_PAGE(x)
 #endif  /* SQLITE_CHECK_PAGES */
 
 #define CHECK_PAGE(x)
 #endif  /* SQLITE_CHECK_PAGES */
 


@@ -34701,7 +35486,7 @@ static int zeroJournalHdr(Pager *pPager, int doTruncate){
 static int writeJournalHdr(Pager *pPager){
   int rc = SQLITE_OK;                 /* Return code */
   char *zHeader = pPager->pTmpSpace;  /* Temporary space used to build header */
 static int writeJournalHdr(Pager *pPager){
   int rc = SQLITE_OK;                 /* Return code */
   char *zHeader = pPager->pTmpSpace;  /* Temporary space used to build header */

-  u32 nHeader = pPager->pageSize;     /* Size of buffer pointed to by zHeader */
+  u32 nHeader = (u32)pPager->pageSize;/* Size of buffer pointed to by zHeader */

   u32 nWrite;                         /* Bytes of header sector written */
   int ii;                             /* Loop counter */
 
   u32 nWrite;                         /* Bytes of header sector written */
   int ii;                             /* Loop counter */
 


@@ -34744,7 +35529,7 @@ static int writeJournalHdr(Pager *pPager){
   **     that garbage data is never appended to the journal file.
   */
   assert( isOpen(pPager->fd) || pPager->noSync );
   **     that garbage data is never appended to the journal file.
   */
   assert( isOpen(pPager->fd) || pPager->noSync );

-  if( (pPager->noSync) || (pPager->journalMode==PAGER_JOURNALMODE_MEMORY)
+  if( pPager->noSync || (pPager->journalMode==PAGER_JOURNALMODE_MEMORY)

    || (sqlite3OsDeviceCharacteristics(pPager->fd)&SQLITE_IOCAP_SAFE_APPEND) 
   ){
     memcpy(zHeader, aJournalMagic, sizeof(aJournalMagic));
    || (sqlite3OsDeviceCharacteristics(pPager->fd)&SQLITE_IOCAP_SAFE_APPEND) 
   ){
     memcpy(zHeader, aJournalMagic, sizeof(aJournalMagic));


@@ -34868,7 +35653,6 @@ static int readJournalHdr(
   if( pPager->journalOff==0 ){
     u32 iPageSize;               /* Page-size field of journal header */
     u32 iSectorSize;             /* Sector-size field of journal header */
   if( pPager->journalOff==0 ){
     u32 iPageSize;               /* Page-size field of journal header */
     u32 iSectorSize;             /* Sector-size field of journal header */

-    u16 iPageSize16;             /* Copy of iPageSize in 16-bit variable */

 
     /* Read the page-size and sector-size journal header fields. */
     if( SQLITE_OK!=(rc = read32bits(pPager->jfd, iHdrOff+20, &iSectorSize))
 
     /* Read the page-size and sector-size journal header fields. */
     if( SQLITE_OK!=(rc = read32bits(pPager->jfd, iHdrOff+20, &iSectorSize))


@@ -34877,6 +35661,14 @@ static int readJournalHdr(
       return rc;
     }
 
       return rc;
     }
 

+    /* Versions of SQLite prior to 3.5.8 set the page-size field of the
+    ** journal header to zero. In this case, assume that the Pager.pageSize
+    ** variable is already set to the correct page size.
+    */
+    if( iPageSize==0 ){
+      iPageSize = pPager->pageSize;
+    }
+

     /* Check that the values read from the page-size and sector-size fields
     ** are within range. To be 'in range', both values need to be a power
     ** of two greater than or equal to 512 or 32, and not greater than their 
     /* Check that the values read from the page-size and sector-size fields
     ** are within range. To be 'in range', both values need to be a power
     ** of two greater than or equal to 512 or 32, and not greater than their 


@@ -34898,10 +35690,8 @@ static int readJournalHdr(
     ** Use a testcase() macro to make sure that malloc failure within 
     ** PagerSetPagesize() is tested.
     */
     ** Use a testcase() macro to make sure that malloc failure within 
     ** PagerSetPagesize() is tested.
     */

-    iPageSize16 = (u16)iPageSize;
-    rc = sqlite3PagerSetPagesize(pPager, &iPageSize16, -1);
+    rc = sqlite3PagerSetPagesize(pPager, &iPageSize, -1);

     testcase( rc!=SQLITE_OK );
     testcase( rc!=SQLITE_OK );

-    assert( rc!=SQLITE_OK || iPageSize16==(u16)iPageSize );

 
     /* Update the assumed sector-size to match the value used by 
     ** the process that created this journal. If this journal was
 
     /* Update the assumed sector-size to match the value used by 
     ** the process that created this journal. If this journal was


@@ -34943,7 +35733,10 @@ static int writeMasterJournal(Pager *pPager, const char *zMaster){
   i64 jrnlSize;                    /* Size of journal file on disk */
   u32 cksum = 0;                   /* Checksum of string zMaster */
 
   i64 jrnlSize;                    /* Size of journal file on disk */
   u32 cksum = 0;                   /* Checksum of string zMaster */
 

-  if( !zMaster || pPager->setMaster
+  assert( pPager->setMaster==0 );
+  assert( !pagerUseWal(pPager) );
+
+  if( !zMaster 

    || pPager->journalMode==PAGER_JOURNALMODE_MEMORY 
    || pPager->journalMode==PAGER_JOURNALMODE_OFF 
   ){
    || pPager->journalMode==PAGER_JOURNALMODE_MEMORY 
    || pPager->journalMode==PAGER_JOURNALMODE_OFF 
   ){


@@ -34979,7 +35772,6 @@ static int writeMasterJournal(Pager *pPager, const char *zMaster){
     return rc;
   }
   pPager->journalOff += (nMaster+20);
     return rc;
   }
   pPager->journalOff += (nMaster+20);

-  pPager->needSync = !pPager->noSync;

 
   /* If the pager is in peristent-journal mode, then the physical 
   ** journal-file may extend past the end of the master-journal name
 
   /* If the pager is in peristent-journal mode, then the physical 
   ** journal-file may extend past the end of the master-journal name


@@ -35015,17 +35807,11 @@ static PgHdr *pager_lookup(Pager *pPager, Pgno pgno){
 }
 
 /*
 }
 
 /*

-** Unless the pager is in error-state, discard all in-memory pages. If
-** the pager is in error-state, then this call is a no-op.
-**
-** TODO: Why can we not reset the pager while in error state?
+** Discard the entire contents of the in-memory page-cache.

 */
 static void pager_reset(Pager *pPager){
 */
 static void pager_reset(Pager *pPager){

-  if( SQLITE_OK==pPager->errCode ){
-    sqlite3BackupRestart(pPager->pBackup);
-    sqlite3PcacheClear(pPager->pPCache);
-    pPager->dbSizeValid = 0;
-  }
+  sqlite3BackupRestart(pPager->pBackup);
+  sqlite3PcacheClear(pPager->pPCache);

 }
 
 /*
 }
 
 /*


@@ -35068,34 +35854,39 @@ static int addToSavepointBitvecs(Pager *pPager, Pgno pgno){
 }
 
 /*
 }
 
 /*

-** Return true if this pager uses a write-ahead log instead of the usual
-** rollback journal. Otherwise false.
-*/
-#ifndef SQLITE_OMIT_WAL
-static int pagerUseWal(Pager *pPager){
-  return (pPager->pWal!=0);
-}
-#else
-# define pagerUseWal(x) 0
-# define pagerRollbackWal(x) 0
-# define pagerWalFrames(v,w,x,y,z) 0
-# define pagerOpenWalIfPresent(z) SQLITE_OK
-# define pagerBeginReadTransaction(z) SQLITE_OK
-#endif
-
-/*
-** Unlock the database file. This function is a no-op if the pager
-** is in exclusive mode.
+** This function is a no-op if the pager is in exclusive mode and not
+** in the ERROR state. Otherwise, it switches the pager to PAGER_OPEN
+** state.
+**
+** If the pager is not in exclusive-access mode, the database file is
+** completely unlocked. If the file is unlocked and the file-system does
+** not exhibit the UNDELETABLE_WHEN_OPEN property, the journal file is
+** closed (if it is open).

 **
 **

-** If the pager is currently in error state, discard the contents of 
-** the cache and reset the Pager structure internal state. If there is
-** an open journal-file, then the next time a shared-lock is obtained
-** on the pager file (by this or any other process), it will be
-** treated as a hot-journal and rolled back.
+** If the pager is in ERROR state when this function is called, the 
+** contents of the pager cache are discarded before switching back to 
+** the OPEN state. Regardless of whether the pager is in exclusive-mode
+** or not, any journal file left in the file-system will be treated
+** as a hot-journal and rolled back the next time a read-transaction
+** is opened (by this or by any other connection).

 */
 static void pager_unlock(Pager *pPager){
 */
 static void pager_unlock(Pager *pPager){

-  if( !pPager->exclusiveMode ){
-    int rc = SQLITE_OK;          /* Return code */
+
+  assert( pPager->eState==PAGER_READER 
+       || pPager->eState==PAGER_OPEN 
+       || pPager->eState==PAGER_ERROR 
+  );
+
+  sqlite3BitvecDestroy(pPager->pInJournal);
+  pPager->pInJournal = 0;
+  releaseAllSavepoints(pPager);
+
+  if( pagerUseWal(pPager) ){
+    assert( !isOpen(pPager->jfd) );
+    sqlite3WalEndReadTransaction(pPager->pWal);
+    pPager->eState = PAGER_OPEN;
+  }else if( !pPager->exclusiveMode ){
+    int rc;                       /* Error code returned by pagerUnlockDb() */

     int iDc = isOpen(pPager->fd)?sqlite3OsDeviceCharacteristics(pPager->fd):0;
 
     /* If the operating system support deletion of open files, then
     int iDc = isOpen(pPager->fd)?sqlite3OsDeviceCharacteristics(pPager->fd):0;
 
     /* If the operating system support deletion of open files, then


@@ -35115,58 +35906,56 @@ static void pager_unlock(Pager *pPager){
       sqlite3OsClose(pPager->jfd);
     }
 
       sqlite3OsClose(pPager->jfd);
     }
 

-    sqlite3BitvecDestroy(pPager->pInJournal);
-    pPager->pInJournal = 0;
-    releaseAllSavepoints(pPager);
-
-    /* If the file is unlocked, somebody else might change it. The
-    ** values stored in Pager.dbSize etc. might become invalid if
-    ** this happens.  One can argue that this doesn't need to be cleared
-    ** until the change-counter check fails in PagerSharedLock().
-    ** Clearing the page size cache here is being conservative.
+    /* If the pager is in the ERROR state and the call to unlock the database
+    ** file fails, set the current lock to UNKNOWN_LOCK. See the comment
+    ** above the #define for UNKNOWN_LOCK for an explanation of why this
+    ** is necessary.

     */
     */

-    pPager->dbSizeValid = 0;
-
-    if( pagerUseWal(pPager) ){
-      sqlite3WalEndReadTransaction(pPager->pWal);
-    }else{
-      rc = osUnlock(pPager->fd, NO_LOCK);
-    }
-    if( rc ){
-      pPager->errCode = rc;
+    rc = pagerUnlockDb(pPager, NO_LOCK);
+    if( rc!=SQLITE_OK && pPager->eState==PAGER_ERROR ){
+      pPager->eLock = UNKNOWN_LOCK;

     }
     }

-    IOTRACE(("UNLOCK %p\n", pPager))

 
 

-    /* If Pager.errCode is set, the contents of the pager cache cannot be
-    ** trusted. Now that the pager file is unlocked, the contents of the
-    ** cache can be discarded and the error code safely cleared.
+    /* The pager state may be changed from PAGER_ERROR to PAGER_OPEN here
+    ** without clearing the error code. This is intentional - the error
+    ** code is cleared and the cache reset in the block below.

     */
     */

-    if( pPager->errCode ){
-      if( rc==SQLITE_OK ){
-        pPager->errCode = SQLITE_OK;
-      }
-      pager_reset(pPager);
-    }
-
+    assert( pPager->errCode || pPager->eState!=PAGER_ERROR );

     pPager->changeCountDone = 0;
     pPager->changeCountDone = 0;

-    pPager->state = PAGER_UNLOCK;
-    pPager->dbModified = 0;
+    pPager->eState = PAGER_OPEN;

   }
   }

+
+  /* If Pager.errCode is set, the contents of the pager cache cannot be
+  ** trusted. Now that there are no outstanding references to the pager,
+  ** it can safely move back to PAGER_OPEN state. This happens in both
+  ** normal and exclusive-locking mode.
+  */
+  if( pPager->errCode ){
+    assert( !MEMDB );
+    pager_reset(pPager);
+    pPager->changeCountDone = pPager->tempFile;
+    pPager->eState = PAGER_OPEN;
+    pPager->errCode = SQLITE_OK;
+  }
+
+  pPager->journalOff = 0;
+  pPager->journalHdr = 0;
+  pPager->setMaster = 0;

 }
 
 /*
 }
 
 /*

-** This function should be called when an IOERR, CORRUPT or FULL error
-** may have occurred. The first argument is a pointer to the pager 
-** structure, the second the error-code about to be returned by a pager 
-** API function. The value returned is a copy of the second argument 
-** to this function. 
+** This function is called whenever an IOERR or FULL error that requires
+** the pager to transition into the ERROR state may ahve occurred.
+** The first argument is a pointer to the pager structure, the second 
+** the error-code about to be returned by a pager API function. The 
+** value returned is a copy of the second argument to this function. 

 **
 **

-** If the second argument is SQLITE_IOERR, SQLITE_CORRUPT, or SQLITE_FULL
-** the error becomes persistent. Until the persistent error is cleared,
-** subsequent API calls on this Pager will immediately return the same 
-** error code.
+** If the second argument is SQLITE_FULL, SQLITE_IOERR or one of the
+** IOERR sub-codes, the pager enters the ERROR state and the error code
+** is stored in Pager.errCode. While the pager remains in the ERROR state,
+** all major API calls on the Pager will immediately return Pager.errCode.

 **
 **

-** A persistent error indicates that the contents of the pager-cache 
+** The ERROR state indicates that the contents of the pager-cache 

 ** cannot be trusted. This state can be cleared by completely discarding 
 ** the contents of the pager-cache. If a transaction was active when
 ** the persistent error occurred, then the rollback journal may need
 ** cannot be trusted. This state can be cleared by completely discarding 
 ** the contents of the pager-cache. If a transaction was active when
 ** the persistent error occurred, then the rollback journal may need


@@ -35183,36 +35972,11 @@ static int pager_error(Pager *pPager, int rc){
   );
   if( rc2==SQLITE_FULL || rc2==SQLITE_IOERR ){
     pPager->errCode = rc;
   );
   if( rc2==SQLITE_FULL || rc2==SQLITE_IOERR ){
     pPager->errCode = rc;

+    pPager->eState = PAGER_ERROR;

   }
   return rc;
 }
 
   }
   return rc;
 }
 

-/*
-** Execute a rollback if a transaction is active and unlock the 
-** database file. 
-**
-** If the pager has already entered the error state, do not attempt 
-** the rollback at this time. Instead, pager_unlock() is called. The
-** call to pager_unlock() will discard all in-memory pages, unlock
-** the database file and clear the error state. If this means that
-** there is a hot-journal left in the file-system, the next connection
-** to obtain a shared lock on the pager (which may be this one) will
-** roll it back.
-**
-** If the pager has not already entered the error state, but an IO or
-** malloc error occurs during a rollback, then this will itself cause 
-** the pager to enter the error state. Which will be cleared by the
-** call to pager_unlock(), as described above.
-*/
-static void pagerUnlockAndRollback(Pager *pPager){
-  if( pPager->errCode==SQLITE_OK && pPager->state>=PAGER_RESERVED ){
-    sqlite3BeginBenignMalloc();
-    sqlite3PagerRollback(pPager);
-    sqlite3EndBenignMalloc();
-  }
-  pager_unlock(pPager);
-}
-

 /*
 ** This routine ends a transaction. A transaction is usually ended by 
 ** either a COMMIT or a ROLLBACK operation. This routine may be called 
 /*
 ** This routine ends a transaction. A transaction is usually ended by 
 ** either a COMMIT or a ROLLBACK operation. This routine may be called 


@@ -35220,8 +35984,9 @@ static void pagerUnlockAndRollback(Pager *pPager){
 ** the journal file or writing the very first journal-header of a
 ** database transaction.
 ** 
 ** the journal file or writing the very first journal-header of a
 ** database transaction.
 ** 

-** If the pager is in PAGER_SHARED or PAGER_UNLOCK state when this
-** routine is called, it is a no-op (returns SQLITE_OK).
+** This routine is never called in PAGER_ERROR state. If it is called
+** in PAGER_NONE or PAGER_SHARED state and the lock held is less
+** exclusive than a RESERVED lock, it is a no-op.

 **
 ** Otherwise, any active savepoints are released.
 **
 **
 ** Otherwise, any active savepoints are released.
 **


@@ -35252,13 +36017,9 @@ static void pagerUnlockAndRollback(Pager *pPager){
 **     DELETE and the pager is in exclusive mode, the method described under
 **     journalMode==PERSIST is used instead.
 **
 **     DELETE and the pager is in exclusive mode, the method described under
 **     journalMode==PERSIST is used instead.
 **

-** After the journal is finalized, if running in non-exclusive mode, the
-** pager moves to PAGER_SHARED state (and downgrades the lock on the
-** database file accordingly).
-**
-** If the pager is running in exclusive mode and is in PAGER_SYNCED state,
-** it moves to PAGER_EXCLUSIVE. No locks are downgraded when running in
-** exclusive mode.
+** After the journal is finalized, the pager moves to PAGER_READER state.
+** If running in non-exclusive rollback mode, the lock on the file is 
+** downgraded to a SHARED_LOCK.

 **
 ** SQLITE_OK is returned if no error occurs. If an error occurs during
 ** any of the IO operations to finalize the journal file or unlock the
 **
 ** SQLITE_OK is returned if no error occurs. If an error occurs during
 ** any of the IO operations to finalize the journal file or unlock the


@@ -35273,11 +36034,26 @@ static int pager_end_transaction(Pager *pPager, int hasMaster){
   int rc = SQLITE_OK;      /* Error code from journal finalization operation */
   int rc2 = SQLITE_OK;     /* Error code from db file unlock operation */
 
   int rc = SQLITE_OK;      /* Error code from journal finalization operation */
   int rc2 = SQLITE_OK;     /* Error code from db file unlock operation */
 

-  if( pPager->state<PAGER_RESERVED ){
+  /* Do nothing if the pager does not have an open write transaction
+  ** or at least a RESERVED lock. This function may be called when there
+  ** is no write-transaction active but a RESERVED or greater lock is
+  ** held under two circumstances:
+  **
+  **   1. After a successful hot-journal rollback, it is called with
+  **      eState==PAGER_NONE and eLock==EXCLUSIVE_LOCK.
+  **
+  **   2. If a connection with locking_mode=exclusive holding an EXCLUSIVE 
+  **      lock switches back to locking_mode=normal and then executes a
+  **      read-transaction, this function is called with eState==PAGER_READER 
+  **      and eLock==EXCLUSIVE_LOCK when the read-transaction is closed.
+  */
+  assert( assert_pager_state(pPager) );
+  assert( pPager->eState!=PAGER_ERROR );
+  if( pPager->eState<PAGER_WRITER_LOCKED && pPager->eLock<RESERVED_LOCK ){

     return SQLITE_OK;
   }
     return SQLITE_OK;
   }

-  releaseAllSavepoints(pPager);

 
 

+  releaseAllSavepoints(pPager);

   assert( isOpen(pPager->jfd) || pPager->pInJournal==0 );
   if( isOpen(pPager->jfd) ){
     assert( !pagerUseWal(pPager) );
   assert( isOpen(pPager->jfd) || pPager->pInJournal==0 );
   if( isOpen(pPager->jfd) ){
     assert( !pagerUseWal(pPager) );


@@ -35293,14 +36069,11 @@ static int pager_end_transaction(Pager *pPager, int hasMaster){
         rc = sqlite3OsTruncate(pPager->jfd, 0);
       }
       pPager->journalOff = 0;
         rc = sqlite3OsTruncate(pPager->jfd, 0);
       }
       pPager->journalOff = 0;

-      pPager->journalStarted = 0;

     }else if( pPager->journalMode==PAGER_JOURNALMODE_PERSIST
       || (pPager->exclusiveMode && pPager->journalMode!=PAGER_JOURNALMODE_WAL)
     ){
       rc = zeroJournalHdr(pPager, hasMaster);
     }else if( pPager->journalMode==PAGER_JOURNALMODE_PERSIST
       || (pPager->exclusiveMode && pPager->journalMode!=PAGER_JOURNALMODE_WAL)
     ){
       rc = zeroJournalHdr(pPager, hasMaster);

-      pager_error(pPager, rc);

       pPager->journalOff = 0;
       pPager->journalOff = 0;

-      pPager->journalStarted = 0;

     }else{
       /* This branch may be executed with Pager.journalMode==MEMORY if
       ** a hot-journal was just rolled back. In this case the journal
     }else{
       /* This branch may be executed with Pager.journalMode==MEMORY if
       ** a hot-journal was just rolled back. In this case the journal


@@ -35316,49 +36089,77 @@ static int pager_end_transaction(Pager *pPager, int hasMaster){
         rc = sqlite3OsDelete(pPager->pVfs, pPager->zJournal, 0);
       }
     }
         rc = sqlite3OsDelete(pPager->pVfs, pPager->zJournal, 0);
       }
     }

+  }

 
 #ifdef SQLITE_CHECK_PAGES
 
 #ifdef SQLITE_CHECK_PAGES

-    sqlite3PcacheIterateDirty(pPager->pPCache, pager_set_pagehash);
-#endif
+  sqlite3PcacheIterateDirty(pPager->pPCache, pager_set_pagehash);
+  if( pPager->dbSize==0 && sqlite3PcacheRefCount(pPager->pPCache)>0 ){
+    PgHdr *p = pager_lookup(pPager, 1);
+    if( p ){
+      p->pageHash = 0;
+      sqlite3PagerUnref(p);
+    }

   }
   }

+#endif
+

   sqlite3BitvecDestroy(pPager->pInJournal);
   pPager->pInJournal = 0;
   pPager->nRec = 0;
   sqlite3PcacheCleanAll(pPager->pPCache);
   sqlite3BitvecDestroy(pPager->pInJournal);
   pPager->pInJournal = 0;
   pPager->nRec = 0;
   sqlite3PcacheCleanAll(pPager->pPCache);

+  sqlite3PcacheTruncate(pPager->pPCache, pPager->dbSize);

 
   if( pagerUseWal(pPager) ){
 
   if( pagerUseWal(pPager) ){

+    /* Drop the WAL write-lock, if any. Also, if the connection was in 
+    ** locking_mode=exclusive mode but is no longer, drop the EXCLUSIVE 
+    ** lock held on the database file.
+    */

     rc2 = sqlite3WalEndWriteTransaction(pPager->pWal);
     assert( rc2==SQLITE_OK );
     rc2 = sqlite3WalEndWriteTransaction(pPager->pWal);
     assert( rc2==SQLITE_OK );

-    pPager->state = PAGER_SHARED;
-
-    /* If the connection was in locking_mode=exclusive mode but is no longer,
-    ** drop the EXCLUSIVE lock held on the database file.
-    */
-    if( !pPager->exclusiveMode && sqlite3WalExclusiveMode(pPager->pWal, 0) ){
-      rc2 = osUnlock(pPager->fd, SHARED_LOCK);
-    }
-  }else if( !pPager->exclusiveMode ){
-    rc2 = osUnlock(pPager->fd, SHARED_LOCK);
-    pPager->state = PAGER_SHARED;
+  }
+  if( !pPager->exclusiveMode 
+   && (!pagerUseWal(pPager) || sqlite3WalExclusiveMode(pPager->pWal, 0))
+  ){
+    rc2 = pagerUnlockDb(pPager, SHARED_LOCK);

     pPager->changeCountDone = 0;
     pPager->changeCountDone = 0;

-  }else if( pPager->state==PAGER_SYNCED ){
-    pPager->state = PAGER_EXCLUSIVE;

   }
   }

+  pPager->eState = PAGER_READER;

   pPager->setMaster = 0;
   pPager->setMaster = 0;

-  pPager->needSync = 0;
-  pPager->dbModified = 0;
-
-  /* TODO: Is this optimal? Why is the db size invalidated here 
-  ** when the database file is not unlocked? */
-  pPager->dbOrigSize = 0;
-  sqlite3PcacheTruncate(pPager->pPCache, pPager->dbSize);
-  if( !MEMDB ){
-    pPager->dbSizeValid = 0;
-  }

 
   return (rc==SQLITE_OK?rc2:rc);
 }
 
 
   return (rc==SQLITE_OK?rc2:rc);
 }
 

+/*
+** Execute a rollback if a transaction is active and unlock the 
+** database file. 
+**
+** If the pager has already entered the ERROR state, do not attempt 
+** the rollback at this time. Instead, pager_unlock() is called. The
+** call to pager_unlock() will discard all in-memory pages, unlock
+** the database file and move the pager back to OPEN state. If this 
+** means that there is a hot-journal left in the file-system, the next 
+** connection to obtain a shared lock on the pager (which may be this one) 
+** will roll it back.
+**
+** If the pager has not already entered the ERROR state, but an IO or
+** malloc error occurs during a rollback, then this will itself cause 
+** the pager to enter the ERROR state. Which will be cleared by the
+** call to pager_unlock(), as described above.
+*/
+static void pagerUnlockAndRollback(Pager *pPager){
+  if( pPager->eState!=PAGER_ERROR && pPager->eState!=PAGER_OPEN ){
+    assert( assert_pager_state(pPager) );
+    if( pPager->eState>=PAGER_WRITER_LOCKED ){
+      sqlite3BeginBenignMalloc();
+      sqlite3PagerRollback(pPager);
+      sqlite3EndBenignMalloc();
+    }else if( !pPager->exclusiveMode ){
+      assert( pPager->eState==PAGER_READER );
+      pager_end_transaction(pPager, 0);
+    }
+  }
+  pager_unlock(pPager);
+}
+

 /*
 ** Parameter aData must point to a buffer of pPager->pageSize bytes
 ** of data. Compute and return a checksum based ont the contents of the 
 /*
 ** Parameter aData must point to a buffer of pPager->pageSize bytes
 ** of data. Compute and return a checksum based ont the contents of the 


@@ -35409,9 +36210,8 @@ static void pagerReportSize(Pager *pPager){
 ** The page begins at offset *pOffset into the file. The *pOffset
 ** value is increased to the start of the next page in the journal.
 **
 ** The page begins at offset *pOffset into the file. The *pOffset
 ** value is increased to the start of the next page in the journal.
 **

-** The isMainJrnl flag is true if this is the main rollback journal and
-** false for the statement journal.  The main rollback journal uses
-** checksums - the statement journal does not.
+** The main rollback journal uses checksums - the statement journal does 
+** not.

 **
 ** If the page number of the page record read from the (sub-)journal file
 ** is greater than the current value of Pager.dbSize, then playback is
 **
 ** If the page number of the page record read from the (sub-)journal file
 ** is greater than the current value of Pager.dbSize, then playback is


@@ -35465,6 +36265,17 @@ static int pager_playback_one_page(
   assert( aData );         /* Temp storage must have already been allocated */
   assert( pagerUseWal(pPager)==0 || (!isMainJrnl && isSavepnt) );
 
   assert( aData );         /* Temp storage must have already been allocated */
   assert( pagerUseWal(pPager)==0 || (!isMainJrnl && isSavepnt) );
 

+  /* Either the state is greater than PAGER_WRITER_CACHEMOD (a transaction 
+  ** or savepoint rollback done at the request of the caller) or this is
+  ** a hot-journal rollback. If it is a hot-journal rollback, the pager
+  ** is in state OPEN and holds an EXCLUSIVE lock. Hot-journal rollback
+  ** only reads from the main journal, not the sub-journal.
+  */
+  assert( pPager->eState>=PAGER_WRITER_CACHEMOD
+       || (pPager->eState==PAGER_OPEN && pPager->eLock==EXCLUSIVE_LOCK)
+  );
+  assert( pPager->eState>=PAGER_WRITER_CACHEMOD || isMainJrnl );
+

   /* Read the page number and page data from the journal or sub-journal
   ** file. Return an error code to the caller if an IO error occurs.
   */
   /* Read the page number and page data from the journal or sub-journal
   ** file. Return an error code to the caller if an IO error occurs.
   */


@@ -35501,7 +36312,6 @@ static int pager_playback_one_page(
   if( pDone && (rc = sqlite3BitvecSet(pDone, pgno))!=SQLITE_OK ){
     return rc;
   }
   if( pDone && (rc = sqlite3BitvecSet(pDone, pgno))!=SQLITE_OK ){
     return rc;
   }

-  assert( pPager->state==PAGER_RESERVED || pPager->state>=PAGER_EXCLUSIVE );

 
   /* When playing back page 1, restore the nReserve setting
   */
 
   /* When playing back page 1, restore the nReserve setting
   */


@@ -35510,7 +36320,7 @@ static int pager_playback_one_page(
     pagerReportSize(pPager);
   }
 
     pagerReportSize(pPager);
   }
 

-  /* If the pager is in RESERVED state, then there must be a copy of this
+  /* If the pager is in CACHEMOD state, then there must be a copy of this

   ** page in the pager cache. In this case just update the pager cache,
   ** not the database file. The page is left marked dirty in this case.
   **
   ** page in the pager cache. In this case just update the pager cache,
   ** not the database file. The page is left marked dirty in this case.
   **


@@ -35521,8 +36331,11 @@ static int pager_playback_one_page(
   ** either. So the condition described in the above paragraph is not
   ** assert()able.
   **
   ** either. So the condition described in the above paragraph is not
   ** assert()able.
   **

-  ** If in EXCLUSIVE state, then we update the pager cache if it exists
-  ** and the main file. The page is then marked not dirty.
+  ** If in WRITER_DBMOD, WRITER_FINISHED or OPEN state, then we update the
+  ** pager cache if it exists and the main file. The page is then marked 
+  ** not dirty. Since this code is only executed in PAGER_OPEN state for
+  ** a hot-journal rollback, it is guaranteed that the page-cache is empty
+  ** if the pager is in OPEN state.

   **
   ** Ticket #1171:  The statement journal might contain page content that is
   ** different from the page content at the start of the transaction.
   **
   ** Ticket #1171:  The statement journal might contain page content that is
   ** different from the page content at the start of the transaction.


@@ -35548,6 +36361,7 @@ static int pager_playback_one_page(
     pPg = pager_lookup(pPager, pgno);
   }
   assert( pPg || !MEMDB );
     pPg = pager_lookup(pPager, pgno);
   }
   assert( pPg || !MEMDB );

+  assert( pPager->eState!=PAGER_OPEN || pPg==0 );

   PAGERTRACE(("PLAYBACK %d page %d hash(%08x) %s\n",
            PAGERID(pPager), pgno, pager_datahash(pPager->pageSize, (u8*)aData),
            (isMainJrnl?"main-journal":"sub-journal")
   PAGERTRACE(("PLAYBACK %d page %d hash(%08x) %s\n",
            PAGERID(pPager), pgno, pager_datahash(pPager->pageSize, (u8*)aData),
            (isMainJrnl?"main-journal":"sub-journal")


@@ -35557,8 +36371,8 @@ static int pager_playback_one_page(
   }else{
     isSynced = (pPg==0 || 0==(pPg->flags & PGHDR_NEED_SYNC));
   }
   }else{
     isSynced = (pPg==0 || 0==(pPg->flags & PGHDR_NEED_SYNC));
   }

-  if( (pPager->state>=PAGER_EXCLUSIVE)
-   && isOpen(pPager->fd)
+  if( isOpen(pPager->fd)
+   && (pPager->eState>=PAGER_WRITER_DBMOD || pPager->eState==PAGER_OPEN)

    && isSynced
   ){
     i64 ofst = (pgno-1)*(i64)pPager->pageSize;
    && isSynced
   ){
     i64 ofst = (pgno-1)*(i64)pPager->pageSize;


@@ -35634,9 +36448,8 @@ static int pager_playback_one_page(
       assert( !pagerUseWal(pPager) );
       sqlite3PcacheMakeClean(pPg);
     }
       assert( !pagerUseWal(pPager) );
       sqlite3PcacheMakeClean(pPg);
     }

-#ifdef SQLITE_CHECK_PAGES
-    pPg->pageHash = pager_pagehash(pPg);
-#endif
+    pager_set_pagehash(pPg);
+

     /* If this was page 1, then restore the value of Pager.dbFileVers.
     ** Do this before any decoding. */
     if( pgno==1 ){
     /* If this was page 1, then restore the value of Pager.dbFileVers.
     ** Do this before any decoding. */
     if( pgno==1 ){


@@ -35788,10 +36601,10 @@ delmaster_out:
 ** file in the file-system. This only happens when committing a transaction,
 ** or rolling back a transaction (including rolling back a hot-journal).
 **
 ** file in the file-system. This only happens when committing a transaction,
 ** or rolling back a transaction (including rolling back a hot-journal).
 **

-** If the main database file is not open, or an exclusive lock is not
-** held, this function is a no-op. Otherwise, the size of the file is
-** changed to nPage pages (nPage*pPager->pageSize bytes). If the file
-** on disk is currently larger than nPage pages, then use the VFS
+** If the main database file is not open, or the pager is not in either
+** DBMOD or OPEN state, this function is a no-op. Otherwise, the size 
+** of the file is changed to nPage pages (nPage*pPager->pageSize bytes). 
+** If the file on disk is currently larger than nPage pages, then use the VFS

 ** xTruncate() method to truncate it.
 **
 ** Or, it might might be the case that the file on disk is smaller than 
 ** xTruncate() method to truncate it.
 **
 ** Or, it might might be the case that the file on disk is smaller than 


@@ -35805,8 +36618,14 @@ delmaster_out:
 */
 static int pager_truncate(Pager *pPager, Pgno nPage){
   int rc = SQLITE_OK;
 */
 static int pager_truncate(Pager *pPager, Pgno nPage){
   int rc = SQLITE_OK;

-  if( pPager->state>=PAGER_EXCLUSIVE && isOpen(pPager->fd) ){
+  assert( pPager->eState!=PAGER_ERROR );
+  assert( pPager->eState!=PAGER_READER );
+  
+  if( isOpen(pPager->fd) 
+   && (pPager->eState>=PAGER_WRITER_DBMOD || pPager->eState==PAGER_OPEN) 
+  ){

     i64 currentSize, newSize;
     i64 currentSize, newSize;

+    assert( pPager->eLock==EXCLUSIVE_LOCK );

     /* TODO: Is it safe to use Pager.dbFileSize here? */
     rc = sqlite3OsFileSize(pPager->fd, &currentSize);
     newSize = pPager->pageSize*(i64)nPage;
     /* TODO: Is it safe to use Pager.dbFileSize here? */
     rc = sqlite3OsFileSize(pPager->fd, &currentSize);
     newSize = pPager->pageSize*(i64)nPage;


@@ -35930,7 +36749,7 @@ static int pager_playback(Pager *pPager, int isHot){
   */
   assert( isOpen(pPager->jfd) );
   rc = sqlite3OsFileSize(pPager->jfd, &szJ);
   */
   assert( isOpen(pPager->jfd) );
   rc = sqlite3OsFileSize(pPager->jfd, &szJ);

-  if( rc!=SQLITE_OK || szJ==0 ){
+  if( rc!=SQLITE_OK ){

     goto end_playback;
   }
 
     goto end_playback;
   }
 


@@ -35964,7 +36783,7 @@ static int pager_playback(Pager *pPager, int isHot){
   while( 1 ){
     /* Read the next journal header from the journal file.  If there are
     ** not enough bytes left in the journal file for a complete header, or
   while( 1 ){
     /* Read the next journal header from the journal file.  If there are
     ** not enough bytes left in the journal file for a complete header, or

-    ** it is corrupted, then a process must of failed while writing it.
+    ** it is corrupted, then a process must have failed while writing it.

     ** This indicates nothing more needs to be rolled back.
     */
     rc = readJournalHdr(pPager, isHot, szJ, &nRec, &mxPg);
     ** This indicates nothing more needs to be rolled back.
     */
     rc = readJournalHdr(pPager, isHot, szJ, &nRec, &mxPg);


@@ -36078,10 +36897,9 @@ end_playback:
     rc = readMasterJournal(pPager->jfd, zMaster, pPager->pVfs->mxPathname+1);
     testcase( rc!=SQLITE_OK );
   }
     rc = readMasterJournal(pPager->jfd, zMaster, pPager->pVfs->mxPathname+1);
     testcase( rc!=SQLITE_OK );
   }

-  if( rc==SQLITE_OK && pPager->noSync==0 && pPager->state>=PAGER_EXCLUSIVE ){
-    rc = sqlite3OsSync(pPager->fd, pPager->sync_flags);
-  }
-  if( rc==SQLITE_OK && pPager->noSync==0 && pPager->state>=PAGER_EXCLUSIVE ){
+  if( rc==SQLITE_OK && !pPager->noSync 
+   && (pPager->eState>=PAGER_WRITER_DBMOD || pPager->eState==PAGER_OPEN)
+  ){

     rc = sqlite3OsSync(pPager->fd, pPager->sync_flags);
   }
   if( rc==SQLITE_OK ){
     rc = sqlite3OsSync(pPager->fd, pPager->sync_flags);
   }
   if( rc==SQLITE_OK ){


@@ -36123,7 +36941,7 @@ static int readDbPage(PgHdr *pPg){
   int isInWal = 0;             /* True if page is in log file */
   int pgsz = pPager->pageSize; /* Number of bytes to read */
 
   int isInWal = 0;             /* True if page is in log file */
   int pgsz = pPager->pageSize; /* Number of bytes to read */
 

-  assert( pPager->state>=PAGER_SHARED && !MEMDB );
+  assert( pPager->eState>=PAGER_READER && !MEMDB );

   assert( isOpen(pPager->fd) );
 
   if( NEVER(!isOpen(pPager->fd)) ){
   assert( isOpen(pPager->fd) );
 
   if( NEVER(!isOpen(pPager->fd)) ){


@@ -36270,6 +37088,14 @@ static int pagerWalFrames(
       sqlite3BackupUpdate(pPager->pBackup, p->pgno, (u8 *)p->pData);
     }
   }
       sqlite3BackupUpdate(pPager->pBackup, p->pgno, (u8 *)p->pData);
     }
   }

+
+#ifdef SQLITE_CHECK_PAGES
+  {
+    PgHdr *p;
+    for(p=pList; p; p=p->pDirty) pager_set_pagehash(p);
+  }
+#endif
+

   return rc;
 }
 
   return rc;
 }
 


@@ -36286,6 +37112,7 @@ static int pagerBeginReadTransaction(Pager *pPager){
   int changed = 0;                /* True if cache must be reset */
 
   assert( pagerUseWal(pPager) );
   int changed = 0;                /* True if cache must be reset */
 
   assert( pagerUseWal(pPager) );

+  assert( pPager->eState==PAGER_OPEN || pPager->eState==PAGER_READER );

 
   /* sqlite3WalEndReadTransaction() was not called for the previous
   ** transaction in locking_mode=EXCLUSIVE.  So call it now.  If we
 
   /* sqlite3WalEndReadTransaction() was not called for the previous
   ** transaction in locking_mode=EXCLUSIVE.  So call it now.  If we


@@ -36295,19 +37122,69 @@ static int pagerBeginReadTransaction(Pager *pPager){
   sqlite3WalEndReadTransaction(pPager->pWal);
 
   rc = sqlite3WalBeginReadTransaction(pPager->pWal, &changed);
   sqlite3WalEndReadTransaction(pPager->pWal);
 
   rc = sqlite3WalBeginReadTransaction(pPager->pWal, &changed);

-  if( rc==SQLITE_OK ){
-    int dummy;
-    if( changed ){
-      pager_reset(pPager);
-      assert( pPager->errCode || pPager->dbSizeValid==0 );
-    }
-    rc = sqlite3PagerPagecount(pPager, &dummy);
+  if( rc==SQLITE_OK && changed ){
+    pager_reset(pPager);

   }
   }

-  pPager->state = PAGER_SHARED;

 
   return rc;
 }
 
 
   return rc;
 }
 

+/*
+** This function is called as part of the transition from PAGER_OPEN
+** to PAGER_READER state to determine the size of the database file
+** in pages (assuming the page size currently stored in Pager.pageSize).
+**
+** If no error occurs, SQLITE_OK is returned and the size of the database
+** in pages is stored in *pnPage. Otherwise, an error code (perhaps
+** SQLITE_IOERR_FSTAT) is returned and *pnPage is left unmodified.
+*/
+static int pagerPagecount(Pager *pPager, Pgno *pnPage){
+  Pgno nPage;                     /* Value to return via *pnPage */
+
+  /* Query the WAL sub-system for the database size. The WalDbsize()
+  ** function returns zero if the WAL is not open (i.e. Pager.pWal==0), or
+  ** if the database size is not available. The database size is not
+  ** available from the WAL sub-system if the log file is empty or
+  ** contains no valid committed transactions.
+  */
+  assert( pPager->eState==PAGER_OPEN );
+  assert( pPager->eLock>=SHARED_LOCK || pPager->noReadlock );
+  nPage = sqlite3WalDbsize(pPager->pWal);
+
+  /* If the database size was not available from the WAL sub-system,
+  ** determine it based on the size of the database file. If the size
+  ** of the database file is not an integer multiple of the page-size,
+  ** round down to the nearest page. Except, any file larger than 0
+  ** bytes in size is considered to contain at least one page.
+  */
+  if( nPage==0 ){
+    i64 n = 0;                    /* Size of db file in bytes */
+    assert( isOpen(pPager->fd) || pPager->tempFile );
+    if( isOpen(pPager->fd) ){
+      int rc = sqlite3OsFileSize(pPager->fd, &n);
+      if( rc!=SQLITE_OK ){
+        return rc;
+      }
+    }
+    nPage = (Pgno)(n / pPager->pageSize);
+    if( nPage==0 && n>0 ){
+      nPage = 1;
+    }
+  }
+
+  /* If the current number of pages in the file is greater than the
+  ** configured maximum pager number, increase the allowed limit so
+  ** that the file can be read.
+  */
+  if( nPage>pPager->mxPgno ){
+    pPager->mxPgno = (Pgno)nPage;
+  }
+
+  *pnPage = nPage;
+  return SQLITE_OK;
+}
+
+

 /*
 ** Check if the *-wal file that corresponds to the database opened by pPager
 ** exists if the database is not empy, or verify that the *-wal file does
 /*
 ** Check if the *-wal file that corresponds to the database opened by pPager
 ** exists if the database is not empy, or verify that the *-wal file does


@@ -36320,8 +37197,6 @@ static int pagerBeginReadTransaction(Pager *pPager){
 **
 ** Return SQLITE_OK or an error code.
 **
 **
 ** Return SQLITE_OK or an error code.
 **

-** If the WAL file is opened, also open a snapshot (read transaction).
-**

 ** The caller must hold a SHARED lock on the database file to call this
 ** function. Because an EXCLUSIVE lock on the db file is required to delete 
 ** a WAL on a none-empty database, this ensures there is no race condition 
 ** The caller must hold a SHARED lock on the database file to call this
 ** function. Because an EXCLUSIVE lock on the db file is required to delete 
 ** a WAL on a none-empty database, this ensures there is no race condition 


@@ -36330,11 +37205,14 @@ static int pagerBeginReadTransaction(Pager *pPager){
 */
 static int pagerOpenWalIfPresent(Pager *pPager){
   int rc = SQLITE_OK;
 */
 static int pagerOpenWalIfPresent(Pager *pPager){
   int rc = SQLITE_OK;

+  assert( pPager->eState==PAGER_OPEN );
+  assert( pPager->eLock>=SHARED_LOCK || pPager->noReadlock );
+

   if( !pPager->tempFile ){
     int isWal;                    /* True if WAL file exists */
   if( !pPager->tempFile ){
     int isWal;                    /* True if WAL file exists */

-    int nPage;                    /* Size of the database file */
-    assert( pPager->state>=SHARED_LOCK );
-    rc = sqlite3PagerPagecount(pPager, &nPage);
+    Pgno nPage;                   /* Size of the database file */
+
+    rc = pagerPagecount(pPager, &nPage);

     if( rc ) return rc;
     if( nPage==0 ){
       rc = sqlite3OsDelete(pPager->pVfs, pPager->zWal, 0);
     if( rc ) return rc;
     if( nPage==0 ){
       rc = sqlite3OsDelete(pPager->pVfs, pPager->zWal, 0);


@@ -36346,11 +37224,8 @@ static int pagerOpenWalIfPresent(Pager *pPager){
     }
     if( rc==SQLITE_OK ){
       if( isWal ){
     }
     if( rc==SQLITE_OK ){
       if( isWal ){

-        pager_reset(pPager);
+        testcase( sqlite3PcachePagecount(pPager->pPCache)==0 );

         rc = sqlite3PagerOpenWal(pPager, 0);
         rc = sqlite3PagerOpenWal(pPager, 0);

-        if( rc==SQLITE_OK ){
-          rc = pagerBeginReadTransaction(pPager);
-        }

       }else if( pPager->journalMode==PAGER_JOURNALMODE_WAL ){
         pPager->journalMode = PAGER_JOURNALMODE_DELETE;
       }
       }else if( pPager->journalMode==PAGER_JOURNALMODE_WAL ){
         pPager->journalMode = PAGER_JOURNALMODE_DELETE;
       }


@@ -36402,7 +37277,8 @@ static int pagerPlaybackSavepoint(Pager *pPager, PagerSavepoint *pSavepoint){
   int rc = SQLITE_OK;      /* Return code */
   Bitvec *pDone = 0;       /* Bitvec to ensure pages played back only once */
 
   int rc = SQLITE_OK;      /* Return code */
   Bitvec *pDone = 0;       /* Bitvec to ensure pages played back only once */
 

-  assert( pPager->state>=PAGER_SHARED );
+  assert( pPager->eState!=PAGER_ERROR );
+  assert( pPager->eState>=PAGER_WRITER_LOCKED );

 
   /* Allocate a bitvec to use to store the set of pages rolled back */
   if( pSavepoint ){
 
   /* Allocate a bitvec to use to store the set of pages rolled back */
   if( pSavepoint ){


@@ -36541,7 +37417,6 @@ SQLITE_PRIVATE void sqlite3PagerSetSafetyLevel(Pager *pPager, int level, int bFu
   pPager->noSync =  (level==1 || pPager->tempFile) ?1:0;
   pPager->fullSync = (level==3 && !pPager->tempFile) ?1:0;
   pPager->sync_flags = (bFullFsync?SQLITE_SYNC_FULL:SQLITE_SYNC_NORMAL);
   pPager->noSync =  (level==1 || pPager->tempFile) ?1:0;
   pPager->fullSync = (level==3 && !pPager->tempFile) ?1:0;
   pPager->sync_flags = (bFullFsync?SQLITE_SYNC_FULL:SQLITE_SYNC_NORMAL);

-  if( pPager->noSync ) pPager->needSync = 0;

 }
 #endif
 
 }
 #endif
 


@@ -36623,7 +37498,7 @@ SQLITE_PRIVATE void sqlite3PagerSetBusyhandler(
 **
 ** If the pager is in the error state when this function is called, it
 ** is a no-op. The value returned is the error state error code (i.e. 
 **
 ** If the pager is in the error state when this function is called, it
 ** is a no-op. The value returned is the error state error code (i.e. 

-** one of SQLITE_IOERR, SQLITE_CORRUPT or SQLITE_FULL).
+** one of SQLITE_IOERR, an SQLITE_IOERR_xxx sub-code or SQLITE_FULL).

 **
 ** Otherwise, if all of the following are true:
 **
 **
 ** Otherwise, if all of the following are true:
 **


@@ -36647,28 +37522,48 @@ SQLITE_PRIVATE void sqlite3PagerSetBusyhandler(
 ** function was called, or because the memory allocation attempt failed, 
 ** then *pPageSize is set to the old, retained page size before returning.
 */
 ** function was called, or because the memory allocation attempt failed, 
 ** then *pPageSize is set to the old, retained page size before returning.
 */

-SQLITE_PRIVATE int sqlite3PagerSetPagesize(Pager *pPager, u16 *pPageSize, int nReserve){
-  int rc = pPager->errCode;
+SQLITE_PRIVATE int sqlite3PagerSetPagesize(Pager *pPager, u32 *pPageSize, int nReserve){
+  int rc = SQLITE_OK;

 
 

-  if( rc==SQLITE_OK ){
-    u16 pageSize = *pPageSize;
-    assert( pageSize==0 || (pageSize>=512 && pageSize<=SQLITE_MAX_PAGE_SIZE) );
-    if( (pPager->memDb==0 || pPager->dbSize==0)
-     && sqlite3PcacheRefCount(pPager->pPCache)==0 
-     && pageSize && pageSize!=pPager->pageSize 
-    ){
-      char *pNew = (char *)sqlite3PageMalloc(pageSize);
-      if( !pNew ){
-        rc = SQLITE_NOMEM;
-      }else{
-        pager_reset(pPager);
-        pPager->pageSize = pageSize;
-        sqlite3PageFree(pPager->pTmpSpace);
-        pPager->pTmpSpace = pNew;
-        sqlite3PcacheSetPageSize(pPager->pPCache, pageSize);
-      }
+  /* It is not possible to do a full assert_pager_state() here, as this
+  ** function may be called from within PagerOpen(), before the state
+  ** of the Pager object is internally consistent.
+  **
+  ** At one point this function returned an error if the pager was in 
+  ** PAGER_ERROR state. But since PAGER_ERROR state guarantees that
+  ** there is at least one outstanding page reference, this function
+  ** is a no-op for that case anyhow.
+  */
+
+  u32 pageSize = *pPageSize;
+  assert( pageSize==0 || (pageSize>=512 && pageSize<=SQLITE_MAX_PAGE_SIZE) );
+  if( (pPager->memDb==0 || pPager->dbSize==0)
+   && sqlite3PcacheRefCount(pPager->pPCache)==0 
+   && pageSize && pageSize!=(u32)pPager->pageSize 
+  ){
+    char *pNew = NULL;             /* New temp space */
+    i64 nByte = 0;
+
+    if( pPager->eState>PAGER_OPEN && isOpen(pPager->fd) ){
+      rc = sqlite3OsFileSize(pPager->fd, &nByte);

     }
     }

-    *pPageSize = (u16)pPager->pageSize;
+    if( rc==SQLITE_OK ){
+      pNew = (char *)sqlite3PageMalloc(pageSize);
+      if( !pNew ) rc = SQLITE_NOMEM;
+    }
+
+    if( rc==SQLITE_OK ){
+      pager_reset(pPager);
+      pPager->dbSize = (Pgno)(nByte/pageSize);
+      pPager->pageSize = pageSize;
+      sqlite3PageFree(pPager->pTmpSpace);
+      pPager->pTmpSpace = pNew;
+      sqlite3PcacheSetPageSize(pPager->pPCache, pageSize);
+    }
+  }
+
+  *pPageSize = pPager->pageSize;
+  if( rc==SQLITE_OK ){

     if( nReserve<0 ) nReserve = pPager->nReserve;
     assert( nReserve>=0 && nReserve<1000 );
     pPager->nReserve = (i16)nReserve;
     if( nReserve<0 ) nReserve = pPager->nReserve;
     assert( nReserve>=0 && nReserve<1000 );
     pPager->nReserve = (i16)nReserve;


@@ -36697,13 +37592,11 @@ SQLITE_PRIVATE void *sqlite3PagerTempSpace(Pager *pPager){
 ** Regardless of mxPage, return the current maximum page count.
 */
 SQLITE_PRIVATE int sqlite3PagerMaxPageCount(Pager *pPager, int mxPage){
 ** Regardless of mxPage, return the current maximum page count.
 */
 SQLITE_PRIVATE int sqlite3PagerMaxPageCount(Pager *pPager, int mxPage){

-  int nPage;

   if( mxPage>0 ){
     pPager->mxPgno = mxPage;
   }
   if( mxPage>0 ){
     pPager->mxPgno = mxPage;
   }

-  if( pPager->state!=PAGER_UNLOCK ){
-    sqlite3PagerPagecount(pPager, &nPage);
-    assert( (int)pPager->mxPgno>=nPage );
+  if( pPager->eState!=PAGER_OPEN && pPager->mxPgno<pPager->dbSize ){
+    pPager->mxPgno = pPager->dbSize;

   }
   return pPager->mxPgno;
 }
   }
   return pPager->mxPgno;
 }


@@ -36768,66 +37661,16 @@ SQLITE_PRIVATE int sqlite3PagerReadFileheader(Pager *pPager, int N, unsigned cha
 }
 
 /*
 }
 
 /*

-** Return the total number of pages in the database file associated 
-** with pPager. Normally, this is calculated as (<db file size>/<page-size>).
+** This function may only be called when a read-transaction is open on
+** the pager. It returns the total number of pages in the database.
+**

 ** However, if the file is between 1 and <page-size> bytes in size, then 
 ** this is considered a 1 page file.
 ** However, if the file is between 1 and <page-size> bytes in size, then 
 ** this is considered a 1 page file.

-**
-** If the pager is in error state when this function is called, then the
-** error state error code is returned and *pnPage left unchanged. Or,
-** if the file system has to be queried for the size of the file and
-** the query attempt returns an IO error, the IO error code is returned
-** and *pnPage is left unchanged.
-**
-** Otherwise, if everything is successful, then SQLITE_OK is returned
-** and *pnPage is set to the number of pages in the database.

 */
 */

-SQLITE_PRIVATE int sqlite3PagerPagecount(Pager *pPager, int *pnPage){
-  Pgno nPage = 0;           /* Value to return via *pnPage */
-
-  /* Determine the number of pages in the file. Store this in nPage. */
-  if( pPager->dbSizeValid ){
-    nPage = pPager->dbSize;
-  }else{
-    int rc;                 /* Error returned by OsFileSize() */
-    i64 n = 0;              /* File size in bytes returned by OsFileSize() */
-
-    if( pagerUseWal(pPager) && pPager->state!=PAGER_UNLOCK ){
-      sqlite3WalDbsize(pPager->pWal, &nPage);
-    }
-
-    if( nPage==0 ){
-      assert( isOpen(pPager->fd) || pPager->tempFile );
-      if( isOpen(pPager->fd) ){
-        if( SQLITE_OK!=(rc = sqlite3OsFileSize(pPager->fd, &n)) ){
-          pager_error(pPager, rc);
-          return rc;
-        }
-      }
-      if( n>0 && n<pPager->pageSize ){
-        nPage = 1;
-      }else{
-        nPage = (Pgno)(n / pPager->pageSize);
-      }
-    }
-    if( pPager->state!=PAGER_UNLOCK ){
-      pPager->dbSize = nPage;
-      pPager->dbFileSize = nPage;
-      pPager->dbSizeValid = 1;
-    }
-  }
-
-  /* If the current number of pages in the file is greater than the 
-  ** configured maximum pager number, increase the allowed limit so
-  ** that the file can be read.
-  */
-  if( nPage>pPager->mxPgno ){
-    pPager->mxPgno = (Pgno)nPage;
-  }
-
-  /* Set the output variable and return SQLITE_OK */
-  *pnPage = nPage;
-  return SQLITE_OK;
+SQLITE_PRIVATE void sqlite3PagerPagecount(Pager *pPager, int *pnPage){
+  assert( pPager->eState>=PAGER_READER );
+  assert( pPager->eState!=PAGER_WRITER_FINISHED );
+  *pnPage = (int)pPager->dbSize;

 }
 
 
 }
 
 


@@ -36848,38 +37691,19 @@ SQLITE_PRIVATE int sqlite3PagerPagecount(Pager *pPager, int *pnPage){
 static int pager_wait_on_lock(Pager *pPager, int locktype){
   int rc;                              /* Return code */
 
 static int pager_wait_on_lock(Pager *pPager, int locktype){
   int rc;                              /* Return code */
 

-  /* The OS lock values must be the same as the Pager lock values */
-  assert( PAGER_SHARED==SHARED_LOCK );
-  assert( PAGER_RESERVED==RESERVED_LOCK );
-  assert( PAGER_EXCLUSIVE==EXCLUSIVE_LOCK );
-
-  /* If the file is currently unlocked then the size must be unknown. It
-  ** must not have been modified at this point.
-  */
-  assert( pPager->state>=PAGER_SHARED || pPager->dbSizeValid==0 );
-  assert( pPager->state>=PAGER_SHARED || pPager->dbModified==0 );
-

   /* Check that this is either a no-op (because the requested lock is 
   ** already held, or one of the transistions that the busy-handler
   ** may be invoked during, according to the comment above
   ** sqlite3PagerSetBusyhandler().
   */
   /* Check that this is either a no-op (because the requested lock is 
   ** already held, or one of the transistions that the busy-handler
   ** may be invoked during, according to the comment above
   ** sqlite3PagerSetBusyhandler().
   */

-  assert( (pPager->state>=locktype)
-       || (pPager->state==PAGER_UNLOCK && locktype==PAGER_SHARED)
-       || (pPager->state==PAGER_RESERVED && locktype==PAGER_EXCLUSIVE)
+  assert( (pPager->eLock>=locktype)
+       || (pPager->eLock==NO_LOCK && locktype==SHARED_LOCK)
+       || (pPager->eLock==RESERVED_LOCK && locktype==EXCLUSIVE_LOCK)

   );
 
   );
 

-  if( pPager->state>=locktype ){
-    rc = SQLITE_OK;
-  }else{
-    do {
-      rc = sqlite3OsLock(pPager->fd, locktype);
-    }while( rc==SQLITE_BUSY && pPager->xBusyHandler(pPager->pBusyHandlerArg) );
-    if( rc==SQLITE_OK ){
-      pPager->state = (u8)locktype;
-      IOTRACE(("LOCK %p %d\n", pPager, locktype))
-    }
-  }
+  do {
+    rc = pagerLockDb(pPager, locktype);
+  }while( rc==SQLITE_BUSY && pPager->xBusyHandler(pPager->pBusyHandlerArg) );

   return rc;
 }
 
   return rc;
 }
 


@@ -36924,9 +37748,8 @@ static void assertTruncateConstraint(Pager *pPager){
 ** truncation will be done when the current transaction is committed.
 */
 SQLITE_PRIVATE void sqlite3PagerTruncateImage(Pager *pPager, Pgno nPage){
 ** truncation will be done when the current transaction is committed.
 */
 SQLITE_PRIVATE void sqlite3PagerTruncateImage(Pager *pPager, Pgno nPage){

-  assert( pPager->dbSizeValid );

   assert( pPager->dbSize>=nPage );
   assert( pPager->dbSize>=nPage );

-  assert( pPager->state>=PAGER_RESERVED );
+  assert( pPager->eState>=PAGER_WRITER_CACHEMOD );

   pPager->dbSize = nPage;
   assertTruncateConstraint(pPager);
 }
   pPager->dbSize = nPage;
   assertTruncateConstraint(pPager);
 }


@@ -36976,7 +37799,7 @@ SQLITE_PRIVATE int sqlite3PagerClose(Pager *pPager){
 
   disable_simulated_io_errors();
   sqlite3BeginBenignMalloc();
 
   disable_simulated_io_errors();
   sqlite3BeginBenignMalloc();

-  pPager->errCode = 0;
+  /* pPager->errCode = 0; */

   pPager->exclusiveMode = 0;
 #ifndef SQLITE_OMIT_WAL
   sqlite3WalClose(pPager->pWal,
   pPager->exclusiveMode = 0;
 #ifndef SQLITE_OMIT_WAL
   sqlite3WalClose(pPager->pWal,


@@ -36989,14 +37812,19 @@ SQLITE_PRIVATE int sqlite3PagerClose(Pager *pPager){
   if( MEMDB ){
     pager_unlock(pPager);
   }else{
   if( MEMDB ){
     pager_unlock(pPager);
   }else{

-    /* Set Pager.journalHdr to -1 for the benefit of the pager_playback() 
-    ** call which may be made from within pagerUnlockAndRollback(). If it
-    ** is not -1, then the unsynced portion of an open journal file may
-    ** be played back into the database. If a power failure occurs while
-    ** this is happening, the database may become corrupt.
+    /* If it is open, sync the journal file before calling UnlockAndRollback.
+    ** If this is not done, then an unsynced portion of the open journal 
+    ** file may be played back into the database. If a power failure occurs 
+    ** while this is happening, the database could become corrupt.
+    **
+    ** If an error occurs while trying to sync the journal, shift the pager
+    ** into the ERROR state. This causes UnlockAndRollback to unlock the
+    ** database and close the journal file without attempting to roll it
+    ** back or finalize it. The next database user will have to do hot-journal
+    ** rollback before accessing the database file.

     */
     if( isOpen(pPager->jfd) ){
     */
     if( isOpen(pPager->jfd) ){

-      pPager->errCode = pagerSyncHotJournal(pPager);
+      pager_error(pPager, pagerSyncHotJournal(pPager));

     }
     pagerUnlockAndRollback(pPager);
   }
     }
     pagerUnlockAndRollback(pPager);
   }


@@ -37041,9 +37869,9 @@ SQLITE_PRIVATE void sqlite3PagerRef(DbPage *pPg){
 ** been written to the journal have actually reached the surface of the
 ** disk and can be restored in the event of a hot-journal rollback.
 **
 ** been written to the journal have actually reached the surface of the
 ** disk and can be restored in the event of a hot-journal rollback.
 **

-** If the Pager.needSync flag is not set, then this function is a
-** no-op. Otherwise, the actions required depend on the journal-mode
-** and the device characteristics of the the file-system, as follows:
+** If the Pager.noSync flag is set, then this function is a no-op.
+** Otherwise, the actions required depend on the journal-mode and the 
+** device characteristics of the the file-system, as follows:

 **
 **   * If the journal file is an in-memory journal file, no action need
 **     be taken.
 **
 **   * If the journal file is an in-memory journal file, no action need
 **     be taken.


@@ -37067,18 +37895,25 @@ SQLITE_PRIVATE void sqlite3PagerRef(DbPage *pPg){
 **     if( NOT SEQUENTIAL ) xSync(<journal file>);
 **   }
 **
 **     if( NOT SEQUENTIAL ) xSync(<journal file>);
 **   }
 **

-** The Pager.needSync flag is never be set for temporary files, or any
-** file operating in no-sync mode (Pager.noSync set to non-zero).
-**

 ** If successful, this routine clears the PGHDR_NEED_SYNC flag of every 
 ** page currently held in memory before returning SQLITE_OK. If an IO
 ** error is encountered, then the IO error code is returned to the caller.
 */
 ** If successful, this routine clears the PGHDR_NEED_SYNC flag of every 
 ** page currently held in memory before returning SQLITE_OK. If an IO
 ** error is encountered, then the IO error code is returned to the caller.
 */

-static int syncJournal(Pager *pPager){
-  if( pPager->needSync ){
+static int syncJournal(Pager *pPager, int newHdr){
+  int rc;                         /* Return code */
+
+  assert( pPager->eState==PAGER_WRITER_CACHEMOD
+       || pPager->eState==PAGER_WRITER_DBMOD
+  );
+  assert( assert_pager_state(pPager) );
+  assert( !pagerUseWal(pPager) );
+
+  rc = sqlite3PagerExclusiveLock(pPager);
+  if( rc!=SQLITE_OK ) return rc;
+
+  if( !pPager->noSync ){

     assert( !pPager->tempFile );
     assert( !pPager->tempFile );

-    if( pPager->journalMode!=PAGER_JOURNALMODE_MEMORY ){
-      int rc;                              /* Return code */
+    if( isOpen(pPager->jfd) && pPager->journalMode!=PAGER_JOURNALMODE_MEMORY ){

       const int iDc = sqlite3OsDeviceCharacteristics(pPager->fd);
       assert( isOpen(pPager->jfd) );
 
       const int iDc = sqlite3OsDeviceCharacteristics(pPager->fd);
       assert( isOpen(pPager->jfd) );
 


@@ -37153,17 +37988,25 @@ static int syncJournal(Pager *pPager){
         );
         if( rc!=SQLITE_OK ) return rc;
       }
         );
         if( rc!=SQLITE_OK ) return rc;
       }

-    }

 
 

-    /* The journal file was just successfully synced. Set Pager.needSync 
-    ** to zero and clear the PGHDR_NEED_SYNC flag on all pagess.
-    */
-    pPager->needSync = 0;
-    pPager->journalStarted = 1;
-    pPager->journalHdr = pPager->journalOff;
-    sqlite3PcacheClearSyncFlags(pPager->pPCache);
+      pPager->journalHdr = pPager->journalOff;
+      if( newHdr && 0==(iDc&SQLITE_IOCAP_SAFE_APPEND) ){
+        pPager->nRec = 0;
+        rc = writeJournalHdr(pPager);
+        if( rc!=SQLITE_OK ) return rc;
+      }
+    }else{
+      pPager->journalHdr = pPager->journalOff;
+    }

   }
 
   }
 

+  /* Unless the pager is in noSync mode, the journal file was just 
+  ** successfully synced. Either way, clear the PGHDR_NEED_SYNC flag on 
+  ** all pages.
+  */
+  sqlite3PcacheClearSyncFlags(pPager->pPCache);
+  pPager->eState = PAGER_WRITER_DBMOD;
+  assert( assert_pager_state(pPager) );

   return SQLITE_OK;
 }
 
   return SQLITE_OK;
 }
 


@@ -37200,27 +38043,12 @@ static int syncJournal(Pager *pPager){
 ** be obtained, SQLITE_BUSY is returned.
 */
 static int pager_write_pagelist(Pager *pPager, PgHdr *pList){
 ** be obtained, SQLITE_BUSY is returned.
 */
 static int pager_write_pagelist(Pager *pPager, PgHdr *pList){

-  int rc;                              /* Return code */
+  int rc = SQLITE_OK;                  /* Return code */

 
 

-  /* At this point there may be either a RESERVED or EXCLUSIVE lock on the
-  ** database file. If there is already an EXCLUSIVE lock, the following
-  ** call is a no-op.
-  **
-  ** Moving the lock from RESERVED to EXCLUSIVE actually involves going
-  ** through an intermediate state PENDING.   A PENDING lock prevents new
-  ** readers from attaching to the database but is unsufficient for us to
-  ** write.  The idea of a PENDING lock is to prevent new readers from
-  ** coming in while we wait for existing readers to clear.
-  **
-  ** While the pager is in the RESERVED state, the original database file
-  ** is unchanged and we can rollback without having to playback the
-  ** journal into the original database file.  Once we transition to
-  ** EXCLUSIVE, it means the database file has been changed and any rollback
-  ** will require a journal playback.
-  */
+  /* This function is only called for rollback pagers in WRITER_DBMOD state. */

   assert( !pagerUseWal(pPager) );
   assert( !pagerUseWal(pPager) );

-  assert( pPager->state>=PAGER_RESERVED );
-  rc = pager_wait_on_lock(pPager, EXCLUSIVE_LOCK);
+  assert( pPager->eState==PAGER_WRITER_DBMOD );
+  assert( pPager->eLock==EXCLUSIVE_LOCK );

 
   /* If the file is a temp-file has not yet been opened, open it now. It
   ** is not possible for rc to be other than SQLITE_OK if this branch
 
   /* If the file is a temp-file has not yet been opened, open it now. It
   ** is not possible for rc to be other than SQLITE_OK if this branch


@@ -37235,9 +38063,10 @@ static int pager_write_pagelist(Pager *pPager, PgHdr *pList){
   ** file size will be.
   */
   assert( rc!=SQLITE_OK || isOpen(pPager->fd) );
   ** file size will be.
   */
   assert( rc!=SQLITE_OK || isOpen(pPager->fd) );

-  if( rc==SQLITE_OK && pPager->dbSize>(pPager->dbOrigSize+1) ){
+  if( rc==SQLITE_OK && pPager->dbSize>pPager->dbHintSize ){

     sqlite3_int64 szFile = pPager->pageSize * (sqlite3_int64)pPager->dbSize;
     sqlite3OsFileControl(pPager->fd, SQLITE_FCNTL_SIZE_HINT, &szFile);
     sqlite3_int64 szFile = pPager->pageSize * (sqlite3_int64)pPager->dbSize;
     sqlite3OsFileControl(pPager->fd, SQLITE_FCNTL_SIZE_HINT, &szFile);

+    pPager->dbHintSize = pPager->dbSize;

   }
 
   while( rc==SQLITE_OK && pList ){
   }
 
   while( rc==SQLITE_OK && pList ){


@@ -37255,6 +38084,8 @@ static int pager_write_pagelist(Pager *pPager, PgHdr *pList){
       i64 offset = (pgno-1)*(i64)pPager->pageSize;   /* Offset to write */
       char *pData;                                   /* Data to write */    
 
       i64 offset = (pgno-1)*(i64)pPager->pageSize;   /* Offset to write */
       char *pData;                                   /* Data to write */    
 

+      assert( (pList->flags&PGHDR_NEED_SYNC)==0 );
+

       /* Encode the database */
       CODEC2(pPager, pList->pData, pgno, 6, return SQLITE_NOMEM, pData);
 
       /* Encode the database */
       CODEC2(pPager, pList->pData, pgno, 6, return SQLITE_NOMEM, pData);
 


@@ -37283,9 +38114,7 @@ static int pager_write_pagelist(Pager *pPager, PgHdr *pList){
     }else{
       PAGERTRACE(("NOSTORE %d page %d\n", PAGERID(pPager), pgno));
     }
     }else{
       PAGERTRACE(("NOSTORE %d page %d\n", PAGERID(pPager), pgno));
     }

-#ifdef SQLITE_CHECK_PAGES
-    pList->pageHash = pager_pagehash(pList);
-#endif
+    pager_set_pagehash(pList);

     pList = pList->pDirty;
   }
 
     pList = pList->pDirty;
   }
 


@@ -37397,9 +38226,14 @@ static int pagerStress(void *p, PgHdr *pPg){
   ** The doNotSpill flag inhibits all cache spilling regardless of whether
   ** or not a sync is required.  This is set during a rollback.
   **
   ** The doNotSpill flag inhibits all cache spilling regardless of whether
   ** or not a sync is required.  This is set during a rollback.
   **

-  ** Spilling is also inhibited when in an error state.
-  */
-  if( pPager->errCode ) return SQLITE_OK;
+  ** Spilling is also prohibited when in an error state since that could
+  ** lead to database corruption.   In the current implementaton it 
+  ** is impossible for sqlite3PCacheFetch() to be called with createFlag==1
+  ** while in the error state, hence it is impossible for this routine to
+  ** be called in the error state.  Nevertheless, we include a NEVER()
+  ** test for the error state as a safeguard against future changes.
+  */
+  if( NEVER(pPager->errCode) ) return SQLITE_OK;

   if( pPager->doNotSpill ) return SQLITE_OK;
   if( pPager->doNotSyncSpill && (pPg->flags & PGHDR_NEED_SYNC)!=0 ){
     return SQLITE_OK;
   if( pPager->doNotSpill ) return SQLITE_OK;
   if( pPager->doNotSyncSpill && (pPg->flags & PGHDR_NEED_SYNC)!=0 ){
     return SQLITE_OK;


@@ -37417,16 +38251,10 @@ static int pagerStress(void *p, PgHdr *pPg){
   }else{
   
     /* Sync the journal file if required. */
   }else{
   
     /* Sync the journal file if required. */

-    if( pPg->flags&PGHDR_NEED_SYNC ){
-      assert( !pPager->noSync );
-      rc = syncJournal(pPager);
-      if( rc==SQLITE_OK && 
-        !(pPager->journalMode==PAGER_JOURNALMODE_MEMORY) &&
-        !(sqlite3OsDeviceCharacteristics(pPager->fd)&SQLITE_IOCAP_SAFE_APPEND)
-      ){
-        pPager->nRec = 0;
-        rc = writeJournalHdr(pPager);
-      }
+    if( pPg->flags&PGHDR_NEED_SYNC 
+     || pPager->eState==PAGER_WRITER_CACHEMOD
+    ){
+      rc = syncJournal(pPager, 1);

     }
   
     /* If the page number of this page is larger than the current size of
     }
   
     /* If the page number of this page is larger than the current size of


@@ -37464,6 +38292,7 @@ static int pagerStress(void *p, PgHdr *pPg){
   
     /* Write the contents of the page out to the database file. */
     if( rc==SQLITE_OK ){
   
     /* Write the contents of the page out to the database file. */
     if( rc==SQLITE_OK ){

+      assert( (pPg->flags&PGHDR_NEED_SYNC)==0 );

       rc = pager_write_pagelist(pPager, pPg);
     }
   }
       rc = pager_write_pagelist(pPager, pPg);
     }
   }


@@ -37474,7 +38303,7 @@ static int pagerStress(void *p, PgHdr *pPg){
     sqlite3PcacheMakeClean(pPg);
   }
 
     sqlite3PcacheMakeClean(pPg);
   }
 

-  return pager_error(pPager, rc);
+  return pager_error(pPager, rc); 

 }
 
 
 }
 
 


@@ -37529,7 +38358,7 @@ SQLITE_PRIVATE int sqlite3PagerOpen(
   int useJournal = (flags & PAGER_OMIT_JOURNAL)==0; /* False to omit journal */
   int noReadlock = (flags & PAGER_NO_READLOCK)!=0;  /* True to omit read-lock */
   int pcacheSize = sqlite3PcacheSize();       /* Bytes to allocate for PCache */
   int useJournal = (flags & PAGER_OMIT_JOURNAL)==0; /* False to omit journal */
   int noReadlock = (flags & PAGER_NO_READLOCK)!=0;  /* True to omit read-lock */
   int pcacheSize = sqlite3PcacheSize();       /* Bytes to allocate for PCache */

-  u16 szPageDflt = SQLITE_DEFAULT_PAGE_SIZE;  /* Default page size */
+  u32 szPageDflt = SQLITE_DEFAULT_PAGE_SIZE;  /* Default page size */

 
   /* Figure out how much space is required for each journal file-handle
   ** (there are two of them, the main journal and the sub-journal). This
 
   /* Figure out how much space is required for each journal file-handle
   ** (there are two of them, the main journal and the sub-journal). This


@@ -37664,7 +38493,7 @@ SQLITE_PRIVATE int sqlite3PagerOpen(
         if( pPager->sectorSize>SQLITE_MAX_DEFAULT_PAGE_SIZE ){
           szPageDflt = SQLITE_MAX_DEFAULT_PAGE_SIZE;
         }else{
         if( pPager->sectorSize>SQLITE_MAX_DEFAULT_PAGE_SIZE ){
           szPageDflt = SQLITE_MAX_DEFAULT_PAGE_SIZE;
         }else{

-          szPageDflt = (u16)pPager->sectorSize;
+          szPageDflt = (u32)pPager->sectorSize;

         }
       }
 #ifdef SQLITE_ENABLE_ATOMIC_WRITE
         }
       }
 #ifdef SQLITE_ENABLE_ATOMIC_WRITE


@@ -37692,7 +38521,8 @@ SQLITE_PRIVATE int sqlite3PagerOpen(
     ** disk and uses an in-memory rollback journal.
     */ 
     tempFile = 1;
     ** disk and uses an in-memory rollback journal.
     */ 
     tempFile = 1;

-    pPager->state = PAGER_EXCLUSIVE;
+    pPager->eState = PAGER_READER;
+    pPager->eLock = EXCLUSIVE_LOCK;

     readOnly = (vfsFlags&SQLITE_OPEN_READONLY);
   }
 
     readOnly = (vfsFlags&SQLITE_OPEN_READONLY);
   }
 


@@ -37729,13 +38559,14 @@ SQLITE_PRIVATE int sqlite3PagerOpen(
   /* pPager->stmtOpen = 0; */
   /* pPager->stmtInUse = 0; */
   /* pPager->nRef = 0; */
   /* pPager->stmtOpen = 0; */
   /* pPager->stmtInUse = 0; */
   /* pPager->nRef = 0; */

-  pPager->dbSizeValid = (u8)memDb;

   /* pPager->stmtSize = 0; */
   /* pPager->stmtJSize = 0; */
   /* pPager->nPage = 0; */
   pPager->mxPgno = SQLITE_MAX_PAGE_COUNT;
   /* pPager->state = PAGER_UNLOCK; */
   /* pPager->stmtSize = 0; */
   /* pPager->stmtJSize = 0; */
   /* pPager->nPage = 0; */
   pPager->mxPgno = SQLITE_MAX_PAGE_COUNT;
   /* pPager->state = PAGER_UNLOCK; */

+#if 0

   assert( pPager->state == (tempFile ? PAGER_EXCLUSIVE : PAGER_UNLOCK) );
   assert( pPager->state == (tempFile ? PAGER_EXCLUSIVE : PAGER_UNLOCK) );

+#endif

   /* pPager->errMask = 0; */
   pPager->tempFile = (u8)tempFile;
   assert( tempFile==PAGER_LOCKINGMODE_NORMAL 
   /* pPager->errMask = 0; */
   pPager->tempFile = (u8)tempFile;
   assert( tempFile==PAGER_LOCKINGMODE_NORMAL 


@@ -37745,7 +38576,6 @@ SQLITE_PRIVATE int sqlite3PagerOpen(
   pPager->changeCountDone = pPager->tempFile;
   pPager->memDb = (u8)memDb;
   pPager->readOnly = (u8)readOnly;
   pPager->changeCountDone = pPager->tempFile;
   pPager->memDb = (u8)memDb;
   pPager->readOnly = (u8)readOnly;

-  /* pPager->needSync = 0; */

   assert( useJournal || pPager->tempFile );
   pPager->noSync = pPager->tempFile;
   pPager->fullSync = pPager->noSync ?0:1;
   assert( useJournal || pPager->tempFile );
   pPager->noSync = pPager->tempFile;
   pPager->fullSync = pPager->noSync ?0:1;


@@ -37810,10 +38640,10 @@ static int hasHotJournal(Pager *pPager, int *pExists){
   int exists = 1;               /* True if a journal file is present */
   int jrnlOpen = !!isOpen(pPager->jfd);
 
   int exists = 1;               /* True if a journal file is present */
   int jrnlOpen = !!isOpen(pPager->jfd);
 

-  assert( pPager!=0 );

   assert( pPager->useJournal );
   assert( isOpen(pPager->fd) );
   assert( pPager->useJournal );
   assert( isOpen(pPager->fd) );

-  assert( pPager->state <= PAGER_SHARED );
+  assert( pPager->eState==PAGER_OPEN );
+

   assert( jrnlOpen==0 || ( sqlite3OsDeviceCharacteristics(pPager->jfd) &
     SQLITE_IOCAP_UNDELETABLE_WHEN_OPEN
   ));
   assert( jrnlOpen==0 || ( sqlite3OsDeviceCharacteristics(pPager->jfd) &
     SQLITE_IOCAP_UNDELETABLE_WHEN_OPEN
   ));


@@ -37823,7 +38653,7 @@ static int hasHotJournal(Pager *pPager, int *pExists){
     rc = sqlite3OsAccess(pVfs, pPager->zJournal, SQLITE_ACCESS_EXISTS, &exists);
   }
   if( rc==SQLITE_OK && exists ){
     rc = sqlite3OsAccess(pVfs, pPager->zJournal, SQLITE_ACCESS_EXISTS, &exists);
   }
   if( rc==SQLITE_OK && exists ){

-    int locked;                 /* True if some process holds a RESERVED lock */
+    int locked = 0;             /* True if some process holds a RESERVED lock */

 
     /* Race condition here:  Another process might have been holding the
     ** the RESERVED lock and have a journal open at the sqlite3OsAccess() 
 
     /* Race condition here:  Another process might have been holding the
     ** the RESERVED lock and have a journal open at the sqlite3OsAccess() 


@@ -37835,7 +38665,7 @@ static int hasHotJournal(Pager *pPager, int *pExists){
     */
     rc = sqlite3OsCheckReservedLock(pPager->fd, &locked);
     if( rc==SQLITE_OK && !locked ){
     */
     rc = sqlite3OsCheckReservedLock(pPager->fd, &locked);
     if( rc==SQLITE_OK && !locked ){

-      int nPage;
+      Pgno nPage;                 /* Number of pages in database file */

 
       /* Check the size of the database file. If it consists of 0 pages,
       ** then delete the journal file. See the header comment above for 
 
       /* Check the size of the database file. If it consists of 0 pages,
       ** then delete the journal file. See the header comment above for 


@@ -37843,13 +38673,13 @@ static int hasHotJournal(Pager *pPager, int *pExists){
       ** a RESERVED lock to avoid race conditions and to avoid violating
       ** [H33020].
       */
       ** a RESERVED lock to avoid race conditions and to avoid violating
       ** [H33020].
       */

-      rc = sqlite3PagerPagecount(pPager, &nPage);
+      rc = pagerPagecount(pPager, &nPage);

       if( rc==SQLITE_OK ){
         if( nPage==0 ){
           sqlite3BeginBenignMalloc();
       if( rc==SQLITE_OK ){
         if( nPage==0 ){
           sqlite3BeginBenignMalloc();

-          if( sqlite3OsLock(pPager->fd, RESERVED_LOCK)==SQLITE_OK ){
+          if( pagerLockDb(pPager, RESERVED_LOCK)==SQLITE_OK ){

             sqlite3OsDelete(pVfs, pPager->zJournal, 0);
             sqlite3OsDelete(pVfs, pPager->zJournal, 0);

-            sqlite3OsUnlock(pPager->fd, SHARED_LOCK);
+            pagerUnlockDb(pPager, SHARED_LOCK);

           }
           sqlite3EndBenignMalloc();
         }else{
           }
           sqlite3EndBenignMalloc();
         }else{


@@ -37902,7 +38732,7 @@ static int hasHotJournal(Pager *pPager, int *pExists){
 **
 ** The following operations are also performed by this function.
 **
 **
 ** The following operations are also performed by this function.
 **

-**   1) If the pager is currently in PAGER_UNLOCK state (no lock held
+**   1) If the pager is currently in PAGER_OPEN state (no lock held

 **      on the database file), then an attempt is made to obtain a
 **      SHARED lock on the database file. Immediately after obtaining
 **      the SHARED lock, the file-system is checked for a hot-journal,
 **      on the database file), then an attempt is made to obtain a
 **      SHARED lock on the database file. Immediately after obtaining
 **      the SHARED lock, the file-system is checked for a hot-journal,


@@ -37917,66 +38747,47 @@ static int hasHotJournal(Pager *pPager, int *pExists){
 **      the contents of the page cache and rolling back any open journal
 **      file.
 **
 **      the contents of the page cache and rolling back any open journal
 **      file.
 **

-** If the operation described by (2) above is not attempted, and if the
-** pager is in an error state other than SQLITE_FULL when this is called,
-** the error state error code is returned. It is permitted to read the
-** database when in SQLITE_FULL error state.
-**
-** Otherwise, if everything is successful, SQLITE_OK is returned. If an
-** IO error occurs while locking the database, checking for a hot-journal
-** file or rolling back a journal file, the IO error code is returned.
+** If everything is successful, SQLITE_OK is returned. If an IO error 
+** occurs while locking the database, checking for a hot-journal file or 
+** rolling back a journal file, the IO error code is returned.

 */
 SQLITE_PRIVATE int sqlite3PagerSharedLock(Pager *pPager){
   int rc = SQLITE_OK;                /* Return code */
 */
 SQLITE_PRIVATE int sqlite3PagerSharedLock(Pager *pPager){
   int rc = SQLITE_OK;                /* Return code */

-  int isErrorReset = 0;              /* True if recovering from error state */

 
   /* This routine is only called from b-tree and only when there are no
 
   /* This routine is only called from b-tree and only when there are no

-  ** outstanding pages */
+  ** outstanding pages. This implies that the pager state should either
+  ** be OPEN or READER. READER is only possible if the pager is or was in 
+  ** exclusive access mode.
+  */

   assert( sqlite3PcacheRefCount(pPager->pPCache)==0 );
   assert( sqlite3PcacheRefCount(pPager->pPCache)==0 );

+  assert( assert_pager_state(pPager) );
+  assert( pPager->eState==PAGER_OPEN || pPager->eState==PAGER_READER );

   if( NEVER(MEMDB && pPager->errCode) ){ return pPager->errCode; }
 
   if( NEVER(MEMDB && pPager->errCode) ){ return pPager->errCode; }
 

-  /* If this database is in an error-state, now is a chance to clear
-  ** the error. Discard the contents of the pager-cache and rollback
-  ** any hot journal in the file-system.
-  */
-  if( pPager->errCode ){
-    if( isOpen(pPager->jfd) || pPager->zJournal ){
-      isErrorReset = 1;
-    }
-    pPager->errCode = SQLITE_OK;
-    pager_reset(pPager);
-  }
+  if( !pagerUseWal(pPager) && pPager->eState==PAGER_OPEN ){
+    int bHotJournal = 1;          /* True if there exists a hot journal-file */

 
 

-  if( pagerUseWal(pPager) ){
-    rc = pagerBeginReadTransaction(pPager);
-  }else if( pPager->state==PAGER_UNLOCK || isErrorReset ){
-    sqlite3_vfs * const pVfs = pPager->pVfs;
-    int isHotJournal = 0;

     assert( !MEMDB );
     assert( !MEMDB );

-    assert( sqlite3PcacheRefCount(pPager->pPCache)==0 );
-    if( pPager->noReadlock ){
-      assert( pPager->readOnly );
-      pPager->state = PAGER_SHARED;
-    }else{
+    assert( pPager->noReadlock==0 || pPager->readOnly );
+
+    if( pPager->noReadlock==0 ){

       rc = pager_wait_on_lock(pPager, SHARED_LOCK);
       if( rc!=SQLITE_OK ){
       rc = pager_wait_on_lock(pPager, SHARED_LOCK);
       if( rc!=SQLITE_OK ){

-        assert( pPager->state==PAGER_UNLOCK );
-        return pager_error(pPager, rc);
+        assert( pPager->eLock==NO_LOCK || pPager->eLock==UNKNOWN_LOCK );
+        goto failed;

       }
     }
       }
     }

-    assert( pPager->state>=SHARED_LOCK );

 
     /* If a journal file exists, and there is no RESERVED lock on the
     ** database file, then it either needs to be played back or deleted.
     */
 
     /* If a journal file exists, and there is no RESERVED lock on the
     ** database file, then it either needs to be played back or deleted.
     */

-    if( !isErrorReset ){
-      assert( pPager->state <= PAGER_SHARED );
-      rc = hasHotJournal(pPager, &isHotJournal);
-      if( rc!=SQLITE_OK ){
-        goto failed;
-      }
+    if( pPager->eLock<=SHARED_LOCK ){
+      rc = hasHotJournal(pPager, &bHotJournal);
+    }
+    if( rc!=SQLITE_OK ){
+      goto failed;

     }
     }

-    if( isErrorReset || isHotJournal ){
+    if( bHotJournal ){

       /* Get an EXCLUSIVE lock on the database file. At this point it is
       ** important that a RESERVED lock is not obtained on the way to the
       ** EXCLUSIVE lock. If it were, another process might open the
       /* Get an EXCLUSIVE lock on the database file. At this point it is
       ** important that a RESERVED lock is not obtained on the way to the
       ** EXCLUSIVE lock. If it were, another process might open the


@@ -37988,58 +38799,45 @@ SQLITE_PRIVATE int sqlite3PagerSharedLock(Pager *pPager){
       ** other process attempting to access the database file will get to 
       ** this point in the code and fail to obtain its own EXCLUSIVE lock 
       ** on the database file.
       ** other process attempting to access the database file will get to 
       ** this point in the code and fail to obtain its own EXCLUSIVE lock 
       ** on the database file.

+      **
+      ** Unless the pager is in locking_mode=exclusive mode, the lock is
+      ** downgraded to SHARED_LOCK before this function returns.

       */
       */

-      if( pPager->state<EXCLUSIVE_LOCK ){
-        rc = sqlite3OsLock(pPager->fd, EXCLUSIVE_LOCK);
-        if( rc!=SQLITE_OK ){
-          rc = pager_error(pPager, rc);
-          goto failed;
-        }
-        pPager->state = PAGER_EXCLUSIVE;
+      rc = pagerLockDb(pPager, EXCLUSIVE_LOCK);
+      if( rc!=SQLITE_OK ){
+        goto failed;

       }
  
       }
  

-      /* Open the journal for read/write access. This is because in 
-      ** exclusive-access mode the file descriptor will be kept open and
-      ** possibly used for a transaction later on. On some systems, the
-      ** OsTruncate() call used in exclusive-access mode also requires
-      ** a read/write file handle.
+      /* If it is not already open and the file exists on disk, open the 
+      ** journal for read/write access. Write access is required because 
+      ** in exclusive-access mode the file descriptor will be kept open 
+      ** and possibly used for a transaction later on. Also, write-access 
+      ** is usually required to finalize the journal in journal_mode=persist 
+      ** mode (and also for journal_mode=truncate on some systems).
+      **
+      ** If the journal does not exist, it usually means that some 
+      ** other connection managed to get in and roll it back before 
+      ** this connection obtained the exclusive lock above. Or, it 
+      ** may mean that the pager was in the error-state when this
+      ** function was called and the journal file does not exist.

       */
       if( !isOpen(pPager->jfd) ){
       */
       if( !isOpen(pPager->jfd) ){

-        int res;
-        rc = sqlite3OsAccess(pVfs,pPager->zJournal,SQLITE_ACCESS_EXISTS,&res);
-        if( rc==SQLITE_OK ){
-          if( res ){
-            int fout = 0;
-            int f = SQLITE_OPEN_READWRITE|SQLITE_OPEN_MAIN_JOURNAL;
-            assert( !pPager->tempFile );
-            rc = sqlite3OsOpen(pVfs, pPager->zJournal, pPager->jfd, f, &fout);
-            assert( rc!=SQLITE_OK || isOpen(pPager->jfd) );
-            if( rc==SQLITE_OK && fout&SQLITE_OPEN_READONLY ){
-              rc = SQLITE_CANTOPEN_BKPT;
-              sqlite3OsClose(pPager->jfd);
-            }
-          }else{
-            /* If the journal does not exist, it usually means that some 
-            ** other connection managed to get in and roll it back before 
-            ** this connection obtained the exclusive lock above. Or, it 
-            ** may mean that the pager was in the error-state when this
-            ** function was called and the journal file does not exist.  */
-            rc = pager_end_transaction(pPager, 0);
+        sqlite3_vfs * const pVfs = pPager->pVfs;
+        int bExists;              /* True if journal file exists */
+        rc = sqlite3OsAccess(
+            pVfs, pPager->zJournal, SQLITE_ACCESS_EXISTS, &bExists);
+        if( rc==SQLITE_OK && bExists ){
+          int fout = 0;
+          int f = SQLITE_OPEN_READWRITE|SQLITE_OPEN_MAIN_JOURNAL;
+          assert( !pPager->tempFile );
+          rc = sqlite3OsOpen(pVfs, pPager->zJournal, pPager->jfd, f, &fout);
+          assert( rc!=SQLITE_OK || isOpen(pPager->jfd) );
+          if( rc==SQLITE_OK && fout&SQLITE_OPEN_READONLY ){
+            rc = SQLITE_CANTOPEN_BKPT;
+            sqlite3OsClose(pPager->jfd);

           }
         }
       }
           }
         }
       }

-      if( rc!=SQLITE_OK ){
-        goto failed;
-      }
-
-      /* Reset the journal status fields to indicates that we have no
-      ** rollback journal at this time. */
-      pPager->journalStarted = 0;
-      pPager->journalOff = 0;
-      pPager->setMaster = 0;
-      pPager->journalHdr = 0;
- 
-      /* Make sure the journal file has been synced to disk. */

  
       /* Playback and delete the journal.  Drop the database write
       ** lock and reacquire the read lock. Purge the cache before
  
       /* Playback and delete the journal.  Drop the database write
       ** lock and reacquire the read lock. Purge the cache before


@@ -38050,21 +38848,46 @@ SQLITE_PRIVATE int sqlite3PagerSharedLock(Pager *pPager){
       ** the journal before playing it back.
       */
       if( isOpen(pPager->jfd) ){
       ** the journal before playing it back.
       */
       if( isOpen(pPager->jfd) ){

+        assert( rc==SQLITE_OK );

         rc = pagerSyncHotJournal(pPager);
         if( rc==SQLITE_OK ){
           rc = pager_playback(pPager, 1);
         rc = pagerSyncHotJournal(pPager);
         if( rc==SQLITE_OK ){
           rc = pager_playback(pPager, 1);

+          pPager->eState = PAGER_OPEN;

         }
         }

-        if( rc!=SQLITE_OK ){
-          rc = pager_error(pPager, rc);
-          goto failed;
-        }
+      }else if( !pPager->exclusiveMode ){
+        pagerUnlockDb(pPager, SHARED_LOCK);
+      }
+
+      if( rc!=SQLITE_OK ){
+        /* This branch is taken if an error occurs while trying to open
+        ** or roll back a hot-journal while holding an EXCLUSIVE lock. The
+        ** pager_unlock() routine will be called before returning to unlock
+        ** the file. If the unlock attempt fails, then Pager.eLock must be
+        ** set to UNKNOWN_LOCK (see the comment above the #define for 
+        ** UNKNOWN_LOCK above for an explanation). 
+        **
+        ** In order to get pager_unlock() to do this, set Pager.eState to
+        ** PAGER_ERROR now. This is not actually counted as a transition
+        ** to ERROR state in the state diagram at the top of this file,
+        ** since we know that the same call to pager_unlock() will very
+        ** shortly transition the pager object to the OPEN state. Calling
+        ** assert_pager_state() would fail now, as it should not be possible
+        ** to be in ERROR state when there are zero outstanding page 
+        ** references.
+        */
+        pager_error(pPager, rc);
+        goto failed;

       }
       }

-      assert( (pPager->state==PAGER_SHARED)
-           || (pPager->exclusiveMode && pPager->state>PAGER_SHARED)
+
+      assert( pPager->eState==PAGER_OPEN );
+      assert( (pPager->eLock==SHARED_LOCK)
+           || (pPager->exclusiveMode && pPager->eLock>SHARED_LOCK)

       );
     }
 
       );
     }
 

-    if( pPager->pBackup || sqlite3PcachePagecount(pPager->pPCache)>0 ){
+    if( !pPager->tempFile 
+     && (pPager->pBackup || sqlite3PcachePagecount(pPager->pPCache)>0) 
+    ){

       /* The shared-lock has just been acquired on the database file
       ** and there are already pages in the cache (from a previous
       ** read or write transaction).  Check to see if the database
       /* The shared-lock has just been acquired on the database file
       ** and there are already pages in the cache (from a previous
       ** read or write transaction).  Check to see if the database


@@ -38081,14 +38904,11 @@ SQLITE_PRIVATE int sqlite3PagerSharedLock(Pager *pPager){
       ** detected.  The chance of an undetected change is so small that
       ** it can be neglected.
       */
       ** detected.  The chance of an undetected change is so small that
       ** it can be neglected.
       */

-      int nPage = 0;
+      Pgno nPage = 0;

       char dbFileVers[sizeof(pPager->dbFileVers)];
       char dbFileVers[sizeof(pPager->dbFileVers)];

-      sqlite3PagerPagecount(pPager, &nPage);

 
 

-      if( pPager->errCode ){
-        rc = pPager->errCode;
-        goto failed;
-      }
+      rc = pagerPagecount(pPager, &nPage);
+      if( rc ) goto failed;

 
       if( nPage>0 ){
         IOTRACE(("CKVERS %p %d\n", pPager, sizeof(dbFileVers)));
 
       if( nPage>0 ){
         IOTRACE(("CKVERS %p %d\n", pPager, sizeof(dbFileVers)));


@@ -38104,18 +38924,30 @@ SQLITE_PRIVATE int sqlite3PagerSharedLock(Pager *pPager){
         pager_reset(pPager);
       }
     }
         pager_reset(pPager);
       }
     }

-    assert( pPager->exclusiveMode || pPager->state==PAGER_SHARED );

 
     /* If there is a WAL file in the file-system, open this database in WAL
     ** mode. Otherwise, the following function call is a no-op.
     */
     rc = pagerOpenWalIfPresent(pPager);
 
     /* If there is a WAL file in the file-system, open this database in WAL
     ** mode. Otherwise, the following function call is a no-op.
     */
     rc = pagerOpenWalIfPresent(pPager);

+    assert( pPager->pWal==0 || rc==SQLITE_OK );
+  }
+
+  if( pagerUseWal(pPager) ){
+    assert( rc==SQLITE_OK );
+    rc = pagerBeginReadTransaction(pPager);
+  }
+
+  if( pPager->eState==PAGER_OPEN && rc==SQLITE_OK ){
+    rc = pagerPagecount(pPager, &pPager->dbSize);

   }
 
  failed:
   if( rc!=SQLITE_OK ){
   }
 
  failed:
   if( rc!=SQLITE_OK ){

-    /* pager_unlock() is a no-op for exclusive mode and in-memory databases. */
+    assert( !MEMDB );

     pager_unlock(pPager);
     pager_unlock(pPager);

+    assert( pPager->eState==PAGER_OPEN );
+  }else{
+    pPager->eState = PAGER_READER;

   }
   return rc;
 }
   }
   return rc;
 }


@@ -38129,9 +38961,7 @@ SQLITE_PRIVATE int sqlite3PagerSharedLock(Pager *pPager){
 ** nothing to rollback, so this routine is a no-op.
 */ 
 static void pagerUnlockIfUnused(Pager *pPager){
 ** nothing to rollback, so this routine is a no-op.
 */ 
 static void pagerUnlockIfUnused(Pager *pPager){

-  if( (sqlite3PcacheRefCount(pPager->pPCache)==0)
-   && (!pPager->exclusiveMode || pPager->journalOff>0) 
-  ){
+  if( (sqlite3PcacheRefCount(pPager->pPCache)==0) ){

     pagerUnlockAndRollback(pPager);
   }
 }
     pagerUnlockAndRollback(pPager);
   }
 }


@@ -38195,8 +39025,8 @@ SQLITE_PRIVATE int sqlite3PagerAcquire(
   int rc;
   PgHdr *pPg;
 
   int rc;
   PgHdr *pPg;
 

+  assert( pPager->eState>=PAGER_READER );

   assert( assert_pager_state(pPager) );
   assert( assert_pager_state(pPager) );

-  assert( pPager->state>PAGER_UNLOCK );

 
   if( pgno==0 ){
     return SQLITE_CORRUPT_BKPT;
 
   if( pgno==0 ){
     return SQLITE_CORRUPT_BKPT;


@@ -38204,7 +39034,7 @@ SQLITE_PRIVATE int sqlite3PagerAcquire(
 
   /* If the pager is in the error state, return an error immediately. 
   ** Otherwise, request the page from the PCache layer. */
 
   /* If the pager is in the error state, return an error immediately. 
   ** Otherwise, request the page from the PCache layer. */

-  if( pPager->errCode!=SQLITE_OK && pPager->errCode!=SQLITE_FULL ){
+  if( pPager->errCode!=SQLITE_OK ){

     rc = pPager->errCode;
   }else{
     rc = sqlite3PcacheFetch(pPager->pPCache, pgno, 1, ppPage);
     rc = pPager->errCode;
   }else{
     rc = sqlite3PcacheFetch(pPager->pPCache, pgno, 1, ppPage);


@@ -38230,7 +39060,6 @@ SQLITE_PRIVATE int sqlite3PagerAcquire(
   }else{
     /* The pager cache has created a new page. Its content needs to 
     ** be initialized.  */
   }else{
     /* The pager cache has created a new page. Its content needs to 
     ** be initialized.  */

-    int nMax;

 
     PAGER_INCR(pPager->nMiss);
     pPg = *ppPage;
 
     PAGER_INCR(pPager->nMiss);
     pPg = *ppPage;


@@ -38243,12 +39072,7 @@ SQLITE_PRIVATE int sqlite3PagerAcquire(
       goto pager_acquire_err;
     }
 
       goto pager_acquire_err;
     }
 

-    rc = sqlite3PagerPagecount(pPager, &nMax);
-    if( rc!=SQLITE_OK ){
-      goto pager_acquire_err;
-    }
-
-    if( MEMDB || nMax<(int)pgno || noContent || !isOpen(pPager->fd) ){
+    if( MEMDB || pPager->dbSize<pgno || noContent || !isOpen(pPager->fd) ){

       if( pgno>pPager->mxPgno ){
         rc = SQLITE_FULL;
         goto pager_acquire_err;
       if( pgno>pPager->mxPgno ){
         rc = SQLITE_FULL;
         goto pager_acquire_err;


@@ -38278,9 +39102,7 @@ SQLITE_PRIVATE int sqlite3PagerAcquire(
         goto pager_acquire_err;
       }
     }
         goto pager_acquire_err;
       }
     }

-#ifdef SQLITE_CHECK_PAGES
-    pPg->pageHash = pager_pagehash(pPg);
-#endif
+    pager_set_pagehash(pPg);

   }
 
   return SQLITE_OK;
   }
 
   return SQLITE_OK;


@@ -38299,9 +39121,7 @@ pager_acquire_err:
 /*
 ** Acquire a page if it is already in the in-memory cache.  Do
 ** not read the page from disk.  Return a pointer to the page,
 /*
 ** Acquire a page if it is already in the in-memory cache.  Do
 ** not read the page from disk.  Return a pointer to the page,

-** or 0 if the page is not in cache. Also, return 0 if the 
-** pager is in PAGER_UNLOCK state when this function is called,
-** or if the pager is in an error state other than SQLITE_FULL.
+** or 0 if the page is not in cache. 

 **
 ** See also sqlite3PagerGet().  The difference between this routine
 ** and sqlite3PagerGet() is that _get() will go to the disk and read
 **
 ** See also sqlite3PagerGet().  The difference between this routine
 ** and sqlite3PagerGet() is that _get() will go to the disk and read


@@ -38314,7 +39134,7 @@ SQLITE_PRIVATE DbPage *sqlite3PagerLookup(Pager *pPager, Pgno pgno){
   assert( pPager!=0 );
   assert( pgno!=0 );
   assert( pPager->pPCache!=0 );
   assert( pPager!=0 );
   assert( pgno!=0 );
   assert( pPager->pPCache!=0 );

-  assert( pPager->state > PAGER_UNLOCK );
+  assert( pPager->eState>=PAGER_READER && pPager->eState!=PAGER_ERROR );

   sqlite3PcacheFetch(pPager->pPCache, pgno, 0, &pPg);
   return pPg;
 }
   sqlite3PcacheFetch(pPager->pPCache, pgno, 0, &pPg);
   return pPg;
 }


@@ -38359,12 +39179,10 @@ SQLITE_PRIVATE void sqlite3PagerUnref(DbPage *pPg){
 */
 static int pager_open_journal(Pager *pPager){
   int rc = SQLITE_OK;                        /* Return code */
 */
 static int pager_open_journal(Pager *pPager){
   int rc = SQLITE_OK;                        /* Return code */

-  int nPage;                                 /* Size of database file */

   sqlite3_vfs * const pVfs = pPager->pVfs;   /* Local cache of vfs pointer */
 
   sqlite3_vfs * const pVfs = pPager->pVfs;   /* Local cache of vfs pointer */
 

-  assert( pPager->state>=PAGER_RESERVED );
-  assert( pPager->useJournal );
-  assert( pPager->journalMode!=PAGER_JOURNALMODE_OFF );
+  assert( pPager->eState==PAGER_WRITER_LOCKED );
+  assert( assert_pager_state(pPager) );

   assert( pPager->pInJournal==0 );
   
   /* If already in the error state, this function is a no-op.  But on
   assert( pPager->pInJournal==0 );
   
   /* If already in the error state, this function is a no-op.  But on


@@ -38372,56 +39190,56 @@ static int pager_open_journal(Pager *pPager){
   ** an error state. */
   if( NEVER(pPager->errCode) ) return pPager->errCode;
 
   ** an error state. */
   if( NEVER(pPager->errCode) ) return pPager->errCode;
 

-  testcase( pPager->dbSizeValid==0 );
-  rc = sqlite3PagerPagecount(pPager, &nPage);
-  if( rc ) return rc;
-  pPager->pInJournal = sqlite3BitvecCreate(nPage);
-  if( pPager->pInJournal==0 ){
-    return SQLITE_NOMEM;
-  }
-
-  /* Open the journal file if it is not already open. */
-  if( !isOpen(pPager->jfd) ){
-    if( pPager->journalMode==PAGER_JOURNALMODE_MEMORY ){
-      sqlite3MemJournalOpen(pPager->jfd);
-    }else{
-      const int flags =                   /* VFS flags to open journal file */
-        SQLITE_OPEN_READWRITE|SQLITE_OPEN_CREATE|
-        (pPager->tempFile ? 
-          (SQLITE_OPEN_DELETEONCLOSE|SQLITE_OPEN_TEMP_JOURNAL):
-          (SQLITE_OPEN_MAIN_JOURNAL)
+  if( !pagerUseWal(pPager) && pPager->journalMode!=PAGER_JOURNALMODE_OFF ){
+    pPager->pInJournal = sqlite3BitvecCreate(pPager->dbSize);
+    if( pPager->pInJournal==0 ){
+      return SQLITE_NOMEM;
+    }
+  
+    /* Open the journal file if it is not already open. */
+    if( !isOpen(pPager->jfd) ){
+      if( pPager->journalMode==PAGER_JOURNALMODE_MEMORY ){
+        sqlite3MemJournalOpen(pPager->jfd);
+      }else{
+        const int flags =                   /* VFS flags to open journal file */
+          SQLITE_OPEN_READWRITE|SQLITE_OPEN_CREATE|
+          (pPager->tempFile ? 
+            (SQLITE_OPEN_DELETEONCLOSE|SQLITE_OPEN_TEMP_JOURNAL):
+            (SQLITE_OPEN_MAIN_JOURNAL)
+          );
+  #ifdef SQLITE_ENABLE_ATOMIC_WRITE
+        rc = sqlite3JournalOpen(
+            pVfs, pPager->zJournal, pPager->jfd, flags, jrnlBufferSize(pPager)

         );
         );

-#ifdef SQLITE_ENABLE_ATOMIC_WRITE
-      rc = sqlite3JournalOpen(
-          pVfs, pPager->zJournal, pPager->jfd, flags, jrnlBufferSize(pPager)
-      );
-#else
-      rc = sqlite3OsOpen(pVfs, pPager->zJournal, pPager->jfd, flags, 0);
-#endif
+  #else
+        rc = sqlite3OsOpen(pVfs, pPager->zJournal, pPager->jfd, flags, 0);
+  #endif
+      }
+      assert( rc!=SQLITE_OK || isOpen(pPager->jfd) );
+    }
+  
+  
+    /* Write the first journal header to the journal file and open 
+    ** the sub-journal if necessary.
+    */
+    if( rc==SQLITE_OK ){
+      /* TODO: Check if all of these are really required. */
+      pPager->nRec = 0;
+      pPager->journalOff = 0;
+      pPager->setMaster = 0;
+      pPager->journalHdr = 0;
+      rc = writeJournalHdr(pPager);

     }
     }

-    assert( rc!=SQLITE_OK || isOpen(pPager->jfd) );
-  }
-
-
-  /* Write the first journal header to the journal file and open 
-  ** the sub-journal if necessary.
-  */
-  if( rc==SQLITE_OK ){
-    /* TODO: Check if all of these are really required. */
-    pPager->dbOrigSize = pPager->dbSize;
-    pPager->journalStarted = 0;
-    pPager->needSync = 0;
-    pPager->nRec = 0;
-    pPager->journalOff = 0;
-    pPager->setMaster = 0;
-    pPager->journalHdr = 0;
-    rc = writeJournalHdr(pPager);

   }
 
   if( rc!=SQLITE_OK ){
     sqlite3BitvecDestroy(pPager->pInJournal);
     pPager->pInJournal = 0;
   }
 
   if( rc!=SQLITE_OK ){
     sqlite3BitvecDestroy(pPager->pInJournal);
     pPager->pInJournal = 0;

+  }else{
+    assert( pPager->eState==PAGER_WRITER_LOCKED );
+    pPager->eState = PAGER_WRITER_CACHEMOD;

   }
   }

+

   return rc;
 }
 
   return rc;
 }
 


@@ -38434,14 +39252,6 @@ static int pager_open_journal(Pager *pPager){
 ** an EXCLUSIVE lock. If such a lock is already held, no locking 
 ** functions need be called.
 **
 ** an EXCLUSIVE lock. If such a lock is already held, no locking 
 ** functions need be called.
 **

-** If this is not a temporary or in-memory file and, the journal file is 
-** opened if it has not been already. For a temporary file, the opening 
-** of the journal file is deferred until there is an actual need to 
-** write to the journal. TODO: Why handle temporary files differently?
-**
-** If the journal file is opened (or if it is already open), then a
-** journal-header is written to the start of it.
-**

 ** If the subjInMemory argument is non-zero, then any sub-journal opened
 ** within this transaction will be opened as an in-memory file. This
 ** has no effect if the sub-journal is already opened (as it may be when
 ** If the subjInMemory argument is non-zero, then any sub-journal opened
 ** within this transaction will be opened as an in-memory file. This
 ** has no effect if the sub-journal is already opened (as it may be when


@@ -38452,20 +39262,20 @@ static int pager_open_journal(Pager *pPager){
 */
 SQLITE_PRIVATE int sqlite3PagerBegin(Pager *pPager, int exFlag, int subjInMemory){
   int rc = SQLITE_OK;
 */
 SQLITE_PRIVATE int sqlite3PagerBegin(Pager *pPager, int exFlag, int subjInMemory){
   int rc = SQLITE_OK;

-  assert( pPager->state!=PAGER_UNLOCK );
+
+  if( pPager->errCode ) return pPager->errCode;
+  assert( pPager->eState>=PAGER_READER && pPager->eState<PAGER_ERROR );

   pPager->subjInMemory = (u8)subjInMemory;
 
   pPager->subjInMemory = (u8)subjInMemory;
 

-  if( pPager->state==PAGER_SHARED ){
+  if( ALWAYS(pPager->eState==PAGER_READER) ){

     assert( pPager->pInJournal==0 );
     assert( pPager->pInJournal==0 );

-    assert( !MEMDB && !pPager->tempFile );

 
     if( pagerUseWal(pPager) ){
       /* If the pager is configured to use locking_mode=exclusive, and an
       ** exclusive lock on the database is not already held, obtain it now.
       */
       if( pPager->exclusiveMode && sqlite3WalExclusiveMode(pPager->pWal, -1) ){
 
     if( pagerUseWal(pPager) ){
       /* If the pager is configured to use locking_mode=exclusive, and an
       ** exclusive lock on the database is not already held, obtain it now.
       */
       if( pPager->exclusiveMode && sqlite3WalExclusiveMode(pPager->pWal, -1) ){

-        rc = sqlite3OsLock(pPager->fd, EXCLUSIVE_LOCK);
-        pPager->state = PAGER_SHARED;
+        rc = pagerLockDb(pPager, EXCLUSIVE_LOCK);

         if( rc!=SQLITE_OK ){
           return rc;
         }
         if( rc!=SQLITE_OK ){
           return rc;
         }


@@ -38476,52 +39286,40 @@ SQLITE_PRIVATE int sqlite3PagerBegin(Pager *pPager, int exFlag, int subjInMemory
       ** PAGER_RESERVED state. Otherwise, return an error code to the caller.
       ** The busy-handler is not invoked if another connection already
       ** holds the write-lock. If possible, the upper layer will call it.
       ** PAGER_RESERVED state. Otherwise, return an error code to the caller.
       ** The busy-handler is not invoked if another connection already
       ** holds the write-lock. If possible, the upper layer will call it.

-      **
-      ** WAL mode sets Pager.state to PAGER_RESERVED when it has an open
-      ** transaction, but never to PAGER_EXCLUSIVE. This is because in 
-      ** PAGER_EXCLUSIVE state the code to roll back savepoint transactions
-      ** may copy data from the sub-journal into the database file as well
-      ** as into the page cache. Which would be incorrect in WAL mode.

       */
       rc = sqlite3WalBeginWriteTransaction(pPager->pWal);
       */
       rc = sqlite3WalBeginWriteTransaction(pPager->pWal);

-      if( rc==SQLITE_OK ){
-        pPager->dbOrigSize = pPager->dbSize;
-        pPager->state = PAGER_RESERVED;
-        pPager->journalOff = 0;
-      }
-
-      assert( rc!=SQLITE_OK || pPager->state==PAGER_RESERVED );
-      assert( rc==SQLITE_OK || pPager->state==PAGER_SHARED );

     }else{
       /* Obtain a RESERVED lock on the database file. If the exFlag parameter
       ** is true, then immediately upgrade this to an EXCLUSIVE lock. The
       ** busy-handler callback can be used when upgrading to the EXCLUSIVE
       ** lock, but not when obtaining the RESERVED lock.
       */
     }else{
       /* Obtain a RESERVED lock on the database file. If the exFlag parameter
       ** is true, then immediately upgrade this to an EXCLUSIVE lock. The
       ** busy-handler callback can be used when upgrading to the EXCLUSIVE
       ** lock, but not when obtaining the RESERVED lock.
       */

-      rc = sqlite3OsLock(pPager->fd, RESERVED_LOCK);
-      if( rc==SQLITE_OK ){
-        pPager->state = PAGER_RESERVED;
-        if( exFlag ){
-          rc = pager_wait_on_lock(pPager, EXCLUSIVE_LOCK);
-        }
+      rc = pagerLockDb(pPager, RESERVED_LOCK);
+      if( rc==SQLITE_OK && exFlag ){
+        rc = pager_wait_on_lock(pPager, EXCLUSIVE_LOCK);

       }
     }
 
       }
     }
 

-    /* No need to open the journal file at this time.  It will be
-    ** opened before it is written to.  If we defer opening the journal,
-    ** we might save the work of creating a file if the transaction
-    ** ends up being a no-op.
-    */
-
-    if( rc!=SQLITE_OK ){
-      assert( !pPager->dbModified );
-      /* Ignore any IO error that occurs within pager_end_transaction(). The
-      ** purpose of this call is to reset the internal state of the pager
-      ** sub-system. It doesn't matter if the journal-file is not properly
-      ** finalized at this point (since it is not a valid journal file anyway).
+    if( rc==SQLITE_OK ){
+      /* Change to WRITER_LOCKED state.
+      **
+      ** WAL mode sets Pager.eState to PAGER_WRITER_LOCKED or CACHEMOD
+      ** when it has an open transaction, but never to DBMOD or FINISHED.
+      ** This is because in those states the code to roll back savepoint 
+      ** transactions may copy data from the sub-journal into the database 
+      ** file as well as into the page cache. Which would be incorrect in 
+      ** WAL mode.

       */
       */

-      pager_end_transaction(pPager, 0);
+      pPager->eState = PAGER_WRITER_LOCKED;
+      pPager->dbHintSize = pPager->dbSize;
+      pPager->dbFileSize = pPager->dbSize;
+      pPager->dbOrigSize = pPager->dbSize;
+      pPager->journalOff = 0;

     }
     }

+
+    assert( rc==SQLITE_OK || pPager->eState==PAGER_READER );
+    assert( rc!=SQLITE_OK || pPager->eState==PAGER_WRITER_LOCKED );
+    assert( assert_pager_state(pPager) );

   }
 
   PAGERTRACE(("TRANSACTION %d\n", PAGERID(pPager)));
   }
 
   PAGERTRACE(("TRANSACTION %d\n", PAGERID(pPager)));


@@ -38540,22 +39338,24 @@ static int pager_write(PgHdr *pPg){
   Pager *pPager = pPg->pPager;
   int rc = SQLITE_OK;
 
   Pager *pPager = pPg->pPager;
   int rc = SQLITE_OK;
 

-  /* This routine is not called unless a transaction has already been
-  ** started.
+  /* This routine is not called unless a write-transaction has already 
+  ** been started. The journal file may or may not be open at this point.
+  ** It is never called in the ERROR state.

   */
   */

-  assert( pPager->state>=PAGER_RESERVED );
+  assert( pPager->eState==PAGER_WRITER_LOCKED
+       || pPager->eState==PAGER_WRITER_CACHEMOD
+       || pPager->eState==PAGER_WRITER_DBMOD
+  );
+  assert( assert_pager_state(pPager) );

 
   /* If an error has been previously detected, report the same error
 
   /* If an error has been previously detected, report the same error

-  ** again.
-  */
+  ** again. This should not happen, but the check provides robustness. */

   if( NEVER(pPager->errCode) )  return pPager->errCode;
 
   /* Higher-level routines never call this function if database is not
   ** writable.  But check anyway, just for robustness. */
   if( NEVER(pPager->readOnly) ) return SQLITE_PERM;
 
   if( NEVER(pPager->errCode) )  return pPager->errCode;
 
   /* Higher-level routines never call this function if database is not
   ** writable.  But check anyway, just for robustness. */
   if( NEVER(pPager->readOnly) ) return SQLITE_PERM;
 

-  assert( !pPager->setMaster );
-

   CHECK_PAGE(pPg);
 
   /* Mark the page as dirty.  If the page has already been written
   CHECK_PAGE(pPg);
 
   /* Mark the page as dirty.  If the page has already been written


@@ -38564,82 +39364,68 @@ static int pager_write(PgHdr *pPg){
   sqlite3PcacheMakeDirty(pPg);
   if( pageInJournal(pPg) && !subjRequiresPage(pPg) ){
     assert( !pagerUseWal(pPager) );
   sqlite3PcacheMakeDirty(pPg);
   if( pageInJournal(pPg) && !subjRequiresPage(pPg) ){
     assert( !pagerUseWal(pPager) );

-    pPager->dbModified = 1;
+    assert( pPager->eState>=PAGER_WRITER_CACHEMOD );

   }else{
 
     /* If we get this far, it means that the page needs to be
   }else{
 
     /* If we get this far, it means that the page needs to be

-    ** written to the transaction journal or the ckeckpoint journal
+    ** written to the transaction journal or the checkpoint journal

     ** or both.
     **
     ** or both.
     **

-    ** Higher level routines should have already started a transaction,
-    ** which means they have acquired the necessary locks but the rollback
-    ** journal might not yet be open.
+    ** Higher level routines have already obtained the necessary locks
+    ** to begin the write-transaction, but the rollback journal might not 
+    ** yet be open. Open it now if this is the case.

     */
     */

-    assert( pPager->state>=RESERVED_LOCK );
-    if( pPager->pInJournal==0
-     && pPager->journalMode!=PAGER_JOURNALMODE_OFF 
-     && !pagerUseWal(pPager)
-    ){
-      assert( pPager->useJournal );
+    if( pPager->eState==PAGER_WRITER_LOCKED ){

       rc = pager_open_journal(pPager);
       if( rc!=SQLITE_OK ) return rc;
     }
       rc = pager_open_journal(pPager);
       if( rc!=SQLITE_OK ) return rc;
     }

-    pPager->dbModified = 1;
+    assert( pPager->eState>=PAGER_WRITER_CACHEMOD );
+    assert( assert_pager_state(pPager) );

   
     /* The transaction journal now exists and we have a RESERVED or an
     ** EXCLUSIVE lock on the main database file.  Write the current page to
     ** the transaction journal if it is not there already.
     */
   
     /* The transaction journal now exists and we have a RESERVED or an
     ** EXCLUSIVE lock on the main database file.  Write the current page to
     ** the transaction journal if it is not there already.
     */

-    if( !pageInJournal(pPg) && isOpen(pPager->jfd) ){
-      assert( !pagerUseWal(pPager) );
-      if( pPg->pgno<=pPager->dbOrigSize ){
+    if( !pageInJournal(pPg) && !pagerUseWal(pPager) ){
+      assert( pagerUseWal(pPager)==0 );
+      if( pPg->pgno<=pPager->dbOrigSize && isOpen(pPager->jfd) ){

         u32 cksum;
         char *pData2;
         u32 cksum;
         char *pData2;

+        i64 iOff = pPager->journalOff;

 
         /* We should never write to the journal file the page that
         ** contains the database locks.  The following assert verifies
         ** that we do not. */
         assert( pPg->pgno!=PAGER_MJ_PGNO(pPager) );
 
 
         /* We should never write to the journal file the page that
         ** contains the database locks.  The following assert verifies
         ** that we do not. */
         assert( pPg->pgno!=PAGER_MJ_PGNO(pPager) );
 

-        assert( pPager->journalHdr <= pPager->journalOff );
+        assert( pPager->journalHdr<=pPager->journalOff );

         CODEC2(pPager, pData, pPg->pgno, 7, return SQLITE_NOMEM, pData2);
         cksum = pager_cksum(pPager, (u8*)pData2);
         CODEC2(pPager, pData, pPg->pgno, 7, return SQLITE_NOMEM, pData2);
         cksum = pager_cksum(pPager, (u8*)pData2);

-        rc = write32bits(pPager->jfd, pPager->journalOff, pPg->pgno);
-        if( rc==SQLITE_OK ){
-          rc = sqlite3OsWrite(pPager->jfd, pData2, pPager->pageSize,
-                              pPager->journalOff + 4);
-          pPager->journalOff += pPager->pageSize+4;
-        }
-        if( rc==SQLITE_OK ){
-          rc = write32bits(pPager->jfd, pPager->journalOff, cksum);
-          pPager->journalOff += 4;
-        }
-        IOTRACE(("JOUT %p %d %lld %d\n", pPager, pPg->pgno, 
-                 pPager->journalOff, pPager->pageSize));
-        PAGER_INCR(sqlite3_pager_writej_count);
-        PAGERTRACE(("JOURNAL %d page %d needSync=%d hash(%08x)\n",
-             PAGERID(pPager), pPg->pgno, 
-             ((pPg->flags&PGHDR_NEED_SYNC)?1:0), pager_pagehash(pPg)));

 
 

-        /* Even if an IO or diskfull error occurred while journalling the
+        /* Even if an IO or diskfull error occurs while journalling the

         ** page in the block above, set the need-sync flag for the page.
         ** Otherwise, when the transaction is rolled back, the logic in
         ** playback_one_page() will think that the page needs to be restored
         ** in the database file. And if an IO error occurs while doing so,
         ** then corruption may follow.
         */
         ** page in the block above, set the need-sync flag for the page.
         ** Otherwise, when the transaction is rolled back, the logic in
         ** playback_one_page() will think that the page needs to be restored
         ** in the database file. And if an IO error occurs while doing so,
         ** then corruption may follow.
         */

-        if( !pPager->noSync ){
-          pPg->flags |= PGHDR_NEED_SYNC;
-          pPager->needSync = 1;
-        }
+        pPg->flags |= PGHDR_NEED_SYNC;

 
 

-        /* An error has occurred writing to the journal file. The 
-        ** transaction will be rolled back by the layer above.
-        */
-        if( rc!=SQLITE_OK ){
-          return rc;
-        }
+        rc = write32bits(pPager->jfd, iOff, pPg->pgno);
+        if( rc!=SQLITE_OK ) return rc;
+        rc = sqlite3OsWrite(pPager->jfd, pData2, pPager->pageSize, iOff+4);
+        if( rc!=SQLITE_OK ) return rc;
+        rc = write32bits(pPager->jfd, iOff+pPager->pageSize+4, cksum);
+        if( rc!=SQLITE_OK ) return rc;

 
 

+        IOTRACE(("JOUT %p %d %lld %d\n", pPager, pPg->pgno, 
+                 pPager->journalOff, pPager->pageSize));
+        PAGER_INCR(sqlite3_pager_writej_count);
+        PAGERTRACE(("JOURNAL %d page %d needSync=%d hash(%08x)\n",
+             PAGERID(pPager), pPg->pgno, 
+             ((pPg->flags&PGHDR_NEED_SYNC)?1:0), pager_pagehash(pPg)));
+
+        pPager->journalOff += 8 + pPager->pageSize;

         pPager->nRec++;
         assert( pPager->pInJournal!=0 );
         rc = sqlite3BitvecSet(pPager->pInJournal, pPg->pgno);
         pPager->nRec++;
         assert( pPager->pInJournal!=0 );
         rc = sqlite3BitvecSet(pPager->pInJournal, pPg->pgno);


@@ -38651,9 +39437,8 @@ static int pager_write(PgHdr *pPg){
           return rc;
         }
       }else{
           return rc;
         }
       }else{

-        if( !pPager->journalStarted && !pPager->noSync ){
+        if( pPager->eState!=PAGER_WRITER_DBMOD ){

           pPg->flags |= PGHDR_NEED_SYNC;
           pPg->flags |= PGHDR_NEED_SYNC;

-          pPager->needSync = 1;

         }
         PAGERTRACE(("APPEND %d page %d needSync=%d\n",
                 PAGERID(pPager), pPg->pgno,
         }
         PAGERTRACE(("APPEND %d page %d needSync=%d\n",
                 PAGERID(pPager), pPg->pgno,


@@ -38673,7 +39458,6 @@ static int pager_write(PgHdr *pPg){
 
   /* Update the database size and return.
   */
 
   /* Update the database size and return.
   */

-  assert( pPager->state>=PAGER_SHARED );

   if( pPager->dbSize<pPg->pgno ){
     pPager->dbSize = pPg->pgno;
   }
   if( pPager->dbSize<pPg->pgno ){
     pPager->dbSize = pPg->pgno;
   }


@@ -38701,6 +39485,10 @@ SQLITE_PRIVATE int sqlite3PagerWrite(DbPage *pDbPage){
   Pager *pPager = pPg->pPager;
   Pgno nPagePerSector = (pPager->sectorSize/pPager->pageSize);
 
   Pager *pPager = pPg->pPager;
   Pgno nPagePerSector = (pPager->sectorSize/pPager->pageSize);
 

+  assert( pPager->eState>=PAGER_WRITER_LOCKED );
+  assert( pPager->eState!=PAGER_ERROR );
+  assert( assert_pager_state(pPager) );
+

   if( nPagePerSector>1 ){
     Pgno nPageCount;          /* Total number of pages in database file */
     Pgno pg1;                 /* First page of the sector pPg is located on. */
   if( nPagePerSector>1 ){
     Pgno nPageCount;          /* Total number of pages in database file */
     Pgno pg1;                 /* First page of the sector pPg is located on. */


@@ -38722,19 +39510,17 @@ SQLITE_PRIVATE int sqlite3PagerWrite(DbPage *pDbPage){
     */
     pg1 = ((pPg->pgno-1) & ~(nPagePerSector-1)) + 1;
 
     */
     pg1 = ((pPg->pgno-1) & ~(nPagePerSector-1)) + 1;
 

-    rc = sqlite3PagerPagecount(pPager, (int *)&nPageCount);
-    if( rc==SQLITE_OK ){
-      if( pPg->pgno>nPageCount ){
-        nPage = (pPg->pgno - pg1)+1;
-      }else if( (pg1+nPagePerSector-1)>nPageCount ){
-        nPage = nPageCount+1-pg1;
-      }else{
-        nPage = nPagePerSector;
-      }
-      assert(nPage>0);
-      assert(pg1<=pPg->pgno);
-      assert((pg1+nPage)>pPg->pgno);
+    nPageCount = pPager->dbSize;
+    if( pPg->pgno>nPageCount ){
+      nPage = (pPg->pgno - pg1)+1;
+    }else if( (pg1+nPagePerSector-1)>nPageCount ){
+      nPage = nPageCount+1-pg1;
+    }else{
+      nPage = nPagePerSector;

     }
     }

+    assert(nPage>0);
+    assert(pg1<=pPg->pgno);
+    assert((pg1+nPage)>pPg->pgno);

 
     for(ii=0; ii<nPage && rc==SQLITE_OK; ii++){
       Pgno pg = pg1+ii;
 
     for(ii=0; ii<nPage && rc==SQLITE_OK; ii++){
       Pgno pg = pg1+ii;


@@ -38746,7 +39532,6 @@ SQLITE_PRIVATE int sqlite3PagerWrite(DbPage *pDbPage){
             rc = pager_write(pPage);
             if( pPage->flags&PGHDR_NEED_SYNC ){
               needSync = 1;
             rc = pager_write(pPage);
             if( pPage->flags&PGHDR_NEED_SYNC ){
               needSync = 1;

-              assert(pPager->needSync);

             }
             sqlite3PagerUnref(pPage);
           }
             }
             sqlite3PagerUnref(pPage);
           }


@@ -38766,7 +39551,7 @@ SQLITE_PRIVATE int sqlite3PagerWrite(DbPage *pDbPage){
     ** before any of them can be written out to the database file.
     */
     if( rc==SQLITE_OK && needSync ){
     ** before any of them can be written out to the database file.
     */
     if( rc==SQLITE_OK && needSync ){

-      assert( !MEMDB && pPager->noSync==0 );
+      assert( !MEMDB );

       for(ii=0; ii<nPage; ii++){
         PgHdr *pPage = pager_lookup(pPager, pg1+ii);
         if( pPage ){
       for(ii=0; ii<nPage; ii++){
         PgHdr *pPage = pager_lookup(pPager, pg1+ii);
         if( pPage ){


@@ -38774,7 +39559,6 @@ SQLITE_PRIVATE int sqlite3PagerWrite(DbPage *pDbPage){
           sqlite3PagerUnref(pPage);
         }
       }
           sqlite3PagerUnref(pPage);
         }
       }

-      assert(pPager->needSync);

     }
 
     assert( pPager->doNotSyncSpill==1 );
     }
 
     assert( pPager->doNotSyncSpill==1 );


@@ -38816,9 +39600,7 @@ SQLITE_PRIVATE void sqlite3PagerDontWrite(PgHdr *pPg){
     PAGERTRACE(("DONT_WRITE page %d of %d\n", pPg->pgno, PAGERID(pPager)));
     IOTRACE(("CLEAN %p %d\n", pPager, pPg->pgno))
     pPg->flags |= PGHDR_DONT_WRITE;
     PAGERTRACE(("DONT_WRITE page %d of %d\n", pPg->pgno, PAGERID(pPager)));
     IOTRACE(("CLEAN %p %d\n", pPager, pPg->pgno))
     pPg->flags |= PGHDR_DONT_WRITE;

-#ifdef SQLITE_CHECK_PAGES
-    pPg->pageHash = pager_pagehash(pPg);
-#endif
+    pager_set_pagehash(pPg);

   }
 }
 
   }
 }
 


@@ -38841,6 +39623,11 @@ SQLITE_PRIVATE void sqlite3PagerDontWrite(PgHdr *pPg){
 static int pager_incr_changecounter(Pager *pPager, int isDirectMode){
   int rc = SQLITE_OK;
 
 static int pager_incr_changecounter(Pager *pPager, int isDirectMode){
   int rc = SQLITE_OK;
 

+  assert( pPager->eState==PAGER_WRITER_CACHEMOD
+       || pPager->eState==PAGER_WRITER_DBMOD
+  );
+  assert( assert_pager_state(pPager) );
+

   /* Declare and initialize constant integer 'isDirect'. If the
   ** atomic-write optimization is enabled in this build, then isDirect
   ** is initialized to the value passed as the isDirectMode parameter
   /* Declare and initialize constant integer 'isDirect'. If the
   ** atomic-write optimization is enabled in this build, then isDirect
   ** is initialized to the value passed as the isDirectMode parameter


@@ -38859,7 +39646,6 @@ static int pager_incr_changecounter(Pager *pPager, int isDirectMode){
 # define DIRECT_MODE isDirectMode
 #endif
 
 # define DIRECT_MODE isDirectMode
 #endif
 

-  assert( pPager->state>=PAGER_RESERVED );

   if( !pPager->changeCountDone && pPager->dbSize>0 ){
     PgHdr *pPgHdr;                /* Reference to page 1 */
     u32 change_counter;           /* Initial value of change-counter field */
   if( !pPager->changeCountDone && pPager->dbSize>0 ){
     PgHdr *pPgHdr;                /* Reference to page 1 */
     u32 change_counter;           /* Initial value of change-counter field */


@@ -38931,6 +39717,30 @@ SQLITE_PRIVATE int sqlite3PagerSync(Pager *pPager){
   return rc;
 }
 
   return rc;
 }
 

+/*
+** This function may only be called while a write-transaction is active in
+** rollback. If the connection is in WAL mode, this call is a no-op. 
+** Otherwise, if the connection does not already have an EXCLUSIVE lock on 
+** the database file, an attempt is made to obtain one.
+**
+** If the EXCLUSIVE lock is already held or the attempt to obtain it is
+** successful, or the connection is in WAL mode, SQLITE_OK is returned.
+** Otherwise, either SQLITE_BUSY or an SQLITE_IOERR_XXX error code is 
+** returned.
+*/
+SQLITE_PRIVATE int sqlite3PagerExclusiveLock(Pager *pPager){
+  int rc = SQLITE_OK;
+  assert( pPager->eState==PAGER_WRITER_CACHEMOD 
+       || pPager->eState==PAGER_WRITER_DBMOD 
+       || pPager->eState==PAGER_WRITER_LOCKED 
+  );
+  assert( assert_pager_state(pPager) );
+  if( 0==pagerUseWal(pPager) ){
+    rc = pager_wait_on_lock(pPager, EXCLUSIVE_LOCK);
+  }
+  return rc;
+}
+

 /*
 ** Sync the database file for the pager pPager. zMaster points to the name
 ** of a master journal file that should be written into the individual
 /*
 ** Sync the database file for the pager pPager. zMaster points to the name
 ** of a master journal file that should be written into the individual


@@ -38964,22 +39774,29 @@ SQLITE_PRIVATE int sqlite3PagerCommitPhaseOne(
 ){
   int rc = SQLITE_OK;             /* Return code */
 
 ){
   int rc = SQLITE_OK;             /* Return code */
 

-  /* The dbOrigSize is never set if journal_mode=OFF */
-  assert( pPager->journalMode!=PAGER_JOURNALMODE_OFF || pPager->dbOrigSize==0 );
+  assert( pPager->eState==PAGER_WRITER_LOCKED
+       || pPager->eState==PAGER_WRITER_CACHEMOD
+       || pPager->eState==PAGER_WRITER_DBMOD
+       || pPager->eState==PAGER_ERROR
+  );
+  assert( assert_pager_state(pPager) );

 
   /* If a prior error occurred, report that error again. */
 
   /* If a prior error occurred, report that error again. */

-  if( pPager->errCode ) return pPager->errCode;
+  if( NEVER(pPager->errCode) ) return pPager->errCode;

 
   PAGERTRACE(("DATABASE SYNC: File=%s zMaster=%s nSize=%d\n", 
       pPager->zFilename, zMaster, pPager->dbSize));
 
 
   PAGERTRACE(("DATABASE SYNC: File=%s zMaster=%s nSize=%d\n", 
       pPager->zFilename, zMaster, pPager->dbSize));
 

-  if( MEMDB && pPager->dbModified ){
+  /* If no database changes have been made, return early. */
+  if( pPager->eState<PAGER_WRITER_CACHEMOD ) return SQLITE_OK;
+
+  if( MEMDB ){

     /* If this is an in-memory db, or no pages have been written to, or this
     ** function has already been called, it is mostly a no-op.  However, any
     ** backup in progress needs to be restarted.
     */
     sqlite3BackupRestart(pPager->pBackup);
     /* If this is an in-memory db, or no pages have been written to, or this
     ** function has already been called, it is mostly a no-op.  However, any
     ** backup in progress needs to be restarted.
     */
     sqlite3BackupRestart(pPager->pBackup);

-  }else if( pPager->state!=PAGER_SYNCED && pPager->dbModified ){
+  }else{

     if( pagerUseWal(pPager) ){
       PgHdr *pList = sqlite3PcacheDirtyList(pPager->pPCache);
       if( pList ){
     if( pagerUseWal(pPager) ){
       PgHdr *pList = sqlite3PcacheDirtyList(pPager->pPCache);
       if( pList ){


@@ -39022,7 +39839,7 @@ SQLITE_PRIVATE int sqlite3PagerCommitPhaseOne(
       );
       if( !zMaster && isOpen(pPager->jfd) 
        && pPager->journalOff==jrnlBufferSize(pPager) 
       );
       if( !zMaster && isOpen(pPager->jfd) 
        && pPager->journalOff==jrnlBufferSize(pPager) 

-       && pPager->dbSize>=pPager->dbFileSize
+       && pPager->dbSize>=pPager->dbOrigSize

        && (0==(pPg = sqlite3PcacheDirtyList(pPager->pPCache)) || 0==pPg->pDirty)
       ){
         /* Update the db file change counter via the direct-write method. The 
        && (0==(pPg = sqlite3PcacheDirtyList(pPager->pPCache)) || 0==pPg->pDirty)
       ){
         /* Update the db file change counter via the direct-write method. The 


@@ -39052,13 +39869,10 @@ SQLITE_PRIVATE int sqlite3PagerCommitPhaseOne(
       ** that it took at the start of the transaction. Otherwise, the
       ** calls to sqlite3PagerGet() return zeroed pages instead of 
       ** reading data from the database file.
       ** that it took at the start of the transaction. Otherwise, the
       ** calls to sqlite3PagerGet() return zeroed pages instead of 
       ** reading data from the database file.

-      **
-      ** When journal_mode==OFF the dbOrigSize is always zero, so this
-      ** block never runs if journal_mode=OFF.

       */
   #ifndef SQLITE_OMIT_AUTOVACUUM
       if( pPager->dbSize<pPager->dbOrigSize 
       */
   #ifndef SQLITE_OMIT_AUTOVACUUM
       if( pPager->dbSize<pPager->dbOrigSize 

-       && ALWAYS(pPager->journalMode!=PAGER_JOURNALMODE_OFF)
+       && pPager->journalMode!=PAGER_JOURNALMODE_OFF

       ){
         Pgno i;                                   /* Iterator variable */
         const Pgno iSkip = PAGER_MJ_PGNO(pPager); /* Pending lock page */
       ){
         Pgno i;                                   /* Iterator variable */
         const Pgno iSkip = PAGER_MJ_PGNO(pPager); /* Pending lock page */


@@ -39085,14 +39899,20 @@ SQLITE_PRIVATE int sqlite3PagerCommitPhaseOne(
       rc = writeMasterJournal(pPager, zMaster);
       if( rc!=SQLITE_OK ) goto commit_phase_one_exit;
   
       rc = writeMasterJournal(pPager, zMaster);
       if( rc!=SQLITE_OK ) goto commit_phase_one_exit;
   

-      /* Sync the journal file. If the atomic-update optimization is being
-      ** used, this call will not create the journal file or perform any
-      ** real IO.
+      /* Sync the journal file and write all dirty pages to the database.
+      ** If the atomic-update optimization is being used, this sync will not 
+      ** create the journal file or perform any real IO.
+      **
+      ** Because the change-counter page was just modified, unless the
+      ** atomic-update optimization is used it is almost certain that the
+      ** journal requires a sync here. However, in locking_mode=exclusive
+      ** on a system under memory pressure it is just possible that this is 
+      ** not the case. In this case it is likely enough that the redundant
+      ** xSync() call will be changed to a no-op by the OS anyhow. 

       */
       */

-      rc = syncJournal(pPager);
+      rc = syncJournal(pPager, 0);

       if( rc!=SQLITE_OK ) goto commit_phase_one_exit;
   
       if( rc!=SQLITE_OK ) goto commit_phase_one_exit;
   

-      /* Write all dirty pages to the database file. */

       rc = pager_write_pagelist(pPager,sqlite3PcacheDirtyList(pPager->pPCache));
       if( rc!=SQLITE_OK ){
         assert( rc!=SQLITE_IOERR_BLOCKED );
       rc = pager_write_pagelist(pPager,sqlite3PcacheDirtyList(pPager->pPCache));
       if( rc!=SQLITE_OK ){
         assert( rc!=SQLITE_IOERR_BLOCKED );


@@ -39105,7 +39925,7 @@ SQLITE_PRIVATE int sqlite3PagerCommitPhaseOne(
       */
       if( pPager->dbSize!=pPager->dbFileSize ){
         Pgno nNew = pPager->dbSize - (pPager->dbSize==PAGER_MJ_PGNO(pPager));
       */
       if( pPager->dbSize!=pPager->dbFileSize ){
         Pgno nNew = pPager->dbSize - (pPager->dbSize==PAGER_MJ_PGNO(pPager));

-        assert( pPager->state>=PAGER_EXCLUSIVE );
+        assert( pPager->eState==PAGER_WRITER_DBMOD );

         rc = pager_truncate(pPager, nNew);
         if( rc!=SQLITE_OK ) goto commit_phase_one_exit;
       }
         rc = pager_truncate(pPager, nNew);
         if( rc!=SQLITE_OK ) goto commit_phase_one_exit;
       }


@@ -39116,11 +39936,12 @@ SQLITE_PRIVATE int sqlite3PagerCommitPhaseOne(
       }
       IOTRACE(("DBSYNC %p\n", pPager))
     }
       }
       IOTRACE(("DBSYNC %p\n", pPager))
     }

-
-    pPager->state = PAGER_SYNCED;

   }
 
 commit_phase_one_exit:
   }
 
 commit_phase_one_exit:

+  if( rc==SQLITE_OK && !pagerUseWal(pPager) ){
+    pPager->eState = PAGER_WRITER_FINISHED;
+  }

   return rc;
 }
 
   return rc;
 }
 


@@ -39148,12 +39969,11 @@ SQLITE_PRIVATE int sqlite3PagerCommitPhaseTwo(Pager *pPager){
   ** called, just return the same error code without doing anything. */
   if( NEVER(pPager->errCode) ) return pPager->errCode;
 
   ** called, just return the same error code without doing anything. */
   if( NEVER(pPager->errCode) ) return pPager->errCode;
 

-  /* This function should not be called if the pager is not in at least
-  ** PAGER_RESERVED state. **FIXME**: Make it so that this test always
-  ** fails - make it so that we never reach this point if we do not hold
-  ** all necessary locks.
-  */
-  if( NEVER(pPager->state<PAGER_RESERVED) ) return SQLITE_ERROR;
+  assert( pPager->eState==PAGER_WRITER_LOCKED
+       || pPager->eState==PAGER_WRITER_FINISHED
+       || (pagerUseWal(pPager) && pPager->eState==PAGER_WRITER_CACHEMOD)
+  );
+  assert( assert_pager_state(pPager) );

 
   /* An optimization. If the database was not actually modified during
   ** this transaction, the pager is running in exclusive-mode and is
 
   /* An optimization. If the database was not actually modified during
   ** this transaction, the pager is running in exclusive-mode and is


@@ -39166,102 +39986,76 @@ SQLITE_PRIVATE int sqlite3PagerCommitPhaseTwo(Pager *pPager){
   ** header. Since the pager is in exclusive mode, there is no need
   ** to drop any locks either.
   */
   ** header. Since the pager is in exclusive mode, there is no need
   ** to drop any locks either.
   */

-  if( pPager->dbModified==0 && pPager->exclusiveMode 
+  if( pPager->eState==PAGER_WRITER_LOCKED 
+   && pPager->exclusiveMode 

    && pPager->journalMode==PAGER_JOURNALMODE_PERSIST
   ){
     assert( pPager->journalOff==JOURNAL_HDR_SZ(pPager) || !pPager->journalOff );
    && pPager->journalMode==PAGER_JOURNALMODE_PERSIST
   ){
     assert( pPager->journalOff==JOURNAL_HDR_SZ(pPager) || !pPager->journalOff );

+    pPager->eState = PAGER_READER;

     return SQLITE_OK;
   }
 
   PAGERTRACE(("COMMIT %d\n", PAGERID(pPager)));
     return SQLITE_OK;
   }
 
   PAGERTRACE(("COMMIT %d\n", PAGERID(pPager)));

-  assert( pPager->state==PAGER_SYNCED || MEMDB || !pPager->dbModified );

   rc = pager_end_transaction(pPager, pPager->setMaster);
   return pager_error(pPager, rc);
 }
 
 /*
   rc = pager_end_transaction(pPager, pPager->setMaster);
   return pager_error(pPager, rc);
 }
 
 /*

-** Rollback all changes. The database falls back to PAGER_SHARED mode.
+** If a write transaction is open, then all changes made within the 
+** transaction are reverted and the current write-transaction is closed.
+** The pager falls back to PAGER_READER state if successful, or PAGER_ERROR
+** state if an error occurs.

 **
 **

-** This function performs two tasks:
+** If the pager is already in PAGER_ERROR state when this function is called,
+** it returns Pager.errCode immediately. No work is performed in this case.
+**
+** Otherwise, in rollback mode, this function performs two functions:

 **
 **   1) It rolls back the journal file, restoring all database file and 
 **      in-memory cache pages to the state they were in when the transaction
 **      was opened, and
 **
 **   1) It rolls back the journal file, restoring all database file and 
 **      in-memory cache pages to the state they were in when the transaction
 **      was opened, and

+**

 **   2) It finalizes the journal file, so that it is not used for hot
 **      rollback at any point in the future.
 **
 **   2) It finalizes the journal file, so that it is not used for hot
 **      rollback at any point in the future.
 **

-** subject to the following qualifications:
-**
-** * If the journal file is not yet open when this function is called,
-**   then only (2) is performed. In this case there is no journal file
-**   to roll back.
-**
-** * If in an error state other than SQLITE_FULL, then task (1) is 
-**   performed. If successful, task (2). Regardless of the outcome
-**   of either, the error state error code is returned to the caller
-**   (i.e. either SQLITE_IOERR or SQLITE_CORRUPT).
-**
-** * If the pager is in PAGER_RESERVED state, then attempt (1). Whether
-**   or not (1) is successful, also attempt (2). If successful, return
-**   SQLITE_OK. Otherwise, enter the error state and return the first 
-**   error code encountered. 
+** Finalization of the journal file (task 2) is only performed if the 
+** rollback is successful.

 **
 **

-**   In this case there is no chance that the database was written to. 
-**   So is safe to finalize the journal file even if the playback 
-**   (operation 1) failed. However the pager must enter the error state
-**   as the contents of the in-memory cache are now suspect.
-**
-** * Finally, if in PAGER_EXCLUSIVE state, then attempt (1). Only
-**   attempt (2) if (1) is successful. Return SQLITE_OK if successful,
-**   otherwise enter the error state and return the error code from the 
-**   failing operation.
-**
-**   In this case the database file may have been written to. So if the
-**   playback operation did not succeed it would not be safe to finalize
-**   the journal file. It needs to be left in the file-system so that
-**   some other process can use it to restore the database state (by
-**   hot-journal rollback).
+** In WAL mode, all cache-entries containing data modified within the
+** current transaction are either expelled from the cache or reverted to
+** their pre-transaction state by re-reading data from the database or
+** WAL files. The WAL transaction is then closed.

 */
 SQLITE_PRIVATE int sqlite3PagerRollback(Pager *pPager){
   int rc = SQLITE_OK;                  /* Return code */
   PAGERTRACE(("ROLLBACK %d\n", PAGERID(pPager)));
 */
 SQLITE_PRIVATE int sqlite3PagerRollback(Pager *pPager){
   int rc = SQLITE_OK;                  /* Return code */
   PAGERTRACE(("ROLLBACK %d\n", PAGERID(pPager)));

+
+  /* PagerRollback() is a no-op if called in READER or OPEN state. If
+  ** the pager is already in the ERROR state, the rollback is not 
+  ** attempted here. Instead, the error code is returned to the caller.
+  */
+  assert( assert_pager_state(pPager) );
+  if( pPager->eState==PAGER_ERROR ) return pPager->errCode;
+  if( pPager->eState<=PAGER_READER ) return SQLITE_OK;
+

   if( pagerUseWal(pPager) ){
     int rc2;
   if( pagerUseWal(pPager) ){
     int rc2;

-

     rc = sqlite3PagerSavepoint(pPager, SAVEPOINT_ROLLBACK, -1);
     rc2 = pager_end_transaction(pPager, pPager->setMaster);
     if( rc==SQLITE_OK ) rc = rc2;
     rc = sqlite3PagerSavepoint(pPager, SAVEPOINT_ROLLBACK, -1);
     rc2 = pager_end_transaction(pPager, pPager->setMaster);
     if( rc==SQLITE_OK ) rc = rc2;

-    rc = pager_error(pPager, rc);
-  }else if( !pPager->dbModified || !isOpen(pPager->jfd) ){
-    rc = pager_end_transaction(pPager, pPager->setMaster);
-  }else if( pPager->errCode && pPager->errCode!=SQLITE_FULL ){
-    if( pPager->state>=PAGER_EXCLUSIVE ){
-      pager_playback(pPager, 0);
-    }
-    rc = pPager->errCode;
+  }else if( !isOpen(pPager->jfd) || pPager->eState==PAGER_WRITER_LOCKED ){
+    rc = pager_end_transaction(pPager, 0);

   }else{
   }else{

-    if( pPager->state==PAGER_RESERVED ){
-      int rc2;
-      rc = pager_playback(pPager, 0);
-      rc2 = pager_end_transaction(pPager, pPager->setMaster);
-      if( rc==SQLITE_OK ){
-        rc = rc2;
-      }
-    }else{
-      rc = pager_playback(pPager, 0);
-    }
+    rc = pager_playback(pPager, 0);
+  }

 
 

-    if( !MEMDB ){
-      pPager->dbSizeValid = 0;
-    }
+  assert( pPager->eState==PAGER_READER || rc!=SQLITE_OK );
+  assert( rc==SQLITE_OK || rc==SQLITE_FULL || (rc&0xFF)==SQLITE_IOERR );

 
 

-    /* If an error occurs during a ROLLBACK, we can no longer trust the pager
-    ** cache. So call pager_error() on the way out to make any error 
-    ** persistent.
-    */
-    rc = pager_error(pPager, rc);
-  }
-  return rc;
+  /* If an error occurs during a ROLLBACK, we can no longer trust the pager
+  ** cache. So call pager_error() on the way out to make any error persistent.
+  */
+  return pager_error(pPager, rc);

 }
 
 /*
 }
 
 /*


@@ -39284,9 +40078,11 @@ SQLITE_PRIVATE int sqlite3PagerRefcount(Pager *pPager){
 ** used by the pager and its associated cache.
 */
 SQLITE_PRIVATE int sqlite3PagerMemUsed(Pager *pPager){
 ** used by the pager and its associated cache.
 */
 SQLITE_PRIVATE int sqlite3PagerMemUsed(Pager *pPager){

-  int perPageSize = pPager->pageSize + pPager->nExtra + 20;
+  int perPageSize = pPager->pageSize + pPager->nExtra + sizeof(PgHdr)
+                                     + 5*sizeof(void*);

   return perPageSize*sqlite3PcachePagecount(pPager->pPCache)
   return perPageSize*sqlite3PcachePagecount(pPager->pPCache)

-           + sqlite3MallocSize(pPager);
+           + sqlite3MallocSize(pPager)
+           + pPager->pageSize;

 }
 
 /*
 }
 
 /*


@@ -39305,8 +40101,8 @@ SQLITE_PRIVATE int *sqlite3PagerStats(Pager *pPager){
   a[0] = sqlite3PcacheRefCount(pPager->pPCache);
   a[1] = sqlite3PcachePagecount(pPager->pPCache);
   a[2] = sqlite3PcacheGetCachesize(pPager->pPCache);
   a[0] = sqlite3PcacheRefCount(pPager->pPCache);
   a[1] = sqlite3PcachePagecount(pPager->pPCache);
   a[2] = sqlite3PcacheGetCachesize(pPager->pPCache);

-  a[3] = pPager->dbSizeValid ? (int) pPager->dbSize : -1;
-  a[4] = pPager->state;
+  a[3] = pPager->eState==PAGER_OPEN ? -1 : (int) pPager->dbSize;
+  a[4] = pPager->eState;

   a[5] = pPager->errCode;
   a[6] = pPager->nHit;
   a[7] = pPager->nMiss;
   a[5] = pPager->errCode;
   a[6] = pPager->nHit;
   a[7] = pPager->nMiss;


@@ -39338,13 +40134,12 @@ SQLITE_PRIVATE int sqlite3PagerOpenSavepoint(Pager *pPager, int nSavepoint){
   int rc = SQLITE_OK;                       /* Return code */
   int nCurrent = pPager->nSavepoint;        /* Current number of savepoints */
 
   int rc = SQLITE_OK;                       /* Return code */
   int nCurrent = pPager->nSavepoint;        /* Current number of savepoints */
 

+  assert( pPager->eState>=PAGER_WRITER_LOCKED );
+  assert( assert_pager_state(pPager) );
+

   if( nSavepoint>nCurrent && pPager->useJournal ){
     int ii;                                 /* Iterator variable */
     PagerSavepoint *aNew;                   /* New Pager.aSavepoint array */
   if( nSavepoint>nCurrent && pPager->useJournal ){
     int ii;                                 /* Iterator variable */
     PagerSavepoint *aNew;                   /* New Pager.aSavepoint array */

-    int nPage;                              /* Size of database file */
-
-    rc = sqlite3PagerPagecount(pPager, &nPage);
-    if( rc ) return rc;

 
     /* Grow the Pager.aSavepoint array using realloc(). Return SQLITE_NOMEM
     ** if the allocation fails. Otherwise, zero the new portion in case a 
 
     /* Grow the Pager.aSavepoint array using realloc(). Return SQLITE_NOMEM
     ** if the allocation fails. Otherwise, zero the new portion in case a 


@@ -39361,14 +40156,14 @@ SQLITE_PRIVATE int sqlite3PagerOpenSavepoint(Pager *pPager, int nSavepoint){
 
     /* Populate the PagerSavepoint structures just allocated. */
     for(ii=nCurrent; ii<nSavepoint; ii++){
 
     /* Populate the PagerSavepoint structures just allocated. */
     for(ii=nCurrent; ii<nSavepoint; ii++){

-      aNew[ii].nOrig = nPage;
+      aNew[ii].nOrig = pPager->dbSize;

       if( isOpen(pPager->jfd) && pPager->journalOff>0 ){
         aNew[ii].iOffset = pPager->journalOff;
       }else{
         aNew[ii].iOffset = JOURNAL_HDR_SZ(pPager);
       }
       aNew[ii].iSubRec = pPager->nSubRec;
       if( isOpen(pPager->jfd) && pPager->journalOff>0 ){
         aNew[ii].iOffset = pPager->journalOff;
       }else{
         aNew[ii].iOffset = JOURNAL_HDR_SZ(pPager);
       }
       aNew[ii].iSubRec = pPager->nSubRec;

-      aNew[ii].pInSavepoint = sqlite3BitvecCreate(nPage);
+      aNew[ii].pInSavepoint = sqlite3BitvecCreate(pPager->dbSize);

       if( !aNew[ii].pInSavepoint ){
         return SQLITE_NOMEM;
       }
       if( !aNew[ii].pInSavepoint ){
         return SQLITE_NOMEM;
       }


@@ -39415,12 +40210,12 @@ SQLITE_PRIVATE int sqlite3PagerOpenSavepoint(Pager *pPager, int nSavepoint){
 ** savepoint. If no errors occur, SQLITE_OK is returned.
 */ 
 SQLITE_PRIVATE int sqlite3PagerSavepoint(Pager *pPager, int op, int iSavepoint){
 ** savepoint. If no errors occur, SQLITE_OK is returned.
 */ 
 SQLITE_PRIVATE int sqlite3PagerSavepoint(Pager *pPager, int op, int iSavepoint){

-  int rc = SQLITE_OK;
+  int rc = pPager->errCode;       /* Return code */

 
   assert( op==SAVEPOINT_RELEASE || op==SAVEPOINT_ROLLBACK );
   assert( iSavepoint>=0 || op==SAVEPOINT_ROLLBACK );
 
 
   assert( op==SAVEPOINT_RELEASE || op==SAVEPOINT_ROLLBACK );
   assert( iSavepoint>=0 || op==SAVEPOINT_ROLLBACK );
 

-  if( iSavepoint<pPager->nSavepoint ){
+  if( rc==SQLITE_OK && iSavepoint<pPager->nSavepoint ){

     int ii;            /* Iterator variable */
     int nNew;          /* Number of remaining savepoints after this op. */
 
     int ii;            /* Iterator variable */
     int nNew;          /* Number of remaining savepoints after this op. */
 


@@ -39456,8 +40251,8 @@ SQLITE_PRIVATE int sqlite3PagerSavepoint(Pager *pPager, int op, int iSavepoint){
       rc = pagerPlaybackSavepoint(pPager, pSavepoint);
       assert(rc!=SQLITE_DONE);
     }
       rc = pagerPlaybackSavepoint(pPager, pSavepoint);
       assert(rc!=SQLITE_DONE);
     }

-  

   }
   }

+

   return rc;
 }
 
   return rc;
 }
 


@@ -39555,6 +40350,10 @@ SQLITE_PRIVATE int sqlite3PagerMovepage(Pager *pPager, DbPage *pPg, Pgno pgno, i
   Pgno origPgno;               /* The original page number */
 
   assert( pPg->nRef>0 );
   Pgno origPgno;               /* The original page number */
 
   assert( pPg->nRef>0 );

+  assert( pPager->eState==PAGER_WRITER_CACHEMOD
+       || pPager->eState==PAGER_WRITER_DBMOD
+  );
+  assert( assert_pager_state(pPager) );

 
   /* In order to be able to rollback, an in-memory database must journal
   ** the page we are moving from.
 
   /* In order to be able to rollback, an in-memory database must journal
   ** the page we are moving from.


@@ -39604,11 +40403,10 @@ SQLITE_PRIVATE int sqlite3PagerMovepage(Pager *pPager, DbPage *pPg, Pgno pgno, i
     needSyncPgno = pPg->pgno;
     assert( pageInJournal(pPg) || pPg->pgno>pPager->dbOrigSize );
     assert( pPg->flags&PGHDR_DIRTY );
     needSyncPgno = pPg->pgno;
     assert( pageInJournal(pPg) || pPg->pgno>pPager->dbOrigSize );
     assert( pPg->flags&PGHDR_DIRTY );

-    assert( pPager->needSync );

   }
 
   /* If the cache contains a page with page-number pgno, remove it
   }
 
   /* If the cache contains a page with page-number pgno, remove it

-  ** from its hash chain. Also, if the PgHdr.needSync was set for 
+  ** from its hash chain. Also, if the PGHDR_NEED_SYNC flag was set for 

   ** page pgno before the 'move' operation, it needs to be retained 
   ** for the page moved there.
   */
   ** page pgno before the 'move' operation, it needs to be retained 
   ** for the page moved there.
   */


@@ -39620,7 +40418,6 @@ SQLITE_PRIVATE int sqlite3PagerMovepage(Pager *pPager, DbPage *pPg, Pgno pgno, i
     if( MEMDB ){
       /* Do not discard pages from an in-memory database since we might
       ** need to rollback later.  Just move the page out of the way. */
     if( MEMDB ){
       /* Do not discard pages from an in-memory database since we might
       ** need to rollback later.  Just move the page out of the way. */

-      assert( pPager->dbSizeValid );

       sqlite3PcacheMove(pPgOld, pPager->dbSize+1);
     }else{
       sqlite3PcacheDrop(pPgOld);
       sqlite3PcacheMove(pPgOld, pPager->dbSize+1);
     }else{
       sqlite3PcacheDrop(pPgOld);


@@ -39630,14 +40427,23 @@ SQLITE_PRIVATE int sqlite3PagerMovepage(Pager *pPager, DbPage *pPg, Pgno pgno, i
   origPgno = pPg->pgno;
   sqlite3PcacheMove(pPg, pgno);
   sqlite3PcacheMakeDirty(pPg);
   origPgno = pPg->pgno;
   sqlite3PcacheMove(pPg, pgno);
   sqlite3PcacheMakeDirty(pPg);

-  pPager->dbModified = 1;
+
+  /* For an in-memory database, make sure the original page continues
+  ** to exist, in case the transaction needs to roll back.  Use pPgOld
+  ** as the original page since it has already been allocated.
+  */
+  if( MEMDB ){
+    assert( pPgOld );
+    sqlite3PcacheMove(pPgOld, origPgno);
+    sqlite3PagerUnref(pPgOld);
+  }

 
   if( needSyncPgno ){
     /* If needSyncPgno is non-zero, then the journal file needs to be 
     ** sync()ed before any data is written to database file page needSyncPgno.
     ** Currently, no such page exists in the page-cache and the 
     ** "is journaled" bitvec flag has been set. This needs to be remedied by
 
   if( needSyncPgno ){
     /* If needSyncPgno is non-zero, then the journal file needs to be 
     ** sync()ed before any data is written to database file page needSyncPgno.
     ** Currently, no such page exists in the page-cache and the 
     ** "is journaled" bitvec flag has been set. This needs to be remedied by

-    ** loading the page into the pager-cache and setting the PgHdr.needSync 
+    ** loading the page into the pager-cache and setting the PGHDR_NEED_SYNC

     ** flag.
     **
     ** If the attempt to load the page into the page-cache fails, (due
     ** flag.
     **
     ** If the attempt to load the page into the page-cache fails, (due


@@ -39646,12 +40452,8 @@ SQLITE_PRIVATE int sqlite3PagerMovepage(Pager *pPager, DbPage *pPg, Pgno pgno, i
     ** this transaction, it may be written to the database file before
     ** it is synced into the journal file. This way, it may end up in
     ** the journal file twice, but that is not a problem.
     ** this transaction, it may be written to the database file before
     ** it is synced into the journal file. This way, it may end up in
     ** the journal file twice, but that is not a problem.

-    **
-    ** The sqlite3PagerGet() call may cause the journal to sync. So make
-    ** sure the Pager.needSync flag is set too.

     */
     PgHdr *pPgHdr;
     */
     PgHdr *pPgHdr;

-    assert( pPager->needSync );

     rc = sqlite3PagerGet(pPager, needSyncPgno, &pPgHdr);
     if( rc!=SQLITE_OK ){
       if( needSyncPgno<=pPager->dbOrigSize ){
     rc = sqlite3PagerGet(pPager, needSyncPgno, &pPgHdr);
     if( rc!=SQLITE_OK ){
       if( needSyncPgno<=pPager->dbOrigSize ){


@@ -39660,23 +40462,11 @@ SQLITE_PRIVATE int sqlite3PagerMovepage(Pager *pPager, DbPage *pPg, Pgno pgno, i
       }
       return rc;
     }
       }
       return rc;
     }

-    pPager->needSync = 1;
-    assert( pPager->noSync==0 && !MEMDB );

     pPgHdr->flags |= PGHDR_NEED_SYNC;
     sqlite3PcacheMakeDirty(pPgHdr);
     sqlite3PagerUnref(pPgHdr);
   }
 
     pPgHdr->flags |= PGHDR_NEED_SYNC;
     sqlite3PcacheMakeDirty(pPgHdr);
     sqlite3PagerUnref(pPgHdr);
   }
 

-  /*
-  ** For an in-memory database, make sure the original page continues
-  ** to exist, in case the transaction needs to roll back.  Use pPgOld
-  ** as the original page since it has already been allocated.
-  */
-  if( MEMDB ){
-    sqlite3PcacheMove(pPgOld, origPgno);
-    sqlite3PagerUnref(pPgOld);
-  }
-

   return SQLITE_OK;
 }
 #endif
   return SQLITE_OK;
 }
 #endif


@@ -39742,6 +40532,13 @@ SQLITE_PRIVATE int sqlite3PagerLockingMode(Pager *pPager, int eMode){
 SQLITE_PRIVATE int sqlite3PagerSetJournalMode(Pager *pPager, int eMode){
   u8 eOld = pPager->journalMode;    /* Prior journalmode */
 
 SQLITE_PRIVATE int sqlite3PagerSetJournalMode(Pager *pPager, int eMode){
   u8 eOld = pPager->journalMode;    /* Prior journalmode */
 

+#ifdef SQLITE_DEBUG
+  /* The print_pager_state() routine is intended to be used by the debugger
+  ** only.  We invoke it once here to suppress a compiler warning. */
+  print_pager_state(pPager);
+#endif
+
+

   /* The eMode parameter is always valid */
   assert(      eMode==PAGER_JOURNALMODE_DELETE
             || eMode==PAGER_JOURNALMODE_TRUNCATE
   /* The eMode parameter is always valid */
   assert(      eMode==PAGER_JOURNALMODE_DELETE
             || eMode==PAGER_JOURNALMODE_TRUNCATE


@@ -39767,20 +40564,13 @@ SQLITE_PRIVATE int sqlite3PagerSetJournalMode(Pager *pPager, int eMode){
   }
 
   if( eMode!=eOld ){
   }
 
   if( eMode!=eOld ){

-    /* When changing between rollback modes, close the journal file prior
-    ** to the change.  But when changing from a rollback mode to WAL, keep
-    ** the journal open since there is a rollback-style transaction in play
-    ** used to convert the version numbers in the btree header.
-    */
-    if( isOpen(pPager->jfd) && eMode!=PAGER_JOURNALMODE_WAL ){
-      sqlite3OsClose(pPager->jfd);
-    }

 
     /* Change the journal mode. */
 
     /* Change the journal mode. */

+    assert( pPager->eState!=PAGER_ERROR );

     pPager->journalMode = (u8)eMode;
 
     /* When transistioning from TRUNCATE or PERSIST to any other journal
     pPager->journalMode = (u8)eMode;
 
     /* When transistioning from TRUNCATE or PERSIST to any other journal

-    ** mode except WAL (and we are not in locking_mode=EXCLUSIVE) then 
+    ** mode except WAL, unless the pager is in locking_mode=exclusive mode,

     ** delete the journal file.
     */
     assert( (PAGER_JOURNALMODE_TRUNCATE & 5)==1 );
     ** delete the journal file.
     */
     assert( (PAGER_JOURNALMODE_TRUNCATE & 5)==1 );


@@ -39801,24 +40591,30 @@ SQLITE_PRIVATE int sqlite3PagerSetJournalMode(Pager *pPager, int eMode){
       ** database file. This ensures that the journal file is not deleted
       ** while it is in use by some other client.
       */
       ** database file. This ensures that the journal file is not deleted
       ** while it is in use by some other client.
       */

-      int rc = SQLITE_OK;
-      int state = pPager->state;
-      if( state<PAGER_SHARED ){
-        rc = sqlite3PagerSharedLock(pPager);
-      }
-      if( pPager->state==PAGER_SHARED ){
-        assert( rc==SQLITE_OK );
-        rc = sqlite3OsLock(pPager->fd, RESERVED_LOCK);
-      }
-      if( rc==SQLITE_OK ){
+      sqlite3OsClose(pPager->jfd);
+      if( pPager->eLock>=RESERVED_LOCK ){

         sqlite3OsDelete(pPager->pVfs, pPager->zJournal, 0);
         sqlite3OsDelete(pPager->pVfs, pPager->zJournal, 0);

+      }else{
+        int rc = SQLITE_OK;
+        int state = pPager->eState;
+        assert( state==PAGER_OPEN || state==PAGER_READER );
+        if( state==PAGER_OPEN ){
+          rc = sqlite3PagerSharedLock(pPager);
+        }
+        if( pPager->eState==PAGER_READER ){
+          assert( rc==SQLITE_OK );
+          rc = pagerLockDb(pPager, RESERVED_LOCK);
+        }
+        if( rc==SQLITE_OK ){
+          sqlite3OsDelete(pPager->pVfs, pPager->zJournal, 0);
+        }
+        if( rc==SQLITE_OK && state==PAGER_READER ){
+          pagerUnlockDb(pPager, SHARED_LOCK);
+        }else if( state==PAGER_OPEN ){
+          pager_unlock(pPager);
+        }
+        assert( state==pPager->eState );

       }
       }

-      if( rc==SQLITE_OK && state==PAGER_SHARED ){
-        sqlite3OsUnlock(pPager->fd, SHARED_LOCK);
-      }else if( state==PAGER_UNLOCK ){
-        pager_unlock(pPager);
-      }
-      assert( state==pPager->state );

     }
   }
 
     }
   }
 


@@ -39839,7 +40635,8 @@ SQLITE_PRIVATE int sqlite3PagerGetJournalMode(Pager *pPager){
 ** is unmodified.
 */
 SQLITE_PRIVATE int sqlite3PagerOkToChangeJournalMode(Pager *pPager){
 ** is unmodified.
 */
 SQLITE_PRIVATE int sqlite3PagerOkToChangeJournalMode(Pager *pPager){

-  if( pPager->dbModified ) return 0;
+  assert( assert_pager_state(pPager) );
+  if( pPager->eState>=PAGER_WRITER_CACHEMOD ) return 0;

   if( NEVER(isOpen(pPager->jfd) && pPager->journalOff>0) ) return 0;
   return 1;
 }
   if( NEVER(isOpen(pPager->jfd) && pPager->journalOff>0) ) return 0;
   return 1;
 }


@@ -39904,25 +40701,31 @@ SQLITE_PRIVATE int sqlite3PagerWalSupported(Pager *pPager){
 ** file (not a temp file or an in-memory database), and the WAL file
 ** is not already open, make an attempt to open it now. If successful,
 ** return SQLITE_OK. If an error occurs or the VFS used by the pager does 
 ** file (not a temp file or an in-memory database), and the WAL file
 ** is not already open, make an attempt to open it now. If successful,
 ** return SQLITE_OK. If an error occurs or the VFS used by the pager does 

-** not support the xShmXXX() methods, return an error code. *pisOpen is
+** not support the xShmXXX() methods, return an error code. *pbOpen is

 ** not modified in either case.
 **
 ** If the pager is open on a temp-file (or in-memory database), or if
 ** not modified in either case.
 **
 ** If the pager is open on a temp-file (or in-memory database), or if

-** the WAL file is already open, set *pisOpen to 1 and return SQLITE_OK
+** the WAL file is already open, set *pbOpen to 1 and return SQLITE_OK

 ** without doing anything.
 */
 SQLITE_PRIVATE int sqlite3PagerOpenWal(
   Pager *pPager,                  /* Pager object */
 ** without doing anything.
 */
 SQLITE_PRIVATE int sqlite3PagerOpenWal(
   Pager *pPager,                  /* Pager object */

-  int *pisOpen                    /* OUT: Set to true if call is a no-op */
+  int *pbOpen                     /* OUT: Set to true if call is a no-op */

 ){
   int rc = SQLITE_OK;             /* Return code */
 
 ){
   int rc = SQLITE_OK;             /* Return code */
 

-  assert( pPager->state>=PAGER_SHARED );
-  assert( (pisOpen==0 && !pPager->tempFile && !pPager->pWal) || *pisOpen==0 );
+  assert( assert_pager_state(pPager) );
+  assert( pPager->eState==PAGER_OPEN   || pbOpen );
+  assert( pPager->eState==PAGER_READER || !pbOpen );
+  assert( pbOpen==0 || *pbOpen==0 );
+  assert( pbOpen!=0 || (!pPager->tempFile && !pPager->pWal) );

 
   if( !pPager->tempFile && !pPager->pWal ){
     if( !sqlite3PagerWalSupported(pPager) ) return SQLITE_CANTOPEN;
 
 
   if( !pPager->tempFile && !pPager->pWal ){
     if( !sqlite3PagerWalSupported(pPager) ) return SQLITE_CANTOPEN;
 

+    /* Close any rollback journal previously open */
+    sqlite3OsClose(pPager->jfd);
+

     /* Open the connection to the log file. If this operation fails, 
     ** (e.g. due to malloc() failure), unlock the database file and 
     ** return an error code.
     /* Open the connection to the log file. If this operation fails, 
     ** (e.g. due to malloc() failure), unlock the database file and 
     ** return an error code.


@@ -39930,9 +40733,10 @@ SQLITE_PRIVATE int sqlite3PagerOpenWal(
     rc = sqlite3WalOpen(pPager->pVfs, pPager->fd, pPager->zWal, &pPager->pWal);
     if( rc==SQLITE_OK ){
       pPager->journalMode = PAGER_JOURNALMODE_WAL;
     rc = sqlite3WalOpen(pPager->pVfs, pPager->fd, pPager->zWal, &pPager->pWal);
     if( rc==SQLITE_OK ){
       pPager->journalMode = PAGER_JOURNALMODE_WAL;

+      pPager->eState = PAGER_OPEN;

     }
   }else{
     }
   }else{

-    *pisOpen = 1;
+    *pbOpen = 1;

   }
 
   return rc;
   }
 
   return rc;


@@ -39958,7 +40762,7 @@ SQLITE_PRIVATE int sqlite3PagerCloseWal(Pager *pPager){
   */
   if( !pPager->pWal ){
     int logexists = 0;
   */
   if( !pPager->pWal ){
     int logexists = 0;

-    rc = sqlite3OsLock(pPager->fd, SQLITE_LOCK_SHARED);
+    rc = pagerLockDb(pPager, SHARED_LOCK);

     if( rc==SQLITE_OK ){
       rc = sqlite3OsAccess(
           pPager->pVfs, pPager->zWal, SQLITE_ACCESS_EXISTS, &logexists
     if( rc==SQLITE_OK ){
       rc = sqlite3OsAccess(
           pPager->pVfs, pPager->zWal, SQLITE_ACCESS_EXISTS, &logexists


@@ -39974,7 +40778,7 @@ SQLITE_PRIVATE int sqlite3PagerCloseWal(Pager *pPager){
   ** the database file, the log and log-summary files will be deleted.
   */
   if( rc==SQLITE_OK && pPager->pWal ){
   ** the database file, the log and log-summary files will be deleted.
   */
   if( rc==SQLITE_OK && pPager->pWal ){

-    rc = sqlite3OsLock(pPager->fd, SQLITE_LOCK_EXCLUSIVE);
+    rc = pagerLockDb(pPager, EXCLUSIVE_LOCK);

     if( rc==SQLITE_OK ){
       rc = sqlite3WalClose(pPager->pWal,
                            (pPager->noSync ? 0 : pPager->sync_flags), 
     if( rc==SQLITE_OK ){
       rc = sqlite3WalClose(pPager->pWal,
                            (pPager->noSync ? 0 : pPager->sync_flags), 


@@ -39984,7 +40788,7 @@ SQLITE_PRIVATE int sqlite3PagerCloseWal(Pager *pPager){
     }else{
       /* If we cannot get an EXCLUSIVE lock, downgrade the PENDING lock
       ** that we did get back to SHARED. */
     }else{
       /* If we cannot get an EXCLUSIVE lock, downgrade the PENDING lock
       ** that we did get back to SHARED. */

-      sqlite3OsUnlock(pPager->fd, SQLITE_LOCK_SHARED);
+      pagerUnlockDb(pPager, SQLITE_LOCK_SHARED);

     }
   }
   return rc;
     }
   }
   return rc;


@@ -40304,6 +41108,10 @@ typedef struct WalCkptInfo WalCkptInfo;
 **
 ** The actual header in the wal-index consists of two copies of this
 ** object.
 **
 ** The actual header in the wal-index consists of two copies of this
 ** object.

+**
+** The szPage value can be any power of 2 between 512 and 32768, inclusive.
+** Or it can be 1 to represent a 65536-byte page.  The latter case was
+** added in 3.7.1 when support for 64K pages was added.  

 */
 struct WalIndexHdr {
   u32 iVersion;                   /* Wal-index version */
 */
 struct WalIndexHdr {
   u32 iVersion;                   /* Wal-index version */


@@ -40311,7 +41119,7 @@ struct WalIndexHdr {
   u32 iChange;                    /* Counter incremented each transaction */
   u8 isInit;                      /* 1 when initialized */
   u8 bigEndCksum;                 /* True if checksums in WAL are big-endian */
   u32 iChange;                    /* Counter incremented each transaction */
   u8 isInit;                      /* 1 when initialized */
   u8 bigEndCksum;                 /* True if checksums in WAL are big-endian */

-  u16 szPage;                     /* Database page size in bytes */
+  u16 szPage;                     /* Database page size in bytes. 1==64K */

   u32 mxFrame;                    /* Index of last valid frame in the WAL */
   u32 nPage;                      /* Size of database in pages */
   u32 aFrameCksum[2];             /* Checksum of last frame in log */
   u32 mxFrame;                    /* Index of last valid frame in the WAL */
   u32 nPage;                      /* Size of database in pages */
   u32 aFrameCksum[2];             /* Checksum of last frame in log */


@@ -40422,7 +41230,7 @@ struct Wal {
   u32 iCallback;             /* Value to pass to log callback (or 0) */
   int nWiData;               /* Size of array apWiData */
   volatile u32 **apWiData;   /* Pointer to wal-index content in memory */
   u32 iCallback;             /* Value to pass to log callback (or 0) */
   int nWiData;               /* Size of array apWiData */
   volatile u32 **apWiData;   /* Pointer to wal-index content in memory */

-  u16 szPage;                /* Database page size */
+  u32 szPage;                /* Database page size */

   i16 readLock;              /* Which read lock is being held.  -1 for none */
   u8 exclusiveMode;          /* Non-zero if connection is in exclusive mode */
   u8 writeLock;              /* True if in a write transaction */
   i16 readLock;              /* Which read lock is being held.  -1 for none */
   u8 exclusiveMode;          /* Non-zero if connection is in exclusive mode */
   u8 writeLock;              /* True if in a write transaction */


@@ -41093,7 +41901,7 @@ static int walIndexRecover(Wal *pWal){
       goto finished;
     }
     pWal->hdr.bigEndCksum = (u8)(magic&0x00000001);
       goto finished;
     }
     pWal->hdr.bigEndCksum = (u8)(magic&0x00000001);

-    pWal->szPage = (u16)szPage;
+    pWal->szPage = szPage;

     pWal->nCkpt = sqlite3Get4byte(&aBuf[12]);
     memcpy(&pWal->hdr.aSalt, &aBuf[16], 8);
 
     pWal->nCkpt = sqlite3Get4byte(&aBuf[12]);
     memcpy(&pWal->hdr.aSalt, &aBuf[16], 8);
 


@@ -41143,7 +41951,9 @@ static int walIndexRecover(Wal *pWal){
       if( nTruncate ){
         pWal->hdr.mxFrame = iFrame;
         pWal->hdr.nPage = nTruncate;
       if( nTruncate ){
         pWal->hdr.mxFrame = iFrame;
         pWal->hdr.nPage = nTruncate;

-        pWal->hdr.szPage = (u16)szPage;
+        pWal->hdr.szPage = (u16)((szPage&0xff00) | (szPage>>16));
+        testcase( szPage<=32768 );
+        testcase( szPage>=65536 );

         aFrameCksum[0] = pWal->hdr.aFrameCksum[0];
         aFrameCksum[1] = pWal->hdr.aFrameCksum[1];
       }
         aFrameCksum[0] = pWal->hdr.aFrameCksum[0];
         aFrameCksum[1] = pWal->hdr.aFrameCksum[1];
       }


@@ -41168,6 +41978,17 @@ finished:
     pInfo->nBackfill = 0;
     pInfo->aReadMark[0] = 0;
     for(i=1; i<WAL_NREADER; i++) pInfo->aReadMark[i] = READMARK_NOT_USED;
     pInfo->nBackfill = 0;
     pInfo->aReadMark[0] = 0;
     for(i=1; i<WAL_NREADER; i++) pInfo->aReadMark[i] = READMARK_NOT_USED;

+
+    /* If more than one frame was recovered from the log file, report an
+    ** event via sqlite3_log(). This is to help with identifying performance
+    ** problems caused by applications routinely shutting down without
+    ** checkpointing the log file.
+    */
+    if( pWal->hdr.nPage ){
+      sqlite3_log(SQLITE_OK, "Recovered %d frames from WAL file %s",
+          pWal->hdr.nPage, pWal->zWalName
+      );
+    }

   }
 
 recovery_error:
   }
 
 recovery_error:


@@ -41528,14 +42349,18 @@ static int walCheckpoint(
   u8 *zBuf                        /* Temporary buffer to use */
 ){
   int rc;                         /* Return code */
   u8 *zBuf                        /* Temporary buffer to use */
 ){
   int rc;                         /* Return code */

-  int szPage = pWal->hdr.szPage;  /* Database page-size */
+  int szPage;                     /* Database page-size */

   WalIterator *pIter = 0;         /* Wal iterator context */
   u32 iDbpage = 0;                /* Next database page to write */
   u32 iFrame = 0;                 /* Wal frame containing data for iDbpage */
   u32 mxSafeFrame;                /* Max frame that can be backfilled */
   WalIterator *pIter = 0;         /* Wal iterator context */
   u32 iDbpage = 0;                /* Next database page to write */
   u32 iFrame = 0;                 /* Wal frame containing data for iDbpage */
   u32 mxSafeFrame;                /* Max frame that can be backfilled */

+  u32 mxPage;                     /* Max database page to write */

   int i;                          /* Loop counter */
   volatile WalCkptInfo *pInfo;    /* The checkpoint status information */
 
   int i;                          /* Loop counter */
   volatile WalCkptInfo *pInfo;    /* The checkpoint status information */
 

+  szPage = (pWal->hdr.szPage&0xfe00) + ((pWal->hdr.szPage&0x0001)<<16);
+  testcase( szPage<=32768 );
+  testcase( szPage>=65536 );

   if( pWal->hdr.mxFrame==0 ) return SQLITE_OK;
 
   /* Allocate the iterator */
   if( pWal->hdr.mxFrame==0 ) return SQLITE_OK;
 
   /* Allocate the iterator */


@@ -41546,7 +42371,7 @@ static int walCheckpoint(
   assert( pIter );
 
   /*** TODO:  Move this test out to the caller.  Make it an assert() here ***/
   assert( pIter );
 
   /*** TODO:  Move this test out to the caller.  Make it an assert() here ***/

-  if( pWal->hdr.szPage!=nBuf ){
+  if( szPage!=nBuf ){

     rc = SQLITE_CORRUPT_BKPT;
     goto walcheckpoint_out;
   }
     rc = SQLITE_CORRUPT_BKPT;
     goto walcheckpoint_out;
   }


@@ -41557,6 +42382,7 @@ static int walCheckpoint(
   ** cannot be backfilled from the WAL.
   */
   mxSafeFrame = pWal->hdr.mxFrame;
   ** cannot be backfilled from the WAL.
   */
   mxSafeFrame = pWal->hdr.mxFrame;

+  mxPage = pWal->hdr.nPage;

   pInfo = walCkptInfo(pWal);
   for(i=1; i<WAL_NREADER; i++){
     u32 y = pInfo->aReadMark[i];
   pInfo = walCkptInfo(pWal);
   for(i=1; i<WAL_NREADER; i++){
     u32 y = pInfo->aReadMark[i];


@@ -41577,6 +42403,7 @@ static int walCheckpoint(
   if( pInfo->nBackfill<mxSafeFrame
    && (rc = walLockExclusive(pWal, WAL_READ_LOCK(0), 1))==SQLITE_OK
   ){
   if( pInfo->nBackfill<mxSafeFrame
    && (rc = walLockExclusive(pWal, WAL_READ_LOCK(0), 1))==SQLITE_OK
   ){

+    i64 nSize;                    /* Current size of database file */

     u32 nBackfill = pInfo->nBackfill;
 
     /* Sync the WAL to disk */
     u32 nBackfill = pInfo->nBackfill;
 
     /* Sync the WAL to disk */


@@ -41584,11 +42411,22 @@ static int walCheckpoint(
       rc = sqlite3OsSync(pWal->pWalFd, sync_flags);
     }
 
       rc = sqlite3OsSync(pWal->pWalFd, sync_flags);
     }
 

+    /* If the database file may grow as a result of this checkpoint, hint
+    ** about the eventual size of the db file to the VFS layer. 
+    */
+    if( rc==SQLITE_OK ){
+      i64 nReq = ((i64)mxPage * szPage);
+      rc = sqlite3OsFileSize(pWal->pDbFd, &nSize);
+      if( rc==SQLITE_OK && nSize<nReq ){
+        sqlite3OsFileControl(pWal->pDbFd, SQLITE_FCNTL_SIZE_HINT, &nReq);
+      }
+    }
+

     /* Iterate through the contents of the WAL, copying data to the db file. */
     while( rc==SQLITE_OK && 0==walIteratorNext(pIter, &iDbpage, &iFrame) ){
       i64 iOffset;
       assert( walFramePgno(pWal, iFrame)==iDbpage );
     /* Iterate through the contents of the WAL, copying data to the db file. */
     while( rc==SQLITE_OK && 0==walIteratorNext(pIter, &iDbpage, &iFrame) ){
       i64 iOffset;
       assert( walFramePgno(pWal, iFrame)==iDbpage );

-      if( iFrame<=nBackfill || iFrame>mxSafeFrame ) continue;
+      if( iFrame<=nBackfill || iFrame>mxSafeFrame || iDbpage>mxPage ) continue;

       iOffset = walFrameOffset(iFrame, szPage) + WAL_FRAME_HDRSIZE;
       /* testcase( IS_BIG_INT(iOffset) ); // requires a 4GiB WAL file */
       rc = sqlite3OsRead(pWal->pWalFd, zBuf, szPage, iOffset);
       iOffset = walFrameOffset(iFrame, szPage) + WAL_FRAME_HDRSIZE;
       /* testcase( IS_BIG_INT(iOffset) ); // requires a 4GiB WAL file */
       rc = sqlite3OsRead(pWal->pWalFd, zBuf, szPage, iOffset);


@@ -41695,7 +42533,7 @@ static int walIndexTryHdr(Wal *pWal, int *pChanged){
   /* The first page of the wal-index must be mapped at this point. */
   assert( pWal->nWiData>0 && pWal->apWiData[0] );
 
   /* The first page of the wal-index must be mapped at this point. */
   assert( pWal->nWiData>0 && pWal->apWiData[0] );
 

-  /* Read the header. This might happen currently with a write to the
+  /* Read the header. This might happen concurrently with a write to the

   ** same area of shared memory on a different CPU in a SMP,
   ** meaning it is possible that an inconsistent snapshot is read
   ** from the file. If this happens, return non-zero.
   ** same area of shared memory on a different CPU in a SMP,
   ** meaning it is possible that an inconsistent snapshot is read
   ** from the file. If this happens, return non-zero.


@@ -41724,7 +42562,9 @@ static int walIndexTryHdr(Wal *pWal, int *pChanged){
   if( memcmp(&pWal->hdr, &h1, sizeof(WalIndexHdr)) ){
     *pChanged = 1;
     memcpy(&pWal->hdr, &h1, sizeof(WalIndexHdr));
   if( memcmp(&pWal->hdr, &h1, sizeof(WalIndexHdr)) ){
     *pChanged = 1;
     memcpy(&pWal->hdr, &h1, sizeof(WalIndexHdr));

-    pWal->szPage = pWal->hdr.szPage;
+    pWal->szPage = (pWal->hdr.szPage&0xfe00) + ((pWal->hdr.szPage&0x0001)<<16);
+    testcase( pWal->szPage<=32768 );
+    testcase( pWal->szPage>=65536 );

   }
 
   /* The header was successfully read. Return zero. */
   }
 
   /* The header was successfully read. Return zero. */


@@ -42043,6 +42883,7 @@ SQLITE_PRIVATE int sqlite3WalBeginReadTransaction(Wal *pWal, int *pChanged){
 ** read-lock.
 */
 SQLITE_PRIVATE void sqlite3WalEndReadTransaction(Wal *pWal){
 ** read-lock.
 */
 SQLITE_PRIVATE void sqlite3WalEndReadTransaction(Wal *pWal){

+  sqlite3WalEndWriteTransaction(pWal);

   if( pWal->readLock>=0 ){
     walUnlockShared(pWal, WAL_READ_LOCK(pWal->readLock));
     pWal->readLock = -1;
   if( pWal->readLock>=0 ){
     walUnlockShared(pWal, WAL_READ_LOCK(pWal->readLock));
     pWal->readLock = -1;


@@ -42153,7 +42994,13 @@ SQLITE_PRIVATE int sqlite3WalRead(
   ** required page. Read and return data from the log file.
   */
   if( iRead ){
   ** required page. Read and return data from the log file.
   */
   if( iRead ){

-    i64 iOffset = walFrameOffset(iRead, pWal->hdr.szPage) + WAL_FRAME_HDRSIZE;
+    int sz;
+    i64 iOffset;
+    sz = pWal->hdr.szPage;
+    sz = (pWal->hdr.szPage&0xfe00) + ((pWal->hdr.szPage&0x0001)<<16);
+    testcase( sz<=32768 );
+    testcase( sz>=65536 );
+    iOffset = walFrameOffset(iRead, sz) + WAL_FRAME_HDRSIZE;

     *pInWal = 1;
     /* testcase( IS_BIG_INT(iOffset) ); // requires a 4GiB WAL */
     return sqlite3OsRead(pWal->pWalFd, pOut, nOut, iOffset);
     *pInWal = 1;
     /* testcase( IS_BIG_INT(iOffset) ); // requires a 4GiB WAL */
     return sqlite3OsRead(pWal->pWalFd, pOut, nOut, iOffset);


@@ -42165,11 +43012,13 @@ SQLITE_PRIVATE int sqlite3WalRead(
 
 
 /* 
 
 
 /* 

-** Set *pPgno to the size of the database file (or zero, if unknown).
+** Return the size of the database in pages (or zero, if unknown).

 */
 */

-SQLITE_PRIVATE void sqlite3WalDbsize(Wal *pWal, Pgno *pPgno){
-  assert( pWal->readLock>=0 || pWal->lockError );
-  *pPgno = pWal->hdr.nPage;
+SQLITE_PRIVATE Pgno sqlite3WalDbsize(Wal *pWal){
+  if( pWal && ALWAYS(pWal->readLock>=0) ){
+    return pWal->hdr.nPage;
+  }
+  return 0;

 }
 
 
 }
 
 


@@ -42245,7 +43094,7 @@ SQLITE_PRIVATE int sqlite3WalEndWriteTransaction(Wal *pWal){
 */
 SQLITE_PRIVATE int sqlite3WalUndo(Wal *pWal, int (*xUndo)(void *, Pgno), void *pUndoCtx){
   int rc = SQLITE_OK;
 */
 SQLITE_PRIVATE int sqlite3WalUndo(Wal *pWal, int (*xUndo)(void *, Pgno), void *pUndoCtx){
   int rc = SQLITE_OK;

-  if( pWal->writeLock ){
+  if( ALWAYS(pWal->writeLock) ){

     Pgno iMax = pWal->hdr.mxFrame;
     Pgno iFrame;
   
     Pgno iMax = pWal->hdr.mxFrame;
     Pgno iFrame;
   


@@ -42434,7 +43283,7 @@ SQLITE_PRIVATE int sqlite3WalFrames(
     sqlite3Put4byte(&aWalHdr[24], aCksum[0]);
     sqlite3Put4byte(&aWalHdr[28], aCksum[1]);
     
     sqlite3Put4byte(&aWalHdr[24], aCksum[0]);
     sqlite3Put4byte(&aWalHdr[28], aCksum[1]);
     

-    pWal->szPage = (u16)szPage;
+    pWal->szPage = szPage;

     pWal->hdr.bigEndCksum = SQLITE_BIGENDIAN;
     pWal->hdr.aFrameCksum[0] = aCksum[0];
     pWal->hdr.aFrameCksum[1] = aCksum[1];
     pWal->hdr.bigEndCksum = SQLITE_BIGENDIAN;
     pWal->hdr.aFrameCksum[0] = aCksum[0];
     pWal->hdr.aFrameCksum[1] = aCksum[1];


@@ -42529,7 +43378,9 @@ SQLITE_PRIVATE int sqlite3WalFrames(
 
   if( rc==SQLITE_OK ){
     /* Update the private copy of the header. */
 
   if( rc==SQLITE_OK ){
     /* Update the private copy of the header. */

-    pWal->hdr.szPage = (u16)szPage;
+    pWal->hdr.szPage = (u16)((szPage&0xff00) | (szPage>>16));
+    testcase( szPage<=32768 );
+    testcase( szPage>=65536 );

     pWal->hdr.mxFrame = iFrame;
     if( isCommit ){
       pWal->hdr.iChange++;
     pWal->hdr.mxFrame = iFrame;
     if( isCommit ){
       pWal->hdr.iChange++;


@@ -42741,7 +43592,7 @@ SQLITE_PRIVATE int sqlite3WalExclusiveMode(Wal *pWal, int op){
 **
 ** The file is divided into pages.  The first page is called page 1,
 ** the second is page 2, and so forth.  A page number of zero indicates
 **
 ** The file is divided into pages.  The first page is called page 1,
 ** the second is page 2, and so forth.  A page number of zero indicates

-** "no such page".  The page size can be any power of 2 between 512 and 32768.
+** "no such page".  The page size can be any power of 2 between 512 and 65536.

 ** Each page can be either a btree page, a freelist page, an overflow
 ** page, or a pointer-map page.
 **
 ** Each page can be either a btree page, a freelist page, an overflow
 ** page, or a pointer-map page.
 **


@@ -43107,14 +43958,14 @@ struct BtShared {
   u8 autoVacuum;        /* True if auto-vacuum is enabled */
   u8 incrVacuum;        /* True if incr-vacuum is enabled */
 #endif
   u8 autoVacuum;        /* True if auto-vacuum is enabled */
   u8 incrVacuum;        /* True if incr-vacuum is enabled */
 #endif

-  u16 pageSize;         /* Total number of bytes on a page */
-  u16 usableSize;       /* Number of usable bytes on each page */

   u16 maxLocal;         /* Maximum local payload in non-LEAFDATA tables */
   u16 minLocal;         /* Minimum local payload in non-LEAFDATA tables */
   u16 maxLeaf;          /* Maximum local payload in a LEAFDATA table */
   u16 minLeaf;          /* Minimum local payload in a LEAFDATA table */
   u8 inTransaction;     /* Transaction state */
   u8 doNotUseWAL;       /* If true, do not open write-ahead-log file */
   u16 maxLocal;         /* Maximum local payload in non-LEAFDATA tables */
   u16 minLocal;         /* Minimum local payload in non-LEAFDATA tables */
   u16 maxLeaf;          /* Maximum local payload in a LEAFDATA table */
   u16 minLeaf;          /* Minimum local payload in a LEAFDATA table */
   u8 inTransaction;     /* Transaction state */
   u8 doNotUseWAL;       /* If true, do not open write-ahead-log file */

+  u32 pageSize;         /* Total number of bytes on a page */
+  u32 usableSize;       /* Number of usable bytes on each page */

   int nTransaction;     /* Number of open transactions (read + write) */
   u32 nPage;            /* Number of pages in the database */
   void *pSchema;        /* Pointer to space allocated by sqlite3BtreeSchema() */
   int nTransaction;     /* Number of open transactions (read + write) */
   u32 nPage;            /* Number of pages in the database */
   void *pSchema;        /* Pointer to space allocated by sqlite3BtreeSchema() */


@@ -43713,7 +44564,16 @@ int sqlite3BtreeTrace=1;  /* True to enable tracing */
 # define TRACE(X)
 #endif
 
 # define TRACE(X)
 #endif
 

-
+/*
+** Extract a 2-byte big-endian integer from an array of unsigned bytes.
+** But if the value is zero, make it 65536.
+**
+** This routine is used to extract the "offset to cell content area" value
+** from the header of a btree page.  If the page size is 65536 and the page
+** is empty, the offset should be 65536, but the 2-byte value stores zero.
+** This routine makes the necessary adjustment to 65536.
+*/
+#define get2byteNotZero(X)  (((((int)get2byte(X))-1)&0xffff)+1)

 
 #ifndef SQLITE_OMIT_SHARED_CACHE
 /*
 
 #ifndef SQLITE_OMIT_SHARED_CACHE
 /*


@@ -44402,11 +45262,16 @@ SQLITE_PRIVATE int sqlite3BtreeCursorHasMoved(BtCursor *pCur, int *pHasMoved){
 ** Given a page number of a regular database page, return the page
 ** number for the pointer-map page that contains the entry for the
 ** input page number.
 ** Given a page number of a regular database page, return the page
 ** number for the pointer-map page that contains the entry for the
 ** input page number.

+**
+** Return 0 (not a valid page) for pgno==1 since there is
+** no pointer map associated with page 1.  The integrity_check logic
+** requires that ptrmapPageno(*,1)!=1.

 */
 static Pgno ptrmapPageno(BtShared *pBt, Pgno pgno){
   int nPagesPerMapPage;
   Pgno iPtrMap, ret;
   assert( sqlite3_mutex_held(pBt->mutex) );
 */
 static Pgno ptrmapPageno(BtShared *pBt, Pgno pgno){
   int nPagesPerMapPage;
   Pgno iPtrMap, ret;
   assert( sqlite3_mutex_held(pBt->mutex) );

+  if( pgno<2 ) return 0;

   nPagesPerMapPage = (pBt->usableSize/5)+1;
   iPtrMap = (pgno-2)/nPagesPerMapPage;
   ret = (iPtrMap*nPagesPerMapPage) + 2; 
   nPagesPerMapPage = (pBt->usableSize/5)+1;
   iPtrMap = (pgno-2)/nPagesPerMapPage;
   ret = (iPtrMap*nPagesPerMapPage) + 2; 


@@ -44835,7 +45700,7 @@ static int allocateSpace(MemPage *pPage, int nByte, int *pIdx){
   nFrag = data[hdr+7];
   assert( pPage->cellOffset == hdr + 12 - 4*pPage->leaf );
   gap = pPage->cellOffset + 2*pPage->nCell;
   nFrag = data[hdr+7];
   assert( pPage->cellOffset == hdr + 12 - 4*pPage->leaf );
   gap = pPage->cellOffset + 2*pPage->nCell;

-  top = get2byte(&data[hdr+5]);
+  top = get2byteNotZero(&data[hdr+5]);

   if( gap>top ) return SQLITE_CORRUPT_BKPT;
   testcase( gap+2==top );
   testcase( gap+1==top );
   if( gap>top ) return SQLITE_CORRUPT_BKPT;
   testcase( gap+2==top );
   testcase( gap+1==top );


@@ -44845,7 +45710,7 @@ static int allocateSpace(MemPage *pPage, int nByte, int *pIdx){
     /* Always defragment highly fragmented pages */
     rc = defragmentPage(pPage);
     if( rc ) return rc;
     /* Always defragment highly fragmented pages */
     rc = defragmentPage(pPage);
     if( rc ) return rc;

-    top = get2byte(&data[hdr+5]);
+    top = get2byteNotZero(&data[hdr+5]);

   }else if( gap+2<=top ){
     /* Search the freelist looking for a free slot big enough to satisfy 
     ** the request. The allocation is made from the first free slot in 
   }else if( gap+2<=top ){
     /* Search the freelist looking for a free slot big enough to satisfy 
     ** the request. The allocation is made from the first free slot in 


@@ -44887,7 +45752,7 @@ static int allocateSpace(MemPage *pPage, int nByte, int *pIdx){
   if( gap+2+nByte>top ){
     rc = defragmentPage(pPage);
     if( rc ) return rc;
   if( gap+2+nByte>top ){
     rc = defragmentPage(pPage);
     if( rc ) return rc;

-    top = get2byte(&data[hdr+5]);
+    top = get2byteNotZero(&data[hdr+5]);

     assert( gap+nByte<=top );
   }
 
     assert( gap+nByte<=top );
   }
 


@@ -45053,10 +45918,10 @@ static int btreeInitPage(MemPage *pPage){
     u8 hdr;            /* Offset to beginning of page header */
     u8 *data;          /* Equal to pPage->aData */
     BtShared *pBt;        /* The main btree structure */
     u8 hdr;            /* Offset to beginning of page header */
     u8 *data;          /* Equal to pPage->aData */
     BtShared *pBt;        /* The main btree structure */

-    u16 usableSize;    /* Amount of usable space on each page */
+    int usableSize;    /* Amount of usable space on each page */

     u16 cellOffset;    /* Offset from start of page to first cell pointer */
     u16 cellOffset;    /* Offset from start of page to first cell pointer */

-    u16 nFree;         /* Number of unused bytes on the page */
-    u16 top;           /* First byte of the cell content area */
+    int nFree;         /* Number of unused bytes on the page */
+    int top;           /* First byte of the cell content area */

     int iCellFirst;    /* First allowable cell or freeblock offset */
     int iCellLast;     /* Last possible cell or freeblock offset */
 
     int iCellFirst;    /* First allowable cell or freeblock offset */
     int iCellLast;     /* Last possible cell or freeblock offset */
 


@@ -45065,12 +45930,12 @@ static int btreeInitPage(MemPage *pPage){
     hdr = pPage->hdrOffset;
     data = pPage->aData;
     if( decodeFlags(pPage, data[hdr]) ) return SQLITE_CORRUPT_BKPT;
     hdr = pPage->hdrOffset;
     data = pPage->aData;
     if( decodeFlags(pPage, data[hdr]) ) return SQLITE_CORRUPT_BKPT;

-    assert( pBt->pageSize>=512 && pBt->pageSize<=32768 );
-    pPage->maskPage = pBt->pageSize - 1;
+    assert( pBt->pageSize>=512 && pBt->pageSize<=65536 );
+    pPage->maskPage = (u16)(pBt->pageSize - 1);

     pPage->nOverflow = 0;
     usableSize = pBt->usableSize;
     pPage->cellOffset = cellOffset = hdr + 12 - 4*pPage->leaf;
     pPage->nOverflow = 0;
     usableSize = pBt->usableSize;
     pPage->cellOffset = cellOffset = hdr + 12 - 4*pPage->leaf;

-    top = get2byte(&data[hdr+5]);
+    top = get2byteNotZero(&data[hdr+5]);

     pPage->nCell = get2byte(&data[hdr+3]);
     if( pPage->nCell>MX_CELL(pBt) ){
       /* To many cells for a single page.  The page must be corrupt */
     pPage->nCell = get2byte(&data[hdr+3]);
     if( pPage->nCell>MX_CELL(pBt) ){
       /* To many cells for a single page.  The page must be corrupt */


@@ -45169,13 +46034,13 @@ static void zeroPage(MemPage *pPage, int flags){
   memset(&data[hdr+1], 0, 4);
   data[hdr+7] = 0;
   put2byte(&data[hdr+5], pBt->usableSize);
   memset(&data[hdr+1], 0, 4);
   data[hdr+7] = 0;
   put2byte(&data[hdr+5], pBt->usableSize);

-  pPage->nFree = pBt->usableSize - first;
+  pPage->nFree = (u16)(pBt->usableSize - first);

   decodeFlags(pPage, flags);
   pPage->hdrOffset = hdr;
   pPage->cellOffset = first;
   pPage->nOverflow = 0;
   decodeFlags(pPage, flags);
   pPage->hdrOffset = hdr;
   pPage->cellOffset = first;
   pPage->nOverflow = 0;

-  assert( pBt->pageSize>=512 && pBt->pageSize<=32768 );
-  pPage->maskPage = pBt->pageSize - 1;
+  assert( pBt->pageSize>=512 && pBt->pageSize<=65536 );
+  pPage->maskPage = (u16)(pBt->pageSize - 1);

   pPage->nCell = 0;
   pPage->isInit = 1;
 }
   pPage->nCell = 0;
   pPage->isInit = 1;
 }


@@ -45483,7 +46348,7 @@ SQLITE_PRIVATE int sqlite3BtreeOpen(
 #ifdef SQLITE_SECURE_DELETE
     pBt->secureDelete = 1;
 #endif
 #ifdef SQLITE_SECURE_DELETE
     pBt->secureDelete = 1;
 #endif

-    pBt->pageSize = get2byte(&zDbHeader[16]);
+    pBt->pageSize = (zDbHeader[16]<<8) | (zDbHeader[17]<<16);

     if( pBt->pageSize<512 || pBt->pageSize>SQLITE_MAX_PAGE_SIZE
          || ((pBt->pageSize-1)&pBt->pageSize)!=0 ){
       pBt->pageSize = 0;
     if( pBt->pageSize<512 || pBt->pageSize>SQLITE_MAX_PAGE_SIZE
          || ((pBt->pageSize-1)&pBt->pageSize)!=0 ){
       pBt->pageSize = 0;


@@ -45685,7 +46550,7 @@ SQLITE_PRIVATE int sqlite3BtreeClose(Btree *p){
     if( pBt->xFreeSchema && pBt->pSchema ){
       pBt->xFreeSchema(pBt->pSchema);
     }
     if( pBt->xFreeSchema && pBt->pSchema ){
       pBt->xFreeSchema(pBt->pSchema);
     }

-    sqlite3_free(pBt->pSchema);
+    sqlite3DbFree(0, pBt->pSchema);

     freeTempSpace(pBt);
     sqlite3_free(pBt);
   }
     freeTempSpace(pBt);
     sqlite3_free(pBt);
   }


@@ -45797,7 +46662,7 @@ SQLITE_PRIVATE int sqlite3BtreeSetPageSize(Btree *p, int pageSize, int nReserve,
         ((pageSize-1)&pageSize)==0 ){
     assert( (pageSize & 7)==0 );
     assert( !pBt->pPage1 && !pBt->pCursor );
         ((pageSize-1)&pageSize)==0 ){
     assert( (pageSize & 7)==0 );
     assert( !pBt->pPage1 && !pBt->pCursor );

-    pBt->pageSize = (u16)pageSize;
+    pBt->pageSize = (u32)pageSize;

     freeTempSpace(pBt);
   }
   rc = sqlite3PagerSetPagesize(pBt->pPager, &pBt->pageSize, nReserve);
     freeTempSpace(pBt);
   }
   rc = sqlite3PagerSetPagesize(pBt->pPager, &pBt->pageSize, nReserve);


@@ -45932,15 +46797,13 @@ static int lockBtree(BtShared *pBt){
   ** a valid database file. 
   */
   nPage = nPageHeader = get4byte(28+(u8*)pPage1->aData);
   ** a valid database file. 
   */
   nPage = nPageHeader = get4byte(28+(u8*)pPage1->aData);

-  if( (rc = sqlite3PagerPagecount(pBt->pPager, &nPageFile))!=SQLITE_OK ){;
-    goto page1_init_failed;
-  }
+  sqlite3PagerPagecount(pBt->pPager, &nPageFile);

   if( nPage==0 || memcmp(24+(u8*)pPage1->aData, 92+(u8*)pPage1->aData,4)!=0 ){
     nPage = nPageFile;
   }
   if( nPage>0 ){
   if( nPage==0 || memcmp(24+(u8*)pPage1->aData, 92+(u8*)pPage1->aData,4)!=0 ){
     nPage = nPageFile;
   }
   if( nPage>0 ){

-    int pageSize;
-    int usableSize;
+    u32 pageSize;
+    u32 usableSize;

     u8 *page1 = pPage1->aData;
     rc = SQLITE_NOTADB;
     if( memcmp(page1, zMagicHeader, 16)!=0 ){
     u8 *page1 = pPage1->aData;
     rc = SQLITE_NOTADB;
     if( memcmp(page1, zMagicHeader, 16)!=0 ){


@@ -45991,15 +46854,16 @@ static int lockBtree(BtShared *pBt){
     if( memcmp(&page1[21], "\100\040\040",3)!=0 ){
       goto page1_init_failed;
     }
     if( memcmp(&page1[21], "\100\040\040",3)!=0 ){
       goto page1_init_failed;
     }

-    pageSize = get2byte(&page1[16]);
-    if( ((pageSize-1)&pageSize)!=0 || pageSize<512 ||
-        (SQLITE_MAX_PAGE_SIZE<32768 && pageSize>SQLITE_MAX_PAGE_SIZE)
+    pageSize = (page1[16]<<8) | (page1[17]<<16);
+    if( ((pageSize-1)&pageSize)!=0
+     || pageSize>SQLITE_MAX_PAGE_SIZE 
+     || pageSize<=256 

     ){
       goto page1_init_failed;
     }
     assert( (pageSize & 7)==0 );
     usableSize = pageSize - page1[20];
     ){
       goto page1_init_failed;
     }
     assert( (pageSize & 7)==0 );
     usableSize = pageSize - page1[20];

-    if( pageSize!=pBt->pageSize ){
+    if( (u32)pageSize!=pBt->pageSize ){

       /* After reading the first page of the database assuming a page size
       ** of BtShared.pageSize, we have discovered that the page-size is
       ** actually pageSize. Unlock the database, leave pBt->pPage1 at
       /* After reading the first page of the database assuming a page size
       ** of BtShared.pageSize, we have discovered that the page-size is
       ** actually pageSize. Unlock the database, leave pBt->pPage1 at


@@ -46007,8 +46871,8 @@ static int lockBtree(BtShared *pBt){
       ** again with the correct page-size.
       */
       releasePage(pPage1);
       ** again with the correct page-size.
       */
       releasePage(pPage1);

-      pBt->usableSize = (u16)usableSize;
-      pBt->pageSize = (u16)pageSize;
+      pBt->usableSize = usableSize;
+      pBt->pageSize = pageSize;

       freeTempSpace(pBt);
       rc = sqlite3PagerSetPagesize(pBt->pPager, &pBt->pageSize,
                                    pageSize-usableSize);
       freeTempSpace(pBt);
       rc = sqlite3PagerSetPagesize(pBt->pPager, &pBt->pageSize,
                                    pageSize-usableSize);


@@ -46021,8 +46885,8 @@ static int lockBtree(BtShared *pBt){
     if( usableSize<480 ){
       goto page1_init_failed;
     }
     if( usableSize<480 ){
       goto page1_init_failed;
     }

-    pBt->pageSize = (u16)pageSize;
-    pBt->usableSize = (u16)usableSize;
+    pBt->pageSize = pageSize;
+    pBt->usableSize = usableSize;

 #ifndef SQLITE_OMIT_AUTOVACUUM
     pBt->autoVacuum = (get4byte(&page1[36 + 4*4])?1:0);
     pBt->incrVacuum = (get4byte(&page1[36 + 7*4])?1:0);
 #ifndef SQLITE_OMIT_AUTOVACUUM
     pBt->autoVacuum = (get4byte(&page1[36 + 4*4])?1:0);
     pBt->incrVacuum = (get4byte(&page1[36 + 7*4])?1:0);


@@ -46038,14 +46902,14 @@ static int lockBtree(BtShared *pBt){
   **     9-byte nKey value
   **     4-byte nData value
   **     4-byte overflow page pointer
   **     9-byte nKey value
   **     4-byte nData value
   **     4-byte overflow page pointer

-  ** So a cell consists of a 2-byte poiner, a header which is as much as
+  ** So a cell consists of a 2-byte pointer, a header which is as much as

   ** 17 bytes long, 0 to N bytes of payload, and an optional 4 byte overflow
   ** page pointer.
   */
   ** 17 bytes long, 0 to N bytes of payload, and an optional 4 byte overflow
   ** page pointer.
   */

-  pBt->maxLocal = (pBt->usableSize-12)*64/255 - 23;
-  pBt->minLocal = (pBt->usableSize-12)*32/255 - 23;
-  pBt->maxLeaf = pBt->usableSize - 35;
-  pBt->minLeaf = (pBt->usableSize-12)*32/255 - 23;
+  pBt->maxLocal = (u16)((pBt->usableSize-12)*64/255 - 23);
+  pBt->minLocal = (u16)((pBt->usableSize-12)*32/255 - 23);
+  pBt->maxLeaf = (u16)(pBt->usableSize - 35);
+  pBt->minLeaf = (u16)((pBt->usableSize-12)*32/255 - 23);

   assert( pBt->maxLeaf + 23 <= MX_CELL_SIZE(pBt) );
   pBt->pPage1 = pPage1;
   pBt->nPage = nPage;
   assert( pBt->maxLeaf + 23 <= MX_CELL_SIZE(pBt) );
   pBt->pPage1 = pPage1;
   pBt->nPage = nPage;


@@ -46098,7 +46962,8 @@ static int newDatabase(BtShared *pBt){
   if( rc ) return rc;
   memcpy(data, zMagicHeader, sizeof(zMagicHeader));
   assert( sizeof(zMagicHeader)==16 );
   if( rc ) return rc;
   memcpy(data, zMagicHeader, sizeof(zMagicHeader));
   assert( sizeof(zMagicHeader)==16 );

-  put2byte(&data[16], pBt->pageSize);
+  data[16] = (u8)((pBt->pageSize>>8)&0xff);
+  data[17] = (u8)((pBt->pageSize>>16)&0xff);

   data[18] = 1;
   data[19] = 1;
   assert( pBt->usableSize<=pBt->pageSize && pBt->usableSize+255>=pBt->pageSize);
   data[18] = 1;
   data[19] = 1;
   assert( pBt->usableSize<=pBt->pageSize && pBt->usableSize+255>=pBt->pageSize);


@@ -47009,9 +47874,11 @@ SQLITE_PRIVATE int sqlite3BtreeSavepoint(Btree *p, int op, int iSavepoint){
       if( iSavepoint<0 && pBt->initiallyEmpty ) pBt->nPage = 0;
       rc = newDatabase(pBt);
       pBt->nPage = get4byte(28 + pBt->pPage1->aData);
       if( iSavepoint<0 && pBt->initiallyEmpty ) pBt->nPage = 0;
       rc = newDatabase(pBt);
       pBt->nPage = get4byte(28 + pBt->pPage1->aData);

-      if( pBt->nPage==0 ){
-        sqlite3PagerPagecount(pBt->pPager, (int*)&pBt->nPage);
-      }
+
+      /* The database size was written into the offset 28 of the header
+      ** when the transaction started, so we know that the value at offset
+      ** 28 is nonzero. */
+      assert( pBt->nPage>0 );

     }
     sqlite3BtreeLeave(p);
   }
     }
     sqlite3BtreeLeave(p);
   }


@@ -48107,9 +48974,9 @@ SQLITE_PRIVATE int sqlite3BtreeMovetoUnpacked(
         pCur->validNKey = 1;
         pCur->info.nKey = nCellKey;
       }else{
         pCur->validNKey = 1;
         pCur->info.nKey = nCellKey;
       }else{

-        /* The maximum supported page-size is 32768 bytes. This means that
+        /* The maximum supported page-size is 65536 bytes. This means that

         ** the maximum number of record bytes stored on an index B-Tree
         ** the maximum number of record bytes stored on an index B-Tree

-        ** page is at most 8198 bytes, which may be stored as a 2-byte
+        ** page is less than 16384 bytes and may be stored as a 2-byte

         ** varint. This information is used to attempt to avoid parsing 
         ** the entire cell by checking for the cases where the record is 
         ** stored entirely within the b-tree page by inspecting the first 
         ** varint. This information is used to attempt to avoid parsing 
         ** the entire cell by checking for the cases where the record is 
         ** stored entirely within the b-tree page by inspecting the first 


@@ -48472,6 +49339,10 @@ static int allocateBtreePage(
           if( !pPrevTrunk ){
             memcpy(&pPage1->aData[32], &pTrunk->aData[0], 4);
           }else{
           if( !pPrevTrunk ){
             memcpy(&pPage1->aData[32], &pTrunk->aData[0], 4);
           }else{

+            rc = sqlite3PagerWrite(pPrevTrunk->pDbPage);
+            if( rc!=SQLITE_OK ){
+              goto end_allocate_page;
+            }

             memcpy(&pPrevTrunk->aData[0], &pTrunk->aData[0], 4);
           }
         }else{
             memcpy(&pPrevTrunk->aData[0], &pTrunk->aData[0], 4);
           }
         }else{


@@ -48778,7 +49649,7 @@ static int clearCell(MemPage *pPage, unsigned char *pCell){
   Pgno ovflPgno;
   int rc;
   int nOvfl;
   Pgno ovflPgno;
   int rc;
   int nOvfl;

-  u16 ovflPageSize;
+  u32 ovflPageSize;

 
   assert( sqlite3_mutex_held(pPage->pBt->mutex) );
   btreeParseCellPtr(pPage, pCell, &info);
 
   assert( sqlite3_mutex_held(pPage->pBt->mutex) );
   btreeParseCellPtr(pPage, pCell, &info);


@@ -49003,7 +49874,7 @@ static int fillInCell(
 */
 static void dropCell(MemPage *pPage, int idx, int sz, int *pRC){
   int i;          /* Loop counter */
 */
 static void dropCell(MemPage *pPage, int idx, int sz, int *pRC){
   int i;          /* Loop counter */

-  int pc;         /* Offset to cell content of cell being deleted */
+  u32 pc;         /* Offset to cell content of cell being deleted */

   u8 *data;       /* pPage->aData */
   u8 *ptr;        /* Used to move bytes around within data[] */
   int rc;         /* The return code */
   u8 *data;       /* pPage->aData */
   u8 *ptr;        /* Used to move bytes around within data[] */
   int rc;         /* The return code */


@@ -49021,7 +49892,7 @@ static void dropCell(MemPage *pPage, int idx, int sz, int *pRC){
   hdr = pPage->hdrOffset;
   testcase( pc==get2byte(&data[hdr+5]) );
   testcase( pc+sz==pPage->pBt->usableSize );
   hdr = pPage->hdrOffset;
   testcase( pc==get2byte(&data[hdr+5]) );
   testcase( pc+sz==pPage->pBt->usableSize );

-  if( pc < get2byte(&data[hdr+5]) || pc+sz > pPage->pBt->usableSize ){
+  if( pc < (u32)get2byte(&data[hdr+5]) || pc+sz > pPage->pBt->usableSize ){

     *pRC = SQLITE_CORRUPT_BKPT;
     return;
   }
     *pRC = SQLITE_CORRUPT_BKPT;
     return;
   }


@@ -49078,7 +49949,7 @@ static void insertCell(
   if( *pRC ) return;
 
   assert( i>=0 && i<=pPage->nCell+pPage->nOverflow );
   if( *pRC ) return;
 
   assert( i>=0 && i<=pPage->nCell+pPage->nOverflow );

-  assert( pPage->nCell<=MX_CELL(pPage->pBt) && MX_CELL(pPage->pBt)<=5460 );
+  assert( pPage->nCell<=MX_CELL(pPage->pBt) && MX_CELL(pPage->pBt)<=10921 );

   assert( pPage->nOverflow<=ArraySize(pPage->aOvfl) );
   assert( sqlite3_mutex_held(pPage->pBt->mutex) );
   /* The cell should normally be sized correctly.  However, when moving a
   assert( pPage->nOverflow<=ArraySize(pPage->aOvfl) );
   assert( sqlite3_mutex_held(pPage->pBt->mutex) );
   /* The cell should normally be sized correctly.  However, when moving a


@@ -49158,12 +50029,12 @@ static void assemblePage(
 
   assert( pPage->nOverflow==0 );
   assert( sqlite3_mutex_held(pPage->pBt->mutex) );
 
   assert( pPage->nOverflow==0 );
   assert( sqlite3_mutex_held(pPage->pBt->mutex) );

-  assert( nCell>=0 && nCell<=MX_CELL(pPage->pBt) && MX_CELL(pPage->pBt)<=5460 );
+  assert( nCell>=0 && nCell<=MX_CELL(pPage->pBt) && MX_CELL(pPage->pBt)<=10921);

   assert( sqlite3PagerIswriteable(pPage->pDbPage) );
 
   /* Check that the page has just been zeroed by zeroPage() */
   assert( pPage->nCell==0 );
   assert( sqlite3PagerIswriteable(pPage->pDbPage) );
 
   /* Check that the page has just been zeroed by zeroPage() */
   assert( pPage->nCell==0 );

-  assert( get2byte(&data[hdr+5])==nUsable );
+  assert( get2byteNotZero(&data[hdr+5])==nUsable );

 
   pCellptr = &data[pPage->cellOffset + nCell*2];
   cellbody = nUsable;
 
   pCellptr = &data[pPage->cellOffset + nCell*2];
   cellbody = nUsable;


@@ -49229,6 +50100,7 @@ static int balance_quick(MemPage *pParent, MemPage *pPage, u8 *pSpace){
   assert( sqlite3PagerIswriteable(pParent->pDbPage) );
   assert( pPage->nOverflow==1 );
 
   assert( sqlite3PagerIswriteable(pParent->pDbPage) );
   assert( pPage->nOverflow==1 );
 

+  /* This error condition is now caught prior to reaching this function */

   if( pPage->nCell<=0 ) return SQLITE_CORRUPT_BKPT;
 
   /* Allocate a new page. This page will become the right-sibling of 
   if( pPage->nCell<=0 ) return SQLITE_CORRUPT_BKPT;
 
   /* Allocate a new page. This page will become the right-sibling of 


@@ -49558,7 +50430,7 @@ static int balance_nonroot(
       ** is allocated.  */
       if( pBt->secureDelete ){
         int iOff = SQLITE_PTR_TO_INT(apDiv[i]) - SQLITE_PTR_TO_INT(pParent->aData);
       ** is allocated.  */
       if( pBt->secureDelete ){
         int iOff = SQLITE_PTR_TO_INT(apDiv[i]) - SQLITE_PTR_TO_INT(pParent->aData);

-        if( (iOff+szNew[i])>pBt->usableSize ){
+        if( (iOff+szNew[i])>(int)pBt->usableSize ){

           rc = SQLITE_CORRUPT_BKPT;
           memset(apOld, 0, (i+1)*sizeof(MemPage*));
           goto balance_cleanup;
           rc = SQLITE_CORRUPT_BKPT;
           memset(apOld, 0, (i+1)*sizeof(MemPage*));
           goto balance_cleanup;


@@ -49637,7 +50509,7 @@ static int balance_nonroot(
       szCell[nCell] = sz;
       pTemp = &aSpace1[iSpace1];
       iSpace1 += sz;
       szCell[nCell] = sz;
       pTemp = &aSpace1[iSpace1];
       iSpace1 += sz;

-      assert( sz<=pBt->pageSize/4 );
+      assert( sz<=pBt->maxLocal+23 );

       assert( iSpace1<=pBt->pageSize );
       memcpy(pTemp, apDiv[i], sz);
       apCell[nCell] = pTemp+leafCorrection;
       assert( iSpace1<=pBt->pageSize );
       memcpy(pTemp, apDiv[i], sz);
       apCell[nCell] = pTemp+leafCorrection;


@@ -49883,7 +50755,7 @@ static int balance_nonroot(
         }
       }
       iOvflSpace += sz;
         }
       }
       iOvflSpace += sz;

-      assert( sz<=pBt->pageSize/4 );
+      assert( sz<=pBt->maxLocal+23 );

       assert( iOvflSpace<=pBt->pageSize );
       insertCell(pParent, nxDiv, pCell, sz, pTemp, pNew->pgno, &rc);
       if( rc!=SQLITE_OK ) goto balance_cleanup;
       assert( iOvflSpace<=pBt->pageSize );
       insertCell(pParent, nxDiv, pCell, sz, pTemp, pNew->pgno, &rc);
       if( rc!=SQLITE_OK ) goto balance_cleanup;


@@ -51127,7 +51999,7 @@ static void checkList(
         checkPtrmap(pCheck, iPage, PTRMAP_FREEPAGE, 0, zContext);
       }
 #endif
         checkPtrmap(pCheck, iPage, PTRMAP_FREEPAGE, 0, zContext);
       }
 #endif

-      if( n>pCheck->pBt->usableSize/4-2 ){
+      if( n>(int)pCheck->pBt->usableSize/4-2 ){

         checkAppendMsg(pCheck, zContext,
            "freelist leaf count too big on page %d", iPage);
         N--;
         checkAppendMsg(pCheck, zContext,
            "freelist leaf count too big on page %d", iPage);
         N--;


@@ -51338,7 +52210,7 @@ static int checkTreePage(
   if( hit==0 ){
     pCheck->mallocFailed = 1;
   }else{
   if( hit==0 ){
     pCheck->mallocFailed = 1;
   }else{

-    u16 contentOffset = get2byte(&data[hdr+5]);
+    int contentOffset = get2byteNotZero(&data[hdr+5]);

     assert( contentOffset<=usableSize );  /* Enforced by btreeInitPage() */
     memset(hit+contentOffset, 0, usableSize-contentOffset);
     memset(hit, 1, contentOffset);
     assert( contentOffset<=usableSize );  /* Enforced by btreeInitPage() */
     memset(hit+contentOffset, 0, usableSize-contentOffset);
     memset(hit, 1, contentOffset);


@@ -51346,12 +52218,12 @@ static int checkTreePage(
     cellStart = hdr + 12 - 4*pPage->leaf;
     for(i=0; i<nCell; i++){
       int pc = get2byte(&data[cellStart+i*2]);
     cellStart = hdr + 12 - 4*pPage->leaf;
     for(i=0; i<nCell; i++){
       int pc = get2byte(&data[cellStart+i*2]);

-      u16 size = 1024;
+      u32 size = 65536;

       int j;
       if( pc<=usableSize-4 ){
         size = cellSizePtr(pPage, &data[pc]);
       }
       int j;
       if( pc<=usableSize-4 ){
         size = cellSizePtr(pPage, &data[pc]);
       }

-      if( (pc+size-1)>=usableSize ){
+      if( (int)(pc+size-1)>=usableSize ){

         checkAppendMsg(pCheck, 0, 
             "Corruption detected in cell %d on page %d",i,iPage);
       }else{
         checkAppendMsg(pCheck, 0, 
             "Corruption detected in cell %d on page %d",i,iPage);
       }else{


@@ -51444,6 +52316,7 @@ SQLITE_PRIVATE char *sqlite3BtreeIntegrityCheck(
     sCheck.anRef[i] = 1;
   }
   sqlite3StrAccumInit(&sCheck.errMsg, zErr, sizeof(zErr), 20000);
     sCheck.anRef[i] = 1;
   }
   sqlite3StrAccumInit(&sCheck.errMsg, zErr, sizeof(zErr), 20000);

+  sCheck.errMsg.useMalloc = 2;

 
   /* Check the integrity of the freelist
   */
 
   /* Check the integrity of the freelist
   */


@@ -51542,6 +52415,29 @@ SQLITE_PRIVATE int sqlite3BtreeIsInTrans(Btree *p){
   return (p && (p->inTrans==TRANS_WRITE));
 }
 
   return (p && (p->inTrans==TRANS_WRITE));
 }
 

+#ifndef SQLITE_OMIT_WAL
+/*
+** Run a checkpoint on the Btree passed as the first argument.
+**
+** Return SQLITE_LOCKED if this or any other connection has an open 
+** transaction on the shared-cache the argument Btree is connected to.
+*/
+SQLITE_PRIVATE int sqlite3BtreeCheckpoint(Btree *p){
+  int rc = SQLITE_OK;
+  if( p ){
+    BtShared *pBt = p->pBt;
+    sqlite3BtreeEnter(p);
+    if( pBt->inTransaction!=TRANS_NONE ){
+      rc = SQLITE_LOCKED;
+    }else{
+      rc = sqlite3PagerCheckpoint(pBt->pPager);
+    }
+    sqlite3BtreeLeave(p);
+  }
+  return rc;
+}
+#endif
+

 /*
 ** Return non-zero if a read (or write) transaction is active.
 */
 /*
 ** Return non-zero if a read (or write) transaction is active.
 */


@@ -51581,7 +52477,7 @@ SQLITE_PRIVATE void *sqlite3BtreeSchema(Btree *p, int nBytes, void(*xFree)(void
   BtShared *pBt = p->pBt;
   sqlite3BtreeEnter(p);
   if( !pBt->pSchema && nBytes ){
   BtShared *pBt = p->pBt;
   sqlite3BtreeEnter(p);
   if( !pBt->pSchema && nBytes ){

-    pBt->pSchema = sqlite3MallocZero(nBytes);
+    pBt->pSchema = sqlite3DbMallocZero(0, nBytes);

     pBt->xFreeSchema = xFree;
   }
   sqlite3BtreeLeave(p);
     pBt->xFreeSchema = xFree;
   }
   sqlite3BtreeLeave(p);


@@ -51951,6 +52847,15 @@ static int backupOnePage(sqlite3_backup *p, Pgno iSrcPg, const u8 *zSrcData){
     rc = SQLITE_READONLY;
   }
 
     rc = SQLITE_READONLY;
   }
 

+#ifdef SQLITE_HAS_CODEC
+  /* Backup is not possible if the page size of the destination is changing
+  ** a a codec is in use.
+  */
+  if( nSrcPgsz!=nDestPgsz && sqlite3PagerGetCodec(pDestPager)!=0 ){
+    rc = SQLITE_READONLY;
+  }
+#endif
+

   /* This loop runs once for each destination page spanned by the source 
   ** page. For each iteration, variable iOff is set to the byte offset
   ** of the destination page.
   /* This loop runs once for each destination page spanned by the source 
   ** page. For each iteration, variable iOff is set to the byte offset
   ** of the destination page.


@@ -53389,7 +54294,7 @@ SQLITE_PRIVATE int sqlite3ValueFromExpr(
   }
   op = pExpr->op;
 
   }
   op = pExpr->op;
 

-  /* op can only be TK_REGISTER is we have compiled with SQLITE_ENABLE_STAT2.
+  /* op can only be TK_REGISTER if we have compiled with SQLITE_ENABLE_STAT2.

   ** The ifdef here is to enable us to achieve 100% branch test coverage even
   ** when SQLITE_ENABLE_STAT2 is omitted.
   */
   ** The ifdef here is to enable us to achieve 100% branch test coverage even
   ** when SQLITE_ENABLE_STAT2 is omitted.
   */


@@ -54067,15 +54972,17 @@ static void freeEphemeralFunction(sqlite3 *db, FuncDef *pDef){
   }
 }
 
   }
 }
 

+static void vdbeFreeOpArray(sqlite3 *, Op *, int);
+

 /*
 ** Delete a P4 value if necessary.
 */
 static void freeP4(sqlite3 *db, int p4type, void *p4){
   if( p4 ){
 /*
 ** Delete a P4 value if necessary.
 */
 static void freeP4(sqlite3 *db, int p4type, void *p4){
   if( p4 ){

+    assert( db );

     switch( p4type ){
       case P4_REAL:
       case P4_INT64:
     switch( p4type ){
       case P4_REAL:
       case P4_INT64:

-      case P4_MPRINTF:

       case P4_DYNAMIC:
       case P4_KEYINFO:
       case P4_INTARRAY:
       case P4_DYNAMIC:
       case P4_KEYINFO:
       case P4_INTARRAY:


@@ -54083,10 +54990,14 @@ static void freeP4(sqlite3 *db, int p4type, void *p4){
         sqlite3DbFree(db, p4);
         break;
       }
         sqlite3DbFree(db, p4);
         break;
       }

+      case P4_MPRINTF: {
+        if( db->pnBytesFreed==0 ) sqlite3_free(p4);
+        break;
+      }

       case P4_VDBEFUNC: {
         VdbeFunc *pVdbeFunc = (VdbeFunc *)p4;
         freeEphemeralFunction(db, pVdbeFunc->pFunc);
       case P4_VDBEFUNC: {
         VdbeFunc *pVdbeFunc = (VdbeFunc *)p4;
         freeEphemeralFunction(db, pVdbeFunc->pFunc);

-        sqlite3VdbeDeleteAuxData(pVdbeFunc, 0);
+        if( db->pnBytesFreed==0 ) sqlite3VdbeDeleteAuxData(pVdbeFunc, 0);

         sqlite3DbFree(db, pVdbeFunc);
         break;
       }
         sqlite3DbFree(db, pVdbeFunc);
         break;
       }


@@ -54095,15 +55006,17 @@ static void freeP4(sqlite3 *db, int p4type, void *p4){
         break;
       }
       case P4_MEM: {
         break;
       }
       case P4_MEM: {

-        sqlite3ValueFree((sqlite3_value*)p4);
+        if( db->pnBytesFreed==0 ){
+          sqlite3ValueFree((sqlite3_value*)p4);
+        }else{
+          Mem *p = (Mem*)p4;
+          sqlite3DbFree(db, p->zMalloc);
+          sqlite3DbFree(db, p);
+        }

         break;
       }
       case P4_VTAB : {
         break;
       }
       case P4_VTAB : {

-        sqlite3VtabUnlock((VTable *)p4);
-        break;
-      }
-      case P4_SUBPROGRAM : {
-        sqlite3VdbeProgramDelete(db, (SubProgram *)p4, 1);
+        if( db->pnBytesFreed==0 ) sqlite3VtabUnlock((VTable *)p4);

         break;
       }
     }
         break;
       }
     }


@@ -54129,35 +55042,15 @@ static void vdbeFreeOpArray(sqlite3 *db, Op *aOp, int nOp){
 }
 
 /*
 }
 
 /*

-** Decrement the ref-count on the SubProgram structure passed as the
-** second argument. If the ref-count reaches zero, free the structure.
-**
-** The array of VDBE opcodes stored as SubProgram.aOp is freed if
-** either the ref-count reaches zero or parameter freeop is non-zero.
-**
-** Since the array of opcodes pointed to by SubProgram.aOp may directly
-** or indirectly contain a reference to the SubProgram structure itself.
-** By passing a non-zero freeop parameter, the caller may ensure that all
-** SubProgram structures and their aOp arrays are freed, even when there
-** are such circular references.
+** Link the SubProgram object passed as the second argument into the linked
+** list at Vdbe.pSubProgram. This list is used to delete all sub-program
+** objects when the VM is no longer required.

 */
 */

-SQLITE_PRIVATE void sqlite3VdbeProgramDelete(sqlite3 *db, SubProgram *p, int freeop){
-  if( p ){
-    assert( p->nRef>0 );
-    if( freeop || p->nRef==1 ){
-      Op *aOp = p->aOp;
-      p->aOp = 0;
-      vdbeFreeOpArray(db, aOp, p->nOp);
-      p->nOp = 0;
-    }
-    p->nRef--;
-    if( p->nRef==0 ){
-      sqlite3DbFree(db, p);
-    }
-  }
+SQLITE_PRIVATE void sqlite3VdbeLinkSubProgram(Vdbe *pVdbe, SubProgram *p){
+  p->pNext = pVdbe->pProgram;
+  pVdbe->pProgram = p;

 }
 
 }
 

-

 /*
 ** Change N opcodes starting at addr to No-ops.
 */
 /*
 ** Change N opcodes starting at addr to No-ops.
 */


@@ -54233,7 +55126,7 @@ SQLITE_PRIVATE void sqlite3VdbeChangeP4(Vdbe *p, int addr, const char *zP4, int
 
     nField = ((KeyInfo*)zP4)->nField;
     nByte = sizeof(*pKeyInfo) + (nField-1)*sizeof(pKeyInfo->aColl[0]) + nField;
 
     nField = ((KeyInfo*)zP4)->nField;
     nByte = sizeof(*pKeyInfo) + (nField-1)*sizeof(pKeyInfo->aColl[0]) + nField;

-    pKeyInfo = sqlite3Malloc( nByte );
+    pKeyInfo = sqlite3DbMallocRaw(0, nByte);

     pOp->p4.pKeyInfo = pKeyInfo;
     if( pKeyInfo ){
       u8 *aSortOrder;
     pOp->p4.pKeyInfo = pKeyInfo;
     if( pKeyInfo ){
       u8 *aSortOrder;


@@ -54497,6 +55390,12 @@ static void releaseMemArray(Mem *p, int N){
     Mem *pEnd;
     sqlite3 *db = p->db;
     u8 malloc_failed = db->mallocFailed;
     Mem *pEnd;
     sqlite3 *db = p->db;
     u8 malloc_failed = db->mallocFailed;

+    if( db->pnBytesFreed ){
+      for(pEnd=&p[N]; p<pEnd; p++){
+        sqlite3DbFree(db, p->zMalloc);
+      }
+      return;
+    }

     for(pEnd=&p[N]; p<pEnd; p++){
       assert( (&p[1])==pEnd || p[0].db==p[1].db );
 
     for(pEnd=&p[N]; p<pEnd; p++){
       assert( (&p[1])==pEnd || p[0].db==p[1].db );
 


@@ -55146,9 +56045,6 @@ static int vdbeCommit(sqlite3 *db, Vdbe *p){
   ** to the transaction.
   */
   rc = sqlite3VtabSync(db, &p->zErrMsg);
   ** to the transaction.
   */
   rc = sqlite3VtabSync(db, &p->zErrMsg);

-  if( rc!=SQLITE_OK ){
-    return rc;
-  }

 
   /* This loop determines (a) if the commit hook should be invoked and
   ** (b) how many database files have open write transactions, not 
 
   /* This loop determines (a) if the commit hook should be invoked and
   ** (b) how many database files have open write transactions, not 


@@ -55156,13 +56052,17 @@ static int vdbeCommit(sqlite3 *db, Vdbe *p){
   ** one database file has an open write transaction, a master journal
   ** file is required for an atomic commit.
   */ 
   ** one database file has an open write transaction, a master journal
   ** file is required for an atomic commit.
   */ 

-  for(i=0; i<db->nDb; i++){ 
+  for(i=0; rc==SQLITE_OK && i<db->nDb; i++){ 

     Btree *pBt = db->aDb[i].pBt;
     if( sqlite3BtreeIsInTrans(pBt) ){
       needXcommit = 1;
       if( i!=1 ) nTrans++;
     Btree *pBt = db->aDb[i].pBt;
     if( sqlite3BtreeIsInTrans(pBt) ){
       needXcommit = 1;
       if( i!=1 ) nTrans++;

+      rc = sqlite3PagerExclusiveLock(sqlite3BtreePager(pBt));

     }
   }
     }
   }

+  if( rc!=SQLITE_OK ){
+    return rc;
+  }

 
   /* If there are any write-transactions at all, invoke the commit hook */
   if( needXcommit && db->xCommitCallback ){
 
   /* If there are any write-transactions at all, invoke the commit hook */
   if( needXcommit && db->xCommitCallback ){


@@ -55301,6 +56201,7 @@ static int vdbeCommit(sqlite3 *db, Vdbe *p){
       }
     }
     sqlite3OsCloseFree(pMaster);
       }
     }
     sqlite3OsCloseFree(pMaster);

+    assert( rc!=SQLITE_BUSY );

     if( rc!=SQLITE_OK ){
       sqlite3DbFree(db, zMaster);
       return rc;
     if( rc!=SQLITE_OK ){
       sqlite3DbFree(db, zMaster);
       return rc;


@@ -55559,8 +56460,17 @@ SQLITE_PRIVATE int sqlite3VdbeHalt(Vdbe *p){
     isSpecialError = mrc==SQLITE_NOMEM || mrc==SQLITE_IOERR
                      || mrc==SQLITE_INTERRUPT || mrc==SQLITE_FULL;
     if( isSpecialError ){
     isSpecialError = mrc==SQLITE_NOMEM || mrc==SQLITE_IOERR
                      || mrc==SQLITE_INTERRUPT || mrc==SQLITE_FULL;
     if( isSpecialError ){

-      /* If the query was read-only, we need do no rollback at all. Otherwise,
-      ** proceed with the special handling.
+      /* If the query was read-only and the error code is SQLITE_INTERRUPT, 
+      ** no rollback is necessary. Otherwise, at least a savepoint 
+      ** transaction must be rolled back to restore the database to a 
+      ** consistent state.
+      **
+      ** Even if the statement is read-only, it is important to perform
+      ** a statement or transaction rollback operation. If the error 
+      ** occured while writing to the journal, sub-journal or database
+      ** file as part of an effort to free up cache space (see function
+      ** pagerStress() in pager.c), the rollback is required to restore 
+      ** the pager to a consistent state.

       */
       if( !p->readOnly || mrc!=SQLITE_INTERRUPT ){
         if( (mrc==SQLITE_NOMEM || mrc==SQLITE_FULL) && p->usesStmtJournal ){
       */
       if( !p->readOnly || mrc!=SQLITE_INTERRUPT ){
         if( (mrc==SQLITE_NOMEM || mrc==SQLITE_FULL) && p->usesStmtJournal ){


@@ -55829,6 +56739,30 @@ SQLITE_PRIVATE void sqlite3VdbeDeleteAuxData(VdbeFunc *pVdbeFunc, int mask){
   }
 }
 
   }
 }
 

+/*
+** Free all memory associated with the Vdbe passed as the second argument.
+** The difference between this function and sqlite3VdbeDelete() is that
+** VdbeDelete() also unlinks the Vdbe from the list of VMs associated with
+** the database connection.
+*/
+SQLITE_PRIVATE void sqlite3VdbeDeleteObject(sqlite3 *db, Vdbe *p){
+  SubProgram *pSub, *pNext;
+  assert( p->db==0 || p->db==db );
+  releaseMemArray(p->aVar, p->nVar);
+  releaseMemArray(p->aColName, p->nResColumn*COLNAME_N);
+  for(pSub=p->pProgram; pSub; pSub=pNext){
+    pNext = pSub->pNext;
+    vdbeFreeOpArray(db, pSub->aOp, pSub->nOp);
+    sqlite3DbFree(db, pSub);
+  }
+  vdbeFreeOpArray(db, p->aOp, p->nOp);
+  sqlite3DbFree(db, p->aLabel);
+  sqlite3DbFree(db, p->aColName);
+  sqlite3DbFree(db, p->zSql);
+  sqlite3DbFree(db, p->pFree);
+  sqlite3DbFree(db, p);
+}
+

 /*
 ** Delete an entire VDBE.
 */
 /*
 ** Delete an entire VDBE.
 */


@@ -55846,16 +56780,9 @@ SQLITE_PRIVATE void sqlite3VdbeDelete(Vdbe *p){
   if( p->pNext ){
     p->pNext->pPrev = p->pPrev;
   }
   if( p->pNext ){
     p->pNext->pPrev = p->pPrev;
   }

-  releaseMemArray(p->aVar, p->nVar);
-  releaseMemArray(p->aColName, p->nResColumn*COLNAME_N);
-  vdbeFreeOpArray(db, p->aOp, p->nOp);
-  sqlite3DbFree(db, p->aLabel);
-  sqlite3DbFree(db, p->aColName);
-  sqlite3DbFree(db, p->zSql);

   p->magic = VDBE_MAGIC_DEAD;
   p->magic = VDBE_MAGIC_DEAD;

-  sqlite3DbFree(db, p->pFree);

   p->db = 0;
   p->db = 0;

-  sqlite3DbFree(db, p);
+  sqlite3VdbeDeleteObject(db, p);

 }
 
 /*
 }
 
 /*


@@ -55881,11 +56808,8 @@ SQLITE_PRIVATE int sqlite3VdbeCursorMoveto(VdbeCursor *p){
     rc = sqlite3BtreeMovetoUnpacked(p->pCursor, 0, p->movetoTarget, 0, &res);
     if( rc ) return rc;
     p->lastRowid = p->movetoTarget;
     rc = sqlite3BtreeMovetoUnpacked(p->pCursor, 0, p->movetoTarget, 0, &res);
     if( rc ) return rc;
     p->lastRowid = p->movetoTarget;

-    p->rowidIsValid = ALWAYS(res==0) ?1:0;
-    if( NEVER(res<0) ){
-      rc = sqlite3BtreeNext(p->pCursor, &res);
-      if( rc ) return rc;
-    }
+    if( res!=0 ) return SQLITE_CORRUPT_BKPT;
+    p->rowidIsValid = 1;

 #ifdef SQLITE_TEST
     sqlite3_search_count++;
 #endif
 #ifdef SQLITE_TEST
     sqlite3_search_count++;
 #endif


@@ -57029,7 +57953,7 @@ static int sqlite3Step(Vdbe *p){
   if( rc!=SQLITE_ROW && db->xProfile && !db->init.busy && p->zSql ){
     sqlite3_int64 iNow;
     sqlite3OsCurrentTimeInt64(db->pVfs, &iNow);
   if( rc!=SQLITE_ROW && db->xProfile && !db->init.busy && p->zSql ){
     sqlite3_int64 iNow;
     sqlite3OsCurrentTimeInt64(db->pVfs, &iNow);

-    db->xProfile(db->pProfileArg, p->zSql, iNow - p->startTime);
+    db->xProfile(db->pProfileArg, p->zSql, (iNow - p->startTime)*1000000);

   }
 #endif
 
   }
 #endif
 


@@ -58645,6 +59569,20 @@ static int checkSavepointCount(sqlite3 *db){
 }
 #endif
 
 }
 #endif
 

+/*
+** Transfer error message text from an sqlite3_vtab.zErrMsg (text stored
+** in memory obtained from sqlite3_malloc) into a Vdbe.zErrMsg (text stored
+** in memory obtained from sqlite3DbMalloc).
+*/
+static void importVtabErrMsg(Vdbe *p, sqlite3_vtab *pVtab){
+  sqlite3 *db = p->db;
+  sqlite3DbFree(db, p->zErrMsg);
+  p->zErrMsg = sqlite3DbStrDup(db, pVtab->zErrMsg);
+  sqlite3_free(pVtab->zErrMsg);
+  pVtab->zErrMsg = 0;
+}
+
+

 /*
 ** Execute as much of a VDBE program as we can then return.
 **
 /*
 ** Execute as much of a VDBE program as we can then return.
 **


@@ -62643,9 +63581,7 @@ case OP_Rowid: {                 /* out2-prerelease */
     u.bi.pModule = u.bi.pVtab->pModule;
     assert( u.bi.pModule->xRowid );
     rc = u.bi.pModule->xRowid(u.bi.pC->pVtabCursor, &u.bi.v);
     u.bi.pModule = u.bi.pVtab->pModule;
     assert( u.bi.pModule->xRowid );
     rc = u.bi.pModule->xRowid(u.bi.pC->pVtabCursor, &u.bi.v);

-    sqlite3DbFree(db, p->zErrMsg);
-    p->zErrMsg = u.bi.pVtab->zErrMsg;
-    u.bi.pVtab->zErrMsg = 0;
+    importVtabErrMsg(p, u.bi.pVtab);

 #endif /* SQLITE_OMIT_VIRTUALTABLE */
   }else{
     assert( u.bi.pC->pCursor!=0 );
 #endif /* SQLITE_OMIT_VIRTUALTABLE */
   }else{
     assert( u.bi.pC->pCursor!=0 );


@@ -62964,7 +63900,7 @@ case OP_IdxRowid: {              /* out2-prerelease */
 ** that if the key from register P3 is a prefix of the key in the cursor,
 ** the result is false whereas it would be true with IdxGT.
 */
 ** that if the key from register P3 is a prefix of the key in the cursor,
 ** the result is false whereas it would be true with IdxGT.
 */

-/* Opcode: IdxLT P1 P2 P3 * P5
+/* Opcode: IdxLT P1 P2 P3 P4 P5

 **
 ** The P4 register values beginning with P3 form an unpacked index 
 ** key that omits the ROWID.  Compare this key value against the index 
 **
 ** The P4 register values beginning with P3 form an unpacked index 
 ** key that omits the ROWID.  Compare this key value against the index 


@@ -64034,11 +64970,7 @@ case OP_VBegin: {
 #endif /* local variables moved into u.cf */
   u.cf.pVTab = pOp->p4.pVtab;
   rc = sqlite3VtabBegin(db, u.cf.pVTab);
 #endif /* local variables moved into u.cf */
   u.cf.pVTab = pOp->p4.pVtab;
   rc = sqlite3VtabBegin(db, u.cf.pVTab);

-  if( u.cf.pVTab ){
-    sqlite3DbFree(db, p->zErrMsg);
-    p->zErrMsg = u.cf.pVTab->pVtab->zErrMsg;
-    u.cf.pVTab->pVtab->zErrMsg = 0;
-  }
+  if( u.cf.pVTab ) importVtabErrMsg(p, u.cf.pVTab->pVtab);

   break;
 }
 #endif /* SQLITE_OMIT_VIRTUALTABLE */
   break;
 }
 #endif /* SQLITE_OMIT_VIRTUALTABLE */


@@ -64090,9 +65022,7 @@ case OP_VOpen: {
   u.cg.pModule = (sqlite3_module *)u.cg.pVtab->pModule;
   assert(u.cg.pVtab && u.cg.pModule);
   rc = u.cg.pModule->xOpen(u.cg.pVtab, &u.cg.pVtabCursor);
   u.cg.pModule = (sqlite3_module *)u.cg.pVtab->pModule;
   assert(u.cg.pVtab && u.cg.pModule);
   rc = u.cg.pModule->xOpen(u.cg.pVtab, &u.cg.pVtabCursor);

-  sqlite3DbFree(db, p->zErrMsg);
-  p->zErrMsg = u.cg.pVtab->zErrMsg;
-  u.cg.pVtab->zErrMsg = 0;
+  importVtabErrMsg(p, u.cg.pVtab);

   if( SQLITE_OK==rc ){
     /* Initialize sqlite3_vtab_cursor base class */
     u.cg.pVtabCursor->pVtab = u.cg.pVtab;
   if( SQLITE_OK==rc ){
     /* Initialize sqlite3_vtab_cursor base class */
     u.cg.pVtabCursor->pVtab = u.cg.pVtab;


@@ -64171,9 +65101,7 @@ case OP_VFilter: {   /* jump */
     p->inVtabMethod = 1;
     rc = u.ch.pModule->xFilter(u.ch.pVtabCursor, u.ch.iQuery, pOp->p4.z, u.ch.nArg, u.ch.apArg);
     p->inVtabMethod = 0;
     p->inVtabMethod = 1;
     rc = u.ch.pModule->xFilter(u.ch.pVtabCursor, u.ch.iQuery, pOp->p4.z, u.ch.nArg, u.ch.apArg);
     p->inVtabMethod = 0;

-    sqlite3DbFree(db, p->zErrMsg);
-    p->zErrMsg = u.ch.pVtab->zErrMsg;
-    u.ch.pVtab->zErrMsg = 0;
+    importVtabErrMsg(p, u.ch.pVtab);

     if( rc==SQLITE_OK ){
       u.ch.res = u.ch.pModule->xEof(u.ch.pVtabCursor);
     }
     if( rc==SQLITE_OK ){
       u.ch.res = u.ch.pModule->xEof(u.ch.pVtabCursor);
     }


@@ -64225,9 +65153,7 @@ case OP_VColumn: {
   MemSetTypeFlag(&u.ci.sContext.s, MEM_Null);
 
   rc = u.ci.pModule->xColumn(pCur->pVtabCursor, &u.ci.sContext, pOp->p2);
   MemSetTypeFlag(&u.ci.sContext.s, MEM_Null);
 
   rc = u.ci.pModule->xColumn(pCur->pVtabCursor, &u.ci.sContext, pOp->p2);

-  sqlite3DbFree(db, p->zErrMsg);
-  p->zErrMsg = u.ci.pVtab->zErrMsg;
-  u.ci.pVtab->zErrMsg = 0;
+  importVtabErrMsg(p, u.ci.pVtab);

   if( u.ci.sContext.isError ){
     rc = u.ci.sContext.isError;
   }
   if( u.ci.sContext.isError ){
     rc = u.ci.sContext.isError;
   }


@@ -64282,9 +65208,7 @@ case OP_VNext: {   /* jump */
   p->inVtabMethod = 1;
   rc = u.cj.pModule->xNext(u.cj.pCur->pVtabCursor);
   p->inVtabMethod = 0;
   p->inVtabMethod = 1;
   rc = u.cj.pModule->xNext(u.cj.pCur->pVtabCursor);
   p->inVtabMethod = 0;

-  sqlite3DbFree(db, p->zErrMsg);
-  p->zErrMsg = u.cj.pVtab->zErrMsg;
-  u.cj.pVtab->zErrMsg = 0;
+  importVtabErrMsg(p, u.cj.pVtab);

   if( rc==SQLITE_OK ){
     u.cj.res = u.cj.pModule->xEof(u.cj.pCur->pVtabCursor);
   }
   if( rc==SQLITE_OK ){
     u.cj.res = u.cj.pModule->xEof(u.cj.pCur->pVtabCursor);
   }


@@ -64316,9 +65240,7 @@ case OP_VRename: {
   REGISTER_TRACE(pOp->p1, u.ck.pName);
   assert( u.ck.pName->flags & MEM_Str );
   rc = u.ck.pVtab->pModule->xRename(u.ck.pVtab, u.ck.pName->z);
   REGISTER_TRACE(pOp->p1, u.ck.pName);
   assert( u.ck.pName->flags & MEM_Str );
   rc = u.ck.pVtab->pModule->xRename(u.ck.pVtab, u.ck.pName->z);

-  sqlite3DbFree(db, p->zErrMsg);
-  p->zErrMsg = u.ck.pVtab->zErrMsg;
-  u.ck.pVtab->zErrMsg = 0;
+  importVtabErrMsg(p, u.ck.pVtab);

 
   break;
 }
 
   break;
 }


@@ -64372,9 +65294,7 @@ case OP_VUpdate: {
       u.cl.pX++;
     }
     rc = u.cl.pModule->xUpdate(u.cl.pVtab, u.cl.nArg, u.cl.apArg, &u.cl.rowid);
       u.cl.pX++;
     }
     rc = u.cl.pModule->xUpdate(u.cl.pVtab, u.cl.nArg, u.cl.apArg, &u.cl.rowid);

-    sqlite3DbFree(db, p->zErrMsg);
-    p->zErrMsg = u.cl.pVtab->zErrMsg;
-    u.cl.pVtab->zErrMsg = 0;
+    importVtabErrMsg(p, u.cl.pVtab);

     if( rc==SQLITE_OK && pOp->p1 ){
       assert( u.cl.nArg>1 && u.cl.apArg[0] && (u.cl.apArg[0]->flags&MEM_Null) );
       db->lastRowid = u.cl.rowid;
     if( rc==SQLITE_OK && pOp->p1 ){
       assert( u.cl.nArg>1 && u.cl.apArg[0] && (u.cl.apArg[0]->flags&MEM_Null) );
       db->lastRowid = u.cl.rowid;


@@ -66828,6 +67748,18 @@ SQLITE_PRIVATE char sqlite3ExprAffinity(Expr *pExpr){
   return pExpr->affinity;
 }
 
   return pExpr->affinity;
 }
 

+/*
+** Set the explicit collating sequence for an expression to the
+** collating sequence supplied in the second argument.
+*/
+SQLITE_PRIVATE Expr *sqlite3ExprSetColl(Expr *pExpr, CollSeq *pColl){
+  if( pExpr && pColl ){
+    pExpr->pColl = pColl;
+    pExpr->flags |= EP_ExpCollate;
+  }
+  return pExpr;
+}
+

 /*
 ** Set the collating sequence for expression pExpr to be the collating
 ** sequence named by pToken.   Return a pointer to the revised expression.
 /*
 ** Set the collating sequence for expression pExpr to be the collating
 ** sequence named by pToken.   Return a pointer to the revised expression.


@@ -66835,18 +67767,13 @@ SQLITE_PRIVATE char sqlite3ExprAffinity(Expr *pExpr){
 ** flag.  An explicit collating sequence will override implicit
 ** collating sequences.
 */
 ** flag.  An explicit collating sequence will override implicit
 ** collating sequences.
 */

-SQLITE_PRIVATE Expr *sqlite3ExprSetColl(Parse *pParse, Expr *pExpr, Token *pCollName){
+SQLITE_PRIVATE Expr *sqlite3ExprSetCollByToken(Parse *pParse, Expr *pExpr, Token *pCollName){

   char *zColl = 0;            /* Dequoted name of collation sequence */
   CollSeq *pColl;
   sqlite3 *db = pParse->db;
   zColl = sqlite3NameFromToken(db, pCollName);
   char *zColl = 0;            /* Dequoted name of collation sequence */
   CollSeq *pColl;
   sqlite3 *db = pParse->db;
   zColl = sqlite3NameFromToken(db, pCollName);

-  if( pExpr && zColl ){
-    pColl = sqlite3LocateCollSeq(pParse, zColl);
-    if( pColl ){
-      pExpr->pColl = pColl;
-      pExpr->flags |= EP_ExpCollate;
-    }
-  }
+  pColl = sqlite3LocateCollSeq(pParse, zColl);
+  sqlite3ExprSetColl(pExpr, pColl);

   sqlite3DbFree(db, zColl);
   return pExpr;
 }
   sqlite3DbFree(db, zColl);
   return pExpr;
 }


@@ -67320,18 +68247,19 @@ SQLITE_PRIVATE void sqlite3ExprAssignVarNumber(Parse *pParse, Expr *pExpr){
   }else if( z[0]=='?' ){
     /* Wildcard of the form "?nnn".  Convert "nnn" to an integer and
     ** use it as the variable number */
   }else if( z[0]=='?' ){
     /* Wildcard of the form "?nnn".  Convert "nnn" to an integer and
     ** use it as the variable number */

-    int i = atoi((char*)&z[1]);
+    i64 i;
+    int bOk = sqlite3Atoi64(&z[1], &i);

     pExpr->iColumn = (ynVar)i;
     testcase( i==0 );
     testcase( i==1 );
     testcase( i==db->aLimit[SQLITE_LIMIT_VARIABLE_NUMBER]-1 );
     testcase( i==db->aLimit[SQLITE_LIMIT_VARIABLE_NUMBER] );
     pExpr->iColumn = (ynVar)i;
     testcase( i==0 );
     testcase( i==1 );
     testcase( i==db->aLimit[SQLITE_LIMIT_VARIABLE_NUMBER]-1 );
     testcase( i==db->aLimit[SQLITE_LIMIT_VARIABLE_NUMBER] );

-    if( i<1 || i>db->aLimit[SQLITE_LIMIT_VARIABLE_NUMBER] ){
+    if( bOk==0 || i<1 || i>db->aLimit[SQLITE_LIMIT_VARIABLE_NUMBER] ){

       sqlite3ErrorMsg(pParse, "variable number must be between ?1 and ?%d",
           db->aLimit[SQLITE_LIMIT_VARIABLE_NUMBER]);
     }
     if( i>pParse->nVar ){
       sqlite3ErrorMsg(pParse, "variable number must be between ?1 and ?%d",
           db->aLimit[SQLITE_LIMIT_VARIABLE_NUMBER]);
     }
     if( i>pParse->nVar ){

-      pParse->nVar = i;
+      pParse->nVar = (int)i;

     }
   }else{
     /* Wildcards like ":aaa", "$aaa" or "@aaa".  Reuse the same variable
     }
   }else{
     /* Wildcards like ":aaa", "$aaa" or "@aaa".  Reuse the same variable


@@ -71324,7 +72252,6 @@ SQLITE_PRIVATE void sqlite3AlterBeginAddColumn(Parse *pParse, SrcList *pSrc){
   if( !pNew ) goto exit_begin_add_column;
   pParse->pNewTable = pNew;
   pNew->nRef = 1;
   if( !pNew ) goto exit_begin_add_column;
   pParse->pNewTable = pNew;
   pNew->nRef = 1;

-  pNew->dbMem = pTab->dbMem;

   pNew->nCol = pTab->nCol;
   assert( pNew->nCol>0 );
   nAlloc = (((pNew->nCol-1)/8)*8)+8;
   pNew->nCol = pTab->nCol;
   assert( pNew->nCol>0 );
   nAlloc = (((pNew->nCol-1)/8)*8)+8;


@@ -71853,21 +72780,20 @@ static int analysisLoader(void *pData, int argc, char **argv, char **NotUsed){
 ** If the Index.aSample variable is not NULL, delete the aSample[] array
 ** and its contents.
 */
 ** If the Index.aSample variable is not NULL, delete the aSample[] array
 ** and its contents.
 */

-SQLITE_PRIVATE void sqlite3DeleteIndexSamples(Index *pIdx){
+SQLITE_PRIVATE void sqlite3DeleteIndexSamples(sqlite3 *db, Index *pIdx){

 #ifdef SQLITE_ENABLE_STAT2
   if( pIdx->aSample ){
     int j;
 #ifdef SQLITE_ENABLE_STAT2
   if( pIdx->aSample ){
     int j;

-    sqlite3 *dbMem = pIdx->pTable->dbMem;

     for(j=0; j<SQLITE_INDEX_SAMPLES; j++){
       IndexSample *p = &pIdx->aSample[j];
       if( p->eType==SQLITE_TEXT || p->eType==SQLITE_BLOB ){
     for(j=0; j<SQLITE_INDEX_SAMPLES; j++){
       IndexSample *p = &pIdx->aSample[j];
       if( p->eType==SQLITE_TEXT || p->eType==SQLITE_BLOB ){

-        sqlite3DbFree(pIdx->pTable->dbMem, p->u.z);
+        sqlite3DbFree(db, p->u.z);

       }
     }
       }
     }

-    sqlite3DbFree(dbMem, pIdx->aSample);
-    pIdx->aSample = 0;
+    sqlite3DbFree(db, pIdx->aSample);

   }
 #else
   }
 #else

+  UNUSED_PARAMETER(db);

   UNUSED_PARAMETER(pIdx);
 #endif
 }
   UNUSED_PARAMETER(pIdx);
 #endif
 }


@@ -71906,7 +72832,8 @@ SQLITE_PRIVATE int sqlite3AnalysisLoad(sqlite3 *db, int iDb){
   for(i=sqliteHashFirst(&db->aDb[iDb].pSchema->idxHash);i;i=sqliteHashNext(i)){
     Index *pIdx = sqliteHashData(i);
     sqlite3DefaultRowEst(pIdx);
   for(i=sqliteHashFirst(&db->aDb[iDb].pSchema->idxHash);i;i=sqliteHashNext(i)){
     Index *pIdx = sqliteHashData(i);
     sqlite3DefaultRowEst(pIdx);

-    sqlite3DeleteIndexSamples(pIdx);
+    sqlite3DeleteIndexSamples(db, pIdx);
+    pIdx->aSample = 0;

   }
 
   /* Check to make sure the sqlite_stat1 table exists */
   }
 
   /* Check to make sure the sqlite_stat1 table exists */


@@ -71950,18 +72877,17 @@ SQLITE_PRIVATE int sqlite3AnalysisLoad(sqlite3 *db, int iDb){
         Index *pIdx = sqlite3FindIndex(db, zIndex, sInfo.zDatabase);
         if( pIdx ){
           int iSample = sqlite3_column_int(pStmt, 1);
         Index *pIdx = sqlite3FindIndex(db, zIndex, sInfo.zDatabase);
         if( pIdx ){
           int iSample = sqlite3_column_int(pStmt, 1);

-          sqlite3 *dbMem = pIdx->pTable->dbMem;
-          assert( dbMem==db || dbMem==0 );

           if( iSample<SQLITE_INDEX_SAMPLES && iSample>=0 ){
             int eType = sqlite3_column_type(pStmt, 2);
 
             if( pIdx->aSample==0 ){
               static const int sz = sizeof(IndexSample)*SQLITE_INDEX_SAMPLES;
           if( iSample<SQLITE_INDEX_SAMPLES && iSample>=0 ){
             int eType = sqlite3_column_type(pStmt, 2);
 
             if( pIdx->aSample==0 ){
               static const int sz = sizeof(IndexSample)*SQLITE_INDEX_SAMPLES;

-              pIdx->aSample = (IndexSample *)sqlite3DbMallocZero(dbMem, sz);
+              pIdx->aSample = (IndexSample *)sqlite3DbMallocRaw(0, sz);

               if( pIdx->aSample==0 ){
                 db->mallocFailed = 1;
                 break;
               }
               if( pIdx->aSample==0 ){
                 db->mallocFailed = 1;
                 break;
               }

+             memset(pIdx->aSample, 0, sz);

             }
 
             assert( pIdx->aSample );
             }
 
             assert( pIdx->aSample );


@@ -71984,10 +72910,8 @@ SQLITE_PRIVATE int sqlite3AnalysisLoad(sqlite3 *db, int iDb){
                 if( n < 1){
                   pSample->u.z = 0;
                 }else{
                 if( n < 1){
                   pSample->u.z = 0;
                 }else{

-                  pSample->u.z = sqlite3DbMallocRaw(dbMem, n);
-                  if( pSample->u.z ){
-                    memcpy(pSample->u.z, z, n);
-                  }else{
+                  pSample->u.z = sqlite3DbStrNDup(0, z, n);
+                  if( pSample->u.z==0 ){

                     db->mallocFailed = 1;
                     break;
                   }
                     db->mallocFailed = 1;
                     break;
                   }


@@ -73150,33 +74074,14 @@ SQLITE_PRIVATE Index *sqlite3FindIndex(sqlite3 *db, const char *zName, const cha
 /*
 ** Reclaim the memory used by an index
 */
 /*
 ** Reclaim the memory used by an index
 */

-static void freeIndex(Index *p){
-  sqlite3 *db = p->pTable->dbMem;
+static void freeIndex(sqlite3 *db, Index *p){

 #ifndef SQLITE_OMIT_ANALYZE
 #ifndef SQLITE_OMIT_ANALYZE

-  sqlite3DeleteIndexSamples(p);
+  sqlite3DeleteIndexSamples(db, p);

 #endif
   sqlite3DbFree(db, p->zColAff);
   sqlite3DbFree(db, p);
 }
 
 #endif
   sqlite3DbFree(db, p->zColAff);
   sqlite3DbFree(db, p);
 }
 

-/*
-** Remove the given index from the index hash table, and free
-** its memory structures.
-**
-** The index is removed from the database hash tables but
-** it is not unlinked from the Table that it indexes.
-** Unlinking from the Table must be done by the calling function.
-*/
-static void sqlite3DeleteIndex(Index *p){
-  Index *pOld;
-  const char *zName = p->zName;
-
-  pOld = sqlite3HashInsert(&p->pSchema->idxHash, zName,
-                           sqlite3Strlen30(zName), 0);
-  assert( pOld==0 || pOld==p );
-  freeIndex(p);
-}
-

 /*
 ** For the index called zIdxName which is found in the database iDb,
 ** unlike that index from its Table then remove the index from
 /*
 ** For the index called zIdxName which is found in the database iDb,
 ** unlike that index from its Table then remove the index from


@@ -73203,7 +74108,7 @@ SQLITE_PRIVATE void sqlite3UnlinkAndDeleteIndex(sqlite3 *db, int iDb, const char
         p->pNext = pIndex->pNext;
       }
     }
         p->pNext = pIndex->pNext;
       }
     }

-    freeIndex(pIndex);
+    freeIndex(db, pIndex);

   }
   db->flags |= SQLITE_InternChanges;
 }
   }
   db->flags |= SQLITE_InternChanges;
 }


@@ -73274,13 +74179,12 @@ SQLITE_PRIVATE void sqlite3CommitInternalChanges(sqlite3 *db){
 }
 
 /*
 }
 
 /*

-** Clear the column names from a table or view.
+** Delete memory allocated for the column names of a table or view (the
+** Table.aCol[] array).

 */
 */

-static void sqliteResetColumnNames(Table *pTable){
+static void sqliteDeleteColumnNames(sqlite3 *db, Table *pTable){

   int i;
   Column *pCol;
   int i;
   Column *pCol;

-  sqlite3 *db = pTable->dbMem;
-  testcase( db==0 );

   assert( pTable!=0 );
   if( (pCol = pTable->aCol)!=0 ){
     for(i=0; i<pTable->nCol; i++, pCol++){
   assert( pTable!=0 );
   if( (pCol = pTable->aCol)!=0 ){
     for(i=0; i<pTable->nCol; i++, pCol++){


@@ -73292,8 +74196,6 @@ static void sqliteResetColumnNames(Table *pTable){
     }
     sqlite3DbFree(db, pTable->aCol);
   }
     }
     sqlite3DbFree(db, pTable->aCol);
   }

-  pTable->aCol = 0;
-  pTable->nCol = 0;

 }
 
 /*
 }
 
 /*


@@ -73305,42 +74207,44 @@ static void sqliteResetColumnNames(Table *pTable){
 ** memory structures of the indices and foreign keys associated with 
 ** the table.
 */
 ** memory structures of the indices and foreign keys associated with 
 ** the table.
 */

-SQLITE_PRIVATE void sqlite3DeleteTable(Table *pTable){
+SQLITE_PRIVATE void sqlite3DeleteTable(sqlite3 *db, Table *pTable){

   Index *pIndex, *pNext;
   Index *pIndex, *pNext;

-  sqlite3 *db;

 
 

-  if( pTable==0 ) return;
-  db = pTable->dbMem;
-  testcase( db==0 );
+  assert( !pTable || pTable->nRef>0 );

 
   /* Do not delete the table until the reference count reaches zero. */
 
   /* Do not delete the table until the reference count reaches zero. */

-  pTable->nRef--;
-  if( pTable->nRef>0 ){
-    return;
-  }
-  assert( pTable->nRef==0 );
+  if( !pTable ) return;
+  if( ((!db || db->pnBytesFreed==0) && (--pTable->nRef)>0) ) return;

 
 

-  /* Delete all indices associated with this table
-  */
+  /* Delete all indices associated with this table. */

   for(pIndex = pTable->pIndex; pIndex; pIndex=pNext){
     pNext = pIndex->pNext;
     assert( pIndex->pSchema==pTable->pSchema );
   for(pIndex = pTable->pIndex; pIndex; pIndex=pNext){
     pNext = pIndex->pNext;
     assert( pIndex->pSchema==pTable->pSchema );

-    sqlite3DeleteIndex(pIndex);
+    if( !db || db->pnBytesFreed==0 ){
+      char *zName = pIndex->zName; 
+      TESTONLY ( Index *pOld = ) sqlite3HashInsert(
+         &pIndex->pSchema->idxHash, zName, sqlite3Strlen30(zName), 0
+      );
+      assert( pOld==pIndex || pOld==0 );
+    }
+    freeIndex(db, pIndex);

   }
 
   /* Delete any foreign keys attached to this table. */
   }
 
   /* Delete any foreign keys attached to this table. */

-  sqlite3FkDelete(pTable);
+  sqlite3FkDelete(db, pTable);

 
   /* Delete the Table structure itself.
   */
 
   /* Delete the Table structure itself.
   */

-  sqliteResetColumnNames(pTable);
+  sqliteDeleteColumnNames(db, pTable);

   sqlite3DbFree(db, pTable->zName);
   sqlite3DbFree(db, pTable->zColAff);
   sqlite3SelectDelete(db, pTable->pSelect);
 #ifndef SQLITE_OMIT_CHECK
   sqlite3ExprDelete(db, pTable->pCheck);
 #endif
   sqlite3DbFree(db, pTable->zName);
   sqlite3DbFree(db, pTable->zColAff);
   sqlite3SelectDelete(db, pTable->pSelect);
 #ifndef SQLITE_OMIT_CHECK
   sqlite3ExprDelete(db, pTable->pCheck);
 #endif

-  sqlite3VtabClear(pTable);
+#ifndef SQLITE_OMIT_VIRTUALTABLE
+  sqlite3VtabClear(db, pTable);
+#endif

   sqlite3DbFree(db, pTable);
 }
 
   sqlite3DbFree(db, pTable);
 }
 


@@ -73359,7 +74263,7 @@ SQLITE_PRIVATE void sqlite3UnlinkAndDeleteTable(sqlite3 *db, int iDb, const char
   pDb = &db->aDb[iDb];
   p = sqlite3HashInsert(&pDb->pSchema->tblHash, zTabName,
                         sqlite3Strlen30(zTabName),0);
   pDb = &db->aDb[iDb];
   p = sqlite3HashInsert(&pDb->pSchema->tblHash, zTabName,
                         sqlite3Strlen30(zTabName),0);

-  sqlite3DeleteTable(p);
+  sqlite3DeleteTable(db, p);

   db->flags |= SQLITE_InternChanges;
 }
 
   db->flags |= SQLITE_InternChanges;
 }
 


@@ -73627,7 +74531,6 @@ SQLITE_PRIVATE void sqlite3StartTable(
   pTable->iPKey = -1;
   pTable->pSchema = db->aDb[iDb].pSchema;
   pTable->nRef = 1;
   pTable->iPKey = -1;
   pTable->pSchema = db->aDb[iDb].pSchema;
   pTable->nRef = 1;

-  pTable->dbMem = 0;

   assert( pParse->pNewTable==0 );
   pParse->pNewTable = pTable;
 
   assert( pParse->pNewTable==0 );
   pParse->pNewTable = pTable;
 


@@ -74179,7 +75082,7 @@ static char *createTableStmt(sqlite3 *db, Table *p){
     zEnd = "\n)";
   }
   n += 35 + 6*p->nCol;
     zEnd = "\n)";
   }
   n += 35 + 6*p->nCol;

-  zStmt = sqlite3Malloc( n );
+  zStmt = sqlite3DbMallocRaw(0, n);

   if( zStmt==0 ){
     db->mallocFailed = 1;
     return 0;
   if( zStmt==0 ){
     db->mallocFailed = 1;
     return 0;


@@ -74360,7 +75263,7 @@ SQLITE_PRIVATE void sqlite3EndTable(
         p->aCol = pSelTab->aCol;
         pSelTab->nCol = 0;
         pSelTab->aCol = 0;
         p->aCol = pSelTab->aCol;
         pSelTab->nCol = 0;
         pSelTab->aCol = 0;

-        sqlite3DeleteTable(pSelTab);
+        sqlite3DeleteTable(db, pSelTab);

       }
     }
 
       }
     }
 


@@ -74604,7 +75507,7 @@ SQLITE_PRIVATE int sqlite3ViewGetColumnNames(Parse *pParse, Table *pTable){
       pTable->aCol = pSelTab->aCol;
       pSelTab->nCol = 0;
       pSelTab->aCol = 0;
       pTable->aCol = pSelTab->aCol;
       pSelTab->nCol = 0;
       pSelTab->aCol = 0;

-      sqlite3DeleteTable(pSelTab);
+      sqlite3DeleteTable(db, pSelTab);

       pTable->pSchema->flags |= DB_UnresetViews;
     }else{
       pTable->nCol = 0;
       pTable->pSchema->flags |= DB_UnresetViews;
     }else{
       pTable->nCol = 0;


@@ -74629,7 +75532,9 @@ static void sqliteViewResetAll(sqlite3 *db, int idx){
   for(i=sqliteHashFirst(&db->aDb[idx].pSchema->tblHash); i;i=sqliteHashNext(i)){
     Table *pTab = sqliteHashData(i);
     if( pTab->pSelect ){
   for(i=sqliteHashFirst(&db->aDb[idx].pSchema->tblHash); i;i=sqliteHashNext(i)){
     Table *pTab = sqliteHashData(i);
     if( pTab->pSelect ){

-      sqliteResetColumnNames(pTab);
+      sqliteDeleteColumnNames(db, pTab);
+      pTab->aCol = 0;
+      pTab->nCol = 0;

     }
   }
   DbClearProperty(db, idx, DB_UnresetViews);
     }
   }
   DbClearProperty(db, idx, DB_UnresetViews);


@@ -75626,7 +76531,7 @@ SQLITE_PRIVATE Index *sqlite3CreateIndex(
   /* Clean up before exiting */
 exit_create_index:
   if( pIndex ){
   /* Clean up before exiting */
 exit_create_index:
   if( pIndex ){

-    sqlite3_free(pIndex->zColAff);
+    sqlite3DbFree(db, pIndex->zColAff);

     sqlite3DbFree(db, pIndex);
   }
   sqlite3ExprListDelete(db, pList);
     sqlite3DbFree(db, pIndex);
   }
   sqlite3ExprListDelete(db, pList);


@@ -76005,7 +76910,7 @@ SQLITE_PRIVATE void sqlite3SrcListDelete(sqlite3 *db, SrcList *pList){
     sqlite3DbFree(db, pItem->zName);
     sqlite3DbFree(db, pItem->zAlias);
     sqlite3DbFree(db, pItem->zIndex);
     sqlite3DbFree(db, pItem->zName);
     sqlite3DbFree(db, pItem->zAlias);
     sqlite3DbFree(db, pItem->zIndex);

-    sqlite3DeleteTable(pItem->pTab);
+    sqlite3DeleteTable(db, pItem->pTab);

     sqlite3SelectDelete(db, pItem->pSelect);
     sqlite3ExprDelete(db, pItem->pOn);
     sqlite3IdListDelete(db, pItem->pUsing);
     sqlite3SelectDelete(db, pItem->pSelect);
     sqlite3ExprDelete(db, pItem->pOn);
     sqlite3IdListDelete(db, pItem->pUsing);


@@ -76936,8 +77841,7 @@ SQLITE_PRIVATE void sqlite3SchemaFree(void *p){
   sqlite3HashInit(&pSchema->tblHash);
   for(pElem=sqliteHashFirst(&temp1); pElem; pElem=sqliteHashNext(pElem)){
     Table *pTab = sqliteHashData(pElem);
   sqlite3HashInit(&pSchema->tblHash);
   for(pElem=sqliteHashFirst(&temp1); pElem; pElem=sqliteHashNext(pElem)){
     Table *pTab = sqliteHashData(pElem);

-    assert( pTab->dbMem==0 );
-    sqlite3DeleteTable(pTab);
+    sqlite3DeleteTable(0, pTab);

   }
   sqlite3HashClear(&temp1);
   sqlite3HashClear(&pSchema->fkeyHash);
   }
   sqlite3HashClear(&temp1);
   sqlite3HashClear(&pSchema->fkeyHash);


@@ -76954,7 +77858,7 @@ SQLITE_PRIVATE Schema *sqlite3SchemaGet(sqlite3 *db, Btree *pBt){
   if( pBt ){
     p = (Schema *)sqlite3BtreeSchema(pBt, sizeof(Schema), sqlite3SchemaFree);
   }else{
   if( pBt ){
     p = (Schema *)sqlite3BtreeSchema(pBt, sizeof(Schema), sqlite3SchemaFree);
   }else{

-    p = (Schema *)sqlite3MallocZero(sizeof(Schema));
+    p = (Schema *)sqlite3DbMallocZero(0, sizeof(Schema));

   }
   if( !p ){
     db->mallocFailed = 1;
   }
   if( !p ){
     db->mallocFailed = 1;


@@ -76995,7 +77899,7 @@ SQLITE_PRIVATE Table *sqlite3SrcListLookup(Parse *pParse, SrcList *pSrc){
   Table *pTab;
   assert( pItem && pSrc->nSrc==1 );
   pTab = sqlite3LocateTable(pParse, 0, pItem->zName, pItem->zDatabase);
   Table *pTab;
   assert( pItem && pSrc->nSrc==1 );
   pTab = sqlite3LocateTable(pParse, 0, pItem->zName, pItem->zDatabase);

-  sqlite3DeleteTable(pItem->pTab);
+  sqlite3DeleteTable(pParse->db, pItem->pTab);

   pItem->pTab = pTab;
   if( pTab ){
     pTab->nRef++;
   pItem->pTab = pTab;
   if( pTab ){
     pTab->nRef++;


@@ -78392,8 +79296,10 @@ static void compileoptionusedFunc(
   const char *zOptName;
   assert( argc==1 );
   UNUSED_PARAMETER(argc);
   const char *zOptName;
   assert( argc==1 );
   UNUSED_PARAMETER(argc);

-  /* IMP: R-xxxx This function is an SQL wrapper around the
-  ** sqlite3_compileoption_used() C interface. */
+  /* IMP: R-39564-36305 The sqlite_compileoption_used() SQL
+  ** function is a wrapper around the sqlite3_compileoption_used() C/C++
+  ** function.
+  */

   if( (zOptName = (const char*)sqlite3_value_text(argv[0]))!=0 ){
     sqlite3_result_int(context, sqlite3_compileoption_used(zOptName));
   }
   if( (zOptName = (const char*)sqlite3_value_text(argv[0]))!=0 ){
     sqlite3_result_int(context, sqlite3_compileoption_used(zOptName));
   }


@@ -78414,8 +79320,9 @@ static void compileoptiongetFunc(
   int n;
   assert( argc==1 );
   UNUSED_PARAMETER(argc);
   int n;
   assert( argc==1 );
   UNUSED_PARAMETER(argc);

-  /* IMP: R-xxxx This function is an SQL wrapper around the
-  ** sqlite3_compileoption_get() C interface. */
+  /* IMP: R-04922-24076 The sqlite_compileoption_get() SQL function
+  ** is a wrapper around the sqlite3_compileoption_get() C/C++ function.
+  */

   n = sqlite3_value_int(argv[0]);
   sqlite3_result_text(context, sqlite3_compileoption_get(n), -1, SQLITE_STATIC);
 }
   n = sqlite3_value_int(argv[0]);
   sqlite3_result_text(context, sqlite3_compileoption_get(n), -1, SQLITE_STATIC);
 }


@@ -78614,14 +79521,14 @@ static void replaceFunc(
       testcase( nOut-2==db->aLimit[SQLITE_LIMIT_LENGTH] );
       if( nOut-1>db->aLimit[SQLITE_LIMIT_LENGTH] ){
         sqlite3_result_error_toobig(context);
       testcase( nOut-2==db->aLimit[SQLITE_LIMIT_LENGTH] );
       if( nOut-1>db->aLimit[SQLITE_LIMIT_LENGTH] ){
         sqlite3_result_error_toobig(context);

-        sqlite3DbFree(db, zOut);
+        sqlite3_free(zOut);

         return;
       }
       zOld = zOut;
       zOut = sqlite3_realloc(zOut, (int)nOut);
       if( zOut==0 ){
         sqlite3_result_error_nomem(context);
         return;
       }
       zOld = zOut;
       zOut = sqlite3_realloc(zOut, (int)nOut);
       if( zOut==0 ){
         sqlite3_result_error_nomem(context);

-        sqlite3DbFree(db, zOld);
+        sqlite3_free(zOld);

         return;
       }
       memcpy(&zOut[j], zRep, nRep);
         return;
       }
       memcpy(&zOut[j], zRep, nRep);


@@ -78982,7 +79889,7 @@ static void groupConcatStep(
   if( pAccum ){
     sqlite3 *db = sqlite3_context_db_handle(context);
     int firstTerm = pAccum->useMalloc==0;
   if( pAccum ){
     sqlite3 *db = sqlite3_context_db_handle(context);
     int firstTerm = pAccum->useMalloc==0;

-    pAccum->useMalloc = 1;
+    pAccum->useMalloc = 2;

     pAccum->mxAlloc = db->aLimit[SQLITE_LIMIT_LENGTH];
     if( !firstTerm ){
       if( argc==2 ){
     pAccum->mxAlloc = db->aLimit[SQLITE_LIMIT_LENGTH];
     if( !firstTerm ){
       if( argc==2 ){


@@ -79699,7 +80606,8 @@ static void fkScanChildren(
       if( pIdx ){
         Column *pCol;
         iCol = pIdx->aiColumn[i];
       if( pIdx ){
         Column *pCol;
         iCol = pIdx->aiColumn[i];

-        pCol = &pIdx->pTable->aCol[iCol];
+        pCol = &pTab->aCol[iCol];
+        if( pTab->iPKey==iCol ) iCol = -1;

         pLeft->iTable = regData+iCol+1;
         pLeft->affinity = pCol->affinity;
         pLeft->pColl = sqlite3LocateCollSeq(pParse, pCol->zColl);
         pLeft->iTable = regData+iCol+1;
         pLeft->affinity = pCol->affinity;
         pLeft->pColl = sqlite3LocateCollSeq(pParse, pCol->zColl);


@@ -80260,11 +81168,7 @@ static Trigger *fkActionTrigger(
       pWhere = 0;
     }
 
       pWhere = 0;
     }
 

-    /* In the current implementation, pTab->dbMem==0 for all tables except
-    ** for temporary tables used to describe subqueries.  And temporary
-    ** tables do not have foreign key constraints.  Hence, pTab->dbMem
-    ** should always be 0 there.
-    */
+    /* Disable lookaside memory allocation */

     enableLookaside = db->lookaside.bEnabled;
     db->lookaside.bEnabled = 0;
 
     enableLookaside = db->lookaside.bEnabled;
     db->lookaside.bEnabled = 0;
 


@@ -80354,37 +81258,39 @@ SQLITE_PRIVATE void sqlite3FkActions(
 ** table pTab. Remove the deleted foreign keys from the Schema.fkeyHash
 ** hash table.
 */
 ** table pTab. Remove the deleted foreign keys from the Schema.fkeyHash
 ** hash table.
 */

-SQLITE_PRIVATE void sqlite3FkDelete(Table *pTab){
+SQLITE_PRIVATE void sqlite3FkDelete(sqlite3 *db, Table *pTab){

   FKey *pFKey;                    /* Iterator variable */
   FKey *pNext;                    /* Copy of pFKey->pNextFrom */
 
   for(pFKey=pTab->pFKey; pFKey; pFKey=pNext){
 
     /* Remove the FK from the fkeyHash hash table. */
   FKey *pFKey;                    /* Iterator variable */
   FKey *pNext;                    /* Copy of pFKey->pNextFrom */
 
   for(pFKey=pTab->pFKey; pFKey; pFKey=pNext){
 
     /* Remove the FK from the fkeyHash hash table. */

-    if( pFKey->pPrevTo ){
-      pFKey->pPrevTo->pNextTo = pFKey->pNextTo;
-    }else{
-      void *data = (void *)pFKey->pNextTo;
-      const char *z = (data ? pFKey->pNextTo->zTo : pFKey->zTo);
-      sqlite3HashInsert(&pTab->pSchema->fkeyHash, z, sqlite3Strlen30(z), data);
-    }
-    if( pFKey->pNextTo ){
-      pFKey->pNextTo->pPrevTo = pFKey->pPrevTo;
+    if( !db || db->pnBytesFreed==0 ){
+      if( pFKey->pPrevTo ){
+        pFKey->pPrevTo->pNextTo = pFKey->pNextTo;
+      }else{
+        void *p = (void *)pFKey->pNextTo;
+        const char *z = (p ? pFKey->pNextTo->zTo : pFKey->zTo);
+        sqlite3HashInsert(&pTab->pSchema->fkeyHash, z, sqlite3Strlen30(z), p);
+      }
+      if( pFKey->pNextTo ){
+        pFKey->pNextTo->pPrevTo = pFKey->pPrevTo;
+      }

     }
 
     }
 

-    /* Delete any triggers created to implement actions for this FK. */
-#ifndef SQLITE_OMIT_TRIGGER
-    fkTriggerDelete(pTab->dbMem, pFKey->apTrigger[0]);
-    fkTriggerDelete(pTab->dbMem, pFKey->apTrigger[1]);
-#endif
-

     /* EV: R-30323-21917 Each foreign key constraint in SQLite is
     ** classified as either immediate or deferred.
     */
     assert( pFKey->isDeferred==0 || pFKey->isDeferred==1 );
 
     /* EV: R-30323-21917 Each foreign key constraint in SQLite is
     ** classified as either immediate or deferred.
     */
     assert( pFKey->isDeferred==0 || pFKey->isDeferred==1 );
 

+    /* Delete any triggers created to implement actions for this FK. */
+#ifndef SQLITE_OMIT_TRIGGER
+    fkTriggerDelete(db, pFKey->apTrigger[0]);
+    fkTriggerDelete(db, pFKey->apTrigger[1]);
+#endif
+

     pNext = pFKey->pNextFrom;
     pNext = pFKey->pNextFrom;

-    sqlite3DbFree(pTab->dbMem, pFKey);
+    sqlite3DbFree(db, pFKey);

   }
 }
 #endif /* ifndef SQLITE_OMIT_FOREIGN_KEY */
   }
 }
 #endif /* ifndef SQLITE_OMIT_FOREIGN_KEY */


@@ -80459,7 +81365,7 @@ SQLITE_PRIVATE const char *sqlite3IndexAffinityStr(Vdbe *v, Index *pIdx){
     int n;
     Table *pTab = pIdx->pTable;
     sqlite3 *db = sqlite3VdbeDb(v);
     int n;
     Table *pTab = pIdx->pTable;
     sqlite3 *db = sqlite3VdbeDb(v);

-    pIdx->zColAff = (char *)sqlite3Malloc(pIdx->nColumn+2);
+    pIdx->zColAff = (char *)sqlite3DbMallocRaw(0, pIdx->nColumn+2);

     if( !pIdx->zColAff ){
       db->mallocFailed = 1;
       return 0;
     if( !pIdx->zColAff ){
       db->mallocFailed = 1;
       return 0;


@@ -80501,7 +81407,7 @@ SQLITE_PRIVATE void sqlite3TableAffinityStr(Vdbe *v, Table *pTab){
     int i;
     sqlite3 *db = sqlite3VdbeDb(v);
 
     int i;
     sqlite3 *db = sqlite3VdbeDb(v);
 

-    zColAff = (char *)sqlite3Malloc(pTab->nCol+1);
+    zColAff = (char *)sqlite3DbMallocRaw(0, pTab->nCol+1);

     if( !zColAff ){
       db->mallocFailed = 1;
       return;
     if( !zColAff ){
       db->mallocFailed = 1;
       return;


@@ -81612,6 +82518,7 @@ SQLITE_PRIVATE void sqlite3GenerateConstraintChecks(
     if( onError==OE_Ignore ){
       sqlite3VdbeAddOp2(v, OP_Goto, 0, ignoreDest);
     }else{
     if( onError==OE_Ignore ){
       sqlite3VdbeAddOp2(v, OP_Goto, 0, ignoreDest);
     }else{

+      if( onError==OE_Replace ) onError = OE_Abort; /* IMP: R-15569-63625 */

       sqlite3HaltConstraint(pParse, onError, 0, 0);
     }
     sqlite3VdbeResolveLabel(v, allOk);
       sqlite3HaltConstraint(pParse, onError, 0, 0);
     }
     sqlite3VdbeResolveLabel(v, allOk);


@@ -83126,13 +84033,11 @@ static int sqlite3LoadExtension(
   handle = sqlite3OsDlOpen(pVfs, zFile);
   if( handle==0 ){
     if( pzErrMsg ){
   handle = sqlite3OsDlOpen(pVfs, zFile);
   if( handle==0 ){
     if( pzErrMsg ){

-      zErrmsg = sqlite3StackAllocZero(db, nMsg);
+      *pzErrMsg = zErrmsg = sqlite3_malloc(nMsg);

       if( zErrmsg ){
         sqlite3_snprintf(nMsg, zErrmsg, 
             "unable to open shared library [%s]", zFile);
         sqlite3OsDlError(pVfs, nMsg-1, zErrmsg);
       if( zErrmsg ){
         sqlite3_snprintf(nMsg, zErrmsg, 
             "unable to open shared library [%s]", zFile);
         sqlite3OsDlError(pVfs, nMsg-1, zErrmsg);

-        *pzErrMsg = sqlite3DbStrDup(0, zErrmsg);
-        sqlite3StackFree(db, zErrmsg);

       }
     }
     return SQLITE_ERROR;
       }
     }
     return SQLITE_ERROR;


@@ -83141,13 +84046,11 @@ static int sqlite3LoadExtension(
                    sqlite3OsDlSym(pVfs, handle, zProc);
   if( xInit==0 ){
     if( pzErrMsg ){
                    sqlite3OsDlSym(pVfs, handle, zProc);
   if( xInit==0 ){
     if( pzErrMsg ){

-      zErrmsg = sqlite3StackAllocZero(db, nMsg);
+      *pzErrMsg = zErrmsg = sqlite3_malloc(nMsg);

       if( zErrmsg ){
         sqlite3_snprintf(nMsg, zErrmsg,
             "no entry point [%s] in shared library [%s]", zProc,zFile);
         sqlite3OsDlError(pVfs, nMsg-1, zErrmsg);
       if( zErrmsg ){
         sqlite3_snprintf(nMsg, zErrmsg,
             "no entry point [%s] in shared library [%s]", zProc,zFile);
         sqlite3OsDlError(pVfs, nMsg-1, zErrmsg);

-        *pzErrMsg = sqlite3DbStrDup(0, zErrmsg);
-        sqlite3StackFree(db, zErrmsg);

       }
       sqlite3OsDlClose(pVfs, handle);
     }
       }
       sqlite3OsDlClose(pVfs, handle);
     }


@@ -84126,7 +85029,7 @@ SQLITE_PRIVATE void sqlite3Pragma(
       }
       sqlite3_free(sqlite3_temp_directory);
       if( zRight[0] ){
       }
       sqlite3_free(sqlite3_temp_directory);
       if( zRight[0] ){

-        sqlite3_temp_directory = sqlite3DbStrDup(0, zRight);
+        sqlite3_temp_directory = sqlite3_mprintf("%s", zRight);

       }else{
         sqlite3_temp_directory = 0;
       }
       }else{
         sqlite3_temp_directory = 0;
       }


@@ -85547,7 +86450,6 @@ static int sqlite3Prepare(
   while( pParse->pTriggerPrg ){
     TriggerPrg *pT = pParse->pTriggerPrg;
     pParse->pTriggerPrg = pT->pNext;
   while( pParse->pTriggerPrg ){
     TriggerPrg *pT = pParse->pTriggerPrg;
     pParse->pTriggerPrg = pT->pNext;

-    sqlite3VdbeProgramDelete(db, pT->pProgram, 0);

     sqlite3DbFree(db, pT);
   }
 
     sqlite3DbFree(db, pT);
   }
 


@@ -87038,16 +87940,15 @@ SQLITE_PRIVATE Table *sqlite3ResultSetOfSelect(Parse *pParse, Select *pSelect){
     return 0;
   }
   /* The sqlite3ResultSetOfSelect() is only used n contexts where lookaside
     return 0;
   }
   /* The sqlite3ResultSetOfSelect() is only used n contexts where lookaside

-  ** is disabled, so we might as well hard-code pTab->dbMem to NULL. */
+  ** is disabled */

   assert( db->lookaside.bEnabled==0 );
   assert( db->lookaside.bEnabled==0 );

-  pTab->dbMem = 0;

   pTab->nRef = 1;
   pTab->zName = 0;
   selectColumnsFromExprList(pParse, pSelect->pEList, &pTab->nCol, &pTab->aCol);
   selectAddColumnTypeAndCollation(pParse, pTab->nCol, pTab->aCol, pSelect);
   pTab->iPKey = -1;
   if( db->mallocFailed ){
   pTab->nRef = 1;
   pTab->zName = 0;
   selectColumnsFromExprList(pParse, pSelect->pEList, &pTab->nCol, &pTab->aCol);
   selectAddColumnTypeAndCollation(pParse, pTab->nCol, pTab->aCol, pSelect);
   pTab->iPKey = -1;
   if( db->mallocFailed ){

-    sqlite3DeleteTable(pTab);
+    sqlite3DeleteTable(db, pTab);

     return 0;
   }
   return pTab;
     return 0;
   }
   return pTab;


@@ -87539,7 +88440,7 @@ multi_select_end:
 ** regReturn is the number of the register holding the subroutine
 ** return address.
 **
 ** regReturn is the number of the register holding the subroutine
 ** return address.
 **

-** If regPrev>0 then it is a the first register in a vector that
+** If regPrev>0 then it is the first register in a vector that

 ** records the previous output.  mem[regPrev] is a flag that is false
 ** if there has been no previous output.  If regPrev>0 then code is
 ** generated to suppress duplicates.  pKeyInfo is used for comparing
 ** records the previous output.  mem[regPrev] is a flag that is false
 ** if there has been no previous output.  If regPrev>0 then code is
 ** generated to suppress duplicates.  pKeyInfo is used for comparing


@@ -88236,12 +89137,13 @@ static void substSelect(
 **   (2)  The subquery is not an aggregate or the outer query is not a join.
 **
 **   (3)  The subquery is not the right operand of a left outer join
 **   (2)  The subquery is not an aggregate or the outer query is not a join.
 **
 **   (3)  The subquery is not the right operand of a left outer join

-**        (Originally ticket #306.  Strenghtened by ticket #3300)
+**        (Originally ticket #306.  Strengthened by ticket #3300)

 **
 **

-**   (4)  The subquery is not DISTINCT or the outer query is not a join.
+**   (4)  The subquery is not DISTINCT.

 **
 **

-**   (5)  The subquery is not DISTINCT or the outer query does not use
-**        aggregates.
+**  (**)  At one point restrictions (4) and (5) defined a subset of DISTINCT
+**        sub-queries that were excluded from this optimization. Restriction 
+**        (4) has since been expanded to exclude all DISTINCT subqueries.

 **
 **   (6)  The subquery does not use aggregates or the outer query is not
 **        DISTINCT.
 **
 **   (6)  The subquery does not use aggregates or the outer query is not
 **        DISTINCT.


@@ -88261,9 +89163,9 @@ static void substSelect(
 **  (**)  Not implemented.  Subsumed into restriction (3).  Was previously
 **        a separate restriction deriving from ticket #350.
 **
 **  (**)  Not implemented.  Subsumed into restriction (3).  Was previously
 **        a separate restriction deriving from ticket #350.
 **

-**  (13)  The subquery and outer query do not both use LIMIT
+**  (13)  The subquery and outer query do not both use LIMIT.

 **
 **

-**  (14)  The subquery does not use OFFSET
+**  (14)  The subquery does not use OFFSET.

 **
 **  (15)  The outer query is not part of a compound select or the
 **        subquery does not have a LIMIT clause.
 **
 **  (15)  The outer query is not part of a compound select or the
 **        subquery does not have a LIMIT clause.


@@ -88354,9 +89256,9 @@ static int flattenSubquery(
     return 0;                                            /* Restriction (15) */
   }
   if( pSubSrc->nSrc==0 ) return 0;                       /* Restriction (7)  */
     return 0;                                            /* Restriction (15) */
   }
   if( pSubSrc->nSrc==0 ) return 0;                       /* Restriction (7)  */

-  if( ((pSub->selFlags & SF_Distinct)!=0 || pSub->pLimit) 
-         && (pSrc->nSrc>1 || isAgg) ){          /* Restrictions (4)(5)(8)(9) */
-     return 0;       
+  if( pSub->selFlags & SF_Distinct ) return 0;           /* Restriction (5)  */
+  if( pSub->pLimit && (pSrc->nSrc>1 || isAgg) ){
+     return 0;         /* Restrictions (8)(9) */

   }
   if( (p->selFlags & SF_Distinct)!=0 && subqueryIsAgg ){
      return 0;         /* Restriction (6)  */
   }
   if( (p->selFlags & SF_Distinct)!=0 && subqueryIsAgg ){
      return 0;         /* Restriction (6)  */


@@ -88836,7 +89738,6 @@ static int selectExpander(Walker *pWalker, Select *p){
       sqlite3WalkSelect(pWalker, pSel);
       pFrom->pTab = pTab = sqlite3DbMallocZero(db, sizeof(Table));
       if( pTab==0 ) return WRC_Abort;
       sqlite3WalkSelect(pWalker, pSel);
       pFrom->pTab = pTab = sqlite3DbMallocZero(db, sizeof(Table));
       if( pTab==0 ) return WRC_Abort;

-      pTab->dbMem = db->lookaside.bEnabled ? db : 0;

       pTab->nRef = 1;
       pTab->zName = sqlite3MPrintf(db, "sqlite_subquery_%p_", (void*)pTab);
       while( pSel->pPrior ){ pSel = pSel->pPrior; }
       pTab->nRef = 1;
       pTab->zName = sqlite3MPrintf(db, "sqlite_subquery_%p_", (void*)pTab);
       while( pSel->pPrior ){ pSel = pSel->pPrior; }


@@ -91050,6 +91951,7 @@ static TriggerPrg *codeRowTrigger(
   int iEndTrigger = 0;        /* Label to jump to if WHEN is false */
 
   assert( pTrigger->zName==0 || pTab==tableOfTrigger(pTrigger) );
   int iEndTrigger = 0;        /* Label to jump to if WHEN is false */
 
   assert( pTrigger->zName==0 || pTab==tableOfTrigger(pTrigger) );

+  assert( pTop->pVdbe );

 
   /* Allocate the TriggerPrg and SubProgram objects. To ensure that they
   ** are freed if an error occurs, link them into the Parse.pTriggerPrg 
 
   /* Allocate the TriggerPrg and SubProgram objects. To ensure that they
   ** are freed if an error occurs, link them into the Parse.pTriggerPrg 


@@ -91060,7 +91962,7 @@ static TriggerPrg *codeRowTrigger(
   pTop->pTriggerPrg = pPrg;
   pPrg->pProgram = pProgram = sqlite3DbMallocZero(db, sizeof(SubProgram));
   if( !pProgram ) return 0;
   pTop->pTriggerPrg = pPrg;
   pPrg->pProgram = pProgram = sqlite3DbMallocZero(db, sizeof(SubProgram));
   if( !pProgram ) return 0;

-  pProgram->nRef = 1;
+  sqlite3VdbeLinkSubProgram(pTop->pVdbe, pProgram);

   pPrg->pTrigger = pTrigger;
   pPrg->orconf = orconf;
   pPrg->aColmask[0] = 0xffffffff;
   pPrg->pTrigger = pTrigger;
   pPrg->orconf = orconf;
   pPrg->aColmask[0] = 0xffffffff;


@@ -91194,8 +92096,9 @@ SQLITE_PRIVATE void sqlite3CodeRowTriggerDirect(
   /* Code the OP_Program opcode in the parent VDBE. P4 of the OP_Program 
   ** is a pointer to the sub-vdbe containing the trigger program.  */
   if( pPrg ){
   /* Code the OP_Program opcode in the parent VDBE. P4 of the OP_Program 
   ** is a pointer to the sub-vdbe containing the trigger program.  */
   if( pPrg ){

+    int bRecursive = (p->zName && 0==(pParse->db->flags&SQLITE_RecTriggers));
+

     sqlite3VdbeAddOp3(v, OP_Program, reg, ignoreJump, ++pParse->nMem);
     sqlite3VdbeAddOp3(v, OP_Program, reg, ignoreJump, ++pParse->nMem);

-    pPrg->pProgram->nRef++;

     sqlite3VdbeChangeP4(v, -1, (const char *)pPrg->pProgram, P4_SUBPROGRAM);
     VdbeComment(
         (v, "Call: %s.%s", (p->zName?p->zName:"fkey"), onErrorText(orconf)));
     sqlite3VdbeChangeP4(v, -1, (const char *)pPrg->pProgram, P4_SUBPROGRAM);
     VdbeComment(
         (v, "Call: %s.%s", (p->zName?p->zName:"fkey"), onErrorText(orconf)));


@@ -91205,7 +92108,7 @@ SQLITE_PRIVATE void sqlite3CodeRowTriggerDirect(
     ** invocation is disallowed if (a) the sub-program is really a trigger,
     ** not a foreign key action, and (b) the flag to enable recursive triggers
     ** is clear.  */
     ** invocation is disallowed if (a) the sub-program is really a trigger,
     ** not a foreign key action, and (b) the flag to enable recursive triggers
     ** is clear.  */

-    sqlite3VdbeChangeP5(v, (u8)(p->zName && !(pParse->db->flags&SQLITE_RecTriggers)));
+    sqlite3VdbeChangeP5(v, (u8)bRecursive);

   }
 }
 
   }
 }
 


@@ -91354,7 +92257,7 @@ SQLITE_PRIVATE u32 sqlite3TriggerColmask(
 **    May you find forgiveness for yourself and forgive others.
 **    May you share freely, never taking more than you give.
 **
 **    May you find forgiveness for yourself and forgive others.
 **    May you share freely, never taking more than you give.
 **

-sqlite*************************************************************************
+*************************************************************************

 ** This file contains C code routines that are called by the parser
 ** to handle UPDATE statements.
 */
 ** This file contains C code routines that are called by the parser
 ** to handle UPDATE statements.
 */


@@ -92573,14 +93476,14 @@ SQLITE_PRIVATE void sqlite3VtabUnlockList(sqlite3 *db){
 ** in the list are moved to the sqlite3.pDisconnect list of the associated 
 ** database connection.
 */
 ** in the list are moved to the sqlite3.pDisconnect list of the associated 
 ** database connection.
 */

-SQLITE_PRIVATE void sqlite3VtabClear(Table *p){
-  vtabDisconnectAll(0, p);
+SQLITE_PRIVATE void sqlite3VtabClear(sqlite3 *db, Table *p){
+  if( !db || db->pnBytesFreed==0 ) vtabDisconnectAll(0, p);

   if( p->azModuleArg ){
     int i;
     for(i=0; i<p->nModuleArg; i++){
   if( p->azModuleArg ){
     int i;
     for(i=0; i<p->nModuleArg; i++){

-      sqlite3DbFree(p->dbMem, p->azModuleArg[i]);
+      sqlite3DbFree(db, p->azModuleArg[i]);

     }
     }

-    sqlite3DbFree(p->dbMem, p->azModuleArg);
+    sqlite3DbFree(db, p->azModuleArg);

   }
 }
 
   }
 }
 


@@ -92745,7 +93648,6 @@ SQLITE_PRIVATE void sqlite3VtabFinishParse(Parse *pParse, Token *pEnd){
       assert( pTab==pOld );  /* Malloc must have failed inside HashInsert() */
       return;
     }
       assert( pTab==pOld );  /* Malloc must have failed inside HashInsert() */
       return;
     }

-    pSchema->db = pParse->db;

     pParse->pNewTable = 0;
   }
 }
     pParse->pNewTable = 0;
   }
 }


@@ -92819,7 +93721,7 @@ static int vtabCallConstructor(
       *pzErr = sqlite3MPrintf(db, "vtable constructor failed: %s", zModuleName);
     }else {
       *pzErr = sqlite3MPrintf(db, "%s", zErr);
       *pzErr = sqlite3MPrintf(db, "vtable constructor failed: %s", zModuleName);
     }else {
       *pzErr = sqlite3MPrintf(db, "%s", zErr);

-      sqlite3DbFree(db, zErr);
+      sqlite3_free(zErr);

     }
     sqlite3DbFree(db, pVTable);
   }else if( ALWAYS(pVTable->pVtab) ){
     }
     sqlite3DbFree(db, pVTable);
   }else if( ALWAYS(pVTable->pVtab) ){


@@ -93034,7 +93936,7 @@ SQLITE_API int sqlite3_declare_vtab(sqlite3 *db, const char *zCreateTable){
     if( pParse->pVdbe ){
       sqlite3VdbeFinalize(pParse->pVdbe);
     }
     if( pParse->pVdbe ){
       sqlite3VdbeFinalize(pParse->pVdbe);
     }

-    sqlite3DeleteTable(pParse->pNewTable);
+    sqlite3DeleteTable(db, pParse->pNewTable);

     sqlite3StackFree(db, pParse);
   }
 
     sqlite3StackFree(db, pParse);
   }
 


@@ -93121,8 +94023,8 @@ SQLITE_PRIVATE int sqlite3VtabSync(sqlite3 *db, char **pzErrmsg){
     if( pVtab && (x = pVtab->pModule->xSync)!=0 ){
       rc = x(pVtab);
       sqlite3DbFree(db, *pzErrmsg);
     if( pVtab && (x = pVtab->pModule->xSync)!=0 ){
       rc = x(pVtab);
       sqlite3DbFree(db, *pzErrmsg);

-      *pzErrmsg = pVtab->zErrMsg;
-      pVtab->zErrMsg = 0;
+      *pzErrmsg = sqlite3DbStrDup(db, pVtab->zErrMsg);
+      sqlite3_free(pVtab->zErrMsg);

     }
   }
   db->aVTrans = aVTrans;
     }
   }
   db->aVTrans = aVTrans;


@@ -93622,6 +94524,7 @@ static void whereClauseClear(WhereClause *pWC){
 static int whereClauseInsert(WhereClause *pWC, Expr *p, u8 wtFlags){
   WhereTerm *pTerm;
   int idx;
 static int whereClauseInsert(WhereClause *pWC, Expr *p, u8 wtFlags){
   WhereTerm *pTerm;
   int idx;

+  testcase( wtFlags & TERM_VIRTUAL );  /* EV: R-00211-15100 */

   if( pWC->nTerm>=pWC->nSlot ){
     WhereTerm *pOld = pWC->a;
     sqlite3 *db = pWC->pParse->db;
   if( pWC->nTerm>=pWC->nSlot ){
     WhereTerm *pOld = pWC->a;
     sqlite3 *db = pWC->pParse->db;


@@ -93767,6 +94670,13 @@ static Bitmask exprSelectTableUsage(WhereMaskSet *pMaskSet, Select *pS){
 ** Return TRUE if the given operator is one of the operators that is
 ** allowed for an indexable WHERE clause term.  The allowed operators are
 ** "=", "<", ">", "<=", ">=", and "IN".
 ** Return TRUE if the given operator is one of the operators that is
 ** allowed for an indexable WHERE clause term.  The allowed operators are
 ** "=", "<", ">", "<=", ">=", and "IN".

+**
+** IMPLEMENTATION-OF: R-59926-26393 To be usable by an index a term must be
+** of one of the following forms: column = expression column > expression
+** column >= expression column < expression column <= expression
+** expression = column expression > column expression >= column
+** expression < column expression <= column column IN
+** (expression-list) column IN (subquery) column IS NULL

 */
 static int allowedOp(int op){
   assert( TK_GT>TK_EQ && TK_GT<TK_GE );
 */
 static int allowedOp(int op){
   assert( TK_GT>TK_EQ && TK_GT<TK_GE );


@@ -93930,7 +94840,6 @@ static int isLikeOrGlob(
   int c;                     /* One character in z[] */
   int cnt;                   /* Number of non-wildcard prefix characters */
   char wc[3];                /* Wildcard characters */
   int c;                     /* One character in z[] */
   int cnt;                   /* Number of non-wildcard prefix characters */
   char wc[3];                /* Wildcard characters */

-  CollSeq *pColl;            /* Collating sequence for LHS */

   sqlite3 *db = pParse->db;  /* Database connection */
   sqlite3_value *pVal = 0;
   int op;                    /* Opcode of pRight */
   sqlite3 *db = pParse->db;  /* Database connection */
   sqlite3_value *pVal = 0;
   int op;                    /* Opcode of pRight */


@@ -93949,19 +94858,6 @@ static int isLikeOrGlob(
     return 0;
   }
   assert( pLeft->iColumn!=(-1) ); /* Because IPK never has AFF_TEXT */
     return 0;
   }
   assert( pLeft->iColumn!=(-1) ); /* Because IPK never has AFF_TEXT */

-  pColl = sqlite3ExprCollSeq(pParse, pLeft);
-  if( pColl==0 ) return 0;  /* Happens when LHS has an undefined collation */
-  if( (pColl->type!=SQLITE_COLL_BINARY || *pnoCase) &&
-      (pColl->type!=SQLITE_COLL_NOCASE || !*pnoCase) ){
-    /* IMP: R-09003-32046 For the GLOB operator, the column must use the
-    ** default BINARY collating sequence.
-    ** IMP: R-41408-28306 For the LIKE operator, if case_sensitive_like mode
-    ** is enabled then the column must use the default BINARY collating
-    ** sequence, or if case_sensitive_like mode is disabled then the column
-    ** must use the built-in NOCASE collating sequence.
-    */
-    return 0;
-  }

 
   pRight = pList->a[0].pExpr;
   op = pRight->op;
 
   pRight = pList->a[0].pExpr;
   op = pRight->op;


@@ -93984,9 +94880,9 @@ static int isLikeOrGlob(
     while( (c=z[cnt])!=0 && c!=wc[0] && c!=wc[1] && c!=wc[2] ){
       cnt++;
     }
     while( (c=z[cnt])!=0 && c!=wc[0] && c!=wc[1] && c!=wc[2] ){
       cnt++;
     }

-    if( cnt!=0 && c!=0 && 255!=(u8)z[cnt-1] ){
+    if( cnt!=0 && 255!=(u8)z[cnt-1] ){

       Expr *pPrefix;
       Expr *pPrefix;

-      *pisComplete = z[cnt]==wc[0] && z[cnt+1]==0;
+      *pisComplete = c==wc[0] && z[cnt+1]==0;

       pPrefix = sqlite3Expr(db, TK_STRING, z);
       if( pPrefix ) pPrefix->u.zToken[cnt] = 0;
       *ppPrefix = pPrefix;
       pPrefix = sqlite3Expr(db, TK_STRING, z);
       if( pPrefix ) pPrefix->u.zToken[cnt] = 0;
       *ppPrefix = pPrefix;


@@ -94325,6 +95221,8 @@ static void exprAnalyzeOrTerm(
     /* At this point, okToChngToIN is true if original pTerm satisfies
     ** case 1.  In that case, construct a new virtual term that is 
     ** pTerm converted into an IN operator.
     /* At this point, okToChngToIN is true if original pTerm satisfies
     ** case 1.  In that case, construct a new virtual term that is 
     ** pTerm converted into an IN operator.

+    **
+    ** EV: R-00211-15100

     */
     if( okToChngToIN ){
       Expr *pDup;            /* A transient duplicate expression */
     */
     if( okToChngToIN ){
       Expr *pDup;            /* A transient duplicate expression */


@@ -94541,6 +95439,7 @@ static void exprAnalyze(
     Expr *pNewExpr2;
     int idxNew1;
     int idxNew2;
     Expr *pNewExpr2;
     int idxNew1;
     int idxNew2;

+    CollSeq *pColl;    /* Collating sequence to use */

 
     pLeft = pExpr->x.pList->a[1].pExpr;
     pStr2 = sqlite3ExprDup(db, pStr1, 0);
 
     pLeft = pExpr->x.pList->a[1].pExpr;
     pStr2 = sqlite3ExprDup(db, pStr1, 0);


@@ -94555,17 +95454,23 @@ static void exprAnalyze(
         ** inequality.  To avoid this, make sure to also run the full
         ** LIKE on all candidate expressions by clearing the isComplete flag
         */
         ** inequality.  To avoid this, make sure to also run the full
         ** LIKE on all candidate expressions by clearing the isComplete flag
         */

-        if( c=='A'-1 ) isComplete = 0;
+        if( c=='A'-1 ) isComplete = 0;   /* EV: R-64339-08207 */
+

 
         c = sqlite3UpperToLower[c];
       }
       *pC = c + 1;
     }
 
         c = sqlite3UpperToLower[c];
       }
       *pC = c + 1;
     }

-    pNewExpr1 = sqlite3PExpr(pParse, TK_GE, sqlite3ExprDup(db,pLeft,0),pStr1,0);
+    pColl = sqlite3FindCollSeq(db, SQLITE_UTF8, noCase ? "NOCASE" : "BINARY",0);
+    pNewExpr1 = sqlite3PExpr(pParse, TK_GE, 
+                     sqlite3ExprSetColl(sqlite3ExprDup(db,pLeft,0), pColl),
+                     pStr1, 0);

     idxNew1 = whereClauseInsert(pWC, pNewExpr1, TERM_VIRTUAL|TERM_DYNAMIC);
     testcase( idxNew1==0 );
     exprAnalyze(pSrc, pWC, idxNew1);
     idxNew1 = whereClauseInsert(pWC, pNewExpr1, TERM_VIRTUAL|TERM_DYNAMIC);
     testcase( idxNew1==0 );
     exprAnalyze(pSrc, pWC, idxNew1);

-    pNewExpr2 = sqlite3PExpr(pParse, TK_LT, sqlite3ExprDup(db,pLeft,0),pStr2,0);
+    pNewExpr2 = sqlite3PExpr(pParse, TK_LT,
+                     sqlite3ExprSetColl(sqlite3ExprDup(db,pLeft,0), pColl),
+                     pStr2, 0);

     idxNew2 = whereClauseInsert(pWC, pNewExpr2, TERM_VIRTUAL|TERM_DYNAMIC);
     testcase( idxNew2==0 );
     exprAnalyze(pSrc, pWC, idxNew2);
     idxNew2 = whereClauseInsert(pWC, pNewExpr2, TERM_VIRTUAL|TERM_DYNAMIC);
     testcase( idxNew2==0 );
     exprAnalyze(pSrc, pWC, idxNew2);


@@ -95317,7 +96222,7 @@ static int vtabBestIndex(Parse *pParse, Table *pTab, sqlite3_index_info *p){
       sqlite3ErrorMsg(pParse, "%s", pVtab->zErrMsg);
     }
   }
       sqlite3ErrorMsg(pParse, "%s", pVtab->zErrMsg);
     }
   }

-  sqlite3DbFree(pParse->db, pVtab->zErrMsg);
+  sqlite3_free(pVtab->zErrMsg);

   pVtab->zErrMsg = 0;
 
   for(i=0; i<p->nConstraint; i++){
   pVtab->zErrMsg = 0;
 
   for(i=0; i<p->nConstraint; i++){


@@ -96182,6 +97087,9 @@ static void bestIndex(
 ** in the ON clause.  The term is disabled in (3) because it is not part
 ** of a LEFT OUTER JOIN.  In (1), the term is not disabled.
 **
 ** in the ON clause.  The term is disabled in (3) because it is not part
 ** of a LEFT OUTER JOIN.  In (1), the term is not disabled.
 **

+** IMPLEMENTATION-OF: R-24597-58655 No tests are done for terms that are
+** completely satisfied by indices.
+**

 ** Disabling a term causes that term to not be tested in the inner loop
 ** of the join.  Disabling is an optimization.  When terms are satisfied
 ** by indices, we disable them to prevent redundant tests in the inner
 ** Disabling a term causes that term to not be tested in the inner loop
 ** of the join.  Disabling is an optimization.  When terms are satisfied
 ** by indices, we disable them to prevent redundant tests in the inner


@@ -96393,6 +97301,7 @@ static int codeAllEqualityTerms(
     /* The following true for indices with redundant columns. 
     ** Ex: CREATE INDEX i1 ON t1(a,b,a); SELECT * FROM t1 WHERE a=0 AND b=0; */
     testcase( (pTerm->wtFlags & TERM_CODED)!=0 );
     /* The following true for indices with redundant columns. 
     ** Ex: CREATE INDEX i1 ON t1(a,b,a); SELECT * FROM t1 WHERE a=0 AND b=0; */
     testcase( (pTerm->wtFlags & TERM_CODED)!=0 );

+    testcase( pTerm->wtFlags & TERM_VIRTUAL ); /* EV: R-30575-11662 */

     r1 = codeEqualityTerm(pParse, pTerm, pLevel, regBase+j);
     if( r1!=regBase+j ){
       if( nReg==1 ){
     r1 = codeEqualityTerm(pParse, pTerm, pLevel, regBase+j);
     if( r1!=regBase+j ){
       if( nReg==1 ){


@@ -96536,6 +97445,7 @@ static Bitmask codeOneLoopStart(
     assert( pTerm->pExpr!=0 );
     assert( pTerm->leftCursor==iCur );
     assert( omitTable==0 );
     assert( pTerm->pExpr!=0 );
     assert( pTerm->leftCursor==iCur );
     assert( omitTable==0 );

+    testcase( pTerm->wtFlags & TERM_VIRTUAL ); /* EV: R-30575-11662 */

     iRowidReg = codeEqualityTerm(pParse, pTerm, pLevel, iReleaseReg);
     addrNxt = pLevel->addrNxt;
     sqlite3VdbeAddOp2(v, OP_MustBeInt, iRowidReg, addrNxt);
     iRowidReg = codeEqualityTerm(pParse, pTerm, pLevel, iReleaseReg);
     addrNxt = pLevel->addrNxt;
     sqlite3VdbeAddOp2(v, OP_MustBeInt, iRowidReg, addrNxt);


@@ -96576,6 +97486,7 @@ static Bitmask codeOneLoopStart(
       assert( TK_LT==TK_GT+2 );      /*  ... of the TK_xx values... */
       assert( TK_GE==TK_GT+3 );      /*  ... is correcct. */
 
       assert( TK_LT==TK_GT+2 );      /*  ... of the TK_xx values... */
       assert( TK_GE==TK_GT+3 );      /*  ... is correcct. */
 

+      testcase( pStart->wtFlags & TERM_VIRTUAL ); /* EV: R-30575-11662 */

       pX = pStart->pExpr;
       assert( pX!=0 );
       assert( pStart->leftCursor==iCur );
       pX = pStart->pExpr;
       assert( pX!=0 );
       assert( pStart->leftCursor==iCur );


@@ -96593,6 +97504,7 @@ static Bitmask codeOneLoopStart(
       pX = pEnd->pExpr;
       assert( pX!=0 );
       assert( pEnd->leftCursor==iCur );
       pX = pEnd->pExpr;
       assert( pX!=0 );
       assert( pEnd->leftCursor==iCur );

+      testcase( pEnd->wtFlags & TERM_VIRTUAL ); /* EV: R-30575-11662 */

       memEndValue = ++pParse->nMem;
       sqlite3ExprCode(pParse, pX->pRight, memEndValue);
       if( pX->op==TK_LT || pX->op==TK_GT ){
       memEndValue = ++pParse->nMem;
       sqlite3ExprCode(pParse, pX->pRight, memEndValue);
       if( pX->op==TK_LT || pX->op==TK_GT ){


@@ -96650,7 +97562,7 @@ static Bitmask codeOneLoopStart(
     **         constraints but an index is selected anyway, in order
     **         to force the output order to conform to an ORDER BY.
     */  
     **         constraints but an index is selected anyway, in order
     **         to force the output order to conform to an ORDER BY.
     */  

-    int aStartOp[] = {
+    static const u8 aStartOp[] = {

       0,
       0,
       OP_Rewind,           /* 2: (!start_constraints && startEq &&  !bRev) */
       0,
       0,
       OP_Rewind,           /* 2: (!start_constraints && startEq &&  !bRev) */


@@ -96660,12 +97572,12 @@ static Bitmask codeOneLoopStart(
       OP_SeekGe,           /* 6: (start_constraints  &&  startEq && !bRev) */
       OP_SeekLe            /* 7: (start_constraints  &&  startEq &&  bRev) */
     };
       OP_SeekGe,           /* 6: (start_constraints  &&  startEq && !bRev) */
       OP_SeekLe            /* 7: (start_constraints  &&  startEq &&  bRev) */
     };

-    int aEndOp[] = {
+    static const u8 aEndOp[] = {

       OP_Noop,             /* 0: (!end_constraints) */
       OP_IdxGE,            /* 1: (end_constraints && !bRev) */
       OP_IdxLT             /* 2: (end_constraints && bRev) */
     };
       OP_Noop,             /* 0: (!end_constraints) */
       OP_IdxGE,            /* 1: (end_constraints && !bRev) */
       OP_IdxLT             /* 2: (end_constraints && bRev) */
     };

-    int nEq = pLevel->plan.nEq;
+    int nEq = pLevel->plan.nEq;  /* Number of == or IN terms */

     int isMinQuery = 0;          /* If this is an optimized SELECT min(x).. */
     int regBase;                 /* Base register holding constraint values */
     int r1;                      /* Temp register */
     int isMinQuery = 0;          /* If this is an optimized SELECT min(x).. */
     int regBase;                 /* Base register holding constraint values */
     int r1;                      /* Temp register */


@@ -96675,10 +97587,10 @@ static Bitmask codeOneLoopStart(
     int endEq;                   /* True if range end uses ==, >= or <= */
     int start_constraints;       /* Start of range is constrained */
     int nConstraint;             /* Number of constraint terms */
     int endEq;                   /* True if range end uses ==, >= or <= */
     int start_constraints;       /* Start of range is constrained */
     int nConstraint;             /* Number of constraint terms */

-    Index *pIdx;         /* The index we will be using */
-    int iIdxCur;         /* The VDBE cursor for the index */
-    int nExtraReg = 0;   /* Number of extra registers needed */
-    int op;              /* Instruction opcode */
+    Index *pIdx;                 /* The index we will be using */
+    int iIdxCur;                 /* The VDBE cursor for the index */
+    int nExtraReg = 0;           /* Number of extra registers needed */
+    int op;                      /* Instruction opcode */

     char *zStartAff;             /* Affinity for start of range constraint */
     char *zEndAff;               /* Affinity for end of range constraint */
 
     char *zStartAff;             /* Affinity for start of range constraint */
     char *zEndAff;               /* Affinity for end of range constraint */
 


@@ -96760,6 +97672,7 @@ static Bitmask codeOneLoopStart(
         }
       }  
       nConstraint++;
         }
       }  
       nConstraint++;

+      testcase( pRangeStart->wtFlags & TERM_VIRTUAL ); /* EV: R-30575-11662 */

     }else if( isMinQuery ){
       sqlite3VdbeAddOp2(v, OP_Null, 0, regBase+nEq);
       nConstraint++;
     }else if( isMinQuery ){
       sqlite3VdbeAddOp2(v, OP_Null, 0, regBase+nEq);
       nConstraint++;


@@ -96799,6 +97712,7 @@ static Bitmask codeOneLoopStart(
       }  
       codeApplyAffinity(pParse, regBase, nEq+1, zEndAff);
       nConstraint++;
       }  
       codeApplyAffinity(pParse, regBase, nEq+1, zEndAff);
       nConstraint++;

+      testcase( pRangeEnd->wtFlags & TERM_VIRTUAL ); /* EV: R-30575-11662 */

     }
     sqlite3DbFree(pParse->db, zStartAff);
     sqlite3DbFree(pParse->db, zEndAff);
     }
     sqlite3DbFree(pParse->db, zStartAff);
     sqlite3DbFree(pParse->db, zEndAff);


@@ -97005,11 +97919,15 @@ static Bitmask codeOneLoopStart(
 
   /* Insert code to test every subexpression that can be completely
   ** computed using the current set of tables.
 
   /* Insert code to test every subexpression that can be completely
   ** computed using the current set of tables.

+  **
+  ** IMPLEMENTATION-OF: R-49525-50935 Terms that cannot be satisfied through
+  ** the use of indices become tests that are evaluated against each row of
+  ** the relevant input tables.

   */
   k = 0;
   for(pTerm=pWC->a, j=pWC->nTerm; j>0; j--, pTerm++){
     Expr *pE;
   */
   k = 0;
   for(pTerm=pWC->a, j=pWC->nTerm; j>0; j--, pTerm++){
     Expr *pE;

-    testcase( pTerm->wtFlags & TERM_VIRTUAL );
+    testcase( pTerm->wtFlags & TERM_VIRTUAL ); /* IMP: R-30575-11662 */

     testcase( pTerm->wtFlags & TERM_CODED );
     if( pTerm->wtFlags & (TERM_VIRTUAL|TERM_CODED) ) continue;
     if( (pTerm->prereqAll & notReady)!=0 ){
     testcase( pTerm->wtFlags & TERM_CODED );
     if( pTerm->wtFlags & (TERM_VIRTUAL|TERM_CODED) ) continue;
     if( (pTerm->prereqAll & notReady)!=0 ){


@@ -97037,7 +97955,7 @@ static Bitmask codeOneLoopStart(
     VdbeComment((v, "record LEFT JOIN hit"));
     sqlite3ExprCacheClear(pParse);
     for(pTerm=pWC->a, j=0; j<pWC->nTerm; j++, pTerm++){
     VdbeComment((v, "record LEFT JOIN hit"));
     sqlite3ExprCacheClear(pParse);
     for(pTerm=pWC->a, j=0; j<pWC->nTerm; j++, pTerm++){

-      testcase( pTerm->wtFlags & TERM_VIRTUAL );
+      testcase( pTerm->wtFlags & TERM_VIRTUAL );  /* IMP: R-30575-11662 */

       testcase( pTerm->wtFlags & TERM_CODED );
       if( pTerm->wtFlags & (TERM_VIRTUAL|TERM_CODED) ) continue;
       if( (pTerm->prereqAll & notReady)!=0 ){
       testcase( pTerm->wtFlags & TERM_CODED );
       if( pTerm->wtFlags & (TERM_VIRTUAL|TERM_CODED) ) continue;
       if( (pTerm->prereqAll & notReady)!=0 ){


@@ -97255,7 +98173,7 @@ SQLITE_PRIVATE WhereInfo *sqlite3WhereBegin(
   initMaskSet(pMaskSet);
   whereClauseInit(pWC, pParse, pMaskSet);
   sqlite3ExprCodeConstants(pParse, pWhere);
   initMaskSet(pMaskSet);
   whereClauseInit(pWC, pParse, pMaskSet);
   sqlite3ExprCodeConstants(pParse, pWhere);

-  whereSplit(pWC, pWhere, TK_AND);
+  whereSplit(pWC, pWhere, TK_AND);   /* IMP: R-15842-53296 */

     
   /* Special case: a WHERE clause that is constant.  Evaluate the
   ** expression and either jump over all of the code or fall thru.
     
   /* Special case: a WHERE clause that is constant.  Evaluate the
   ** expression and either jump over all of the code or fall thru.


@@ -97343,6 +98261,8 @@ SQLITE_PRIVATE WhereInfo *sqlite3WhereBegin(
     int bestJ = -1;             /* The value of j */
     Bitmask m;                  /* Bitmask value for j or bestJ */
     int isOptimal;              /* Iterator for optimal/non-optimal search */
     int bestJ = -1;             /* The value of j */
     Bitmask m;                  /* Bitmask value for j or bestJ */
     int isOptimal;              /* Iterator for optimal/non-optimal search */

+    int nUnconstrained;         /* Number tables without INDEXED BY */
+    Bitmask notIndexed;         /* Mask of tables that cannot use an index */

 
     memset(&bestPlan, 0, sizeof(bestPlan));
     bestPlan.rCost = SQLITE_BIG_DBL;
 
     memset(&bestPlan, 0, sizeof(bestPlan));
     bestPlan.rCost = SQLITE_BIG_DBL;


@@ -97384,8 +98304,10 @@ SQLITE_PRIVATE WhereInfo *sqlite3WhereBegin(
     ** algorithm may choose to use t2 for the outer loop, which is a much
     ** costlier approach.
     */
     ** algorithm may choose to use t2 for the outer loop, which is a much
     ** costlier approach.
     */

+    nUnconstrained = 0;
+    notIndexed = 0;

     for(isOptimal=(iFrom<nTabList-1); isOptimal>=0; isOptimal--){
     for(isOptimal=(iFrom<nTabList-1); isOptimal>=0; isOptimal--){

-      Bitmask mask;  /* Mask of tables not yet ready */
+      Bitmask mask;             /* Mask of tables not yet ready */

       for(j=iFrom, pTabItem=&pTabList->a[j]; j<nTabList; j++, pTabItem++){
         int doNotReorder;    /* True if this table should not be reordered */
         WhereCost sCost;     /* Cost information from best[Virtual]Index() */
       for(j=iFrom, pTabItem=&pTabList->a[j]; j<nTabList; j++, pTabItem++){
         int doNotReorder;    /* True if this table should not be reordered */
         WhereCost sCost;     /* Cost information from best[Virtual]Index() */


@@ -97400,6 +98322,7 @@ SQLITE_PRIVATE WhereInfo *sqlite3WhereBegin(
         }
         mask = (isOptimal ? m : notReady);
         pOrderBy = ((i==0 && ppOrderBy )?*ppOrderBy:0);
         }
         mask = (isOptimal ? m : notReady);
         pOrderBy = ((i==0 && ppOrderBy )?*ppOrderBy:0);

+        if( pTabItem->pIndex==0 ) nUnconstrained++;

   
         assert( pTabItem->pTab );
 #ifndef SQLITE_OMIT_VIRTUALTABLE
   
         assert( pTabItem->pTab );
 #ifndef SQLITE_OMIT_VIRTUALTABLE


@@ -97413,9 +98336,43 @@ SQLITE_PRIVATE WhereInfo *sqlite3WhereBegin(
         }
         assert( isOptimal || (sCost.used&notReady)==0 );
 
         }
         assert( isOptimal || (sCost.used&notReady)==0 );
 

-        if( (sCost.used&notReady)==0
-         && (bestJ<0 || sCost.rCost<bestPlan.rCost
-             || (sCost.rCost<=bestPlan.rCost && sCost.nRow<bestPlan.nRow))
+        /* If an INDEXED BY clause is present, then the plan must use that
+        ** index if it uses any index at all */
+        assert( pTabItem->pIndex==0 
+                  || (sCost.plan.wsFlags & WHERE_NOT_FULLSCAN)==0
+                  || sCost.plan.u.pIdx==pTabItem->pIndex );
+
+        if( isOptimal && (sCost.plan.wsFlags & WHERE_NOT_FULLSCAN)==0 ){
+          notIndexed |= m;
+        }
+
+        /* Conditions under which this table becomes the best so far:
+        **
+        **   (1) The table must not depend on other tables that have not
+        **       yet run.
+        **
+        **   (2) A full-table-scan plan cannot supercede another plan unless
+        **       it is an "optimal" plan as defined above.
+        **
+        **   (3) All tables have an INDEXED BY clause or this table lacks an
+        **       INDEXED BY clause or this table uses the specific
+        **       index specified by its INDEXED BY clause.  This rule ensures
+        **       that a best-so-far is always selected even if an impossible
+        **       combination of INDEXED BY clauses are given.  The error
+        **       will be detected and relayed back to the application later.
+        **       The NEVER() comes about because rule (2) above prevents
+        **       An indexable full-table-scan from reaching rule (3).
+        **
+        **   (4) The plan cost must be lower than prior plans or else the
+        **       cost must be the same and the number of rows must be lower.
+        */
+        if( (sCost.used&notReady)==0                       /* (1) */
+            && (bestJ<0 || (notIndexed&m)!=0               /* (2) */
+                || (sCost.plan.wsFlags & WHERE_NOT_FULLSCAN)!=0)
+            && (nUnconstrained==0 || pTabItem->pIndex==0   /* (3) */
+                || NEVER((sCost.plan.wsFlags & WHERE_NOT_FULLSCAN)!=0))
+            && (bestJ<0 || sCost.rCost<bestPlan.rCost      /* (4) */
+                || (sCost.rCost<=bestPlan.rCost && sCost.nRow<bestPlan.nRow))

         ){
           WHERETRACE(("... best so far with cost=%g and nRow=%g\n",
                       sCost.rCost, sCost.nRow));
         ){
           WHERETRACE(("... best so far with cost=%g and nRow=%g\n",
                       sCost.rCost, sCost.nRow));


@@ -100430,7 +101387,7 @@ static void yy_reduce(
         break;
       case 195: /* expr ::= expr COLLATE ids */
 {
         break;
       case 195: /* expr ::= expr COLLATE ids */
 {

-  yygotominor.yy118.pExpr = sqlite3ExprSetColl(pParse, yymsp[-2].minor.yy118.pExpr, &yymsp[0].minor.yy0);
+  yygotominor.yy118.pExpr = sqlite3ExprSetCollByToken(pParse, yymsp[-2].minor.yy118.pExpr, &yymsp[0].minor.yy0);

   yygotominor.yy118.zStart = yymsp[-2].minor.yy118.zStart;
   yygotominor.yy118.zEnd = &yymsp[0].minor.yy0.z[yymsp[0].minor.yy0.n];
 }
   yygotominor.yy118.zStart = yymsp[-2].minor.yy118.zStart;
   yygotominor.yy118.zEnd = &yymsp[0].minor.yy0.z[yymsp[0].minor.yy0.n];
 }


@@ -100686,7 +101643,7 @@ static void yy_reduce(
   Expr *p = 0;
   if( yymsp[-1].minor.yy0.n>0 ){
     p = sqlite3Expr(pParse->db, TK_COLUMN, 0);
   Expr *p = 0;
   if( yymsp[-1].minor.yy0.n>0 ){
     p = sqlite3Expr(pParse->db, TK_COLUMN, 0);

-    sqlite3ExprSetColl(pParse, p, &yymsp[-1].minor.yy0);
+    sqlite3ExprSetCollByToken(pParse, p, &yymsp[-1].minor.yy0);

   }
   yygotominor.yy322 = sqlite3ExprListAppend(pParse,yymsp[-4].minor.yy322, p);
   sqlite3ExprListSetName(pParse,yygotominor.yy322,&yymsp[-2].minor.yy0,1);
   }
   yygotominor.yy322 = sqlite3ExprListAppend(pParse,yymsp[-4].minor.yy322, p);
   sqlite3ExprListSetName(pParse,yygotominor.yy322,&yymsp[-2].minor.yy0,1);


@@ -100699,7 +101656,7 @@ static void yy_reduce(
   Expr *p = 0;
   if( yymsp[-1].minor.yy0.n>0 ){
     p = sqlite3PExpr(pParse, TK_COLUMN, 0, 0, 0);
   Expr *p = 0;
   if( yymsp[-1].minor.yy0.n>0 ){
     p = sqlite3PExpr(pParse, TK_COLUMN, 0, 0, 0);

-    sqlite3ExprSetColl(pParse, p, &yymsp[-1].minor.yy0);
+    sqlite3ExprSetCollByToken(pParse, p, &yymsp[-1].minor.yy0);

   }
   yygotominor.yy322 = sqlite3ExprListAppend(pParse,0, p);
   sqlite3ExprListSetName(pParse, yygotominor.yy322, &yymsp[-2].minor.yy0, 1);
   }
   yygotominor.yy322 = sqlite3ExprListAppend(pParse,0, p);
   sqlite3ExprListSetName(pParse, yygotominor.yy322, &yymsp[-2].minor.yy0, 1);


@@ -101979,7 +102936,7 @@ abort_parse:
   }
 #endif
 #ifndef SQLITE_OMIT_VIRTUALTABLE
   }
 #endif
 #ifndef SQLITE_OMIT_VIRTUALTABLE

-  sqlite3DbFree(db, pParse->apVtabLock);
+  sqlite3_free(pParse->apVtabLock);

 #endif
 
   if( !IN_DECLARE_VTAB ){
 #endif
 
   if( !IN_DECLARE_VTAB ){


@@ -101987,7 +102944,7 @@ abort_parse:
     ** structure built up in pParse->pNewTable. The calling code (see vtab.c)
     ** will take responsibility for freeing the Table structure.
     */
     ** structure built up in pParse->pNewTable. The calling code (see vtab.c)
     ** will take responsibility for freeing the Table structure.
     */

-    sqlite3DeleteTable(pParse->pNewTable);
+    sqlite3DeleteTable(db, pParse->pNewTable);

   }
 
   sqlite3DeleteTrigger(db, pParse->pNewTrigger);
   }
 
   sqlite3DeleteTrigger(db, pParse->pNewTrigger);


@@ -102001,7 +102958,7 @@ abort_parse:
   while( pParse->pZombieTab ){
     Table *p = pParse->pZombieTab;
     pParse->pZombieTab = p->pNextZombie;
   while( pParse->pZombieTab ){
     Table *p = pParse->pZombieTab;
     pParse->pZombieTab = p->pNextZombie;

-    sqlite3DeleteTable(p);
+    sqlite3DeleteTable(db, p);

   }
   if( nErr>0 && pParse->rc==SQLITE_OK ){
     pParse->rc = SQLITE_ERROR;
   }
   if( nErr>0 && pParse->rc==SQLITE_OK ){
     pParse->rc = SQLITE_ERROR;


@@ -103693,16 +104650,7 @@ SQLITE_PRIVATE int sqlite3Checkpoint(sqlite3 *db, int iDb){
 
   for(i=0; i<db->nDb && rc==SQLITE_OK; i++){
     if( i==iDb || iDb==SQLITE_MAX_ATTACHED ){
 
   for(i=0; i<db->nDb && rc==SQLITE_OK; i++){
     if( i==iDb || iDb==SQLITE_MAX_ATTACHED ){

-      Btree *pBt = db->aDb[i].pBt;
-      if( pBt ){
-        if( sqlite3BtreeIsInReadTrans(pBt) ){
-          rc = SQLITE_LOCKED;
-        }else{
-          sqlite3BtreeEnter(pBt);
-          rc = sqlite3PagerCheckpoint(sqlite3BtreePager(pBt));
-          sqlite3BtreeLeave(pBt);
-        }
-      }
+      rc = sqlite3BtreeCheckpoint(db->aDb[i].pBt);

     }
   }
 
     }
   }
 


@@ -105151,7 +106099,7 @@ SQLITE_PRIVATE void sqlite3ConnectionUnlocked(sqlite3 *db){
       assert( aArg==aDyn || (aDyn==0 && aArg==aStatic) );
       assert( nArg<=(int)ArraySize(aStatic) || aArg==aDyn );
       if( (!aDyn && nArg==(int)ArraySize(aStatic))
       assert( aArg==aDyn || (aDyn==0 && aArg==aStatic) );
       assert( nArg<=(int)ArraySize(aStatic) || aArg==aDyn );
       if( (!aDyn && nArg==(int)ArraySize(aStatic))

-       || (aDyn && nArg==(int)(sqlite3DbMallocSize(db, aDyn)/sizeof(void*)))
+       || (aDyn && nArg==(int)(sqlite3MallocSize(aDyn)/sizeof(void*)))

       ){
         /* The aArg[] array needs to grow. */
         void **pNew = (void **)sqlite3Malloc(nArg*sizeof(void *)*2);
       ){
         /* The aArg[] array needs to grow. */
         void **pNew = (void **)sqlite3Malloc(nArg*sizeof(void *)*2);


@@ -108475,7 +109423,7 @@ static void hashDestroy(void *p){
 ** used to retrieve the respective implementations.
 **
 ** Calling sqlite3Fts3SimpleTokenizerModule() sets the value pointed
 ** used to retrieve the respective implementations.
 **
 ** Calling sqlite3Fts3SimpleTokenizerModule() sets the value pointed

-** to by the argument to point a the "simple" tokenizer implementation.
+** to by the argument to point to the "simple" tokenizer implementation.

 ** Function ...PorterTokenizerModule() sets *pModule to point to the
 ** porter tokenizer/stemmer implementation.
 */
 ** Function ...PorterTokenizerModule() sets *pModule to point to the
 ** porter tokenizer/stemmer implementation.
 */


@@ -108677,7 +109625,7 @@ struct ParseContext {
 ** negative values).
 */
 static int fts3isspace(char c){
 ** negative values).
 */
 static int fts3isspace(char c){

-  return (c&0x80)==0 ? isspace(c) : 0;
+  return c==' ' || c=='\t' || c=='\n' || c=='\r' || c=='\v' || c=='\f';

 }
 
 /*
 }
 
 /*


@@ -111064,6 +112012,9 @@ typedef struct simple_tokenizer_cursor {
 static int simpleDelim(simple_tokenizer *t, unsigned char c){
   return c<0x80 && t->delim[c];
 }
 static int simpleDelim(simple_tokenizer *t, unsigned char c){
   return c<0x80 && t->delim[c];
 }

+static int fts3_isalnum(int x){
+  return (x>='0' && x<='9') || (x>='A' && x<='Z') || (x>='a' && x<='z');
+}

 
 /*
 ** Create a new tokenizer instance.
 
 /*
 ** Create a new tokenizer instance.


@@ -111098,7 +112049,7 @@ static int simpleCreate(
     /* Mark non-alphanumeric ASCII characters as delimiters */
     int i;
     for(i=1; i<0x80; i++){
     /* Mark non-alphanumeric ASCII characters as delimiters */
     int i;
     for(i=1; i<0x80; i++){

-      t->delim[i] = !isalnum(i) ? -1 : 0;
+      t->delim[i] = !fts3_isalnum(i) ? -1 : 0;

     }
   }
 
     }
   }
 


@@ -111204,7 +112155,7 @@ static int simpleNext(
         ** case-insensitivity.
         */
         unsigned char ch = p[iStartOffset+i];
         ** case-insensitivity.
         */
         unsigned char ch = p[iStartOffset+i];

-        c->pToken[i] = (char)(ch<0x80 ? tolower(ch) : ch);
+        c->pToken[i] = (char)((ch>='A' && ch<='Z') ? ch-'A'+'a' : ch);

       }
       *ppToken = c->pToken;
       *pnBytes = n;
       }
       *ppToken = c->pToken;
       *pnBytes = n;


@@ -116110,11 +117061,10 @@ static int rtreeFilter(
 **   idxNum     idxStr        Strategy
 **   ------------------------------------------------
 **     1        Unused        Direct lookup by rowid.
 **   idxNum     idxStr        Strategy
 **   ------------------------------------------------
 **     1        Unused        Direct lookup by rowid.

-**     2        See below     R-tree query.
-**     3        Unused        Full table scan.
+**     2        See below     R-tree query or full-table scan.

 **   ------------------------------------------------
 **
 **   ------------------------------------------------
 **

-** If strategy 1 or 3 is used, then idxStr is not meaningful. If strategy
+** If strategy 1 is used, then idxStr is not meaningful. If strategy

 ** 2 is used, idxStr is formatted to contain 2 bytes for each 
 ** constraint used. The first two bytes of idxStr correspond to 
 ** the constraint in sqlite3_index_info.aConstraintUsage[] with
 ** 2 is used, idxStr is formatted to contain 2 bytes for each 
 ** constraint used. The first two bytes of idxStr correspond to 
 ** the constraint in sqlite3_index_info.aConstraintUsage[] with

diff --git a/l4/pkg/sqlite/lib/contrib/sqlite3.h b/l4/pkg/sqlite/lib/contrib/sqlite3.h
index 3d02c7cca6849bbc826133ba313eeb12f8094da3..ceca47ab3d240af248bd58afaeae95f32d4c9ca1 100644 (file)
--- a/l4/pkg/sqlite/lib/contrib/sqlite3.h
+++ b/l4/pkg/sqlite/lib/contrib/sqlite3.h
@@ -97,7 +97,7 @@ extern "C" {
 **
 ** Since version 3.6.18, SQLite source code has been stored in the
 ** <a href="http://www.fossil-scm.org/">Fossil configuration management
 **
 ** Since version 3.6.18, SQLite source code has been stored in the
 ** <a href="http://www.fossil-scm.org/">Fossil configuration management

-** system</a>.  ^The SQLITE_SOURCE_ID macro evalutes to
+** system</a>.  ^The SQLITE_SOURCE_ID macro evaluates to

 ** a string which identifies a particular check-in of SQLite
 ** within its configuration management system.  ^The SQLITE_SOURCE_ID
 ** string contains the date and time of the check-in (UTC) and an SHA1
 ** a string which identifies a particular check-in of SQLite
 ** within its configuration management system.  ^The SQLITE_SOURCE_ID
 ** string contains the date and time of the check-in (UTC) and an SHA1


@@ -107,9 +107,9 @@ extern "C" {
 ** [sqlite3_libversion_number()], [sqlite3_sourceid()],
 ** [sqlite_version()] and [sqlite_source_id()].
 */
 ** [sqlite3_libversion_number()], [sqlite3_sourceid()],
 ** [sqlite_version()] and [sqlite_source_id()].
 */

-#define SQLITE_VERSION        "3.7.0.1"
-#define SQLITE_VERSION_NUMBER 3007000
-#define SQLITE_SOURCE_ID      "2010-08-04 12:31:11 042a1abb030a0711386add7eb6e10832cc8b0f57"
+#define SQLITE_VERSION        "3.7.2"
+#define SQLITE_VERSION_NUMBER 3007002
+#define SQLITE_SOURCE_ID      "2010-08-23 18:52:01 42537b60566f288167f1b5864a5435986838e3a3"

 
 /*
 ** CAPI3REF: Run-Time Library Version Numbers
 
 /*
 ** CAPI3REF: Run-Time Library Version Numbers


@@ -154,7 +154,7 @@ SQLITE_API int sqlite3_libversion_number(void);
 ** compile time.  ^The SQLITE_ prefix may be omitted from the 
 ** option name passed to sqlite3_compileoption_used().  
 **
 ** compile time.  ^The SQLITE_ prefix may be omitted from the 
 ** option name passed to sqlite3_compileoption_used().  
 **

-** ^The sqlite3_compileoption_get() function allows interating
+** ^The sqlite3_compileoption_get() function allows iterating

 ** over the list of options that were defined at compile time by
 ** returning the N-th compile time option string.  ^If N is out of range,
 ** sqlite3_compileoption_get() returns a NULL pointer.  ^The SQLITE_ 
 ** over the list of options that were defined at compile time by
 ** returning the N-th compile time option string.  ^If N is out of range,
 ** sqlite3_compileoption_get() returns a NULL pointer.  ^The SQLITE_ 


@@ -162,7 +162,7 @@ SQLITE_API int sqlite3_libversion_number(void);
 ** sqlite3_compileoption_get().
 **
 ** ^Support for the diagnostic functions sqlite3_compileoption_used()
 ** sqlite3_compileoption_get().
 **
 ** ^Support for the diagnostic functions sqlite3_compileoption_used()

-** and sqlite3_compileoption_get() may be omitted by specifing the 
+** and sqlite3_compileoption_get() may be omitted by specifying the 

 ** [SQLITE_OMIT_COMPILEOPTION_DIAGS] option at compile time.
 **
 ** See also: SQL functions [sqlite_compileoption_used()] and
 ** [SQLITE_OMIT_COMPILEOPTION_DIAGS] option at compile time.
 **
 ** See also: SQL functions [sqlite_compileoption_used()] and


@@ -268,7 +268,7 @@ typedef sqlite_uint64 sqlite3_uint64;
 **
 ** ^The sqlite3_close() routine is the destructor for the [sqlite3] object.
 ** ^Calls to sqlite3_close() return SQLITE_OK if the [sqlite3] object is
 **
 ** ^The sqlite3_close() routine is the destructor for the [sqlite3] object.
 ** ^Calls to sqlite3_close() return SQLITE_OK if the [sqlite3] object is

-** successfullly destroyed and all associated resources are deallocated.
+** successfully destroyed and all associated resources are deallocated.

 **
 ** Applications must [sqlite3_finalize | finalize] all [prepared statements]
 ** and [sqlite3_blob_close | close] all [BLOB handles] associated with
 **
 ** Applications must [sqlite3_finalize | finalize] all [prepared statements]
 ** and [sqlite3_blob_close | close] all [BLOB handles] associated with


@@ -695,12 +695,21 @@ struct sqlite3_io_methods {
 ** is often close.  The underlying VFS might choose to preallocate database
 ** file space based on this hint in order to help writes to the database
 ** file run faster.
 ** is often close.  The underlying VFS might choose to preallocate database
 ** file space based on this hint in order to help writes to the database
 ** file run faster.

+**
+** The [SQLITE_FCNTL_CHUNK_SIZE] opcode is used to request that the VFS
+** extends and truncates the database file in chunks of a size specified
+** by the user. The fourth argument to [sqlite3_file_control()] should 
+** point to an integer (type int) containing the new chunk-size to use
+** for the nominated database. Allocating database file space in large
+** chunks (say 1MB at a time), may reduce file-system fragmentation and
+** improve performance on some systems.

 */
 #define SQLITE_FCNTL_LOCKSTATE        1
 #define SQLITE_GET_LOCKPROXYFILE      2
 #define SQLITE_SET_LOCKPROXYFILE      3
 #define SQLITE_LAST_ERRNO             4
 #define SQLITE_FCNTL_SIZE_HINT        5
 */
 #define SQLITE_FCNTL_LOCKSTATE        1
 #define SQLITE_GET_LOCKPROXYFILE      2
 #define SQLITE_SET_LOCKPROXYFILE      3
 #define SQLITE_LAST_ERRNO             4
 #define SQLITE_FCNTL_SIZE_HINT        5

+#define SQLITE_FCNTL_CHUNK_SIZE       6

 
 /*
 ** CAPI3REF: Mutex Handle
 
 /*
 ** CAPI3REF: Mutex Handle


@@ -2176,7 +2185,13 @@ SQLITE_API int sqlite3_set_authorizer(
 ** ^The callback function registered by sqlite3_profile() is invoked
 ** as each SQL statement finishes.  ^The profile callback contains
 ** the original statement text and an estimate of wall-clock time
 ** ^The callback function registered by sqlite3_profile() is invoked
 ** as each SQL statement finishes.  ^The profile callback contains
 ** the original statement text and an estimate of wall-clock time

-** of how long that statement took to run.
+** of how long that statement took to run.  ^The profile callback
+** time is in units of nanoseconds, however the current implementation
+** is only capable of millisecond resolution so the six least significant
+** digits in the time are meaningless.  Future versions of SQLite
+** might provide greater resolution on the profiler callback.  The
+** sqlite3_profile() function is considered experimental and is
+** subject to change in future versions of SQLite.

 */
 SQLITE_API void *sqlite3_trace(sqlite3*, void(*xTrace)(void*,const char*), void*);
 SQLITE_API SQLITE_EXPERIMENTAL void *sqlite3_profile(sqlite3*,
 */
 SQLITE_API void *sqlite3_trace(sqlite3*, void(*xTrace)(void*,const char*), void*);
 SQLITE_API SQLITE_EXPERIMENTAL void *sqlite3_profile(sqlite3*,


@@ -2657,7 +2672,7 @@ typedef struct sqlite3_context sqlite3_context;
 ** </ul>
 **
 ** In the templates above, NNN represents an integer literal,
 ** </ul>
 **
 ** In the templates above, NNN represents an integer literal,

-** and VVV represents an alphanumeric identifer.)^  ^The values of these
+** and VVV represents an alphanumeric identifier.)^  ^The values of these

 ** parameters (also called "host parameter names" or "SQL parameters")
 ** can be set using the sqlite3_bind_*() routines defined here.
 **
 ** parameters (also called "host parameter names" or "SQL parameters")
 ** can be set using the sqlite3_bind_*() routines defined here.
 **


@@ -3436,7 +3451,7 @@ SQLITE_API int sqlite3_value_numeric_type(sqlite3_value*);
 /*
 ** CAPI3REF: Obtain Aggregate Function Context
 **
 /*
 ** CAPI3REF: Obtain Aggregate Function Context
 **

-** Implementions of aggregate SQL functions use this
+** Implementations of aggregate SQL functions use this

 ** routine to allocate memory for storing their state.
 **
 ** ^The first time the sqlite3_aggregate_context(C,N) routine is called 
 ** routine to allocate memory for storing their state.
 **
 ** ^The first time the sqlite3_aggregate_context(C,N) routine is called 


@@ -3708,7 +3723,7 @@ SQLITE_API void sqlite3_result_zeroblob(sqlite3_context*, int n);
 **
 ** A pointer to the user supplied routine must be passed as the fifth
 ** argument.  ^If it is NULL, this is the same as deleting the collation
 **
 ** A pointer to the user supplied routine must be passed as the fifth
 ** argument.  ^If it is NULL, this is the same as deleting the collation

-** sequence (so that SQLite cannot call it anymore).
+** sequence (so that SQLite cannot call it any more).

 ** ^Each time the application supplied function is invoked, it is passed
 ** as its first parameter a copy of the void* passed as the fourth argument
 ** to sqlite3_create_collation() or sqlite3_create_collation16().
 ** ^Each time the application supplied function is invoked, it is passed
 ** as its first parameter a copy of the void* passed as the fourth argument
 ** to sqlite3_create_collation() or sqlite3_create_collation16().


@@ -4325,7 +4340,8 @@ struct sqlite3_module {
 ** CAPI3REF: Virtual Table Indexing Information
 ** KEYWORDS: sqlite3_index_info
 **
 ** CAPI3REF: Virtual Table Indexing Information
 ** KEYWORDS: sqlite3_index_info
 **

-** The sqlite3_index_info structure and its substructures is used to
+** The sqlite3_index_info structure and its substructures is used as part
+** of the [virtual table] interface to

 ** pass information into and receive the reply from the [xBestIndex]
 ** method of a [virtual table module].  The fields under **Inputs** are the
 ** inputs to xBestIndex and are read-only.  xBestIndex inserts its
 ** pass information into and receive the reply from the [xBestIndex]
 ** method of a [virtual table module].  The fields under **Inputs** are the
 ** inputs to xBestIndex and are read-only.  xBestIndex inserts its


@@ -4333,10 +4349,12 @@ struct sqlite3_module {
 **
 ** ^(The aConstraint[] array records WHERE clause constraints of the form:
 **
 **
 ** ^(The aConstraint[] array records WHERE clause constraints of the form:
 **

-** <pre>column OP expr</pre>
+** <blockquote>column OP expr</blockquote>

 **
 ** where OP is =, &lt;, &lt;=, &gt;, or &gt;=.)^  ^(The particular operator is
 **
 ** where OP is =, &lt;, &lt;=, &gt;, or &gt;=.)^  ^(The particular operator is

-** stored in aConstraint[].op.)^  ^(The index of the column is stored in
+** stored in aConstraint[].op using one of the
+** [SQLITE_INDEX_CONSTRAINT_EQ | SQLITE_INDEX_CONSTRAINT_ values].)^
+** ^(The index of the column is stored in

 ** aConstraint[].iColumn.)^  ^(aConstraint[].usable is TRUE if the
 ** expr on the right-hand side can be evaluated (and thus the constraint
 ** is usable) and false if it cannot.)^
 ** aConstraint[].iColumn.)^  ^(aConstraint[].usable is TRUE if the
 ** expr on the right-hand side can be evaluated (and thus the constraint
 ** is usable) and false if it cannot.)^


@@ -4396,6 +4414,15 @@ struct sqlite3_index_info {
   int orderByConsumed;       /* True if output is already ordered */
   double estimatedCost;      /* Estimated cost of using this index */
 };
   int orderByConsumed;       /* True if output is already ordered */
   double estimatedCost;      /* Estimated cost of using this index */
 };

+
+/*
+** CAPI3REF: Virtual Table Constraint Operator Codes
+**
+** These macros defined the allowed values for the
+** [sqlite3_index_info].aConstraint[].op field.  Each value represents
+** an operator that is part of a constraint term in the wHERE clause of
+** a query that uses a [virtual table].
+*/

 #define SQLITE_INDEX_CONSTRAINT_EQ    2
 #define SQLITE_INDEX_CONSTRAINT_GT    4
 #define SQLITE_INDEX_CONSTRAINT_LE    8
 #define SQLITE_INDEX_CONSTRAINT_EQ    2
 #define SQLITE_INDEX_CONSTRAINT_GT    4
 #define SQLITE_INDEX_CONSTRAINT_LE    8


@@ -4914,7 +4941,7 @@ SQLITE_API void sqlite3_mutex_leave(sqlite3_mutex*);
 ** it is passed a NULL pointer).
 **
 ** The xMutexInit() method must be threadsafe.  ^It must be harmless to
 ** it is passed a NULL pointer).
 **
 ** The xMutexInit() method must be threadsafe.  ^It must be harmless to

-** invoke xMutexInit() mutiple times within the same process and without
+** invoke xMutexInit() multiple times within the same process and without

 ** intervening calls to xMutexEnd().  Second and subsequent calls to
 ** xMutexInit() must be no-ops.
 **
 ** intervening calls to xMutexEnd().  Second and subsequent calls to
 ** xMutexInit() must be no-ops.
 **


@@ -5084,7 +5111,7 @@ SQLITE_API int sqlite3_test_control(int op, ...);
 ** CAPI3REF: SQLite Runtime Status
 **
 ** ^This interface is used to retrieve runtime status information
 ** CAPI3REF: SQLite Runtime Status
 **
 ** ^This interface is used to retrieve runtime status information

-** about the preformance of SQLite, and optionally to reset various
+** about the performance of SQLite, and optionally to reset various

 ** highwater marks.  ^The first argument is an integer code for
 ** the specific parameter to measure.  ^(Recognized integer codes
 ** are of the form [SQLITE_STATUS_MEMORY_USED | SQLITE_STATUS_...].)^
 ** highwater marks.  ^The first argument is an integer code for
 ** the specific parameter to measure.  ^(Recognized integer codes
 ** are of the form [SQLITE_STATUS_MEMORY_USED | SQLITE_STATUS_...].)^


@@ -5136,6 +5163,9 @@ SQLITE_API int sqlite3_status(int op, int *pCurrent, int *pHighwater, int resetF
 ** *pHighwater parameter to [sqlite3_status()] is of interest.  
 ** The value written into the *pCurrent parameter is undefined.</dd>)^
 **
 ** *pHighwater parameter to [sqlite3_status()] is of interest.  
 ** The value written into the *pCurrent parameter is undefined.</dd>)^
 **

+** ^(<dt>SQLITE_STATUS_MALLOC_COUNT</dt>
+** <dd>This parameter records the number of separate memory allocations.</dd>)^
+**

 ** ^(<dt>SQLITE_STATUS_PAGECACHE_USED</dt>
 ** <dd>This parameter returns the number of pages used out of the
 ** [pagecache memory allocator] that was configured using 
 ** ^(<dt>SQLITE_STATUS_PAGECACHE_USED</dt>
 ** <dd>This parameter returns the number of pages used out of the
 ** [pagecache memory allocator] that was configured using 


@@ -5197,6 +5227,7 @@ SQLITE_API int sqlite3_status(int op, int *pCurrent, int *pHighwater, int resetF
 #define SQLITE_STATUS_PARSER_STACK         6
 #define SQLITE_STATUS_PAGECACHE_SIZE       7
 #define SQLITE_STATUS_SCRATCH_SIZE         8
 #define SQLITE_STATUS_PARSER_STACK         6
 #define SQLITE_STATUS_PAGECACHE_SIZE       7
 #define SQLITE_STATUS_SCRATCH_SIZE         8

+#define SQLITE_STATUS_MALLOC_COUNT         9

 
 /*
 ** CAPI3REF: Database Connection Status
 
 /*
 ** CAPI3REF: Database Connection Status


@@ -5206,7 +5237,7 @@ SQLITE_API int sqlite3_status(int op, int *pCurrent, int *pHighwater, int resetF
 ** database connection object to be interrogated.  ^The second argument
 ** is an integer constant, taken from the set of
 ** [SQLITE_DBSTATUS_LOOKASIDE_USED | SQLITE_DBSTATUS_*] macros, that
 ** database connection object to be interrogated.  ^The second argument
 ** is an integer constant, taken from the set of
 ** [SQLITE_DBSTATUS_LOOKASIDE_USED | SQLITE_DBSTATUS_*] macros, that

-** determiness the parameter to interrogate.  The set of 
+** determines the parameter to interrogate.  The set of 

 ** [SQLITE_DBSTATUS_LOOKASIDE_USED | SQLITE_DBSTATUS_*] macros is likely
 ** to grow in future releases of SQLite.
 **
 ** [SQLITE_DBSTATUS_LOOKASIDE_USED | SQLITE_DBSTATUS_*] macros is likely
 ** to grow in future releases of SQLite.
 **


@@ -5236,16 +5267,33 @@ SQLITE_API int sqlite3_db_status(sqlite3*, int op, int *pCur, int *pHiwtr, int r
 ** <dd>This parameter returns the number of lookaside memory slots currently
 ** checked out.</dd>)^
 **
 ** <dd>This parameter returns the number of lookaside memory slots currently
 ** checked out.</dd>)^
 **

-** <dt>SQLITE_DBSTATUS_CACHE_USED</dt>
-** <dd>^This parameter returns the approximate number of of bytes of heap
-** memory used by all pager caches associated with the database connection.
+** ^(<dt>SQLITE_DBSTATUS_CACHE_USED</dt>
+** <dd>This parameter returns the approximate number of of bytes of heap
+** memory used by all pager caches associated with the database connection.)^

 ** ^The highwater mark associated with SQLITE_DBSTATUS_CACHE_USED is always 0.
 ** ^The highwater mark associated with SQLITE_DBSTATUS_CACHE_USED is always 0.

+**
+** ^(<dt>SQLITE_DBSTATUS_SCHEMA_USED</dt>
+** <dd>This parameter returns the approximate number of of bytes of heap
+** memory used to store the schema for all databases associated
+** with the connection - main, temp, and any [ATTACH]-ed databases.)^ 
+** ^The full amount of memory used by the schemas is reported, even if the
+** schema memory is shared with other database connections due to
+** [shared cache mode] being enabled.
+** ^The highwater mark associated with SQLITE_DBSTATUS_SCHEMA_USED is always 0.
+**
+** ^(<dt>SQLITE_DBSTATUS_STMT_USED</dt>
+** <dd>This parameter returns the approximate number of of bytes of heap
+** and lookaside memory used by all prepared statements associated with
+** the database connection.)^
+** ^The highwater mark associated with SQLITE_DBSTATUS_STMT_USED is always 0.

 ** </dd>
 ** </dl>
 */
 #define SQLITE_DBSTATUS_LOOKASIDE_USED     0
 #define SQLITE_DBSTATUS_CACHE_USED         1
 ** </dd>
 ** </dl>
 */
 #define SQLITE_DBSTATUS_LOOKASIDE_USED     0
 #define SQLITE_DBSTATUS_CACHE_USED         1

-#define SQLITE_DBSTATUS_MAX                1   /* Largest defined DBSTATUS */
+#define SQLITE_DBSTATUS_SCHEMA_USED        2
+#define SQLITE_DBSTATUS_STMT_USED          3
+#define SQLITE_DBSTATUS_MAX                3   /* Largest defined DBSTATUS */

 
 
 /*
 
 
 /*


@@ -5611,7 +5659,7 @@ typedef struct sqlite3_backup sqlite3_backup;
 **
 ** ^Each call to sqlite3_backup_step() sets two values inside
 ** the [sqlite3_backup] object: the number of pages still to be backed
 **
 ** ^Each call to sqlite3_backup_step() sets two values inside
 ** the [sqlite3_backup] object: the number of pages still to be backed

-** up and the total number of pages in the source databae file.
+** up and the total number of pages in the source database file.

 ** The sqlite3_backup_remaining() and sqlite3_backup_pagecount() interfaces
 ** retrieve these two values, respectively.
 **
 ** The sqlite3_backup_remaining() and sqlite3_backup_pagecount() interfaces
 ** retrieve these two values, respectively.
 **


@@ -5707,7 +5755,7 @@ SQLITE_API int sqlite3_backup_pagecount(sqlite3_backup *p);
 ** blocked connection already has a registered unlock-notify callback,
 ** then the new callback replaces the old.)^ ^If sqlite3_unlock_notify() is
 ** called with a NULL pointer as its second argument, then any existing
 ** blocked connection already has a registered unlock-notify callback,
 ** then the new callback replaces the old.)^ ^If sqlite3_unlock_notify() is
 ** called with a NULL pointer as its second argument, then any existing

-** unlock-notify callback is cancelled. ^The blocked connections 
+** unlock-notify callback is canceled. ^The blocked connections 

 ** unlock-notify callback may also be canceled by closing the blocked
 ** connection using [sqlite3_close()].
 **
 ** unlock-notify callback may also be canceled by closing the blocked
 ** connection using [sqlite3_close()].
 **


@@ -5789,7 +5837,7 @@ SQLITE_API int sqlite3_unlock_notify(
 **
 ** ^The [sqlite3_strnicmp()] API allows applications and extensions to
 ** compare the contents of two buffers containing UTF-8 strings in a
 **
 ** ^The [sqlite3_strnicmp()] API allows applications and extensions to
 ** compare the contents of two buffers containing UTF-8 strings in a

-** case-indendent fashion, using the same definition of case independence 
+** case-independent fashion, using the same definition of case independence 

 ** that SQLite uses internally when comparing identifiers.
 */
 SQLITE_API int sqlite3_strnicmp(const char *, const char *, int);
 ** that SQLite uses internally when comparing identifiers.
 */
 SQLITE_API int sqlite3_strnicmp(const char *, const char *, int);

diff --git a/l4/pkg/sqlite/lib/contrib/sqlite3.pc b/l4/pkg/sqlite/lib/contrib/sqlite3.pc
index 1beeefa92d00cecbe89f1b9a47d450afdaa8d9ed..dd023eea85efa6c7d34c44186eaa72a03bbb9d14 100644 (file)
--- a/l4/pkg/sqlite/lib/contrib/sqlite3.pc
+++ b/l4/pkg/sqlite/lib/contrib/sqlite3.pc
@@ -7,7 +7,7 @@ includedir=${prefix}/include
 
 Name: SQLite
 Description: SQL database engine
 
 Name: SQLite
 Description: SQL database engine

-Version: 3.7.0.1
+Version: 3.7.2

 Libs: -L${libdir} -lsqlite3
 Libs.private: -ldl -lpthread 
 Cflags: -I${includedir}
 Libs: -L${libdir} -lsqlite3
 Libs.private: -ldl -lpthread 
 Cflags: -I${includedir}

diff --git a/l4/pkg/uclibc/lib/libpthread/src/internals.h b/l4/pkg/uclibc/lib/libpthread/src/internals.h
index 92b8b937d2a2a95fba848967e3ff76485203a540..95e2a17150f504c45f9fdd30abba57e74ae905ad 100644 (file)
--- a/l4/pkg/uclibc/lib/libpthread/src/internals.h
+++ b/l4/pkg/uclibc/lib/libpthread/src/internals.h
@@ -156,9 +156,10 @@ inline static void __pthread_send_manager_rq(struct pthread_request *r, int bloc
   if (l4_is_invalid_cap(__pthread_manager_request))
     return;
   __builtin_memcpy(l4_utcb_mr()->mr, r, sizeof(struct pthread_request));
   if (l4_is_invalid_cap(__pthread_manager_request))
     return;
   __builtin_memcpy(l4_utcb_mr()->mr, r, sizeof(struct pthread_request));

-  l4_msgtag_t tag = l4_msgtag(0, 
-      (sizeof(struct pthread_request) + sizeof(l4_umword_t) - 1) / sizeof(l4_umword_t),
-      0, 0);
+  l4_msgtag_t tag
+    = l4_msgtag(0,
+                (sizeof(struct pthread_request) + sizeof(l4_umword_t) - 1) / sizeof(l4_umword_t),
+                0, L4_MSGTAG_SCHEDULE);

   if (block)
     l4_ipc_call(__pthread_manager_request, l4_utcb(), tag, L4_IPC_NEVER);
   else
   if (block)
     l4_ipc_call(__pthread_manager_request, l4_utcb(), tag, L4_IPC_NEVER);
   else

diff --git a/l4/pkg/uclibc/lib/libpthread/src/manager.cc b/l4/pkg/uclibc/lib/libpthread/src/manager.cc
index 58bc6867d678e6326cb5010abbe5e87d42d14386..7931f146ff7f19758d67dd08340d6037b30b269d 100644 (file)
--- a/l4/pkg/uclibc/lib/libpthread/src/manager.cc
+++ b/l4/pkg/uclibc/lib/libpthread/src/manager.cc
@@ -123,10 +123,10 @@ __pthread_manager(void *arg)
   __pthread_manager_adjust_prio(__pthread_main_thread->p_priority);
 
   l4_umword_t src;
   __pthread_manager_adjust_prio(__pthread_main_thread->p_priority);
 
   l4_umword_t src;

-  l4_msgtag_t tag = l4_msgtag(0,0,0,0);
+  l4_msgtag_t tag = l4_msgtag(0, 0, 0, L4_MSGTAG_SCHEDULE);

   int do_reply = 0;
   /* Enter server loop */
   int do_reply = 0;
   /* Enter server loop */

-  while(1)
+  while (1)

     {
       if (do_reply)
        tag = l4_ipc_reply_and_wait(l4_utcb(), tag, &src, L4_IPC_NEVER);
     {
       if (do_reply)
        tag = l4_ipc_reply_and_wait(l4_utcb(), tag, &src, L4_IPC_NEVER);


@@ -199,7 +199,7 @@ __pthread_manager(void *arg)
          do_reply = 1;
          break;
        }
          do_reply = 1;
          break;
        }

-      tag = l4_msgtag(0,0,0,0);
+      tag = l4_msgtag(0, 0, 0, L4_MSGTAG_SCHEDULE);

     }
 }
 
     }
 }
 

diff --git a/l4/pkg/valgrind/doc/scripts/VG.lua b/l4/pkg/valgrind/doc/scripts/VG.lua
index dbc7826843c121fe3fb463b68a2d1dc94fc65b74..ccdebff22c434b3963cb626534b93d8966fcaa1f 100644 (file)
--- a/l4/pkg/valgrind/doc/scripts/VG.lua
+++ b/l4/pkg/valgrind/doc/scripts/VG.lua
@@ -72,8 +72,8 @@ end
 
 function debug_memcheck(cmdline, ...)
        args = {}
 
 function debug_memcheck(cmdline, ...)
        args = {}

-       args.debuglevel = 3;
-       args.verbosity  = 3;
+       args.debuglevel = 4;
+       args.verbosity  = 4;

        args.cmdline    = { "--leak-check=yes", "--show-reachable=yes", cmdline, ... };
        args.tool = "memcheck";
        valgrind(args);
        args.cmdline    = { "--leak-check=yes", "--show-reachable=yes", cmdline, ... };
        args.tool = "memcheck";
        valgrind(args);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.all.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.all.am
index a46ac1acdf642fb81ff1a3e0e5abec8c5d6b0605..9c6a261862d0ac88b1d6f653d389c32fd79ecde7 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.all.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.all.am
@@ -96,7 +96,8 @@ AM_CFLAGS_BASE = \
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 if VGCONF_OS_IS_DARWIN
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 if VGCONF_OS_IS_DARWIN

-AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+               -mno-dynamic-no-pic -fpic -fPIC

 else
 AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing
 endif
 else
 AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing
 endif


@@ -165,7 +166,7 @@ AM_CCASFLAGS_PPC64_LINUX  = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 
 AM_FLAG_M3264_ARM_LINUX   = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX       = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 
 AM_FLAG_M3264_ARM_LINUX   = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX       = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 AM_CCASFLAGS_ARM_LINUX    = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 
 AM_FLAG_M3264_PPC32_AIX5  = @FLAG_MAIX32@
 AM_CCASFLAGS_ARM_LINUX    = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 
 AM_FLAG_M3264_PPC32_AIX5  = @FLAG_MAIX32@


@@ -180,8 +181,9 @@ AM_CCASFLAGS_PPC64_AIX5   = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN     = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN     = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC
+

 AM_CCASFLAGS_X86_DARWIN  = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 AM_CCASFLAGS_X86_DARWIN  = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.am
index 99023d04a8d3fc5360b5a70ea316940bffa3611c..ff9e1b524a8a62dcb3c7d44218d03589d368fc46 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.am
@@ -63,7 +63,8 @@ SUPP_FILES = \
        glibc-2.2-LinuxThreads-helgrind.supp \
        glibc-2.X-drd.supp \
        exp-ptrcheck.supp \
        glibc-2.2-LinuxThreads-helgrind.supp \
        glibc-2.X-drd.supp \
        exp-ptrcheck.supp \

-       darwin9.supp darwin9-drd.supp
+       darwin9.supp darwin9-drd.supp \
+       darwin10.supp darwin10-drd.supp

 
 DEFAULT_SUPP_FILES = @DEFAULT_SUPP@
 GENERATED_SUPP_FILES = @GENERATED_SUPP@
 
 DEFAULT_SUPP_FILES = @DEFAULT_SUPP@
 GENERATED_SUPP_FILES = @GENERATED_SUPP@

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.in
index 24bb4d0530e7342500bcab74ffa6244baad93b66..a07bb24f2f0325ffcf32c04b24ed7d93dd7a4a5e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.in
@@ -176,6 +176,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -210,14 +211,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -301,7 +306,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -360,7 +367,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -375,8 +382,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -472,7 +479,8 @@ SUPP_FILES = \
        glibc-2.2-LinuxThreads-helgrind.supp \
        glibc-2.X-drd.supp \
        exp-ptrcheck.supp \
        glibc-2.2-LinuxThreads-helgrind.supp \
        glibc-2.X-drd.supp \
        exp-ptrcheck.supp \

-       darwin9.supp darwin9-drd.supp
+       darwin9.supp darwin9-drd.supp \
+       darwin10.supp darwin10-drd.supp

 
 DEFAULT_SUPP_FILES = @DEFAULT_SUPP@
 GENERATED_SUPP_FILES = @GENERATED_SUPP@
 
 DEFAULT_SUPP_FILES = @DEFAULT_SUPP@
 GENERATED_SUPP_FILES = @GENERATED_SUPP@

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.tool.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.tool.am
index 786abbe49419455790a26f747adfcde2d5428610..df5f6b7ddebc628fd35f571e0236e49e8d18e6ee 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.tool.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.tool.am
@@ -26,35 +26,33 @@ TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 endif
 
 
 endif
 
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start
-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -63,124 +61,27 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE =  \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE =  \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64

 
 
 
 

-BUILT_SOURCES =
-CLEANFILES =
-if VGCONF_PLATFORMS_INCLUDE_X86_LINUX
-BUILT_SOURCES += $(top_builddir)/valt_load_address_x86_linux.lds
-CLEANFILES    += $(top_builddir)/valt_load_address_x86_linux.lds
-endif
-if VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX
-BUILT_SOURCES += $(top_builddir)/valt_load_address_amd64_linux.lds
-CLEANFILES    += $(top_builddir)/valt_load_address_amd64_linux.lds
-endif
-if VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX
-BUILT_SOURCES += $(top_builddir)/valt_load_address_ppc32_linux.lds
-CLEANFILES    += $(top_builddir)/valt_load_address_ppc32_linux.lds
-endif
-if VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX
-BUILT_SOURCES += $(top_builddir)/valt_load_address_ppc64_linux.lds
-CLEANFILES    += $(top_builddir)/valt_load_address_ppc64_linux.lds
-endif
-if VGCONF_PLATFORMS_INCLUDE_ARM_LINUX
-BUILT_SOURCES += $(top_builddir)/valt_load_address_arm_linux.lds
-CLEANFILES    += $(top_builddir)/valt_load_address_arm_linux.lds
-endif
-if VGCONF_PLATFORMS_INCLUDE_PPC32_AIX5
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-endif
-if VGCONF_PLATFORMS_INCLUDE_PPC64_AIX5
-# Ditto
-endif
-if VGCONF_PLATFORMS_INCLUDE_X86_L4RE
-BUILT_SOURCES += $(top_builddir)/valt_load_address_x86_l4re.lds
-CLEANFILES    += $(top_builddir)/valt_load_address_x86_l4re.lds
-endif
-if VGCONF_OS_IS_DARWIN
-# GrP untested, possibly hopeless
-endif
-
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.vex.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.vex.am
index e7f2c6d76855995c972cd689bf5bce219a8b25bd..1bfb1a9bfc77c960484def2980f3d93e43e083a4 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.vex.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.vex.am
@@ -40,6 +40,7 @@ noinst_HEADERS = \
        priv/guest_arm_defs.h \
        priv/host_generic_regs.h \
        priv/host_generic_simd64.h \
        priv/guest_arm_defs.h \
        priv/host_generic_regs.h \
        priv/host_generic_simd64.h \

+       priv/host_generic_simd128.h \

        priv/host_x86_defs.h \
        priv/host_amd64_defs.h \
        priv/host_ppc_defs.h \
        priv/host_x86_defs.h \
        priv/host_amd64_defs.h \
        priv/host_ppc_defs.h \


@@ -57,8 +58,10 @@ pub/libvex_guest_offsets.h:
        mkdir -p pub
        mkdir -p priv
        rm -f auxprogs/genoffsets.s
        mkdir -p pub
        mkdir -p priv
        rm -f auxprogs/genoffsets.s

-       $(CC) $(LIBVEX_CFLAGS) -O -S -o auxprogs/genoffsets.s \
-                                       $(VEX_SRC)/auxprogs/genoffsets.c
+       $(CC) $(LIBVEX_CFLAGS) \
+             $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
+                               -O -S -o auxprogs/genoffsets.s \
+                                        $(VEX_SRC)/auxprogs/genoffsets.c

        grep xyzzy auxprogs/genoffsets.s | grep define \
           | sed "s/xyzzy\\$$//g" \
           | sed "s/xyzzy#//g" \
        grep xyzzy auxprogs/genoffsets.s | grep define \
           | sed "s/xyzzy\\$$//g" \
           | sed "s/xyzzy#//g" \


@@ -94,6 +97,7 @@ LIBVEX_SOURCES_COMMON = \
        priv/guest_arm_toIR.c \
        priv/host_generic_regs.c \
        priv/host_generic_simd64.c \
        priv/guest_arm_toIR.c \
        priv/host_generic_regs.c \
        priv/host_generic_simd64.c \

+       priv/host_generic_simd128.c \

        priv/host_generic_reg_alloc2.c \
        priv/host_x86_defs.c \
        priv/host_x86_isel.c \
        priv/host_generic_reg_alloc2.c \
        priv/host_x86_defs.c \
        priv/host_x86_isel.c \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.vex.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.vex.in
index a487cb9e3ced921c8e58dab27a3c902399645b8e..22fd0d3b9686debc355913cf3f8e310dd4b8e484 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.vex.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/Makefile.vex.in
@@ -103,6 +103,7 @@ am__objects_1 =  \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_arm_toIR.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-guest_arm_toIR.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \

+       libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.$(OBJEXT) \

        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_x86_defs.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_x86_isel.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_x86_defs.$(OBJEXT) \
        libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_x86_isel.$(OBJEXT) \


@@ -126,10 +127,11 @@ am__libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST =  \
        priv/guest_ppc_helpers.c priv/guest_ppc_toIR.c \
        priv/guest_arm_helpers.c priv/guest_arm_toIR.c \
        priv/host_generic_regs.c priv/host_generic_simd64.c \
        priv/guest_ppc_helpers.c priv/guest_ppc_toIR.c \
        priv/guest_arm_helpers.c priv/guest_arm_toIR.c \
        priv/host_generic_regs.c priv/host_generic_simd64.c \

-       priv/host_generic_reg_alloc2.c priv/host_x86_defs.c \
-       priv/host_x86_isel.c priv/host_amd64_defs.c \
-       priv/host_amd64_isel.c priv/host_ppc_defs.c \
-       priv/host_ppc_isel.c priv/host_arm_defs.c priv/host_arm_isel.c
+       priv/host_generic_simd128.c priv/host_generic_reg_alloc2.c \
+       priv/host_x86_defs.c priv/host_x86_isel.c \
+       priv/host_amd64_defs.c priv/host_amd64_isel.c \
+       priv/host_ppc_defs.c priv/host_ppc_isel.c priv/host_arm_defs.c \
+       priv/host_arm_isel.c

 am__objects_2 =  \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_globals.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_main.$(OBJEXT) \
 am__objects_2 =  \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_globals.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-main_main.$(OBJEXT) \


@@ -149,6 +151,7 @@ am__objects_2 =  \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_arm_toIR.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-guest_arm_toIR.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.$(OBJEXT) \

+       libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.$(OBJEXT) \

        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_x86_defs.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_x86_isel.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_x86_defs.$(OBJEXT) \
        libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_x86_isel.$(OBJEXT) \


@@ -215,6 +218,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -249,14 +253,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -339,7 +347,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -398,7 +408,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -413,8 +423,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -496,6 +506,7 @@ noinst_HEADERS = \
        priv/guest_arm_defs.h \
        priv/host_generic_regs.h \
        priv/host_generic_simd64.h \
        priv/guest_arm_defs.h \
        priv/host_generic_regs.h \
        priv/host_generic_simd64.h \

+       priv/host_generic_simd128.h \

        priv/host_x86_defs.h \
        priv/host_amd64_defs.h \
        priv/host_ppc_defs.h \
        priv/host_x86_defs.h \
        priv/host_amd64_defs.h \
        priv/host_ppc_defs.h \


@@ -529,6 +540,7 @@ LIBVEX_SOURCES_COMMON = \
        priv/guest_arm_toIR.c \
        priv/host_generic_regs.c \
        priv/host_generic_simd64.c \
        priv/guest_arm_toIR.c \
        priv/host_generic_regs.c \
        priv/host_generic_simd64.c \

+       priv/host_generic_simd128.c \

        priv/host_generic_reg_alloc2.c \
        priv/host_x86_defs.c \
        priv/host_x86_isel.c \
        priv/host_generic_reg_alloc2.c \
        priv/host_x86_defs.c \
        priv/host_x86_isel.c \


@@ -657,6 +669,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_arm_isel.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_arm_isel.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_regs.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_ppc_defs.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_ppc_isel.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_ppc_defs.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_ppc_isel.Po@am__quote@


@@ -684,6 +697,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_arm_isel.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_arm_isel.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_regs.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_ppc_defs.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_ppc_isel.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_ppc_defs.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_ppc_isel.Po@am__quote@


@@ -962,6 +976,20 @@ libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.obj: priv/host_generi
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.obj `if test -f 'priv/host_generic_simd64.c'; then $(CYGPATH_W) 'priv/host_generic_simd64.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd64.c'; fi`
 
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd64.obj `if test -f 'priv/host_generic_simd64.c'; then $(CYGPATH_W) 'priv/host_generic_simd64.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd64.c'; fi`
 

+libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.o: priv/host_generic_simd128.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.o `test -f 'priv/host_generic_simd128.c' || echo '$(srcdir)/'`priv/host_generic_simd128.c
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='priv/host_generic_simd128.c' object='libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.o `test -f 'priv/host_generic_simd128.c' || echo '$(srcdir)/'`priv/host_generic_simd128.c
+
+libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.obj: priv/host_generic_simd128.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.obj -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.obj `if test -f 'priv/host_generic_simd128.c'; then $(CYGPATH_W) 'priv/host_generic_simd128.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd128.c'; fi`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='priv/host_generic_simd128.c' object='libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_simd128.obj `if test -f 'priv/host_generic_simd128.c'; then $(CYGPATH_W) 'priv/host_generic_simd128.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd128.c'; fi`
+

 libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o: priv/host_generic_reg_alloc2.c
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o `test -f 'priv/host_generic_reg_alloc2.c' || echo '$(srcdir)/'`priv/host_generic_reg_alloc2.c
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po
 libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o: priv/host_generic_reg_alloc2.c
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo -c -o libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.o `test -f 'priv/host_generic_reg_alloc2.c' || echo '$(srcdir)/'`priv/host_generic_reg_alloc2.c
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po


@@ -1340,6 +1368,20 @@ libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.obj: priv/host_generi
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.obj `if test -f 'priv/host_generic_simd64.c'; then $(CYGPATH_W) 'priv/host_generic_simd64.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd64.c'; fi`
 
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd64.obj `if test -f 'priv/host_generic_simd64.c'; then $(CYGPATH_W) 'priv/host_generic_simd64.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd64.c'; fi`
 

+libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.o: priv/host_generic_simd128.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.o `test -f 'priv/host_generic_simd128.c' || echo '$(srcdir)/'`priv/host_generic_simd128.c
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='priv/host_generic_simd128.c' object='libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.o `test -f 'priv/host_generic_simd128.c' || echo '$(srcdir)/'`priv/host_generic_simd128.c
+
+libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.obj: priv/host_generic_simd128.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.obj -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.obj `if test -f 'priv/host_generic_simd128.c'; then $(CYGPATH_W) 'priv/host_generic_simd128.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd128.c'; fi`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='priv/host_generic_simd128.c' object='libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_simd128.obj `if test -f 'priv/host_generic_simd128.c'; then $(CYGPATH_W) 'priv/host_generic_simd128.c'; else $(CYGPATH_W) '$(srcdir)/priv/host_generic_simd128.c'; fi`
+

 libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o: priv/host_generic_reg_alloc2.c
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o `test -f 'priv/host_generic_reg_alloc2.c' || echo '$(srcdir)/'`priv/host_generic_reg_alloc2.c
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po
 libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o: priv/host_generic_reg_alloc2.c
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CFLAGS) $(CFLAGS) -MT libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o -MD -MP -MF $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo -c -o libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.o `test -f 'priv/host_generic_reg_alloc2.c' || echo '$(srcdir)/'`priv/host_generic_reg_alloc2.c
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Tpo $(DEPDIR)/libvex_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-host_generic_reg_alloc2.Po


@@ -1763,8 +1805,10 @@ pub/libvex_guest_offsets.h:
        mkdir -p pub
        mkdir -p priv
        rm -f auxprogs/genoffsets.s
        mkdir -p pub
        mkdir -p priv
        rm -f auxprogs/genoffsets.s

-       $(CC) $(LIBVEX_CFLAGS) -O -S -o auxprogs/genoffsets.s \
-                                       $(VEX_SRC)/auxprogs/genoffsets.c
+       $(CC) $(LIBVEX_CFLAGS) \
+             $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
+                               -O -S -o auxprogs/genoffsets.s \
+                                        $(VEX_SRC)/auxprogs/genoffsets.c

        grep xyzzy auxprogs/genoffsets.s | grep define \
           | sed "s/xyzzy\\$$//g" \
           | sed "s/xyzzy#//g" \
        grep xyzzy auxprogs/genoffsets.s | grep define \
           | sed "s/xyzzy\\$$//g" \
           | sed "s/xyzzy#//g" \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/NEWS b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/NEWS
index 8726e21f4ee7b50575fc10ce9c11303106a257a9..ead2949dd1be88482e85f966940ffcb5534ea581 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/NEWS
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/NEWS
@@ -3,9 +3,33 @@ Release 3.6.0 (???)
 ~~~~~~~~~~~~~~~~~~~
 Improvements:
 - XXX: ARM support
 ~~~~~~~~~~~~~~~~~~~
 Improvements:
 - XXX: ARM support

+- XXX: Mac OS 10.6 support (32 and 64 bit)
+- XXX: Much faster startup on Mac OS 10.5 for 64-bit programs.

 
 

-- --smc-check=all is much faster
+- Valgrind runs much faster when the --smc-check=all option is given.

 
 

+- Cachegrind has a new processing script, cg_diff, which finds the
+  difference between two profiles.  It's very useful for evaluating the
+  performance effects of a change in a program.
+  
+  Related to this change, the meaning of cg_annotate's (rarely-used)
+  --threshold option has changed; this is unlikely to affect many people, if
+  you do use it please see the user manual for details.
+
+- Massif has a new option, --pages-as-heap, which is disabled by default.
+  When enabled, instead of tracking allocations at the level of heap blocks
+  (as allocated with malloc/new/new[]), it instead tracks memory allocations
+  at the level of memory pages (as mapped by mmap, brk, etc).  Each mapped
+  page is treated as its own block.  Interpreting the page-level output is
+  harder than the heap-level output, but this option is useful if you want
+  to account for every byte of memory used by a program.
+
+- Callgrind now can do branch prediction simulation, similar to Cachegrind.
+  In addition, it optionally can count the number of executed global bus events.
+  Both can be used for a better approximation of a "Cycle Estimation" as
+  derived event (you need to update the event formula in KCachegrind yourself).
+
+- Added new memcheck command-line option --show-possibly-lost.

 
 
 Release 3.5.0 (19 August 2009)
 
 
 Release 3.5.0 (19 August 2009)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/Makefile-gcc b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/Makefile-gcc
index 8b3724085797a937e999268a493aa43511da4893..d12516219bc8e2cc4f1e4037014adc7bfc0fa813 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/Makefile-gcc
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/Makefile-gcc
@@ -17,6 +17,7 @@ PRIV_HEADERS =        priv/host_x86_defs.h                    \
                priv/host_ppc_defs.h                    \
                priv/host_generic_regs.h                \
                priv/host_generic_simd64.h              \
                priv/host_ppc_defs.h                    \
                priv/host_generic_regs.h                \
                priv/host_generic_simd64.h              \

+               priv/host_generic_simd128.h             \

                priv/main_globals.h                     \
                priv/main_util.h                        \
                priv/guest_generic_x87.h                \
                priv/main_globals.h                     \
                priv/main_util.h                        \
                priv/guest_generic_x87.h                \


@@ -44,6 +45,7 @@ LIB_OBJS =    priv/ir_defs.o                          \
                priv/host_ppc_isel.o                    \
                priv/host_generic_regs.o                \
                priv/host_generic_simd64.o              \
                priv/host_ppc_isel.o                    \
                priv/host_generic_regs.o                \
                priv/host_generic_simd64.o              \

+               priv/host_generic_simd128.o             \

                priv/host_generic_reg_alloc2.o          \
                priv/guest_generic_x87.o                \
                priv/guest_generic_bb_to_IR.o           \
                priv/host_generic_reg_alloc2.o          \
                priv/guest_generic_x87.o                \
                priv/guest_generic_bb_to_IR.o           \


@@ -268,6 +270,10 @@ priv/host_generic_simd64.o: $(ALL_HEADERS) priv/host_generic_simd64.c
        $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_simd64.o \
                                         -c priv/host_generic_simd64.c
 
        $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_simd64.o \
                                         -c priv/host_generic_simd64.c
 

+priv/host_generic_simd128.o: $(ALL_HEADERS) priv/host_generic_simd128.c
+       $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_simd128.o \
+                                        -c priv/host_generic_simd128.c
+

 priv/host_generic_reg_alloc2.o: $(ALL_HEADERS) priv/host_generic_reg_alloc2.c
        $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_reg_alloc2.o \
                                         -c priv/host_generic_reg_alloc2.c
 priv/host_generic_reg_alloc2.o: $(ALL_HEADERS) priv/host_generic_reg_alloc2.c
        $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_reg_alloc2.o \
                                         -c priv/host_generic_reg_alloc2.c

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/auxprogs/genoffsets.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/auxprogs/genoffsets.c
index 512b430fe70b67927134d338a5d2a78cf0091ac3..b379691835827f66df067719a8faf9d002fb94da 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/auxprogs/genoffsets.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/auxprogs/genoffsets.c
@@ -154,7 +154,7 @@ void foo ( void )
    GENOFFSET(ARM,arm,R7);
    GENOFFSET(ARM,arm,R13);
    GENOFFSET(ARM,arm,R14);
    GENOFFSET(ARM,arm,R7);
    GENOFFSET(ARM,arm,R13);
    GENOFFSET(ARM,arm,R14);

-   GENOFFSET(ARM,arm,R15);
+   GENOFFSET(ARM,arm,R15T);

 }
 
 /*--------------------------------------------------------------------*/
 }
 
 /*--------------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_defs.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_defs.h
index 40ed37f1434cd679a8ae9fe0c8ad84012aa025ec..6525076f1e3b65815a3f48e9691a02fcab7f0f7c 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_defs.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_defs.h
@@ -61,8 +61,10 @@ DisResult disInstr_AMD64 ( IRSB*        irbb,
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern

-IRExpr* guest_amd64_spechelper ( HChar* function_name,
-                                 IRExpr** args );
+IRExpr* guest_amd64_spechelper ( HChar*   function_name,
+                                 IRExpr** args,
+                                 IRStmt** precedingStmts,
+                                 Int      n_precedingStmts );

 
 /* Describes to the optimiser which part of the guest state require
    precise memory exceptions.  This is logically part of the guest
 
 /* Describes to the optimiser which part of the guest state require
    precise memory exceptions.  This is logically part of the guest


@@ -142,6 +144,7 @@ extern void  amd64g_dirtyhelper_storeF80le ( ULong/*addr*/, ULong/*data*/ );
 
 extern void  amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st );
 extern void  amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st );
 
 extern void  amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st );
 extern void  amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st );

+extern void  amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st );

 
 extern void  amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* );
 
 
 extern void  amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* );
 


@@ -153,6 +156,55 @@ extern ULong amd64g_dirtyhelper_IN  ( ULong portno, ULong sz/*1,2 or 4*/ );
 extern void  amd64g_dirtyhelper_OUT ( ULong portno, ULong data, 
                                       ULong sz/*1,2 or 4*/ );
 
 extern void  amd64g_dirtyhelper_OUT ( ULong portno, ULong data, 
                                       ULong sz/*1,2 or 4*/ );
 

+extern void amd64g_dirtyhelper_SxDT ( void* address,
+                                      ULong op /* 0 or 1 */ );
+
+/* Helps with PCMP{I,E}STR{I,M}.
+
+   CALLED FROM GENERATED CODE: DIRTY HELPER(s).  (But not really,
+   actually it could be a clean helper, but for the fact that we can't
+   pass by value 2 x V128 to a clean helper, nor have one returned.)
+   Reads guest state, writes to guest state for the xSTRM cases, no
+   accesses of memory, is a pure function.
+
+   opc_and_imm contains (4th byte of opcode << 8) | the-imm8-byte so
+   the callee knows which I/E and I/M variant it is dealing with and
+   what the specific operation is.  4th byte of opcode is in the range
+   0x60 to 0x63:
+       istri  66 0F 3A 63
+       istrm  66 0F 3A 62
+       estri  66 0F 3A 61
+       estrm  66 0F 3A 60
+
+   gstOffL and gstOffR are the guest state offsets for the two XMM
+   register inputs.  We never have to deal with the memory case since
+   that is handled by pre-loading the relevant value into the fake
+   XMM16 register.
+
+   For ESTRx variants, edxIN and eaxIN hold the values of those two
+   registers.
+
+   In all cases, the bottom 16 bits of the result contain the new
+   OSZACP %rflags values.  For xSTRI variants, bits[31:16] of the
+   result hold the new %ecx value.  For xSTRM variants, the helper
+   writes the result directly to the guest XMM0.
+
+   Declarable side effects: in all cases, reads guest state at
+   [gstOffL, +16) and [gstOffR, +16).  For xSTRM variants, also writes
+   guest_XMM0.
+
+   Is expected to be called with opc_and_imm combinations which have
+   actually been validated, and will assert if otherwise.  The front
+   end should ensure we're only called with verified values.
+*/
+extern ULong amd64g_dirtyhelper_PCMPxSTRx ( 
+          VexGuestAMD64State*,
+          HWord opc4_and_imm,
+          HWord gstOffL, HWord gstOffR,
+          HWord edxIN, HWord eaxIN
+       );
+
+

 //extern void  amd64g_dirtyhelper_CPUID_sse0 ( VexGuestAMD64State* );
 //extern void  amd64g_dirtyhelper_CPUID_sse1 ( VexGuestAMD64State* );
 //extern void  amd64g_dirtyhelper_CPUID_sse2 ( VexGuestAMD64State* );
 //extern void  amd64g_dirtyhelper_CPUID_sse0 ( VexGuestAMD64State* );
 //extern void  amd64g_dirtyhelper_CPUID_sse1 ( VexGuestAMD64State* );
 //extern void  amd64g_dirtyhelper_CPUID_sse2 ( VexGuestAMD64State* );

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_helpers.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_helpers.c
index 74e1b5ea5eef1d6dcde18bba9bbc4b4ca5d7b435..c24cba37b91f18d4b2a910a238e517b81517566d 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_helpers.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_helpers.c
@@ -867,7 +867,9 @@ static Bool isU64 ( IRExpr* e, ULong n )
 }
 
 IRExpr* guest_amd64_spechelper ( HChar* function_name,
 }
 
 IRExpr* guest_amd64_spechelper ( HChar* function_name,

-                                 IRExpr** args )
+                                 IRExpr** args,
+                                 IRStmt** precedingStmts,
+                                 Int      n_precedingStmts )

 {
 #  define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
 #  define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))
 {
 #  define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
 #  define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))


@@ -2009,6 +2011,158 @@ void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st )
 }
 
 
 }
 
 

+/* Claim to be the following CPU (4 x ...), which is sse4.2 and cx16
+   capable.
+
+   vendor_id       : GenuineIntel
+   cpu family      : 6
+   model           : 37
+   model name      : Intel(R) Core(TM) i5 CPU         670  @ 3.47GHz
+   stepping        : 2
+   cpu MHz         : 3334.000
+   cache size      : 4096 KB
+   physical id     : 0
+   siblings        : 4
+   core id         : 0
+   cpu cores       : 2
+   apicid          : 0
+   initial apicid  : 0
+   fpu             : yes
+   fpu_exception   : yes
+   cpuid level     : 11
+   wp              : yes
+   flags           : fpu vme de pse tsc msr pae mce cx8 apic sep
+                     mtrr pge mca cmov pat pse36 clflush dts acpi
+                     mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp
+                     lm constant_tsc arch_perfmon pebs bts rep_good
+                     xtopology nonstop_tsc aperfmperf pni pclmulqdq
+                     dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16
+                     xtpr pdcm sse4_1 sse4_2 popcnt aes lahf_lm ida
+                     arat tpr_shadow vnmi flexpriority ept vpid
+   bogomips        : 6957.57
+   clflush size    : 64
+   cache_alignment : 64
+   address sizes   : 36 bits physical, 48 bits virtual
+   power management:
+*/
+void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st )
+{
+#  define SET_ABCD(_a,_b,_c,_d)                \
+      do { st->guest_RAX = (ULong)(_a);        \
+           st->guest_RBX = (ULong)(_b);        \
+           st->guest_RCX = (ULong)(_c);        \
+           st->guest_RDX = (ULong)(_d);        \
+      } while (0)
+
+   UInt old_eax = (UInt)st->guest_RAX;
+   UInt old_ecx = (UInt)st->guest_RCX;
+
+   switch (old_eax) {
+      case 0x00000000:
+         SET_ABCD(0x0000000b, 0x756e6547, 0x6c65746e, 0x49656e69);
+         break;
+      case 0x00000001:
+         SET_ABCD(0x00020652, 0x00100800, 0x0298e3ff, 0xbfebfbff);
+         break;
+      case 0x00000002:
+         SET_ABCD(0x55035a01, 0x00f0b2e3, 0x00000000, 0x09ca212c);
+         break;
+      case 0x00000003:
+         SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+         break;
+      case 0x00000004:
+         switch (old_ecx) {
+            case 0x00000000: SET_ABCD(0x1c004121, 0x01c0003f,
+                                      0x0000003f, 0x00000000); break;
+            case 0x00000001: SET_ABCD(0x1c004122, 0x00c0003f,
+                                      0x0000007f, 0x00000000); break;
+            case 0x00000002: SET_ABCD(0x1c004143, 0x01c0003f,
+                                      0x000001ff, 0x00000000); break;
+            case 0x00000003: SET_ABCD(0x1c03c163, 0x03c0003f,
+                                      0x00000fff, 0x00000002); break;
+            default:         SET_ABCD(0x00000000, 0x00000000,
+                                      0x00000000, 0x00000000); break;
+         }
+         break;
+      case 0x00000005:
+         SET_ABCD(0x00000040, 0x00000040, 0x00000003, 0x00001120);
+         break;
+      case 0x00000006:
+         SET_ABCD(0x00000007, 0x00000002, 0x00000001, 0x00000000);
+         break;
+      case 0x00000007:
+         SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+         break;
+      case 0x00000008:
+         SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+         break;
+      case 0x00000009:
+         SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+         break;
+      case 0x0000000a:
+         SET_ABCD(0x07300403, 0x00000004, 0x00000000, 0x00000603);
+         break;
+      case 0x0000000b:
+         switch (old_ecx) {
+            case 0x00000000:
+               SET_ABCD(0x00000001, 0x00000002,
+                        0x00000100, 0x00000000); break;
+            case 0x00000001:
+               SET_ABCD(0x00000004, 0x00000004,
+                        0x00000201, 0x00000000); break;
+            default:
+               SET_ABCD(0x00000000, 0x00000000,
+                        old_ecx,    0x00000000); break;
+         }
+         break;
+      case 0x0000000c:
+         SET_ABCD(0x00000001, 0x00000002, 0x00000100, 0x00000000);
+         break;
+      case 0x0000000d:
+         switch (old_ecx) {
+            case 0x00000000: SET_ABCD(0x00000001, 0x00000002,
+                                      0x00000100, 0x00000000); break;
+            case 0x00000001: SET_ABCD(0x00000004, 0x00000004,
+                                      0x00000201, 0x00000000); break;
+            default:         SET_ABCD(0x00000000, 0x00000000,
+                                      old_ecx,    0x00000000); break;
+         }
+         break;
+      case 0x80000000:
+         SET_ABCD(0x80000008, 0x00000000, 0x00000000, 0x00000000);
+         break;
+      case 0x80000001:
+         SET_ABCD(0x00000000, 0x00000000, 0x00000001, 0x28100800);
+         break;
+      case 0x80000002:
+         SET_ABCD(0x65746e49, 0x2952286c, 0x726f4320, 0x4d542865);
+         break;
+      case 0x80000003:
+         SET_ABCD(0x35692029, 0x55504320, 0x20202020, 0x20202020);
+         break;
+      case 0x80000004:
+         SET_ABCD(0x30373620, 0x20402020, 0x37342e33, 0x007a4847);
+         break;
+      case 0x80000005:
+         SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000000);
+         break;
+      case 0x80000006:
+         SET_ABCD(0x00000000, 0x00000000, 0x01006040, 0x00000000);
+         break;
+      case 0x80000007:
+         SET_ABCD(0x00000000, 0x00000000, 0x00000000, 0x00000100);
+         break;
+      case 0x80000008:
+         SET_ABCD(0x00003024, 0x00000000, 0x00000000, 0x00000000);
+         break;
+      default:
+         SET_ABCD(0x00000001, 0x00000002, 0x00000100, 0x00000000);
+         break;
+   }
+#  undef SET_ABCD
+}
+
+

 ULong amd64g_calculate_RCR ( ULong arg, 
                              ULong rot_amt, 
                              ULong rflags_in, 
 ULong amd64g_calculate_RCR ( ULong arg, 
                              ULong rot_amt, 
                              ULong rflags_in, 


@@ -2218,6 +2372,31 @@ void amd64g_dirtyhelper_OUT ( ULong portno, ULong data, ULong sz/*1,2 or 4*/ )
 #  endif
 }
 
 #  endif
 }
 

+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack.  On non-amd64 platforms, do nothing. */
+/* op = 0: call the native SGDT instruction.
+   op = 1: call the native SIDT instruction.
+*/
+void amd64g_dirtyhelper_SxDT ( void *address, ULong op ) {
+#  if defined(__x86_64__)
+   switch (op) {
+      case 0:
+         __asm__ __volatile__("sgdt (%0)" : : "r" (address) : "memory");
+         break;
+      case 1:
+         __asm__ __volatile__("sidt (%0)" : : "r" (address) : "memory");
+         break;
+      default:
+         vpanic("amd64g_dirtyhelper_SxDT");
+   }
+#  else
+   /* do nothing */
+   UChar* p = (UChar*)address;
+   p[0] = p[1] = p[2] = p[3] = p[4] = p[5] = 0;
+   p[6] = p[7] = p[8] = p[9] = 0;
+#  endif
+}

 
 /*---------------------------------------------------------------*/
 /*--- Helpers for MMX/SSE/SSE2.                               ---*/
 
 /*---------------------------------------------------------------*/
 /*--- Helpers for MMX/SSE/SSE2.                               ---*/


@@ -2333,6 +2512,130 @@ ULong amd64g_calculate_sse_pmovmskb ( ULong w64hi, ULong w64lo )
 }
 
 
 }
 
 

+/*---------------------------------------------------------------*/
+/*--- Helpers for SSE4.2 PCMP{E,I}STR{I,M}                    ---*/
+/*---------------------------------------------------------------*/
+
+static UInt zmask_from_V128 ( V128* arg )
+{
+   UInt i, res = 0;
+   for (i = 0; i < 16; i++) {
+      res |=  ((arg->w8[i] == 0) ? 1 : 0) << i;
+   }
+   return res;
+}
+
+/* Helps with PCMP{I,E}STR{I,M}.
+
+   CALLED FROM GENERATED CODE: DIRTY HELPER(s).  (But not really,
+   actually it could be a clean helper, but for the fact that we can't
+   pass by value 2 x V128 to a clean helper, nor have one returned.)
+   Reads guest state, writes to guest state for the xSTRM cases, no
+   accesses of memory, is a pure function.
+
+   opc_and_imm contains (4th byte of opcode << 8) | the-imm8-byte so
+   the callee knows which I/E and I/M variant it is dealing with and
+   what the specific operation is.  4th byte of opcode is in the range
+   0x60 to 0x63:
+       istri  66 0F 3A 63
+       istrm  66 0F 3A 62
+       estri  66 0F 3A 61
+       estrm  66 0F 3A 60
+
+   gstOffL and gstOffR are the guest state offsets for the two XMM
+   register inputs.  We never have to deal with the memory case since
+   that is handled by pre-loading the relevant value into the fake
+   XMM16 register.
+
+   For ESTRx variants, edxIN and eaxIN hold the values of those two
+   registers.
+
+   In all cases, the bottom 16 bits of the result contain the new
+   OSZACP %rflags values.  For xSTRI variants, bits[31:16] of the
+   result hold the new %ecx value.  For xSTRM variants, the helper
+   writes the result directly to the guest XMM0.
+
+   Declarable side effects: in all cases, reads guest state at
+   [gstOffL, +16) and [gstOffR, +16).  For xSTRM variants, also writes
+   guest_XMM0.
+
+   Is expected to be called with opc_and_imm combinations which have
+   actually been validated, and will assert if otherwise.  The front
+   end should ensure we're only called with verified values.
+*/
+ULong amd64g_dirtyhelper_PCMPxSTRx ( 
+          VexGuestAMD64State* gst,
+          HWord opc4_and_imm,
+          HWord gstOffL, HWord gstOffR,
+          HWord edxIN, HWord eaxIN
+       )
+{
+   HWord opc4 = (opc4_and_imm >> 8) & 0xFF;
+   HWord imm8 = opc4_and_imm & 0xFF;
+   HWord isISTRx = opc4 & 2;
+   HWord isxSTRM = (opc4 & 1) ^ 1;
+   vassert((opc4 & 0xFC) == 0x60); /* 0x60 .. 0x63 */
+   vassert((imm8 & 1) == 0); /* we support byte-size cases only */
+
+   // where the args are
+   V128* argL = (V128*)( ((UChar*)gst) + gstOffL );
+   V128* argR = (V128*)( ((UChar*)gst) + gstOffR );
+
+   /* Create the arg validity masks, either from the vectors
+      themselves or from the supplied edx/eax values. */
+   // FIXME: this is only right for the 8-bit data cases.
+   // At least that is asserted above.
+   UInt zmaskL, zmaskR;
+   if (isISTRx) {
+      zmaskL = zmask_from_V128(argL);
+      zmaskR = zmask_from_V128(argR);
+   } else {
+      Int tmp;
+      tmp = edxIN & 0xFFFFFFFF;
+      if (tmp < -16) tmp = -16;
+      if (tmp > 16)  tmp = 16;
+      if (tmp < 0)   tmp = -tmp;
+      vassert(tmp >= 0 && tmp <= 16);
+      zmaskL = (1 << tmp) & 0xFFFF;
+      tmp = eaxIN & 0xFFFFFFFF;
+      if (tmp < -16) tmp = -16;
+      if (tmp > 16)  tmp = 16;
+      if (tmp < 0)   tmp = -tmp;
+      vassert(tmp >= 0 && tmp <= 16);
+      zmaskR = (1 << tmp) & 0xFFFF;
+   }
+
+   // temp spot for the resulting flags and vector.
+   V128 resV;
+   UInt resOSZACP;
+
+   // do the meyaath
+   Bool ok = compute_PCMPxSTRx ( 
+                &resV, &resOSZACP, argL, argR, 
+                zmaskL, zmaskR, imm8, (Bool)isxSTRM
+             );
+
+   // front end shouldn't pass us any imm8 variants we can't
+   // handle.  Hence:
+   vassert(ok);
+
+   // So, finally we need to get the results back to the caller.
+   // In all cases, the new OSZACP value is the lowest 16 of
+   // the return value.
+   if (isxSTRM) {
+      /* gst->guest_XMM0 = resV; */ // gcc don't like that
+      gst->guest_XMM0[0] = resV.w32[0];
+      gst->guest_XMM0[1] = resV.w32[1];
+      gst->guest_XMM0[2] = resV.w32[2];
+      gst->guest_XMM0[3] = resV.w32[3];
+      return resOSZACP & 0x8D5;
+   } else {
+      UInt newECX = resV.w32[0] & 0xFFFF;
+      return (newECX << 16) | (resOSZACP & 0x8D5);
+   }
+}
+
+

 /*---------------------------------------------------------------*/
 /*--- Helpers for dealing with, and describing,               ---*/
 /*--- guest state as a whole.                                 ---*/
 /*---------------------------------------------------------------*/
 /*--- Helpers for dealing with, and describing,               ---*/
 /*--- guest state as a whole.                                 ---*/


@@ -2396,6 +2699,7 @@ void LibVEX_GuestAMD64_initialise ( /*OUT*/VexGuestAMD64State* vex_state )
    SSEZERO(vex_state->guest_XMM13);
    SSEZERO(vex_state->guest_XMM14);
    SSEZERO(vex_state->guest_XMM15);
    SSEZERO(vex_state->guest_XMM13);
    SSEZERO(vex_state->guest_XMM14);
    SSEZERO(vex_state->guest_XMM15);

+   SSEZERO(vex_state->guest_XMM16);

 
 #  undef SSEZERO
 
 
 #  undef SSEZERO
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_toIR.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_toIR.c
index 1fa1ed429b7390071f824381154173640e8c218f..f8a5da178cfba0f54a94e1ff42e28268bdce5d43 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_toIR.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_amd64_toIR.c
@@ -442,6 +442,7 @@ static void unimplemented ( HChar* str )
 #define OFFB_XMM13     offsetof(VexGuestAMD64State,guest_XMM13)
 #define OFFB_XMM14     offsetof(VexGuestAMD64State,guest_XMM14)
 #define OFFB_XMM15     offsetof(VexGuestAMD64State,guest_XMM15)
 #define OFFB_XMM13     offsetof(VexGuestAMD64State,guest_XMM13)
 #define OFFB_XMM14     offsetof(VexGuestAMD64State,guest_XMM14)
 #define OFFB_XMM15     offsetof(VexGuestAMD64State,guest_XMM15)

+#define OFFB_XMM16     offsetof(VexGuestAMD64State,guest_XMM16)

 
 #define OFFB_EMWARN    offsetof(VexGuestAMD64State,guest_EMWARN)
 #define OFFB_TISTART   offsetof(VexGuestAMD64State,guest_TISTART)
 
 #define OFFB_EMWARN    offsetof(VexGuestAMD64State,guest_EMWARN)
 #define OFFB_TISTART   offsetof(VexGuestAMD64State,guest_TISTART)


@@ -741,6 +742,13 @@ static Bool haveF3no66noF2 ( Prefix pfx )
      toBool((pfx & (PFX_66|PFX_F2|PFX_F3)) == PFX_F3);
 }
 
      toBool((pfx & (PFX_66|PFX_F2|PFX_F3)) == PFX_F3);
 }
 

+/* Return True iff pfx has F3 set and F2 clear */
+static Bool haveF3noF2 ( Prefix pfx )
+{
+  return 
+     toBool((pfx & (PFX_F2|PFX_F3)) == PFX_F3);
+}
+

 /* Return True iff pfx has 66, F2 and F3 clear */
 static Bool haveNo66noF2noF3 ( Prefix pfx )
 {
 /* Return True iff pfx has 66, F2 and F3 clear */
 static Bool haveNo66noF2noF3 ( Prefix pfx )
 {


@@ -4334,6 +4342,135 @@ ULong dis_imul_I_E_G ( VexAbiInfo* vbi,
 }
 
 
 }
 
 

+/* Generate an IR sequence to do a popcount operation on the supplied
+   IRTemp, and return a new IRTemp holding the result.  'ty' may be
+   Ity_I16, Ity_I32 or Ity_I64 only. */
+static IRTemp gen_POPCOUNT ( IRType ty, IRTemp src )
+{
+   Int i;
+   if (ty == Ity_I16) {
+      IRTemp old = IRTemp_INVALID;
+      IRTemp nyu = IRTemp_INVALID;
+      IRTemp mask[4], shift[4];
+      for (i = 0; i < 4; i++) {
+         mask[i]  = newTemp(ty);
+         shift[i] = 1 << i;
+      }
+      assign(mask[0], mkU16(0x5555));
+      assign(mask[1], mkU16(0x3333));
+      assign(mask[2], mkU16(0x0F0F));
+      assign(mask[3], mkU16(0x00FF));
+      old = src;
+      for (i = 0; i < 4; i++) {
+         nyu = newTemp(ty);
+         assign(nyu,
+                binop(Iop_Add16, 
+                      binop(Iop_And16,
+                            mkexpr(old),
+                            mkexpr(mask[i])),
+                      binop(Iop_And16,
+                            binop(Iop_Shr16, mkexpr(old), mkU8(shift[i])),
+                            mkexpr(mask[i]))));
+         old = nyu;
+      }
+      return nyu;
+   }
+   if (ty == Ity_I32) {
+      IRTemp old = IRTemp_INVALID;
+      IRTemp nyu = IRTemp_INVALID;
+      IRTemp mask[5], shift[5];
+      for (i = 0; i < 5; i++) {
+         mask[i]  = newTemp(ty);
+         shift[i] = 1 << i;
+      }
+      assign(mask[0], mkU32(0x55555555));
+      assign(mask[1], mkU32(0x33333333));
+      assign(mask[2], mkU32(0x0F0F0F0F));
+      assign(mask[3], mkU32(0x00FF00FF));
+      assign(mask[4], mkU32(0x0000FFFF));
+      old = src;
+      for (i = 0; i < 5; i++) {
+         nyu = newTemp(ty);
+         assign(nyu,
+                binop(Iop_Add32, 
+                      binop(Iop_And32,
+                            mkexpr(old),
+                            mkexpr(mask[i])),
+                      binop(Iop_And32,
+                            binop(Iop_Shr32, mkexpr(old), mkU8(shift[i])),
+                            mkexpr(mask[i]))));
+         old = nyu;
+      }
+      return nyu;
+   }
+   if (ty == Ity_I64) {
+      IRTemp old = IRTemp_INVALID;
+      IRTemp nyu = IRTemp_INVALID;
+      IRTemp mask[6], shift[6];
+      for (i = 0; i < 6; i++) {
+         mask[i]  = newTemp(ty);
+         shift[i] = 1 << i;
+      }
+      assign(mask[0], mkU64(0x5555555555555555ULL));
+      assign(mask[1], mkU64(0x3333333333333333ULL));
+      assign(mask[2], mkU64(0x0F0F0F0F0F0F0F0FULL));
+      assign(mask[3], mkU64(0x00FF00FF00FF00FFULL));
+      assign(mask[4], mkU64(0x0000FFFF0000FFFFULL));
+      assign(mask[5], mkU64(0x00000000FFFFFFFFULL));
+      old = src;
+      for (i = 0; i < 6; i++) {
+         nyu = newTemp(ty);
+         assign(nyu,
+                binop(Iop_Add64, 
+                      binop(Iop_And64,
+                            mkexpr(old),
+                            mkexpr(mask[i])),
+                      binop(Iop_And64,
+                            binop(Iop_Shr64, mkexpr(old), mkU8(shift[i])),
+                            mkexpr(mask[i]))));
+         old = nyu;
+      }
+      return nyu;
+   }
+   /*NOTREACHED*/
+   vassert(0);
+}
+
+
+/* Generate an IR sequence to do a count-leading-zeroes operation on
+   the supplied IRTemp, and return a new IRTemp holding the result.
+   'ty' may be Ity_I16, Ity_I32 or Ity_I64 only.  In the case where
+   the argument is zero, return the number of bits in the word (the
+   natural semantics). */
+static IRTemp gen_LZCNT ( IRType ty, IRTemp src )
+{
+   vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16);
+
+   IRTemp src64 = newTemp(Ity_I64);
+   assign(src64, widenUto64( mkexpr(src) ));
+
+   IRTemp src64x = newTemp(Ity_I64);
+   assign(src64x, 
+          binop(Iop_Shl64, mkexpr(src64),
+                           mkU8(64 - 8 * sizeofIRType(ty))));
+
+   // Clz64 has undefined semantics when its input is zero, so
+   // special-case around that.
+   IRTemp res64 = newTemp(Ity_I64);
+   assign(res64,
+          IRExpr_Mux0X(
+             unop(Iop_1Uto8,
+                  binop(Iop_CmpEQ64, mkexpr(src64x), mkU64(0))),
+             unop(Iop_Clz64, mkexpr(src64x)),
+             mkU64(8 * sizeofIRType(ty))
+   ));
+
+   IRTemp res = newTemp(ty);
+   assign(res, narrowTo(ty, mkexpr(res64)));
+   return res;
+}
+
+

 /*------------------------------------------------------------*/
 /*---                                                      ---*/
 /*--- x87 FLOATING POINT INSTRUCTIONS                      ---*/
 /*------------------------------------------------------------*/
 /*---                                                      ---*/
 /*--- x87 FLOATING POINT INSTRUCTIONS                      ---*/


@@ -6146,11 +6283,12 @@ ULong dis_FPU ( /*OUT*/Bool* decode_ok,
                fp_pop();
                break;
 
                fp_pop();
                break;
 

-//..             case 2: /* FIST m16 */
-//..                DIP("fistp %s\n", dis_buf);
-//..                storeLE( mkexpr(addr), 
-//..                         binop(Iop_F64toI16, get_roundingmode(), get_ST(0)) );
-//..                break;
+            case 2: /* FIST m16 */
+               DIP("fists %s\n", dis_buf);
+               storeLE( mkexpr(addr), 
+                        x87ishly_qnarrow_32_to_16(
+                        binop(Iop_F64toI32S, get_roundingmode(), get_ST(0)) ));
+               break;

 
             case 3: /* FISTP m16 */
                DIP("fistps %s\n", dis_buf);
 
             case 3: /* FISTP m16 */
                DIP("fistps %s\n", dis_buf);


@@ -7230,11 +7368,25 @@ ULong dis_bt_G_E ( VexAbiInfo* vbi,
    
    if (epartIsReg(modrm)) {
       delta++;
    
    if (epartIsReg(modrm)) {
       delta++;

-      /* Get it onto the client's stack. */
+      /* Get it onto the client's stack.  Oh, this is a horrible
+         kludge.  See https://bugs.kde.org/show_bug.cgi?id=245925.
+         Because of the ELF ABI stack redzone, there may be live data
+         up to 128 bytes below %RSP.  So we can't just push it on the
+         stack, else we may wind up trashing live data, and causing
+         impossible-to-find simulation errors.  (Yes, this did
+         happen.)  So we need to drop RSP before at least 128 before
+         pushing it.  That unfortunately means hitting Memcheck's
+         fast-case painting code.  Ideally we should drop more than
+         128, to reduce the chances of breaking buggy programs that
+         have live data below -128(%RSP).  Memcheck fast-cases moves
+         of 288 bytes due to the need to handle ppc64-linux quickly,
+         so let's use 288.  Of course the real fix is to get rid of
+         this kludge entirely.  */

       t_rsp = newTemp(Ity_I64);
       t_addr0 = newTemp(Ity_I64);
 
       t_rsp = newTemp(Ity_I64);
       t_addr0 = newTemp(Ity_I64);
 

-      assign( t_rsp, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(sz)) );
+      vassert(vbi->guest_stack_redzone_size == 128);
+      assign( t_rsp, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(288)) );

       putIReg64(R_RSP, mkexpr(t_rsp));
 
       storeLE( mkexpr(t_rsp), getIRegE(sz, pfx, modrm) );
       putIReg64(R_RSP, mkexpr(t_rsp));
 
       storeLE( mkexpr(t_rsp), getIRegE(sz, pfx, modrm) );


@@ -7333,7 +7485,7 @@ ULong dis_bt_G_E ( VexAbiInfo* vbi,
          standard zero-extend rule */
       if (op != BtOpNone)
          putIRegE(sz, pfx, modrm, loadLE(szToITy(sz), mkexpr(t_rsp)) );
          standard zero-extend rule */
       if (op != BtOpNone)
          putIRegE(sz, pfx, modrm, loadLE(szToITy(sz), mkexpr(t_rsp)) );

-      putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t_rsp), mkU64(sz)) );
+      putIReg64(R_RSP, binop(Iop_Add64, mkexpr(t_rsp), mkU64(288)) );

    }
 
    DIP("bt%s%c %s, %s\n",
    }
 
    DIP("bt%s%c %s, %s\n",


@@ -7719,7 +7871,8 @@ ULong dis_xadd_G_E ( /*OUT*/Bool* decode_ok,
 
    /* There are 3 cases to consider:
 
 
    /* There are 3 cases to consider:
 

-      reg-reg: currently unhandled
+      reg-reg: ignore any lock prefix,
+               generate 'naive' (non-atomic) sequence

 
       reg-mem, not locked: ignore any lock prefix, generate 'naive'
                            (non-atomic) sequence
 
       reg-mem, not locked: ignore any lock prefix, generate 'naive'
                            (non-atomic) sequence


@@ -7729,9 +7882,18 @@ ULong dis_xadd_G_E ( /*OUT*/Bool* decode_ok,
 
    if (epartIsReg(rm)) {
       /* case 1 */
 
    if (epartIsReg(rm)) {
       /* case 1 */

-      *decode_ok = False;
-      return delta0;
-      /* Currently we don't handle xadd_G_E with register operand. */
+      assign( tmpd, getIRegE(sz, pfx, rm) );
+      assign( tmpt0, getIRegG(sz, pfx, rm) );
+      assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8),
+                           mkexpr(tmpd), mkexpr(tmpt0)) );
+      setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty );
+      putIRegG(sz, pfx, rm, mkexpr(tmpd));
+      putIRegE(sz, pfx, rm, mkexpr(tmpt1));
+      DIP("xadd%c %s, %s\n",
+          nameISize(sz), nameIRegG(sz,pfx,rm),
+                                        nameIRegE(sz,pfx,rm));
+      *decode_ok = True;
+      return 1+delta0;

    }
    else if (!epartIsReg(rm) && !(pfx & PFX_LOCK)) {
       /* case 2 */
    }
    else if (!epartIsReg(rm) && !(pfx & PFX_LOCK)) {
       /* case 2 */


@@ -9838,7 +10000,8 @@ DisResult disInstr_AMD64_WRK (
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
       put it into the specified lane of mmx(G). */
    /* ***--- this is an MMX class insn introduced in SSE1 ---*** */
    /* 0F C4 = PINSRW -- get 16 bits from E(mem or low half ireg) and
       put it into the specified lane of mmx(G). */

-   if (haveNo66noF2noF3(pfx) && sz == 4 
+   if (haveNo66noF2noF3(pfx)
+       && (sz == 4 || /* ignore redundant REX.W */ sz == 8)

        && insn[0] == 0x0F && insn[1] == 0xC4) {
       /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the
          mmx reg.  t4 is the new lane value.  t5 is the original
        && insn[0] == 0x0F && insn[1] == 0xC4) {
       /* Use t0 .. t3 to hold the 4 original 16-bit lanes of the
          mmx reg.  t4 is the new lane value.  t5 is the original


@@ -10922,19 +11085,24 @@ DisResult disInstr_AMD64_WRK (
 
    /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */
    /* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */
 
    /* 66 0F 29 = MOVAPD -- move from G (xmm) to E (mem or xmm). */
    /* 66 0F 11 = MOVUPD -- move from G (xmm) to E (mem or xmm). */

-   if (have66noF2noF3(pfx) && insn[0] == 0x0F 
+   if (have66noF2noF3(pfx) && insn[0] == 0x0F

        && (insn[1] == 0x29 || insn[1] == 0x11)) {
        && (insn[1] == 0x29 || insn[1] == 0x11)) {

+      HChar* wot = insn[1]==0x29 ? "apd" : "upd";

       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {
       modrm = getUChar(delta+2);
       if (epartIsReg(modrm)) {

-         /* fall through; awaiting test case */
+         putXMMReg( eregOfRexRM(pfx,modrm),
+                   getXMMReg( gregOfRexRM(pfx,modrm) ) );
+         DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRexRM(pfx,modrm)),
+                                  nameXMMReg(eregOfRexRM(pfx,modrm)));
+         delta += 2+1;

       } else {
          addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
          storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );
       } else {
          addr = disAMode ( &alen, vbi, pfx, delta+2, dis_buf, 0 );
          storeLE( mkexpr(addr), getXMMReg(gregOfRexRM(pfx,modrm)) );

-         DIP("mov[ua]pd %s,%s\n", nameXMMReg(gregOfRexRM(pfx,modrm)),
-                                  dis_buf );
+         DIP("mov%s %s,%s\n", wot, nameXMMReg(gregOfRexRM(pfx,modrm)),
+                              dis_buf );

          delta += 2+alen;
          delta += 2+alen;

-         goto decode_success;

       }
       }

+      goto decode_success;

    }
 
    /* 66 0F 6E = MOVD from ireg32/m32 to xmm lo 1/4, zeroing high 3/4 of xmm. */
    }
 
    /* 66 0F 6E = MOVD from ireg32/m32 to xmm lo 1/4, zeroing high 3/4 of xmm. */


@@ -14236,110 +14404,197 @@ DisResult disInstr_AMD64_WRK (
    }
 
 
    }
 
 

-   /* 66 0F 38 3D /r = PMAXSD xmm1, xmm2/m128
-      Maximum of Packed Signed Double Word Integers (XMM) 
-      --
-      66 0F 38 39 /r = PMINSD xmm1, xmm2/m128
-      Minimum of Packed Signed Double Word Integers (XMM) */
+   /* 66 no-REX.W 0F 3A 22 /r ib = PINSRD xmm1, r/m32, imm8
+      Extract Doubleword int from gen.reg/mem32 and insert into xmm1 */

    if ( have66noF2noF3( pfx ) 
    if ( have66noF2noF3( pfx ) 

-        && sz == 2 
-        && insn[0] == 0x0F && insn[1] == 0x38
-        && ( (insn[2] == 0x3D) || (insn[2] == 0x39) ) ) {
-
-      IRTemp reg_vec  = newTemp(Ity_V128);
-      IRTemp rom_vec  = newTemp(Ity_V128);
-      IRTemp mask_vec = newTemp(Ity_V128);
-
-      Bool isPMAX     = (insn[2] == 0x3D) ? True : False;
+        && sz == 2 /* REX.W is NOT present */
+        && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x22 ) {

 
 

-      HChar* str      = isPMAX ? "pmaxsd" : "pminsd";
+      Int imm8_10;
+      IRTemp src_elems = newTemp(Ity_I32);
+      IRTemp src_vec   = newTemp(Ity_V128);
+      IRTemp z32       = newTemp(Ity_I32);

 
       modrm = insn[3];
 
       modrm = insn[3];

-      assign( reg_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );

 
       if ( epartIsReg( modrm ) ) {
 
       if ( epartIsReg( modrm ) ) {

-         assign( rom_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
-         delta += 3+1;
-         DIP( "%s %s,%s\n", str,
-              nameXMMReg( eregOfRexRM(pfx, modrm) ),
-              nameXMMReg( gregOfRexRM(pfx, modrm) ) );    
+         imm8_10 = (Int)(insn[3+1] & 3);
+         assign( src_elems, getIReg32( eregOfRexRM(pfx,modrm) ) );
+         delta += 3+1+1;
+         DIP( "pinsrd $%d, %s,%s\n", imm8_10,
+              nameIReg32( eregOfRexRM(pfx, modrm) ),
+              nameXMMReg( gregOfRexRM(pfx, modrm) ) );

       } else {
       } else {

-         addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
-         assign( rom_vec, loadLE( Ity_V128, mkexpr(addr) ) );
-         delta += 3+alen;
-         DIP( "%s %s,%s\n", str, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+         addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
+         imm8_10 = (Int)(insn[3+alen] & 3);
+         assign( src_elems, loadLE( Ity_I32, mkexpr(addr) ) );
+         delta += 3+alen+1;
+         DIP( "pinsrd $%d, %s,%s\n", 
+              imm8_10, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );

       }
 
       }
 

-      assign( mask_vec, binop( Iop_CmpGT32Sx4, mkexpr(reg_vec), mkexpr(rom_vec) ) );
+      assign(z32, mkU32(0));

 
 

-      IRTemp max_min_vec = newTemp(Ity_V128);
-      if ( isPMAX ) {
-         assign( max_min_vec,
-                 binop( Iop_OrV128, 
-                        binop( Iop_AndV128, mkexpr(rom_vec),
-                               unop( Iop_NotV128, mkexpr(mask_vec) ) ),
-                        binop( Iop_AndV128, mkexpr(reg_vec), mkexpr(mask_vec) ) ) );
-      } else {
-         assign( max_min_vec, 
-                 binop( Iop_OrV128, 
-                        binop( Iop_AndV128, mkexpr(reg_vec),
-                               unop( Iop_NotV128, mkexpr(mask_vec) ) ), 
-                        binop( Iop_AndV128, mkexpr(rom_vec), mkexpr(mask_vec) ) ) );
+      UShort mask = 0;
+      switch (imm8_10) {
+         case 3:  mask = 0x0FFF;
+                  assign(src_vec, mk128from32s(src_elems, z32, z32, z32));
+                  break;
+         case 2:  mask = 0xF0FF;
+                  assign(src_vec, mk128from32s(z32, src_elems, z32, z32));
+                  break;
+         case 1:  mask = 0xFF0F;
+                  assign(src_vec, mk128from32s(z32, z32, src_elems, z32));
+                  break;
+         case 0:  mask = 0xFFF0;
+                  assign(src_vec, mk128from32s(z32, z32, z32, src_elems));
+                  break;
+         default: vassert(0);

       }
 
       }
 

-      putXMMReg( gregOfRexRM(pfx, modrm), mkexpr(max_min_vec) );
+      putXMMReg( gregOfRexRM(pfx, modrm), 
+                 binop( Iop_OrV128, mkexpr(src_vec),
+                        binop( Iop_AndV128, 
+                               getXMMReg( gregOfRexRM(pfx, modrm) ),
+                               mkV128(mask) ) ) );

 
       goto decode_success;
    }
 
 
       goto decode_success;
    }
 

+   /* 66 0F 3A 20 /r ib = PINSRB xmm1, r32/m8, imm8
+      Extract byte from r32/m8 and insert into xmm1 */
+   if ( have66noF2noF3( pfx )
+        && sz == 2
+        && insn[0] == 0x0F && insn[1] == 0x3A && insn[2] == 0x20 ) {

 
 

-   /* 66 0F 38 3F /r = PMAXUD xmm1, xmm2/m128
-      Maximum of Packed Unsigned Doubleword Integers (XMM) */
-   if ( have66noF2noF3( pfx ) 
-        && sz == 2 
-        && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x3F ) {
+      Int    imm8;
+      IRTemp new8 = newTemp(Ity_I64);

 
 

-      IRTemp reg_vec  = newTemp(Ity_V128);
-      IRTemp rom_vec  = newTemp(Ity_V128);
-      IRTemp mask_vec = newTemp(Ity_V128);
-      IRTemp and_vec  = newTemp(Ity_V128);
-      IRTemp not_vec  = newTemp(Ity_V128);
-  

       modrm = insn[3];
       modrm = insn[3];

-      assign( reg_vec, getXMMReg( gregOfRexRM(pfx, modrm) ) );

 
       if ( epartIsReg( modrm ) ) {
 
       if ( epartIsReg( modrm ) ) {

-         assign( rom_vec, getXMMReg( eregOfRexRM(pfx, modrm) ) );
-         delta += 3+1;
-         DIP( "pmaxud %s,%s\n", 
-              nameXMMReg( eregOfRexRM(pfx, modrm) ),
-              nameXMMReg( gregOfRexRM(pfx, modrm) ) );    
+         imm8 = (Int)(insn[3+1] & 0xF);
+         assign( new8, binop(Iop_And64,
+                             unop(Iop_32Uto64,
+                                  getIReg32(eregOfRexRM(pfx,modrm))),
+                             mkU64(0xFF)));
+         delta += 3+1+1;
+         DIP( "pinsrb $%d,%s,%s\n", imm8,
+              nameIReg32( eregOfRexRM(pfx, modrm) ),
+              nameXMMReg( gregOfRexRM(pfx, modrm) ) );

       } else {
       } else {

-         addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
-         assign( rom_vec, loadLE( Ity_V128, mkexpr(addr) ) );
-         delta += 3+alen;
-         DIP( "pmaxud %s,%s\n", dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+         addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 1 );
+         imm8 = (Int)(insn[3+alen] & 0xF);
+         assign( new8, unop(Iop_8Uto64, loadLE( Ity_I8, mkexpr(addr) )));
+         delta += 3+alen+1;
+         DIP( "pinsrb $%d,%s,%s\n", 
+              imm8, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );

       }
 
       }
 

-      /* the foll. simulates Iop_CmpGT32Ux4 (not implemented) 
-         c.f. Hacker's Delight, S2-11, p.23 */
-      assign( mask_vec, 
-              binop( Iop_XorV128, 
-                     binop( Iop_XorV128, 
-                            binop( Iop_CmpGT32Sx4, mkexpr(reg_vec), mkexpr(rom_vec) ),
-                            binop( Iop_SarN32x4, mkexpr(reg_vec), mkU8(31) ) ), 
-                     binop( Iop_SarN32x4, mkexpr(rom_vec), mkU8(31) ) ) );
+      // Create a V128 value which has the selected byte in the
+      // specified lane, and zeroes everywhere else.
+      IRTemp tmp128 = newTemp(Ity_V128);
+      IRTemp halfshift = newTemp(Ity_I64);
+      assign(halfshift, binop(Iop_Shl64,
+                              mkexpr(new8), mkU8(8 * (imm8 & 7))));
+      vassert(imm8 >= 0 && imm8 <= 15);
+      if (imm8 < 8) {
+         assign(tmp128, binop(Iop_64HLtoV128, mkU64(0), mkexpr(halfshift)));
+      } else {
+         assign(tmp128, binop(Iop_64HLtoV128, mkexpr(halfshift), mkU64(0)));
+      }

 
 

-      assign( and_vec, binop( Iop_AndV128, mkexpr(reg_vec), mkexpr(mask_vec) ) );
-      assign( not_vec, binop( Iop_AndV128, mkexpr(rom_vec), 
-                              unop( Iop_NotV128, mkexpr(mask_vec) ) ) );
+      UShort mask = ~(1 << imm8);

 
       putXMMReg( gregOfRexRM(pfx, modrm), 
 
       putXMMReg( gregOfRexRM(pfx, modrm), 

-                 binop( Iop_OrV128, mkexpr(not_vec), mkexpr(and_vec) ) );
- 
+                 binop( Iop_OrV128,
+                        mkexpr(tmp128),
+                        binop( Iop_AndV128, 
+                               getXMMReg( gregOfRexRM(pfx, modrm) ),
+                               mkV128(mask) ) ) );
+
+      goto decode_success;
+   }
+
+   /* 66 0F 38 37 = PCMPGTQ
+      64x2 comparison (signed, presumably; the Intel docs don't say :-)
+   */
+   if ( have66noF2noF3( pfx ) && sz == 2 
+        && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x37) {
+      delta = dis_SSEint_E_to_G( vbi, pfx, delta+3, 
+                                 "pcmpgtq", Iop_CmpGT64Sx2, False );
+      goto decode_success;
+   }
+
+   /* 66 0F 38 3D /r = PMAXSD xmm1, xmm2/m128
+      Maximum of Packed Signed Double Word Integers (XMM) 
+      66 0F 38 39 /r = PMINSD xmm1, xmm2/m128
+      Minimum of Packed Signed Double Word Integers (XMM) */
+   if ( have66noF2noF3( pfx ) && sz == 2 
+        && insn[0] == 0x0F && insn[1] == 0x38
+        && (insn[2] == 0x3D || insn[2] == 0x39)) {
+      Bool isMAX = insn[2] == 0x3D;
+      delta = dis_SSEint_E_to_G(
+                 vbi, pfx, delta+3, 
+                 isMAX ? "pmaxsd" : "pminsd",
+                 isMAX ? Iop_Max32Sx4 : Iop_Min32Sx4,
+                 False
+              );
+      goto decode_success;
+   }
+
+   /* 66 0F 38 3F /r = PMAXUD xmm1, xmm2/m128
+      Maximum of Packed Unsigned Doubleword Integers (XMM)
+      66 0F 38 3B /r = PMINUD xmm1, xmm2/m128
+      Minimum of Packed Unsigned Doubleword Integers (XMM) */
+   if ( have66noF2noF3( pfx ) && sz == 2 
+        && insn[0] == 0x0F && insn[1] == 0x38
+        && (insn[2] == 0x3F || insn[2] == 0x3B)) {
+      Bool isMAX = insn[2] == 0x3F;
+      delta = dis_SSEint_E_to_G(
+                 vbi, pfx, delta+3, 
+                 isMAX ? "pmaxud" : "pminud",
+                 isMAX ? Iop_Max32Ux4 : Iop_Min32Ux4,
+                 False
+              );
+      goto decode_success;
+   }
+
+   /* 66 0F 38 3E /r = PMAXUW xmm1, xmm2/m128
+      Maximum of Packed Unsigned Word Integers (XMM)
+      66 0F 38 3A /r = PMINUW xmm1, xmm2/m128
+      Minimum of Packed Unsigned Word Integers (XMM)
+   */
+   if ( have66noF2noF3( pfx ) && sz == 2 
+        && insn[0] == 0x0F && insn[1] == 0x38
+        && (insn[2] == 0x3E || insn[2] == 0x3A)) {
+      Bool isMAX = insn[2] == 0x3E;
+      delta = dis_SSEint_E_to_G(
+                 vbi, pfx, delta+3, 
+                 isMAX ? "pmaxuw" : "pminuw",
+                 isMAX ? Iop_Max16Ux8 : Iop_Min16Ux8,
+                 False
+              );

       goto decode_success;
    }
 
       goto decode_success;
    }
 

+   /* 66 0F 38 3C /r = PMAXSB xmm1, xmm2/m128
+      8Sx16 (signed) max
+      66 0F 38 38 /r = PMINSB xmm1, xmm2/m128
+      8Sx16 (signed) min
+   */
+   if ( have66noF2noF3( pfx ) && sz == 2 
+        && insn[0] == 0x0F && insn[1] == 0x38
+        && (insn[2] == 0x3C || insn[2] == 0x38)) {
+      Bool isMAX = insn[2] == 0x3C;
+      delta = dis_SSEint_E_to_G(
+                 vbi, pfx, delta+3, 
+                 isMAX ? "pmaxsb" : "pminsb",
+                 isMAX ? Iop_Max8Sx16 : Iop_Min8Sx16,
+                 False
+              );
+      goto decode_success;
+   }

 
    /* 66 0f 38 20 /r = PMOVSXBW xmm1, xmm2/m64 
       Packed Move with Sign Extend from Byte to Word (XMM) */
 
    /* 66 0f 38 20 /r = PMOVSXBW xmm1, xmm2/m64 
       Packed Move with Sign Extend from Byte to Word (XMM) */


@@ -14783,6 +15038,437 @@ DisResult disInstr_AMD64_WRK (
    }
 
 
    }
 
 

+   /* 66 0f 38 40 /r = PMULLD xmm1, xmm2/m128
+      32x4 integer multiply from xmm2/m128 to xmm1 */
+   if ( have66noF2noF3( pfx ) 
+        && sz == 2 
+        && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x40 ) {
+  
+      modrm = insn[3];
+
+      IRTemp argL = newTemp(Ity_V128);
+      IRTemp argR = newTemp(Ity_V128);
+
+      if ( epartIsReg(modrm) ) {
+         assign( argL, getXMMReg( eregOfRexRM(pfx, modrm) ) );
+         delta += 3+1;
+         DIP( "pmulld %s,%s\n",
+              nameXMMReg( eregOfRexRM(pfx, modrm) ),
+              nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+      } else {
+         addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
+         assign( argL, loadLE( Ity_V128, mkexpr(addr) ));
+         delta += 3+alen;
+         DIP( "pmulld %s,%s\n",
+              dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+      }
+
+      assign(argR, getXMMReg( gregOfRexRM(pfx, modrm) ));
+
+      putXMMReg( gregOfRexRM(pfx, modrm), 
+                 binop( Iop_Mul32x4, mkexpr(argL), mkexpr(argR)) );
+
+      goto decode_success;
+   }
+
+
+   /* F3 0F B8  = POPCNT{W,L,Q}
+      Count the number of 1 bits in a register
+    */
+   if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
+       && insn[0] == 0x0F && insn[1] == 0xB8) {
+      vassert(sz == 2 || sz == 4 || sz == 8);
+      /*IRType*/ ty  = szToITy(sz);
+      IRTemp     src = newTemp(ty);
+      modrm = insn[2];
+      if (epartIsReg(modrm)) {
+         assign(src, getIRegE(sz, pfx, modrm));
+         delta += 2+1;
+         DIP("popcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
+             nameIRegG(sz, pfx, modrm));
+      } else {
+         addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0);
+         assign(src, loadLE(ty, mkexpr(addr)));
+         delta += 2+alen;
+         DIP("popcnt%c %s, %s\n", nameISize(sz), dis_buf,
+             nameIRegG(sz, pfx, modrm));
+      }
+
+      IRTemp result = gen_POPCOUNT(ty, src);
+      putIRegG(sz, pfx, modrm, mkexpr(result));
+
+      // Update flags.  This is pretty lame .. perhaps can do better
+      // if this turns out to be performance critical.
+      // O S A C P are cleared.  Z is set if SRC == 0.
+      stmt( IRStmt_Put( OFFB_CC_OP,   mkU64(AMD64G_CC_OP_COPY) ));
+      stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+      stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+      stmt( IRStmt_Put( OFFB_CC_DEP1,
+            binop(Iop_Shl64,
+                  unop(Iop_1Uto64,
+                       binop(Iop_CmpEQ64,
+                             widenUto64(mkexpr(src)),
+                             mkU64(0))),
+                  mkU8(AMD64G_CC_SHIFT_Z))));
+
+      goto decode_success;
+   }
+
+
+   /* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1
+      (Partial implementation only -- only deal with cases where
+      the rounding mode is specified directly by the immediate byte.)
+      66 0F 3A 0A /r ib = ROUNDSS imm8, xmm2/m32, xmm1
+      (Limitations ditto)
+   */
+   if (have66noF2noF3(pfx) 
+       && sz == 2 
+       && insn[0] == 0x0F && insn[1] == 0x3A
+       && (insn[2] == 0x0B || insn[2] == 0x0A)) {
+
+      Bool   isD = insn[2] == 0x0B;
+      IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32);
+      IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32);
+      Int    imm = 0;
+
+      modrm = insn[3];
+
+      if (epartIsReg(modrm)) {
+         assign( src, 
+                 isD ? getXMMRegLane64F( eregOfRexRM(pfx, modrm), 0 )
+                     : getXMMRegLane32F( eregOfRexRM(pfx, modrm), 0 ) );
+         imm = insn[3+1];
+         if (imm & ~3) goto decode_failure;
+         delta += 3+1+1;
+         DIP( "rounds%c $%d,%s,%s\n",
+              isD ? 'd' : 's',
+              imm, nameXMMReg( eregOfRexRM(pfx, modrm) ),
+                   nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+      } else {
+         addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
+         assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) ));
+         imm = insn[3+alen];
+         if (imm & ~3) goto decode_failure;
+         delta += 3+alen+1;
+         DIP( "roundsd $%d,%s,%s\n",
+              imm, dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+      }
+
+      /* (imm & 3) contains an Intel-encoded rounding mode.  Because
+         that encoding is the same as the encoding for IRRoundingMode,
+         we can use that value directly in the IR as a rounding
+         mode. */
+      assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+                  mkU32(imm & 3), mkexpr(src)) );
+
+      if (isD)
+         putXMMRegLane64F( gregOfRexRM(pfx, modrm), 0, mkexpr(res) );
+      else
+         putXMMRegLane32F( gregOfRexRM(pfx, modrm), 0, mkexpr(res) );
+
+      goto decode_success;
+   }
+
+   /* F3 0F BD -- LZCNT (count leading zeroes.  An AMD extension,
+      which we can only decode if we're sure this is an AMD cpu that
+      supports LZCNT, since otherwise it's BSR, which behaves
+      differently. */
+   if (haveF3noF2(pfx) /* so both 66 and 48 are possibilities */
+       && insn[0] == 0x0F && insn[1] == 0xBD
+       && 0 != (archinfo->hwcaps & VEX_HWCAPS_AMD64_LZCNT)) {
+      vassert(sz == 2 || sz == 4 || sz == 8);
+      /*IRType*/ ty  = szToITy(sz);
+      IRTemp     src = newTemp(ty);
+      modrm = insn[2];
+      if (epartIsReg(modrm)) {
+         assign(src, getIRegE(sz, pfx, modrm));
+         delta += 2+1;
+         DIP("lzcnt%c %s, %s\n", nameISize(sz), nameIRegE(sz, pfx, modrm),
+             nameIRegG(sz, pfx, modrm));
+      } else {
+         addr = disAMode( &alen, vbi, pfx, delta+2, dis_buf, 0);
+         assign(src, loadLE(ty, mkexpr(addr)));
+         delta += 2+alen;
+         DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf,
+             nameIRegG(sz, pfx, modrm));
+      }
+
+      IRTemp res = gen_LZCNT(ty, src);
+      putIRegG(sz, pfx, modrm, mkexpr(res));
+
+      // Update flags.  This is pretty lame .. perhaps can do better
+      // if this turns out to be performance critical.
+      // O S A P are cleared.  Z is set if RESULT == 0.
+      // C is set if SRC is zero.
+      IRTemp src64 = newTemp(Ity_I64);
+      IRTemp res64 = newTemp(Ity_I64);
+      assign(src64, widenUto64(mkexpr(src)));
+      assign(res64, widenUto64(mkexpr(res)));
+
+      IRTemp oszacp = newTemp(Ity_I64);
+      assign(
+         oszacp,
+         binop(Iop_Or64,
+               binop(Iop_Shl64,
+                     unop(Iop_1Uto64,
+                          binop(Iop_CmpEQ64, mkexpr(res64), mkU64(0))),
+                     mkU8(AMD64G_CC_SHIFT_Z)),
+               binop(Iop_Shl64,
+                     unop(Iop_1Uto64,
+                          binop(Iop_CmpEQ64, mkexpr(src64), mkU64(0))),
+                     mkU8(AMD64G_CC_SHIFT_C))
+         )
+      );
+
+      stmt( IRStmt_Put( OFFB_CC_OP,   mkU64(AMD64G_CC_OP_COPY) ));
+      stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+      stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+      stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) ));
+
+      goto decode_success;
+   }
+
+   /* 66 0F 3A 63 /r ib = PCMPISTRI imm8, xmm2/m128, xmm1
+      66 0F 3A 62 /r ib = PCMPISTRM imm8, xmm2/m128, xmm1
+      66 0F 3A 61 /r ib = PCMPESTRI imm8, xmm2/m128, xmm1
+      66 0F 3A 60 /r ib = PCMPESTRM imm8, xmm2/m128, xmm1
+      (selected special cases that actually occur in glibc,
+       not by any means a complete implementation.)
+   */
+   if (have66noF2noF3(pfx) 
+       && sz == 2 
+       && insn[0] == 0x0F && insn[1] == 0x3A
+       && (insn[2] >= 0x60 && insn[2] <= 0x63)) {
+
+      UInt  isISTRx = insn[2] & 2;
+      UInt  isxSTRM = (insn[2] & 1) ^ 1;
+      UInt  regNoL = 0;
+      UInt  regNoR = 0;
+      UChar imm    = 0;
+
+      /* This is a nasty kludge.  We need to pass 2 x V128 to the
+         helper (which is clean).  Since we can't do that, use a dirty
+         helper to compute the results directly from the XMM regs in
+         the guest state.  That means for the memory case, we need to
+         move the left operand into a pseudo-register (XMM16, let's
+         call it). */
+      modrm = insn[3];
+      if (epartIsReg(modrm)) {
+         regNoL = eregOfRexRM(pfx, modrm);
+         regNoR = gregOfRexRM(pfx, modrm);
+         imm = insn[3+1];
+         delta += 3+1+1;
+      } else {
+         regNoL = 16; /* use XMM16 as an intermediary */
+         regNoR = gregOfRexRM(pfx, modrm);
+         addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
+         stmt( IRStmt_Put( OFFB_XMM16, loadLE(Ity_V128, mkexpr(addr)) ));
+         imm = insn[3+alen];
+         delta += 3+alen+1;
+      }
+
+      /* Now we know the XMM reg numbers for the operands, and the
+         immediate byte.  Is it one we can actually handle? Throw out
+         any cases for which the helper function has not been
+         verified. */
+      switch (imm) {
+         case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
+         case 0x1A: case 0x3A: case 0x44: case 0x4A:
+            break;
+         default:
+            goto decode_failure;
+      }
+
+      /* Who ya gonna call?  Presumably not Ghostbusters. */
+      void*  fn = &amd64g_dirtyhelper_PCMPxSTRx;
+      HChar* nm = "amd64g_dirtyhelper_PCMPxSTRx";
+
+      /* Round up the arguments.  Note that this is a kludge -- the
+         use of mkU64 rather than mkIRExpr_HWord implies the
+         assumption that the host's word size is 64-bit. */
+      UInt gstOffL = regNoL == 16 ? OFFB_XMM16 : xmmGuestRegOffset(regNoL);
+      UInt gstOffR = xmmGuestRegOffset(regNoR);
+
+      IRExpr*  opc4_and_imm = mkU64((insn[2] << 8) | (imm & 0xFF));
+      IRExpr*  gstOffLe     = mkU64(gstOffL);
+      IRExpr*  gstOffRe     = mkU64(gstOffR);
+      IRExpr*  edxIN        = isISTRx ? mkU64(0) : getIRegRDX(8);
+      IRExpr*  eaxIN        = isISTRx ? mkU64(0) : getIRegRAX(8);
+      IRExpr** args
+         = mkIRExprVec_5( opc4_and_imm, gstOffLe, gstOffRe, edxIN, eaxIN );
+
+      IRTemp   resT = newTemp(Ity_I64);
+      IRDirty* d    = unsafeIRDirty_1_N( resT, 0/*regparms*/, nm, fn, args );
+      /* It's not really a dirty call, but we can't use the clean
+         helper mechanism here for the very lame reason that we can't
+         pass 2 x V128s by value to a helper, nor get one back.  Hence
+         this roundabout scheme. */
+      d->needsBBP = True;
+      d->nFxState = 2;
+      d->fxState[0].fx     = Ifx_Read;
+      d->fxState[0].offset = gstOffL;
+      d->fxState[0].size   = sizeof(U128);
+      d->fxState[1].fx     = Ifx_Read;
+      d->fxState[1].offset = gstOffR;
+      d->fxState[1].size   = sizeof(U128);
+      if (isxSTRM) {
+         /* Declare that the helper writes XMM0. */
+         d->nFxState = 3;
+         d->fxState[2].fx     = Ifx_Write;
+         d->fxState[2].offset = xmmGuestRegOffset(0);
+         d->fxState[2].size   = sizeof(U128);
+      }
+
+      stmt( IRStmt_Dirty(d) );
+
+      /* Now resT[15:0] holds the new OSZACP values, so the condition
+         codes must be updated. And for a xSTRI case, resT[31:16]
+         holds the new ECX value, so stash that too. */
+      if (!isxSTRM) {
+         putIReg64(R_RCX, binop(Iop_And64,
+                                binop(Iop_Shr64, mkexpr(resT), mkU8(16)),
+                                mkU64(0xFFFF)));
+      }
+
+      stmt( IRStmt_Put(
+               OFFB_CC_DEP1,
+               binop(Iop_And64, mkexpr(resT), mkU64(0xFFFF))
+      ));
+      stmt( IRStmt_Put( OFFB_CC_OP,   mkU64(AMD64G_CC_OP_COPY) ));
+      stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+      stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+
+      if (regNoL == 16) {
+         DIP("pcmp%cstr%c $%x,%s,%s\n",
+             isISTRx ? 'i' : 'e', isxSTRM ? 'm' : 'i',
+             (UInt)imm, dis_buf, nameXMMReg(regNoR));
+      } else {
+         DIP("pcmp%cstr%c $%x,%s,%s\n",
+             isISTRx ? 'i' : 'e', isxSTRM ? 'm' : 'i',
+             (UInt)imm, nameXMMReg(regNoL), nameXMMReg(regNoR));
+      }
+
+      goto decode_success;
+   }
+
+
+   /* 66 0f 38 17 /r = PTEST xmm1, xmm2/m128
+      Logical compare (set ZF and CF from AND/ANDN of the operands) */
+   if (have66noF2noF3( pfx ) && sz == 2 
+       && insn[0] == 0x0F && insn[1] == 0x38 && insn[2] == 0x17) {
+      modrm = insn[3];
+      IRTemp vecE = newTemp(Ity_V128);
+      IRTemp vecG = newTemp(Ity_V128);
+
+      if ( epartIsReg(modrm) ) {
+         assign(vecE, getXMMReg(eregOfRexRM(pfx, modrm)));
+         delta += 3+1;
+         DIP( "ptest %s,%s\n", 
+              nameXMMReg( eregOfRexRM(pfx, modrm) ),
+              nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+      } else {
+         addr = disAMode( &alen, vbi, pfx, delta+3, dis_buf, 0 );
+         assign(vecE, loadLE( Ity_V128, mkexpr(addr) ));
+         delta += 3+alen;
+         DIP( "ptest %s,%s\n",
+              dis_buf, nameXMMReg( gregOfRexRM(pfx, modrm) ) );
+      }
+
+      assign(vecG, getXMMReg(gregOfRexRM(pfx, modrm)));
+
+      /* Set Z=1 iff (vecE & vecG) == 0
+         Set C=1 iff (vecE & not vecG) == 0
+      */
+
+      /* andV, andnV:  vecE & vecG,  vecE and not(vecG) */
+      IRTemp andV  = newTemp(Ity_V128);
+      IRTemp andnV = newTemp(Ity_V128);
+      assign(andV,  binop(Iop_AndV128, mkexpr(vecE), mkexpr(vecG)));
+      assign(andnV, binop(Iop_AndV128,
+                          mkexpr(vecE),
+                          binop(Iop_XorV128, mkexpr(vecG),
+                                             mkV128(0xFFFF))));
+
+      /* The same, but reduced to 64-bit values, by or-ing the top
+         and bottom 64-bits together.  It relies on this trick:
+
+          InterleaveLO64x2([a,b],[c,d]) == [b,d]    hence
+
+          InterleaveLO64x2([a,b],[a,b]) == [b,b]    and similarly
+          InterleaveHI64x2([a,b],[a,b]) == [a,a] 
+
+          and so the OR of the above 2 exprs produces
+          [a OR b, a OR b], from which we simply take the lower half.
+      */
+      IRTemp and64  = newTemp(Ity_I64);
+      IRTemp andn64 = newTemp(Ity_I64);
+   
+      assign(
+         and64,
+         unop(Iop_V128to64,
+              binop(Iop_OrV128,
+                    binop(Iop_InterleaveLO64x2, mkexpr(andV), mkexpr(andV)),
+                    binop(Iop_InterleaveHI64x2, mkexpr(andV), mkexpr(andV))
+              )
+         )
+      );
+
+      assign(
+         andn64,
+         unop(Iop_V128to64,
+              binop(Iop_OrV128,
+                    binop(Iop_InterleaveLO64x2, mkexpr(andnV), mkexpr(andnV)),
+                    binop(Iop_InterleaveHI64x2, mkexpr(andnV), mkexpr(andnV))
+              )
+          )
+       );
+
+      /* Now convert and64, andn64 to all-zeroes or all-1s, so we can
+         slice out the Z and C bits conveniently.  We use the standard
+         trick all-zeroes -> all-zeroes, anything-else -> all-ones
+         done by "(x | -x) >>s (word-size - 1)".
+      */
+      IRTemp z64 = newTemp(Ity_I64);
+      IRTemp c64 = newTemp(Ity_I64);
+      assign(z64,
+             unop(Iop_Not64,
+                  binop(Iop_Sar64,
+                        binop(Iop_Or64,
+                              binop(Iop_Sub64, mkU64(0), mkexpr(and64)),
+                              mkexpr(and64)
+                        ), 
+                        mkU8(63)))
+      );
+
+      assign(c64,
+             unop(Iop_Not64,
+                  binop(Iop_Sar64,
+                        binop(Iop_Or64,
+                              binop(Iop_Sub64, mkU64(0), mkexpr(andn64)),
+                              mkexpr(andn64)
+                        ),
+                        mkU8(63)))
+      );
+
+      /* And finally, slice out the Z and C flags and set the flags
+         thunk to COPY for them.  OSAP are set to zero. */
+      IRTemp newOSZACP = newTemp(Ity_I64);
+      assign(newOSZACP, 
+             binop(Iop_Or64,
+                   binop(Iop_And64, mkexpr(z64), mkU64(AMD64G_CC_MASK_Z)),
+                   binop(Iop_And64, mkexpr(c64), mkU64(AMD64G_CC_MASK_C))
+             )
+      );
+
+      stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(newOSZACP)));
+      stmt( IRStmt_Put( OFFB_CC_OP,   mkU64(AMD64G_CC_OP_COPY) ));
+      stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+      stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+
+      goto decode_success;
+   }
+
+

    /* ---------------------------------------------------- */
    /* --- end of the SSE4 decoder                      --- */
    /* ---------------------------------------------------- */
    /* ---------------------------------------------------- */
    /* --- end of the SSE4 decoder                      --- */
    /* ---------------------------------------------------- */


@@ -16827,13 +17513,16 @@ DisResult disInstr_AMD64_WRK (
          if (haveF2orF3(pfx)) goto decode_failure;
          if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3
                                   |VEX_HWCAPS_AMD64_CX16)) {
          if (haveF2orF3(pfx)) goto decode_failure;
          if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3
                                   |VEX_HWCAPS_AMD64_CX16)) {

-            fName = "amd64g_dirtyhelper_CPUID_sse3_and_cx16";
-            fAddr = &amd64g_dirtyhelper_CPUID_sse3_and_cx16; 
+            //fName = "amd64g_dirtyhelper_CPUID_sse3_and_cx16";
+            //fAddr = &amd64g_dirtyhelper_CPUID_sse3_and_cx16; 

             /* This is a Core-2-like machine */
             /* This is a Core-2-like machine */

+            fName = "amd64g_dirtyhelper_CPUID_sse42_and_cx16";
+            fAddr = &amd64g_dirtyhelper_CPUID_sse42_and_cx16;
+            /* This is a Core-i5-like machine */

          }
          else {
          }
          else {

-            /* Give a CPUID for at least a baseline machine, no SSE2
-               and no CX16 */
+            /* Give a CPUID for at least a baseline machine, SSE2
+               only, and no CX16 */

             fName = "amd64g_dirtyhelper_CPUID_baseline";
             fAddr = &amd64g_dirtyhelper_CPUID_baseline;
          }
             fName = "amd64g_dirtyhelper_CPUID_baseline";
             fAddr = &amd64g_dirtyhelper_CPUID_baseline;
          }


@@ -17249,6 +17938,41 @@ DisResult disInstr_AMD64_WRK (
          DIP("{f}emms\n");
          break;
 
          DIP("{f}emms\n");
          break;
 

+      /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */
+      case 0x01: /* 0F 01 /0 -- SGDT */
+                 /* 0F 01 /1 -- SIDT */
+      {
+          /* This is really revolting, but ... since each processor
+             (core) only has one IDT and one GDT, just let the guest
+             see it (pass-through semantics).  I can't see any way to
+             construct a faked-up value, so don't bother to try. */
+         modrm = getUChar(delta);
+         addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+         delta += alen;
+         if (epartIsReg(modrm)) goto decode_failure;
+         if (gregLO3ofRM(modrm) != 0 && gregLO3ofRM(modrm) != 1)
+            goto decode_failure;
+         switch (gregLO3ofRM(modrm)) {
+            case 0: DIP("sgdt %s\n", dis_buf); break;
+            case 1: DIP("sidt %s\n", dis_buf); break;
+            default: vassert(0); /*NOTREACHED*/
+         }
+
+         IRDirty* d = unsafeIRDirty_0_N (
+                          0/*regparms*/,
+                          "amd64g_dirtyhelper_SxDT",
+                          &amd64g_dirtyhelper_SxDT,
+                          mkIRExprVec_2( mkexpr(addr),
+                                         mkU64(gregLO3ofRM(modrm)) )
+                      );
+         /* declare we're writing memory */
+         d->mFx   = Ifx_Write;
+         d->mAddr = mkexpr(addr);
+         d->mSize = 6;
+         stmt( IRStmt_Dirty(d) );
+         break;
+      }
+

       /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */
 
       default:
       /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */
 
       default:


@@ -17390,6 +18114,72 @@ DisResult disInstr_AMD64 ( IRSB*        irsb_IN,
 }
 
 
 }
 
 

+/*------------------------------------------------------------*/
+/*--- Unused stuff                                         ---*/
+/*------------------------------------------------------------*/
+
+// A potentially more Memcheck-friendly version of gen_LZCNT, if
+// this should ever be needed.
+//
+//static IRTemp gen_LZCNT ( IRType ty, IRTemp src )
+//{
+//   /* Scheme is simple: propagate the most significant 1-bit into all
+//      lower positions in the word.  This gives a word of the form
+//      0---01---1.  Now invert it, giving a word of the form
+//      1---10---0, then do a population-count idiom (to count the 1s,
+//      which is the number of leading zeroes, or the word size if the
+//      original word was 0.
+//   */
+//   Int i;
+//   IRTemp t[7];
+//   for (i = 0; i < 7; i++) {
+//      t[i] = newTemp(ty);
+//   }
+//   if (ty == Ity_I64) {
+//      assign(t[0], binop(Iop_Or64, mkexpr(src),
+//                                   binop(Iop_Shr64, mkexpr(src),  mkU8(1))));
+//      assign(t[1], binop(Iop_Or64, mkexpr(t[0]),
+//                                   binop(Iop_Shr64, mkexpr(t[0]), mkU8(2))));
+//      assign(t[2], binop(Iop_Or64, mkexpr(t[1]),
+//                                   binop(Iop_Shr64, mkexpr(t[1]), mkU8(4))));
+//      assign(t[3], binop(Iop_Or64, mkexpr(t[2]),
+//                                   binop(Iop_Shr64, mkexpr(t[2]), mkU8(8))));
+//      assign(t[4], binop(Iop_Or64, mkexpr(t[3]),
+//                                   binop(Iop_Shr64, mkexpr(t[3]), mkU8(16))));
+//      assign(t[5], binop(Iop_Or64, mkexpr(t[4]),
+//                                   binop(Iop_Shr64, mkexpr(t[4]), mkU8(32))));
+//      assign(t[6], unop(Iop_Not64, mkexpr(t[5])));
+//      return gen_POPCOUNT(ty, t[6]);
+//   }
+//   if (ty == Ity_I32) {
+//      assign(t[0], binop(Iop_Or32, mkexpr(src),
+//                                   binop(Iop_Shr32, mkexpr(src),  mkU8(1))));
+//      assign(t[1], binop(Iop_Or32, mkexpr(t[0]),
+//                                   binop(Iop_Shr32, mkexpr(t[0]), mkU8(2))));
+//      assign(t[2], binop(Iop_Or32, mkexpr(t[1]),
+//                                   binop(Iop_Shr32, mkexpr(t[1]), mkU8(4))));
+//      assign(t[3], binop(Iop_Or32, mkexpr(t[2]),
+//                                   binop(Iop_Shr32, mkexpr(t[2]), mkU8(8))));
+//      assign(t[4], binop(Iop_Or32, mkexpr(t[3]),
+//                                   binop(Iop_Shr32, mkexpr(t[3]), mkU8(16))));
+//      assign(t[5], unop(Iop_Not32, mkexpr(t[4])));
+//      return gen_POPCOUNT(ty, t[5]);
+//   }
+//   if (ty == Ity_I16) {
+//      assign(t[0], binop(Iop_Or16, mkexpr(src),
+//                                   binop(Iop_Shr16, mkexpr(src),  mkU8(1))));
+//      assign(t[1], binop(Iop_Or16, mkexpr(t[0]),
+//                                   binop(Iop_Shr16, mkexpr(t[0]), mkU8(2))));
+//      assign(t[2], binop(Iop_Or16, mkexpr(t[1]),
+//                                   binop(Iop_Shr16, mkexpr(t[1]), mkU8(4))));
+//      assign(t[3], binop(Iop_Or16, mkexpr(t[2]),
+//                                   binop(Iop_Shr16, mkexpr(t[2]), mkU8(8))));
+//      assign(t[4], unop(Iop_Not16, mkexpr(t[3])));
+//      return gen_POPCOUNT(ty, t[4]);
+//   }
+//   vassert(0);
+//}
+

 
 /*--------------------------------------------------------------------*/
 /*--- end                                       guest_amd64_toIR.c ---*/
 
 /*--------------------------------------------------------------------*/
 /*--- end                                       guest_amd64_toIR.c ---*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_defs.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_defs.h
index 87a10d5aff2bb8cf88c44985ef4763cb53182c98..02078c4595b01500fae64b3ebb77c9db80ec23b7 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_defs.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_defs.h
@@ -55,8 +55,10 @@ DisResult disInstr_ARM ( IRSB*        irbb,
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern

-IRExpr* guest_arm_spechelper ( HChar* function_name,
-                               IRExpr** args );
+IRExpr* guest_arm_spechelper ( HChar*   function_name,
+                               IRExpr** args,
+                               IRStmt** precedingStmts,
+                               Int      n_precedingStmts );

 
 /* Describes to the optimser which part of the guest state require
    precise memory exceptions.  This is logically part of the guest
 
 /* Describes to the optimser which part of the guest state require
    precise memory exceptions.  This is logically part of the guest


@@ -100,6 +102,12 @@ UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */,
                                 UInt cc_dep1,
                                 UInt cc_dep2, UInt cc_dep3 );
 
                                 UInt cc_dep1,
                                 UInt cc_dep2, UInt cc_dep3 );
 

+/* Calculate the QC flag from the thunk components, in the lowest bit
+   of the word (bit 0). */
+extern 
+UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2,
+                              UInt resR1, UInt resR2 );
+

 
 /*---------------------------------------------------------*/
 /*--- Condition code stuff                              ---*/
 
 /*---------------------------------------------------------*/
 /*--- Condition code stuff                              ---*/


@@ -110,14 +118,16 @@ UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */,
 #define ARMG_CC_SHIFT_Z  30
 #define ARMG_CC_SHIFT_C  29
 #define ARMG_CC_SHIFT_V  28
 #define ARMG_CC_SHIFT_Z  30
 #define ARMG_CC_SHIFT_C  29
 #define ARMG_CC_SHIFT_V  28

+#define ARMG_CC_SHIFT_Q  27

 
 #define ARMG_CC_MASK_N    (1 << ARMG_CC_SHIFT_N)
 #define ARMG_CC_MASK_Z    (1 << ARMG_CC_SHIFT_Z)
 #define ARMG_CC_MASK_C    (1 << ARMG_CC_SHIFT_C)
 #define ARMG_CC_MASK_V    (1 << ARMG_CC_SHIFT_V)
 
 #define ARMG_CC_MASK_N    (1 << ARMG_CC_SHIFT_N)
 #define ARMG_CC_MASK_Z    (1 << ARMG_CC_SHIFT_Z)
 #define ARMG_CC_MASK_C    (1 << ARMG_CC_SHIFT_C)
 #define ARMG_CC_MASK_V    (1 << ARMG_CC_SHIFT_V)

+#define ARMG_CC_MASK_Q    (1 << ARMG_CC_SHIFT_Q)

 
 /* Flag thunk descriptors.  A four-word thunk is used to record
 
 /* Flag thunk descriptors.  A four-word thunk is used to record

-   details of the most recent flag-setting operation, so the flags can
+   details of the most recent flag-setting operation, so NZCV can

    be computed later if needed.
 
    The four words are:
    be computed later if needed.
 
    The four words are:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_helpers.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_helpers.c
index 2394e0536cbade5bcae0069228b4868fb2d002e3..2adbb391c932ff775c5cc87d32f036c67c59ec54 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_helpers.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_helpers.c
@@ -204,6 +204,18 @@ UInt armg_calculate_flag_v ( UInt cc_op, UInt cc_dep1,
    return (r >> ARMG_CC_SHIFT_V) & 1;
 }
 
    return (r >> ARMG_CC_SHIFT_V) & 1;
 }
 

+/* CALLED FROM GENERATED CODE: CLEAN HELPER */
+/* Calculate the QC flag from the arguments, in the lowest bit
+   of the word (bit 0).  Urr, having this out of line is bizarre.
+   Push back inline. */
+UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2,
+                              UInt resR1, UInt resR2 )
+{
+   if (resL1 != resR1 || resL2 != resR2)
+      return 1;
+   else
+      return 0;
+}

 
 /* CALLED FROM GENERATED CODE: CLEAN HELPER */
 /* Calculate the specified condition from the thunk components, in the
 
 /* CALLED FROM GENERATED CODE: CLEAN HELPER */
 /* Calculate the specified condition from the thunk components, in the


@@ -215,10 +227,15 @@ UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */,
 {
    UInt cond  = cond_n_op >> 4;
    UInt cc_op = cond_n_op & 0xF;
 {
    UInt cond  = cond_n_op >> 4;
    UInt cc_op = cond_n_op & 0xF;

-   UInt nf, zf, vf, cf;
-   UInt inv  = cond & 1;
-   //   vex_printf("XXXXXXXX %x %x %x %x\n", cond_n_op, cc_dep1, cc_dep2, cc_dep3);
-   UInt nzcv = armg_calculate_flags_nzcv(cc_op, cc_dep1, cc_dep2, cc_dep3);
+   UInt nf, zf, vf, cf, nzcv, inv;
+   //   vex_printf("XXXXXXXX %x %x %x %x\n", 
+   //              cond_n_op, cc_dep1, cc_dep2, cc_dep3);
+
+   // skip flags computation in this case
+   if (cond == ARMCondAL) return 1;
+
+   inv  = cond & 1;
+   nzcv = armg_calculate_flags_nzcv(cc_op, cc_dep1, cc_dep2, cc_dep3);

 
    switch (cond) {
       case ARMCondEQ:    // Z=1         => z
 
    switch (cond) {
       case ARMCondEQ:    // Z=1         => z


@@ -260,7 +277,7 @@ UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */,
          zf = nzcv >> ARMG_CC_SHIFT_Z;
          return 1 & (inv ^ ~(zf | (nf ^ vf)));
 
          zf = nzcv >> ARMG_CC_SHIFT_Z;
          return 1 & (inv ^ ~(zf | (nf ^ vf)));
 

-      case ARMCondAL: // should never get here: Always => no flags to calc
+      case ARMCondAL: // handled above

       case ARMCondNV: // should never get here: Illegal instr
       default:
          /* shouldn't really make these calls from generated code */
       case ARMCondNV: // should never get here: Illegal instr
       default:
          /* shouldn't really make these calls from generated code */


@@ -289,8 +306,10 @@ static Bool isU32 ( IRExpr* e, UInt n )
               && e->Iex.Const.con->Ico.U32 == n );
 }
 
               && e->Iex.Const.con->Ico.U32 == n );
 }
 

-IRExpr* guest_arm_spechelper ( HChar* function_name,
-                               IRExpr** args )
+IRExpr* guest_arm_spechelper ( HChar*   function_name,
+                               IRExpr** args,
+                               IRStmt** precedingStmts,
+                               Int      n_precedingStmts )

 {
 #  define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
 #  define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))
 {
 #  define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
 #  define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))


@@ -310,7 +329,7 @@ IRExpr* guest_arm_spechelper ( HChar* function_name,
    vex_printf("\n");
 #  endif
 
    vex_printf("\n");
 #  endif
 

-   /* --------- specialising "x86g_calculate_condition" --------- */
+   /* --------- specialising "armg_calculate_condition" --------- */

 
    if (vex_streq(function_name, "armg_calculate_condition")) {
       /* specialise calls to above "armg_calculate condition" function */
 
    if (vex_streq(function_name, "armg_calculate_condition")) {
       /* specialise calls to above "armg_calculate condition" function */


@@ -341,7 +360,7 @@ IRExpr* guest_arm_spechelper ( HChar* function_name,
       }
 
       if (isU32(cond_n_op, (ARMCondLT << 4) | ARMG_CC_OP_SUB)) {
       }
 
       if (isU32(cond_n_op, (ARMCondLT << 4) | ARMG_CC_OP_SUB)) {

-         /* LE after SUB --> test argL <s argR */
+         /* LT after SUB --> test argL <s argR */

          return unop(Iop_1Uto32,
                      binop(Iop_CmpLT32S, cc_dep1, cc_dep2));
       }
          return unop(Iop_1Uto32,
                      binop(Iop_CmpLT32S, cc_dep1, cc_dep2));
       }


@@ -378,6 +397,51 @@ IRExpr* guest_arm_spechelper ( HChar* function_name,
                      binop(Iop_CmpNE32, cc_dep1, mkU32(0)));
       }
 
                      binop(Iop_CmpNE32, cc_dep1, mkU32(0)));
       }
 

+      /*----------------- AL -----------------*/
+      /* A critically important case for Thumb code.
+
+         What we're trying to spot is the case where cond_n_op is an
+         expression of the form Or32(..., 0xE0) since that means the
+         caller is asking for CondAL and we can simply return 1
+         without caring what the ... part is.  This is a potentially
+         dodgy kludge in that it assumes that the ... part has zeroes
+         in bits 7:4, so that the result of the Or32 is guaranteed to
+         be 0xE in bits 7:4.  Given that the places where this first
+         arg are constructed (in guest_arm_toIR.c) are very
+         constrained, we can get away with this.  To make this
+         guaranteed safe would require to have a new primop, Slice44
+         or some such, thusly
+
+         Slice44(arg1, arg2) = 0--(24)--0 arg1[7:4] arg2[3:0]
+
+         and we would then look for Slice44(0xE0, ...)
+         which would give the required safety property.
+
+         It would be infeasibly expensive to scan backwards through
+         the entire block looking for an assignment to the temp, so
+         just look at the previous 16 statements.  That should find it
+         if it is an interesting case, as a result of how the
+         boilerplate guff at the start of each Thumb insn translation
+         is made.
+      */
+      if (cond_n_op->tag == Iex_RdTmp) {
+         Int    j;
+         IRTemp look_for = cond_n_op->Iex.RdTmp.tmp;
+         Int    limit    = n_precedingStmts - 16;
+         if (limit < 0) limit = 0;
+         if (0) vex_printf("scanning %d .. %d\n", n_precedingStmts-1, limit);
+         for (j = n_precedingStmts - 1; j >= limit; j--) {
+            IRStmt* st = precedingStmts[j];
+            if (st->tag == Ist_WrTmp
+                && st->Ist.WrTmp.tmp == look_for
+                && st->Ist.WrTmp.data->tag == Iex_Binop
+                && st->Ist.WrTmp.data->Iex.Binop.op == Iop_Or32
+                && isU32(st->Ist.WrTmp.data->Iex.Binop.arg2, (ARMCondAL << 4)))
+               return mkU32(1);
+         }
+         /* Didn't find any useful binding to the first arg
+            in the previous 16 stmts. */
+      }

    }
 
 #  undef unop
    }
 
 #  undef unop


@@ -442,12 +506,13 @@ void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state )
    vex_state->guest_R12 = 0;
    vex_state->guest_R13 = 0;
    vex_state->guest_R14 = 0;
    vex_state->guest_R12 = 0;
    vex_state->guest_R13 = 0;
    vex_state->guest_R14 = 0;

-   vex_state->guest_R15 = 0;
+   vex_state->guest_R15T = 0;  /* NB: implies ARM mode */

 
    vex_state->guest_CC_OP   = ARMG_CC_OP_COPY;
    vex_state->guest_CC_DEP1 = 0;
    vex_state->guest_CC_DEP2 = 0;
    vex_state->guest_CC_NDEP = 0;
 
    vex_state->guest_CC_OP   = ARMG_CC_OP_COPY;
    vex_state->guest_CC_DEP1 = 0;
    vex_state->guest_CC_DEP2 = 0;
    vex_state->guest_CC_NDEP = 0;

+   vex_state->guest_QFLAG32 = 0;

 
    vex_state->guest_EMWARN  = 0;
    vex_state->guest_TISTART = 0;
 
    vex_state->guest_EMWARN  = 0;
    vex_state->guest_TISTART = 0;


@@ -471,6 +536,22 @@ void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state )
    vex_state->guest_D13 = 0;
    vex_state->guest_D14 = 0;
    vex_state->guest_D15 = 0;
    vex_state->guest_D13 = 0;
    vex_state->guest_D14 = 0;
    vex_state->guest_D15 = 0;

+   vex_state->guest_D16 = 0;
+   vex_state->guest_D17 = 0;
+   vex_state->guest_D18 = 0;
+   vex_state->guest_D19 = 0;
+   vex_state->guest_D20 = 0;
+   vex_state->guest_D21 = 0;
+   vex_state->guest_D22 = 0;
+   vex_state->guest_D23 = 0;
+   vex_state->guest_D24 = 0;
+   vex_state->guest_D25 = 0;
+   vex_state->guest_D26 = 0;
+   vex_state->guest_D27 = 0;
+   vex_state->guest_D28 = 0;
+   vex_state->guest_D29 = 0;
+   vex_state->guest_D30 = 0;
+   vex_state->guest_D31 = 0;

 
    /* ARM encoded; zero is the default as it happens (result flags
       (NZCV) cleared, FZ disabled, round to nearest, non-vector mode,
 
    /* ARM encoded; zero is the default as it happens (result flags
       (NZCV) cleared, FZ disabled, round to nearest, non-vector mode,


@@ -479,8 +560,12 @@ void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state )
 
    vex_state->guest_TPIDRURO = 0;
 
 
    vex_state->guest_TPIDRURO = 0;
 

-   /* vex_state->padding1 = 0; */
-   /* vex_state->padding2 = 0; */
+   /* Not in a Thumb IT block. */
+   vex_state->guest_ITSTATE = 0;
+
+   vex_state->padding1 = 0;
+   vex_state->padding2 = 0;
+   vex_state->padding3 = 0;

 }
 
 
 }
 
 


@@ -493,14 +578,14 @@ void LibVEX_GuestARM_initialise ( /*OUT*/VexGuestARMState* vex_state )
    .. maxoff requires precise memory exceptions.  If in doubt return
    True (but this is generates significantly slower code).  
 
    .. maxoff requires precise memory exceptions.  If in doubt return
    True (but this is generates significantly slower code).  
 

-   We enforce precise exns for guest R13(sp), R15(pc).
+   We enforce precise exns for guest R13(sp), R15T(pc).

 */
 Bool guest_arm_state_requires_precise_mem_exns ( Int minoff, 
                                                  Int maxoff)
 {
    Int sp_min = offsetof(VexGuestARMState, guest_R13);
    Int sp_max = sp_min + 4 - 1;
 */
 Bool guest_arm_state_requires_precise_mem_exns ( Int minoff, 
                                                  Int maxoff)
 {
    Int sp_min = offsetof(VexGuestARMState, guest_R13);
    Int sp_max = sp_min + 4 - 1;

-   Int pc_min = offsetof(VexGuestARMState, guest_R15);
+   Int pc_min = offsetof(VexGuestARMState, guest_R15T);

    Int pc_max = pc_min + 4 - 1;
 
    if (maxoff < sp_min || minoff > sp_max) {
    Int pc_max = pc_min + 4 - 1;
 
    if (maxoff < sp_min || minoff > sp_max) {


@@ -546,18 +631,18 @@ VexGuestLayout
           .sizeof_SP = 4,
 
           /* Describe the instruction pointer. */
           .sizeof_SP = 4,
 
           /* Describe the instruction pointer. */

-          .offset_IP = offsetof(VexGuestARMState,guest_R15),
+          .offset_IP = offsetof(VexGuestARMState,guest_R15T),

           .sizeof_IP = 4,
 
           /* Describe any sections to be regarded by Memcheck as
              'always-defined'. */
           .sizeof_IP = 4,
 
           /* Describe any sections to be regarded by Memcheck as
              'always-defined'. */

-          .n_alwaysDefd = 9,
+          .n_alwaysDefd = 10,

 
           /* flags thunk: OP is always defd, whereas DEP1 and DEP2
              have to be tracked.  See detailed comment in gdefs.h on
              meaning of thunk fields. */
           .alwaysDefd
 
           /* flags thunk: OP is always defd, whereas DEP1 and DEP2
              have to be tracked.  See detailed comment in gdefs.h on
              meaning of thunk fields. */
           .alwaysDefd

-             = { /* 0 */ ALWAYSDEFD(guest_R15),
+             = { /* 0 */ ALWAYSDEFD(guest_R15T),

                  /* 1 */ ALWAYSDEFD(guest_CC_OP),
                  /* 2 */ ALWAYSDEFD(guest_CC_NDEP),
                  /* 3 */ ALWAYSDEFD(guest_EMWARN),
                  /* 1 */ ALWAYSDEFD(guest_CC_OP),
                  /* 2 */ ALWAYSDEFD(guest_CC_NDEP),
                  /* 3 */ ALWAYSDEFD(guest_EMWARN),


@@ -565,7 +650,8 @@ VexGuestLayout
                  /* 5 */ ALWAYSDEFD(guest_TILEN),
                  /* 6 */ ALWAYSDEFD(guest_NRADDR),
                  /* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL),
                  /* 5 */ ALWAYSDEFD(guest_TILEN),
                  /* 6 */ ALWAYSDEFD(guest_NRADDR),
                  /* 7 */ ALWAYSDEFD(guest_IP_AT_SYSCALL),

-                 /* 8 */ ALWAYSDEFD(guest_TPIDRURO)
+                 /* 8 */ ALWAYSDEFD(guest_TPIDRURO),
+                 /* 9 */ ALWAYSDEFD(guest_ITSTATE)

                }
         };
 
                }
         };
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_toIR.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_toIR.c
index ec5d2eaecab8e69431a7fd1a2b5f9b3c614bdf4e..e570ba80ae2695cbd512e2883f5f1c7e2de235f1 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_toIR.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_arm_toIR.c
@@ -9,6 +9,8 @@
 
    Copyright (C) 2004-2010 OpenWorks LLP
       info@open-works.net
 
    Copyright (C) 2004-2010 OpenWorks LLP
       info@open-works.net

+   Copyright (C) 2010-2010 Dmitry Zhurikhin
+      zhur@ispras.ru

 
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as
 
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as


@@ -28,6 +30,38 @@
    The GNU General Public License is contained in the file COPYING.
 */
 
    The GNU General Public License is contained in the file COPYING.
 */
 

+/* XXXX thumb to check:
+   that all cases where putIRegT writes r15, we generate a jump.
+
+   All uses of newTemp assign to an IRTemp and not a UInt
+
+   For all thumb loads and stores, including VFP ones, new-ITSTATE is
+   backed out before the memory op, and restored afterwards.  This
+   needs to happen even after we go uncond.  (and for sure it doesn't
+   happen for VFP loads/stores right now).
+
+   VFP on thumb: check that we exclude all r13/r15 cases that we
+   should.
+
+   XXXX thumb to do: improve the ITSTATE-zeroing optimisation by
+   taking into account the number of insns guarded by an IT.
+
+   remove the nasty hack, in the spechelper, of looking for Or32(...,
+   0xE0) in as the first arg to armg_calculate_condition, and instead
+   use Slice44 as specified in comments in the spechelper.
+
+   add specialisations for armg_calculate_flag_c and _v, as they
+   are moderately often needed in Thumb code.
+
+   Correctness: ITSTATE handling in Thumb SVCs is wrong.
+
+   Correctness (obscure): in m_transtab, when invalidating code
+   address ranges, invalidate up to 18 bytes after the end of the
+   range.  This is because the ITSTATE optimisation at the top of
+   _THUMB_WRK below analyses up to 18 bytes before the start of any
+   given instruction, and so might depend on the invalidated area.
+*/
+

 /* Limitations, etc
 
    - pretty dodgy exception semantics for {LD,ST}Mxx, no doubt
 /* Limitations, etc
 
    - pretty dodgy exception semantics for {LD,ST}Mxx, no doubt


@@ -35,7 +69,6 @@
    - SWP: the restart jump back is Ijk_Boring; it should be
      Ijk_NoRedir but that's expensive.  See comments on casLE() in
      guest_x86_toIR.c.
    - SWP: the restart jump back is Ijk_Boring; it should be
      Ijk_NoRedir but that's expensive.  See comments on casLE() in
      guest_x86_toIR.c.

-

 */
 
 /* "Special" instructions.
 */
 
 /* "Special" instructions.


@@ -90,8 +123,13 @@
 static Bool host_is_bigendian;
 
 /* CONST: The guest address for the instruction currently being
 static Bool host_is_bigendian;
 
 /* CONST: The guest address for the instruction currently being

-   translated. */
-static Addr32 guest_R15_curr_instr;
+   translated.  This is the real, "decoded" address (not subject
+   to the CPSR.T kludge). */
+static Addr32 guest_R15_curr_instr_notENC;
+
+/* CONST, FOR ASSERTIONS ONLY.  Indicates whether currently processed
+   insn is Thumb (True) or ARM (False). */
+static Bool __curr_is_Thumb;

 
 /* MOD: The IRSB* into which we're generating code. */
 static IRSB* irsb;
 
 /* MOD: The IRSB* into which we're generating code. */
 static IRSB* irsb;


@@ -132,6 +170,12 @@ static IRTemp r15kind;
    if (vex_traceflags & VEX_TRACE_FE)  \
       vex_sprintf(buf, format, ## args)
 
    if (vex_traceflags & VEX_TRACE_FE)  \
       vex_sprintf(buf, format, ## args)
 

+#define ASSERT_IS_THUMB \
+   do { vassert(__curr_is_Thumb); } while (0)
+
+#define ASSERT_IS_ARM \
+   do { vassert(! __curr_is_Thumb); } while (0)
+

 
 /*------------------------------------------------------------*/
 /*--- Helper bits and pieces for deconstructing the        ---*/
 
 /*------------------------------------------------------------*/
 /*--- Helper bits and pieces for deconstructing the        ---*/


@@ -150,6 +194,16 @@ static inline UInt getUIntLittleEndianly ( UChar* p )
    return w;
 }
 
    return w;
 }
 

+/* Do a little-endian load of a 16-bit word, regardless of the
+   endianness of the underlying host. */
+static inline UShort getUShortLittleEndianly ( UChar* p )
+{
+   UShort w = 0;
+   w = (w << 8) | p[1];
+   w = (w << 8) | p[0];
+   return w;
+}
+

 static UInt ROR32 ( UInt x, UInt sh ) {
    vassert(sh >= 0 && sh < 32);
    if (sh == 0)
 static UInt ROR32 ( UInt x, UInt sh ) {
    vassert(sh >= 0 && sh < 32);
    if (sh == 0)


@@ -158,6 +212,24 @@ static UInt ROR32 ( UInt x, UInt sh ) {
       return (x << (32-sh)) | (x >> sh);
 }
 
       return (x << (32-sh)) | (x >> sh);
 }
 

+static Int popcount32 ( UInt x )
+{
+   Int res = 0, i;
+   for (i = 0; i < 32; i++) {
+      res += (x & 1);
+      x >>= 1;
+   }
+   return res;
+}
+
+static UInt setbit32 ( UInt x, Int ix, UInt b )
+{
+   UInt mask = 1 << ix;
+   x &= ~mask;
+   x |= ((b << ix) & mask);
+   return x;
+}
+

 #define BITS2(_b1,_b0) \
    (((_b1) << 1) | (_b0))
 
 #define BITS2(_b1,_b0) \
    (((_b1) << 1) | (_b0))
 


@@ -171,16 +243,32 @@ static UInt ROR32 ( UInt x, UInt sh ) {
    ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \
     | BITS4((_b3),(_b2),(_b1),(_b0)))
 
    ((BITS4((_b7),(_b6),(_b5),(_b4)) << 4) \
     | BITS4((_b3),(_b2),(_b1),(_b0)))
 

+#define BITS5(_b4,_b3,_b2,_b1,_b0)  \
+   (BITS8(0,0,0,(_b4),(_b3),(_b2),(_b1),(_b0)))
+#define BITS6(_b5,_b4,_b3,_b2,_b1,_b0)  \
+   (BITS8(0,0,(_b5),(_b4),(_b3),(_b2),(_b1),(_b0)))
+#define BITS7(_b6,_b5,_b4,_b3,_b2,_b1,_b0)  \
+   (BITS8(0,(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0)))
+
+#define BITS9(_b8,_b7,_b6,_b5,_b4,_b3,_b2,_b1,_b0)      \
+   (((_b8) << 8) \
+    | BITS8((_b7),(_b6),(_b5),(_b4),(_b3),(_b2),(_b1),(_b0)))
+

 /* produces _uint[_bMax:_bMin] */
 #define SLICE_UInt(_uint,_bMax,_bMin) \
    (( ((UInt)(_uint)) >> (_bMin)) \
 /* produces _uint[_bMax:_bMin] */
 #define SLICE_UInt(_uint,_bMax,_bMin) \
    (( ((UInt)(_uint)) >> (_bMin)) \

-      & ((1 << ((_bMax) - (_bMin) + 1)) - 1))
+    & (UInt)((1ULL << ((_bMax) - (_bMin) + 1)) - 1ULL))

 
 
 /*------------------------------------------------------------*/
 /*--- Helper bits and pieces for creating IR fragments.    ---*/
 /*------------------------------------------------------------*/
 
 
 
 /*------------------------------------------------------------*/
 /*--- Helper bits and pieces for creating IR fragments.    ---*/
 /*------------------------------------------------------------*/
 

+static IRExpr* mkU64 ( ULong i )
+{
+   return IRExpr_Const(IRConst_U64(i));
+}
+

 static IRExpr* mkU32 ( UInt i )
 {
    return IRExpr_Const(IRConst_U32(i));
 static IRExpr* mkU32 ( UInt i )
 {
    return IRExpr_Const(IRConst_U32(i));


@@ -259,6 +347,21 @@ static IRExpr* genROR32( IRTemp src, Int rot )
             binop(Iop_Shr32, mkexpr(src), mkU8(rot)));
 }
 
             binop(Iop_Shr32, mkexpr(src), mkU8(rot)));
 }
 

+static IRExpr* mkU128 ( ULong i )
+{
+   return binop(Iop_64HLtoV128, mkU64(i), mkU64(i));
+}
+
+/* Generate a 4-aligned version of the given expression if
+   the given condition is true.  Else return it unchanged. */
+static IRExpr* align4if ( IRExpr* e, Bool b )
+{
+   if (b)
+      return binop(Iop_And32, e, mkU32(~3));
+   else
+      return e;
+}
+

 
 /*------------------------------------------------------------*/
 /*--- Helpers for accessing guest registers.               ---*/
 
 /*------------------------------------------------------------*/
 /*--- Helpers for accessing guest registers.               ---*/


@@ -279,7 +382,7 @@ static IRExpr* genROR32( IRTemp src, Int rot )
 #define OFFB_R12      offsetof(VexGuestARMState,guest_R12)
 #define OFFB_R13      offsetof(VexGuestARMState,guest_R13)
 #define OFFB_R14      offsetof(VexGuestARMState,guest_R14)
 #define OFFB_R12      offsetof(VexGuestARMState,guest_R12)
 #define OFFB_R13      offsetof(VexGuestARMState,guest_R13)
 #define OFFB_R14      offsetof(VexGuestARMState,guest_R14)

-#define OFFB_R15      offsetof(VexGuestARMState,guest_R15)
+#define OFFB_R15T     offsetof(VexGuestARMState,guest_R15T)

 
 #define OFFB_CC_OP    offsetof(VexGuestARMState,guest_CC_OP)
 #define OFFB_CC_DEP1  offsetof(VexGuestARMState,guest_CC_DEP1)
 
 #define OFFB_CC_OP    offsetof(VexGuestARMState,guest_CC_OP)
 #define OFFB_CC_DEP1  offsetof(VexGuestARMState,guest_CC_DEP1)


@@ -303,9 +406,27 @@ static IRExpr* genROR32( IRTemp src, Int rot )
 #define OFFB_D13      offsetof(VexGuestARMState,guest_D13)
 #define OFFB_D14      offsetof(VexGuestARMState,guest_D14)
 #define OFFB_D15      offsetof(VexGuestARMState,guest_D15)
 #define OFFB_D13      offsetof(VexGuestARMState,guest_D13)
 #define OFFB_D14      offsetof(VexGuestARMState,guest_D14)
 #define OFFB_D15      offsetof(VexGuestARMState,guest_D15)

+#define OFFB_D16      offsetof(VexGuestARMState,guest_D16)
+#define OFFB_D17      offsetof(VexGuestARMState,guest_D17)
+#define OFFB_D18      offsetof(VexGuestARMState,guest_D18)
+#define OFFB_D19      offsetof(VexGuestARMState,guest_D19)
+#define OFFB_D20      offsetof(VexGuestARMState,guest_D20)
+#define OFFB_D21      offsetof(VexGuestARMState,guest_D21)
+#define OFFB_D22      offsetof(VexGuestARMState,guest_D22)
+#define OFFB_D23      offsetof(VexGuestARMState,guest_D23)
+#define OFFB_D24      offsetof(VexGuestARMState,guest_D24)
+#define OFFB_D25      offsetof(VexGuestARMState,guest_D25)
+#define OFFB_D26      offsetof(VexGuestARMState,guest_D26)
+#define OFFB_D27      offsetof(VexGuestARMState,guest_D27)
+#define OFFB_D28      offsetof(VexGuestARMState,guest_D28)
+#define OFFB_D29      offsetof(VexGuestARMState,guest_D29)
+#define OFFB_D30      offsetof(VexGuestARMState,guest_D30)
+#define OFFB_D31      offsetof(VexGuestARMState,guest_D31)

 
 #define OFFB_FPSCR    offsetof(VexGuestARMState,guest_FPSCR)
 #define OFFB_TPIDRURO offsetof(VexGuestARMState,guest_TPIDRURO)
 
 #define OFFB_FPSCR    offsetof(VexGuestARMState,guest_FPSCR)
 #define OFFB_TPIDRURO offsetof(VexGuestARMState,guest_TPIDRURO)

+#define OFFB_ITSTATE  offsetof(VexGuestARMState,guest_ITSTATE)
+#define OFFB_QFLAG32  offsetof(VexGuestARMState,guest_QFLAG32)

 
 
 /* ---------------- Integer registers ---------------- */
 
 
 /* ---------------- Integer registers ---------------- */


@@ -331,7 +452,7 @@ static Int integerGuestRegOffset ( UInt iregNo )
       case 12: return OFFB_R12;
       case 13: return OFFB_R13;
       case 14: return OFFB_R14;
       case 12: return OFFB_R12;
       case 13: return OFFB_R13;
       case 14: return OFFB_R14;

-      case 15: return OFFB_R15;
+      case 15: return OFFB_R15T;

       default: vassert(0);
    }
 }
       default: vassert(0);
    }
 }


@@ -343,11 +464,12 @@ static IRExpr* llGetIReg ( UInt iregNo )
    return IRExpr_Get( integerGuestRegOffset(iregNo), Ity_I32 );
 }
 
    return IRExpr_Get( integerGuestRegOffset(iregNo), Ity_I32 );
 }
 

-/* Architected read from a reg.  This automagically adds 8 to all 
-   reads of r15. */
-static IRExpr* getIReg ( UInt iregNo )
+/* Architected read from a reg in ARM mode.  This automagically adds 8
+   to all reads of r15. */
+static IRExpr* getIRegA ( UInt iregNo )

 {
    IRExpr* e;
 {
    IRExpr* e;

+   ASSERT_IS_ARM;

    vassert(iregNo < 16);
    if (iregNo == 15) {
       /* If asked for r15, don't read the guest state value, as that
    vassert(iregNo < 16);
    if (iregNo == 15) {
       /* If asked for r15, don't read the guest state value, as that


@@ -356,7 +478,25 @@ static IRExpr* getIReg ( UInt iregNo )
          omitted; hence in the 2nd and subsequent unrollings we don't
          have a correct value in guest r15.  Instead produce the
          constant that we know would be produced at this point. */
          omitted; hence in the 2nd and subsequent unrollings we don't
          have a correct value in guest r15.  Instead produce the
          constant that we know would be produced at this point. */

-      e = mkU32(guest_R15_curr_instr + 8);
+      vassert(0 == (guest_R15_curr_instr_notENC & 3));
+      e = mkU32(guest_R15_curr_instr_notENC + 8);
+   } else {
+      e = IRExpr_Get( integerGuestRegOffset(iregNo), Ity_I32 );
+   }
+   return e;
+}
+
+/* Architected read from a reg in Thumb mode.  This automagically adds
+   4 to all reads of r15. */
+static IRExpr* getIRegT ( UInt iregNo )
+{
+   IRExpr* e;
+   ASSERT_IS_THUMB;
+   vassert(iregNo < 16);
+   if (iregNo == 15) {
+      /* Ditto comment in getIReg. */
+      vassert(0 == (guest_R15_curr_instr_notENC & 1));
+      e = mkU32(guest_R15_curr_instr_notENC + 4);

    } else {
       e = IRExpr_Get( integerGuestRegOffset(iregNo), Ity_I32 );
    }
    } else {
       e = IRExpr_Get( integerGuestRegOffset(iregNo), Ity_I32 );
    }


@@ -372,19 +512,23 @@ static void llPutIReg ( UInt iregNo, IRExpr* e )
    stmt( IRStmt_Put(integerGuestRegOffset(iregNo), e) );
 }
 
    stmt( IRStmt_Put(integerGuestRegOffset(iregNo), e) );
 }
 

-/* Architected write to a reg.  If it is to r15, record info so at the
-   end of this insn's translation, a branch to it can be made.  Also
-   handles conditional writes to the register:
-   if guardT == IRTemp_INVALID then the write is unconditional.
-   If writing r15, also 4-align it. */
-static void putIReg ( UInt       iregNo,
-                      IRExpr*    e,
-                      IRTemp     guardT /* :: Ity_I32, 0 or 1 */,
-                      IRJumpKind jk /* if a jump is generated */ )
+/* Architected write to an integer register in ARM mode.  If it is to
+   r15, record info so at the end of this insn's translation, a branch
+   to it can be made.  Also handles conditional writes to the
+   register: if guardT == IRTemp_INVALID then the write is
+   unconditional.  If writing r15, also 4-align it. */
+static void putIRegA ( UInt       iregNo,
+                       IRExpr*    e,
+                       IRTemp     guardT /* :: Ity_I32, 0 or 1 */,
+                       IRJumpKind jk /* if a jump is generated */ )

 {
    /* if writing r15, force e to be 4-aligned. */
 {
    /* if writing r15, force e to be 4-aligned. */

-   if (iregNo == 15)
-      e = binop(Iop_And32, e, mkU32(~3));
+   // INTERWORKING FIXME.  this needs to be relaxed so that
+   // puts caused by LDMxx which load r15 interwork right.
+   // but is no aligned too relaxed?
+   //if (iregNo == 15)
+   //   e = binop(Iop_And32, e, mkU32(~3));
+   ASSERT_IS_ARM;

    /* So, generate either an unconditional or a conditional write to
       the reg. */
    if (guardT == IRTemp_INVALID) {
    /* So, generate either an unconditional or a conditional write to
       the reg. */
    if (guardT == IRTemp_INVALID) {


@@ -410,6 +554,40 @@ static void putIReg ( UInt       iregNo,
 }
 
 
 }
 
 

+/* Architected write to an integer register in Thumb mode.  Writes to
+   r15 are not allowed.  Handles conditional writes to the register:
+   if guardT == IRTemp_INVALID then the write is unconditional. */
+static void putIRegT ( UInt       iregNo,
+                       IRExpr*    e,
+                       IRTemp     guardT /* :: Ity_I32, 0 or 1 */ )
+{
+   /* So, generate either an unconditional or a conditional write to
+      the reg. */
+   ASSERT_IS_THUMB;
+   vassert(iregNo >= 0 && iregNo <= 14);
+   if (guardT == IRTemp_INVALID) {
+      /* unconditional write */
+      llPutIReg( iregNo, e );
+   } else {
+      llPutIReg( iregNo,
+                 IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)),
+                               llGetIReg(iregNo),
+                               e ));
+   }
+}
+
+
+/* Thumb16 and Thumb32 only.
+   Returns true if reg is 13 or 15.  Implements the BadReg
+   predicate in the ARM ARM. */
+static Bool isBadRegT ( UInt r )
+{
+   vassert(r <= 15);
+   ASSERT_IS_THUMB;
+   return r == 13 || r == 15;
+}
+
+

 /* ---------------- Double registers ---------------- */
 
 static Int doubleGuestRegOffset ( UInt dregNo )
 /* ---------------- Double registers ---------------- */
 
 static Int doubleGuestRegOffset ( UInt dregNo )


@@ -434,6 +612,22 @@ static Int doubleGuestRegOffset ( UInt dregNo )
       case 13: return OFFB_D13;
       case 14: return OFFB_D14;
       case 15: return OFFB_D15;
       case 13: return OFFB_D13;
       case 14: return OFFB_D14;
       case 15: return OFFB_D15;

+      case 16: return OFFB_D16;
+      case 17: return OFFB_D17;
+      case 18: return OFFB_D18;
+      case 19: return OFFB_D19;
+      case 20: return OFFB_D20;
+      case 21: return OFFB_D21;
+      case 22: return OFFB_D22;
+      case 23: return OFFB_D23;
+      case 24: return OFFB_D24;
+      case 25: return OFFB_D25;
+      case 26: return OFFB_D26;
+      case 27: return OFFB_D27;
+      case 28: return OFFB_D28;
+      case 29: return OFFB_D29;
+      case 30: return OFFB_D30;
+      case 31: return OFFB_D31;

       default: vassert(0);
    }
 }
       default: vassert(0);
    }
 }


@@ -441,7 +635,7 @@ static Int doubleGuestRegOffset ( UInt dregNo )
 /* Plain ("low level") read from a VFP Dreg. */
 static IRExpr* llGetDReg ( UInt dregNo )
 {
 /* Plain ("low level") read from a VFP Dreg. */
 static IRExpr* llGetDReg ( UInt dregNo )
 {

-   vassert(dregNo < 16);
+   vassert(dregNo < 32);

    return IRExpr_Get( doubleGuestRegOffset(dregNo), Ity_F64 );
 }
 
    return IRExpr_Get( doubleGuestRegOffset(dregNo), Ity_F64 );
 }
 


@@ -453,7 +647,7 @@ static IRExpr* getDReg ( UInt dregNo ) {
 /* Plain ("low level") write to a VFP Dreg. */
 static void llPutDReg ( UInt dregNo, IRExpr* e )
 {
 /* Plain ("low level") write to a VFP Dreg. */
 static void llPutDReg ( UInt dregNo, IRExpr* e )
 {

-   vassert(dregNo < 16);
+   vassert(dregNo < 32);

    vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64);
    stmt( IRStmt_Put(doubleGuestRegOffset(dregNo), e) );
 }
    vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64);
    stmt( IRStmt_Put(doubleGuestRegOffset(dregNo), e) );
 }


@@ -478,12 +672,123 @@ static void putDReg ( UInt    dregNo,
    }
 }
 
    }
 }
 

+/* And now exactly the same stuff all over again, but this time
+   taking/returning I64 rather than F64, to support 64-bit Neon
+   ops. */
+
+/* Plain ("low level") read from a Neon Integer Dreg. */
+static IRExpr* llGetDRegI64 ( UInt dregNo )
+{
+   vassert(dregNo < 32);
+   return IRExpr_Get( doubleGuestRegOffset(dregNo), Ity_I64 );
+}
+
+/* Architected read from a Neon Integer Dreg. */
+static IRExpr* getDRegI64 ( UInt dregNo ) {
+   return llGetDRegI64( dregNo );
+}
+
+/* Plain ("low level") write to a Neon Integer Dreg. */
+static void llPutDRegI64 ( UInt dregNo, IRExpr* e )
+{
+   vassert(dregNo < 32);
+   vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64);
+   stmt( IRStmt_Put(doubleGuestRegOffset(dregNo), e) );
+}
+
+/* Architected write to a Neon Integer Dreg.  Handles conditional
+   writes to the register: if guardT == IRTemp_INVALID then the write
+   is unconditional. */
+static void putDRegI64 ( UInt    dregNo,
+                         IRExpr* e,
+                         IRTemp  guardT /* :: Ity_I32, 0 or 1 */)
+{
+   /* So, generate either an unconditional or a conditional write to
+      the reg. */
+   if (guardT == IRTemp_INVALID) {
+      /* unconditional write */
+      llPutDRegI64( dregNo, e );
+   } else {
+      llPutDRegI64( dregNo,
+                    IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)),
+                                  llGetDRegI64(dregNo),
+                                  e ));
+   }
+}
+
+/* ---------------- Quad registers ---------------- */
+
+static Int quadGuestRegOffset ( UInt qregNo )
+{
+   /* Do we care about endianness here?  Probably do if we ever get
+      into the situation of dealing with the 64 bit Neon registers. */
+   switch (qregNo) {
+      case 0:  return OFFB_D0;
+      case 1:  return OFFB_D2;
+      case 2:  return OFFB_D4;
+      case 3:  return OFFB_D6;
+      case 4:  return OFFB_D8;
+      case 5:  return OFFB_D10;
+      case 6:  return OFFB_D12;
+      case 7:  return OFFB_D14;
+      case 8:  return OFFB_D16;
+      case 9:  return OFFB_D18;
+      case 10: return OFFB_D20;
+      case 11: return OFFB_D22;
+      case 12: return OFFB_D24;
+      case 13: return OFFB_D26;
+      case 14: return OFFB_D28;
+      case 15: return OFFB_D30;
+      default: vassert(0);
+   }
+}
+
+/* Plain ("low level") read from a Neon Qreg. */
+static IRExpr* llGetQReg ( UInt qregNo )
+{
+   vassert(qregNo < 16);
+   return IRExpr_Get( quadGuestRegOffset(qregNo), Ity_V128 );
+}
+
+/* Architected read from a Neon Qreg. */
+static IRExpr* getQReg ( UInt qregNo ) {
+   return llGetQReg( qregNo );
+}
+
+/* Plain ("low level") write to a Neon Qreg. */
+static void llPutQReg ( UInt qregNo, IRExpr* e )
+{
+   vassert(qregNo < 16);
+   vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128);
+   stmt( IRStmt_Put(quadGuestRegOffset(qregNo), e) );
+}
+
+/* Architected write to a Neon Qreg.  Handles conditional writes to the
+   register: if guardT == IRTemp_INVALID then the write is
+   unconditional. */
+static void putQReg ( UInt    qregNo,
+                      IRExpr* e,
+                      IRTemp  guardT /* :: Ity_I32, 0 or 1 */)
+{
+   /* So, generate either an unconditional or a conditional write to
+      the reg. */
+   if (guardT == IRTemp_INVALID) {
+      /* unconditional write */
+      llPutQReg( qregNo, e );
+   } else {
+      llPutQReg( qregNo,
+                 IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)),
+                               llGetQReg(qregNo),
+                               e ));
+   }
+}
+

 
 /* ---------------- Float registers ---------------- */
 
 static Int floatGuestRegOffset ( UInt fregNo )
 {
 
 /* ---------------- Float registers ---------------- */
 
 static Int floatGuestRegOffset ( UInt fregNo )
 {

-   /* Start with the offset of the containing double, and the correct
+   /* Start with the offset of the containing double, and then correct

       for endianness.  Actually this is completely bogus and needs
       careful thought. */
    Int off;
       for endianness.  Actually this is completely bogus and needs
       careful thought. */
    Int off;


@@ -546,7 +851,8 @@ static void putMiscReg32 ( UInt    gsoffset,
                            IRTemp  guardT /* :: Ity_I32, 0 or 1 */)
 {
    switch (gsoffset) {
                            IRTemp  guardT /* :: Ity_I32, 0 or 1 */)
 {
    switch (gsoffset) {

-      case OFFB_FPSCR: break;
+      case OFFB_FPSCR:   break;
+      case OFFB_QFLAG32: break;

       default: vassert(0); /* awaiting more cases */
    }
    vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);
       default: vassert(0); /* awaiting more cases */
    }
    vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);


@@ -555,15 +861,50 @@ static void putMiscReg32 ( UInt    gsoffset,
       /* unconditional write */
       stmt(IRStmt_Put(gsoffset, e));
    } else {
       /* unconditional write */
       stmt(IRStmt_Put(gsoffset, e));
    } else {

-      vassert(0); //ATC
-      stmt(IRStmt_Put( gsoffset,
-                       IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)),
-                                     IRExpr_Get(gsoffset, Ity_I32),
-                                     e) ));
-
+      stmt(IRStmt_Put(
+         gsoffset,
+         IRExpr_Mux0X( unop(Iop_32to8, mkexpr(guardT)),
+                       IRExpr_Get(gsoffset, Ity_I32),
+                       e
+         )
+      ));

    }
 }
 
    }
 }
 

+static IRTemp get_ITSTATE ( void )
+{
+   ASSERT_IS_THUMB;
+   IRTemp t = newTemp(Ity_I32);
+   assign(t, IRExpr_Get( OFFB_ITSTATE, Ity_I32));
+   return t;
+}
+
+static void put_ITSTATE ( IRTemp t )
+{
+   ASSERT_IS_THUMB;
+   stmt( IRStmt_Put( OFFB_ITSTATE, mkexpr(t)) );
+}
+
+static IRTemp get_QFLAG32 ( void )
+{
+   IRTemp t = newTemp(Ity_I32);
+   assign(t, IRExpr_Get( OFFB_QFLAG32, Ity_I32));
+   return t;
+}
+
+static void put_QFLAG32 ( IRTemp t, IRTemp condT )
+{
+   putMiscReg32( OFFB_QFLAG32, mkexpr(t), condT );
+}
+
+static void or_into_QFLAG32 ( IRTemp t, IRTemp condT )
+{
+   IRTemp old = get_QFLAG32();
+   IRTemp nyu = newTemp(Ity_I32);
+   assign(nyu, binop(Iop_Or32, mkexpr(old), mkexpr(t)) );
+   put_QFLAG32(nyu, condT);
+}
+

 
 /* ---------------- FPSCR stuff ---------------- */
 
 
 /* ---------------- FPSCR stuff ---------------- */
 


@@ -641,18 +982,28 @@ static HChar* nCC ( ARMCondcode cond ) {
 /* Build IR to calculate some particular condition from stored
    CC_OP/CC_DEP1/CC_DEP2/CC_NDEP.  Returns an expression of type
    Ity_I32, suitable for narrowing.  Although the return type is
 /* Build IR to calculate some particular condition from stored
    CC_OP/CC_DEP1/CC_DEP2/CC_NDEP.  Returns an expression of type
    Ity_I32, suitable for narrowing.  Although the return type is

-   Ity_I32, the returned value is either 0 or 1.
+   Ity_I32, the returned value is either 0 or 1.  'cond' must be
+   :: Ity_I32 and must denote the condition to compute in 
+   bits 7:4, and be zero everywhere else.

 */
 */

-static IRExpr* mk_armg_calculate_condition ( ARMCondcode cond )
+static IRExpr* mk_armg_calculate_condition_dyn ( IRExpr* cond )

 {
 {

-  /* First arg is "(cond << 4) | condition".  This requires that the
-     ARM_CC_OP_ values all fit in 4 bits.  Hence we are passing a
-     (COND, OP) pair in the lowest 8 bits of the first argument. */
-   vassert(cond >= 0 && cond <= 15);
+   vassert(typeOfIRExpr(irsb->tyenv, cond) == Ity_I32);
+   /* And 'cond' had better produce a value in which only bits 7:4
+      bits are nonzero.  However, obviously we can't assert for
+      that. */
+
+   /* So what we're constructing for the first argument is 
+      "(cond << 4) | stored-operation-operation".  However,
+      as per comments above, must be supplied pre-shifted to this
+      function.
+
+      This pairing scheme requires that the ARM_CC_OP_ values all fit
+      in 4 bits.  Hence we are passing a (COND, OP) pair in the lowest
+      8 bits of the first argument. */

    IRExpr** args
       = mkIRExprVec_4(
    IRExpr** args
       = mkIRExprVec_4(

-           binop(Iop_Or32, IRExpr_Get(OFFB_CC_OP, Ity_I32),
-                           mkU32(cond << 4)),
+           binop(Iop_Or32, IRExpr_Get(OFFB_CC_OP, Ity_I32), cond),

            IRExpr_Get(OFFB_CC_DEP1, Ity_I32),
            IRExpr_Get(OFFB_CC_DEP2, Ity_I32),
            IRExpr_Get(OFFB_CC_NDEP, Ity_I32)
            IRExpr_Get(OFFB_CC_DEP1, Ity_I32),
            IRExpr_Get(OFFB_CC_DEP2, Ity_I32),
            IRExpr_Get(OFFB_CC_NDEP, Ity_I32)


@@ -672,6 +1023,21 @@ static IRExpr* mk_armg_calculate_condition ( ARMCondcode cond )
 }
 
 
 }
 
 

+/* Build IR to calculate some particular condition from stored
+   CC_OP/CC_DEP1/CC_DEP2/CC_NDEP.  Returns an expression of type
+   Ity_I32, suitable for narrowing.  Although the return type is
+   Ity_I32, the returned value is either 0 or 1.
+*/
+static IRExpr* mk_armg_calculate_condition ( ARMCondcode cond )
+{
+  /* First arg is "(cond << 4) | condition".  This requires that the
+     ARM_CC_OP_ values all fit in 4 bits.  Hence we are passing a
+     (COND, OP) pair in the lowest 8 bits of the first argument. */
+   vassert(cond >= 0 && cond <= 15);
+   return mk_armg_calculate_condition_dyn( mkU32(cond << 4) );
+}
+
+

 /* Build IR to calculate just the carry flag from stored
    CC_OP/CC_DEP1/CC_DEP2/CC_NDEP.  Returns an expression ::
    Ity_I32. */
 /* Build IR to calculate just the carry flag from stored
    CC_OP/CC_DEP1/CC_DEP2/CC_NDEP.  Returns an expression ::
    Ity_I32. */


@@ -742,6 +1108,97 @@ static IRExpr* mk_armg_calculate_flags_nzcv ( void )
    return call;
 }
 
    return call;
 }
 

+static IRExpr* mk_armg_calculate_flag_qc ( IRExpr* resL, IRExpr* resR, Bool Q )
+{
+   IRExpr** args1;
+   IRExpr** args2;
+   IRExpr *call1, *call2, *res;
+
+   if (Q) {
+      args1 = mkIRExprVec_4 ( binop(Iop_GetElem32x4, resL, mkU8(0)),
+                              binop(Iop_GetElem32x4, resL, mkU8(1)),
+                              binop(Iop_GetElem32x4, resR, mkU8(0)),
+                              binop(Iop_GetElem32x4, resR, mkU8(1)) );
+      args2 = mkIRExprVec_4 ( binop(Iop_GetElem32x4, resL, mkU8(2)),
+                              binop(Iop_GetElem32x4, resL, mkU8(3)),
+                              binop(Iop_GetElem32x4, resR, mkU8(2)),
+                              binop(Iop_GetElem32x4, resR, mkU8(3)) );
+   } else {
+      args1 = mkIRExprVec_4 ( binop(Iop_GetElem32x2, resL, mkU8(0)),
+                              binop(Iop_GetElem32x2, resL, mkU8(1)),
+                              binop(Iop_GetElem32x2, resR, mkU8(0)),
+                              binop(Iop_GetElem32x2, resR, mkU8(1)) );
+   }
+
+#if 1
+   call1 = mkIRExprCCall(
+             Ity_I32,
+             0/*regparm*/, 
+             "armg_calculate_flag_qc", &armg_calculate_flag_qc,
+             args1
+          );
+   if (Q) {
+      call2 = mkIRExprCCall(
+                Ity_I32,
+                0/*regparm*/, 
+                "armg_calculate_flag_qc", &armg_calculate_flag_qc,
+                args2
+             );
+   }
+   if (Q) {
+      res = binop(Iop_Or32, call1, call2);
+   } else {
+      res = call1;
+   }
+#else
+   if (Q) {
+      res = unop(Iop_1Uto32,
+                 binop(Iop_CmpNE32,
+                       binop(Iop_Or32,
+                             binop(Iop_Or32,
+                                   binop(Iop_Xor32,
+                                         args1[0],
+                                         args1[2]),
+                                   binop(Iop_Xor32,
+                                         args1[1],
+                                         args1[3])),
+                             binop(Iop_Or32,
+                                   binop(Iop_Xor32,
+                                         args2[0],
+                                         args2[2]),
+                                   binop(Iop_Xor32,
+                                         args2[1],
+                                         args2[3]))),
+                       mkU32(0)));
+   } else {
+      res = unop(Iop_1Uto32,
+                 binop(Iop_CmpNE32,
+                       binop(Iop_Or32,
+                             binop(Iop_Xor32,
+                                   args1[0],
+                                   args1[2]),
+                             binop(Iop_Xor32,
+                                   args1[1],
+                                   args1[3])),
+                       mkU32(0)));
+   }
+#endif
+   return res;
+}
+
+// FIXME: this is named wrongly .. looks like a sticky set of
+// QC, not a write to it.
+static void setFlag_QC ( IRExpr* resL, IRExpr* resR, Bool Q,
+                         IRTemp condT )
+{
+   putMiscReg32 (OFFB_FPSCR,
+                 binop(Iop_Or32,
+                       IRExpr_Get(OFFB_FPSCR, Ity_I32),
+                       binop(Iop_Shl32,
+                             mk_armg_calculate_flag_qc(resL, resR, Q),
+                             mkU8(27))),
+                 condT);
+}

 
 /* Build IR to conditionally set the flags thunk.  As with putIReg, if
    guard is IRTemp_INVALID then it's unconditional, else it holds a
 
 /* Build IR to conditionally set the flags thunk.  As with putIReg, if
    guard is IRTemp_INVALID then it's unconditional, else it holds a


@@ -825,6 +1282,7 @@ static void setFlags_D1 ( UInt cc_op, IRTemp t_dep1,
 }
 
 
 }
 
 

+/* ARM only */

 /* Generate a side-exit to the next instruction, if the given guard
    expression :: Ity_I32 is 0 (note!  the side exit is taken if the
    condition is false!)  This is used to skip over conditional
 /* Generate a side-exit to the next instruction, if the given guard
    expression :: Ity_I32 is 0 (note!  the side exit is taken if the
    condition is false!)  This is used to skip over conditional


@@ -832,214 +1290,729 @@ static void setFlags_D1 ( UInt cc_op, IRTemp t_dep1,
    because they are too complex or (more likely) they potentially
    generate exceptions.
 */
    because they are too complex or (more likely) they potentially
    generate exceptions.
 */

-static void mk_skip_to_next_if_cond_is_false ( 
+static void mk_skip_over_A32_if_cond_is_false ( 

                IRTemp guardT /* :: Ity_I32, 0 or 1 */
             )
 {
                IRTemp guardT /* :: Ity_I32, 0 or 1 */
             )
 {

+   ASSERT_IS_ARM;

    vassert(guardT != IRTemp_INVALID);
    vassert(guardT != IRTemp_INVALID);

+   vassert(0 == (guest_R15_curr_instr_notENC & 3));

    stmt( IRStmt_Exit(
             unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))),
             Ijk_Boring,
    stmt( IRStmt_Exit(
             unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))),
             Ijk_Boring,

-            IRConst_U32(toUInt(guest_R15_curr_instr + 4))
+            IRConst_U32(toUInt(guest_R15_curr_instr_notENC + 4))

        ));
 }
 
        ));
 }
 

+/* Thumb16 only */
+/* ditto, but jump over a 16-bit thumb insn */
+static void mk_skip_over_T16_if_cond_is_false ( 
+               IRTemp guardT /* :: Ity_I32, 0 or 1 */
+            )
+{
+   ASSERT_IS_THUMB;
+   vassert(guardT != IRTemp_INVALID);
+   vassert(0 == (guest_R15_curr_instr_notENC & 1));
+   stmt( IRStmt_Exit(
+            unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))),
+            Ijk_Boring,
+            IRConst_U32(toUInt((guest_R15_curr_instr_notENC + 2) | 1))
+       ));
+}

 
 

-/*------------------------------------------------------------*/
-/*--- Larger helpers                                       ---*/
-/*------------------------------------------------------------*/

 
 

-/* Generate an expression corresponding to a shifter_operand, bind it
-   to a temporary, and return that via *shop.  If shco is non-NULL,
-   also compute a value for the shifter's carry out (in the LSB of a
-   word), bind it to a temporary, and return that via *shco.
+/* Thumb32 only */
+/* ditto, but jump over a 32-bit thumb insn */
+static void mk_skip_over_T32_if_cond_is_false ( 
+               IRTemp guardT /* :: Ity_I32, 0 or 1 */
+            )
+{
+   ASSERT_IS_THUMB;
+   vassert(guardT != IRTemp_INVALID);
+   vassert(0 == (guest_R15_curr_instr_notENC & 1));
+   stmt( IRStmt_Exit(
+            unop(Iop_Not1, unop(Iop_32to1, mkexpr(guardT))),
+            Ijk_Boring,
+            IRConst_U32(toUInt((guest_R15_curr_instr_notENC + 4) | 1))
+       ));
+}

 
 

-   If for some reason we can't come up with a shifter operand (missing
-   case?  not really a shifter operand?) return False.
-*/
-static Bool mk_shifter_operand ( UInt insn_25, UInt insn_11_0,
-                                 /*OUT*/IRTemp* shop,
-                                 /*OUT*/IRTemp* shco,
-                                 /*OUT*/HChar* buf )
+
+/* Thumb16 and Thumb32 only
+   Generate a SIGILL followed by a restart of the current instruction
+   if the given temp is nonzero. */
+static void gen_SIGILL_T_if_nonzero ( IRTemp t /* :: Ity_I32 */ )

 {
 {

-   UInt insn_4 = (insn_11_0 >> 4) & 1;
-   UInt insn_7 = (insn_11_0 >> 7) & 1;
-   vassert(insn_25 <= 0x1);
-   vassert(insn_11_0 <= 0xFFF);
+   ASSERT_IS_THUMB;
+   vassert(t != IRTemp_INVALID);
+   vassert(0 == (guest_R15_curr_instr_notENC & 1));
+   stmt(
+      IRStmt_Exit(
+         binop(Iop_CmpNE32, mkexpr(t), mkU32(0)),
+         Ijk_NoDecode,
+         IRConst_U32(toUInt(guest_R15_curr_instr_notENC | 1))
+      )
+   );
+}

 
 

-   vassert(shop && *shop == IRTemp_INVALID);
-   *shop = newTemp(Ity_I32);

 
 

-   if (shco) {
-      vassert(*shco == IRTemp_INVALID);
-      *shco = newTemp(Ity_I32);
-   }
+/* Inspect the old_itstate, and generate a SIGILL if it indicates that
+   we are currently in an IT block and are not the last in the block.
+   This also rolls back guest_ITSTATE to its old value before the exit
+   and restores it to its new value afterwards.  This is so that if
+   the exit is taken, we have an up to date version of ITSTATE
+   available.  Without doing that, we have no hope of making precise
+   exceptions work. */
+static void gen_SIGILL_T_if_in_but_NLI_ITBlock (
+               IRTemp old_itstate /* :: Ity_I32 */,
+               IRTemp new_itstate /* :: Ity_I32 */
+            )
+{
+   ASSERT_IS_THUMB;
+   put_ITSTATE(old_itstate); // backout
+   IRTemp guards_for_next3 = newTemp(Ity_I32);
+   assign(guards_for_next3,
+          binop(Iop_Shr32, mkexpr(old_itstate), mkU8(8)));
+   gen_SIGILL_T_if_nonzero(guards_for_next3);
+   put_ITSTATE(new_itstate); //restore
+}

 
 

-   /* 32-bit immediate */

 
 

-   if (insn_25 == 1) {
-      /* immediate: (7:0) rotated right by 2 * (11:8) */
-      UInt imm = (insn_11_0 >> 0) & 0xFF;
-      UInt rot = 2 * ((insn_11_0 >> 8) & 0xF);
-      vassert(rot <= 30);
-      imm = ROR32(imm, rot);
-      if (shco) {
-         if (rot == 0) {
-            assign( *shco, mk_armg_calculate_flag_c() );
-         } else {
-            assign( *shco, mkU32( (imm >> 31) & 1 ) );
-         }
-      }
-      DIS(buf, "#0x%x", imm);
-      assign( *shop, mkU32(imm) );
-      return True;
-   }
+/* Simpler version of the above, which generates a SIGILL if
+   we're anywhere within an IT block. */
+static void gen_SIGILL_T_if_in_ITBlock (
+               IRTemp old_itstate /* :: Ity_I32 */,
+               IRTemp new_itstate /* :: Ity_I32 */
+            )
+{
+   put_ITSTATE(old_itstate); // backout
+   gen_SIGILL_T_if_nonzero(old_itstate);
+   put_ITSTATE(new_itstate); //restore
+}

 
 

-   /* Shift/rotate by immediate */

 
 

-   if (insn_25 == 0 && insn_4 == 0) {
-      /* Rm (3:0) shifted (6:5) by immediate (11:7) */
-      UInt shift_amt = (insn_11_0 >> 7) & 0x1F;
-      UInt rM        = (insn_11_0 >> 0) & 0xF;
-      UInt how       = (insn_11_0 >> 5) & 3;
-      /* how: 00 = Shl, 01 = Shr, 10 = Sar, 11 = Ror */
-      IRTemp rMt = newTemp(Ity_I32);
-      assign(rMt, getIReg(rM));

 
 

-      vassert(shift_amt <= 31);
+/*------------------------------------------------------------*/
+/*--- Larger helpers                                       ---*/
+/*------------------------------------------------------------*/

 
 

-      switch (how) {
+/* Compute both the result and new C flag value for a LSL by an imm5
+   or by a register operand.  May generate reads of the old C value
+   (hence only safe to use before any writes to guest state happen).
+   Are factored out so can be used by both ARM and Thumb.

 
 

-         case 0:
-            if (shift_amt == 0) {
-               if (shco) {
-                  assign( *shco, mk_armg_calculate_flag_c() );
-               }
-               assign( *shop, mkexpr(rMt) );
-               DIS(buf, "r%u", rM);
-            } else {
-               vassert(shift_amt >= 1 && shift_amt <= 31);
-               if (shco) {
-                  assign( *shco,
-                          binop(Iop_And32,
-                                binop(Iop_Shr32, mkexpr(rMt), 
-                                                 mkU8(32 - shift_amt)),
-                                mkU32(1)));
-               }
-               assign( *shop,
-                       binop(Iop_Shl32, mkexpr(rMt), mkU8(shift_amt)) );
-               DIS(buf, "r%u, LSL #%u", rM, shift_amt);
-            }
-            return True;
-            /*NOTREACHED*/
+   Note that in compute_result_and_C_after_{LSL,LSR,ASR}_by{imm5,reg},
+   "res" (the result)  is a.k.a. "shop", shifter operand
+   "newC" (the new C)  is a.k.a. "shco", shifter carry out

 
 

-         case 1:
-            if (shift_amt == 0) {
-               // conceptually a 32-bit shift, however:
-               // shop = 0
-               // shco = Rm[31]
-               if (shco) {
-                  assign( *shco,
-                          binop(Iop_And32,
-                                binop(Iop_Shr32, mkexpr(rMt), mkU8(31)), 
-                                mkU32(1)));
-               }
-               assign( *shop, mkU32(0) );
-               DIS(buf, "r%u, LSR #0(a.k.a. 32)", rM);
-            } else {
-               // shift in range 1..31
-               // shop = Rm >>u shift_amt
-               // shco = Rm[shift_amt - 1]
-               vassert(shift_amt >= 1 && shift_amt <= 31);
-               if (shco) {
-                  assign( *shco,
-                          binop(Iop_And32,
-                                binop(Iop_Shr32, mkexpr(rMt), 
-                                                 mkU8(shift_amt - 1)),
-                                mkU32(1)));
-               }
-               assign( *shop,
-                       binop(Iop_Shr32, mkexpr(rMt), mkU8(shift_amt)) );
-               DIS(buf, "r%u, LSR #%u", rM, shift_amt);
-            }
-            return True;
-            /*NOTREACHED*/
+   The calling convention for res and newC is a bit funny.  They could
+   be passed by value, but instead are passed by ref.
+*/

 
 

-         case 2:
-            if (shift_amt == 0) {
-               // conceptually a 32-bit shift, however:
-               // shop = Rm >>s 31
-               // shco = Rm[31]
-               if (shco) {
-                  assign( *shco,
+static void compute_result_and_C_after_LSL_by_imm5 (
+               /*OUT*/HChar* buf,
+               IRTemp* res,
+               IRTemp* newC,
+               IRTemp rMt, UInt shift_amt, /* operands */
+               UInt rM      /* only for debug printing */
+            )
+{
+   if (shift_amt == 0) {
+      if (newC) {
+         assign( *newC, mk_armg_calculate_flag_c() );
+      }
+      assign( *res, mkexpr(rMt) );
+      DIS(buf, "r%u", rM);
+   } else {
+      vassert(shift_amt >= 1 && shift_amt <= 31);
+      if (newC) {
+         assign( *newC,
+                 binop(Iop_And32,
+                       binop(Iop_Shr32, mkexpr(rMt), 
+                                        mkU8(32 - shift_amt)),
+                       mkU32(1)));
+      }
+      assign( *res,
+              binop(Iop_Shl32, mkexpr(rMt), mkU8(shift_amt)) );
+      DIS(buf, "r%u, LSL #%u", rM, shift_amt);
+   }
+}
+
+
+static void compute_result_and_C_after_LSL_by_reg (
+               /*OUT*/HChar* buf,
+               IRTemp* res,
+               IRTemp* newC,
+               IRTemp rMt, IRTemp rSt,  /* operands */
+               UInt rM,    UInt rS      /* only for debug printing */
+            )
+{
+   // shift left in range 0 .. 255
+   // amt  = rS & 255
+   // res  = amt < 32 ?  Rm << amt  : 0
+   // newC = amt == 0     ? oldC  :
+   //        amt in 1..32 ?  Rm[32-amt]  : 0
+   IRTemp amtT = newTemp(Ity_I32);
+   assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) );
+   if (newC) {
+      /* mux0X(amt == 0,
+               mux0X(amt < 32, 
+                     0,
+                     Rm[(32-amt) & 31])
+               oldC)
+      */
+      /* About the best you can do is pray that iropt is able
+         to nuke most or all of the following junk. */
+      IRTemp oldC = newTemp(Ity_I32);
+      assign(oldC, mk_armg_calculate_flag_c() );
+      assign(
+         *newC,
+         IRExpr_Mux0X(
+            unop(Iop_1Uto8,
+                 binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))),
+            IRExpr_Mux0X(
+               unop(Iop_1Uto8,
+                    binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))),
+               mkU32(0),
+               binop(Iop_Shr32,
+                     mkexpr(rMt),
+                     unop(Iop_32to8,

                           binop(Iop_And32,
                           binop(Iop_And32,

-                                binop(Iop_Shr32, mkexpr(rMt), mkU8(31)), 
-                                mkU32(1)));
-               }
-               assign( *shop, binop(Iop_Sar32, mkexpr(rMt), mkU8(31)) );
-               DIS(buf, "r%u, ASR #0(a.k.a. 32)", rM);
-            } else {
-               // shift in range 1..31
-               // shop = Rm >>s shift_amt
-               // shco = Rm[shift_amt - 1]
-               vassert(shift_amt >= 1 && shift_amt <= 31);
-               if (shco) {
-                  assign( *shco,
+                                binop(Iop_Sub32,
+                                      mkU32(32),
+                                      mkexpr(amtT)),
+                                mkU32(31)
+                          )
+                     )
+               )
+            ),
+            mkexpr(oldC)
+         )
+      );
+   }
+   // (Rm << (Rs & 31))  &  (((Rs & 255) - 32) >>s 31)
+   // Lhs of the & limits the shift to 31 bits, so as to
+   // give known IR semantics.  Rhs of the & is all 1s for
+   // Rs <= 31 and all 0s for Rs >= 32.
+   assign(
+      *res,
+      binop(
+         Iop_And32,
+         binop(Iop_Shl32,
+               mkexpr(rMt),
+               unop(Iop_32to8,
+                    binop(Iop_And32, mkexpr(rSt), mkU32(31)))),
+         binop(Iop_Sar32,
+               binop(Iop_Sub32,
+                     mkexpr(amtT),
+                     mkU32(32)),
+               mkU8(31))));
+    DIS(buf, "r%u, LSL r%u", rM, rS);
+}
+
+
+static void compute_result_and_C_after_LSR_by_imm5 (
+               /*OUT*/HChar* buf,
+               IRTemp* res,
+               IRTemp* newC,
+               IRTemp rMt, UInt shift_amt, /* operands */
+               UInt rM      /* only for debug printing */
+            )
+{
+   if (shift_amt == 0) {
+      // conceptually a 32-bit shift, however:
+      // res  = 0
+      // newC = Rm[31]
+      if (newC) {
+         assign( *newC,
+                 binop(Iop_And32,
+                       binop(Iop_Shr32, mkexpr(rMt), mkU8(31)), 
+                       mkU32(1)));
+      }
+      assign( *res, mkU32(0) );
+      DIS(buf, "r%u, LSR #0(a.k.a. 32)", rM);
+   } else {
+      // shift in range 1..31
+      // res  = Rm >>u shift_amt
+      // newC = Rm[shift_amt - 1]
+      vassert(shift_amt >= 1 && shift_amt <= 31);
+      if (newC) {
+         assign( *newC,
+                 binop(Iop_And32,
+                       binop(Iop_Shr32, mkexpr(rMt), 
+                                        mkU8(shift_amt - 1)),
+                       mkU32(1)));
+      }
+      assign( *res,
+              binop(Iop_Shr32, mkexpr(rMt), mkU8(shift_amt)) );
+      DIS(buf, "r%u, LSR #%u", rM, shift_amt);
+   }
+}
+
+
+static void compute_result_and_C_after_LSR_by_reg (
+               /*OUT*/HChar* buf,
+               IRTemp* res,
+               IRTemp* newC,
+               IRTemp rMt, IRTemp rSt,  /* operands */
+               UInt rM,    UInt rS      /* only for debug printing */
+            )
+{
+   // shift right in range 0 .. 255
+   // amt = rS & 255
+   // res  = amt < 32 ?  Rm >>u amt  : 0
+   // newC = amt == 0     ? oldC  :
+   //        amt in 1..32 ?  Rm[amt-1]  : 0
+   IRTemp amtT = newTemp(Ity_I32);
+   assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) );
+   if (newC) {
+      /* mux0X(amt == 0,
+               mux0X(amt < 32, 
+                     0,
+                     Rm[(amt-1) & 31])
+               oldC)
+      */
+      IRTemp oldC = newTemp(Ity_I32);
+      assign(oldC, mk_armg_calculate_flag_c() );
+      assign(
+         *newC,
+         IRExpr_Mux0X(
+            unop(Iop_1Uto8,
+                 binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))),
+            IRExpr_Mux0X(
+               unop(Iop_1Uto8,
+                    binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))),
+               mkU32(0),
+               binop(Iop_Shr32,
+                     mkexpr(rMt),
+                     unop(Iop_32to8,

                           binop(Iop_And32,
                           binop(Iop_And32,

-                                binop(Iop_Shr32, mkexpr(rMt), 
-                                                 mkU8(shift_amt - 1)),
-                                mkU32(1)));
-               }
-               assign( *shop,
-                       binop(Iop_Sar32, mkexpr(rMt), mkU8(shift_amt)) );
-               DIS(buf, "r%u, ASR #%u", rM, shift_amt);
-            }
-            return True;
-            /*NOTREACHED*/
+                                binop(Iop_Sub32,
+                                      mkexpr(amtT),
+                                      mkU32(1)),
+                                mkU32(31)
+                          )
+                     )
+               )
+            ),
+            mkexpr(oldC)
+         )
+      );
+   }
+   // (Rm >>u (Rs & 31))  &  (((Rs & 255) - 32) >>s 31)
+   // Lhs of the & limits the shift to 31 bits, so as to
+   // give known IR semantics.  Rhs of the & is all 1s for
+   // Rs <= 31 and all 0s for Rs >= 32.
+   assign(
+      *res,
+      binop(
+         Iop_And32,
+         binop(Iop_Shr32,
+               mkexpr(rMt),
+               unop(Iop_32to8,
+                    binop(Iop_And32, mkexpr(rSt), mkU32(31)))),
+         binop(Iop_Sar32,
+               binop(Iop_Sub32,
+                     mkexpr(amtT),
+                     mkU32(32)),
+               mkU8(31))));
+    DIS(buf, "r%u, LSR r%u", rM, rS);
+}

 
 

-         case 3:
-            if (shift_amt == 0) {
-               IRTemp oldcT = newTemp(Ity_I32);
-               // rotate right 1 bit through carry (?)
-               // RRX -- described at ARM ARM A5-17
-               // shop = (oldC << 31) | (Rm >>u 1)
-               // shco = Rm[0]
-               if (shco) {
-                  assign( *shco,
-                           binop(Iop_And32, mkexpr(rMt), mkU32(1)));
-               }
-               assign( oldcT, mk_armg_calculate_flag_c() );
-               assign( *shop, 
-                       binop(Iop_Or32,
-                             binop(Iop_Shl32, mkexpr(oldcT), mkU8(31)),
-                             binop(Iop_Shr32, mkexpr(rMt), mkU8(1))) );
-               DIS(buf, "r%u, RRX", rM);
-            } else {
-               // rotate right in range 1..31
-               // shop = Rm `ror` shift_amt
-               // shco = Rm[shift_amt - 1]
-               vassert(shift_amt >= 1 && shift_amt <= 31);
-               if (shco) {
-                  assign( *shco,
+
+static void compute_result_and_C_after_ASR_by_imm5 (
+               /*OUT*/HChar* buf,
+               IRTemp* res,
+               IRTemp* newC,
+               IRTemp rMt, UInt shift_amt, /* operands */
+               UInt rM      /* only for debug printing */
+            )
+{
+   if (shift_amt == 0) {
+      // conceptually a 32-bit shift, however:
+      // res  = Rm >>s 31
+      // newC = Rm[31]
+      if (newC) {
+         assign( *newC,
+                 binop(Iop_And32,
+                       binop(Iop_Shr32, mkexpr(rMt), mkU8(31)), 
+                       mkU32(1)));
+      }
+      assign( *res, binop(Iop_Sar32, mkexpr(rMt), mkU8(31)) );
+      DIS(buf, "r%u, ASR #0(a.k.a. 32)", rM);
+   } else {
+      // shift in range 1..31
+      // res = Rm >>s shift_amt
+      // newC = Rm[shift_amt - 1]
+      vassert(shift_amt >= 1 && shift_amt <= 31);
+      if (newC) {
+         assign( *newC,
+                 binop(Iop_And32,
+                       binop(Iop_Shr32, mkexpr(rMt), 
+                                        mkU8(shift_amt - 1)),
+                       mkU32(1)));
+      }
+      assign( *res,
+              binop(Iop_Sar32, mkexpr(rMt), mkU8(shift_amt)) );
+      DIS(buf, "r%u, ASR #%u", rM, shift_amt);
+   }
+}
+
+
+static void compute_result_and_C_after_ASR_by_reg (
+               /*OUT*/HChar* buf,
+               IRTemp* res,
+               IRTemp* newC,
+               IRTemp rMt, IRTemp rSt,  /* operands */
+               UInt rM,    UInt rS      /* only for debug printing */
+            )
+{
+   // arithmetic shift right in range 0 .. 255
+   // amt = rS & 255
+   // res  = amt < 32 ?  Rm >>s amt  : Rm >>s 31
+   // newC = amt == 0     ? oldC  :
+   //        amt in 1..32 ?  Rm[amt-1]  : Rm[31]
+   IRTemp amtT = newTemp(Ity_I32);
+   assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) );
+   if (newC) {
+      /* mux0X(amt == 0,
+               mux0X(amt < 32, 
+                     Rm[31],
+                     Rm[(amt-1) & 31])
+               oldC)
+      */
+      IRTemp oldC = newTemp(Ity_I32);
+      assign(oldC, mk_armg_calculate_flag_c() );
+      assign(
+         *newC,
+         IRExpr_Mux0X(
+            unop(Iop_1Uto8,
+                 binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))),
+            IRExpr_Mux0X(
+               unop(Iop_1Uto8,
+                    binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))),
+               binop(Iop_Shr32,
+                     mkexpr(rMt),
+                     mkU8(31)
+               ),
+               binop(Iop_Shr32,
+                     mkexpr(rMt),
+                     unop(Iop_32to8,

                           binop(Iop_And32,
                           binop(Iop_And32,

-                                binop(Iop_Shr32, mkexpr(rMt), 
-                                                 mkU8(shift_amt - 1)),
-                                mkU32(1)));
-               }
-               assign( *shop,
-                       binop(Iop_Or32,
-                             binop(Iop_Shr32, mkexpr(rMt), mkU8(shift_amt)),
-                             binop(Iop_Shl32, mkexpr(rMt),
-                                              mkU8(32-shift_amt))));
-               DIS(buf, "r%u, ROR #%u", rM, shift_amt);
+                                binop(Iop_Sub32,
+                                      mkexpr(amtT),
+                                      mkU32(1)),
+                                mkU32(31)
+                          )
+                     )
+               )
+            ),
+            mkexpr(oldC)
+         )
+      );
+   }
+   // (Rm >>s (amt <u 32 ? amt : 31))
+   assign(
+      *res,
+      binop(
+         Iop_Sar32,
+         mkexpr(rMt),
+         unop(
+            Iop_32to8,
+            IRExpr_Mux0X(
+               unop(
+                 Iop_1Uto8,
+                 binop(Iop_CmpLT32U, mkexpr(amtT), mkU32(32))),
+               mkU32(31),
+               mkexpr(amtT)))));
+    DIS(buf, "r%u, ASR r%u", rM, rS);
+}
+
+
+static void compute_result_and_C_after_ROR_by_reg (
+               /*OUT*/HChar* buf,
+               IRTemp* res,
+               IRTemp* newC,
+               IRTemp rMt, IRTemp rSt,  /* operands */
+               UInt rM,    UInt rS      /* only for debug printing */
+            )
+{
+   // rotate right in range 0 .. 255
+   // amt = rS & 255
+   // shop =  Rm `ror` (amt & 31)
+   // shco =  amt == 0 ? oldC : Rm[(amt-1) & 31]
+   IRTemp amtT = newTemp(Ity_I32);
+   assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) );
+   IRTemp amt5T = newTemp(Ity_I32);
+   assign( amt5T, binop(Iop_And32, mkexpr(rSt), mkU32(31)) );
+   IRTemp oldC = newTemp(Ity_I32);
+   assign(oldC, mk_armg_calculate_flag_c() );
+   if (newC) {
+      assign(
+         *newC,
+         IRExpr_Mux0X(
+            unop(Iop_32to8, mkexpr(amtT)),
+            mkexpr(oldC),
+            binop(Iop_And32,
+                  binop(Iop_Shr32,
+                        mkexpr(rMt), 
+                        unop(Iop_32to8,
+                             binop(Iop_And32,
+                                   binop(Iop_Sub32,
+                                         mkexpr(amtT), 
+                                         mkU32(1)
+                                   ),
+                                   mkU32(31)
+                             )
+                        )
+                  ),
+                  mkU32(1)
+            )
+         )
+      );
+   }
+   assign(
+      *res,
+      IRExpr_Mux0X(
+         unop(Iop_32to8, mkexpr(amt5T)), mkexpr(rMt),
+         binop(Iop_Or32,
+               binop(Iop_Shr32,
+                     mkexpr(rMt), 
+                     unop(Iop_32to8, mkexpr(amt5T))
+               ),
+               binop(Iop_Shl32,
+                     mkexpr(rMt),
+                     unop(Iop_32to8,
+                          binop(Iop_Sub32, mkU32(32), mkexpr(amt5T))
+                     )
+               )
+         )
+      )
+   );
+   DIS(buf, "r%u, ROR r#%u", rM, rS);
+}
+
+
+/* Generate an expression corresponding to the immediate-shift case of
+   a shifter operand.  This is used both for ARM and Thumb2.
+
+   Bind it to a temporary, and return that via *res.  If newC is
+   non-NULL, also compute a value for the shifter's carry out (in the
+   LSB of a word), bind it to a temporary, and return that via *shco.
+
+   Generates GETs from the guest state and is therefore not safe to
+   use once we start doing PUTs to it, for any given instruction.
+
+   'how' is encoded thusly:
+      00b LSL,  01b LSR,  10b ASR,  11b ROR
+   Most but not all ARM and Thumb integer insns use this encoding.
+   Be careful to ensure the right value is passed here.
+*/
+static void compute_result_and_C_after_shift_by_imm5 (
+               /*OUT*/HChar* buf,
+               /*OUT*/IRTemp* res,
+               /*OUT*/IRTemp* newC,
+               IRTemp  rMt,       /* reg to shift */
+               UInt    how,       /* what kind of shift */
+               UInt    shift_amt, /* shift amount (0..31) */
+               UInt    rM         /* only for debug printing */
+            )
+{
+   vassert(shift_amt < 32);
+   vassert(how < 4);
+
+   switch (how) {
+
+      case 0:
+         compute_result_and_C_after_LSL_by_imm5(
+            buf, res, newC, rMt, shift_amt, rM
+         );
+         break;
+
+      case 1:
+         compute_result_and_C_after_LSR_by_imm5(
+            buf, res, newC, rMt, shift_amt, rM
+         );
+         break;
+
+      case 2:
+         compute_result_and_C_after_ASR_by_imm5(
+            buf, res, newC, rMt, shift_amt, rM
+         );
+         break;
+
+      case 3:
+         if (shift_amt == 0) {
+            IRTemp oldcT = newTemp(Ity_I32);
+            // rotate right 1 bit through carry (?)
+            // RRX -- described at ARM ARM A5-17
+            // res  = (oldC << 31) | (Rm >>u 1)
+            // newC = Rm[0]
+            if (newC) {
+               assign( *newC,
+                       binop(Iop_And32, mkexpr(rMt), mkU32(1)));

             }
             }

-            return True;
-            /*NOTREACHED*/
+            assign( oldcT, mk_armg_calculate_flag_c() );
+            assign( *res, 
+                    binop(Iop_Or32,
+                          binop(Iop_Shl32, mkexpr(oldcT), mkU8(31)),
+                          binop(Iop_Shr32, mkexpr(rMt), mkU8(1))) );
+            DIS(buf, "r%u, RRX", rM);
+         } else {
+            // rotate right in range 1..31
+            // res  = Rm `ror` shift_amt
+            // newC = Rm[shift_amt - 1]
+            vassert(shift_amt >= 1 && shift_amt <= 31);
+            if (newC) {
+               assign( *newC,
+                       binop(Iop_And32,
+                             binop(Iop_Shr32, mkexpr(rMt), 
+                                              mkU8(shift_amt - 1)),
+                             mkU32(1)));
+            }
+            assign( *res,
+                    binop(Iop_Or32,
+                          binop(Iop_Shr32, mkexpr(rMt), mkU8(shift_amt)),
+                          binop(Iop_Shl32, mkexpr(rMt),
+                                           mkU8(32-shift_amt))));
+            DIS(buf, "r%u, ROR #%u", rM, shift_amt);
+         }
+         break;

 
 

-         default:
-            /*NOTREACHED*/
-            vassert(0);
+      default:
+         /*NOTREACHED*/
+         vassert(0);
+   }
+}
+
+
+/* Generate an expression corresponding to the register-shift case of
+   a shifter operand.  This is used both for ARM and Thumb2.
+
+   Bind it to a temporary, and return that via *res.  If newC is
+   non-NULL, also compute a value for the shifter's carry out (in the
+   LSB of a word), bind it to a temporary, and return that via *shco.
+
+   Generates GETs from the guest state and is therefore not safe to
+   use once we start doing PUTs to it, for any given instruction.
+
+   'how' is encoded thusly:
+      00b LSL,  01b LSR,  10b ASR,  11b ROR
+   Most but not all ARM and Thumb integer insns use this encoding.
+   Be careful to ensure the right value is passed here.
+*/
+static void compute_result_and_C_after_shift_by_reg (
+               /*OUT*/HChar*  buf,
+               /*OUT*/IRTemp* res,
+               /*OUT*/IRTemp* newC,
+               IRTemp  rMt,       /* reg to shift */
+               UInt    how,       /* what kind of shift */
+               IRTemp  rSt,       /* shift amount */
+               UInt    rM,        /* only for debug printing */
+               UInt    rS         /* only for debug printing */
+            )
+{
+   vassert(how < 4);
+   switch (how) {
+      case 0: { /* LSL */
+         compute_result_and_C_after_LSL_by_reg(
+            buf, res, newC, rMt, rSt, rM, rS
+         );
+         break;
+      }
+      case 1: { /* LSR */
+         compute_result_and_C_after_LSR_by_reg(
+            buf, res, newC, rMt, rSt, rM, rS
+         );
+         break;
+      }
+      case 2: { /* ASR */
+         compute_result_and_C_after_ASR_by_reg(
+            buf, res, newC, rMt, rSt, rM, rS
+         );
+         break;
+      }
+      case 3: { /* ROR */
+         compute_result_and_C_after_ROR_by_reg(
+             buf, res, newC, rMt, rSt, rM, rS
+         );
+         break;
+      }
+      default:
+         /*NOTREACHED*/
+         vassert(0);
+   }
+}
+
+
+/* Generate an expression corresponding to a shifter_operand, bind it
+   to a temporary, and return that via *shop.  If shco is non-NULL,
+   also compute a value for the shifter's carry out (in the LSB of a
+   word), bind it to a temporary, and return that via *shco.
+
+   If for some reason we can't come up with a shifter operand (missing
+   case?  not really a shifter operand?) return False.
+
+   Generates GETs from the guest state and is therefore not safe to
+   use once we start doing PUTs to it, for any given instruction.
+
+   For ARM insns only; not for Thumb.
+*/
+static Bool mk_shifter_operand ( UInt insn_25, UInt insn_11_0,
+                                 /*OUT*/IRTemp* shop,
+                                 /*OUT*/IRTemp* shco,
+                                 /*OUT*/HChar* buf )
+{
+   UInt insn_4 = (insn_11_0 >> 4) & 1;
+   UInt insn_7 = (insn_11_0 >> 7) & 1;
+   vassert(insn_25 <= 0x1);
+   vassert(insn_11_0 <= 0xFFF);
+
+   vassert(shop && *shop == IRTemp_INVALID);
+   *shop = newTemp(Ity_I32);
+
+   if (shco) {
+      vassert(*shco == IRTemp_INVALID);
+      *shco = newTemp(Ity_I32);
+   }
+
+   /* 32-bit immediate */
+
+   if (insn_25 == 1) {
+      /* immediate: (7:0) rotated right by 2 * (11:8) */
+      UInt imm = (insn_11_0 >> 0) & 0xFF;
+      UInt rot = 2 * ((insn_11_0 >> 8) & 0xF);
+      vassert(rot <= 30);
+      imm = ROR32(imm, rot);
+      if (shco) {
+         if (rot == 0) {
+            assign( *shco, mk_armg_calculate_flag_c() );
+         } else {
+            assign( *shco, mkU32( (imm >> 31) & 1 ) );
+         }

       }
       }

+      DIS(buf, "#0x%x", imm);
+      assign( *shop, mkU32(imm) );
+      return True;
+   }
+
+   /* Shift/rotate by immediate */
+
+   if (insn_25 == 0 && insn_4 == 0) {
+      /* Rm (3:0) shifted (6:5) by immediate (11:7) */
+      UInt shift_amt = (insn_11_0 >> 7) & 0x1F;
+      UInt rM        = (insn_11_0 >> 0) & 0xF;
+      UInt how       = (insn_11_0 >> 5) & 3;
+      /* how: 00 = Shl, 01 = Shr, 10 = Sar, 11 = Ror */
+      IRTemp rMt = newTemp(Ity_I32);
+      assign(rMt, getIRegA(rM));
+
+      vassert(shift_amt <= 31);
+
+         compute_result_and_C_after_shift_by_imm5(
+               buf, shop, shco, rMt, how, shift_amt, rM
+         );
+         return True;

    }
 
    /* Shift/rotate by register */
    }
 
    /* Shift/rotate by register */


@@ -1055,259 +2028,13 @@ static Bool mk_shifter_operand ( UInt insn_25, UInt insn_11_0,
       if (insn_7 == 1)
          return False; /* not really a shifter operand */
 
       if (insn_7 == 1)
          return False; /* not really a shifter operand */
 

-      assign(rMt, getIReg(rM));
-      assign(rSt, getIReg(rS));
-
-      switch (how) {
-         case 0: { /* LSL */
-            // shift left in range 0 .. 255
-            // amt = rS & 255
-            // shop = amt < 32 ?  Rm << amt  : 0
-            // shco = amt == 0     ? oldC  :
-            //        amt in 1..32 ?  Rm[32-amt]  : 0
-            IRTemp amtT = newTemp(Ity_I32);
-            assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) );
-            if (shco) {
-               /* mux0X(amt == 0,
-                        mux0X(amt < 32, 
-                              0,
-                              Rm[(32-amt) & 31])
-                        oldC)
-               */
-               /* About the best you can do is pray that iropt is able
-                  to nuke most or all of the following junk. */
-               IRTemp oldC = newTemp(Ity_I32);
-               assign(oldC, mk_armg_calculate_flag_c() );
-               assign(
-                  *shco,
-                  IRExpr_Mux0X(
-                     unop(Iop_1Uto8,
-                          binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))),
-                     IRExpr_Mux0X(
-                        unop(Iop_1Uto8,
-                             binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))),
-                        mkU32(0),
-                        binop(Iop_Shr32,
-                              mkexpr(rMt),
-                              unop(Iop_32to8,
-                                   binop(Iop_And32,
-                                         binop(Iop_Sub32,
-                                               mkU32(32),
-                                               mkexpr(amtT)),
-                                         mkU32(31)
-                                   )
-                              )
-                        )
-                     ),
-                     mkexpr(oldC)
-                  )
-               );
-            }
-            // (Rm << (Rs & 31))  &  (((Rs & 255) - 32) >>s 31)
-            // Lhs of the & limits the shift to 31 bits, so as to
-            // give known IR semantics.  Rhs of the & is all 1s for
-            // Rs <= 31 and all 0s for Rs >= 32.
-            assign(
-               *shop,
-               binop(
-                  Iop_And32,
-                  binop(Iop_Shl32,
-                        mkexpr(rMt),
-                        unop(Iop_32to8,
-                             binop(Iop_And32, mkexpr(rSt), mkU32(31)))),
-                  binop(Iop_Sar32,
-                        binop(Iop_Sub32,
-                              mkexpr(amtT),
-                              mkU32(32)),
-                        mkU8(31))));
-             DIS(buf, "r%u, LSL r%u", rM, rS);
-             return True;
-         }
-         case 1: { /* LSR */
-            // shift right in range 0 .. 255
-            // amt = rS & 255
-            // shop = amt < 32 ?  Rm >>u amt  : 0
-            // shco = amt == 0     ? oldC  :
-            //        amt in 1..32 ?  Rm[amt-1]  : 0
-            IRTemp amtT = newTemp(Ity_I32);
-            assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) );
-            if (shco) {
-               /* mux0X(amt == 0,
-                        mux0X(amt < 32, 
-                              0,
-                              Rm[(amt-1) & 31])
-                        oldC)
-               */
-               IRTemp oldC = newTemp(Ity_I32);
-               assign(oldC, mk_armg_calculate_flag_c() );
-               assign(
-                  *shco,
-                  IRExpr_Mux0X(
-                     unop(Iop_1Uto8,
-                          binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))),
-                     IRExpr_Mux0X(
-                        unop(Iop_1Uto8,
-                             binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))),
-                        mkU32(0),
-                        binop(Iop_Shr32,
-                              mkexpr(rMt),
-                              unop(Iop_32to8,
-                                   binop(Iop_And32,
-                                         binop(Iop_Sub32,
-                                               mkexpr(amtT),
-                                               mkU32(1)),
-                                         mkU32(31)
-                                   )
-                              )
-                        )
-                     ),
-                     mkexpr(oldC)
-                  )
-               );
-            }
-            // (Rm >>u (Rs & 31))  &  (((Rs & 255) - 32) >>s 31)
-            // Lhs of the & limits the shift to 31 bits, so as to
-            // give known IR semantics.  Rhs of the & is all 1s for
-            // Rs <= 31 and all 0s for Rs >= 32.
-            assign(
-               *shop,
-               binop(
-                  Iop_And32,
-                  binop(Iop_Shr32,
-                        mkexpr(rMt),
-                        unop(Iop_32to8,
-                             binop(Iop_And32, mkexpr(rSt), mkU32(31)))),
-                  binop(Iop_Sar32,
-                        binop(Iop_Sub32,
-                              mkexpr(amtT),
-                              mkU32(32)),
-                        mkU8(31))));
-             DIS(buf, "r%u, LSR r%u", rM, rS);
-             return True;
-         }
-         case 2: { /* ASR */
-            // arithmetic shift right in range 0 .. 255
-            // amt = rS & 255
-            // shop = amt < 32 ?  Rm >>s amt  : Rm >>s 31
-            // shco = amt == 0     ? oldC  :
-            //        amt in 1..32 ?  Rm[amt-1]  : Rm[31]
-            IRTemp amtT = newTemp(Ity_I32);
-            assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) );
-            if (shco) {
-               /* mux0X(amt == 0,
-                        mux0X(amt < 32, 
-                              Rm[31],
-                              Rm[(amt-1) & 31])
-                        oldC)
-               */
-               IRTemp oldC = newTemp(Ity_I32);
-               assign(oldC, mk_armg_calculate_flag_c() );
-               assign(
-                  *shco,
-                  IRExpr_Mux0X(
-                     unop(Iop_1Uto8,
-                          binop(Iop_CmpEQ32, mkexpr(amtT), mkU32(0))),
-                     IRExpr_Mux0X(
-                        unop(Iop_1Uto8,
-                             binop(Iop_CmpLE32U, mkexpr(amtT), mkU32(32))),
-                        binop(Iop_Shr32,
-                              mkexpr(rMt),
-                              mkU8(31)
-                        ),
-                        binop(Iop_Shr32,
-                              mkexpr(rMt),
-                              unop(Iop_32to8,
-                                   binop(Iop_And32,
-                                         binop(Iop_Sub32,
-                                               mkexpr(amtT),
-                                               mkU32(1)),
-                                         mkU32(31)
-                                   )
-                              )
-                        )
-                     ),
-                     mkexpr(oldC)
-                  )
-               );
-            }
-            // (Rm >>s (amt <u 32 ? amt : 31))
-            assign(
-               *shop,
-               binop(
-                  Iop_Sar32,
-                  mkexpr(rMt),
-                  unop(
-                     Iop_32to8,
-                     IRExpr_Mux0X(
-                        unop(
-                          Iop_1Uto8,
-                          binop(Iop_CmpLT32U, mkexpr(amtT), mkU32(32))),
-                        mkU32(31),
-                        mkexpr(amtT)))));
-             DIS(buf, "r%u, ASR r%u", rM, rS);
-             return True;
-         }
-         case 3: { /* ROR */
-            // rotate right in range 0 .. 255
-            // amt = rS & 255
-            // shop =  Rm `ror` (amt & 31)
-            // shco =  amt == 0 ? oldC : Rm[(amt-1) & 31]
-            IRTemp amtT = newTemp(Ity_I32);
-            assign( amtT, binop(Iop_And32, mkexpr(rSt), mkU32(255)) );
-            IRTemp amt5T = newTemp(Ity_I32);
-            assign( amt5T, binop(Iop_And32, mkexpr(rSt), mkU32(31)) );
-            IRTemp oldC = newTemp(Ity_I32);
-            assign(oldC, mk_armg_calculate_flag_c() );
-            if (shco) {
-               assign(
-                  *shco,
-                  IRExpr_Mux0X(
-                     unop(Iop_32to8, mkexpr(amtT)),
-                     mkexpr(oldC),
-                     binop(Iop_And32,
-                           binop(Iop_Shr32,
-                                 mkexpr(rMt), 
-                                 unop(Iop_32to8,
-                                      binop(Iop_And32,
-                                            binop(Iop_Sub32,
-                                                  mkexpr(amtT), 
-                                                  mkU32(1)
-                                            ),
-                                            mkU32(31)
-                                      )
-                                 )
-                           ),
-                           mkU32(1)
-                     )
-                  )
-               );
-            }
-            assign(
-               *shop,
-               IRExpr_Mux0X(
-                  unop(Iop_32to8, mkexpr(amt5T)), mkexpr(rMt),
-                  binop(Iop_Or32,
-                        binop(Iop_Shr32,
-                              mkexpr(rMt), 
-                              unop(Iop_32to8, mkexpr(amt5T))
-                        ),
-                        binop(Iop_Shl32,
-                              mkexpr(rMt),
-                              unop(Iop_32to8,
-                                   binop(Iop_Sub32, mkU32(32), mkexpr(amt5T))
-                              )
-                        )
-                  )
-               )
-            );
-            DIS(buf, "r%u, ROR r#%u", rM, rS);
-            return True;
-            /*NOTREACHED*/
-         }
-         default:
-            /*NOTREACHED*/
-            vassert(0);
-      }
+      assign(rMt, getIRegA(rM));
+      assign(rSt, getIRegA(rS));
+
+      compute_result_and_C_after_shift_by_reg(
+         buf, shop, shco, rMt, how, rSt, rM, rS
+      );
+      return True;

    }
 
    vex_printf("mk_shifter_operand(0x%x,0x%x)\n", insn_25, insn_11_0 );
    }
 
    vex_printf("mk_shifter_operand(0x%x,0x%x)\n", insn_25, insn_11_0 );


@@ -1315,6 +2042,7 @@ static Bool mk_shifter_operand ( UInt insn_25, UInt insn_11_0,
 }
 
 
 }
 
 

+/* ARM only */

 static 
 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12,
                                     /*OUT*/HChar* buf )
 static 
 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12,
                                     /*OUT*/HChar* buf )


@@ -1326,12 +2054,13 @@ IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12,
    DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12);
    return
       binop( (bU == 1 ? Iop_Add32 : Iop_Sub32),
    DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12);
    return
       binop( (bU == 1 ? Iop_Add32 : Iop_Sub32),

-             getIReg(rN),
+             getIRegA(rN),

              mkU32(imm12) );
 }
 
 
              mkU32(imm12) );
 }
 
 

-/* NB: This is "DecodeImmShift" in newer versions of the the ARM ARM.
+/* ARM only.
+   NB: This is "DecodeImmShift" in newer versions of the the ARM ARM.

 */
 static
 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
 */
 static
 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,


@@ -1348,7 +2077,7 @@ IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
    switch (sh2) {
       case 0: /* LSL */
          /* imm5 can be in the range 0 .. 31 inclusive. */
    switch (sh2) {
       case 0: /* LSL */
          /* imm5 can be in the range 0 .. 31 inclusive. */

-         index = binop(Iop_Shl32, getIReg(rM), mkU8(imm5));
+         index = binop(Iop_Shl32, getIRegA(rM), mkU8(imm5));

          DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); 
          break;
       case 1: /* LSR */
          DIS(buf, "[r%u, %c r%u LSL #%u]", rN, opChar, rM, imm5); 
          break;
       case 1: /* LSR */


@@ -1356,7 +2085,7 @@ IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
             index = mkU32(0);
             vassert(0); // ATC
          } else {
             index = mkU32(0);
             vassert(0); // ATC
          } else {

-            index = binop(Iop_Shr32, getIReg(rM), mkU8(imm5));
+            index = binop(Iop_Shr32, getIRegA(rM), mkU8(imm5));

          }
          DIS(buf, "[r%u, %cr%u, LSR #%u]",
                   rN, opChar, rM, imm5 == 0 ? 32 : imm5); 
          }
          DIS(buf, "[r%u, %cr%u, LSR #%u]",
                   rN, opChar, rM, imm5 == 0 ? 32 : imm5); 


@@ -1365,10 +2094,10 @@ IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
          /* Doesn't this just mean that the behaviour with imm5 == 0
             is the same as if it had been 31 ? */
          if (imm5 == 0) {
          /* Doesn't this just mean that the behaviour with imm5 == 0
             is the same as if it had been 31 ? */
          if (imm5 == 0) {

-            index = binop(Iop_Sar32, getIReg(rM), mkU8(31));
+            index = binop(Iop_Sar32, getIRegA(rM), mkU8(31));

             vassert(0); // ATC
          } else {
             vassert(0); // ATC
          } else {

-            index = binop(Iop_Sar32, getIReg(rM), mkU8(imm5));
+            index = binop(Iop_Sar32, getIRegA(rM), mkU8(imm5));

          }
          DIS(buf, "[r%u, %cr%u, ASR #%u]",
                   rN, opChar, rM, imm5 == 0 ? 32 : imm5); 
          }
          DIS(buf, "[r%u, %cr%u, ASR #%u]",
                   rN, opChar, rM, imm5 == 0 ? 32 : imm5); 


@@ -1377,7 +2106,7 @@ IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
          if (imm5 == 0) {
             IRTemp rmT    = newTemp(Ity_I32);
             IRTemp cflagT = newTemp(Ity_I32);
          if (imm5 == 0) {
             IRTemp rmT    = newTemp(Ity_I32);
             IRTemp cflagT = newTemp(Ity_I32);

-            assign(rmT, getIReg(rM));
+            assign(rmT, getIRegA(rM));

             assign(cflagT, mk_armg_calculate_flag_c());
             index = binop(Iop_Or32, 
                           binop(Iop_Shl32, mkexpr(cflagT), mkU8(31)),
             assign(cflagT, mk_armg_calculate_flag_c());
             index = binop(Iop_Or32, 
                           binop(Iop_Shl32, mkexpr(cflagT), mkU8(31)),


@@ -1385,7 +2114,7 @@ IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
             DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM);
          } else {
             IRTemp rmT = newTemp(Ity_I32);
             DIS(buf, "[r%u, %cr%u, RRX]", rN, opChar, rM);
          } else {
             IRTemp rmT = newTemp(Ity_I32);

-            assign(rmT, getIReg(rM));
+            assign(rmT, getIRegA(rM));

             vassert(imm5 >= 1 && imm5 <= 31);
             index = binop(Iop_Or32, 
                           binop(Iop_Shl32, mkexpr(rmT), mkU8(32-imm5)),
             vassert(imm5 >= 1 && imm5 <= 31);
             index = binop(Iop_Or32, 
                           binop(Iop_Shl32, mkexpr(rmT), mkU8(32-imm5)),


@@ -1398,10 +2127,11 @@ IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
    }
    vassert(index);
    return binop(bU == 1 ? Iop_Add32 : Iop_Sub32,
    }
    vassert(index);
    return binop(bU == 1 ? Iop_Add32 : Iop_Sub32,

-                getIReg(rN), index);
+                getIRegA(rN), index);

 }
 
 
 }
 
 

+/* ARM only */

 static 
 IRExpr* mk_EA_reg_plusminus_imm8 ( UInt rN, UInt bU, UInt imm8,
                                    /*OUT*/HChar* buf )
 static 
 IRExpr* mk_EA_reg_plusminus_imm8 ( UInt rN, UInt bU, UInt imm8,
                                    /*OUT*/HChar* buf )


@@ -1413,11 +2143,12 @@ IRExpr* mk_EA_reg_plusminus_imm8 ( UInt rN, UInt bU, UInt imm8,
    DIS(buf, "[r%u, #%c%u]", rN, opChar, imm8);
    return
       binop( (bU == 1 ? Iop_Add32 : Iop_Sub32),
    DIS(buf, "[r%u, #%c%u]", rN, opChar, imm8);
    return
       binop( (bU == 1 ? Iop_Add32 : Iop_Sub32),

-             getIReg(rN),
+             getIRegA(rN),

              mkU32(imm8) );
 }
 
 
              mkU32(imm8) );
 }
 
 

+/* ARM only */

 static
 IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM,
                                   /*OUT*/HChar* buf )
 static
 IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM,
                                   /*OUT*/HChar* buf )


@@ -1426,10 +2157,10 @@ IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM,
    vassert(bU < 2);
    vassert(rM < 16);
    UChar   opChar = bU == 1 ? '+' : '-';
    vassert(bU < 2);
    vassert(rM < 16);
    UChar   opChar = bU == 1 ? '+' : '-';

-   IRExpr* index  = getIReg(rM);
+   IRExpr* index  = getIRegA(rM);

    DIS(buf, "[r%u, %c r%u]", rN, opChar, rM); 
    return binop(bU == 1 ? Iop_Add32 : Iop_Sub32,
    DIS(buf, "[r%u, %c r%u]", rN, opChar, rM); 
    return binop(bU == 1 ? Iop_Add32 : Iop_Sub32,

-                getIReg(rN), index);
+                getIRegA(rN), index);

 }
 
 
 }
 
 


@@ -1508,523 +2239,7790 @@ IRTemp mk_convert_IRCmpF64Result_to_NZCV ( IRTemp irRes )
 }
 
 
 }
 
 

-/*------------------------------------------------------------*/
-/*--- Instructions in NV (never) space                     ---*/
-/*------------------------------------------------------------*/
+/* Thumb32 only.  This is "ThumbExpandImm" in the ARM ARM.  If
+   updatesC is non-NULL, a boolean is written to it indicating whether
+   or not the C flag is updated, as per ARM ARM "ThumbExpandImm_C".
+*/
+static UInt thumbExpandImm ( Bool* updatesC,
+                             UInt imm1, UInt imm3, UInt imm8 )
+{
+   vassert(imm1 < (1<<1));
+   vassert(imm3 < (1<<3));
+   vassert(imm8 < (1<<8));
+   UInt i_imm3_a = (imm1 << 4) | (imm3 << 1) | ((imm8 >> 7) & 1);
+   UInt abcdefgh = imm8;
+   UInt lbcdefgh = imm8 | 0x80;
+   if (updatesC) {
+      *updatesC = i_imm3_a >= 8;
+   }
+   switch (i_imm3_a) {
+      case 0: case 1:
+         return abcdefgh;
+      case 2: case 3:
+         return (abcdefgh << 16) | abcdefgh;
+      case 4: case 5:
+         return (abcdefgh << 24) | (abcdefgh << 8);
+      case 6: case 7:
+         return (abcdefgh << 24) | (abcdefgh << 16)
+                | (abcdefgh << 8) | abcdefgh;
+      case 8 ... 31:
+         return lbcdefgh << (32 - i_imm3_a);
+      default:
+         break;
+   }
+   /*NOTREACHED*/vassert(0);
+}

 
 

-static Bool decode_NV_instruction ( UInt insn )
+
+/* Version of thumbExpandImm where we simply feed it the
+   instruction halfwords (the lowest addressed one is I0). */
+static UInt thumbExpandImm_from_I0_I1 ( Bool* updatesC,
+                                        UShort i0s, UShort i1s )

 {
 {

-#  define INSN(_bMax,_bMin)  SLICE_UInt(insn, (_bMax), (_bMin))
-#  define INSN_COND          SLICE_UInt(insn, 31, 28)
+   UInt i0    = (UInt)i0s;
+   UInt i1    = (UInt)i1s;
+   UInt imm1  = SLICE_UInt(i0,10,10);
+   UInt imm3  = SLICE_UInt(i1,14,12);
+   UInt imm8  = SLICE_UInt(i1,7,0);
+   return thumbExpandImm(updatesC, imm1, imm3, imm8);
+}

 
 

-   HChar dis_buf[128];

 
 

-   // Should only be called for NV instructions
-   vassert(BITS4(1,1,1,1) == INSN_COND);
+/* Thumb16 only.  Given the firstcond and mask fields from an IT
+   instruction, compute the 32-bit ITSTATE value implied, as described
+   in libvex_guest_arm.h.  This is not the ARM ARM representation.
+   Also produce the t/e chars for the 2nd, 3rd, 4th insns, for
+   disassembly printing.  Returns False if firstcond or mask
+   denote something invalid.

 
 

-   /* ------------------------ pld ------------------------ */
-   if (BITS8(0,1,0,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
-       && BITS4(1,1,1,1) == INSN(15,12)) {
-      UInt rN    = INSN(19,16);
-      UInt imm12 = INSN(11,0);
-      UInt bU    = INSN(23,23);
-      DIP("pld [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12);
+   The number and conditions for the instructions to be
+   conditionalised depend on firstcond and mask:
+
+   mask      cond 1    cond 2      cond 3      cond 4
+
+   1000      fc[3:0]
+   x100      fc[3:0]   fc[3:1]:x
+   xy10      fc[3:0]   fc[3:1]:x   fc[3:1]:y
+   xyz1      fc[3:0]   fc[3:1]:x   fc[3:1]:y   fc[3:1]:z
+
+   The condition fields are assembled in *itstate backwards (cond 4 at
+   the top, cond 1 at the bottom).  Conditions are << 4'd and then
+   ^0xE'd, and those fields that correspond to instructions in the IT
+   block are tagged with a 1 bit.
+*/
+static Bool compute_ITSTATE ( /*OUT*/UInt*  itstate,
+                              /*OUT*/UChar* ch1,
+                              /*OUT*/UChar* ch2,
+                              /*OUT*/UChar* ch3,
+                              UInt firstcond, UInt mask )
+{
+   vassert(firstcond <= 0xF);
+   vassert(mask <= 0xF);
+   *itstate = 0;
+   *ch1 = *ch2 = *ch3 = '.';
+   if (mask == 0)
+      return False; /* the logic below actually ensures this anyway,
+                       but clearer to make it explicit. */
+   if (firstcond == 0xF)
+      return False; /* NV is not allowed */
+   if (firstcond == 0xE && popcount32(mask) != 1) 
+      return False; /* if firstcond is AL then all the rest must be too */
+
+   UInt m3 = (mask >> 3) & 1;
+   UInt m2 = (mask >> 2) & 1;
+   UInt m1 = (mask >> 1) & 1;
+   UInt m0 = (mask >> 0) & 1;
+
+   UInt fc = (firstcond << 4) | 1/*in-IT-block*/;
+   UInt ni = (0xE/*AL*/ << 4) | 0/*not-in-IT-block*/;
+
+   if (m3 == 1 && (m2|m1|m0) == 0) {
+      *itstate = (ni << 24) | (ni << 16) | (ni << 8) | fc;
+      *itstate ^= 0xE0E0E0E0;

       return True;
    }
 
       return True;
    }
 

-   if (BITS8(0,1,1,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
-       && BITS4(1,1,1,1) == INSN(15,12)
-       && 0 == INSN(4,4)) {
-      UInt rN   = INSN(19,16);
-      UInt rM   = INSN(3,0);
-      UInt imm5 = INSN(11,7);
-      UInt sh2  = INSN(6,5);
-      UInt bU   = INSN(23,23);
-      if (rM != 15) {
-         IRExpr* eaE = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
-                                                       sh2, imm5, dis_buf);
-         IRTemp eaT = newTemp(Ity_I32);
-         /* Bind eaE to a temp merely for debugging-vex purposes, so we
-            can check it's a plausible decoding.  It will get removed
-            by iropt a little later on. */
-         vassert(eaE);
-         assign(eaT, eaE);
-         DIP("pld %s\n", dis_buf);
-         return True;
-      }
-      /* fall through */
+   if (m2 == 1 && (m1|m0) == 0) {
+      *itstate = (ni << 24) | (ni << 16) | (setbit32(fc, 4, m3) << 8) | fc;
+      *itstate ^= 0xE0E0E0E0;
+      *ch1 = m3 == (firstcond & 1) ? 't' : 'e';
+      return True;

    }
 
    }
 

-   /* ------------------- v7 barrier insns ------------------- */
-   switch (insn) {
-      case 0xF57FF06F: /* ISB */
-         stmt( IRStmt_MBE(Imbe_Fence) );
-         DIP("ISB\n");
-         return True;
-      case 0xF57FF04F: /* DSB */
-         stmt( IRStmt_MBE(Imbe_Fence) );
-         DIP("DSB\n");
-         return True;
-      case 0xF57FF05F: /* DMB */
-         stmt( IRStmt_MBE(Imbe_Fence) );
-         DIP("DMB\n");
-         return True;
-      default:
-         break;
+   if (m1 == 1 && m0 == 0) {
+      *itstate = (ni << 24)
+                 | (setbit32(fc, 4, m2) << 16)
+                 | (setbit32(fc, 4, m3) << 8) | fc;
+      *itstate ^= 0xE0E0E0E0;
+      *ch1 = m3 == (firstcond & 1) ? 't' : 'e';
+      *ch2 = m2 == (firstcond & 1) ? 't' : 'e';
+      return True;

    }
 
    }
 

-   return False;
+   if (m0 == 1) {
+      *itstate = (setbit32(fc, 4, m1) << 24)
+                 | (setbit32(fc, 4, m2) << 16)
+                 | (setbit32(fc, 4, m3) << 8) | fc;
+      *itstate ^= 0xE0E0E0E0;
+      *ch1 = m3 == (firstcond & 1) ? 't' : 'e';
+      *ch2 = m2 == (firstcond & 1) ? 't' : 'e';
+      *ch3 = m1 == (firstcond & 1) ? 't' : 'e';
+      return True;
+   }

 
 

-#  undef INSN_COND
-#  undef INSN
+   return False;

 }
 
 }
 

+/*------------------------------------------------------------*/
+/*--- Advanced SIMD (NEON) instructions                    ---*/
+/*------------------------------------------------------------*/

 
 /*------------------------------------------------------------*/
 
 /*------------------------------------------------------------*/

-/*--- Disassemble a single instruction                     ---*/
+/*--- NEON data processing                                 ---*/

 /*------------------------------------------------------------*/
 
 /*------------------------------------------------------------*/
 

-/* Disassemble a single instruction into IR.  The instruction is
-   located in host memory at guest_instr, and has guest IP of
-   guest_R15_curr_instr, which will have been set before the call
-   here. */
+/* For all NEON DP ops, we use the normal scheme to handle conditional
+   writes to registers -- pass in condT and hand that on to the
+   put*Reg functions.  In ARM mode condT is always IRTemp_INVALID
+   since NEON is unconditional for ARM.  In Thumb mode condT is
+   derived from the ITSTATE shift register in the normal way. */

 
 

-static   
-DisResult disInstr_ARM_WRK (
-             Bool         put_IP,
-             Bool         (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
-             Bool         resteerCisOk,
-             void*        callback_opaque,
-             UChar*       guest_instr,
-             VexArchInfo* archinfo,
-             VexAbiInfo*  abiinfo
-          )
+static
+UInt get_neon_d_regno(UInt theInstr)

 {
 {

-   // A macro to fish bits out of 'insn'.
-#  define INSN(_bMax,_bMin)  SLICE_UInt(insn, (_bMax), (_bMin))
-#  define INSN_COND          SLICE_UInt(insn, 31, 28)
-
-   DisResult dres;
-   UInt      insn;
-   //Bool      allow_VFP = False;
-   //UInt      hwcaps = archinfo->hwcaps;
-   IRTemp    condT; /* :: Ity_I32 */
-   UInt      summary;
-   HChar     dis_buf[128];  // big enough to hold LDMIA etc text
-
-   /* What insn variants are we supporting today? */
-   //allow_VFP  = (0 != (hwcaps & VEX_HWCAPS_ARM_VFP));
-   // etc etc
-
-   /* Set result defaults. */
-   dres.whatNext   = Dis_Continue;
-   dres.len        = 4;
-   dres.continueAt = 0;
-
-   /* Set default actions for post-insn handling of writes to r15, if
-      required. */
-   r15written = False;
-   r15guard   = IRTemp_INVALID; /* unconditional */
-   r15kind    = Ijk_Boring;
-
-   /* At least this is simple on ARM: insns are all 4 bytes long, and
-      4-aligned.  So just fish the whole thing out of memory right now
-      and have done. */
-   insn = getUIntLittleEndianly( guest_instr );
-
-   if (0) vex_printf("insn: 0x%x\n", insn);
-
-   DIP("\t0x%x:  ", (UInt)guest_R15_curr_instr);
-
-   /* We may be asked to update the guest R15 before going further. */
-   if (put_IP) {
-      vassert(0 == (guest_R15_curr_instr & 3));
-      llPutIReg( 15, mkU32(guest_R15_curr_instr) );
+   UInt x = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF);
+   if (theInstr & 0x40) {
+      if (x & 1) {
+         x = x + 0x100;
+      } else {
+         x = x >> 1;
+      }

    }
    }

+   return x;
+}

 
 

-   /* ----------------------------------------------------------- */
-
-   /* Spot "Special" instructions (see comment at top of file). */
-   {
-      UChar* code = (UChar*)guest_instr;
-      /* Spot the 16-byte preamble: 
-
-         e1a0c1ec  mov r12, r12, ROR #3
-         e1a0c6ec  mov r12, r12, ROR #13
-         e1a0ceec  mov r12, r12, ROR #29
-         e1a0c9ec  mov r12, r12, ROR #19
-      */
-      UInt word1 = 0xE1A0C1EC;
-      UInt word2 = 0xE1A0C6EC;
-      UInt word3 = 0xE1A0CEEC;
-      UInt word4 = 0xE1A0C9EC;
-      if (getUIntLittleEndianly(code+ 0) == word1 &&
-          getUIntLittleEndianly(code+ 4) == word2 &&
-          getUIntLittleEndianly(code+ 8) == word3 &&
-          getUIntLittleEndianly(code+12) == word4) {
-         /* Got a "Special" instruction preamble.  Which one is it? */
-         if (getUIntLittleEndianly(code+16) == 0xE18AA00A
-                                               /* orr r10,r10,r10 */) {
-            /* R3 = client_request ( R4 ) */
-            DIP("r3 = client_request ( %%r4 )\n");
-            irsb->next     = mkU32( guest_R15_curr_instr + 20 );
-            irsb->jumpkind = Ijk_ClientReq;
-            dres.whatNext  = Dis_StopHere;
-            goto decode_success;
-         }
-         else
-         if (getUIntLittleEndianly(code+16) == 0xE18BB00B
-                                               /* orr r11,r11,r11 */) {
-            /* R3 = guest_NRADDR */
-            DIP("r3 = guest_NRADDR\n");
-            dres.len = 20;
-            llPutIReg(3, IRExpr_Get( OFFB_NRADDR, Ity_I32 ));
-            goto decode_success;
-         }
-         else
-         if (getUIntLittleEndianly(code+16) == 0xE18CC00C
-                                               /* orr r12,r12,r12 */) {
-            /*  branch-and-link-to-noredir R4 */
-            DIP("branch-and-link-to-noredir r4\n");
-            llPutIReg(14, mkU32( guest_R15_curr_instr + 20) );
-            irsb->next     = llGetIReg(4);
-            irsb->jumpkind = Ijk_NoRedir;
-            dres.whatNext  = Dis_StopHere;
-            goto decode_success;
-         }
-         /* We don't know what it is.  Set opc1/opc2 so decode_failure
-            can print the insn following the Special-insn preamble. */
-         insn = getUIntLittleEndianly(code+16);
-         goto decode_failure;
-         /*NOTREACHED*/
+static
+UInt get_neon_n_regno(UInt theInstr)
+{
+   UInt x = ((theInstr >> 3) & 0x10) | ((theInstr >> 16) & 0xF);
+   if (theInstr & 0x40) {
+      if (x & 1) {
+         x = x + 0x100;
+      } else {
+         x = x >> 1;

       }
       }

-

    }
    }

+   return x;
+}

 
 

-   /* ----------------------------------------------------------- */
-
-   /* Main instruction decoder starts here. */
-
-   /* Deal with the condition.  Strategy is to merely generate a
-      condition expression at this point (or NULL, meaning
-      unconditional).  We leave it to lower-level instruction decoders
-      to decide whether they can generate straight-line code, or
-      whether they must generate a side exit before the instruction.
-      condT :: Ity_I32 and is always either zero or one. */
-   condT = IRTemp_INVALID;
-   switch ( (ARMCondcode)INSN_COND ) {
-      case ARMCondNV: {
-         // Illegal instruction prior to v5 (see ARM ARM A3-5), but
-         // some cases are acceptable
-         Bool ok = decode_NV_instruction(insn);
-         if (ok)
-            goto decode_success;
-         else
-         goto decode_failure;
+static
+UInt get_neon_m_regno(UInt theInstr)
+{
+   UInt x = ((theInstr >> 1) & 0x10) | (theInstr & 0xF);
+   if (theInstr & 0x40) {
+      if (x & 1) {
+         x = x + 0x100;
+      } else {
+         x = x >> 1;

       }
       }

-      case ARMCondAL: // Always executed
-         break;
-      case ARMCondEQ: case ARMCondNE: case ARMCondHS: case ARMCondLO:
-      case ARMCondMI: case ARMCondPL: case ARMCondVS: case ARMCondVC:
-      case ARMCondHI: case ARMCondLS: case ARMCondGE: case ARMCondLT:
-      case ARMCondGT: case ARMCondLE:
-         condT = newTemp(Ity_I32);
-         assign( condT, mk_armg_calculate_condition( INSN_COND ));
-         break;

    }
    }

+   return x;
+}

 
 

-   /* ----------------------------------------------------------- */
-   /* -- ARMv5 integer instructions                            -- */
-   /* ----------------------------------------------------------- */
+static
+Bool dis_neon_vext ( UInt theInstr, IRTemp condT )
+{
+   UInt dreg = get_neon_d_regno(theInstr);
+   UInt mreg = get_neon_m_regno(theInstr);
+   UInt nreg = get_neon_n_regno(theInstr);
+   UInt imm4 = (theInstr >> 8) & 0xf;
+   UInt Q = (theInstr >> 6) & 1;
+   HChar reg_t = Q ? 'q' : 'd';
+
+   if (Q) {
+      putQReg(dreg, triop(Iop_ExtractV128, getQReg(nreg),
+               getQReg(mreg), mkU8(imm4)), condT);
+   } else {
+      putDRegI64(dreg, triop(Iop_Extract64, getDRegI64(nreg),
+                 getDRegI64(mreg), mkU8(imm4)), condT);
+   }
+   DIP("vext.8 %c%d, %c%d, %c%d, #%d\n", reg_t, dreg, reg_t, nreg,
+                                         reg_t, mreg, imm4);
+   return True;
+}

 
 

-   /* ---------------- Data processing ops ------------------- */
+/* VTBL, VTBX */
+static
+Bool dis_neon_vtb ( UInt theInstr, IRTemp condT )
+{
+   UInt op = (theInstr >> 6) & 1;
+   UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6));
+   UInt nreg = get_neon_n_regno(theInstr & ~(1 << 6));
+   UInt mreg = get_neon_m_regno(theInstr & ~(1 << 6));
+   UInt len = (theInstr >> 8) & 3;
+   Int i;
+   IROp cmp;
+   ULong imm;
+   IRTemp arg_l;
+   IRTemp old_mask, new_mask, cur_mask;
+   IRTemp old_res, new_res;
+   IRTemp old_arg, new_arg;
+
+   if (dreg >= 0x100 || mreg >= 0x100 || nreg >= 0x100)
+      return False;
+   if (nreg + len > 31)
+      return False;
+
+   cmp = Iop_CmpGT8Ux8;
+
+   old_mask = newTemp(Ity_I64);
+   old_res = newTemp(Ity_I64);
+   old_arg = newTemp(Ity_I64);
+   assign(old_mask, mkU64(0));
+   assign(old_res, mkU64(0));
+   assign(old_arg, getDRegI64(mreg));
+   imm = 8;
+   imm = (imm <<  8) | imm;
+   imm = (imm << 16) | imm;
+   imm = (imm << 32) | imm;
+
+   for (i = 0; i <= len; i++) {
+      arg_l = newTemp(Ity_I64);
+      new_mask = newTemp(Ity_I64);
+      cur_mask = newTemp(Ity_I64);
+      new_res = newTemp(Ity_I64);
+      new_arg = newTemp(Ity_I64);
+      assign(arg_l, getDRegI64(nreg+i));
+      assign(new_arg, binop(Iop_Sub8x8, mkexpr(old_arg), mkU64(imm)));
+      assign(cur_mask, binop(cmp, mkU64(imm), mkexpr(old_arg)));
+      assign(new_mask, binop(Iop_Or64, mkexpr(old_mask), mkexpr(cur_mask)));
+      assign(new_res, binop(Iop_Or64,
+                            mkexpr(old_res),
+                            binop(Iop_And64,
+                                  binop(Iop_Perm8x8,
+                                        mkexpr(arg_l),
+                                        binop(Iop_And64,
+                                              mkexpr(old_arg),
+                                              mkexpr(cur_mask))),
+                                  mkexpr(cur_mask))));
+
+      old_arg = new_arg;
+      old_mask = new_mask;
+      old_res = new_res;
+   }
+   if (op) {
+      new_res = newTemp(Ity_I64);
+      assign(new_res, binop(Iop_Or64,
+                            binop(Iop_And64,
+                                  getDRegI64(dreg),
+                                  unop(Iop_Not64, mkexpr(old_mask))),
+                            mkexpr(old_res)));
+      old_res = new_res;
+   }

 
 

-   if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0))
-       && !(INSN(25,25) == 0 && INSN(7,7) == 1 && INSN(4,4) == 1)) {
-      IRTemp  shop = IRTemp_INVALID; /* shifter operand */
-      IRTemp  shco = IRTemp_INVALID; /* shifter carry out */
-      UInt    rD   = (insn >> 12) & 0xF; /* 15:12 */
-      UInt    rN   = (insn >> 16) & 0xF; /* 19:16 */
-      UInt    bitS = (insn >> 20) & 1; /* 20:20 */
-      IRTemp  rNt  = IRTemp_INVALID;
-      IRTemp  res  = IRTemp_INVALID;
-      IRTemp  oldV = IRTemp_INVALID;
-      IRTemp  oldC = IRTemp_INVALID;
-      HChar*  name = NULL;
-      IROp    op   = Iop_INVALID;
-      Bool    ok;
+   putDRegI64(dreg, mkexpr(old_res), condT);
+   DIP("vtb%c.8 d%u, {", op ? 'x' : 'l', dreg);
+   if (len > 0) {
+      DIP("d%u-d%u", nreg, nreg + len);
+   } else {
+      DIP("d%u", nreg);
+   }
+   DIP("}, d%u\n", mreg);
+   return True;
+}

 
 

-      switch (INSN(24,21)) {
+/* VDUP (scalar)  */
+static
+Bool dis_neon_vdup ( UInt theInstr, IRTemp condT )
+{
+   UInt Q = (theInstr >> 6) & 1;
+   UInt dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF);
+   UInt mreg = ((theInstr >> 1) & 0x10) | (theInstr & 0xF);
+   UInt imm4 = (theInstr >> 16) & 0xF;
+   UInt index;
+   UInt size;
+   IRTemp arg_m;
+   IRTemp res;
+   IROp op, op2;
+
+   if ((imm4 == 0) || (imm4 == 8))
+      return False;
+   if ((Q == 1) && ((dreg & 1) == 1))
+      return False;
+   if (Q)
+      dreg >>= 1;
+   arg_m = newTemp(Ity_I64);
+   assign(arg_m, getDRegI64(mreg));
+   if (Q)
+      res = newTemp(Ity_V128);
+   else
+      res = newTemp(Ity_I64);
+   if ((imm4 & 1) == 1) {
+      op = Q ? Iop_Dup8x16 : Iop_Dup8x8;
+      op2 = Iop_GetElem8x8;
+      index = imm4 >> 1;
+      size = 8;
+   } else if ((imm4 & 3) == 2) {
+      op = Q ? Iop_Dup16x8 : Iop_Dup16x4;
+      op2 = Iop_GetElem16x4;
+      index = imm4 >> 2;
+      size = 16;
+   } else if ((imm4 & 7) == 4) {
+      op = Q ? Iop_Dup32x4 : Iop_Dup32x2;
+      op2 = Iop_GetElem32x2;
+      index = imm4 >> 3;
+      size = 32;
+   } else {
+      return False; // can this ever happen?
+   }
+   assign(res, unop(op, binop(op2, mkexpr(arg_m), mkU8(index))));
+   if (Q) {
+      putQReg(dreg, mkexpr(res), condT);
+   } else {
+      putDRegI64(dreg, mkexpr(res), condT);
+   }
+   DIP("vdup.%d %c%d, d%d[%d]\n", size, Q ? 'q' : 'd', dreg, mreg, index);
+   return True;
+}

 
 

-         /* --------- ADD, SUB, AND, OR --------- */
-         case BITS4(0,1,0,0): /* ADD:  Rd = Rn + shifter_operand */
-            name = "add"; op = Iop_Add32; goto rd_eq_rn_op_SO;
-         case BITS4(0,0,1,0): /* SUB:  Rd = Rn - shifter_operand */
-            name = "sub"; op = Iop_Sub32; goto rd_eq_rn_op_SO;
-         case BITS4(0,0,1,1): /* RSB:  Rd = shifter_operand - Rn */
-            name = "rsb"; op = Iop_Sub32; goto rd_eq_rn_op_SO;
-         case BITS4(0,0,0,0): /* AND:  Rd = Rn & shifter_operand */
-            name = "and"; op = Iop_And32; goto rd_eq_rn_op_SO;
-         case BITS4(1,1,0,0): /* OR:   Rd = Rn | shifter_operand */
-            name = "orr"; op = Iop_Or32; goto rd_eq_rn_op_SO;
-         case BITS4(0,0,0,1): /* EOR:  Rd = Rn ^ shifter_operand */
-            name = "eor"; op = Iop_Xor32; goto rd_eq_rn_op_SO;
-         case BITS4(1,1,1,0): /* BIC:  Rd = Rn & ~shifter_operand */
-            name = "bic"; op = Iop_And32; goto rd_eq_rn_op_SO;
-         rd_eq_rn_op_SO: {
-            Bool isRSB = False;
-            Bool isBIC = False;
-            switch (INSN(24,21)) {
-               case BITS4(0,0,1,1):
-                  vassert(op == Iop_Sub32); isRSB = True; break;
-               case BITS4(1,1,1,0):
-                  vassert(op == Iop_And32); isBIC = True; break;
-               default:
-                  break;
+/* A7.4.1 Three registers of the same length */
+static
+Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT )
+{
+   UInt Q = (theInstr >> 6) & 1;
+   UInt dreg = get_neon_d_regno(theInstr);
+   UInt nreg = get_neon_n_regno(theInstr);
+   UInt mreg = get_neon_m_regno(theInstr);
+   UInt A = (theInstr >> 8) & 0xF;
+   UInt B = (theInstr >> 4) & 1;
+   UInt C = (theInstr >> 20) & 0x3;
+   UInt U = (theInstr >> 24) & 1;
+   UInt size = C;
+
+   IRTemp arg_n;
+   IRTemp arg_m;
+   IRTemp res;
+
+   if (Q) {
+      arg_n = newTemp(Ity_V128);
+      arg_m = newTemp(Ity_V128);
+      res = newTemp(Ity_V128);
+      assign(arg_n, getQReg(nreg));
+      assign(arg_m, getQReg(mreg));
+   } else {
+      arg_n = newTemp(Ity_I64);
+      arg_m = newTemp(Ity_I64);
+      res = newTemp(Ity_I64);
+      assign(arg_n, getDRegI64(nreg));
+      assign(arg_m, getDRegI64(mreg));
+   }
+
+   switch(A) {
+      case 0:
+         if (B == 0) {
+            /* VHADD */
+            ULong imm = 0;
+            IRExpr *imm_val;
+            IROp addOp;
+            IROp andOp;
+            IROp shOp;
+            char regType = Q ? 'q' : 'd';
+
+            if (size == 3)
+               return False;
+            switch(size) {
+               case 0: imm = 0x101010101010101LL; break;
+               case 1: imm = 0x1000100010001LL; break;
+               case 2: imm = 0x100000001LL; break;
+               default: vassert(0);

             }
             }

-            rNt = newTemp(Ity_I32);
-            assign(rNt, getIReg(rN));
-            ok = mk_shifter_operand(
-                    INSN(25,25), INSN(11,0), 
-                    &shop, bitS ? &shco : NULL, dis_buf
-                 );
-            if (!ok)
-               break;
-            res = newTemp(Ity_I32);
-            // compute the main result
-            if (isRSB) {
-               // reverse-subtract: shifter_operand - Rn
-               vassert(op == Iop_Sub32);
-               assign(res, binop(op, mkexpr(shop), mkexpr(rNt)) );
-            } else if (isBIC) {
-               // andn: shifter_operand & ~Rn
-               vassert(op == Iop_And32);
-               assign(res, binop(op, mkexpr(rNt),
-                                     unop(Iop_Not32, mkexpr(shop))) );
+            if (Q) {
+               imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm));
+               andOp = Iop_AndV128;

             } else {
             } else {

-               // normal: Rn op shifter_operand
-               assign(res, binop(op, mkexpr(rNt), mkexpr(shop)) );
-            }
-            // but don't commit it until after we've finished
-            // all necessary reads from the guest state
-            if (bitS
-                && (op == Iop_And32 || op == Iop_Or32 || op == Iop_Xor32)) {
-               oldV = newTemp(Ity_I32);
-               assign( oldV, mk_armg_calculate_flag_v() );
+               imm_val = mkU64(imm);
+               andOp = Iop_And64;

             }
             }

-            // now safe to put the main result
-            putIReg( rD, mkexpr(res), condT, Ijk_Boring );
-            // XXXX!! not safe to read any guest state after
-            // this point (I think the code below doesn't do that).
-            if (!bitS)
-               vassert(shco == IRTemp_INVALID);
-            /* Update the flags thunk if necessary */
-            if (bitS) {
-               vassert(shco != IRTemp_INVALID);
-               switch (op) {
-                  case Iop_Add32:
-                     setFlags_D1_D2( ARMG_CC_OP_ADD, rNt, shop, condT );
+            if (U) {
+               switch(size) {
+                  case 0:
+                     addOp = Q ? Iop_Add8x16 : Iop_Add8x8;
+                     shOp = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;

                      break;
                      break;

-                  case Iop_Sub32:
-                     if (isRSB) {
-                        setFlags_D1_D2( ARMG_CC_OP_SUB, shop, rNt, condT );
-                     } else {
-                        setFlags_D1_D2( ARMG_CC_OP_SUB, rNt, shop, condT );
-                     }
+                  case 1:
+                     addOp = Q ? Iop_Add16x8 : Iop_Add16x4;
+                     shOp = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;

                      break;
                      break;

-                  case Iop_And32: /* BIC and AND set the flags the same */
-                  case Iop_Or32:
-                  case Iop_Xor32:
-                     // oldV has been read just above
-                     setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC,
-                                        res, shco, oldV, condT );
+                  case 2:
+                     addOp = Q ? Iop_Add32x4 : Iop_Add32x2;
+                     shOp = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch(size) {
+                  case 0:
+                     addOp = Q ? Iop_Add8x16 : Iop_Add8x8;
+                     shOp = Q ? Iop_SarN8x16 : Iop_SarN8x8;
+                     break;
+                  case 1:
+                     addOp = Q ? Iop_Add16x8 : Iop_Add16x4;
+                     shOp = Q ? Iop_SarN16x8 : Iop_SarN16x4;
+                     break;
+                  case 2:
+                     addOp = Q ? Iop_Add32x4 : Iop_Add32x2;
+                     shOp = Q ? Iop_SarN32x4 : Iop_SarN32x2;

                      break;
                   default:
                      vassert(0);
                }
             }
                      break;
                   default:
                      vassert(0);
                }
             }

-            DIP("%s%s%s r%u, r%u, %s\n",
-                name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
-            goto decode_success;
-         }
-
-         /* --------- MOV, MVN --------- */
-         case BITS4(1,1,0,1):   /* MOV: Rd = shifter_operand */
-         case BITS4(1,1,1,1): { /* MVN: Rd = not(shifter_operand) */
-            Bool isMVN = INSN(24,21) == BITS4(1,1,1,1);
-            if (rN != 0)
-               break; /* rN must be zero */
-            ok = mk_shifter_operand(
-                    INSN(25,25), INSN(11,0), 
-                    &shop, bitS ? &shco : NULL, dis_buf
-                 );
-            if (!ok)
-               break;
-            res = newTemp(Ity_I32);
-            assign( res, isMVN ? unop(Iop_Not32, mkexpr(shop))
-                               : mkexpr(shop) );
-            if (bitS) {
-               vassert(shco != IRTemp_INVALID);
-               oldV = newTemp(Ity_I32);
-               assign( oldV, mk_armg_calculate_flag_v() );
+            assign(res,
+                   binop(addOp,
+                         binop(addOp,
+                               binop(shOp, mkexpr(arg_m), mkU8(1)),
+                               binop(shOp, mkexpr(arg_n), mkU8(1))),
+                         binop(shOp,
+                               binop(addOp,
+                                     binop(andOp, mkexpr(arg_m), imm_val),
+                                     binop(andOp, mkexpr(arg_n), imm_val)),
+                               mkU8(1))));
+            DIP("vhadd.%c%d %c%d, %c%d, %c%d\n",
+                U ? 'u' : 's', 8 << size, regType,
+                dreg, regType, nreg, regType, mreg);
+         } else {
+            /* VQADD */
+            IROp op, op2;
+            IRTemp tmp;
+            char reg_t = Q ? 'q' : 'd';
+            if (Q) {
+               switch (size) {
+                  case 0:
+                     op = U ? Iop_QAdd8Ux16 : Iop_QAdd8Sx16;
+                     op2 = Iop_Add8x16;
+                     break;
+                  case 1:
+                     op = U ? Iop_QAdd16Ux8 : Iop_QAdd16Sx8;
+                     op2 = Iop_Add16x8;
+                     break;
+                  case 2:
+                     op = U ? Iop_QAdd32Ux4 : Iop_QAdd32Sx4;
+                     op2 = Iop_Add32x4;
+                     break;
+                  case 3:
+                     op = U ? Iop_QAdd64Ux2 : Iop_QAdd64Sx2;
+                     op2 = Iop_Add64x2;
+                     break;
+                  default:
+                     vassert(0);
+               }

             } else {
             } else {

-               vassert(shco == IRTemp_INVALID);
+               switch (size) {
+                  case 0:
+                     op = U ? Iop_QAdd8Ux8 : Iop_QAdd8Sx8;
+                     op2 = Iop_Add8x8;
+                     break;
+                  case 1:
+                     op = U ? Iop_QAdd16Ux4 : Iop_QAdd16Sx4;
+                     op2 = Iop_Add16x4;
+                     break;
+                  case 2:
+                     op = U ? Iop_QAdd32Ux2 : Iop_QAdd32Sx2;
+                     op2 = Iop_Add32x2;
+                     break;
+                  case 3:
+                     op = U ? Iop_QAdd64Ux1 : Iop_QAdd64Sx1;
+                     op2 = Iop_Add64;
+                     break;
+                  default:
+                     vassert(0);
+               }

             }
             }

-            // can't safely read guest state after here
-            putIReg( rD, mkexpr(res), condT, Ijk_Boring );
-            /* Update the flags thunk if necessary */
-            if (bitS) {
-               setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, 
-                                  res, shco, oldV, condT );
+            if (Q) {
+               tmp = newTemp(Ity_V128);
+            } else {
+               tmp = newTemp(Ity_I64);

             }
             }

-            DIP("%s%s%s r%u, %s\n",
-                isMVN ? "mvn" : "mov",
-                nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf );
-            goto decode_success;
-         }
-
-         /* --------- CMP --------- */
-         case BITS4(1,0,1,0):   /* CMP:  (void) Rn - shifter_operand */
-         case BITS4(1,0,1,1): { /* CMN:  (void) Rn + shifter_operand */
-            Bool isCMN = INSN(24,21) == BITS4(1,0,1,1);
-            if (rD != 0)
-               break; /* rD must be zero */
-            if (bitS == 0)
-               break; /* if S (bit 20) is not set, it's not CMP/CMN */
-            rNt = newTemp(Ity_I32);
-            assign(rNt, getIReg(rN));
-            ok = mk_shifter_operand(
-                    INSN(25,25), INSN(11,0), 
-                    &shop, NULL, dis_buf
-                 );
-            if (!ok)
-               break;
-            /* Update the flags thunk. */
-            setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB,
-                            rNt, shop, condT );
-            DIP("%s%s r%u, %s\n",
-                isCMN ? "cmn" : "cmp",
-                nCC(INSN_COND), rN, dis_buf );
-            goto decode_success;
-         }
-
-         /* --------- TST --------- */
-         case BITS4(1,0,0,0):   /* TST:  (void) Rn & shifter_operand */
-         case BITS4(1,0,0,1): { /* TEQ:  (void) Rn ^ shifter_operand */
-            Bool isTEQ = INSN(24,21) == BITS4(1,0,0,1);
-            if (rD != 0)
-               break; /* rD must be zero */
-            if (bitS == 0)
-               break; /* if S (bit 20) is not set, it's not TST/TEQ */
-            rNt = newTemp(Ity_I32);
-            assign(rNt, getIReg(rN));
-            ok = mk_shifter_operand(
-                    INSN(25,25), INSN(11,0), 
-                    &shop, &shco, dis_buf
-                 );
-            if (!ok)
-               break;
-            /* Update the flags thunk. */
-            res = newTemp(Ity_I32);
-            assign( res, binop(isTEQ ? Iop_Xor32 : Iop_And32, 
-                               mkexpr(rNt), mkexpr(shop)) );
-            oldV = newTemp(Ity_I32);
-            assign( oldV, mk_armg_calculate_flag_v() );
-            setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC,
-                               res, shco, oldV, condT );
-            DIP("%s%s r%u, %s\n",
-                isTEQ ? "teq" : "tst",
-                nCC(INSN_COND), rN, dis_buf );
-            goto decode_success;
+            assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+#ifndef DISABLE_QC_FLAG
+            assign(tmp, binop(op2, mkexpr(arg_n), mkexpr(arg_m)));
+            setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT);
+#endif
+            DIP("vqadd.%c%d %c%d, %c%d, %c%d\n",
+                U ? 'u' : 's',
+                8 << size, reg_t, dreg, reg_t, nreg, reg_t, mreg);

          }
          }

-
-         /* --------- ADC, SBC, RSC --------- */
-         case BITS4(0,1,0,1): /* ADC:  Rd = Rn + shifter_operand + oldC */
-            name = "adc"; goto rd_eq_rn_op_SO_op_oldC;
-         case BITS4(0,1,1,0): /* SBC:  Rd = Rn - shifter_operand - (oldC ^ 1) */
-            name = "sbc"; goto rd_eq_rn_op_SO_op_oldC;
-         case BITS4(0,1,1,1): /* RSC:  Rd = shifter_operand - Rn - (oldC ^ 1) */
-            name = "rsc"; goto rd_eq_rn_op_SO_op_oldC;
-         rd_eq_rn_op_SO_op_oldC: {
-            rNt = newTemp(Ity_I32);
-            assign(rNt, getIReg(rN));
-            ok = mk_shifter_operand(
-                    INSN(25,25), INSN(11,0), 
-                    &shop, bitS ? &shco : NULL, dis_buf
-                 );
-            if (!ok)
-               break;
-            oldC = newTemp(Ity_I32);
-            assign( oldC, mk_armg_calculate_flag_c() );
-            res = newTemp(Ity_I32);
-            // compute the main result
-            switch (INSN(24,21)) {
-               case BITS4(0,1,0,1): /* ADC */
-                  assign(res,
-                         binop(Iop_Add32,
-                               binop(Iop_Add32, mkexpr(rNt), mkexpr(shop)),
-                               mkexpr(oldC) ));
-                  break;
-               case BITS4(0,1,1,0): /* SBC */
-                  assign(res,
-                         binop(Iop_Sub32,
-                               binop(Iop_Sub32, mkexpr(rNt), mkexpr(shop)),
-                               binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) ));
-                  break;
-               case BITS4(0,1,1,1): /* RSC */
-                  assign(res,
-                         binop(Iop_Sub32,
-                               binop(Iop_Sub32, mkexpr(shop), mkexpr(rNt)),
-                               binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) ));
-                  break;
-               default:
-                  vassert(0);
+         break;
+      case 1:
+         if (B == 0) {
+            /* VRHADD */
+            /* VRHADD C, A, B ::=
+                 C = (A >> 1) + (B >> 1) + (((A & 1) + (B & 1) + 1) >> 1) */
+            IROp shift_op, add_op;
+            IRTemp cc;
+            ULong one = 1;
+            HChar reg_t = Q ? 'q' : 'd';
+            switch (size) {
+               case 0: one = (one <<  8) | one; /* fall through */
+               case 1: one = (one << 16) | one; /* fall through */
+               case 2: one = (one << 32) | one; break;
+               case 3: return False;
+               default: vassert(0);

             }
             }

-            // but don't commit it until after we've finished
-            // all necessary reads from the guest state
-            // now safe to put the main result
-            putIReg( rD, mkexpr(res), condT, Ijk_Boring );
-            // XXXX!! not safe to read any guest state after
-            // this point (I think the code below doesn't do that).
-            if (!bitS)
-               vassert(shco == IRTemp_INVALID);
-            /* Update the flags thunk if necessary */
-            if (bitS) {
-               vassert(shco != IRTemp_INVALID);
-               switch (INSN(24,21)) {
-                  case BITS4(0,1,0,1): /* ADC */
-                     setFlags_D1_D2_ND( ARMG_CC_OP_ADC,
-                                        rNt, shop, oldC, condT );
+            if (Q) {
+               switch (size) {
+                  case 0:
+                     shift_op = U ? Iop_ShrN8x16 : Iop_SarN8x16;
+                     add_op = Iop_Add8x16;

                      break;
                      break;

-                  case BITS4(0,1,1,0): /* SBC */
-                     setFlags_D1_D2_ND( ARMG_CC_OP_SBB,
-                                        rNt, shop, oldC, condT );
+                  case 1:
+                     shift_op = U ? Iop_ShrN16x8 : Iop_SarN16x8;
+                     add_op = Iop_Add16x8;

                      break;
                      break;

-                  case BITS4(0,1,1,1): /* RSC */
-                     setFlags_D1_D2_ND( ARMG_CC_OP_SBB,
-                                        shop, rNt, oldC, condT );
+                  case 2:
+                     shift_op = U ? Iop_ShrN32x4 : Iop_SarN32x4;
+                     add_op = Iop_Add32x4;

                      break;
                      break;

+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     shift_op = U ? Iop_ShrN8x8 : Iop_SarN8x8;
+                     add_op = Iop_Add8x8;
+                     break;
+                  case 1:
+                     shift_op = U ? Iop_ShrN16x4 : Iop_SarN16x4;
+                     add_op = Iop_Add16x4;
+                     break;
+                  case 2:
+                     shift_op = U ? Iop_ShrN32x2 : Iop_SarN32x2;
+                     add_op = Iop_Add32x2;
+                     break;
+                  case 3:
+                     return False;

                   default:
                      vassert(0);
                }
             }
                   default:
                      vassert(0);
                }
             }

-            DIP("%s%s%s r%u, r%u, %s\n",
-                name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
-            goto decode_success;
-         }
-
-         /* --------- ??? --------- */
-         default:
-            break;
-      }
-   } /* if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0)) */
-
-   /* --------------------- Load/store (ubyte & word) -------- */
-   // LDR STR LDRB STRB
-   /*                 31   27   23   19 15 11    6   4 3  # highest bit
-                        28   24   20 16 12
-      A5-20   1 | 16  cond 0101 UB0L Rn Rd imm12
-      A5-22   1 | 32  cond 0111 UBOL Rn Rd imm5  sh2 0 Rm
+            if (Q) {
+               cc = newTemp(Ity_V128);
+               assign(cc, binop(shift_op,
+                                binop(add_op,
+                                      binop(add_op,
+                                            binop(Iop_AndV128,
+                                                  mkexpr(arg_n),
+                                                  binop(Iop_64HLtoV128,
+                                                        mkU64(one),
+                                                        mkU64(one))),
+                                            binop(Iop_AndV128,
+                                                  mkexpr(arg_m),
+                                                  binop(Iop_64HLtoV128,
+                                                        mkU64(one),
+                                                        mkU64(one)))),
+                                      binop(Iop_64HLtoV128,
+                                            mkU64(one),
+                                            mkU64(one))),
+                                mkU8(1)));
+               assign(res, binop(add_op,
+                                 binop(add_op,
+                                       binop(shift_op,
+                                             mkexpr(arg_n),
+                                             mkU8(1)),
+                                       binop(shift_op,
+                                             mkexpr(arg_m),
+                                             mkU8(1))),
+                                 mkexpr(cc)));
+            } else {
+               cc = newTemp(Ity_I64);
+               assign(cc, binop(shift_op,
+                                binop(add_op,
+                                      binop(add_op,
+                                            binop(Iop_And64,
+                                                  mkexpr(arg_n),
+                                                  mkU64(one)),
+                                            binop(Iop_And64,
+                                                  mkexpr(arg_m),
+                                                  mkU64(one))),
+                                      mkU64(one)),
+                                mkU8(1)));
+               assign(res, binop(add_op,
+                                 binop(add_op,
+                                       binop(shift_op,
+                                             mkexpr(arg_n),
+                                             mkU8(1)),
+                                       binop(shift_op,
+                                             mkexpr(arg_m),
+                                             mkU8(1))),
+                                 mkexpr(cc)));
+            }
+            DIP("vrhadd.%c%d %c%d, %c%d, %c%d\n",
+                U ? 'u' : 's',
+                8 << size, reg_t, dreg, reg_t, nreg, reg_t, mreg);
+         } else {
+            if (U == 0)  {
+               switch(C) {
+                  case 0: {
+                     /* VAND  */
+                     HChar reg_t = Q ? 'q' : 'd';
+                     if (Q) {
+                        assign(res, binop(Iop_AndV128, mkexpr(arg_n), 
+                                                       mkexpr(arg_m)));
+                     } else {
+                        assign(res, binop(Iop_And64, mkexpr(arg_n),
+                                                     mkexpr(arg_m)));
+                     }
+                     DIP("vand %c%d, %c%d, %c%d\n",
+                         reg_t, dreg, reg_t, nreg, reg_t, mreg);
+                     break;
+                  }
+                  case 1: {
+                     /* VBIC  */
+                     HChar reg_t = Q ? 'q' : 'd';
+                     if (Q) {
+                        assign(res, binop(Iop_AndV128,mkexpr(arg_n),
+                               unop(Iop_NotV128, mkexpr(arg_m))));
+                     } else {
+                        assign(res, binop(Iop_And64, mkexpr(arg_n),
+                               unop(Iop_Not64, mkexpr(arg_m))));
+                     }
+                     DIP("vbic %c%d, %c%d, %c%d\n",
+                         reg_t, dreg, reg_t, nreg, reg_t, mreg);
+                     break;
+                  }
+                  case 2:
+                     if ( nreg != mreg) {
+                        /* VORR  */
+                        HChar reg_t = Q ? 'q' : 'd';
+                        if (Q) {
+                           assign(res, binop(Iop_OrV128, mkexpr(arg_n),
+                                                         mkexpr(arg_m)));
+                        } else {
+                           assign(res, binop(Iop_Or64, mkexpr(arg_n),
+                                                       mkexpr(arg_m)));
+                        }
+                        DIP("vorr %c%d, %c%d, %c%d\n",
+                            reg_t, dreg, reg_t, nreg, reg_t, mreg);
+                     } else {
+                        /* VMOV  */
+                        HChar reg_t = Q ? 'q' : 'd';
+                        assign(res, mkexpr(arg_m));
+                        DIP("vmov %c%d, %c%d\n", reg_t, dreg, reg_t, mreg);
+                     }
+                     break;
+                  case 3:{
+                     /* VORN  */
+                     HChar reg_t = Q ? 'q' : 'd';
+                     if (Q) {
+                        assign(res, binop(Iop_OrV128,mkexpr(arg_n),
+                               unop(Iop_NotV128, mkexpr(arg_m))));
+                     } else {
+                        assign(res, binop(Iop_Or64, mkexpr(arg_n),
+                               unop(Iop_Not64, mkexpr(arg_m))));
+                     }
+                     DIP("vorn %c%d, %c%d, %c%d\n",
+                         reg_t, dreg, reg_t, nreg, reg_t, mreg);
+                     break;
+                  }
+               }
+            } else {
+               switch(C) {
+                  case 0:
+                     /* VEOR (XOR)  */
+                     if (Q) {
+                        assign(res, binop(Iop_XorV128, mkexpr(arg_n),
+                                                       mkexpr(arg_m)));
+                     } else {
+                        assign(res, binop(Iop_Xor64, mkexpr(arg_n),
+                                                     mkexpr(arg_m)));
+                     }
+                     DIP("veor %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg,
+                           Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+                     break;
+                  case 1:
+                     /* VBSL  */
+                     if (Q) {
+                        IRTemp reg_d = newTemp(Ity_V128);
+                        assign(reg_d, getQReg(dreg));
+                        assign(res,
+                               binop(Iop_OrV128,
+                                     binop(Iop_AndV128, mkexpr(arg_n),
+                                                        mkexpr(reg_d)),
+                                     binop(Iop_AndV128,
+                                           mkexpr(arg_m),
+                                           unop(Iop_NotV128,
+                                                 mkexpr(reg_d)) ) ) );
+                     } else {
+                        IRTemp reg_d = newTemp(Ity_I64);
+                        assign(reg_d, getDRegI64(dreg));
+                        assign(res,
+                               binop(Iop_Or64,
+                                     binop(Iop_And64, mkexpr(arg_n),
+                                                      mkexpr(reg_d)),
+                                     binop(Iop_And64,
+                                           mkexpr(arg_m),
+                                           unop(Iop_Not64, mkexpr(reg_d)))));
+                     }
+                     DIP("vbsl %c%u, %c%u, %c%u\n",
+                         Q ? 'q' : 'd', dreg,
+                         Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+                     break;
+                  case 2:
+                     /* VBIT  */
+                     if (Q) {
+                        IRTemp reg_d = newTemp(Ity_V128);
+                        assign(reg_d, getQReg(dreg));
+                        assign(res,
+                               binop(Iop_OrV128,
+                                     binop(Iop_AndV128, mkexpr(arg_n), 
+                                                        mkexpr(arg_m)),
+                                     binop(Iop_AndV128,
+                                           mkexpr(reg_d),
+                                           unop(Iop_NotV128, mkexpr(arg_m)))));
+                     } else {
+                        IRTemp reg_d = newTemp(Ity_I64);
+                        assign(reg_d, getDRegI64(dreg));
+                        assign(res,
+                               binop(Iop_Or64,
+                                     binop(Iop_And64, mkexpr(arg_n),
+                                                      mkexpr(arg_m)),
+                                     binop(Iop_And64,
+                                           mkexpr(reg_d),
+                                           unop(Iop_Not64, mkexpr(arg_m)))));
+                     }
+                     DIP("vbit %c%u, %c%u, %c%u\n",
+                         Q ? 'q' : 'd', dreg,
+                         Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+                     break;
+                  case 3:
+                     /* VBIF  */
+                     if (Q) {
+                        IRTemp reg_d = newTemp(Ity_V128);
+                        assign(reg_d, getQReg(dreg));
+                        assign(res,
+                               binop(Iop_OrV128,
+                                     binop(Iop_AndV128, mkexpr(reg_d),
+                                                        mkexpr(arg_m)),
+                                     binop(Iop_AndV128,
+                                           mkexpr(arg_n),
+                                           unop(Iop_NotV128, mkexpr(arg_m)))));
+                     } else {
+                        IRTemp reg_d = newTemp(Ity_I64);
+                        assign(reg_d, getDRegI64(dreg));
+                        assign(res,
+                               binop(Iop_Or64,
+                                     binop(Iop_And64, mkexpr(reg_d),
+                                                      mkexpr(arg_m)),
+                                     binop(Iop_And64,
+                                           mkexpr(arg_n),
+                                           unop(Iop_Not64, mkexpr(arg_m)))));
+                     }
+                     DIP("vbif %c%u, %c%u, %c%u\n",
+                         Q ? 'q' : 'd', dreg,
+                         Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+                     break;
+               }
+            }
+         }
+         break;
+      case 2:
+         if (B == 0) {
+            /* VHSUB */
+            /* (A >> 1) - (B >> 1) - (NOT (A) & B & 1)   */
+            ULong imm = 0;
+            IRExpr *imm_val;
+            IROp subOp;
+            IROp notOp;
+            IROp andOp;
+            IROp shOp;
+            if (size == 3)
+               return False;
+            switch(size) {
+               case 0: imm = 0x101010101010101LL; break;
+               case 1: imm = 0x1000100010001LL; break;
+               case 2: imm = 0x100000001LL; break;
+               default: vassert(0);
+            }
+            if (Q) {
+               imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm));
+               andOp = Iop_AndV128;
+               notOp = Iop_NotV128;
+            } else {
+               imm_val = mkU64(imm);
+               andOp = Iop_And64;
+               notOp = Iop_Not64;
+            }
+            if (U) {
+               switch(size) {
+                  case 0:
+                     subOp = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     shOp = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     break;
+                  case 1:
+                     subOp = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     shOp = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     break;
+                  case 2:
+                     subOp = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     shOp = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch(size) {
+                  case 0:
+                     subOp = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     shOp = Q ? Iop_SarN8x16 : Iop_SarN8x8;
+                     break;
+                  case 1:
+                     subOp = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     shOp = Q ? Iop_SarN16x8 : Iop_SarN16x4;
+                     break;
+                  case 2:
+                     subOp = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     shOp = Q ? Iop_SarN32x4 : Iop_SarN32x2;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            assign(res,
+                   binop(subOp,
+                         binop(subOp,
+                               binop(shOp, mkexpr(arg_n), mkU8(1)),
+                               binop(shOp, mkexpr(arg_m), mkU8(1))),
+                         binop(andOp,
+                               binop(andOp,
+                                     unop(notOp, mkexpr(arg_n)),
+                                     mkexpr(arg_m)),
+                               imm_val)));
+            DIP("vhsub.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                mreg);
+         } else {
+            /* VQSUB */
+            IROp op, op2;
+            IRTemp tmp;
+            if (Q) {
+               switch (size) {
+                  case 0:
+                     op = U ? Iop_QSub8Ux16 : Iop_QSub8Sx16;
+                     op2 = Iop_Sub8x16;
+                     break;
+                  case 1:
+                     op = U ? Iop_QSub16Ux8 : Iop_QSub16Sx8;
+                     op2 = Iop_Sub16x8;
+                     break;
+                  case 2:
+                     op = U ? Iop_QSub32Ux4 : Iop_QSub32Sx4;
+                     op2 = Iop_Sub32x4;
+                     break;
+                  case 3:
+                     op = U ? Iop_QSub64Ux2 : Iop_QSub64Sx2;
+                     op2 = Iop_Sub64x2;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     op = U ? Iop_QSub8Ux8 : Iop_QSub8Sx8;
+                     op2 = Iop_Sub8x8;
+                     break;
+                  case 1:
+                     op = U ? Iop_QSub16Ux4 : Iop_QSub16Sx4;
+                     op2 = Iop_Sub16x4;
+                     break;
+                  case 2:
+                     op = U ? Iop_QSub32Ux2 : Iop_QSub32Sx2;
+                     op2 = Iop_Sub32x2;
+                     break;
+                  case 3:
+                     op = U ? Iop_QSub64Ux1 : Iop_QSub64Sx1;
+                     op2 = Iop_Sub64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            if (Q)
+               tmp = newTemp(Ity_V128);
+            else
+               tmp = newTemp(Ity_I64);
+            assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+#ifndef DISABLE_QC_FLAG
+            assign(tmp, binop(op2, mkexpr(arg_n), mkexpr(arg_m)));
+            setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT);
+#endif
+            DIP("vqsub.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                mreg);
+         }
+         break;
+      case 3: {
+            IROp op;
+            if (Q) {
+               switch (size) {
+                  case 0: op = U ? Iop_CmpGT8Ux16 : Iop_CmpGT8Sx16; break;
+                  case 1: op = U ? Iop_CmpGT16Ux8 : Iop_CmpGT16Sx8; break;
+                  case 2: op = U ? Iop_CmpGT32Ux4 : Iop_CmpGT32Sx4; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0: op = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8; break;
+                  case 1: op = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4; break;
+                  case 2: op = U ? Iop_CmpGT32Ux2: Iop_CmpGT32Sx2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+            }
+            if (B == 0) {
+               /* VCGT  */
+               assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+               DIP("vcgt.%c%u %c%u, %c%u, %c%u\n",
+                   U ? 'u' : 's', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                   mreg);
+            } else {
+               /* VCGE  */
+               /* VCGE res, argn, argm
+                    is equal to
+                  VCGT tmp, argm, argn
+                  VNOT res, tmp */
+               assign(res,
+                      unop(Q ? Iop_NotV128 : Iop_Not64,
+                           binop(op, mkexpr(arg_m), mkexpr(arg_n))));
+               DIP("vcge.%c%u %c%u, %c%u, %c%u\n",
+                   U ? 'u' : 's', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                   mreg);
+            }
+         }
+         break;
+      case 4:
+         if (B == 0) {
+            /* VSHL */
+            IROp op, sub_op;
+            IRTemp tmp;
+            if (U) {
+               switch (size) {
+                  case 0: op = Q ? Iop_Shl8x16 : Iop_Shl8x8; break;
+                  case 1: op = Q ? Iop_Shl16x8 : Iop_Shl16x4; break;
+                  case 2: op = Q ? Iop_Shl32x4 : Iop_Shl32x2; break;
+                  case 3: op = Q ? Iop_Shl64x2 : Iop_Shl64; break;
+                  default: vassert(0);
+               }
+            } else {
+               tmp = newTemp(Q ? Ity_V128 : Ity_I64);
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_Sar8x16 : Iop_Sar8x8;
+                     sub_op = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_Sar16x8 : Iop_Sar16x4;
+                     sub_op = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_Sar32x4 : Iop_Sar32x2;
+                     sub_op = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_Sar64x2 : Iop_Sar64;
+                     sub_op = Q ? Iop_Sub64x2 : Iop_Sub64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            if (U) {
+               if (!Q && (size == 3))
+                  assign(res, binop(op, mkexpr(arg_m),
+                                        unop(Iop_64to8, mkexpr(arg_n))));
+               else
+                  assign(res, binop(op, mkexpr(arg_m), mkexpr(arg_n)));
+            } else {
+               if (Q)
+                  assign(tmp, binop(sub_op,
+                                    binop(Iop_64HLtoV128, mkU64(0), mkU64(0)),
+                                    mkexpr(arg_n)));
+               else
+                  assign(tmp, binop(sub_op, mkU64(0), mkexpr(arg_n)));
+               if (!Q && (size == 3))
+                  assign(res, binop(op, mkexpr(arg_m),
+                                        unop(Iop_64to8, mkexpr(tmp))));
+               else
+                  assign(res, binop(op, mkexpr(arg_m), mkexpr(tmp)));
+            }
+            DIP("vshl.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd',
+                nreg);
+         } else {
+            /* VQSHL */
+            IROp op, op_rev, op_shrn, op_shln, cmp_neq, cmp_gt;
+            IRTemp tmp, shval, mask, old_shval;
+            UInt i;
+            ULong esize;
+            cmp_neq = Q ? Iop_CmpNEZ8x16 : Iop_CmpNEZ8x8;
+            cmp_gt = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8;
+            if (U) {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_QShl8x16 : Iop_QShl8x8;
+                     op_rev = Q ? Iop_Shr8x16 : Iop_Shr8x8;
+                     op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_QShl16x8 : Iop_QShl16x4;
+                     op_rev = Q ? Iop_Shr16x8 : Iop_Shr16x4;
+                     op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_QShl32x4 : Iop_QShl32x2;
+                     op_rev = Q ? Iop_Shr32x4 : Iop_Shr32x2;
+                     op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_QShl64x2 : Iop_QShl64x1;
+                     op_rev = Q ? Iop_Shr64x2 : Iop_Shr64;
+                     op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64;
+                     op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_QSal8x16 : Iop_QSal8x8;
+                     op_rev = Q ? Iop_Sar8x16 : Iop_Sar8x8;
+                     op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_QSal16x8 : Iop_QSal16x4;
+                     op_rev = Q ? Iop_Sar16x8 : Iop_Sar16x4;
+                     op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_QSal32x4 : Iop_QSal32x2;
+                     op_rev = Q ? Iop_Sar32x4 : Iop_Sar32x2;
+                     op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_QSal64x2 : Iop_QSal64x1;
+                     op_rev = Q ? Iop_Sar64x2 : Iop_Sar64;
+                     op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64;
+                     op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            if (Q) {
+               tmp = newTemp(Ity_V128);
+               shval = newTemp(Ity_V128);
+               mask = newTemp(Ity_V128);
+            } else {
+               tmp = newTemp(Ity_I64);
+               shval = newTemp(Ity_I64);
+               mask = newTemp(Ity_I64);
+            }
+            assign(res, binop(op, mkexpr(arg_m), mkexpr(arg_n)));
+#ifndef DISABLE_QC_FLAG
+            /* Only least significant byte from second argument is used.
+               Copy this byte to the whole vector element. */
+            assign(shval, binop(op_shrn,
+                                binop(op_shln,
+                                       mkexpr(arg_n),
+                                       mkU8((8 << size) - 8)),
+                                mkU8((8 << size) - 8)));
+            for(i = 0; i < size; i++) {
+               old_shval = shval;
+               shval = newTemp(Q ? Ity_V128 : Ity_I64);
+               assign(shval, binop(Q ? Iop_OrV128 : Iop_Or64,
+                                   mkexpr(old_shval),
+                                   binop(op_shln,
+                                         mkexpr(old_shval),
+                                         mkU8(8 << i))));
+            }
+            /* If shift is greater or equal to the element size and
+               element is non-zero, then QC flag should be set. */
+            esize = (8 << size) - 1;
+            esize = (esize <<  8) | esize;
+            esize = (esize << 16) | esize;
+            esize = (esize << 32) | esize;
+            setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64,
+                             binop(cmp_gt, mkexpr(shval),
+                                           Q ? mkU128(esize) : mkU64(esize)),
+                             unop(cmp_neq, mkexpr(arg_m))),
+                       Q ? mkU128(0) : mkU64(0),
+                       Q, condT);
+            /* Othervise QC flag should be set if shift value is positive and
+               result beign rightshifted the same value is not equal to left
+               argument. */
+            assign(mask, binop(cmp_gt, mkexpr(shval),
+                                       Q ? mkU128(0) : mkU64(0)));
+            if (!Q && size == 3)
+               assign(tmp, binop(op_rev, mkexpr(res),
+                                         unop(Iop_64to8, mkexpr(arg_n))));
+            else
+               assign(tmp, binop(op_rev, mkexpr(res), mkexpr(arg_n)));
+            setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64,
+                             mkexpr(tmp), mkexpr(mask)),
+                       binop(Q ? Iop_AndV128 : Iop_And64,
+                             mkexpr(arg_m), mkexpr(mask)),
+                       Q, condT);
+#endif
+            DIP("vqshl.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd',
+                nreg);
+         }
+         break;
+      case 5:
+         if (B == 0) {
+            /* VRSHL */
+            IROp op, op_shrn, op_shln, cmp_gt, op_sub, op_add;
+            IRTemp shval, old_shval, imm_val, round;
+            UInt i;
+            ULong imm;
+            cmp_gt = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8;
+            imm = 1L;
+            switch (size) {
+               case 0: imm = (imm <<  8) | imm; /* fall through */
+               case 1: imm = (imm << 16) | imm; /* fall through */
+               case 2: imm = (imm << 32) | imm; /* fall through */
+               case 3: break;
+               default: vassert(0);
+            }
+            imm_val = newTemp(Q ? Ity_V128 : Ity_I64);
+            round = newTemp(Q ? Ity_V128 : Ity_I64);
+            assign(imm_val, Q ? mkU128(imm) : mkU64(imm));
+            if (U) {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_Shl8x16 : Iop_Shl8x8;
+                     op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     op_add = Q ? Iop_Add8x16 : Iop_Add8x8;
+                     op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_Shl16x8 : Iop_Shl16x4;
+                     op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     op_add = Q ? Iop_Add16x8 : Iop_Add16x4;
+                     op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_Shl32x4 : Iop_Shl32x2;
+                     op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     op_add = Q ? Iop_Add32x4 : Iop_Add32x2;
+                     op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_Shl64x2 : Iop_Shl64;
+                     op_sub = Q ? Iop_Sub64x2 : Iop_Sub64;
+                     op_add = Q ? Iop_Add64x2 : Iop_Add64;
+                     op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64;
+                     op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_Sal8x16 : Iop_Sal8x8;
+                     op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     op_add = Q ? Iop_Add8x16 : Iop_Add8x8;
+                     op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_Sal16x8 : Iop_Sal16x4;
+                     op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     op_add = Q ? Iop_Add16x8 : Iop_Add16x4;
+                     op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_Sal32x4 : Iop_Sal32x2;
+                     op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     op_add = Q ? Iop_Add32x4 : Iop_Add32x2;
+                     op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_Sal64x2 : Iop_Sal64x1;
+                     op_sub = Q ? Iop_Sub64x2 : Iop_Sub64;
+                     op_add = Q ? Iop_Add64x2 : Iop_Add64;
+                     op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64;
+                     op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            if (Q) {
+               shval = newTemp(Ity_V128);
+            } else {
+               shval = newTemp(Ity_I64);
+            }
+            /* Only least significant byte from second argument is used.
+               Copy this byte to the whole vector element. */
+            assign(shval, binop(op_shrn,
+                                binop(op_shln,
+                                       mkexpr(arg_n),
+                                       mkU8((8 << size) - 8)),
+                                mkU8((8 << size) - 8)));
+            for (i = 0; i < size; i++) {
+               old_shval = shval;
+               shval = newTemp(Q ? Ity_V128 : Ity_I64);
+               assign(shval, binop(Q ? Iop_OrV128 : Iop_Or64,
+                                   mkexpr(old_shval),
+                                   binop(op_shln,
+                                         mkexpr(old_shval),
+                                         mkU8(8 << i))));
+            }
+            /* Compute the result */
+            if (!Q && size == 3 && U) {
+               assign(round, binop(Q ? Iop_AndV128 : Iop_And64,
+                                   binop(op,
+                                         mkexpr(arg_m),
+                                         unop(Iop_64to8,
+                                              binop(op_sub,
+                                                    mkexpr(arg_n),
+                                                    mkexpr(imm_val)))),
+                                   binop(Q ? Iop_AndV128 : Iop_And64,
+                                         mkexpr(imm_val),
+                                         binop(cmp_gt,
+                                               Q ? mkU128(0) : mkU64(0),
+                                               mkexpr(arg_n)))));
+               assign(res, binop(op_add,
+                                 binop(op,
+                                       mkexpr(arg_m),
+                                       unop(Iop_64to8, mkexpr(arg_n))),
+                                 mkexpr(round)));
+            } else {
+               assign(round, binop(Q ? Iop_AndV128 : Iop_And64,
+                                   binop(op,
+                                         mkexpr(arg_m),
+                                         binop(op_add,
+                                               mkexpr(arg_n),
+                                               mkexpr(imm_val))),
+                                   binop(Q ? Iop_AndV128 : Iop_And64,
+                                         mkexpr(imm_val),
+                                         binop(cmp_gt,
+                                               Q ? mkU128(0) : mkU64(0),
+                                               mkexpr(arg_n)))));
+               assign(res, binop(op_add,
+                                 binop(op, mkexpr(arg_m), mkexpr(arg_n)),
+                                 mkexpr(round)));
+            }
+            DIP("vrshl.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd',
+                nreg);
+         } else {
+            /* VQRSHL */
+            IROp op, op_rev, op_shrn, op_shln, cmp_neq, cmp_gt, op_sub, op_add;
+            IRTemp tmp, shval, mask, old_shval, imm_val, round;
+            UInt i;
+            ULong esize, imm;
+            cmp_neq = Q ? Iop_CmpNEZ8x16 : Iop_CmpNEZ8x8;
+            cmp_gt = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8;
+            imm = 1L;
+            switch (size) {
+               case 0: imm = (imm <<  8) | imm; /* fall through */
+               case 1: imm = (imm << 16) | imm; /* fall through */
+               case 2: imm = (imm << 32) | imm; /* fall through */
+               case 3: break;
+               default: vassert(0);
+            }
+            imm_val = newTemp(Q ? Ity_V128 : Ity_I64);
+            round = newTemp(Q ? Ity_V128 : Ity_I64);
+            assign(imm_val, Q ? mkU128(imm) : mkU64(imm));
+            if (U) {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_QShl8x16 : Iop_QShl8x8;
+                     op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     op_add = Q ? Iop_Add8x16 : Iop_Add8x8;
+                     op_rev = Q ? Iop_Shr8x16 : Iop_Shr8x8;
+                     op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_QShl16x8 : Iop_QShl16x4;
+                     op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     op_add = Q ? Iop_Add16x8 : Iop_Add16x4;
+                     op_rev = Q ? Iop_Shr16x8 : Iop_Shr16x4;
+                     op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_QShl32x4 : Iop_QShl32x2;
+                     op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     op_add = Q ? Iop_Add32x4 : Iop_Add32x2;
+                     op_rev = Q ? Iop_Shr32x4 : Iop_Shr32x2;
+                     op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_QShl64x2 : Iop_QShl64x1;
+                     op_sub = Q ? Iop_Sub64x2 : Iop_Sub64;
+                     op_add = Q ? Iop_Add64x2 : Iop_Add64;
+                     op_rev = Q ? Iop_Shr64x2 : Iop_Shr64;
+                     op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64;
+                     op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_QSal8x16 : Iop_QSal8x8;
+                     op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     op_add = Q ? Iop_Add8x16 : Iop_Add8x8;
+                     op_rev = Q ? Iop_Sar8x16 : Iop_Sar8x8;
+                     op_shrn = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     op_shln = Q ? Iop_ShlN8x16 : Iop_ShlN8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_QSal16x8 : Iop_QSal16x4;
+                     op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     op_add = Q ? Iop_Add16x8 : Iop_Add16x4;
+                     op_rev = Q ? Iop_Sar16x8 : Iop_Sar16x4;
+                     op_shrn = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     op_shln = Q ? Iop_ShlN16x8 : Iop_ShlN16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_QSal32x4 : Iop_QSal32x2;
+                     op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     op_add = Q ? Iop_Add32x4 : Iop_Add32x2;
+                     op_rev = Q ? Iop_Sar32x4 : Iop_Sar32x2;
+                     op_shrn = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     op_shln = Q ? Iop_ShlN32x4 : Iop_ShlN32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_QSal64x2 : Iop_QSal64x1;
+                     op_sub = Q ? Iop_Sub64x2 : Iop_Sub64;
+                     op_add = Q ? Iop_Add64x2 : Iop_Add64;
+                     op_rev = Q ? Iop_Sar64x2 : Iop_Sar64;
+                     op_shrn = Q ? Iop_ShrN64x2 : Iop_Shr64;
+                     op_shln = Q ? Iop_ShlN64x2 : Iop_Shl64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            if (Q) {
+               tmp = newTemp(Ity_V128);
+               shval = newTemp(Ity_V128);
+               mask = newTemp(Ity_V128);
+            } else {
+               tmp = newTemp(Ity_I64);
+               shval = newTemp(Ity_I64);
+               mask = newTemp(Ity_I64);
+            }
+            /* Only least significant byte from second argument is used.
+               Copy this byte to the whole vector element. */
+            assign(shval, binop(op_shrn,
+                                binop(op_shln,
+                                       mkexpr(arg_n),
+                                       mkU8((8 << size) - 8)),
+                                mkU8((8 << size) - 8)));
+            for (i = 0; i < size; i++) {
+               old_shval = shval;
+               shval = newTemp(Q ? Ity_V128 : Ity_I64);
+               assign(shval, binop(Q ? Iop_OrV128 : Iop_Or64,
+                                   mkexpr(old_shval),
+                                   binop(op_shln,
+                                         mkexpr(old_shval),
+                                         mkU8(8 << i))));
+            }
+            /* Compute the result */
+            assign(round, binop(Q ? Iop_AndV128 : Iop_And64,
+                                binop(op,
+                                      mkexpr(arg_m),
+                                      binop(op_add,
+                                            mkexpr(arg_n),
+                                            mkexpr(imm_val))),
+                                binop(Q ? Iop_AndV128 : Iop_And64,
+                                      mkexpr(imm_val),
+                                      binop(cmp_gt,
+                                            Q ? mkU128(0) : mkU64(0),
+                                            mkexpr(arg_n)))));
+            assign(res, binop(op_add,
+                              binop(op, mkexpr(arg_m), mkexpr(arg_n)),
+                              mkexpr(round)));
+#ifndef DISABLE_QC_FLAG
+            /* If shift is greater or equal to the element size and element is
+               non-zero, then QC flag should be set. */
+            esize = (8 << size) - 1;
+            esize = (esize <<  8) | esize;
+            esize = (esize << 16) | esize;
+            esize = (esize << 32) | esize;
+            setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64,
+                             binop(cmp_gt, mkexpr(shval),
+                                           Q ? mkU128(esize) : mkU64(esize)),
+                             unop(cmp_neq, mkexpr(arg_m))),
+                       Q ? mkU128(0) : mkU64(0),
+                       Q, condT);
+            /* Othervise QC flag should be set if shift value is positive and
+               result beign rightshifted the same value is not equal to left
+               argument. */
+            assign(mask, binop(cmp_gt, mkexpr(shval),
+                               Q ? mkU128(0) : mkU64(0)));
+            if (!Q && size == 3)
+               assign(tmp, binop(op_rev, mkexpr(res),
+                                         unop(Iop_64to8, mkexpr(arg_n))));
+            else
+               assign(tmp, binop(op_rev, mkexpr(res), mkexpr(arg_n)));
+            setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64,
+                             mkexpr(tmp), mkexpr(mask)),
+                       binop(Q ? Iop_AndV128 : Iop_And64,
+                             mkexpr(arg_m), mkexpr(mask)),
+                       Q, condT);
+#endif
+            DIP("vqrshl.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, Q ? 'q' : 'd',
+                nreg);
+         }
+         break;
+      case 6:
+         /* VMAX, VMIN  */
+         if (B == 0) {
+            /* VMAX */
+            IROp op;
+            if (U == 0) {
+               switch (size) {
+                  case 0: op = Q ? Iop_Max8Sx16 : Iop_Max8Sx8; break;
+                  case 1: op = Q ? Iop_Max16Sx8 : Iop_Max16Sx4; break;
+                  case 2: op = Q ? Iop_Max32Sx4 : Iop_Max32Sx2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0: op = Q ? Iop_Max8Ux16 : Iop_Max8Ux8; break;
+                  case 1: op = Q ? Iop_Max16Ux8 : Iop_Max16Ux4; break;
+                  case 2: op = Q ? Iop_Max32Ux4 : Iop_Max32Ux2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+            }
+            assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+            DIP("vmax.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                mreg);
+         } else {
+            /* VMIN */
+            IROp op;
+            if (U == 0) {
+               switch (size) {
+                  case 0: op = Q ? Iop_Min8Sx16 : Iop_Min8Sx8; break;
+                  case 1: op = Q ? Iop_Min16Sx8 : Iop_Min16Sx4; break;
+                  case 2: op = Q ? Iop_Min32Sx4 : Iop_Min32Sx2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0: op = Q ? Iop_Min8Sx16 : Iop_Min8Sx8; break;
+                  case 1: op = Q ? Iop_Min16Sx8 : Iop_Min16Sx4; break;
+                  case 2: op = Q ? Iop_Min32Sx4 : Iop_Min32Sx2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+            }
+            assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+            DIP("vmin.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                mreg);
+         }
+         break;
+      case 7:
+         if (B == 0) {
+            /* VABD */
+            IROp op_cmp, op_sub;
+            IRTemp cond;
+            if ((theInstr >> 23) & 1) {
+               vpanic("VABDL should not be in dis_neon_data_3same\n");
+            }
+            if (Q) {
+               switch (size) {
+                  case 0:
+                     op_cmp = U ? Iop_CmpGT8Ux16 : Iop_CmpGT8Sx16;
+                     op_sub = Iop_Sub8x16;
+                     break;
+                  case 1:
+                     op_cmp = U ? Iop_CmpGT16Ux8 : Iop_CmpGT16Sx8;
+                     op_sub = Iop_Sub16x8;
+                     break;
+                  case 2:
+                     op_cmp = U ? Iop_CmpGT32Ux4 : Iop_CmpGT32Sx4;
+                     op_sub = Iop_Sub32x4;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     op_cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8;
+                     op_sub = Iop_Sub8x8;
+                     break;
+                  case 1:
+                     op_cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4;
+                     op_sub = Iop_Sub16x4;
+                     break;
+                  case 2:
+                     op_cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2;
+                     op_sub = Iop_Sub32x2;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            }
+            if (Q) {
+               cond = newTemp(Ity_V128);
+            } else {
+               cond = newTemp(Ity_I64);
+            }
+            assign(cond, binop(op_cmp, mkexpr(arg_n), mkexpr(arg_m)));
+            assign(res, binop(Q ? Iop_OrV128 : Iop_Or64,
+                              binop(Q ? Iop_AndV128 : Iop_And64,
+                                    binop(op_sub, mkexpr(arg_n),
+                                                  mkexpr(arg_m)),
+                                    mkexpr(cond)),
+                              binop(Q ? Iop_AndV128 : Iop_And64,
+                                    binop(op_sub, mkexpr(arg_m),
+                                                  mkexpr(arg_n)),
+                                    unop(Q ? Iop_NotV128 : Iop_Not64,
+                                         mkexpr(cond)))));
+            DIP("vabd.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                mreg);
+         } else {
+            /* VABA */
+            IROp op_cmp, op_sub, op_add;
+            IRTemp cond, acc, tmp;
+            if ((theInstr >> 23) & 1) {
+               vpanic("VABAL should not be in dis_neon_data_3same");
+            }
+            if (Q) {
+               switch (size) {
+                  case 0:
+                     op_cmp = U ? Iop_CmpGT8Ux16 : Iop_CmpGT8Sx16;
+                     op_sub = Iop_Sub8x16;
+                     op_add = Iop_Add8x16;
+                     break;
+                  case 1:
+                     op_cmp = U ? Iop_CmpGT16Ux8 : Iop_CmpGT16Sx8;
+                     op_sub = Iop_Sub16x8;
+                     op_add = Iop_Add16x8;
+                     break;
+                  case 2:
+                     op_cmp = U ? Iop_CmpGT32Ux4 : Iop_CmpGT32Sx4;
+                     op_sub = Iop_Sub32x4;
+                     op_add = Iop_Add32x4;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     op_cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8;
+                     op_sub = Iop_Sub8x8;
+                     op_add = Iop_Add8x8;
+                     break;
+                  case 1:
+                     op_cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4;
+                     op_sub = Iop_Sub16x4;
+                     op_add = Iop_Add16x4;
+                     break;
+                  case 2:
+                     op_cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2;
+                     op_sub = Iop_Sub32x2;
+                     op_add = Iop_Add32x2;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            }
+            if (Q) {
+               cond = newTemp(Ity_V128);
+               acc = newTemp(Ity_V128);
+               tmp = newTemp(Ity_V128);
+               assign(acc, getQReg(dreg));
+            } else {
+               cond = newTemp(Ity_I64);
+               acc = newTemp(Ity_I64);
+               tmp = newTemp(Ity_I64);
+               assign(acc, getDRegI64(dreg));
+            }
+            assign(cond, binop(op_cmp, mkexpr(arg_n), mkexpr(arg_m)));
+            assign(tmp, binop(Q ? Iop_OrV128 : Iop_Or64,
+                              binop(Q ? Iop_AndV128 : Iop_And64,
+                                    binop(op_sub, mkexpr(arg_n),
+                                                  mkexpr(arg_m)),
+                                    mkexpr(cond)),
+                              binop(Q ? Iop_AndV128 : Iop_And64,
+                                    binop(op_sub, mkexpr(arg_m),
+                                                  mkexpr(arg_n)),
+                                    unop(Q ? Iop_NotV128 : Iop_Not64,
+                                         mkexpr(cond)))));
+            assign(res, binop(op_add, mkexpr(acc), mkexpr(tmp)));
+            DIP("vaba.%c%u %c%u, %c%u, %c%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                mreg);
+         }
+         break;
+      case 8:
+         if (B == 0) {
+            IROp op;
+            if (U == 0) {
+               /* VADD  */
+               switch (size) {
+                  case 0: op = Q ? Iop_Add8x16 : Iop_Add8x8; break;
+                  case 1: op = Q ? Iop_Add16x8 : Iop_Add16x4; break;
+                  case 2: op = Q ? Iop_Add32x4 : Iop_Add32x2; break;
+                  case 3: op = Q ? Iop_Add64x2 : Iop_Add64; break;
+                  default: vassert(0);
+               }
+               DIP("vadd.i%u %c%u, %c%u, %c%u\n",
+                   8 << size, Q ? 'q' : 'd',
+                   dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            } else {
+               /* VSUB  */
+               switch (size) {
+                  case 0: op = Q ? Iop_Sub8x16 : Iop_Sub8x8; break;
+                  case 1: op = Q ? Iop_Sub16x8 : Iop_Sub16x4; break;
+                  case 2: op = Q ? Iop_Sub32x4 : Iop_Sub32x2; break;
+                  case 3: op = Q ? Iop_Sub64x2 : Iop_Sub64; break;
+                  default: vassert(0);
+               }
+               DIP("vsub.i%u %c%u, %c%u, %c%u\n",
+                   8 << size, Q ? 'q' : 'd',
+                   dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            }
+            assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+         } else {
+            IROp op;
+            switch (size) {
+               case 0: op = Q ? Iop_CmpNEZ8x16 : Iop_CmpNEZ8x8; break;
+               case 1: op = Q ? Iop_CmpNEZ16x8 : Iop_CmpNEZ16x4; break;
+               case 2: op = Q ? Iop_CmpNEZ32x4 : Iop_CmpNEZ32x2; break;
+               case 3: op = Q ? Iop_CmpNEZ64x2 : Iop_CmpwNEZ64; break;
+               default: vassert(0);
+            }
+            if (U == 0) {
+               /* VTST  */
+               assign(res, unop(op, binop(Q ? Iop_AndV128 : Iop_And64,
+                                          mkexpr(arg_n),
+                                          mkexpr(arg_m))));
+               DIP("vtst.%u %c%u, %c%u, %c%u\n",
+                   8 << size, Q ? 'q' : 'd',
+                   dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            } else {
+               /* VCEQ  */
+               assign(res, unop(Q ? Iop_NotV128 : Iop_Not64,
+                                unop(op,
+                                     binop(Q ? Iop_XorV128 : Iop_Xor64,
+                                           mkexpr(arg_n),
+                                           mkexpr(arg_m)))));
+               DIP("vceq.i%u %c%u, %c%u, %c%u\n",
+                   8 << size, Q ? 'q' : 'd',
+                   dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            }
+         }
+         break;
+      case 9:
+         if (B == 0) {
+            /* VMLA, VMLS (integer) */
+            IROp op, op2;
+            UInt P = (theInstr >> 24) & 1;
+            if (P) {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_Mul8x16 : Iop_Mul8x8;
+                     op2 = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_Mul16x8 : Iop_Mul16x4;
+                     op2 = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_Mul32x4 : Iop_Mul32x2;
+                     op2 = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_Mul8x16 : Iop_Mul8x8;
+                     op2 = Q ? Iop_Add8x16 : Iop_Add8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_Mul16x8 : Iop_Mul16x4;
+                     op2 = Q ? Iop_Add16x8 : Iop_Add16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_Mul32x4 : Iop_Mul32x2;
+                     op2 = Q ? Iop_Add32x4 : Iop_Add32x2;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            }
+            assign(res, binop(op2,
+                              Q ? getQReg(dreg) : getDRegI64(dreg),
+                              binop(op, mkexpr(arg_n), mkexpr(arg_m))));
+            DIP("vml%c.i%u %c%u, %c%u, %c%u\n",
+                P ? 's' : 'a', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                mreg);
+         } else {
+            /* VMUL */
+            IROp op;
+            UInt P = (theInstr >> 24) & 1;
+            if (P) {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_PolynomialMul8x16 : Iop_PolynomialMul8x8;
+                     break;
+                  case 1: case 2: case 3: return False;
+                  default: vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0: op = Q ? Iop_Mul8x16 : Iop_Mul8x8; break;
+                  case 1: op = Q ? Iop_Mul16x8 : Iop_Mul16x4; break;
+                  case 2: op = Q ? Iop_Mul32x4 : Iop_Mul32x2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+            }
+            assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+            DIP("vmul.%c%u %c%u, %c%u, %c%u\n",
+                P ? 'p' : 'i', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd',
+                mreg);
+         }
+         break;
+      case 10: {
+         /* VPMAX, VPMIN  */
+         UInt P = (theInstr >> 4) & 1;
+         IROp op;
+         if (Q)
+            return False;
+         if (P) {
+            switch (size) {
+               case 0: op = U ? Iop_PwMin8Ux8  : Iop_PwMin8Sx8; break;
+               case 1: op = U ? Iop_PwMin16Ux4 : Iop_PwMin16Sx4; break;
+               case 2: op = U ? Iop_PwMin32Ux2 : Iop_PwMin32Sx2; break;
+               case 3: return False;
+               default: vassert(0);
+            }
+         } else {
+            switch (size) {
+               case 0: op = U ? Iop_PwMax8Ux8  : Iop_PwMax8Sx8; break;
+               case 1: op = U ? Iop_PwMax16Ux4 : Iop_PwMax16Sx4; break;
+               case 2: op = U ? Iop_PwMax32Ux2 : Iop_PwMax32Sx2; break;
+               case 3: return False;
+               default: vassert(0);
+            }
+         }
+         assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+         DIP("vp%s.%c%u %c%u, %c%u, %c%u\n",
+             P ? "min" : "max", U ? 'u' : 's',
+             8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg,
+             Q ? 'q' : 'd', mreg);
+         break;
+      }
+      case 11:
+         if (B == 0) {
+            if (U == 0) {
+               /* VQDMULH  */
+               IROp op ,op2;
+               ULong imm;
+               switch (size) {
+                  case 0: case 3:
+                     return False;
+                  case 1:
+                     op = Q ? Iop_QDMulHi16Sx8 : Iop_QDMulHi16Sx4;
+                     op2 = Q ? Iop_CmpEQ16x8 : Iop_CmpEQ16x4;
+                     imm = 1LL << 15;
+                     imm = (imm << 16) | imm;
+                     imm = (imm << 32) | imm;
+                     break;
+                  case 2:
+                     op = Q ? Iop_QDMulHi32Sx4 : Iop_QDMulHi32Sx2;
+                     op2 = Q ? Iop_CmpEQ32x4 : Iop_CmpEQ32x2;
+                     imm = 1LL << 31;
+                     imm = (imm << 32) | imm;
+                     break;
+                  default:
+                     vassert(0);
+               }
+               assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+#ifndef DISABLE_QC_FLAG
+               setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64,
+                                binop(op2, mkexpr(arg_n),
+                                           Q ? mkU128(imm) : mkU64(imm)),
+                                binop(op2, mkexpr(arg_m),
+                                           Q ? mkU128(imm) : mkU64(imm))),
+                          Q ? mkU128(0) : mkU64(0),
+                          Q, condT);
+#endif
+               DIP("vqdmulh.s%u %c%u, %c%u, %c%u\n",
+                   8 << size, Q ? 'q' : 'd',
+                   dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            } else {
+               /* VQRDMULH */
+               IROp op ,op2;
+               ULong imm;
+               switch(size) {
+                  case 0: case 3:
+                     return False;
+                  case 1:
+                     imm = 1LL << 15;
+                     imm = (imm << 16) | imm;
+                     imm = (imm << 32) | imm;
+                     op = Q ? Iop_QRDMulHi16Sx8 : Iop_QRDMulHi16Sx4;
+                     op2 = Q ? Iop_CmpEQ16x8 : Iop_CmpEQ16x4;
+                     break;
+                  case 2:
+                     imm = 1LL << 31;
+                     imm = (imm << 32) | imm;
+                     op = Q ? Iop_QRDMulHi32Sx4 : Iop_QRDMulHi32Sx2;
+                     op2 = Q ? Iop_CmpEQ32x4 : Iop_CmpEQ32x2;
+                     break;
+                  default:
+                     vassert(0);
+               }
+               assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+#ifndef DISABLE_QC_FLAG
+               setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64,
+                                binop(op2, mkexpr(arg_n),
+                                           Q ? mkU128(imm) : mkU64(imm)),
+                                binop(op2, mkexpr(arg_m),
+                                           Q ? mkU128(imm) : mkU64(imm))),
+                          Q ? mkU128(0) : mkU64(0),
+                          Q, condT);
+#endif
+               DIP("vqrdmulh.s%u %c%u, %c%u, %c%u\n",
+                   8 << size, Q ? 'q' : 'd',
+                   dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            }
+         } else {
+            if (U == 0) {
+               /* VPADD */
+               IROp op;
+               if (Q)
+                  return False;
+               switch (size) {
+                  case 0: op = Q ? Iop_PwAdd8x16 : Iop_PwAdd8x8;  break;
+                  case 1: op = Q ? Iop_PwAdd16x8 : Iop_PwAdd16x4; break;
+                  case 2: op = Q ? Iop_PwAdd32x4 : Iop_PwAdd32x2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+               assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+               DIP("vpadd.i%d %c%u, %c%u, %c%u\n",
+                   8 << size, Q ? 'q' : 'd',
+                   dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            }
+         }
+         break;
+      /* Starting from here these are FP SIMD cases */
+      case 13:
+         if (B == 0) {
+            IROp op;
+            if (U == 0) {
+               if ((C >> 1) == 0) {
+                  /* VADD  */
+                  op = Q ? Iop_Add32Fx4 : Iop_Add32Fx2 ;
+                  DIP("vadd.f32 %c%u, %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               } else {
+                  /* VSUB  */
+                  op = Q ? Iop_Sub32Fx4 : Iop_Sub32Fx2 ;
+                  DIP("vsub.f32 %c%u, %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               }
+            } else {
+               if ((C >> 1) == 0) {
+                  /* VPADD */
+                  if (Q)
+                     return False;
+                  op = Iop_PwAdd32Fx2;
+                  DIP("vpadd.f32 d%u, d%u, d%u\n", dreg, nreg, mreg);
+               } else {
+                  /* VABD  */
+                  if (Q) {
+                     assign(res, unop(Iop_Abs32Fx4,
+                                      binop(Iop_Sub32Fx4,
+                                            mkexpr(arg_n),
+                                            mkexpr(arg_m))));
+                  } else {
+                     assign(res, unop(Iop_Abs32Fx2,
+                                      binop(Iop_Sub32Fx2,
+                                            mkexpr(arg_n),
+                                            mkexpr(arg_m))));
+                  }
+                  DIP("vabd.f32 %c%u, %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+                  break;
+               }
+            }
+            assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+         } else {
+            if (U == 0) {
+               /* VMLA, VMLS  */
+               IROp op, op2;
+               UInt P = (theInstr >> 21) & 1;
+               if (P) {
+                  switch (size & 1) {
+                     case 0:
+                        op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2;
+                        op2 = Q ? Iop_Sub32Fx4 : Iop_Sub32Fx2;
+                        break;
+                     case 1: return False;
+                     default: vassert(0);
+                  }
+               } else {
+                  switch (size & 1) {
+                     case 0:
+                        op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2;
+                        op2 = Q ? Iop_Add32Fx4 : Iop_Add32Fx2;
+                        break;
+                     case 1: return False;
+                     default: vassert(0);
+                  }
+               }
+               assign(res, binop(op2,
+                                 Q ? getQReg(dreg) : getDRegI64(dreg),
+                                 binop(op, mkexpr(arg_n), mkexpr(arg_m))));
+
+               DIP("vml%c.f32 %c%u, %c%u, %c%u\n",
+                   P ? 's' : 'a', Q ? 'q' : 'd',
+                   dreg, Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            } else {
+               /* VMUL  */
+               IROp op;
+               if ((C >> 1) != 0)
+                  return False;
+               op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2 ;
+               assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+               DIP("vmul.f32 %c%u, %c%u, %c%u\n",
+                   Q ? 'q' : 'd', dreg,
+                   Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+            }
+         }
+         break;
+      case 14:
+         if (B == 0) {
+            if (U == 0) {
+               if ((C >> 1) == 0) {
+                  /* VCEQ  */
+                  IROp op;
+                  if ((theInstr >> 20) & 1)
+                     return False;
+                  op = Q ? Iop_CmpEQ32Fx4 : Iop_CmpEQ32Fx2;
+                  assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+                  DIP("vceq.f32 %c%u, %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               } else {
+                  return False;
+               }
+            } else {
+               if ((C >> 1) == 0) {
+                  /* VCGE  */
+                  IROp op;
+                  if ((theInstr >> 20) & 1)
+                     return False;
+                  op = Q ? Iop_CmpGE32Fx4 : Iop_CmpGE32Fx2;
+                  assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+                  DIP("vcge.f32 %c%u, %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               } else {
+                  /* VCGT  */
+                  IROp op;
+                  if ((theInstr >> 20) & 1)
+                     return False;
+                  op = Q ? Iop_CmpGT32Fx4 : Iop_CmpGT32Fx2;
+                  assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+                  DIP("vcgt.f32 %c%u, %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               }
+            }
+         } else {
+            if (U == 1) {
+               /* VACGE, VACGT */
+               UInt op_bit = (theInstr >> 21) & 1;
+               IROp op, op2;
+               op2 = Q ? Iop_Abs32Fx4 : Iop_Abs32Fx2;
+               if (op_bit) {
+                  op = Q ? Iop_CmpGT32Fx4 : Iop_CmpGT32Fx2;
+                  assign(res, binop(op,
+                                    unop(op2, mkexpr(arg_n)),
+                                    unop(op2, mkexpr(arg_m))));
+               } else {
+                  op = Q ? Iop_CmpGE32Fx4 : Iop_CmpGE32Fx2;
+                  assign(res, binop(op,
+                                    unop(op2, mkexpr(arg_n)),
+                                    unop(op2, mkexpr(arg_m))));
+               }
+               DIP("vacg%c.f32 %c%u, %c%u, %c%u\n", op_bit ? 't' : 'e',
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg,
+                   Q ? 'q' : 'd', mreg);
+            }
+         }
+         break;
+      case 15:
+         if (B == 0) {
+            if (U == 0) {
+               /* VMAX, VMIN  */
+               IROp op;
+               if ((theInstr >> 20) & 1)
+                  return False;
+               if ((theInstr >> 21) & 1) {
+                  op = Q ? Iop_Min32Fx4 : Iop_Min32Fx2;
+                  DIP("vmin.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               } else {
+                  op = Q ? Iop_Max32Fx4 : Iop_Max32Fx2;
+                  DIP("vmax.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               }
+               assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+            } else {
+               /* VPMAX, VPMIN   */
+               IROp op;
+               if (Q)
+                  return False;
+               if ((theInstr >> 20) & 1)
+                  return False;
+               if ((theInstr >> 21) & 1) {
+                  op = Iop_PwMin32Fx2;
+                  DIP("vpmin.f32 d%u, d%u, d%u\n", dreg, nreg, mreg);
+               } else {
+                  op = Iop_PwMax32Fx2;
+                  DIP("vpmax.f32 d%u, d%u, d%u\n", dreg, nreg, mreg);
+               }
+               assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+            }
+         } else {
+            if (U == 0) {
+               if ((C >> 1) == 0) {
+                  /* VRECPS */
+                  if ((theInstr >> 20) & 1)
+                     return False;
+                  assign(res, binop(Q ? Iop_Recps32Fx4 : Iop_Recps32Fx2,
+                                    mkexpr(arg_n),
+                                    mkexpr(arg_m)));
+                  DIP("vrecps.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               } else {
+                  /* VRSQRTS  */
+                  if ((theInstr >> 20) & 1)
+                     return False;
+                  assign(res, binop(Q ? Iop_Rsqrts32Fx4 : Iop_Rsqrts32Fx2,
+                                    mkexpr(arg_n),
+                                    mkexpr(arg_m)));
+                  DIP("vrsqrts.f32 %c%u, %c%u, %c%u\n", Q ? 'q' : 'd', dreg,
+                      Q ? 'q' : 'd', nreg, Q ? 'q' : 'd', mreg);
+               }
+            }
+         }
+         break;
+   }
+
+   if (Q) {
+      putQReg(dreg, mkexpr(res), condT);
+   } else {
+      putDRegI64(dreg, mkexpr(res), condT);
+   }
+
+   return True;
+}
+
+/* A7.4.2 Three registers of different length */
+static
+Bool dis_neon_data_3diff ( UInt theInstr, IRTemp condT )
+{
+   UInt A = (theInstr >> 8) & 0xf;
+   UInt B = (theInstr >> 20) & 3;
+   UInt U = (theInstr >> 24) & 1;
+   UInt P = (theInstr >> 9) & 1;
+   UInt mreg = get_neon_m_regno(theInstr);
+   UInt nreg = get_neon_n_regno(theInstr);
+   UInt dreg = get_neon_d_regno(theInstr);
+   UInt size = B;
+   ULong imm;
+   IRTemp res, arg_m, arg_n, cond, tmp;
+   IROp cvt, cvt2, cmp, op, op2, sh, add;
+   switch (A) {
+      case 0: case 1: case 2: case 3:
+         /* VADDL, VADDW, VSUBL, VSUBW */
+         if (dreg & 1)
+            return False;
+         dreg >>= 1;
+         size = B;
+         switch (size) {
+            case 0:
+               cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
+               op = (A & 2) ? Iop_Sub16x8 : Iop_Add16x8;
+               break;
+            case 1:
+               cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
+               op = (A & 2) ? Iop_Sub32x4 : Iop_Add32x4;
+               break;
+            case 2:
+               cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
+               op = (A & 2) ? Iop_Sub64x2 : Iop_Add64x2;
+               break;
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         arg_n = newTemp(Ity_V128);
+         arg_m = newTemp(Ity_V128);
+         if (A & 1) {
+            if (nreg & 1)
+               return False;
+            nreg >>= 1;
+            assign(arg_n, getQReg(nreg));
+         } else {
+            assign(arg_n, unop(cvt, getDRegI64(nreg)));
+         }
+         assign(arg_m, unop(cvt, getDRegI64(mreg)));
+         putQReg(dreg, binop(op, mkexpr(arg_n), mkexpr(arg_m)),
+                       condT);
+         DIP("v%s%c.%c%u q%u, %c%u, d%u\n", (A & 2) ? "sub" : "add",
+             (A & 1) ? 'w' : 'l', U ? 'u' : 's', 8 << size, dreg,
+             (A & 1) ? 'q' : 'd', nreg, mreg);
+         return True;
+      case 4:
+         /* VADDHN, VRADDHN */
+         if (mreg & 1)
+            return False;
+         mreg >>= 1;
+         if (nreg & 1)
+            return False;
+         nreg >>= 1;
+         size = B;
+         switch (size) {
+            case 0:
+               op = Iop_Add16x8;
+               cvt = Iop_Shorten16x8;
+               sh = Iop_ShrN16x8;
+               imm = 1U << 7;
+               imm = (imm << 16) | imm;
+               imm = (imm << 32) | imm;
+               break;
+            case 1:
+               op = Iop_Add32x4;
+               cvt = Iop_Shorten32x4;
+               sh = Iop_ShrN32x4;
+               imm = 1U << 15;
+               imm = (imm << 32) | imm;
+               break;
+            case 2:
+               op = Iop_Add64x2;
+               cvt = Iop_Shorten64x2;
+               sh = Iop_ShrN64x2;
+               imm = 1U << 31;
+               break;
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         tmp = newTemp(Ity_V128);
+         res = newTemp(Ity_V128);
+         assign(tmp, binop(op, getQReg(nreg), getQReg(mreg)));
+         if (U) {
+            /* VRADDHN */
+            assign(res, binop(op, mkexpr(tmp),
+                     binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm))));
+         } else {
+            assign(res, mkexpr(tmp));
+         }
+         putDRegI64(dreg, unop(cvt, binop(sh, mkexpr(res), mkU8(8 << size))),
+                    condT);
+         DIP("v%saddhn.i%u d%u, q%u, q%u\n", U ? "r" : "", 16 << size, dreg,
+             nreg, mreg);
+         return True;
+      case 5:
+         /* VABAL */
+         if (!((theInstr >> 23) & 1)) {
+            vpanic("VABA should not be in dis_neon_data_3diff\n");
+         }
+         if (dreg & 1)
+            return False;
+         dreg >>= 1;
+         switch (size) {
+            case 0:
+               cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8;
+               cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
+               cvt2 = Iop_Longen8Sx8;
+               op = Iop_Sub16x8;
+               op2 = Iop_Add16x8;
+               break;
+            case 1:
+               cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4;
+               cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
+               cvt2 = Iop_Longen16Sx4;
+               op = Iop_Sub32x4;
+               op2 = Iop_Add32x4;
+               break;
+            case 2:
+               cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2;
+               cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
+               cvt2 = Iop_Longen32Sx2;
+               op = Iop_Sub64x2;
+               op2 = Iop_Add64x2;
+               break;
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         arg_n = newTemp(Ity_V128);
+         arg_m = newTemp(Ity_V128);
+         cond = newTemp(Ity_V128);
+         res = newTemp(Ity_V128);
+         assign(arg_n, unop(cvt, getDRegI64(nreg)));
+         assign(arg_m, unop(cvt, getDRegI64(mreg)));
+         assign(cond, unop(cvt2, binop(cmp, getDRegI64(nreg),
+                                            getDRegI64(mreg))));
+         assign(res, binop(op2,
+                           binop(Iop_OrV128,
+                                 binop(Iop_AndV128,
+                                       binop(op, mkexpr(arg_n), mkexpr(arg_m)),
+                                       mkexpr(cond)),
+                                 binop(Iop_AndV128,
+                                       binop(op, mkexpr(arg_m), mkexpr(arg_n)),
+                                       unop(Iop_NotV128, mkexpr(cond)))),
+                           getQReg(dreg)));
+         putQReg(dreg, mkexpr(res), condT);
+         DIP("vabal.%c%u q%u, d%u, d%u\n", U ? 'u' : 's', 8 << size, dreg,
+             nreg, mreg);
+         return True;
+      case 6:
+         /* VSUBHN, VRSUBHN */
+         if (mreg & 1)
+            return False;
+         mreg >>= 1;
+         if (nreg & 1)
+            return False;
+         nreg >>= 1;
+         size = B;
+         switch (size) {
+            case 0:
+               op = Iop_Sub16x8;
+               op2 = Iop_Add16x8;
+               cvt = Iop_Shorten16x8;
+               sh = Iop_ShrN16x8;
+               imm = 1U << 7;
+               imm = (imm << 16) | imm;
+               imm = (imm << 32) | imm;
+               break;
+            case 1:
+               op = Iop_Sub32x4;
+               op2 = Iop_Add32x4;
+               cvt = Iop_Shorten32x4;
+               sh = Iop_ShrN32x4;
+               imm = 1U << 15;
+               imm = (imm << 32) | imm;
+               break;
+            case 2:
+               op = Iop_Sub64x2;
+               op2 = Iop_Add64x2;
+               cvt = Iop_Shorten64x2;
+               sh = Iop_ShrN64x2;
+               imm = 1U << 31;
+               break;
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         tmp = newTemp(Ity_V128);
+         res = newTemp(Ity_V128);
+         assign(tmp, binop(op, getQReg(nreg), getQReg(mreg)));
+         if (U) {
+            /* VRSUBHN */
+            assign(res, binop(op2, mkexpr(tmp),
+                     binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm))));
+         } else {
+            assign(res, mkexpr(tmp));
+         }
+         putDRegI64(dreg, unop(cvt, binop(sh, mkexpr(res), mkU8(8 << size))),
+                    condT);
+         DIP("v%ssubhn.i%u d%u, q%u, q%u\n", U ? "r" : "", 16 << size, dreg,
+             nreg, mreg);
+         return True;
+      case 7:
+         /* VABDL */
+         if (!((theInstr >> 23) & 1)) {
+            vpanic("VABL should not be in dis_neon_data_3diff\n");
+         }
+         if (dreg & 1)
+            return False;
+         dreg >>= 1;
+         switch (size) {
+            case 0:
+               cmp = U ? Iop_CmpGT8Ux8 : Iop_CmpGT8Sx8;
+               cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
+               cvt2 = Iop_Longen8Sx8;
+               op = Iop_Sub16x8;
+               break;
+            case 1:
+               cmp = U ? Iop_CmpGT16Ux4 : Iop_CmpGT16Sx4;
+               cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
+               cvt2 = Iop_Longen16Sx4;
+               op = Iop_Sub32x4;
+               break;
+            case 2:
+               cmp = U ? Iop_CmpGT32Ux2 : Iop_CmpGT32Sx2;
+               cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
+               cvt2 = Iop_Longen32Sx2;
+               op = Iop_Sub64x2;
+               break;
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         arg_n = newTemp(Ity_V128);
+         arg_m = newTemp(Ity_V128);
+         cond = newTemp(Ity_V128);
+         res = newTemp(Ity_V128);
+         assign(arg_n, unop(cvt, getDRegI64(nreg)));
+         assign(arg_m, unop(cvt, getDRegI64(mreg)));
+         assign(cond, unop(cvt2, binop(cmp, getDRegI64(nreg),
+                                            getDRegI64(mreg))));
+         assign(res, binop(Iop_OrV128,
+                           binop(Iop_AndV128,
+                                 binop(op, mkexpr(arg_n), mkexpr(arg_m)),
+                                 mkexpr(cond)),
+                           binop(Iop_AndV128,
+                                 binop(op, mkexpr(arg_m), mkexpr(arg_n)),
+                                 unop(Iop_NotV128, mkexpr(cond)))));
+         putQReg(dreg, mkexpr(res), condT);
+         DIP("vabdl.%c%u q%u, d%u, d%u\n", U ? 'u' : 's', 8 << size, dreg,
+             nreg, mreg);
+         return True;
+      case 8:
+      case 10:
+         /* VMLAL, VMLSL (integer) */
+         if (dreg & 1)
+            return False;
+         dreg >>= 1;
+         size = B;
+         switch (size) {
+            case 0:
+               op = U ? Iop_Mull8Ux8 : Iop_Mull8Sx8;
+               op2 = P ? Iop_Sub16x8 : Iop_Add16x8;
+               break;
+            case 1:
+               op = U ? Iop_Mull16Ux4 : Iop_Mull16Sx4;
+               op2 = P ? Iop_Sub32x4 : Iop_Add32x4;
+               break;
+            case 2:
+               op = U ? Iop_Mull32Ux2 : Iop_Mull32Sx2;
+               op2 = P ? Iop_Sub64x2 : Iop_Add64x2;
+               break;
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         res = newTemp(Ity_V128);
+         assign(res, binop(op, getDRegI64(nreg),getDRegI64(mreg)));
+         putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)), condT);
+         DIP("vml%cl.%c%u q%u, d%u, d%u\n", P ? 's' : 'a', U ? 'u' : 's',
+             8 << size, dreg, nreg, mreg);
+         return True;
+      case 9:
+      case 11:
+         /* VQDMLAL, VQDMLSL */
+         if (U)
+            return False;
+         if (dreg & 1)
+            return False;
+         dreg >>= 1;
+         size = B;
+         switch (size) {
+            case 0: case 3:
+               return False;
+            case 1:
+               op = Iop_QDMulLong16Sx4;
+               cmp = Iop_CmpEQ16x4;
+               add = P ? Iop_QSub32Sx4 : Iop_QAdd32Sx4;
+               op2 = P ? Iop_Sub32x4 : Iop_Add32x4;
+               imm = 1LL << 15;
+               imm = (imm << 16) | imm;
+               imm = (imm << 32) | imm;
+               break;
+            case 2:
+               op = Iop_QDMulLong32Sx2;
+               cmp = Iop_CmpEQ32x2;
+               add = P ? Iop_QSub64Sx2 : Iop_QAdd64Sx2;
+               op2 = P ? Iop_Sub64x2 : Iop_Add64x2;
+               imm = 1LL << 31;
+               imm = (imm << 32) | imm;
+               break;
+            default:
+               vassert(0);
+         }
+         res = newTemp(Ity_V128);
+         tmp = newTemp(Ity_V128);
+         assign(res, binop(op, getDRegI64(nreg), getDRegI64(mreg)));
+#ifndef DISABLE_QC_FLAG
+         assign(tmp, binop(op2, getQReg(dreg), mkexpr(res)));
+         setFlag_QC(mkexpr(tmp), binop(add, getQReg(dreg), mkexpr(res)),
+                    True, condT);
+         setFlag_QC(binop(Iop_And64,
+                          binop(cmp, getDRegI64(nreg), mkU64(imm)),
+                          binop(cmp, getDRegI64(mreg), mkU64(imm))),
+                    mkU64(0),
+                    False, condT);
+#endif
+         putQReg(dreg, binop(add, getQReg(dreg), mkexpr(res)), condT);
+         DIP("vqdml%cl.s%u q%u, d%u, d%u\n", P ? 's' : 'a', 8 << size, dreg,
+             nreg, mreg);
+         return True;
+      case 12:
+      case 14:
+         /* VMULL (integer or polynomial) */
+         if (dreg & 1)
+            return False;
+         dreg >>= 1;
+         size = B;
+         switch (size) {
+            case 0:
+               op = (U) ? Iop_Mull8Ux8 : Iop_Mull8Sx8;
+               if (P)
+                  op = Iop_PolynomialMull8x8;
+               break;
+            case 1:
+               op = (U) ? Iop_Mull16Ux4 : Iop_Mull16Sx4;
+               break;
+            case 2:
+               op = (U) ? Iop_Mull32Ux2 : Iop_Mull32Sx2;
+               break;
+            default:
+               vassert(0);
+         }
+         putQReg(dreg, binop(op, getDRegI64(nreg),
+                                 getDRegI64(mreg)), condT);
+         DIP("vmull.%c%u q%u, d%u, d%u\n", P ? 'p' : (U ? 'u' : 's'),
+               8 << size, dreg, nreg, mreg);
+         return True;
+      case 13:
+         /* VQDMULL */
+         if (U)
+            return False;
+         if (dreg & 1)
+            return False;
+         dreg >>= 1;
+         size = B;
+         switch (size) {
+            case 0:
+            case 3:
+               return False;
+            case 1:
+               op = Iop_QDMulLong16Sx4;
+               op2 = Iop_CmpEQ16x4;
+               imm = 1LL << 15;
+               imm = (imm << 16) | imm;
+               imm = (imm << 32) | imm;
+               break;
+            case 2:
+               op = Iop_QDMulLong32Sx2;
+               op2 = Iop_CmpEQ32x2;
+               imm = 1LL << 31;
+               imm = (imm << 32) | imm;
+               break;
+            default:
+               vassert(0);
+         }
+         putQReg(dreg, binop(op, getDRegI64(nreg), getDRegI64(mreg)),
+               condT);
+#ifndef DISABLE_QC_FLAG
+         setFlag_QC(binop(Iop_And64,
+                          binop(op2, getDRegI64(nreg), mkU64(imm)),
+                          binop(op2, getDRegI64(mreg), mkU64(imm))),
+                    mkU64(0),
+                    False, condT);
+#endif
+         DIP("vqdmull.s%u q%u, d%u, d%u\n", 8 << size, dreg, nreg, mreg);
+         return True;
+      default:
+         return False;
+   }
+   return False;
+}
+
+/* A7.4.3 Two registers and a scalar */
+static
+Bool dis_neon_data_2reg_and_scalar ( UInt theInstr, IRTemp condT )
+{
+#  define INSN(_bMax,_bMin)  SLICE_UInt(theInstr, (_bMax), (_bMin))
+   UInt U = INSN(24,24);
+   UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6));
+   UInt nreg = get_neon_n_regno(theInstr & ~(1 << 6));
+   UInt mreg = get_neon_m_regno(theInstr & ~(1 << 6));
+   UInt size = INSN(21,20);
+   UInt index;
+   UInt Q = INSN(24,24);
+
+   if (INSN(27,25) != 1 || INSN(23,23) != 1
+       || INSN(6,6) != 1 || INSN(4,4) != 0)
+      return False;
+
+   /* VMLA, VMLS (scalar)  */
+   if ((INSN(11,8) & BITS4(1,0,1,0)) == BITS4(0,0,0,0)) {
+      IRTemp res, arg_m, arg_n;
+      IROp dup, get, op, op2, add, sub;
+      if (Q) {
+         if ((dreg & 1) || (nreg & 1))
+            return False;
+         dreg >>= 1;
+         nreg >>= 1;
+         res = newTemp(Ity_V128);
+         arg_m = newTemp(Ity_V128);
+         arg_n = newTemp(Ity_V128);
+         assign(arg_n, getQReg(nreg));
+         switch(size) {
+            case 1:
+               dup = Iop_Dup16x8;
+               get = Iop_GetElem16x4;
+               index = mreg >> 3;
+               mreg &= 7;
+               break;
+            case 2:
+               dup = Iop_Dup32x4;
+               get = Iop_GetElem32x2;
+               index = mreg >> 4;
+               mreg &= 0xf;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      } else {
+         res = newTemp(Ity_I64);
+         arg_m = newTemp(Ity_I64);
+         arg_n = newTemp(Ity_I64);
+         assign(arg_n, getDRegI64(nreg));
+         switch(size) {
+            case 1:
+               dup = Iop_Dup16x4;
+               get = Iop_GetElem16x4;
+               index = mreg >> 3;
+               mreg &= 7;
+               break;
+            case 2:
+               dup = Iop_Dup32x2;
+               get = Iop_GetElem32x2;
+               index = mreg >> 4;
+               mreg &= 0xf;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      }
+      if (INSN(8,8)) {
+         switch (size) {
+            case 2:
+               op = Q ? Iop_Mul32Fx4 : Iop_Mul32Fx2;
+               add = Q ? Iop_Add32Fx4 : Iop_Add32Fx2;
+               sub = Q ? Iop_Sub32Fx4 : Iop_Sub32Fx2;
+               break;
+            case 0:
+            case 1:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+      } else {
+         switch (size) {
+            case 1:
+               op = Q ? Iop_Mul16x8 : Iop_Mul16x4;
+               add = Q ? Iop_Add16x8 : Iop_Add16x4;
+               sub = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+               break;
+            case 2:
+               op = Q ? Iop_Mul32x4 : Iop_Mul32x2;
+               add = Q ? Iop_Add32x4 : Iop_Add32x2;
+               sub = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+      }
+      op2 = INSN(10,10) ? sub : add;
+      assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+      if (Q)
+         putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)),
+               condT);
+      else
+         putDRegI64(dreg, binop(op2, getDRegI64(dreg), mkexpr(res)),
+                    condT);
+      DIP("vml%c.%c%u %c%u, %c%u, d%u[%u]\n", INSN(10,10) ? 's' : 'a',
+            INSN(8,8) ? 'f' : 'i', 8 << size,
+            Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', nreg, mreg, index);
+      return True;
+   }
+
+   /* VMLAL, VMLSL (scalar)   */
+   if ((INSN(11,8) & BITS4(1,0,1,1)) == BITS4(0,0,1,0)) {
+      IRTemp res, arg_m, arg_n;
+      IROp dup, get, op, op2, add, sub;
+      if (dreg & 1)
+         return False;
+      dreg >>= 1;
+      res = newTemp(Ity_V128);
+      arg_m = newTemp(Ity_I64);
+      arg_n = newTemp(Ity_I64);
+      assign(arg_n, getDRegI64(nreg));
+      switch(size) {
+         case 1:
+            dup = Iop_Dup16x4;
+            get = Iop_GetElem16x4;
+            index = mreg >> 3;
+            mreg &= 7;
+            break;
+         case 2:
+            dup = Iop_Dup32x2;
+            get = Iop_GetElem32x2;
+            index = mreg >> 4;
+            mreg &= 0xf;
+            break;
+         case 0:
+         case 3:
+            return False;
+         default:
+            vassert(0);
+      }
+      assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      switch (size) {
+         case 1:
+            op = U ? Iop_Mull16Ux4 : Iop_Mull16Sx4;
+            add = Iop_Add32x4;
+            sub = Iop_Sub32x4;
+            break;
+         case 2:
+            op = U ? Iop_Mull32Ux2 : Iop_Mull32Sx2;
+            add = Iop_Add64x2;
+            sub = Iop_Sub64x2;
+            break;
+         case 0:
+         case 3:
+            return False;
+         default:
+            vassert(0);
+      }
+      op2 = INSN(10,10) ? sub : add;
+      assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+      putQReg(dreg, binop(op2, getQReg(dreg), mkexpr(res)), condT);
+      DIP("vml%cl.%c%u q%u, d%u, d%u[%u]\n",
+          INSN(10,10) ? 's' : 'a', U ? 'u' : 's',
+          8 << size, dreg, nreg, mreg, index);
+      return True;
+   }
+
+   /* VQDMLAL, VQDMLSL (scalar)  */
+   if ((INSN(11,8) & BITS4(1,0,1,1)) == BITS4(0,0,1,1) && !U) {
+      IRTemp res, arg_m, arg_n, tmp;
+      IROp dup, get, op, op2, add, cmp;
+      UInt P = INSN(10,10);
+      ULong imm;
+      if (dreg & 1)
+         return False;
+      dreg >>= 1;
+      res = newTemp(Ity_V128);
+      arg_m = newTemp(Ity_I64);
+      arg_n = newTemp(Ity_I64);
+      assign(arg_n, getDRegI64(nreg));
+      switch(size) {
+         case 1:
+            dup = Iop_Dup16x4;
+            get = Iop_GetElem16x4;
+            index = mreg >> 3;
+            mreg &= 7;
+            break;
+         case 2:
+            dup = Iop_Dup32x2;
+            get = Iop_GetElem32x2;
+            index = mreg >> 4;
+            mreg &= 0xf;
+            break;
+         case 0:
+         case 3:
+            return False;
+         default:
+            vassert(0);
+      }
+      assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      switch (size) {
+         case 0:
+         case 3:
+            return False;
+         case 1:
+            op = Iop_QDMulLong16Sx4;
+            cmp = Iop_CmpEQ16x4;
+            add = P ? Iop_QSub32Sx4 : Iop_QAdd32Sx4;
+            op2 = P ? Iop_Sub32x4 : Iop_Add32x4;
+            imm = 1LL << 15;
+            imm = (imm << 16) | imm;
+            imm = (imm << 32) | imm;
+            break;
+         case 2:
+            op = Iop_QDMulLong32Sx2;
+            cmp = Iop_CmpEQ32x2;
+            add = P ? Iop_QSub64Sx2 : Iop_QAdd64Sx2;
+            op2 = P ? Iop_Sub64x2 : Iop_Add64x2;
+            imm = 1LL << 31;
+            imm = (imm << 32) | imm;
+            break;
+         default:
+            vassert(0);
+      }
+      res = newTemp(Ity_V128);
+      tmp = newTemp(Ity_V128);
+      assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+#ifndef DISABLE_QC_FLAG
+      assign(tmp, binop(op2, getQReg(dreg), mkexpr(res)));
+      setFlag_QC(binop(Iop_And64,
+                       binop(cmp, mkexpr(arg_n), mkU64(imm)),
+                       binop(cmp, mkexpr(arg_m), mkU64(imm))),
+                 mkU64(0),
+                 False, condT);
+      setFlag_QC(mkexpr(tmp), binop(add, getQReg(dreg), mkexpr(res)),
+                 True, condT);
+#endif
+      putQReg(dreg, binop(add, getQReg(dreg), mkexpr(res)), condT);
+      DIP("vqdml%cl.s%u q%u, d%u, d%u[%u]\n", P ? 's' : 'a', 8 << size,
+          dreg, nreg, mreg, index);
+      return True;
+   }
+
+   /* VMUL (by scalar)  */
+   if ((INSN(11,8) & BITS4(1,1,1,0)) == BITS4(1,0,0,0)) {
+      IRTemp res, arg_m, arg_n;
+      IROp dup, get, op;
+      if (Q) {
+         if ((dreg & 1) || (nreg & 1))
+            return False;
+         dreg >>= 1;
+         nreg >>= 1;
+         res = newTemp(Ity_V128);
+         arg_m = newTemp(Ity_V128);
+         arg_n = newTemp(Ity_V128);
+         assign(arg_n, getQReg(nreg));
+         switch(size) {
+            case 1:
+               dup = Iop_Dup16x8;
+               get = Iop_GetElem16x4;
+               index = mreg >> 3;
+               mreg &= 7;
+               break;
+            case 2:
+               dup = Iop_Dup32x4;
+               get = Iop_GetElem32x2;
+               index = mreg >> 4;
+               mreg &= 0xf;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      } else {
+         res = newTemp(Ity_I64);
+         arg_m = newTemp(Ity_I64);
+         arg_n = newTemp(Ity_I64);
+         assign(arg_n, getDRegI64(nreg));
+         switch(size) {
+            case 1:
+               dup = Iop_Dup16x4;
+               get = Iop_GetElem16x4;
+               index = mreg >> 3;
+               mreg &= 7;
+               break;
+            case 2:
+               dup = Iop_Dup32x2;
+               get = Iop_GetElem32x2;
+               index = mreg >> 4;
+               mreg &= 0xf;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      }
+      switch (size) {
+         case 1:
+            op = Q ? Iop_Mul16x8 : Iop_Mul16x4;
+            break;
+         case 2:
+            op = Q ? Iop_Mul32x4 : Iop_Mul32x2;
+            break;
+         case 0:
+         case 3:
+            return False;
+         default:
+            vassert(0);
+      }
+      assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+      if (Q)
+         putQReg(dreg, mkexpr(res), condT);
+      else
+         putDRegI64(dreg, mkexpr(res), condT);
+      DIP("vmul.i%u %c%u, %c%u, d%u[%u]\n", 8 << size, Q ? 'q' : 'd', dreg,
+          Q ? 'q' : 'd', nreg, mreg, index);
+      return True;
+   }
+
+   /* VMULL (scalar) */
+   if (INSN(11,8) == BITS4(1,0,1,0)) {
+      IRTemp res, arg_m, arg_n;
+      IROp dup, get, op;
+      if (dreg & 1)
+         return False;
+      dreg >>= 1;
+      res = newTemp(Ity_V128);
+      arg_m = newTemp(Ity_I64);
+      arg_n = newTemp(Ity_I64);
+      assign(arg_n, getDRegI64(nreg));
+      switch(size) {
+         case 1:
+            dup = Iop_Dup16x4;
+            get = Iop_GetElem16x4;
+            index = mreg >> 3;
+            mreg &= 7;
+            break;
+         case 2:
+            dup = Iop_Dup32x2;
+            get = Iop_GetElem32x2;
+            index = mreg >> 4;
+            mreg &= 0xf;
+            break;
+         case 0:
+         case 3:
+            return False;
+         default:
+            vassert(0);
+      }
+      assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      switch (size) {
+         case 1: op = U ? Iop_Mull16Ux4 : Iop_Mull16Sx4; break;
+         case 2: op = U ? Iop_Mull32Ux2 : Iop_Mull32Sx2; break;
+         case 0: case 3: return False;
+         default: vassert(0);
+      }
+      assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+      putQReg(dreg, mkexpr(res), condT);
+      DIP("vmull.%c%u q%u, d%u, d%u[%u]\n", U ? 'u' : 's', 8 << size, dreg,
+          nreg, mreg, index);
+      return True;
+   }
+
+   /* VQDMULL */
+   if (INSN(11,8) == BITS4(1,0,1,1) && !U) {
+      IROp op ,op2, dup, get;
+      ULong imm;
+      IRTemp res, arg_m, arg_n;
+      if (dreg & 1)
+         return False;
+      dreg >>= 1;
+      res = newTemp(Ity_V128);
+      arg_m = newTemp(Ity_I64);
+      arg_n = newTemp(Ity_I64);
+      assign(arg_n, getDRegI64(nreg));
+      switch(size) {
+         case 1:
+            dup = Iop_Dup16x4;
+            get = Iop_GetElem16x4;
+            index = mreg >> 3;
+            mreg &= 7;
+            break;
+         case 2:
+            dup = Iop_Dup32x2;
+            get = Iop_GetElem32x2;
+            index = mreg >> 4;
+            mreg &= 0xf;
+            break;
+         case 0:
+         case 3:
+            return False;
+         default:
+            vassert(0);
+      }
+      assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      switch (size) {
+         case 0:
+         case 3:
+            return False;
+         case 1:
+            op = Iop_QDMulLong16Sx4;
+            op2 = Iop_CmpEQ16x4;
+            imm = 1LL << 15;
+            imm = (imm << 16) | imm;
+            imm = (imm << 32) | imm;
+            break;
+         case 2:
+            op = Iop_QDMulLong32Sx2;
+            op2 = Iop_CmpEQ32x2;
+            imm = 1LL << 31;
+            imm = (imm << 32) | imm;
+            break;
+         default:
+            vassert(0);
+      }
+      putQReg(dreg, binop(op, mkexpr(arg_n), mkexpr(arg_m)),
+            condT);
+#ifndef DISABLE_QC_FLAG
+      setFlag_QC(binop(Iop_And64,
+                       binop(op2, mkexpr(arg_n), mkU64(imm)),
+                       binop(op2, mkexpr(arg_m), mkU64(imm))),
+                 mkU64(0),
+                 False, condT);
+#endif
+      DIP("vqdmull.s%u q%u, d%u, d%u[%u]\n", 8 << size, dreg, nreg, mreg,
+          index);
+      return True;
+   }
+
+   /* VQDMULH */
+   if (INSN(11,8) == BITS4(1,1,0,0)) {
+      IROp op ,op2, dup, get;
+      ULong imm;
+      IRTemp res, arg_m, arg_n;
+      if (Q) {
+         if ((dreg & 1) || (nreg & 1))
+            return False;
+         dreg >>= 1;
+         nreg >>= 1;
+         res = newTemp(Ity_V128);
+         arg_m = newTemp(Ity_V128);
+         arg_n = newTemp(Ity_V128);
+         assign(arg_n, getQReg(nreg));
+         switch(size) {
+            case 1:
+               dup = Iop_Dup16x8;
+               get = Iop_GetElem16x4;
+               index = mreg >> 3;
+               mreg &= 7;
+               break;
+            case 2:
+               dup = Iop_Dup32x4;
+               get = Iop_GetElem32x2;
+               index = mreg >> 4;
+               mreg &= 0xf;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      } else {
+         res = newTemp(Ity_I64);
+         arg_m = newTemp(Ity_I64);
+         arg_n = newTemp(Ity_I64);
+         assign(arg_n, getDRegI64(nreg));
+         switch(size) {
+            case 1:
+               dup = Iop_Dup16x4;
+               get = Iop_GetElem16x4;
+               index = mreg >> 3;
+               mreg &= 7;
+               break;
+            case 2:
+               dup = Iop_Dup32x2;
+               get = Iop_GetElem32x2;
+               index = mreg >> 4;
+               mreg &= 0xf;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      }
+      switch (size) {
+         case 0:
+         case 3:
+            return False;
+         case 1:
+            op = Q ? Iop_QDMulHi16Sx8 : Iop_QDMulHi16Sx4;
+            op2 = Q ? Iop_CmpEQ16x8 : Iop_CmpEQ16x4;
+            imm = 1LL << 15;
+            imm = (imm << 16) | imm;
+            imm = (imm << 32) | imm;
+            break;
+         case 2:
+            op = Q ? Iop_QDMulHi32Sx4 : Iop_QDMulHi32Sx2;
+            op2 = Q ? Iop_CmpEQ32x4 : Iop_CmpEQ32x2;
+            imm = 1LL << 31;
+            imm = (imm << 32) | imm;
+            break;
+         default:
+            vassert(0);
+      }
+      assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+#ifndef DISABLE_QC_FLAG
+      setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64,
+                       binop(op2, mkexpr(arg_n),
+                                  Q ? mkU128(imm) : mkU64(imm)),
+                       binop(op2, mkexpr(arg_m),
+                             Q ? mkU128(imm) : mkU64(imm))),
+                 Q ? mkU128(0) : mkU64(0),
+                 Q, condT);
+#endif
+      if (Q)
+         putQReg(dreg, mkexpr(res), condT);
+      else
+         putDRegI64(dreg, mkexpr(res), condT);
+      DIP("vqdmulh.s%u %c%u, %c%u, d%u[%u]\n",
+          8 << size, Q ? 'q' : 'd', dreg,
+          Q ? 'q' : 'd', nreg, mreg, index);
+      return True;
+   }
+
+   /* VQRDMULH (scalar) */
+   if (INSN(11,8) == BITS4(1,1,0,1)) {
+      IROp op ,op2, dup, get;
+      ULong imm;
+      IRTemp res, arg_m, arg_n;
+      if (Q) {
+         if ((dreg & 1) || (nreg & 1))
+            return False;
+         dreg >>= 1;
+         nreg >>= 1;
+         res = newTemp(Ity_V128);
+         arg_m = newTemp(Ity_V128);
+         arg_n = newTemp(Ity_V128);
+         assign(arg_n, getQReg(nreg));
+         switch(size) {
+            case 1:
+               dup = Iop_Dup16x8;
+               get = Iop_GetElem16x4;
+               index = mreg >> 3;
+               mreg &= 7;
+               break;
+            case 2:
+               dup = Iop_Dup32x4;
+               get = Iop_GetElem32x2;
+               index = mreg >> 4;
+               mreg &= 0xf;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      } else {
+         res = newTemp(Ity_I64);
+         arg_m = newTemp(Ity_I64);
+         arg_n = newTemp(Ity_I64);
+         assign(arg_n, getDRegI64(nreg));
+         switch(size) {
+            case 1:
+               dup = Iop_Dup16x4;
+               get = Iop_GetElem16x4;
+               index = mreg >> 3;
+               mreg &= 7;
+               break;
+            case 2:
+               dup = Iop_Dup32x2;
+               get = Iop_GetElem32x2;
+               index = mreg >> 4;
+               mreg &= 0xf;
+               break;
+            case 0:
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(arg_m, unop(dup, binop(get, getDRegI64(mreg), mkU8(index))));
+      }
+      switch (size) {
+         case 0:
+         case 3:
+            return False;
+         case 1:
+            op = Q ? Iop_QRDMulHi16Sx8 : Iop_QRDMulHi16Sx4;
+            op2 = Q ? Iop_CmpEQ16x8 : Iop_CmpEQ16x4;
+            imm = 1LL << 15;
+            imm = (imm << 16) | imm;
+            imm = (imm << 32) | imm;
+            break;
+         case 2:
+            op = Q ? Iop_QRDMulHi32Sx4 : Iop_QRDMulHi32Sx2;
+            op2 = Q ? Iop_CmpEQ32x4 : Iop_CmpEQ32x2;
+            imm = 1LL << 31;
+            imm = (imm << 32) | imm;
+            break;
+         default:
+            vassert(0);
+      }
+      assign(res, binop(op, mkexpr(arg_n), mkexpr(arg_m)));
+#ifndef DISABLE_QC_FLAG
+      setFlag_QC(binop(Q ? Iop_AndV128 : Iop_And64,
+                       binop(op2, mkexpr(arg_n),
+                                  Q ? mkU128(imm) : mkU64(imm)),
+                       binop(op2, mkexpr(arg_m),
+                                  Q ? mkU128(imm) : mkU64(imm))),
+                 Q ? mkU128(0) : mkU64(0),
+                 Q, condT);
+#endif
+      if (Q)
+         putQReg(dreg, mkexpr(res), condT);
+      else
+         putDRegI64(dreg, mkexpr(res), condT);
+      DIP("vqrdmulh.s%u %c%u, %c%u, d%u[%u]\n",
+          8 << size, Q ? 'q' : 'd', dreg,
+          Q ? 'q' : 'd', nreg, mreg, index);
+      return True;
+   }
+
+   return False;
+#  undef INSN
+}
+
+/* A7.4.4 Two registers and a shift amount */
+static
+Bool dis_neon_data_2reg_and_shift ( UInt theInstr, IRTemp condT )
+{
+   UInt A = (theInstr >> 8) & 0xf;
+   UInt B = (theInstr >> 6) & 1;
+   UInt L = (theInstr >> 7) & 1;
+   UInt U = (theInstr >> 24) & 1;
+   UInt Q = B;
+   UInt imm6 = (theInstr >> 16) & 0x3f;
+   UInt shift_imm;
+   UInt size = 4;
+   UInt tmp;
+   UInt mreg = get_neon_m_regno(theInstr);
+   UInt dreg = get_neon_d_regno(theInstr);
+   ULong imm = 0;
+   IROp op, cvt, add = Iop_INVALID, cvt2, op_rev;
+   IRTemp reg_m, res, mask;
+
+   if (L == 0 && ((theInstr >> 19) & 7) == 0)
+      /* It is one reg and immediate */
+      return False;
+
+   tmp = (L << 6) | imm6;
+   if (tmp & 0x40) {
+      size = 3;
+      shift_imm = 64 - imm6;
+   } else if (tmp & 0x20) {
+      size = 2;
+      shift_imm = 64 - imm6;
+   } else if (tmp & 0x10) {
+      size = 1;
+      shift_imm = 32 - imm6;
+   } else if (tmp & 0x8) {
+      size = 0;
+      shift_imm = 16 - imm6;
+   } else {
+      return False;
+   }
+
+   switch (A) {
+      case 3:
+      case 2:
+         /* VRSHR, VRSRA */
+         if (shift_imm > 0) {
+            IRExpr *imm_val;
+            imm = 1L;
+            switch (size) {
+               case 0:
+                  imm = (imm << 8) | imm;
+                  /* fall through */
+               case 1:
+                  imm = (imm << 16) | imm;
+                  /* fall through */
+               case 2:
+                  imm = (imm << 32) | imm;
+                  /* fall through */
+               case 3:
+                  break;
+               default:
+                  vassert(0);
+            }
+            if (Q) {
+               reg_m = newTemp(Ity_V128);
+               res = newTemp(Ity_V128);
+               imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm));
+               assign(reg_m, getQReg(mreg));
+               switch (size) {
+                  case 0:
+                     add = Iop_Add8x16;
+                     op = U ? Iop_ShrN8x16 : Iop_SarN8x16;
+                     break;
+                  case 1:
+                     add = Iop_Add16x8;
+                     op = U ? Iop_ShrN16x8 : Iop_SarN16x8;
+                     break;
+                  case 2:
+                     add = Iop_Add32x4;
+                     op = U ? Iop_ShrN32x4 : Iop_SarN32x4;
+                     break;
+                  case 3:
+                     add = Iop_Add64x2;
+                     op = U ? Iop_ShrN64x2 : Iop_SarN64x2;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               reg_m = newTemp(Ity_I64);
+               res = newTemp(Ity_I64);
+               imm_val = mkU64(imm);
+               assign(reg_m, getDRegI64(mreg));
+               switch (size) {
+                  case 0:
+                     add = Iop_Add8x8;
+                     op = U ? Iop_ShrN8x8 : Iop_SarN8x8;
+                     break;
+                  case 1:
+                     add = Iop_Add16x4;
+                     op = U ? Iop_ShrN16x4 : Iop_SarN16x4;
+                     break;
+                  case 2:
+                     add = Iop_Add32x2;
+                     op = U ? Iop_ShrN32x2 : Iop_SarN32x2;
+                     break;
+                  case 3:
+                     add = Iop_Add64;
+                     op = U ? Iop_Shr64 : Iop_Sar64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            assign(res,
+                   binop(add,
+                         binop(op,
+                               mkexpr(reg_m),
+                               mkU8(shift_imm)),
+                         binop(Q ? Iop_AndV128 : Iop_And64,
+                               binop(op,
+                                     mkexpr(reg_m),
+                                     mkU8(shift_imm - 1)),
+                               imm_val)));
+         } else {
+            if (Q) {
+               res = newTemp(Ity_V128);
+               assign(res, getQReg(mreg));
+            } else {
+               res = newTemp(Ity_I64);
+               assign(res, getDRegI64(mreg));
+            }
+         }
+         if (A == 3) {
+            if (Q) {
+               putQReg(dreg, binop(add, mkexpr(res), getQReg(dreg)),
+                             condT);
+            } else {
+               putDRegI64(dreg, binop(add, mkexpr(res), getDRegI64(dreg)),
+                                condT);
+            }
+            DIP("vrsra.%c%u %c%u, %c%u, #%u\n",
+                U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
+         } else {
+            if (Q) {
+               putQReg(dreg, mkexpr(res), condT);
+            } else {
+               putDRegI64(dreg, mkexpr(res), condT);
+            }
+            DIP("vrshr.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
+         }
+         return True;
+      case 1:
+      case 0:
+         /* VSHR, VSRA */
+         if (Q) {
+            reg_m = newTemp(Ity_V128);
+            assign(reg_m, getQReg(mreg));
+            res = newTemp(Ity_V128);
+         } else {
+            reg_m = newTemp(Ity_I64);
+            assign(reg_m, getDRegI64(mreg));
+            res = newTemp(Ity_I64);
+         }
+         if (Q) {
+            switch (size) {
+               case 0:
+                  op = U ? Iop_ShrN8x16 : Iop_SarN8x16;
+                  add = Iop_Add8x16;
+                  break;
+               case 1:
+                  op = U ? Iop_ShrN16x8 : Iop_SarN16x8;
+                  add = Iop_Add16x8;
+                  break;
+               case 2:
+                  op = U ? Iop_ShrN32x4 : Iop_SarN32x4;
+                  add = Iop_Add32x4;
+                  break;
+               case 3:
+                  op = U ? Iop_ShrN64x2 : Iop_SarN64x2;
+                  add = Iop_Add64x2;
+                  break;
+               default:
+                  vassert(0);
+            }
+         } else {
+            switch (size) {
+               case 0:
+                  op =  U ? Iop_ShrN8x8 : Iop_SarN8x8;
+                  add = Iop_Add8x8;
+                  break;
+               case 1:
+                  op = U ? Iop_ShrN16x4 : Iop_SarN16x4;
+                  add = Iop_Add16x4;
+                  break;
+               case 2:
+                  op = U ? Iop_ShrN32x2 : Iop_SarN32x2;
+                  add = Iop_Add32x2;
+                  break;
+               case 3:
+                  op = U ? Iop_Shr64 : Iop_Sar64;
+                  add = Iop_Add64;
+                  break;
+               default:
+                  vassert(0);
+            }
+         }
+         assign(res, binop(op, mkexpr(reg_m), mkU8(shift_imm)));
+         if (A == 1) {
+            if (Q) {
+               putQReg(dreg, binop(add, mkexpr(res), getQReg(dreg)),
+                             condT);
+            } else {
+               putDRegI64(dreg, binop(add, mkexpr(res), getDRegI64(dreg)),
+                                condT);
+            }
+            DIP("vsra.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
+                  Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
+         } else {
+            if (Q) {
+               putQReg(dreg, mkexpr(res), condT);
+            } else {
+               putDRegI64(dreg, mkexpr(res), condT);
+            }
+            DIP("vshr.%c%u %c%u, %c%u, #%u\n", U ? 'u' : 's', 8 << size,
+                  Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
+         }
+         return True;
+      case 4:
+         /* VSRI */
+         if (!U)
+            return False;
+         if (Q) {
+            res = newTemp(Ity_V128);
+            mask = newTemp(Ity_V128);
+         } else {
+            res = newTemp(Ity_I64);
+            mask = newTemp(Ity_I64);
+         }
+         switch (size) {
+            case 0: op = Q ? Iop_ShrN8x16 : Iop_ShrN8x8; break;
+            case 1: op = Q ? Iop_ShrN16x8 : Iop_ShrN16x4; break;
+            case 2: op = Q ? Iop_ShrN32x4 : Iop_ShrN32x2; break;
+            case 3: op = Q ? Iop_ShrN64x2 : Iop_Shr64; break;
+            default: vassert(0);
+         }
+         if (Q) {
+            assign(mask, binop(op, binop(Iop_64HLtoV128,
+                                         mkU64(0xFFFFFFFFFFFFFFFFLL),
+                                         mkU64(0xFFFFFFFFFFFFFFFFLL)),
+                               mkU8(shift_imm)));
+            assign(res, binop(Iop_OrV128,
+                              binop(Iop_AndV128,
+                                    getQReg(dreg),
+                                    unop(Iop_NotV128,
+                                         mkexpr(mask))),
+                              binop(op,
+                                    getQReg(mreg),
+                                    mkU8(shift_imm))));
+            putQReg(dreg, mkexpr(res), condT);
+         } else {
+            assign(mask, binop(op, mkU64(0xFFFFFFFFFFFFFFFFLL),
+                               mkU8(shift_imm)));
+            assign(res, binop(Iop_Or64,
+                              binop(Iop_And64,
+                                    getDRegI64(dreg),
+                                    unop(Iop_Not64,
+                                         mkexpr(mask))),
+                              binop(op,
+                                    getDRegI64(mreg),
+                                    mkU8(shift_imm))));
+            putDRegI64(dreg, mkexpr(res), condT);
+         }
+         DIP("vsri.%u %c%u, %c%u, #%u\n",
+             8 << size, Q ? 'q' : 'd', dreg,
+             Q ? 'q' : 'd', mreg, shift_imm);
+         return True;
+      case 5:
+         if (U) {
+            /* VSLI */
+            shift_imm = 8 * (1 << size) - shift_imm;
+            if (Q) {
+               res = newTemp(Ity_V128);
+               mask = newTemp(Ity_V128);
+            } else {
+               res = newTemp(Ity_I64);
+               mask = newTemp(Ity_I64);
+            }
+            switch (size) {
+               case 0: op = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; break;
+               case 1: op = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; break;
+               case 2: op = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; break;
+               case 3: op = Q ? Iop_ShlN64x2 : Iop_Shl64; break;
+               default: vassert(0);
+            }
+            if (Q) {
+               assign(mask, binop(op, binop(Iop_64HLtoV128,
+                                            mkU64(0xFFFFFFFFFFFFFFFFLL),
+                                            mkU64(0xFFFFFFFFFFFFFFFFLL)),
+                                  mkU8(shift_imm)));
+               assign(res, binop(Iop_OrV128,
+                                 binop(Iop_AndV128,
+                                       getQReg(dreg),
+                                       unop(Iop_NotV128,
+                                            mkexpr(mask))),
+                                 binop(op,
+                                       getQReg(mreg),
+                                       mkU8(shift_imm))));
+               putQReg(dreg, mkexpr(res), condT);
+            } else {
+               assign(mask, binop(op, mkU64(0xFFFFFFFFFFFFFFFFLL),
+                                  mkU8(shift_imm)));
+               assign(res, binop(Iop_Or64,
+                                 binop(Iop_And64,
+                                       getDRegI64(dreg),
+                                       unop(Iop_Not64,
+                                            mkexpr(mask))),
+                                 binop(op,
+                                       getDRegI64(mreg),
+                                       mkU8(shift_imm))));
+               putDRegI64(dreg, mkexpr(res), condT);
+            }
+            DIP("vsli.%u %c%u, %c%u, #%u\n",
+                8 << size, Q ? 'q' : 'd', dreg,
+                Q ? 'q' : 'd', mreg, shift_imm);
+            return True;
+         } else {
+            /* VSHL #imm */
+            shift_imm = 8 * (1 << size) - shift_imm;
+            if (Q) {
+               res = newTemp(Ity_V128);
+            } else {
+               res = newTemp(Ity_I64);
+            }
+            switch (size) {
+               case 0: op = Q ? Iop_ShlN8x16 : Iop_ShlN8x8; break;
+               case 1: op = Q ? Iop_ShlN16x8 : Iop_ShlN16x4; break;
+               case 2: op = Q ? Iop_ShlN32x4 : Iop_ShlN32x2; break;
+               case 3: op = Q ? Iop_ShlN64x2 : Iop_Shl64; break;
+               default: vassert(0);
+            }
+            assign(res, binop(op, Q ? getQReg(mreg) : getDRegI64(mreg),
+                     mkU8(shift_imm)));
+            if (Q) {
+               putQReg(dreg, mkexpr(res), condT);
+            } else {
+               putDRegI64(dreg, mkexpr(res), condT);
+            }
+            DIP("vshl.i%u %c%u, %c%u, #%u\n",
+                8 << size, Q ? 'q' : 'd', dreg,
+                Q ? 'q' : 'd', mreg, shift_imm);
+            return True;
+         }
+         break;
+      case 6:
+      case 7:
+         /* VQSHL, VQSHLU */
+         shift_imm = 8 * (1 << size) - shift_imm;
+         if (U) {
+            if (A & 1) {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_QShlN8x16 : Iop_QShlN8x8;
+                     op_rev = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_QShlN16x8 : Iop_QShlN16x4;
+                     op_rev = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_QShlN32x4 : Iop_QShlN32x2;
+                     op_rev = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_QShlN64x2 : Iop_QShlN64x1;
+                     op_rev = Q ? Iop_ShrN64x2 : Iop_Shr64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+               DIP("vqshl.u%u %c%u, %c%u, #%u\n",
+                   8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
+            } else {
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_QShlN8Sx16 : Iop_QShlN8Sx8;
+                     op_rev = Q ? Iop_ShrN8x16 : Iop_ShrN8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_QShlN16Sx8 : Iop_QShlN16Sx4;
+                     op_rev = Q ? Iop_ShrN16x8 : Iop_ShrN16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_QShlN32Sx4 : Iop_QShlN32Sx2;
+                     op_rev = Q ? Iop_ShrN32x4 : Iop_ShrN32x2;
+                     break;
+                  case 3:
+                     op = Q ? Iop_QShlN64Sx2 : Iop_QShlN64Sx1;
+                     op_rev = Q ? Iop_ShrN64x2 : Iop_Shr64;
+                     break;
+                  default:
+                     vassert(0);
+               }
+               DIP("vqshlu.s%u %c%u, %c%u, #%u\n",
+                   8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
+            }
+         } else {
+            if (!(A & 1))
+               return False;
+            switch (size) {
+               case 0:
+                  op = Q ? Iop_QSalN8x16 : Iop_QSalN8x8;
+                  op_rev = Q ? Iop_SarN8x16 : Iop_SarN8x8;
+                  break;
+               case 1:
+                  op = Q ? Iop_QSalN16x8 : Iop_QSalN16x4;
+                  op_rev = Q ? Iop_SarN16x8 : Iop_SarN16x4;
+                  break;
+               case 2:
+                  op = Q ? Iop_QSalN32x4 : Iop_QSalN32x2;
+                  op_rev = Q ? Iop_SarN32x4 : Iop_SarN32x2;
+                  break;
+               case 3:
+                  op = Q ? Iop_QSalN64x2 : Iop_QSalN64x1;
+                  op_rev = Q ? Iop_SarN64x2 : Iop_Sar64;
+                  break;
+               default:
+                  vassert(0);
+            }
+            DIP("vqshl.s%u %c%u, %c%u, #%u\n",
+                8 << size,
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg, shift_imm);
+         }
+         if (Q) {
+            tmp = newTemp(Ity_V128);
+            res = newTemp(Ity_V128);
+            reg_m = newTemp(Ity_V128);
+            assign(reg_m, getQReg(mreg));
+         } else {
+            tmp = newTemp(Ity_I64);
+            res = newTemp(Ity_I64);
+            reg_m = newTemp(Ity_I64);
+            assign(reg_m, getDRegI64(mreg));
+         }
+         assign(res, binop(op, mkexpr(reg_m), mkU8(shift_imm)));
+#ifndef DISABLE_QC_FLAG
+         assign(tmp, binop(op_rev, mkexpr(res), mkU8(shift_imm)));
+         setFlag_QC(mkexpr(tmp), mkexpr(reg_m), Q, condT);
+#endif
+         if (Q)
+            putQReg(dreg, mkexpr(res), condT);
+         else
+            putDRegI64(dreg, mkexpr(res), condT);
+         return True;
+      case 8:
+         if (!U) {
+            if (L == 1)
+               return False;
+            size++;
+            dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF);
+            mreg = ((theInstr >> 1) & 0x10) | (theInstr & 0xF);
+            if (mreg & 1)
+               return False;
+            mreg >>= 1;
+            if (!B) {
+               /* VSHRN*/
+               IROp narOp;
+               reg_m = newTemp(Ity_V128);
+               assign(reg_m, getQReg(mreg));
+               res = newTemp(Ity_I64);
+               switch (size) {
+                  case 1:
+                     op = Iop_ShrN16x8;
+                     narOp = Iop_Shorten16x8;
+                     break;
+                  case 2:
+                     op = Iop_ShrN32x4;
+                     narOp = Iop_Shorten32x4;
+                     break;
+                  case 3:
+                     op = Iop_ShrN64x2;
+                     narOp = Iop_Shorten64x2;
+                     break;
+                  default:
+                     vassert(0);
+               }
+               assign(res, unop(narOp,
+                                binop(op,
+                                      mkexpr(reg_m),
+                                      mkU8(shift_imm))));
+               putDRegI64(dreg, mkexpr(res), condT);
+               DIP("vshrn.i%u d%u, q%u, #%u\n", 8 << size, dreg, mreg,
+                   shift_imm);
+               return True;
+            } else {
+               /* VRSHRN   */
+               IROp addOp, shOp, narOp;
+               IRExpr *imm_val;
+               reg_m = newTemp(Ity_V128);
+               assign(reg_m, getQReg(mreg));
+               res = newTemp(Ity_I64);
+               imm = 1L;
+               switch (size) {
+                  case 0: imm = (imm <<  8) | imm; /* fall through */
+                  case 1: imm = (imm << 16) | imm; /* fall through */
+                  case 2: imm = (imm << 32) | imm; /* fall through */
+                  case 3: break;
+                  default: vassert(0);
+               }
+               imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm));
+               switch (size) {
+                  case 1:
+                     addOp = Iop_Add16x8;
+                     shOp = Iop_ShrN16x8;
+                     narOp = Iop_Shorten16x8;
+                     break;
+                  case 2:
+                     addOp = Iop_Add32x4;
+                     shOp = Iop_ShrN32x4;
+                     narOp = Iop_Shorten32x4;
+                     break;
+                  case 3:
+                     addOp = Iop_Add64x2;
+                     shOp = Iop_ShrN64x2;
+                     narOp = Iop_Shorten64x2;
+                     break;
+                  default:
+                     vassert(0);
+               }
+               assign(res, unop(narOp,
+                                binop(addOp,
+                                      binop(shOp,
+                                            mkexpr(reg_m),
+                                            mkU8(shift_imm)),
+                                      binop(Iop_AndV128,
+                                            binop(shOp,
+                                                  mkexpr(reg_m),
+                                                  mkU8(shift_imm - 1)),
+                                            imm_val))));
+               putDRegI64(dreg, mkexpr(res), condT);
+               if (shift_imm == 0) {
+                  DIP("vmov%u d%u, q%u, #%u\n", 8 << size, dreg, mreg,
+                      shift_imm);
+               } else {
+                  DIP("vrshrn.i%u d%u, q%u, #%u\n", 8 << size, dreg, mreg,
+                      shift_imm);
+               }
+               return True;
+            }
+         } else {
+            /* fall through */
+         }
+      case 9:
+         dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF);
+         mreg = ((theInstr >>  1) & 0x10) | (theInstr & 0xF);
+         if (mreg & 1)
+            return False;
+         mreg >>= 1;
+         size++;
+         if ((theInstr >> 8) & 1) {
+            switch (size) {
+               case 1:
+                  op = U ? Iop_ShrN16x8 : Iop_SarN16x8;
+                  cvt = U ? Iop_QShortenU16Ux8 : Iop_QShortenS16Sx8;
+                  cvt2 = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
+                  break;
+               case 2:
+                  op = U ? Iop_ShrN32x4 : Iop_SarN32x4;
+                  cvt = U ? Iop_QShortenU32Ux4 : Iop_QShortenS32Sx4;
+                  cvt2 = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
+                  break;
+               case 3:
+                  op = U ? Iop_ShrN64x2 : Iop_SarN64x2;
+                  cvt = U ? Iop_QShortenU64Ux2 : Iop_QShortenS64Sx2;
+                  cvt2 = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
+                  break;
+               default:
+                  vassert(0);
+            }
+            DIP("vq%sshrn.%c%u d%u, q%u, #%u\n", B ? "r" : "",
+                U ? 'u' : 's', 8 << size, dreg, mreg, shift_imm);
+         } else {
+            vassert(U);
+            switch (size) {
+               case 1:
+                  op = Iop_SarN16x8;
+                  cvt = Iop_QShortenU16Sx8;
+                  cvt2 = Iop_Longen8Ux8;
+                  break;
+               case 2:
+                  op = Iop_SarN32x4;
+                  cvt = Iop_QShortenU32Sx4;
+                  cvt2 = Iop_Longen16Ux4;
+                  break;
+               case 3:
+                  op = Iop_SarN64x2;
+                  cvt = Iop_QShortenU64Sx2;
+                  cvt2 = Iop_Longen32Ux2;
+                  break;
+               default:
+                  vassert(0);
+            }
+            DIP("vq%sshrun.s%u d%u, q%u, #%u\n", B ? "r" : "",
+                8 << size, dreg, mreg, shift_imm);
+         }
+         if (B) {
+            if (shift_imm > 0) {
+               imm = 1;
+               switch (size) {
+                  case 1: imm = (imm << 16) | imm; /* fall through */
+                  case 2: imm = (imm << 32) | imm; /* fall through */
+                  case 3: break;
+                  case 0: default: vassert(0);
+               }
+               switch (size) {
+                  case 1: add = Iop_Add16x8; break;
+                  case 2: add = Iop_Add32x4; break;
+                  case 3: add = Iop_Add64x2; break;
+                  case 0: default: vassert(0);
+               }
+            }
+         }
+         reg_m = newTemp(Ity_V128);
+         res = newTemp(Ity_V128);
+         assign(reg_m, getQReg(mreg));
+         if (B) {
+            /* VQRSHRN, VQRSHRUN */
+            assign(res, binop(add,
+                              binop(op, mkexpr(reg_m), mkU8(shift_imm)),
+                              binop(Iop_AndV128,
+                                    binop(op,
+                                          mkexpr(reg_m),
+                                          mkU8(shift_imm - 1)),
+                                    mkU128(imm))));
+         } else {
+            /* VQSHRN, VQSHRUN */
+            assign(res, binop(op, mkexpr(reg_m), mkU8(shift_imm)));
+         }
+#ifndef DISABLE_QC_FLAG
+         setFlag_QC(unop(cvt2, unop(cvt, mkexpr(res))), mkexpr(res),
+                    True, condT);
+#endif
+         putDRegI64(dreg, unop(cvt, mkexpr(res)), condT);
+         return True;
+      case 10:
+         /* VSHLL
+            VMOVL ::= VSHLL #0 */
+         if (B)
+            return False;
+         if (dreg & 1)
+            return False;
+         dreg >>= 1;
+         shift_imm = (8 << size) - shift_imm;
+         res = newTemp(Ity_V128);
+         switch (size) {
+            case 0:
+               op = Iop_ShlN16x8;
+               cvt = U ? Iop_Longen8Ux8 : Iop_Longen8Sx8;
+               break;
+            case 1:
+               op = Iop_ShlN32x4;
+               cvt = U ? Iop_Longen16Ux4 : Iop_Longen16Sx4;
+               break;
+            case 2:
+               op = Iop_ShlN64x2;
+               cvt = U ? Iop_Longen32Ux2 : Iop_Longen32Sx2;
+               break;
+            case 3:
+               return False;
+            default:
+               vassert(0);
+         }
+         assign(res, binop(op, unop(cvt, getDRegI64(mreg)), mkU8(shift_imm)));
+         putQReg(dreg, mkexpr(res), condT);
+         if (shift_imm == 0) {
+            DIP("vmovl.%c%u q%u, d%u\n", U ? 'u' : 's', 8 << size,
+                dreg, mreg);
+         } else {
+            DIP("vshll.%c%u q%u, d%u, #%u\n", U ? 'u' : 's', 8 << size,
+                dreg, mreg, shift_imm);
+         }
+         return True;
+      case 14:
+      case 15:
+         /* VCVT floating-point <-> fixed-point */
+         if ((theInstr >> 8) & 1) {
+            if (U) {
+               op = Q ? Iop_F32ToFixed32Ux4_RZ : Iop_F32ToFixed32Ux2_RZ;
+            } else {
+               op = Q ? Iop_F32ToFixed32Sx4_RZ : Iop_F32ToFixed32Sx2_RZ;
+            }
+            DIP("vcvt.%c32.f32 %c%u, %c%u, #%u\n", U ? 'u' : 's',
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg,
+                64 - ((theInstr >> 16) & 0x3f));
+         } else {
+            if (U) {
+               op = Q ? Iop_Fixed32UToF32x4_RN : Iop_Fixed32UToF32x2_RN;
+            } else {
+               op = Q ? Iop_Fixed32SToF32x4_RN : Iop_Fixed32SToF32x2_RN;
+            }
+            DIP("vcvt.f32.%c32 %c%u, %c%u, #%u\n", U ? 'u' : 's',
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg,
+                64 - ((theInstr >> 16) & 0x3f));
+         }
+         if (((theInstr >> 21) & 1) == 0)
+            return False;
+         if (Q) {
+            putQReg(dreg, binop(op, getQReg(mreg),
+                     mkU8(64 - ((theInstr >> 16) & 0x3f))), condT);
+         } else {
+            putDRegI64(dreg, binop(op, getDRegI64(mreg),
+                       mkU8(64 - ((theInstr >> 16) & 0x3f))), condT);
+         }
+         return True;
+      default:
+         return False;
+
+   }
+   return False;
+}
+
+/* A7.4.5 Two registers, miscellaneous */
+static
+Bool dis_neon_data_2reg_misc ( UInt theInstr, IRTemp condT )
+{
+   UInt A = (theInstr >> 16) & 3;
+   UInt B = (theInstr >> 6) & 0x1f;
+   UInt Q = (theInstr >> 6) & 1;
+   UInt U = (theInstr >> 24) & 1;
+   UInt size = (theInstr >> 18) & 3;
+   UInt dreg = get_neon_d_regno(theInstr);
+   UInt mreg = get_neon_m_regno(theInstr);
+   UInt F = (theInstr >> 10) & 1;
+   IRTemp arg_d;
+   IRTemp arg_m;
+   IRTemp res;
+   switch (A) {
+      case 0:
+         if (Q) {
+            arg_m = newTemp(Ity_V128);
+            res = newTemp(Ity_V128);
+            assign(arg_m, getQReg(mreg));
+         } else {
+            arg_m = newTemp(Ity_I64);
+            res = newTemp(Ity_I64);
+            assign(arg_m, getDRegI64(mreg));
+         }
+         switch (B >> 1) {
+            case 0: {
+               /* VREV64 */
+               IROp op;
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_Reverse64_8x16 : Iop_Reverse64_8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_Reverse64_16x8 : Iop_Reverse64_16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_Reverse64_32x4 : Iop_Reverse64_32x2;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+               assign(res, unop(op, mkexpr(arg_m)));
+               DIP("vrev64.%u %c%u, %c%u\n", 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 1: {
+               /* VREV32 */
+               IROp op;
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_Reverse32_8x16 : Iop_Reverse32_8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_Reverse32_16x8 : Iop_Reverse32_16x4;
+                     break;
+                  case 2:
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+               assign(res, unop(op, mkexpr(arg_m)));
+               DIP("vrev32.%u %c%u, %c%u\n", 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 2: {
+               /* VREV16 */
+               IROp op;
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_Reverse16_8x16 : Iop_Reverse16_8x8;
+                     break;
+                  case 1:
+                  case 2:
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+               assign(res, unop(op, mkexpr(arg_m)));
+               DIP("vrev16.%u %c%u, %c%u\n", 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 3:
+               return False;
+            case 4:
+            case 5: {
+               /* VPADDL */
+               IROp op;
+               U = (theInstr >> 7) & 1;
+               if (Q) {
+                  switch (size) {
+                     case 0: op = U ? Iop_PwAddL8Ux16 : Iop_PwAddL8Sx16; break;
+                     case 1: op = U ? Iop_PwAddL16Ux8 : Iop_PwAddL16Sx8; break;
+                     case 2: op = U ? Iop_PwAddL32Ux4 : Iop_PwAddL32Sx4; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+               } else {
+                  switch (size) {
+                     case 0: op = U ? Iop_PwAddL8Ux8  : Iop_PwAddL8Sx8;  break;
+                     case 1: op = U ? Iop_PwAddL16Ux4 : Iop_PwAddL16Sx4; break;
+                     case 2: op = U ? Iop_PwAddL32Ux2 : Iop_PwAddL32Sx2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+               }
+               assign(res, unop(op, mkexpr(arg_m)));
+               DIP("vpaddl.%c%u %c%u, %c%u\n", U ? 'u' : 's', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 6:
+            case 7:
+               return False;
+            case 8: {
+               /* VCLS */
+               IROp op;
+               switch (size) {
+                  case 0: op = Q ? Iop_Cls8Sx16 : Iop_Cls8Sx8; break;
+                  case 1: op = Q ? Iop_Cls16Sx8 : Iop_Cls16Sx4; break;
+                  case 2: op = Q ? Iop_Cls32Sx4 : Iop_Cls32Sx2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+               assign(res, unop(op, mkexpr(arg_m)));
+               DIP("vcls.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
+                   Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 9: {
+               /* VCLZ */
+               IROp op;
+               switch (size) {
+                  case 0: op = Q ? Iop_Clz8Sx16 : Iop_Clz8Sx8; break;
+                  case 1: op = Q ? Iop_Clz16Sx8 : Iop_Clz16Sx4; break;
+                  case 2: op = Q ? Iop_Clz32Sx4 : Iop_Clz32Sx2; break;
+                  case 3: return False;
+                  default: vassert(0);
+               }
+               assign(res, unop(op, mkexpr(arg_m)));
+               DIP("vclz.i%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
+                   Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 10:
+               /* VCNT */
+               assign(res, unop(Q ? Iop_Cnt8x16 : Iop_Cnt8x8, mkexpr(arg_m)));
+               DIP("vcnt.8 %c%u, %c%u\n", Q ? 'q' : 'd', dreg, Q ? 'q' : 'd',
+                   mreg);
+               break;
+            case 11:
+               /* VMVN */
+               if (Q)
+                  assign(res, unop(Iop_NotV128, mkexpr(arg_m)));
+               else
+                  assign(res, unop(Iop_Not64, mkexpr(arg_m)));
+               DIP("vmvn %c%u, %c%u\n", Q ? 'q' : 'd', dreg, Q ? 'q' : 'd',
+                   mreg);
+               break;
+            case 12:
+            case 13: {
+               /* VPADAL */
+               IROp op, add_op;
+               U = (theInstr >> 7) & 1;
+               if (Q) {
+                  switch (size) {
+                     case 0:
+                        op = U ? Iop_PwAddL8Ux16 : Iop_PwAddL8Sx16;
+                        add_op = Iop_Add16x8;
+                        break;
+                     case 1:
+                        op = U ? Iop_PwAddL16Ux8 : Iop_PwAddL16Sx8;
+                        add_op = Iop_Add32x4;
+                        break;
+                     case 2:
+                        op = U ? Iop_PwAddL32Ux4 : Iop_PwAddL32Sx4;
+                        add_op = Iop_Add64x2;
+                        break;
+                     case 3:
+                        return False;
+                     default:
+                        vassert(0);
+                  }
+               } else {
+                  switch (size) {
+                     case 0:
+                        op = U ? Iop_PwAddL8Ux8 : Iop_PwAddL8Sx8;
+                        add_op = Iop_Add16x4;
+                        break;
+                     case 1:
+                        op = U ? Iop_PwAddL16Ux4 : Iop_PwAddL16Sx4;
+                        add_op = Iop_Add32x2;
+                        break;
+                     case 2:
+                        op = U ? Iop_PwAddL32Ux2 : Iop_PwAddL32Sx2;
+                        add_op = Iop_Add64;
+                        break;
+                     case 3:
+                        return False;
+                     default:
+                        vassert(0);
+                  }
+               }
+               if (Q) {
+                  arg_d = newTemp(Ity_V128);
+                  assign(arg_d, getQReg(dreg));
+               } else {
+                  arg_d = newTemp(Ity_I64);
+                  assign(arg_d, getDRegI64(dreg));
+               }
+               assign(res, binop(add_op, unop(op, mkexpr(arg_m)),
+                                         mkexpr(arg_d)));
+               DIP("vpadal.%c%u %c%u, %c%u\n", U ? 'u' : 's', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 14: {
+               /* VQABS */
+               IROp op_sub, op_qsub, op_cmp;
+               IRTemp mask, tmp;
+               IRExpr *zero1, *zero2;
+               IRExpr *neg, *neg2;
+               if (Q) {
+                  zero1 = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+                  zero2 = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+                  mask = newTemp(Ity_V128);
+                  tmp = newTemp(Ity_V128);
+               } else {
+                  zero1 = mkU64(0);
+                  zero2 = mkU64(0);
+                  mask = newTemp(Ity_I64);
+                  tmp = newTemp(Ity_I64);
+               }
+               switch (size) {
+                  case 0:
+                     op_sub = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     op_qsub = Q ? Iop_QSub8Sx16 : Iop_QSub8Sx8;
+                     op_cmp = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8;
+                     break;
+                  case 1:
+                     op_sub = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     op_qsub = Q ? Iop_QSub16Sx8 : Iop_QSub16Sx4;
+                     op_cmp = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4;
+                     break;
+                  case 2:
+                     op_sub = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     op_qsub = Q ? Iop_QSub32Sx4 : Iop_QSub32Sx2;
+                     op_cmp = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+               assign(mask, binop(op_cmp, mkexpr(arg_m), zero1));
+               neg = binop(op_qsub, zero2, mkexpr(arg_m));
+               neg2 = binop(op_sub, zero2, mkexpr(arg_m));
+               assign(res, binop(Q ? Iop_OrV128 : Iop_Or64,
+                                 binop(Q ? Iop_AndV128 : Iop_And64,
+                                       mkexpr(mask),
+                                       mkexpr(arg_m)),
+                                 binop(Q ? Iop_AndV128 : Iop_And64,
+                                       unop(Q ? Iop_NotV128 : Iop_Not64,
+                                            mkexpr(mask)),
+                                       neg)));
+#ifndef DISABLE_QC_FLAG
+               assign(tmp, binop(Q ? Iop_OrV128 : Iop_Or64,
+                                 binop(Q ? Iop_AndV128 : Iop_And64,
+                                       mkexpr(mask),
+                                       mkexpr(arg_m)),
+                                 binop(Q ? Iop_AndV128 : Iop_And64,
+                                       unop(Q ? Iop_NotV128 : Iop_Not64,
+                                            mkexpr(mask)),
+                                       neg2)));
+               setFlag_QC(mkexpr(res), mkexpr(tmp), Q, condT);
+#endif
+               DIP("vqabs.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
+                   Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 15: {
+               /* VQNEG */
+               IROp op, op2;
+               IRExpr *zero;
+               if (Q) {
+                  zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+               } else {
+                  zero = mkU64(0);
+               }
+               switch (size) {
+                  case 0:
+                     op = Q ? Iop_QSub8Sx16 : Iop_QSub8Sx8;
+                     op2 = Q ? Iop_Sub8x16 : Iop_Sub8x8;
+                     break;
+                  case 1:
+                     op = Q ? Iop_QSub16Sx8 : Iop_QSub16Sx4;
+                     op2 = Q ? Iop_Sub16x8 : Iop_Sub16x4;
+                     break;
+                  case 2:
+                     op = Q ? Iop_QSub32Sx4 : Iop_QSub32Sx2;
+                     op2 = Q ? Iop_Sub32x4 : Iop_Sub32x2;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+               assign(res, binop(op, zero, mkexpr(arg_m)));
+#ifndef DISABLE_QC_FLAG
+               setFlag_QC(mkexpr(res), binop(op2, zero, mkexpr(arg_m)),
+                          Q, condT);
+#endif
+               DIP("vqneg.s%u %c%u, %c%u\n", 8 << size, Q ? 'q' : 'd', dreg,
+                   Q ? 'q' : 'd', mreg);
+               break;
+            }
+            default:
+               vassert(0);
+         }
+         if (Q) {
+            putQReg(dreg, mkexpr(res), condT);
+         } else {
+            putDRegI64(dreg, mkexpr(res), condT);
+         }
+         return True;
+      case 1:
+         if (Q) {
+            arg_m = newTemp(Ity_V128);
+            res = newTemp(Ity_V128);
+            assign(arg_m, getQReg(mreg));
+         } else {
+            arg_m = newTemp(Ity_I64);
+            res = newTemp(Ity_I64);
+            assign(arg_m, getDRegI64(mreg));
+         }
+         switch ((B >> 1) & 0x7) {
+            case 0: {
+               /* VCGT #0 */
+               IRExpr *zero;
+               IROp op;
+               if (Q) {
+                  zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+               } else {
+                  zero = mkU64(0);
+               }
+               if (F) {
+                  switch (size) {
+                     case 0: case 1: case 3: return False;
+                     case 2: op = Q ? Iop_CmpGT32Fx4 : Iop_CmpGT32Fx2; break;
+                     default: vassert(0);
+                  }
+               } else {
+                  switch (size) {
+                     case 0: op = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; break;
+                     case 1: op = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; break;
+                     case 2: op = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+               }
+               assign(res, binop(op, mkexpr(arg_m), zero));
+               DIP("vcgt.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 1: {
+               /* VCGE #0 */
+               IROp op;
+               IRExpr *zero;
+               if (Q) {
+                  zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+               } else {
+                  zero = mkU64(0);
+               }
+               if (F) {
+                  switch (size) {
+                     case 0: case 1: case 3: return False;
+                     case 2: op = Q ? Iop_CmpGE32Fx4 : Iop_CmpGE32Fx2; break;
+                     default: vassert(0);
+                  }
+                  assign(res, binop(op, mkexpr(arg_m), zero));
+               } else {
+                  switch (size) {
+                     case 0: op = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; break;
+                     case 1: op = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; break;
+                     case 2: op = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  assign(res, unop(Q ? Iop_NotV128 : Iop_Not64,
+                                   binop(op, zero, mkexpr(arg_m))));
+               }
+               DIP("vcge.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 2: {
+               /* VCEQ #0 */
+               IROp op;
+               IRExpr *zero;
+               if (F) {
+                  if (Q) {
+                     zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+                  } else {
+                     zero = mkU64(0);
+                  }
+                  switch (size) {
+                     case 0: case 1: case 3: return False;
+                     case 2: op = Q ? Iop_CmpEQ32Fx4 : Iop_CmpEQ32Fx2; break;
+                     default: vassert(0);
+                  }
+                  assign(res, binop(op, zero, mkexpr(arg_m)));
+               } else {
+                  switch (size) {
+                     case 0: op = Q ? Iop_CmpNEZ8x16 : Iop_CmpNEZ8x8; break;
+                     case 1: op = Q ? Iop_CmpNEZ16x8 : Iop_CmpNEZ16x4; break;
+                     case 2: op = Q ? Iop_CmpNEZ32x4 : Iop_CmpNEZ32x2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  assign(res, unop(Q ? Iop_NotV128 : Iop_Not64,
+                                   unop(op, mkexpr(arg_m))));
+               }
+               DIP("vceq.%c%u %c%u, %c%u, #0\n", F ? 'f' : 'i', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 3: {
+               /* VCLE #0 */
+               IRExpr *zero;
+               IROp op;
+               if (Q) {
+                  zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+               } else {
+                  zero = mkU64(0);
+               }
+               if (F) {
+                  switch (size) {
+                     case 0: case 1: case 3: return False;
+                     case 2: op = Q ? Iop_CmpGE32Fx4 : Iop_CmpGE32Fx2; break;
+                     default: vassert(0);
+                  }
+                  assign(res, binop(op, zero, mkexpr(arg_m)));
+               } else {
+                  switch (size) {
+                     case 0: op = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; break;
+                     case 1: op = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; break;
+                     case 2: op = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  assign(res, unop(Q ? Iop_NotV128 : Iop_Not64,
+                                   binop(op, mkexpr(arg_m), zero)));
+               }
+               DIP("vcle.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 4: {
+               /* VCLT #0 */
+               IROp op;
+               IRExpr *zero;
+               if (Q) {
+                  zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+               } else {
+                  zero = mkU64(0);
+               }
+               if (F) {
+                  switch (size) {
+                     case 0: case 1: case 3: return False;
+                     case 2: op = Q ? Iop_CmpGT32Fx4 : Iop_CmpGT32Fx2; break;
+                     default: vassert(0);
+                  }
+                  assign(res, binop(op, zero, mkexpr(arg_m)));
+               } else {
+                  switch (size) {
+                     case 0: op = Q ? Iop_CmpGT8Sx16 : Iop_CmpGT8Sx8; break;
+                     case 1: op = Q ? Iop_CmpGT16Sx8 : Iop_CmpGT16Sx4; break;
+                     case 2: op = Q ? Iop_CmpGT32Sx4 : Iop_CmpGT32Sx2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  assign(res, binop(op, zero, mkexpr(arg_m)));
+               }
+               DIP("vclt.%c%u %c%u, %c%u, #0\n", F ? 'f' : 's', 8 << size,
+                   Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 5:
+               return False;
+            case 6: {
+               /* VABS */
+               if (!F) {
+                  IROp op;
+                  switch(size) {
+                     case 0: op = Q ? Iop_Abs8x16 : Iop_Abs8x8; break;
+                     case 1: op = Q ? Iop_Abs16x8 : Iop_Abs16x4; break;
+                     case 2: op = Q ? Iop_Abs32x4 : Iop_Abs32x2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  assign(res, unop(op, mkexpr(arg_m)));
+               } else {
+                  assign(res, unop(Q ? Iop_Abs32Fx4 : Iop_Abs32Fx2,
+                                   mkexpr(arg_m)));
+               }
+               DIP("vabs.%c%u %c%u, %c%u\n",
+                   F ? 'f' : 's', 8 << size, Q ? 'q' : 'd', dreg,
+                   Q ? 'q' : 'd', mreg);
+               break;
+            }
+            case 7: {
+               /* VNEG */
+               IROp op;
+               IRExpr *zero;
+               if (F) {
+                  switch (size) {
+                     case 0: case 1: case 3: return False;
+                     case 2: op = Q ? Iop_Neg32Fx4 : Iop_Neg32Fx2; break;
+                     default: vassert(0);
+                  }
+                  assign(res, unop(op, mkexpr(arg_m)));
+               } else {
+                  if (Q) {
+                     zero = binop(Iop_64HLtoV128, mkU64(0), mkU64(0));
+                  } else {
+                     zero = mkU64(0);
+                  }
+                  switch (size) {
+                     case 0: op = Q ? Iop_Sub8x16 : Iop_Sub8x8; break;
+                     case 1: op = Q ? Iop_Sub16x8 : Iop_Sub16x4; break;
+                     case 2: op = Q ? Iop_Sub32x4 : Iop_Sub32x2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  assign(res, binop(op, zero, mkexpr(arg_m)));
+               }
+               DIP("vneg.%c%u %c%u, %c%u\n",
+                   F ? 'f' : 's', 8 << size, Q ? 'q' : 'd', dreg,
+                   Q ? 'q' : 'd', mreg);
+               break;
+            }
+            default:
+               vassert(0);
+         }
+         if (Q) {
+            putQReg(dreg, mkexpr(res), condT);
+         } else {
+            putDRegI64(dreg, mkexpr(res), condT);
+         }
+         return True;
+      case 2:
+         if ((B >> 1) == 0) {
+            /* VSWP */
+            if (Q) {
+               arg_m = newTemp(Ity_V128);
+               assign(arg_m, getQReg(mreg));
+               putQReg(mreg, getQReg(dreg), condT);
+               putQReg(dreg, mkexpr(arg_m), condT);
+            } else {
+               arg_m = newTemp(Ity_I64);
+               assign(arg_m, getDRegI64(mreg));
+               putDRegI64(mreg, getDRegI64(dreg), condT);
+               putDRegI64(dreg, mkexpr(arg_m), condT);
+            }
+            DIP("vswp %c%u, %c%u\n",
+                Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+            return True;
+         } else if ((B >> 1) == 1) {
+            /* VTRN */
+            IROp op_lo, op_hi;
+            IRTemp res1, res2;
+            if (Q) {
+               arg_m = newTemp(Ity_V128);
+               arg_d = newTemp(Ity_V128);
+               res1 = newTemp(Ity_V128);
+               res2 = newTemp(Ity_V128);
+               assign(arg_m, getQReg(mreg));
+               assign(arg_d, getQReg(dreg));
+            } else {
+               res1 = newTemp(Ity_I64);
+               res2 = newTemp(Ity_I64);
+               arg_m = newTemp(Ity_I64);
+               arg_d = newTemp(Ity_I64);
+               assign(arg_m, getDRegI64(mreg));
+               assign(arg_d, getDRegI64(dreg));
+            }
+            if (Q) {
+               switch (size) {
+                  case 0:
+                     op_lo = Iop_InterleaveOddLanes8x16;
+                     op_hi = Iop_InterleaveEvenLanes8x16;
+                     break;
+                  case 1:
+                     op_lo = Iop_InterleaveOddLanes16x8;
+                     op_hi = Iop_InterleaveEvenLanes16x8;
+                     break;
+                  case 2:
+                     op_lo = Iop_InterleaveOddLanes32x4;
+                     op_hi = Iop_InterleaveEvenLanes32x4;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            } else {
+               switch (size) {
+                  case 0:
+                     op_lo = Iop_InterleaveOddLanes8x8;
+                     op_hi = Iop_InterleaveEvenLanes8x8;
+                     break;
+                  case 1:
+                     op_lo = Iop_InterleaveOddLanes16x4;
+                     op_hi = Iop_InterleaveEvenLanes16x4;
+                     break;
+                  case 2:
+                     op_lo = Iop_InterleaveHI32x2;
+                     op_hi = Iop_InterleaveLO32x2;
+                     break;
+                  case 3:
+                     return False;
+                  default:
+                     vassert(0);
+               }
+            }
+            assign(res1, binop(op_lo, mkexpr(arg_m), mkexpr(arg_d)));
+            assign(res2, binop(op_hi, mkexpr(arg_m), mkexpr(arg_d)));
+            if (Q) {
+               putQReg(dreg, mkexpr(res1), condT);
+               putQReg(mreg, mkexpr(res2), condT);
+            } else {
+               putDRegI64(dreg, mkexpr(res1), condT);
+               putDRegI64(mreg, mkexpr(res2), condT);
+            }
+            DIP("vtrn.%u %c%u, %c%u\n",
+                8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+            return True;
+         } else if ((B >> 1) == 2) {
+            /* VUZP */
+            IROp op_lo, op_hi;
+            IRTemp res1, res2;
+            if (!Q && size == 2)
+               return False;
+            if (Q) {
+               arg_m = newTemp(Ity_V128);
+               arg_d = newTemp(Ity_V128);
+               res1 = newTemp(Ity_V128);
+               res2 = newTemp(Ity_V128);
+               assign(arg_m, getQReg(mreg));
+               assign(arg_d, getQReg(dreg));
+            } else {
+               res1 = newTemp(Ity_I64);
+               res2 = newTemp(Ity_I64);
+               arg_m = newTemp(Ity_I64);
+               arg_d = newTemp(Ity_I64);
+               assign(arg_m, getDRegI64(mreg));
+               assign(arg_d, getDRegI64(dreg));
+            }
+            switch (size) {
+               case 0:
+                  op_lo = Q ? Iop_CatOddLanes8x16 : Iop_CatOddLanes8x8;
+                  op_hi = Q ? Iop_CatEvenLanes8x16 : Iop_CatEvenLanes8x8;
+                  break;
+               case 1:
+                  op_lo = Q ? Iop_CatOddLanes16x8 : Iop_CatOddLanes16x4;
+                  op_hi = Q ? Iop_CatEvenLanes16x8 : Iop_CatEvenLanes16x4;
+                  break;
+               case 2:
+                  op_lo = Iop_CatOddLanes32x4;
+                  op_hi = Iop_CatEvenLanes32x4;
+                  break;
+               case 3:
+                  return False;
+               default:
+                  vassert(0);
+            }
+            assign(res1, binop(op_lo, mkexpr(arg_m), mkexpr(arg_d)));
+            assign(res2, binop(op_hi, mkexpr(arg_m), mkexpr(arg_d)));
+            if (Q) {
+               putQReg(dreg, mkexpr(res1), condT);
+               putQReg(mreg, mkexpr(res2), condT);
+            } else {
+               putDRegI64(dreg, mkexpr(res1), condT);
+               putDRegI64(mreg, mkexpr(res2), condT);
+            }
+            DIP("vuzp.%u %c%u, %c%u\n",
+                8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+            return True;
+         } else if ((B >> 1) == 3) {
+            /* VZIP */
+            IROp op_lo, op_hi;
+            IRTemp res1, res2;
+            if (!Q && size == 2)
+               return False;
+            if (Q) {
+               arg_m = newTemp(Ity_V128);
+               arg_d = newTemp(Ity_V128);
+               res1 = newTemp(Ity_V128);
+               res2 = newTemp(Ity_V128);
+               assign(arg_m, getQReg(mreg));
+               assign(arg_d, getQReg(dreg));
+            } else {
+               res1 = newTemp(Ity_I64);
+               res2 = newTemp(Ity_I64);
+               arg_m = newTemp(Ity_I64);
+               arg_d = newTemp(Ity_I64);
+               assign(arg_m, getDRegI64(mreg));
+               assign(arg_d, getDRegI64(dreg));
+            }
+            switch (size) {
+               case 0:
+                  op_lo = Q ? Iop_InterleaveLO8x16 : Iop_InterleaveHI8x8;
+                  op_hi = Q ? Iop_InterleaveLO8x16 : Iop_InterleaveLO8x8;
+                  break;
+               case 1:
+                  op_lo = Q ? Iop_InterleaveHI16x8 : Iop_InterleaveHI16x4;
+                  op_hi = Q ? Iop_InterleaveLO16x8 : Iop_InterleaveLO16x4;
+                  break;
+               case 2:
+                  op_lo = Iop_InterleaveHI32x4;
+                  op_hi = Iop_InterleaveLO32x4;
+                  break;
+               case 3:
+                  return False;
+               default:
+                  vassert(0);
+            }
+            assign(res1, binop(op_lo, mkexpr(arg_m), mkexpr(arg_d)));
+            assign(res2, binop(op_hi, mkexpr(arg_m), mkexpr(arg_d)));
+            if (Q) {
+               putQReg(dreg, mkexpr(res1), condT);
+               putQReg(mreg, mkexpr(res2), condT);
+            } else {
+               putDRegI64(dreg, mkexpr(res1), condT);
+               putDRegI64(mreg, mkexpr(res2), condT);
+            }
+            DIP("vzip.%u %c%u, %c%u\n",
+                8 << size, Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+            return True;
+         } else if (B == 8) {
+            /* VMOVN */
+            IROp op;
+            mreg >>= 1;
+            switch (size) {
+               case 0: op = Iop_Shorten16x8; break;
+               case 1: op = Iop_Shorten32x4; break;
+               case 2: op = Iop_Shorten64x2; break;
+               case 3: return False;
+               default: vassert(0);
+            }
+            putDRegI64(dreg, unop(op, getQReg(mreg)), condT);
+            DIP("vmovn.i%u d%u, q%u\n", 16 << size, dreg, mreg);
+            return True;
+         } else if (B == 9 || (B >> 1) == 5) {
+            /* VQMOVN, VQMOVUN */
+            IROp op, op2;
+            IRTemp tmp;
+            dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF);
+            mreg = ((theInstr >> 1) & 0x10) | (theInstr & 0xF);
+            if (mreg & 1)
+               return False;
+            mreg >>= 1;
+            switch (size) {
+               case 0: op2 = Iop_Shorten16x8; break;
+               case 1: op2 = Iop_Shorten32x4; break;
+               case 2: op2 = Iop_Shorten64x2; break;
+               case 3: return False;
+               default: vassert(0);
+            }
+            switch (B & 3) {
+               case 0:
+                  vassert(0);
+               case 1:
+                  switch (size) {
+                     case 0: op = Iop_QShortenU16Sx8; break;
+                     case 1: op = Iop_QShortenU32Sx4; break;
+                     case 2: op = Iop_QShortenU64Sx2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  DIP("vqmovun.s%u d%u, q%u\n", 16 << size, dreg, mreg);
+                  break;
+               case 2:
+                  switch (size) {
+                     case 0: op = Iop_QShortenS16Sx8; break;
+                     case 1: op = Iop_QShortenS32Sx4; break;
+                     case 2: op = Iop_QShortenS64Sx2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  DIP("vqmovn.s%u d%u, q%u\n", 16 << size, dreg, mreg);
+                  break;
+               case 3:
+                  switch (size) {
+                     case 0: op = Iop_QShortenU16Ux8; break;
+                     case 1: op = Iop_QShortenU32Ux4; break;
+                     case 2: op = Iop_QShortenU64Ux2; break;
+                     case 3: return False;
+                     default: vassert(0);
+                  }
+                  DIP("vqmovn.u%u d%u, q%u\n", 16 << size, dreg, mreg);
+                  break;
+               default:
+                  vassert(0);
+            }
+            res = newTemp(Ity_I64);
+            tmp = newTemp(Ity_I64);
+            assign(res, unop(op, getQReg(mreg)));
+#ifndef DISABLE_QC_FLAG
+            assign(tmp, unop(op2, getQReg(mreg)));
+            setFlag_QC(mkexpr(res), mkexpr(tmp), False, condT);
+#endif
+            putDRegI64(dreg, mkexpr(res), condT);
+            return True;
+         } else if (B == 12) {
+            /* VSHLL (maximum shift) */
+            IROp op, cvt;
+            UInt shift_imm;
+            if (Q)
+               return False;
+            if (dreg & 1)
+               return False;
+            dreg >>= 1;
+            shift_imm = 8 << size;
+            res = newTemp(Ity_V128);
+            switch (size) {
+               case 0: op = Iop_ShlN16x8; cvt = Iop_Longen8Ux8; break;
+               case 1: op = Iop_ShlN32x4; cvt = Iop_Longen16Ux4; break;
+               case 2: op = Iop_ShlN64x2; cvt = Iop_Longen32Ux2; break;
+               case 3: return False;
+               default: vassert(0);
+            }
+            assign(res, binop(op, unop(cvt, getDRegI64(mreg)),
+                                  mkU8(shift_imm)));
+            putQReg(dreg, mkexpr(res), condT);
+            DIP("vshll.i%u q%u, d%u, #%u\n", 8 << size, dreg, mreg, 8 << size);
+            return True;
+         } else if ((B >> 3) == 3 && (B & 3) == 0) {
+            /* VCVT (half<->single) */
+            /* Half-precision extensions are needed to run this */
+            vassert(0); // ATC
+            if (((theInstr >> 18) & 3) != 1)
+               return False;
+            if ((theInstr >> 8) & 1) {
+               if (dreg & 1)
+                  return False;
+               dreg >>= 1;
+               putQReg(dreg, unop(Iop_F16toF32x4, getDRegI64(mreg)),
+                     condT);
+               DIP("vcvt.f32.f16 q%u, d%u\n", dreg, mreg);
+            } else {
+               if (mreg & 1)
+                  return False;
+               mreg >>= 1;
+               putDRegI64(dreg, unop(Iop_F32toF16x4, getQReg(mreg)),
+                                condT);
+               DIP("vcvt.f16.f32 d%u, q%u\n", dreg, mreg);
+            }
+            return True;
+         } else {
+            return False;
+         }
+         vassert(0);
+         return True;
+      case 3:
+         if (((B >> 1) & BITS4(1,1,0,1)) == BITS4(1,0,0,0)) {
+            /* VRECPE */
+            IROp op;
+            F = (theInstr >> 8) & 1;
+            if (size != 2)
+               return False;
+            if (Q) {
+               op = F ? Iop_Recip32Fx4 : Iop_Recip32x4;
+               putQReg(dreg, unop(op, getQReg(mreg)), condT);
+               DIP("vrecpe.%c32 q%u, q%u\n", F ? 'f' : 'u', dreg, mreg);
+            } else {
+               op = F ? Iop_Recip32Fx2 : Iop_Recip32x2;
+               putDRegI64(dreg, unop(op, getDRegI64(mreg)), condT);
+               DIP("vrecpe.%c32 d%u, d%u\n", F ? 'f' : 'u', dreg, mreg);
+            }
+            return True;
+         } else if (((B >> 1) & BITS4(1,1,0,1)) == BITS4(1,0,0,1)) {
+            /* VRSQRTE */
+            IROp op;
+            F = (B >> 2) & 1;
+            if (size != 2)
+               return False;
+            if (F) {
+               /* fp */
+               op = Q ? Iop_Rsqrte32Fx4 : Iop_Rsqrte32Fx2;
+            } else {
+               /* unsigned int */
+               op = Q ? Iop_Rsqrte32x4 : Iop_Rsqrte32x2;
+            }
+            if (Q) {
+               putQReg(dreg, unop(op, getQReg(mreg)), condT);
+               DIP("vrsqrte.%c32 q%u, q%u\n", F ? 'f' : 'u', dreg, mreg);
+            } else {
+               putDRegI64(dreg, unop(op, getDRegI64(mreg)), condT);
+               DIP("vrsqrte.%c32 d%u, d%u\n", F ? 'f' : 'u', dreg, mreg);
+            }
+            return True;
+         } else if ((B >> 3) == 3) {
+            /* VCVT (fp<->integer) */
+            IROp op;
+            if (size != 2)
+               return False;
+            switch ((B >> 1) & 3) {
+               case 0:
+                  op = Q ? Iop_I32StoFx4 : Iop_I32StoFx2;
+                  DIP("vcvt.f32.s32 %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+                  break;
+               case 1:
+                  op = Q ? Iop_I32UtoFx4 : Iop_I32UtoFx2;
+                  DIP("vcvt.f32.u32 %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+                  break;
+               case 2:
+                  op = Q ? Iop_FtoI32Sx4_RZ : Iop_FtoI32Sx2_RZ;
+                  DIP("vcvt.s32.f32 %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+                  break;
+               case 3:
+                  op = Q ? Iop_FtoI32Ux4_RZ : Iop_FtoI32Ux2_RZ;
+                  DIP("vcvt.u32.f32 %c%u, %c%u\n",
+                      Q ? 'q' : 'd', dreg, Q ? 'q' : 'd', mreg);
+                  break;
+               default:
+                  vassert(0);
+            }
+            if (Q) {
+               putQReg(dreg, unop(op, getQReg(mreg)), condT);
+            } else {
+               putDRegI64(dreg, unop(op, getDRegI64(mreg)), condT);
+            }
+            return True;
+         } else {
+            return False;
+         }
+         vassert(0);
+         return True;
+      default:
+         vassert(0);
+   }
+   return False;
+}
+
+/* A7.4.6 One register and a modified immediate value */
+static
+void ppNeonImm(UInt imm, UInt cmode, UInt op)
+{
+   int i;
+   switch (cmode) {
+      case 0: case 1: case 8: case 9:
+         vex_printf("0x%x", imm);
+         break;
+      case 2: case 3: case 10: case 11:
+         vex_printf("0x%x00", imm);
+         break;
+      case 4: case 5:
+         vex_printf("0x%x0000", imm);
+         break;
+      case 6: case 7:
+         vex_printf("0x%x000000", imm);
+         break;
+      case 12:
+         vex_printf("0x%xff", imm);
+         break;
+      case 13:
+         vex_printf("0x%xffff", imm);
+         break;
+      case 14:
+         if (op) {
+            vex_printf("0x");
+            for (i = 7; i >= 0; i--)
+               vex_printf("%s", (imm & (1 << i)) ? "ff" : "00");
+         } else {
+            vex_printf("0x%x", imm);
+         }
+         break;
+      case 15:
+         vex_printf("0x%x", imm);
+         break;
+   }
+}
+
+static
+const char *ppNeonImmType(UInt cmode, UInt op)
+{
+   switch (cmode) {
+      case 0 ... 7:
+      case 12: case 13:
+         return "i32";
+      case 8 ... 11:
+         return "i16";
+      case 14:
+         if (op)
+            return "i64";
+         else
+            return "i8";
+      case 15:
+         if (op)
+            vassert(0);
+         else
+            return "f32";
+      default:
+         vassert(0);
+   }
+}
+
+static
+void DIPimm(UInt imm, UInt cmode, UInt op,
+            const char *instr, UInt Q, UInt dreg)
+{
+   if (vex_traceflags & VEX_TRACE_FE) {
+      vex_printf("%s.%s %c%u, #", instr,
+                 ppNeonImmType(cmode, op), Q ? 'q' : 'd', dreg);
+      ppNeonImm(imm, cmode, op);
+      vex_printf("\n");
+   }
+}
+
+static
+Bool dis_neon_data_1reg_and_imm ( UInt theInstr, IRTemp condT )
+{
+   UInt dreg = get_neon_d_regno(theInstr);
+   ULong imm_raw = ((theInstr >> 17) & 0x80) | ((theInstr >> 12) & 0x70) |
+                  (theInstr & 0xf);
+   ULong imm_raw_pp = imm_raw;
+   UInt cmode = (theInstr >> 8) & 0xf;
+   UInt op_bit = (theInstr >> 5) & 1;
+   ULong imm = 0;
+   UInt Q = (theInstr >> 6) & 1;
+   int i, j;
+   UInt tmp;
+   IRExpr *imm_val;
+   IRExpr *expr;
+   IRTemp tmp_var;
+   switch(cmode) {
+      case 7: case 6:
+         imm_raw = imm_raw << 8;
+         /* fallthrough */
+      case 5: case 4:
+         imm_raw = imm_raw << 8;
+         /* fallthrough */
+      case 3: case 2:
+         imm_raw = imm_raw << 8;
+         /* fallthrough */
+      case 0: case 1:
+         imm = (imm_raw << 32) | imm_raw;
+         break;
+      case 11: case 10:
+         imm_raw = imm_raw << 8;
+         /* fallthrough */
+      case 9: case 8:
+         imm_raw = (imm_raw << 16) | imm_raw;
+         imm = (imm_raw << 32) | imm_raw;
+         break;
+      case 13:
+         imm_raw = (imm_raw << 8) | 0xff;
+         /* fallthrough */
+      case 12:
+         imm_raw = (imm_raw << 8) | 0xff;
+         imm = (imm_raw << 32) | imm_raw;
+         break;
+      case 14:
+         if (! op_bit) {
+            for(i = 0; i < 8; i++) {
+               imm = (imm << 8) | imm_raw;
+            }
+         } else {
+            for(i = 7; i >= 0; i--) {
+               tmp = 0;
+               for(j = 0; j < 8; j++) {
+                  tmp = (tmp << 1) | ((imm_raw >> i) & 1);
+               }
+               imm = (imm << 8) | tmp;
+            }
+         }
+         break;
+      case 15:
+         imm = (imm_raw & 0x80) << 5;
+         imm |= ~((imm_raw & 0x40) << 5);
+         for(i = 1; i <= 4; i++)
+            imm |= (imm_raw & 0x40) << i;
+         imm |= (imm_raw & 0x7f);
+         imm = imm << 19;
+         imm = (imm << 32) | imm;
+         break;
+      default:
+         return False;
+   }
+   if (Q) {
+      imm_val = binop(Iop_64HLtoV128, mkU64(imm), mkU64(imm));
+   } else {
+      imm_val = mkU64(imm);
+   }
+   if (((op_bit == 0) &&
+      (((cmode & 9) == 0) || ((cmode & 13) == 8) || ((cmode & 12) == 12))) ||
+      ((op_bit == 1) && (cmode == 14))) {
+      /* VMOV (immediate) */
+      if (Q) {
+         putQReg(dreg, imm_val, condT);
+      } else {
+         putDRegI64(dreg, imm_val, condT);
+      }
+      DIPimm(imm_raw_pp, cmode, op_bit, "vmov", Q, dreg);
+      return True;
+   }
+   if ((op_bit == 1) &&
+      (((cmode & 9) == 0) || ((cmode & 13) == 8) || ((cmode & 14) == 12))) {
+      /* VMVN (immediate) */
+      if (Q) {
+         putQReg(dreg, unop(Iop_NotV128, imm_val), condT);
+      } else {
+         putDRegI64(dreg, unop(Iop_Not64, imm_val), condT);
+      }
+      DIPimm(imm_raw_pp, cmode, op_bit, "vmvn", Q, dreg);
+      return True;
+   }
+   if (Q) {
+      tmp_var = newTemp(Ity_V128);
+      assign(tmp_var, getQReg(dreg));
+   } else {
+      tmp_var = newTemp(Ity_I64);
+      assign(tmp_var, getDRegI64(dreg));
+   }
+   if ((op_bit == 0) && (((cmode & 9) == 1) || ((cmode & 13) == 9))) {
+      /* VORR (immediate) */
+      if (Q)
+         expr = binop(Iop_OrV128, mkexpr(tmp_var), imm_val);
+      else
+         expr = binop(Iop_Or64, mkexpr(tmp_var), imm_val);
+      DIPimm(imm_raw_pp, cmode, op_bit, "vorr", Q, dreg);
+   } else if ((op_bit == 1) && (((cmode & 9) == 1) || ((cmode & 13) == 9))) {
+      /* VBIC (immediate) */
+      if (Q)
+         expr = binop(Iop_AndV128, mkexpr(tmp_var),
+                                   unop(Iop_NotV128, imm_val));
+      else
+         expr = binop(Iop_And64, mkexpr(tmp_var), unop(Iop_Not64, imm_val));
+      DIPimm(imm_raw_pp, cmode, op_bit, "vbic", Q, dreg);
+   } else {
+      return False;
+   }
+   if (Q)
+      putQReg(dreg, expr, condT);
+   else
+      putDRegI64(dreg, expr, condT);
+   return True;
+}
+
+/* A7.4 Advanced SIMD data-processing instructions */
+static
+Bool dis_neon_data_processing ( UInt theInstr, IRTemp condT )
+{
+   UInt A = (theInstr >> 19) & 0x1F;
+   UInt B = (theInstr >>  8) & 0xF;
+   UInt C = (theInstr >>  4) & 0xF;
+   UInt U = (theInstr >> 24) & 0x1;
+
+   if (! (A & 0x10)) {
+      return dis_neon_data_3same(theInstr, condT);
+   }
+   if (((A & 0x17) == 0x10) && ((C & 0x9) == 0x1)) {
+      return dis_neon_data_1reg_and_imm(theInstr, condT);
+   }
+   if ((C & 1) == 1) {
+      return dis_neon_data_2reg_and_shift(theInstr, condT);
+   }
+   if (((C & 5) == 0) && (((A & 0x14) == 0x10) || ((A & 0x16) == 0x14))) {
+      return dis_neon_data_3diff(theInstr, condT);
+   }
+   if (((C & 5) == 4) && (((A & 0x14) == 0x10) || ((A & 0x16) == 0x14))) {
+      return dis_neon_data_2reg_and_scalar(theInstr, condT);
+   }
+   if ((A & 0x16) == 0x16) {
+      if ((U == 0) && ((C & 1) == 0)) {
+         return dis_neon_vext(theInstr, condT);
+      }
+      if ((U != 1) || ((C & 1) == 1))
+         return False;
+      if ((B & 8) == 0) {
+         return dis_neon_data_2reg_misc(theInstr, condT);
+      }
+      if ((B & 12) == 8) {
+         return dis_neon_vtb(theInstr, condT);
+      }
+      if ((B == 12) && ((C & 9) == 0)) {
+         return dis_neon_vdup(theInstr, condT);
+      }
+   }
+   return False;
+}
+
+
+/*------------------------------------------------------------*/
+/*--- NEON loads and stores                                ---*/
+/*------------------------------------------------------------*/
+
+/* For NEON memory operations, we use the standard scheme to handle
+   conditionalisation: generate a jump around the instruction if the
+   condition is false.  That's only necessary in Thumb mode, however,
+   since in ARM mode NEON instructions are unconditional. */
+
+/* A helper function for what follows.  It assumes we already went
+   uncond as per comments at the top of this section. */
+static
+void mk_neon_elem_load_to_one_lane( UInt rD, UInt inc, UInt index,
+                                    UInt N, UInt size, IRTemp addr )
+{
+   UInt i;
+   switch (size) {
+      case 0:
+         putDRegI64(rD, triop(Iop_SetElem8x8, getDRegI64(rD), mkU8(index),
+                    loadLE(Ity_I8, mkexpr(addr))), IRTemp_INVALID);
+         break;
+      case 1:
+         putDRegI64(rD, triop(Iop_SetElem16x4, getDRegI64(rD), mkU8(index),
+                    loadLE(Ity_I16, mkexpr(addr))), IRTemp_INVALID);
+         break;
+      case 2:
+         putDRegI64(rD, triop(Iop_SetElem32x2, getDRegI64(rD), mkU8(index),
+                    loadLE(Ity_I32, mkexpr(addr))), IRTemp_INVALID);
+         break;
+      default:
+         vassert(0);
+   }
+   for (i = 1; i <= N; i++) {
+      switch (size) {
+         case 0:
+            putDRegI64(rD + i * inc,
+                       triop(Iop_SetElem8x8,
+                             getDRegI64(rD + i * inc),
+                             mkU8(index),
+                             loadLE(Ity_I8, binop(Iop_Add32,
+                                                  mkexpr(addr),
+                                                  mkU32(i * 1)))),
+                       IRTemp_INVALID);
+            break;
+         case 1:
+            putDRegI64(rD + i * inc,
+                       triop(Iop_SetElem16x4,
+                             getDRegI64(rD + i * inc),
+                             mkU8(index),
+                             loadLE(Ity_I16, binop(Iop_Add32,
+                                                   mkexpr(addr),
+                                                   mkU32(i * 2)))),
+                       IRTemp_INVALID);
+            break;
+         case 2:
+            putDRegI64(rD + i * inc,
+                       triop(Iop_SetElem32x2,
+                             getDRegI64(rD + i * inc),
+                             mkU8(index),
+                             loadLE(Ity_I32, binop(Iop_Add32,
+                                                   mkexpr(addr),
+                                                   mkU32(i * 4)))),
+                       IRTemp_INVALID);
+            break;
+         default:
+            vassert(0);
+      }
+   }
+}
+
+/* A(nother) helper function for what follows.  It assumes we already
+   went uncond as per comments at the top of this section. */
+static
+void mk_neon_elem_store_from_one_lane( UInt rD, UInt inc, UInt index,
+                                       UInt N, UInt size, IRTemp addr )
+{
+   UInt i;
+   switch (size) {
+      case 0:
+         storeLE(mkexpr(addr),
+                 binop(Iop_GetElem8x8, getDRegI64(rD), mkU8(index)));
+         break;
+      case 1:
+         storeLE(mkexpr(addr),
+                 binop(Iop_GetElem16x4, getDRegI64(rD), mkU8(index)));
+         break;
+      case 2:
+         storeLE(mkexpr(addr),
+                 binop(Iop_GetElem32x2, getDRegI64(rD), mkU8(index)));
+         break;
+      default:
+         vassert(0);
+   }
+   for (i = 1; i <= N; i++) {
+      switch (size) {
+         case 0:
+            storeLE(binop(Iop_Add32, mkexpr(addr), mkU32(i * 1)),
+                    binop(Iop_GetElem8x8, getDRegI64(rD + i * inc),
+                                          mkU8(index)));
+            break;
+         case 1:
+            storeLE(binop(Iop_Add32, mkexpr(addr), mkU32(i * 2)),
+                    binop(Iop_GetElem16x4, getDRegI64(rD + i * inc),
+                                           mkU8(index)));
+            break;
+         case 2:
+            storeLE(binop(Iop_Add32, mkexpr(addr), mkU32(i * 4)),
+                    binop(Iop_GetElem32x2, getDRegI64(rD + i * inc),
+                                           mkU8(index)));
+            break;
+         default:
+            vassert(0);
+      }
+   }
+}
+
+/* A7.7 Advanced SIMD element or structure load/store instructions */
+static
+Bool dis_neon_elem_or_struct_load ( UInt theInstr,
+                                    Bool isT, IRTemp condT )
+{
+#  define INSN(_bMax,_bMin)  SLICE_UInt(theInstr, (_bMax), (_bMin))
+   UInt A = INSN(23,23);
+   UInt B = INSN(11,8);
+   UInt L = INSN(21,21);
+   UInt rD = (INSN(22,22) << 4) | INSN(15,12);
+   UInt rN = INSN(19,16);
+   UInt rM = INSN(3,0);
+   UInt N, size, i, j;
+   UInt inc;
+   UInt regs = 1;
+   IRTemp addr;
+
+   if (isT) {
+      vassert(condT != IRTemp_INVALID);
+   } else {
+      vassert(condT == IRTemp_INVALID);
+   }
+   /* So now, if condT is not IRTemp_INVALID, we know we're
+      dealing with Thumb code. */
+
+   if (INSN(20,20) != 0)
+      return False;
+
+   if (A) {
+      N = B & 3;
+      if ((B >> 2) < 3) {
+         /* VSTn / VLDn (n-element structure from/to one lane) */
+
+         size = B >> 2;
+
+         switch (size) {
+            case 0: i = INSN(7,5); inc = 1; break;
+            case 1: i = INSN(7,6); inc = INSN(5,5) ? 2 : 1; break;
+            case 2: i = INSN(7,7); inc = INSN(6,6) ? 2 : 1; break;
+            case 3: return False;
+            default: vassert(0);
+         }
+
+         addr = newTemp(Ity_I32);
+         assign(addr, isT ? getIRegT(rN) : getIRegA(rN));
+
+         // go uncond
+         if (condT != IRTemp_INVALID)
+            mk_skip_over_T32_if_cond_is_false(condT);
+         // now uncond
+
+         if (L)
+            mk_neon_elem_load_to_one_lane(rD, inc, i, N, size, addr);
+         else
+            mk_neon_elem_store_from_one_lane(rD, inc, i, N, size, addr);
+         DIP("v%s%u.%u {", L ? "ld" : "st", N + 1, 8 << size);
+         for (j = 0; j <= N; j++) {
+            if (j)
+               DIP(", ");
+            DIP("d%u[%u]", rD + j * inc, i);
+         }
+            DIP("}, [r%u]%s\n", rN, (rM != 15) ? "!" : "");
+      } else {
+         /* VLDn (single element to all lanes) */
+         UInt r;
+         if (L == 0)
+            return False;
+
+         inc = INSN(5,5) + 1;
+         size = INSN(7,6);
+
+         /* size == 3 and size == 2 cases differ in alignment constraints */
+         if (size == 3 && N == 3 && INSN(4,4) == 1)
+            size = 2;
+
+         if (size == 0 && N == 0 && INSN(4,4) == 1)
+            return False;
+         if (N == 2 && INSN(4,4) == 1)
+            return False;
+         if (size == 3)
+            return False;
+
+         // go uncond
+         if (condT != IRTemp_INVALID)
+            mk_skip_over_T32_if_cond_is_false(condT);
+         // now uncond
+
+         addr = newTemp(Ity_I32);
+         assign(addr, isT ? getIRegT(rN) : getIRegA(rN));
+
+         if (N == 0 && INSN(5,5))
+            regs = 2;
+
+         for (r = 0; r < regs; r++) {
+            switch (size) {
+               case 0:
+                  putDRegI64(rD + r, unop(Iop_Dup8x8,
+                                          loadLE(Ity_I8, mkexpr(addr))),
+                             IRTemp_INVALID);
+                  break;
+               case 1:
+                  putDRegI64(rD + r, unop(Iop_Dup16x4,
+                                          loadLE(Ity_I16, mkexpr(addr))),
+                             IRTemp_INVALID);
+                  break;
+               case 2:
+                  putDRegI64(rD + r, unop(Iop_Dup32x2,
+                                          loadLE(Ity_I32, mkexpr(addr))),
+                             IRTemp_INVALID);
+                  break;
+               default:
+                  vassert(0);
+            }
+            for (i = 1; i <= N; i++) {
+               switch (size) {
+                  case 0:
+                     putDRegI64(rD + r + i * inc,
+                                unop(Iop_Dup8x8,
+                                     loadLE(Ity_I8, binop(Iop_Add32,
+                                                          mkexpr(addr),
+                                                          mkU32(i * 1)))),
+                                IRTemp_INVALID);
+                     break;
+                  case 1:
+                     putDRegI64(rD + r + i * inc,
+                                unop(Iop_Dup16x4,
+                                     loadLE(Ity_I16, binop(Iop_Add32,
+                                                           mkexpr(addr),
+                                                           mkU32(i * 2)))),
+                                IRTemp_INVALID);
+                     break;
+                  case 2:
+                     putDRegI64(rD + r + i * inc,
+                                unop(Iop_Dup32x2,
+                                     loadLE(Ity_I32, binop(Iop_Add32,
+                                                           mkexpr(addr),
+                                                           mkU32(i * 4)))),
+                                IRTemp_INVALID);
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+         }
+         DIP("vld%u.%u {", N + 1, 8 << size);
+         for (r = 0; r < regs; r++) {
+            for (i = 0; i <= N; i++) {
+               if (i || r)
+                  DIP(", ");
+               DIP("d%u[]", rD + r + i * inc);
+            }
+         }
+         DIP("}, [r%u]%s\n", rN, (rM != 15) ? "!" : "");
+      }
+      /* Writeback.  We're uncond here, so no condT-ing. */
+      if (rM != 15) {
+         if (rM == 13) {
+            IRExpr* e = binop(Iop_Add32,
+                              mkexpr(addr),
+                              mkU32((1 << size) * (N + 1)));
+            if (isT)
+               putIRegT(rN, e, IRTemp_INVALID);
+            else
+               putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
+         } else {
+            IRExpr* e = binop(Iop_Add32, mkexpr(addr),
+                              isT ? getIRegT(rM) : getIRegA(rM));
+            if (isT)
+               putIRegT(rN, e, IRTemp_INVALID);
+            else
+               putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
+         }
+      }
+      return True;
+   } else {
+      IRTemp tmp;
+      UInt r, elems;
+      /* VSTn / VLDn (multiple n-element structures) */
+      if (B == BITS4(0,0,1,0) || B == BITS4(0,1,1,0)
+          || B == BITS4(0,1,1,1) || B == BITS4(1,0,1,0)) {
+         N = 0;
+      } else if (B == BITS4(0,0,1,1) || B == BITS4(1,0,0,0)
+                 || B == BITS4(1,0,0,1)) {
+         N = 1;
+      } else if (B == BITS4(0,1,0,0) || B == BITS4(0,1,0,1)) {
+         N = 2;
+      } else if (B == BITS4(0,0,0,0) || B == BITS4(0,0,0,1)) {
+         N = 3;
+      } else {
+         return False;
+      }
+      inc = (B & 1) + 1;
+      if (N == 1 && B == BITS4(0,0,1,1)) {
+         regs = 2;
+      } else if (N == 0) {
+         if (B == BITS4(1,0,1,0)) {
+            regs = 2;
+         } else if (B == BITS4(0,1,1,0)) {
+            regs = 3;
+         } else if (B == BITS4(0,0,1,0)) {
+            regs = 4;
+         }
+      }
+
+      size = INSN(7,6);
+      if (N == 0 && size == 3)
+         size = 2;
+      if (size == 3)
+         return False;
+
+      elems = 8 / (1 << size);
+
+      // go uncond
+      if (condT != IRTemp_INVALID)
+         mk_skip_over_T32_if_cond_is_false(condT);
+      // now uncond
+
+      addr = newTemp(Ity_I32);
+      assign(addr, isT ? getIRegT(rN) : getIRegA(rN));
+
+      for (r = 0; r < regs; r++) {
+         for (i = 0; i < elems; i++) {
+            if (L)
+               mk_neon_elem_load_to_one_lane(rD + r, inc, i, N, size, addr);
+            else
+               mk_neon_elem_store_from_one_lane(rD + r, inc, i, N, size, addr);
+            tmp = newTemp(Ity_I32);
+            assign(tmp, binop(Iop_Add32, mkexpr(addr),
+                                         mkU32((1 << size) * (N + 1))));
+            addr = tmp;
+         }
+      }
+      /* Writeback */
+      if (rM != 15) {
+         if (rM == 13) {
+            IRExpr* e = binop(Iop_Add32,
+                              mkexpr(addr),
+                              mkU32(8 * (N + 1) * regs));
+            if (isT)
+               putIRegT(rN, e, IRTemp_INVALID);
+            else
+               putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
+         } else {
+            IRExpr* e = binop(Iop_Add32, mkexpr(addr),
+                              isT ? getIRegT(rM) : getIRegA(rM));
+            if (isT)
+               putIRegT(rN, e, IRTemp_INVALID);
+            else
+               putIRegA(rN, e, IRTemp_INVALID, Ijk_Boring);
+         }
+      }
+      DIP("v%s%u.%u {", L ? "ld" : "st", N + 1, 8 << INSN(7,6));
+      if ((inc == 1 && regs * (N + 1) > 1)
+          || (inc == 2 && regs > 1 && N > 0)) {
+         DIP("d%u-d%u", rD, rD + regs * (N + 1) - 1);
+      } else {
+         for (r = 0; r < regs; r++) {
+            for (i = 0; i <= N; i++) {
+               if (i || r)
+                  DIP(", ");
+               DIP("d%u", rD + r + i * inc);
+            }
+         }
+      }
+      DIP("}, [r%u]%s\n", rN, (rM != 15) ? "!" : "");
+      return True;
+   }
+#  undef INSN
+}
+
+
+/*------------------------------------------------------------*/
+/*--- NEON, top level control                              ---*/
+/*------------------------------------------------------------*/
+
+/* Both ARM and Thumb */
+
+/* Translate a NEON instruction.    If successful, returns
+   True and *dres may or may not be updated.  If failure, returns
+   False and doesn't change *dres nor create any IR.
+
+   The Thumb and ARM encodings are similar for the 24 bottom bits, but
+   the top 8 bits are slightly different.  In both cases, the caller
+   must pass the entire 32 bits.  Callers may pass any instruction;
+   this ignores non-NEON ones.
+
+   Caller must supply an IRTemp 'condT' holding the gating condition,
+   or IRTemp_INVALID indicating the insn is always executed.  In ARM
+   code, this must always be IRTemp_INVALID because NEON insns are
+   unconditional for ARM.
+
+   Finally, the caller must indicate whether this occurs in ARM or in
+   Thumb code.
+*/
+static Bool decode_NEON_instruction (
+               /*MOD*/DisResult* dres,
+               UInt              insn32,
+               IRTemp            condT,
+               Bool              isT
+            )
+{
+#  define INSN(_bMax,_bMin)  SLICE_UInt(insn32, (_bMax), (_bMin))
+
+   /* There are two kinds of instruction to deal with: load/store and
+      data processing.  In each case, in ARM mode we merely identify
+      the kind, and pass it on to the relevant sub-handler.  In Thumb
+      mode we identify the kind, swizzle the bits around to make it
+      have the same encoding as in ARM, and hand it on to the
+      sub-handler.
+   */
+
+   /* In ARM mode, NEON instructions can't be conditional. */
+   if (!isT)
+      vassert(condT == IRTemp_INVALID);
+
+   /* Data processing:
+      Thumb: 111U 1111 AAAA Axxx xxxx BBBB CCCC xxxx
+      ARM:   1111 001U AAAA Axxx xxxx BBBB CCCC xxxx
+   */
+   if (!isT && INSN(31,25) == BITS7(1,1,1,1,0,0,1)) {
+      // ARM, DP
+      return dis_neon_data_processing(INSN(31,0), condT);
+   }
+   if (isT && INSN(31,29) == BITS3(1,1,1)
+       && INSN(27,24) == BITS4(1,1,1,1)) {
+      // Thumb, DP
+      UInt reformatted = INSN(23,0);
+      reformatted |= (INSN(28,28) << 24); // U bit
+      reformatted |= (BITS7(1,1,1,1,0,0,1) << 25);
+      return dis_neon_data_processing(reformatted, condT);
+   }
+
+   /* Load/store:
+      Thumb: 1111 1001 AxL0 xxxx xxxx BBBB xxxx xxxx
+      ARM:   1111 0100 AxL0 xxxx xxxx BBBB xxxx xxxx
+   */
+   if (!isT && INSN(31,24) == BITS8(1,1,1,1,0,1,0,0)) {
+      // ARM, memory
+      return dis_neon_elem_or_struct_load(INSN(31,0), isT, condT);
+   }
+   if (isT && INSN(31,24) == BITS8(1,1,1,1,1,0,0,1)) {
+      UInt reformatted = INSN(23,0);
+      reformatted |= (BITS8(1,1,1,1,0,1,0,0) << 24);
+      return dis_neon_elem_or_struct_load(reformatted, isT, condT);
+   }
+
+   /* Doesn't match. */
+   return False;
+
+#  undef INSN
+}
+
+
+/*------------------------------------------------------------*/
+/*--- LDMxx/STMxx helper (both ARM and Thumb32)            ---*/
+/*------------------------------------------------------------*/
+
+/* Generate IR for LDMxx and STMxx.  This is complex.  Assumes it's
+   unconditional, so the caller must produce a jump-around before
+   calling this, if the insn is to be conditional.  Caller is
+   responsible for all validation of parameters.  For LDMxx, if PC is
+   amongst the values loaded, caller is also responsible for
+   generating the jump. */
+static void mk_ldm_stm ( Bool arm,     /* True: ARM, False: Thumb */
+                         UInt rN,      /* base reg */
+                         UInt bINC,    /* 1: inc,  0: dec */
+                         UInt bBEFORE, /* 1: inc/dec before, 0: after */
+                         UInt bW,      /* 1: writeback to Rn */
+                         UInt bL,      /* 1: load, 0: store */
+                         UInt regList )
+{
+   Int i, r, m, nRegs;
+
+   /* Get hold of the old Rn value.  We might need to write its value
+      to memory during a store, and if it's also the writeback
+      register then we need to get its value now.  We can't treat it
+      exactly like the other registers we're going to transfer,
+      because for xxMDA and xxMDB writeback forms, the generated IR
+      updates Rn in the guest state before any transfers take place.
+      We have to do this as per comments below, in order that if Rn is
+      the stack pointer then it always has a value is below or equal
+      to any of the transfer addresses.  Ick. */
+   IRTemp oldRnT = newTemp(Ity_I32);
+   assign(oldRnT, arm ? getIRegA(rN) : getIRegT(rN));
+
+   IRTemp anchorT = newTemp(Ity_I32);
+   /* The old (Addison-Wesley) ARM ARM seems to say that LDMxx/STMxx
+      ignore the bottom two bits of the address.  However, Cortex-A8
+      doesn't seem to care.  Hence: */
+   /* No .. don't force alignment .. */
+   /* assign(anchorT, binop(Iop_And32, mkexpr(oldRnT), mkU32(~3U))); */
+   /* Instead, use the potentially misaligned address directly. */
+   assign(anchorT, mkexpr(oldRnT));
+
+   IROp opADDorSUB = bINC ? Iop_Add32 : Iop_Sub32;
+   // bINC == 1:  xxMIA, xxMIB
+   // bINC == 0:  xxMDA, xxMDB
+
+   // For xxMDA and xxMDB, update Rn first if necessary.  We have
+   // to do this first so that, for the common idiom of the transfers
+   // faulting because we're pushing stuff onto a stack and the stack
+   // is growing down onto allocate-on-fault pages (as Valgrind simulates),
+   // we need to have the SP up-to-date "covering" (pointing below) the
+   // transfer area.  For the same reason, if we are doing xxMIA or xxMIB,
+   // do the transfer first, and then update rN afterwards.
+   nRegs = 0;
+   for (i = 0; i < 16; i++) {
+     if ((regList & (1 << i)) != 0)
+         nRegs++;
+   }
+   if (bW == 1 && !bINC) {
+      IRExpr* e = binop(opADDorSUB, mkexpr(oldRnT), mkU32(4*nRegs));
+      if (arm)
+         putIRegA( rN, e, IRTemp_INVALID, Ijk_Boring );
+      else
+         putIRegT( rN, e, IRTemp_INVALID );
+   }
+
+   // Make up a list of the registers to transfer, and their offsets
+   // in memory relative to the anchor.  If the base reg (Rn) is part
+   // of the transfer, then do it last for a load and first for a store.
+   UInt xReg[16], xOff[16];
+   Int  nX = 0;
+   m = 0;
+   for (i = 0; i < 16; i++) {
+      r = bINC ? i : (15-i);
+      if (0 == (regList & (1<<r)))
+         continue;
+      if (bBEFORE)
+         m++;
+      /* paranoia: check we aren't transferring the writeback
+         register during a load. Should be assured by decode-point
+         check above. */
+      if (bW == 1 && bL == 1)
+         vassert(r != rN);
+
+      xOff[nX] = 4 * m;
+      xReg[nX] = r;
+      nX++;
+
+      if (!bBEFORE)
+         m++;
+   }
+   vassert(m == nRegs);
+   vassert(nX == nRegs);
+   vassert(nX <= 16);
+
+   if (bW == 0 && (regList & (1<<rN)) != 0) {
+      /* Non-writeback, and basereg is to be transferred.  Do its
+         transfer last for a load and first for a store.  Requires
+         reordering xOff/xReg. */
+      if (0) {
+         vex_printf("\nREG_LIST_PRE: (rN=%d)\n", rN);
+         for (i = 0; i < nX; i++)
+            vex_printf("reg %d   off %d\n", xReg[i], xOff[i]);
+         vex_printf("\n");
+      }
+
+      vassert(nX > 0);
+      for (i = 0; i < nX; i++) {
+         if (xReg[i] == rN)
+             break;
+      }
+      vassert(i < nX); /* else we didn't find it! */
+      UInt tReg = xReg[i];
+      UInt tOff = xOff[i];
+      if (bL == 1) {
+         /* load; make this transfer happen last */
+         if (i < nX-1) {
+            for (m = i+1; m < nX; m++) {
+               xReg[m-1] = xReg[m];
+               xOff[m-1] = xOff[m];
+            }
+            vassert(m == nX);
+            xReg[m-1] = tReg;
+            xOff[m-1] = tOff;
+         }
+      } else {
+         /* store; make this transfer happen first */
+         if (i > 0) {
+            for (m = i-1; m >= 0; m--) {
+               xReg[m+1] = xReg[m];
+               xOff[m+1] = xOff[m];
+            }
+            vassert(m == -1);
+            xReg[0] = tReg;
+            xOff[0] = tOff;
+         }
+      }
+
+      if (0) {
+         vex_printf("REG_LIST_POST:\n");
+         for (i = 0; i < nX; i++)
+            vex_printf("reg %d   off %d\n", xReg[i], xOff[i]);
+         vex_printf("\n");
+      }
+   }
+
+   /* Actually generate the transfers */
+   for (i = 0; i < nX; i++) {
+      r = xReg[i];
+      if (bL == 1) {
+         IRExpr* e = loadLE(Ity_I32,
+                            binop(opADDorSUB, mkexpr(anchorT),
+                                  mkU32(xOff[i])));
+         if (arm) {
+            putIRegA( r, e, IRTemp_INVALID, Ijk_Ret );
+         } else {
+            // no: putIRegT( r, e, IRTemp_INVALID );
+            // putIRegT refuses to write to R15.  But that might happen.
+            // Since this is uncond, and we need to be able to
+            // write the PC, just use the low level put:
+            llPutIReg( r, e );
+         }
+      } else {
+         /* if we're storing Rn, make sure we use the correct
+            value, as per extensive comments above */
+         storeLE( binop(opADDorSUB, mkexpr(anchorT), mkU32(xOff[i])),
+                  r == rN ? mkexpr(oldRnT) 
+                          : (arm ? getIRegA(r) : getIRegT(r) ) );
+      }
+   }
+
+   // If we are doing xxMIA or xxMIB,
+   // do the transfer first, and then update rN afterwards.
+   if (bW == 1 && bINC) {
+      IRExpr* e = binop(opADDorSUB, mkexpr(oldRnT), mkU32(4*nRegs));
+      if (arm)
+         putIRegA( rN, e, IRTemp_INVALID, Ijk_Boring );
+      else
+         putIRegT( rN, e, IRTemp_INVALID );
+   }
+}
+
+
+/*------------------------------------------------------------*/
+/*--- VFP (CP 10 and 11) instructions                      ---*/
+/*------------------------------------------------------------*/
+
+/* Both ARM and Thumb */
+
+/* Translate a CP10 or CP11 instruction.  If successful, returns
+   True and *dres may or may not be updated.  If failure, returns
+   False and doesn't change *dres nor create any IR.
+
+   The ARM and Thumb encodings are identical for the low 28 bits of
+   the insn (yay!) and that's what the caller must supply, iow, imm28
+   has the top 4 bits masked out.  Caller is responsible for
+   determining whether the masked-out bits are valid for a CP10/11
+   insn.  The rules for the top 4 bits are:
+
+     ARM: 0000 to 1110 allowed, and this is the gating condition.
+     1111 (NV) is not allowed.
+
+     Thumb: must be 1110.  The gating condition is taken from
+     ITSTATE in the normal way.
+
+   Conditionalisation:
+
+   Caller must supply an IRTemp 'condT' holding the gating condition,
+   or IRTemp_INVALID indicating the insn is always executed.
+
+   Caller must also supply an ARMCondcode 'cond'.  This is only used
+   for debug printing, no other purpose.  For ARM, this is simply the
+   top 4 bits of the original instruction.  For Thumb, the condition
+   is not (really) known until run time, and so ARMCondAL should be
+   passed, only so that printing of these instructions does not show
+   any condition.
+
+   Finally, the caller must indicate whether this occurs in ARM or
+   Thumb code.
+*/
+static Bool decode_CP10_CP11_instruction (
+               /*MOD*/DisResult* dres,
+               UInt              insn28,
+               IRTemp            condT,
+               ARMCondcode       conq,
+               Bool              isT
+            )
+{
+#  define INSN(_bMax,_bMin)  SLICE_UInt(insn28, (_bMax), (_bMin))
+
+   vassert(INSN(31,28) == BITS4(0,0,0,0)); // caller's obligation
+
+   if (isT) {
+      vassert(conq == ARMCondAL);
+   } else {
+      vassert(conq >= ARMCondEQ && conq <= ARMCondAL);
+   }
+
+   /* ----------------------------------------------------------- */
+   /* -- VFP instructions -- double precision (mostly)         -- */
+   /* ----------------------------------------------------------- */
+
+   /* --------------------- fldmx, fstmx --------------------- */
+   /*
+                                 31   27   23   19 15 11   7   0
+                                         P U WL
+      C4-100, C5-26  1  FSTMX    cond 1100 1000 Rn Dd 1011 offset
+      C4-100, C5-28  2  FSTMIAX  cond 1100 1010 Rn Dd 1011 offset
+      C4-100, C5-30  3  FSTMDBX  cond 1101 0010 Rn Dd 1011 offset
+
+      C4-42, C5-26   1  FLDMX    cond 1100 1001 Rn Dd 1011 offset
+      C4-42, C5-28   2  FLDMIAX  cond 1100 1011 Rn Dd 1011 offset
+      C4-42, C5-30   3  FLDMDBX  cond 1101 0011 Rn Dd 1011 offset
+
+      Regs transferred: Dd .. D(d + (offset-3)/2)
+      offset must be odd, must not imply a reg > 15
+      IA/DB: Rn is changed by (4 + 8 x # regs transferred)
+
+      case coding:
+         1  at-Rn   (access at Rn)
+         2  ia-Rn   (access at Rn, then Rn += 4+8n)
+         3  db-Rn   (Rn -= 4+8n,   then access at Rn)
+   */
+   if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))
+       && INSN(11,8) == BITS4(1,0,1,1)) {
+      UInt bP      = (insn28 >> 24) & 1;
+      UInt bU      = (insn28 >> 23) & 1;
+      UInt bW      = (insn28 >> 21) & 1;
+      UInt bL      = (insn28 >> 20) & 1;
+      UInt offset  = (insn28 >> 0) & 0xFF;
+      UInt rN      = INSN(19,16);
+      UInt dD      = (INSN(22,22) << 4) | INSN(15,12);
+      UInt nRegs   = (offset - 1) / 2;
+      UInt summary = 0;
+      Int  i;
+
+      /**/ if (bP == 0 && bU == 1 && bW == 0) {
+         summary = 1;
+      }
+      else if (bP == 0 && bU == 1 && bW == 1) {
+         summary = 2;
+      }
+      else if (bP == 1 && bU == 0 && bW == 1) {
+         summary = 3;
+      }
+      else goto after_vfp_fldmx_fstmx;
+
+      /* no writebacks to r15 allowed.  No use of r15 in thumb mode. */
+      if (rN == 15 && (summary == 2 || summary == 3 || isT))
+         goto after_vfp_fldmx_fstmx;
+
+      /* offset must be odd, and specify at least one register */
+      if (0 == (offset & 1) || offset < 3)
+         goto after_vfp_fldmx_fstmx;
+
+      /* can't transfer regs after D15 */
+      if (dD + nRegs - 1 >= 32)
+         goto after_vfp_fldmx_fstmx;
+
+      /* Now, we can't do a conditional load or store, since that very
+         likely will generate an exception.  So we have to take a side
+         exit at this point if the condition is false. */
+      if (condT != IRTemp_INVALID) {
+         if (isT)
+            mk_skip_over_T32_if_cond_is_false( condT );
+         else
+            mk_skip_over_A32_if_cond_is_false( condT );
+         condT = IRTemp_INVALID;
+      }
+      /* Ok, now we're unconditional.  Do the load or store. */
+
+      /* get the old Rn value */
+      IRTemp rnT = newTemp(Ity_I32);
+      assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN),
+                           rN == 15));
+
+      /* make a new value for Rn, post-insn */
+      IRTemp rnTnew = IRTemp_INVALID;
+      if (summary == 2 || summary == 3) {
+         rnTnew = newTemp(Ity_I32);
+         assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32,
+                              mkexpr(rnT),
+                              mkU32(4 + 8 * nRegs)));
+      }
+
+      /* decide on the base transfer address */
+      IRTemp taT = newTemp(Ity_I32);
+      assign(taT,  summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT));
+
+      /* update Rn if necessary -- in case 3, we're moving it down, so
+         update before any memory reference, in order to keep Memcheck
+         and V's stack-extending logic (on linux) happy */
+      if (summary == 3) {
+         if (isT)
+            putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
+         else
+            putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+      }
+
+      /* generate the transfers */
+      for (i = 0; i < nRegs; i++) {
+         IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(8*i));
+         if (bL) {
+            putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID);
+         } else {
+            storeLE(addr, getDReg(dD + i));
+         }
+      }
+
+      /* update Rn if necessary -- in case 2, we're moving it up, so
+         update after any memory reference, in order to keep Memcheck
+         and V's stack-extending logic (on linux) happy */
+      if (summary == 2) {
+         if (isT)
+            putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
+         else
+            putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+      }
+
+      HChar* nm = bL==1 ? "ld" : "st";
+      switch (summary) {
+         case 1:  DIP("f%smx%s r%u, {d%u-d%u}\n", 
+                      nm, nCC(conq), rN, dD, dD + nRegs - 1);
+                  break;
+         case 2:  DIP("f%smiax%s r%u!, {d%u-d%u}\n", 
+                      nm, nCC(conq), rN, dD, dD + nRegs - 1);
+                  break;
+         case 3:  DIP("f%smdbx%s r%u!, {d%u-d%u}\n", 
+                      nm, nCC(conq), rN, dD, dD + nRegs - 1);
+                  break;
+         default: vassert(0);
+      }
+
+      goto decode_success_vfp;
+      /* FIXME alignment constraints? */
+   }
+
+  after_vfp_fldmx_fstmx:
+
+   /* --------------------- fldmd, fstmd --------------------- */
+   /*
+                                 31   27   23   19 15 11   7   0
+                                         P U WL
+      C4-96, C5-26   1  FSTMD    cond 1100 1000 Rn Dd 1011 offset
+      C4-96, C5-28   2  FSTMDIA  cond 1100 1010 Rn Dd 1011 offset
+      C4-96, C5-30   3  FSTMDDB  cond 1101 0010 Rn Dd 1011 offset
+
+      C4-38, C5-26   1  FLDMD    cond 1100 1001 Rn Dd 1011 offset
+      C4-38, C5-28   2  FLDMIAD  cond 1100 1011 Rn Dd 1011 offset
+      C4-38, C5-30   3  FLDMDBD  cond 1101 0011 Rn Dd 1011 offset
+
+      Regs transferred: Dd .. D(d + (offset-2)/2)
+      offset must be even, must not imply a reg > 15
+      IA/DB: Rn is changed by (8 x # regs transferred)
+
+      case coding:
+         1  at-Rn   (access at Rn)
+         2  ia-Rn   (access at Rn, then Rn += 8n)
+         3  db-Rn   (Rn -= 8n,     then access at Rn)
+   */
+   if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))
+       && INSN(11,8) == BITS4(1,0,1,1)) {
+      UInt bP      = (insn28 >> 24) & 1;
+      UInt bU      = (insn28 >> 23) & 1;
+      UInt bW      = (insn28 >> 21) & 1;
+      UInt bL      = (insn28 >> 20) & 1;
+      UInt offset  = (insn28 >> 0) & 0xFF;
+      UInt rN      = INSN(19,16);
+      UInt dD      = (INSN(22,22) << 4) | INSN(15,12);
+      UInt nRegs   = offset / 2;
+      UInt summary = 0;
+      Int  i;
+
+      /**/ if (bP == 0 && bU == 1 && bW == 0) {
+         summary = 1;
+      }
+      else if (bP == 0 && bU == 1 && bW == 1) {
+         summary = 2;
+      }
+      else if (bP == 1 && bU == 0 && bW == 1) {
+         summary = 3;
+      }
+      else goto after_vfp_fldmd_fstmd;
+
+      /* no writebacks to r15 allowed.  No use of r15 in thumb mode. */
+      if (rN == 15 && (summary == 2 || summary == 3 || isT))
+         goto after_vfp_fldmd_fstmd;
+
+      /* offset must be even, and specify at least one register */
+      if (1 == (offset & 1) || offset < 2)
+         goto after_vfp_fldmd_fstmd;
+
+      /* can't transfer regs after D15 */
+      if (dD + nRegs - 1 >= 32)
+         goto after_vfp_fldmd_fstmd;
+
+      /* Now, we can't do a conditional load or store, since that very
+         likely will generate an exception.  So we have to take a side
+         exit at this point if the condition is false. */
+      if (condT != IRTemp_INVALID) {
+         if (isT)
+            mk_skip_over_T32_if_cond_is_false( condT );
+         else
+            mk_skip_over_A32_if_cond_is_false( condT );
+         condT = IRTemp_INVALID;
+      }
+      /* Ok, now we're unconditional.  Do the load or store. */
+
+      /* get the old Rn value */
+      IRTemp rnT = newTemp(Ity_I32);
+      assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN),
+                           rN == 15));
+
+      /* make a new value for Rn, post-insn */
+      IRTemp rnTnew = IRTemp_INVALID;
+      if (summary == 2 || summary == 3) {
+         rnTnew = newTemp(Ity_I32);
+         assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32,
+                              mkexpr(rnT),
+                              mkU32(8 * nRegs)));
+      }
+
+      /* decide on the base transfer address */
+      IRTemp taT = newTemp(Ity_I32);
+      assign(taT, summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT));
+
+      /* update Rn if necessary -- in case 3, we're moving it down, so
+         update before any memory reference, in order to keep Memcheck
+         and V's stack-extending logic (on linux) happy */
+      if (summary == 3) {
+         if (isT)
+            putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
+         else
+            putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+      }
+
+      /* generate the transfers */
+      for (i = 0; i < nRegs; i++) {
+         IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(8*i));
+         if (bL) {
+            putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID);
+         } else {
+            storeLE(addr, getDReg(dD + i));
+         }
+      }
+
+      /* update Rn if necessary -- in case 2, we're moving it up, so
+         update after any memory reference, in order to keep Memcheck
+         and V's stack-extending logic (on linux) happy */
+      if (summary == 2) {
+         if (isT)
+            putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
+         else
+            putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+      }
+
+      HChar* nm = bL==1 ? "ld" : "st";
+      switch (summary) {
+         case 1:  DIP("f%smd%s r%u, {d%u-d%u}\n", 
+                      nm, nCC(conq), rN, dD, dD + nRegs - 1);
+                  break;
+         case 2:  DIP("f%smiad%s r%u!, {d%u-d%u}\n", 
+                      nm, nCC(conq), rN, dD, dD + nRegs - 1);
+                  break;
+         case 3:  DIP("f%smdbd%s r%u!, {d%u-d%u}\n", 
+                      nm, nCC(conq), rN, dD, dD + nRegs - 1);
+                  break;
+         default: vassert(0);
+      }
+
+      goto decode_success_vfp;
+      /* FIXME alignment constraints? */
+   }
+
+  after_vfp_fldmd_fstmd:
+
+   /* ------------------- fmrx, fmxr ------------------- */
+   if (BITS8(1,1,1,0,1,1,1,1) == INSN(27,20)
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS8(0,0,0,1,0,0,0,0) == (insn28 & 0xFF)) {
+      UInt rD  = INSN(15,12);
+      UInt reg = INSN(19,16);
+      if (reg == BITS4(0,0,0,1)) {
+         if (rD == 15) {
+            IRTemp nzcvT = newTemp(Ity_I32);
+            /* When rD is 15, we are copying the top 4 bits of FPSCR
+               into CPSR.  That is, set the flags thunk to COPY and
+               install FPSCR[31:28] as the value to copy. */
+            assign(nzcvT, binop(Iop_And32,
+                                IRExpr_Get(OFFB_FPSCR, Ity_I32),
+                                mkU32(0xF0000000)));
+            setFlags_D1(ARMG_CC_OP_COPY, nzcvT, condT);
+            DIP("fmstat%s\n", nCC(conq));
+         } else {
+            /* Otherwise, merely transfer FPSCR to r0 .. r14. */
+            IRExpr* e = IRExpr_Get(OFFB_FPSCR, Ity_I32);
+            if (isT)
+               putIRegT(rD, e, condT);
+            else
+               putIRegA(rD, e, condT, Ijk_Boring);
+            DIP("fmrx%s r%u, fpscr\n", nCC(conq), rD);
+         }
+         goto decode_success_vfp;
+      }
+      /* fall through */
+   }
+
+   if (BITS8(1,1,1,0,1,1,1,0) == INSN(27,20)
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS8(0,0,0,1,0,0,0,0) == (insn28 & 0xFF)) {
+      UInt rD  = INSN(15,12);
+      UInt reg = INSN(19,16);
+      if (reg == BITS4(0,0,0,1)) {
+         putMiscReg32(OFFB_FPSCR,
+                      isT ? getIRegT(rD) : getIRegA(rD), condT);
+         DIP("fmxr%s fpscr, r%u\n", nCC(conq), rD);
+         goto decode_success_vfp;
+      }
+      /* fall through */
+   }
+
+   /* --------------------- vmov --------------------- */
+   // VMOV dM, rD, rN
+   if (0x0C400B10 == (insn28 & 0x0FF00FD0)) {
+      UInt dM = INSN(3,0) | (INSN(5,5) << 4);
+      UInt rD = INSN(15,12); /* lo32 */
+      UInt rN = INSN(19,16); /* hi32 */
+      if (rD == 15 || rN == 15) {
+         /* fall through */
+      } else {
+         putDReg(dM,
+                 unop(Iop_ReinterpI64asF64,
+                      binop(Iop_32HLto64,
+                            isT ? getIRegT(rN) : getIRegA(rN),
+                            isT ? getIRegT(rD) : getIRegA(rD))),
+                 condT);
+         DIP("vmov%s d%u, r%u, r%u\n", nCC(conq), dM, rD, rN);
+         goto decode_success_vfp;
+      }
+      /* fall through */
+   }
+
+   // VMOV rD, rN, dM
+   if (0x0C500B10 == (insn28 & 0x0FF00FD0)) {
+      UInt dM = INSN(3,0) | (INSN(5,5) << 4);
+      UInt rD = INSN(15,12); /* lo32 */
+      UInt rN = INSN(19,16); /* hi32 */
+      if (rD == 15 || rN == 15 || rD == rN) {
+         /* fall through */
+      } else {
+         IRTemp i64 = newTemp(Ity_I64);
+         assign(i64, unop(Iop_ReinterpF64asI64, getDReg(dM)));
+         IRExpr* hi32 = unop(Iop_64HIto32, mkexpr(i64));
+         IRExpr* lo32 = unop(Iop_64to32,   mkexpr(i64));
+         if (isT) {
+            putIRegT(rN, hi32, condT);
+            putIRegT(rD, lo32, condT);
+         } else {
+            putIRegA(rN, hi32, condT, Ijk_Boring);
+            putIRegA(rD, lo32, condT, Ijk_Boring);
+         }
+         DIP("vmov%s r%u, r%u, d%u\n", nCC(conq), rD, rN, dM);
+         goto decode_success_vfp;
+      }
+      /* fall through */
+   }
+
+   // VMOV rD[x], rT
+   if (0x0E000B10 == (insn28 & 0x0F900F1F)) {
+      UInt rD  = (INSN(7,7) << 4) | INSN(19,16);
+      UInt rT  = INSN(15,12);
+      UInt opc = (INSN(22,21) << 2) | INSN(6,5);
+      UInt index;
+      if (rT == 15) {
+         /* fall through */
+      } else {
+         if ((opc & BITS4(1,0,0,0)) == BITS4(1,0,0,0)) {
+            index = opc & 7;
+            putDRegI64(rD, triop(Iop_SetElem8x8,
+                                 getDRegI64(rD),
+                                 mkU8(index),
+                                 unop(Iop_32to8,
+                                      isT ? getIRegT(rT) : getIRegA(rT))),
+                           condT);
+            DIP("vmov%s.8 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
+            goto decode_success_vfp;
+         }
+         else if ((opc & BITS4(1,0,0,1)) == BITS4(0,0,0,1)) {
+            index = (opc >> 1) & 3;
+            putDRegI64(rD, triop(Iop_SetElem16x4,
+                                 getDRegI64(rD),
+                                 mkU8(index),
+                                 unop(Iop_32to16,
+                                      isT ? getIRegT(rT) : getIRegA(rT))),
+                           condT);
+            DIP("vmov%s.16 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
+            goto decode_success_vfp;
+         }
+         else if ((opc & BITS4(1,0,1,1)) == BITS4(0,0,0,0)) {
+            index = (opc >> 2) & 1;
+            putDRegI64(rD, triop(Iop_SetElem32x2,
+                                 getDRegI64(rD),
+                                 mkU8(index),
+                                 isT ? getIRegT(rT) : getIRegA(rT)),
+                           condT);
+            DIP("vmov%s.32 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
+            goto decode_success_vfp;
+         } else {
+            /* fall through */
+         }
+      }
+   }
+
+   // VMOV rT, rD[x]
+   if (0x0E100B10 == (insn28 & 0x0F100F1F)) {
+      UInt rN  = (INSN(7,7) << 4) | INSN(19,16);
+      UInt rT  = INSN(15,12);
+      UInt U   = INSN(23,23);
+      UInt opc = (INSN(22,21) << 2) | INSN(6,5);
+      UInt index;
+      if (rT == 15) {
+         /* fall through */
+      } else {
+         if ((opc & BITS4(1,0,0,0)) == BITS4(1,0,0,0)) {
+            index = opc & 7;
+            IRExpr* e = unop(U ? Iop_8Uto32 : Iop_8Sto32,
+                             binop(Iop_GetElem8x8,
+                                   getDRegI64(rN),
+                                   mkU8(index)));
+            if (isT)
+               putIRegT(rT, e, condT);
+            else
+               putIRegA(rT, e, condT, Ijk_Boring);
+            DIP("vmov%s.%c8 r%u, d%u[%u]\n", nCC(conq), U ? 'u' : 's',
+                  rT, rN, index);
+            goto decode_success_vfp;
+         }
+         else if ((opc & BITS4(1,0,0,1)) == BITS4(0,0,0,1)) {
+            index = (opc >> 1) & 3;
+            IRExpr* e = unop(U ? Iop_16Uto32 : Iop_16Sto32,
+                             binop(Iop_GetElem16x4,
+                                   getDRegI64(rN),
+                                   mkU8(index)));
+            if (isT)
+               putIRegT(rT, e, condT);
+            else
+               putIRegA(rT, e, condT, Ijk_Boring);
+            DIP("vmov%s.%c16 r%u, d%u[%u]\n", nCC(conq), U ? 'u' : 's',
+                  rT, rN, index);
+            goto decode_success_vfp;
+         }
+         else if ((opc & BITS4(1,0,1,1)) == BITS4(0,0,0,0) && U == 0) {
+            index = (opc >> 2) & 1;
+            IRExpr* e = binop(Iop_GetElem32x2, getDRegI64(rN), mkU8(index));
+            if (isT)
+               putIRegT(rT, e, condT);
+            else
+               putIRegA(rT, e, condT, Ijk_Boring);
+            DIP("vmov%s.32 r%u, d%u[%u]\n", nCC(conq), rT, rN, index);
+            goto decode_success_vfp;
+         } else {
+            /* fall through */
+         }
+      }
+   }
+
+   // VMOV.F32 sD, #imm
+   // FCONSTS sD, #imm
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(0,0,0,0) == INSN(7,4) && INSN(11,8) == BITS4(1,0,1,0)) {
+      UInt rD   = (INSN(15,12) << 1) | INSN(22,22);
+      UInt imm8 = (INSN(19,16) << 4) | INSN(3,0);
+      UInt b    = (imm8 >> 6) & 1;
+      UInt imm;
+      imm = (BITS8((imm8 >> 7) & 1,(~b) & 1,b,b,b,b,b,(imm8 >> 5) & 1) << 8)
+             | ((imm8 & 0x1f) << 3);
+      imm <<= 16;
+      putFReg(rD, unop(Iop_ReinterpI32asF32, mkU32(imm)), condT);
+      DIP("fconsts%s s%u #%u", nCC(conq), rD, imm8);
+      goto decode_success_vfp;
+   }
+
+   // VMOV.F64 dD, #imm
+   // FCONSTD dD, #imm
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(0,0,0,0) == INSN(7,4) && INSN(11,8) == BITS4(1,0,1,1)) {
+      UInt rD   = INSN(15,12) | (INSN(22,22) << 4);
+      UInt imm8 = (INSN(19,16) << 4) | INSN(3,0);
+      UInt b    = (imm8 >> 6) & 1;
+      ULong imm;
+      imm = (BITS8((imm8 >> 7) & 1,(~b) & 1,b,b,b,b,b,b) << 8)
+             | BITS8(b,b,0,0,0,0,0,0) | (imm8 & 0x3f);
+      imm <<= 48;
+      putDReg(rD, unop(Iop_ReinterpI64asF64, mkU64(imm)), condT);
+      DIP("fconstd%s d%u #%u", nCC(conq), rD, imm8);
+      goto decode_success_vfp;
+   }
+
+   /* ---------------------- vdup ------------------------- */
+   // VDUP dD, rT
+   // VDUP qD, rT
+   if (BITS8(1,1,1,0,1,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,0,1))
+       && BITS4(1,0,1,1) == INSN(11,8) && INSN(6,6) == 0 && INSN(4,4) == 1) {
+      UInt rD   = (INSN(7,7) << 4) | INSN(19,16);
+      UInt rT   = INSN(15,12);
+      UInt Q    = INSN(21,21);
+      UInt size = (INSN(22,22) << 1) | INSN(5,5);
+      if (rT == 15 || size == 3i || (Q && (rD & 1))) {
+         /* fall through */
+      } else {
+         IRExpr* e = isT ? getIRegT(rT) : getIRegA(rT);
+         if (Q) {
+            rD >>= 1;
+            switch (size) {
+               case 0:
+                  putQReg(rD, unop(Iop_Dup32x4, e), condT);
+                  break;
+               case 1:
+                  putQReg(rD, unop(Iop_Dup16x8, unop(Iop_32to16, e)),
+                              condT);
+                  break;
+               case 2:
+                  putQReg(rD, unop(Iop_Dup8x16, unop(Iop_32to8, e)),
+                              condT);
+                  break;
+               default:
+                  vassert(0);
+            }
+            DIP("vdup.%u q%u, r%u\n", 32 / (1<<size), rD, rT);
+         } else {
+            switch (size) {
+               case 0:
+                  putDRegI64(rD, unop(Iop_Dup32x2, e), condT);
+                  break;
+               case 1:
+                  putDRegI64(rD, unop(Iop_Dup16x4, unop(Iop_32to16, e)),
+                               condT);
+                  break;
+               case 2:
+                  putDRegI64(rD, unop(Iop_Dup8x8, unop(Iop_32to8, e)),
+                               condT);
+                  break;
+               default:
+                  vassert(0);
+            }
+            DIP("vdup.%u d%u, r%u\n", 32 / (1<<size), rD, rT);
+         }
+         goto decode_success_vfp;
+      }
+   }
+
+   /* --------------------- f{ld,st}d --------------------- */
+   // FLDD, FSTD
+   if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,0))
+       && BITS4(1,0,1,1) == INSN(11,8)) {
+      UInt dD     = INSN(15,12);
+      UInt rN     = INSN(19,16);
+      UInt offset = (insn28 & 0xFF) << 2;
+      UInt bU     = (insn28 >> 23) & 1; /* 1: +offset  0: -offset */
+      UInt bL     = (insn28 >> 20) & 1; /* 1: load  0: store */
+      /* make unconditional */
+      if (condT != IRTemp_INVALID) {
+         if (isT)
+            mk_skip_over_T32_if_cond_is_false( condT );
+         else
+            mk_skip_over_A32_if_cond_is_false( condT );
+         condT = IRTemp_INVALID;
+      }
+      IRTemp ea = newTemp(Ity_I32);
+      assign(ea, binop(bU ? Iop_Add32 : Iop_Sub32,
+                       align4if(isT ? getIRegT(rN) : getIRegA(rN),
+                                rN == 15),
+                       mkU32(offset)));
+      if (bL) {
+         putDReg(dD, loadLE(Ity_F64,mkexpr(ea)), IRTemp_INVALID);
+      } else {
+         storeLE(mkexpr(ea), getDReg(dD));
+      }
+      DIP("f%sd%s d%u, [r%u, %c#%u]\n",
+          bL ? "ld" : "st", nCC(conq), dD, rN,
+          bU ? '+' : '-', offset);
+      goto decode_success_vfp;
+   }
+
+   /* --------------------- dp insns (D) --------------------- */
+   if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,1,0,0))
+       && BITS4(1,0,1,1) == INSN(11,8)
+       && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(1,0,1,1))) {
+      UInt    dM  = INSN(3,0);   /* argR */
+      UInt    dD  = INSN(15,12); /* dst/acc */
+      UInt    dN  = INSN(19,16); /* argL */
+      UInt    bP  = (insn28 >> 23) & 1;
+      UInt    bQ  = (insn28 >> 21) & 1;
+      UInt    bR  = (insn28 >> 20) & 1;
+      UInt    bS  = (insn28 >> 6) & 1;
+      UInt    opc = (bP << 3) | (bQ << 2) | (bR << 1) | bS;
+      IRExpr* rm  = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
+      switch (opc) {
+         case BITS4(0,0,0,0): /* MAC: d + n * m */
+            putDReg(dD, triop(Iop_AddF64, rm,
+                              getDReg(dD),
+                              triop(Iop_MulF64, rm, getDReg(dN),
+                                                    getDReg(dM))),
+                        condT);
+            DIP("fmacd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         case BITS4(0,0,0,1): /* NMAC: d - n * m */
+            putDReg(dD, triop(Iop_SubF64, rm,
+                              getDReg(dD),
+                              triop(Iop_MulF64, rm, getDReg(dN),
+                                                    getDReg(dM))),
+                        condT);
+            DIP("fnmacd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         case BITS4(0,0,1,0): /* MSC: - d + n * m */
+            putDReg(dD, triop(Iop_AddF64, rm,
+                              unop(Iop_NegF64, getDReg(dD)),
+                              triop(Iop_MulF64, rm, getDReg(dN),
+                                                    getDReg(dM))),
+                        condT);
+            DIP("fmscd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         case BITS4(0,0,1,1): /* NMSC: - d - n * m */
+            putDReg(dD, triop(Iop_SubF64, rm,
+                              unop(Iop_NegF64, getDReg(dD)),
+                              triop(Iop_MulF64, rm, getDReg(dN),
+                                                    getDReg(dM))),
+                        condT);
+            DIP("fnmscd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         case BITS4(0,1,0,0): /* MUL: n * m */
+            putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)),
+                        condT);
+            DIP("fmuld%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         case BITS4(0,1,0,1): /* NMUL: - n * m */
+            putDReg(dD, unop(Iop_NegF64,
+                             triop(Iop_MulF64, rm, getDReg(dN),
+                                                   getDReg(dM))),
+                    condT);
+            DIP("fnmuld%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         case BITS4(0,1,1,0): /* ADD: n + m */
+            putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)),
+                        condT);
+            DIP("faddd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         case BITS4(0,1,1,1): /* SUB: n - m */
+            putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)),
+                        condT);
+            DIP("fsubd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         case BITS4(1,0,0,0): /* DIV: n / m */
+            putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)),
+                        condT);
+            DIP("fdivd%s d%u, d%u, d%u\n", nCC(conq), dD, dN, dM);
+            goto decode_success_vfp;
+         default:
+            break;
+      }
+   }
+
+   /* --------------------- compares (D) --------------------- */
+   /*          31   27   23   19   15 11   7    3
+                 28   24   20   16 12    8    4    0 
+      FCMPD    cond 1110 1011 0100 Dd 1011 0100 Dm
+      FCMPED   cond 1110 1011 0100 Dd 1011 1100 Dm
+      FCMPZD   cond 1110 1011 0101 Dd 1011 0100 0000
+      FCMPZED  cond 1110 1011 0101 Dd 1011 1100 0000
+                                 Z         N
+
+      Z=0 Compare Dd vs Dm     and set FPSCR 31:28 accordingly
+      Z=1 Compare Dd vs zero
+
+      N=1 generates Invalid Operation exn if either arg is any kind of NaN
+      N=0 generates Invalid Operation exn if either arg is a signalling NaN
+      (Not that we pay any attention to N here)
+   */
+   if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
+       && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+       && BITS4(1,0,1,1) == INSN(11,8)
+       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
+      UInt bZ = (insn28 >> 16) & 1;
+      UInt bN = (insn28 >> 7) & 1;
+      UInt dD = INSN(15,12);
+      UInt dM = INSN(3,0);
+      if (bZ && INSN(3,0) != 0) {
+         /* does not decode; fall through */
+      } else {
+         IRTemp argL = newTemp(Ity_F64);
+         IRTemp argR = newTemp(Ity_F64);
+         IRTemp irRes = newTemp(Ity_I32);
+         assign(argL, getDReg(dD));
+         assign(argR, bZ ? IRExpr_Const(IRConst_F64i(0)) : getDReg(dM));
+         assign(irRes, binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR)));
+
+         IRTemp nzcv     = IRTemp_INVALID;
+         IRTemp oldFPSCR = newTemp(Ity_I32);
+         IRTemp newFPSCR = newTemp(Ity_I32);
+
+         /* This is where the fun starts.  We have to convert 'irRes'
+            from an IR-convention return result (IRCmpF64Result) to an
+            ARM-encoded (N,Z,C,V) group.  The final result is in the
+            bottom 4 bits of 'nzcv'. */
+         /* Map compare result from IR to ARM(nzcv) */
+         /*
+            FP cmp result | IR   | ARM(nzcv)
+            --------------------------------
+            UN              0x45   0011
+            LT              0x01   1000
+            GT              0x00   0010
+            EQ              0x40   0110
+         */
+         nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes);
+
+         /* And update FPSCR accordingly */
+         assign(oldFPSCR, IRExpr_Get(OFFB_FPSCR, Ity_I32));
+         assign(newFPSCR, 
+                binop(Iop_Or32, 
+                      binop(Iop_And32, mkexpr(oldFPSCR), mkU32(0x0FFFFFFF)),
+                      binop(Iop_Shl32, mkexpr(nzcv), mkU8(28))));
+
+         putMiscReg32(OFFB_FPSCR, mkexpr(newFPSCR), condT);
+
+         if (bZ) {
+            DIP("fcmpz%sd%s d%u\n", bN ? "e" : "", nCC(conq), dD);
+         } else {
+            DIP("fcmp%sd%s d%u, d%u\n", bN ? "e" : "", nCC(conq), dD, dM);
+         }
+         goto decode_success_vfp;
+      }
+      /* fall through */
+   }  
+
+   /* --------------------- unary (D) --------------------- */
+   if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
+       && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+       && BITS4(1,0,1,1) == INSN(11,8)
+       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
+      UInt dD  = INSN(15,12);
+      UInt dM  = INSN(3,0);
+      UInt b16 = (insn28 >> 16) & 1;
+      UInt b7  = (insn28 >> 7) & 1;
+      /**/ if (b16 == 0 && b7 == 0) {
+         // FCPYD
+         putDReg(dD, getDReg(dM), condT);
+         DIP("fcpyd%s d%u, d%u\n", nCC(conq), dD, dM);
+         goto decode_success_vfp;
+      }
+      else if (b16 == 0 && b7 == 1) {
+         // FABSD
+         putDReg(dD, unop(Iop_AbsF64, getDReg(dM)), condT);
+         DIP("fabsd%s d%u, d%u\n", nCC(conq), dD, dM);
+         goto decode_success_vfp;
+      }
+      else if (b16 == 1 && b7 == 0) {
+         // FNEGD
+         putDReg(dD, unop(Iop_NegF64, getDReg(dM)), condT);
+         DIP("fnegd%s d%u, d%u\n", nCC(conq), dD, dM);
+         goto decode_success_vfp;
+      }
+      else if (b16 == 1 && b7 == 1) {
+         // FSQRTD
+         IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
+         putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT);
+         DIP("fsqrtd%s d%u, d%u\n", nCC(conq), dD, dM);
+         goto decode_success_vfp;
+      }
+      else
+         vassert(0);
+
+      /* fall through */
+   }
+
+   /* ----------------- I <-> D conversions ----------------- */
+
+   // F{S,U}ITOD dD, fM
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,1))
+       && BITS4(1,0,0,0) == (INSN(19,16) & BITS4(1,1,1,1))
+       && BITS4(1,0,1,1) == INSN(11,8)
+       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
+      UInt bM    = (insn28 >> 5) & 1;
+      UInt fM    = (INSN(3,0) << 1) | bM;
+      UInt dD    = INSN(15,12);
+      UInt syned = (insn28 >> 7) & 1;
+      if (syned) {
+         // FSITOD
+         putDReg(dD, unop(Iop_I32StoF64,
+                          unop(Iop_ReinterpF32asI32, getFReg(fM))),
+                 condT);
+         DIP("fsitod%s d%u, s%u\n", nCC(conq), dD, fM);
+      } else {
+         // FUITOD
+         putDReg(dD, unop(Iop_I32UtoF64,
+                          unop(Iop_ReinterpF32asI32, getFReg(fM))),
+                 condT);
+         DIP("fuitod%s d%u, s%u\n", nCC(conq), dD, fM);
+      }
+      goto decode_success_vfp;
+   }
+
+   // FTO{S,U}ID fD, dM
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+       && BITS4(1,0,1,1) == INSN(11,8)
+       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
+      UInt   bD    = (insn28 >> 22) & 1;
+      UInt   fD    = (INSN(15,12) << 1) | bD;
+      UInt   dM    = INSN(3,0);
+      UInt   bZ    = (insn28 >> 7) & 1;
+      UInt   syned = (insn28 >> 16) & 1;
+      IRTemp rmode = newTemp(Ity_I32);
+      assign(rmode, bZ ? mkU32(Irrm_ZERO)
+                       : mkexpr(mk_get_IR_rounding_mode()));
+      if (syned) {
+         // FTOSID
+         putFReg(fD, unop(Iop_ReinterpI32asF32,
+                          binop(Iop_F64toI32S, mkexpr(rmode),
+                                getDReg(dM))),
+                 condT);
+         DIP("ftosi%sd%s s%u, d%u\n", bZ ? "z" : "",
+             nCC(conq), fD, dM);
+      } else {
+         // FTOUID
+         putFReg(fD, unop(Iop_ReinterpI32asF32,
+                          binop(Iop_F64toI32U, mkexpr(rmode),
+                                getDReg(dM))),
+                 condT);
+         DIP("ftoui%sd%s s%u, d%u\n", bZ ? "z" : "",
+             nCC(conq), fD, dM);
+      }
+      goto decode_success_vfp;
+   }
+
+   /* ----------------------------------------------------------- */
+   /* -- VFP instructions -- single precision                  -- */
+   /* ----------------------------------------------------------- */
+
+   /* --------------------- fldms, fstms --------------------- */
+   /*
+                                 31   27   23   19 15 11   7   0
+                                         P UDWL
+      C4-98, C5-26   1  FSTMD    cond 1100 1x00 Rn Fd 1010 offset
+      C4-98, C5-28   2  FSTMDIA  cond 1100 1x10 Rn Fd 1010 offset
+      C4-98, C5-30   3  FSTMDDB  cond 1101 0x10 Rn Fd 1010 offset
+
+      C4-40, C5-26   1  FLDMD    cond 1100 1x01 Rn Fd 1010 offset
+      C4-40, C5-26   2  FLDMIAD  cond 1100 1x11 Rn Fd 1010 offset
+      C4-40, C5-26   3  FLDMDBD  cond 1101 0x11 Rn Fd 1010 offset
+
+      Regs transferred: F(Fd:D) .. F(Fd:d + offset)
+      offset must not imply a reg > 15
+      IA/DB: Rn is changed by (4 x # regs transferred)
+
+      case coding:
+         1  at-Rn   (access at Rn)
+         2  ia-Rn   (access at Rn, then Rn += 4n)
+         3  db-Rn   (Rn -= 4n,     then access at Rn)
+   */
+   if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))
+       && INSN(11,8) == BITS4(1,0,1,0)) {
+      UInt bP      = (insn28 >> 24) & 1;
+      UInt bU      = (insn28 >> 23) & 1;
+      UInt bW      = (insn28 >> 21) & 1;
+      UInt bL      = (insn28 >> 20) & 1;
+      UInt bD      = (insn28 >> 22) & 1;
+      UInt offset  = (insn28 >> 0) & 0xFF;
+      UInt rN      = INSN(19,16);
+      UInt fD      = (INSN(15,12) << 1) | bD;
+      UInt nRegs   = offset;
+      UInt summary = 0;
+      Int  i;
+
+      /**/ if (bP == 0 && bU == 1 && bW == 0) {
+         summary = 1;
+      }
+      else if (bP == 0 && bU == 1 && bW == 1) {
+         summary = 2;
+      }
+      else if (bP == 1 && bU == 0 && bW == 1) {
+         summary = 3;
+      }
+      else goto after_vfp_fldms_fstms;
+
+      /* no writebacks to r15 allowed.  No use of r15 in thumb mode. */
+      if (rN == 15 && (summary == 2 || summary == 3 || isT))
+         goto after_vfp_fldms_fstms;
+
+      /* offset must specify at least one register */
+      if (offset < 1)
+         goto after_vfp_fldms_fstms;
+
+      /* can't transfer regs after S31 */
+      if (fD + nRegs - 1 >= 32)
+         goto after_vfp_fldms_fstms;
+
+      /* Now, we can't do a conditional load or store, since that very
+         likely will generate an exception.  So we have to take a side
+         exit at this point if the condition is false. */
+      if (condT != IRTemp_INVALID) {
+         if (isT)
+            mk_skip_over_T32_if_cond_is_false( condT );
+         else
+            mk_skip_over_A32_if_cond_is_false( condT );
+         condT = IRTemp_INVALID;
+      }
+      /* Ok, now we're unconditional.  Do the load or store. */
+
+      /* get the old Rn value */
+      IRTemp rnT = newTemp(Ity_I32);
+      assign(rnT, align4if(isT ? getIRegT(rN) : getIRegA(rN),
+                           rN == 15));
+
+      /* make a new value for Rn, post-insn */
+      IRTemp rnTnew = IRTemp_INVALID;
+      if (summary == 2 || summary == 3) {
+         rnTnew = newTemp(Ity_I32);
+         assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32,
+                              mkexpr(rnT),
+                              mkU32(4 * nRegs)));
+      }
+
+      /* decide on the base transfer address */
+      IRTemp taT = newTemp(Ity_I32);
+      assign(taT, summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT));
+
+      /* update Rn if necessary -- in case 3, we're moving it down, so
+         update before any memory reference, in order to keep Memcheck
+         and V's stack-extending logic (on linux) happy */
+      if (summary == 3) {
+         if (isT)
+            putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
+         else
+            putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+      }
+
+      /* generate the transfers */
+      for (i = 0; i < nRegs; i++) {
+         IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(4*i));
+         if (bL) {
+            putFReg(fD + i, loadLE(Ity_F32, addr), IRTemp_INVALID);
+         } else {
+            storeLE(addr, getFReg(fD + i));
+         }
+      }
+
+      /* update Rn if necessary -- in case 2, we're moving it up, so
+         update after any memory reference, in order to keep Memcheck
+         and V's stack-extending logic (on linux) happy */
+      if (summary == 2) {
+         if (isT)
+            putIRegT(rN, mkexpr(rnTnew), IRTemp_INVALID);
+         else
+            putIRegA(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+      }
+
+      HChar* nm = bL==1 ? "ld" : "st";
+      switch (summary) {
+         case 1:  DIP("f%sms%s r%u, {s%u-s%u}\n", 
+                      nm, nCC(conq), rN, fD, fD + nRegs - 1);
+                  break;
+         case 2:  DIP("f%smias%s r%u!, {s%u-s%u}\n", 
+                      nm, nCC(conq), rN, fD, fD + nRegs - 1);
+                  break;
+         case 3:  DIP("f%smdbs%s r%u!, {s%u-s%u}\n", 
+                      nm, nCC(conq), rN, fD, fD + nRegs - 1);
+                  break;
+         default: vassert(0);
+      }
+
+      goto decode_success_vfp;
+      /* FIXME alignment constraints? */
+   }
+
+  after_vfp_fldms_fstms:
+
+   /* --------------------- fmsr, fmrs --------------------- */
+   if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS4(0,0,0,0) == INSN(3,0)
+       && BITS4(0,0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
+      UInt rD  = INSN(15,12);
+      UInt b7  = (insn28 >> 7) & 1;
+      UInt fN  = (INSN(19,16) << 1) | b7;
+      UInt b20 = (insn28 >> 20) & 1;
+      if (rD == 15) {
+         /* fall through */
+         /* Let's assume that no sane person would want to do
+            floating-point transfers to or from the program counter,
+            and simply decline to decode the instruction.  The ARM ARM
+            doesn't seem to explicitly disallow this case, though. */
+      } else {
+         if (b20) {
+            IRExpr* res = unop(Iop_ReinterpF32asI32, getFReg(fN));
+            if (isT)
+               putIRegT(rD, res, condT);
+            else
+               putIRegA(rD, res, condT, Ijk_Boring);
+            DIP("fmrs%s r%u, s%u\n", nCC(conq), rD, fN);
+         } else {
+            putFReg(fN, unop(Iop_ReinterpI32asF32,
+                             isT ? getIRegT(rD) : getIRegA(rD)),
+                        condT);
+            DIP("fmsr%s s%u, r%u\n", nCC(conq), fN, rD);
+         }
+         goto decode_success_vfp;
+      }
+      /* fall through */
+   }
+
+   /* --------------------- f{ld,st}s --------------------- */
+   // FLDS, FSTS
+   if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,1,0))
+       && BITS4(1,0,1,0) == INSN(11,8)) {
+      UInt bD     = (insn28 >> 22) & 1;
+      UInt fD     = (INSN(15,12) << 1) | bD;
+      UInt rN     = INSN(19,16);
+      UInt offset = (insn28 & 0xFF) << 2;
+      UInt bU     = (insn28 >> 23) & 1; /* 1: +offset  0: -offset */
+      UInt bL     = (insn28 >> 20) & 1; /* 1: load  0: store */
+      /* make unconditional */
+      if (condT != IRTemp_INVALID) {
+         if (isT)
+            mk_skip_over_T32_if_cond_is_false( condT );
+         else
+            mk_skip_over_A32_if_cond_is_false( condT );
+         condT = IRTemp_INVALID;
+      }
+      IRTemp ea = newTemp(Ity_I32);
+      assign(ea, binop(bU ? Iop_Add32 : Iop_Sub32,
+                       align4if(isT ? getIRegT(rN) : getIRegA(rN),
+                                rN == 15),
+                       mkU32(offset)));
+      if (bL) {
+         putFReg(fD, loadLE(Ity_F32,mkexpr(ea)), IRTemp_INVALID);
+      } else {
+         storeLE(mkexpr(ea), getFReg(fD));
+      }
+      DIP("f%ss%s s%u, [r%u, %c#%u]\n",
+          bL ? "ld" : "st", nCC(conq), fD, rN,
+          bU ? '+' : '-', offset);
+      goto decode_success_vfp;
+   }
+
+   /* --------------------- dp insns (F) --------------------- */
+   if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(0,0,0,1))) {
+      UInt    bM  = (insn28 >> 5) & 1;
+      UInt    bD  = (insn28 >> 22) & 1;
+      UInt    bN  = (insn28 >> 7) & 1;
+      UInt    fM  = (INSN(3,0) << 1) | bM;   /* argR */
+      UInt    fD  = (INSN(15,12) << 1) | bD; /* dst/acc */
+      UInt    fN  = (INSN(19,16) << 1) | bN; /* argL */
+      UInt    bP  = (insn28 >> 23) & 1;
+      UInt    bQ  = (insn28 >> 21) & 1;
+      UInt    bR  = (insn28 >> 20) & 1;
+      UInt    bS  = (insn28 >> 6) & 1;
+      UInt    opc = (bP << 3) | (bQ << 2) | (bR << 1) | bS;
+      IRExpr* rm  = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
+      switch (opc) {
+         case BITS4(0,0,0,0): /* MAC: d + n * m */
+            putFReg(fD, triop(Iop_AddF32, rm,
+                              getFReg(fD),
+                              triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
+                        condT);
+            DIP("fmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+            goto decode_success_vfp;
+         case BITS4(0,0,0,1): /* NMAC: d - n * m */
+            putFReg(fD, triop(Iop_SubF32, rm,
+                              getFReg(fD),
+                              triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
+                        condT);
+            DIP("fnmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+            goto decode_success_vfp;
+         case BITS4(0,0,1,0): /* MSC: - d + n * m */
+            putFReg(fD, triop(Iop_AddF32, rm,
+                              unop(Iop_NegF32, getFReg(fD)),
+                              triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
+                        condT);
+            DIP("fmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+            goto decode_success_vfp;
+         case BITS4(0,0,1,1): /* NMSC: - d - n * m */
+            break; //ATC
+         case BITS4(0,1,0,0): /* MUL: n * m */
+            putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
+                        condT);
+            DIP("fmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+            goto decode_success_vfp;
+         case BITS4(0,1,0,1): /* NMUL: - n * m */
+            putFReg(fD, unop(Iop_NegF32,
+                             triop(Iop_MulF32, rm, getFReg(fN),
+                                                   getFReg(fM))),
+                    condT);
+            DIP("fnmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+            goto decode_success_vfp;
+         case BITS4(0,1,1,0): /* ADD: n + m */
+            putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
+                        condT);
+            DIP("fadds%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+            goto decode_success_vfp;
+         case BITS4(0,1,1,1): /* SUB: n - m */
+            putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
+                        condT);
+            DIP("fsubs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+            goto decode_success_vfp;
+         case BITS4(1,0,0,0): /* DIV: n / m */
+            putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
+                        condT);
+            DIP("fdivs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
+            goto decode_success_vfp;
+         default:
+            break;
+      }
+   }
+
+   /* --------------------- compares (S) --------------------- */
+   /*          31   27   23   19   15 11   7    3
+                 28   24   20   16 12    8    4    0 
+      FCMPS    cond 1110 1D11 0100 Fd 1010 01M0 Fm
+      FCMPES   cond 1110 1D11 0100 Fd 1010 11M0 Fm
+      FCMPZS   cond 1110 1D11 0101 Fd 1010 0100 0000
+      FCMPZED  cond 1110 1D11 0101 Fd 1010 1100 0000
+                                 Z         N
+
+      Z=0 Compare Fd:D vs Fm:M     and set FPSCR 31:28 accordingly
+      Z=1 Compare Fd:D vs zero
+
+      N=1 generates Invalid Operation exn if either arg is any kind of NaN
+      N=0 generates Invalid Operation exn if either arg is a signalling NaN
+      (Not that we pay any attention to N here)
+   */
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
+      UInt bZ = (insn28 >> 16) & 1;
+      UInt bN = (insn28 >> 7) & 1;
+      UInt bD = (insn28 >> 22) & 1;
+      UInt bM = (insn28 >> 5) & 1;
+      UInt fD = (INSN(15,12) << 1) | bD;
+      UInt fM = (INSN(3,0) << 1) | bM;
+      if (bZ && (INSN(3,0) != 0 || (INSN(7,4) & 3) != 0)) {
+         /* does not decode; fall through */
+      } else {
+         IRTemp argL = newTemp(Ity_F64);
+         IRTemp argR = newTemp(Ity_F64);
+         IRTemp irRes = newTemp(Ity_I32);
+
+         assign(argL, unop(Iop_F32toF64, getFReg(fD)));
+         assign(argR, bZ ? IRExpr_Const(IRConst_F64i(0))
+                         : unop(Iop_F32toF64, getFReg(fM)));
+         assign(irRes, binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR)));
+
+         IRTemp nzcv     = IRTemp_INVALID;
+         IRTemp oldFPSCR = newTemp(Ity_I32);
+         IRTemp newFPSCR = newTemp(Ity_I32);
+
+         /* This is where the fun starts.  We have to convert 'irRes'
+            from an IR-convention return result (IRCmpF64Result) to an
+            ARM-encoded (N,Z,C,V) group.  The final result is in the
+            bottom 4 bits of 'nzcv'. */
+         /* Map compare result from IR to ARM(nzcv) */
+         /*
+            FP cmp result | IR   | ARM(nzcv)
+            --------------------------------
+            UN              0x45   0011
+            LT              0x01   1000
+            GT              0x00   0010
+            EQ              0x40   0110
+         */
+         nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes);
+
+         /* And update FPSCR accordingly */
+         assign(oldFPSCR, IRExpr_Get(OFFB_FPSCR, Ity_I32));
+         assign(newFPSCR, 
+                binop(Iop_Or32, 
+                      binop(Iop_And32, mkexpr(oldFPSCR), mkU32(0x0FFFFFFF)),
+                      binop(Iop_Shl32, mkexpr(nzcv), mkU8(28))));
+
+         putMiscReg32(OFFB_FPSCR, mkexpr(newFPSCR), condT);
+
+         if (bZ) {
+            DIP("fcmpz%ss%s s%u\n", bN ? "e" : "", nCC(conq), fD);
+         } else {
+            DIP("fcmp%ss%s s%u, s%u\n", bN ? "e" : "",
+                nCC(conq), fD, fM);
+         }
+         goto decode_success_vfp;
+      }
+      /* fall through */
+   }  
+
+   /* --------------------- unary (S) --------------------- */
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
+      UInt bD = (insn28 >> 22) & 1;
+      UInt bM = (insn28 >> 5) & 1;
+      UInt fD  = (INSN(15,12) << 1) | bD;
+      UInt fM  = (INSN(3,0) << 1) | bM;
+      UInt b16 = (insn28 >> 16) & 1;
+      UInt b7  = (insn28 >> 7) & 1;
+      /**/ if (b16 == 0 && b7 == 0) {
+         // FCPYS
+         putFReg(fD, getFReg(fM), condT);
+         DIP("fcpys%s s%u, s%u\n", nCC(conq), fD, fM);
+         goto decode_success_vfp;
+      }
+      else if (b16 == 0 && b7 == 1) {
+         // FABSS
+         putFReg(fD, unop(Iop_AbsF32, getFReg(fM)), condT);
+         DIP("fabss%s s%u, s%u\n", nCC(conq), fD, fM);
+         goto decode_success_vfp;
+      }
+      else if (b16 == 1 && b7 == 0) {
+         // FNEGS
+         putFReg(fD, unop(Iop_NegF32, getFReg(fM)), condT);
+         DIP("fnegs%s s%u, s%u\n", nCC(conq), fD, fM);
+         goto decode_success_vfp;
+      }
+      else if (b16 == 1 && b7 == 1) {
+         // FSQRTS
+         IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
+         putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT);
+         DIP("fsqrts%s s%u, s%u\n", nCC(conq), fD, fM);
+         goto decode_success_vfp;
+      }
+      else
+         vassert(0);
+
+      /* fall through */
+   }
+
+   /* ----------------- I <-> S conversions ----------------- */
+
+   // F{S,U}ITOS fD, fM
+   /* These are more complex than FSITOD/FUITOD.  In the D cases, a 32
+      bit int will always fit within the 53 bit mantissa, so there's
+      no possibility of a loss of precision, but that's obviously not
+      the case here.  Hence this case possibly requires rounding, and
+      so it drags in the current rounding mode. */
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(1,0,0,0) == (INSN(19,16) & BITS4(1,1,1,1))
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
+      UInt bM    = (insn28 >> 5) & 1;
+      UInt bD    = (insn28 >> 22) & 1;
+      UInt fM    = (INSN(3,0) << 1) | bM;
+      UInt fD    = (INSN(15,12) << 1) | bD;
+      UInt syned = (insn28 >> 7) & 1;
+      IRTemp rmode = newTemp(Ity_I32);
+      assign(rmode, mkexpr(mk_get_IR_rounding_mode()));
+      if (syned) {
+         // FSITOS
+         putFReg(fD, binop(Iop_F64toF32,
+                           mkexpr(rmode),
+                           unop(Iop_I32StoF64,
+                                unop(Iop_ReinterpF32asI32, getFReg(fM)))),
+                 condT);
+         DIP("fsitos%s s%u, s%u\n", nCC(conq), fD, fM);
+      } else {
+         // FUITOS
+         putFReg(fD, binop(Iop_F64toF32,
+                           mkexpr(rmode),
+                           unop(Iop_I32UtoF64,
+                                unop(Iop_ReinterpF32asI32, getFReg(fM)))),
+                 condT);
+         DIP("fuitos%s s%u, s%u\n", nCC(conq), fD, fM);
+      }
+      goto decode_success_vfp;
+   }
+
+   // FTO{S,U}IS fD, fM
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
+      UInt   bM    = (insn28 >> 5) & 1;
+      UInt   bD    = (insn28 >> 22) & 1;
+      UInt   fD    = (INSN(15,12) << 1) | bD;
+      UInt   fM    = (INSN(3,0) << 1) | bM;
+      UInt   bZ    = (insn28 >> 7) & 1;
+      UInt   syned = (insn28 >> 16) & 1;
+      IRTemp rmode = newTemp(Ity_I32);
+      assign(rmode, bZ ? mkU32(Irrm_ZERO)
+                       : mkexpr(mk_get_IR_rounding_mode()));
+      if (syned) {
+         // FTOSIS
+         putFReg(fD, unop(Iop_ReinterpI32asF32,
+                          binop(Iop_F64toI32S, mkexpr(rmode),
+                                unop(Iop_F32toF64, getFReg(fM)))),
+                 condT);
+         DIP("ftosi%ss%s s%u, d%u\n", bZ ? "z" : "",
+             nCC(conq), fD, fM);
+         goto decode_success_vfp;
+      } else {
+         // FTOUIS
+         putFReg(fD, unop(Iop_ReinterpI32asF32,
+                          binop(Iop_F64toI32U, mkexpr(rmode),
+                                unop(Iop_F32toF64, getFReg(fM)))),
+                 condT);
+         DIP("ftoui%ss%s s%u, d%u\n", bZ ? "z" : "",
+             nCC(conq), fD, fM);
+         goto decode_success_vfp;
+      }
+   }
+
+   /* ----------------- S <-> D conversions ----------------- */
+
+   // FCVTDS
+   if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
+       && BITS4(0,1,1,1) == INSN(19,16)
+       && BITS4(1,0,1,0) == INSN(11,8)
+       && BITS4(1,1,0,0) == (INSN(7,4) & BITS4(1,1,0,1))) {
+      UInt dD = INSN(15,12);
+      UInt bM = (insn28 >> 5) & 1;
+      UInt fM = (INSN(3,0) << 1) | bM;
+      putDReg(dD, unop(Iop_F32toF64, getFReg(fM)), condT);
+      DIP("fcvtds%s d%u, s%u\n", nCC(conq), dD, fM);
+      goto decode_success_vfp;
+   }
+
+   // FCVTSD
+   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(0,1,1,1) == INSN(19,16)
+       && BITS4(1,0,1,1) == INSN(11,8)
+       && BITS4(1,1,0,0) == INSN(7,4)) {
+      UInt   bD    = (insn28 >> 22) & 1;
+      UInt   fD    = (INSN(15,12) << 1) | bD;
+      UInt   dM    = INSN(3,0);
+      IRTemp rmode = newTemp(Ity_I32);
+      assign(rmode, mkexpr(mk_get_IR_rounding_mode()));
+      putFReg(fD, binop(Iop_F64toF32, mkexpr(rmode), getDReg(dM)),
+                  condT);
+      DIP("fcvtsd%s s%u, d%u\n", nCC(conq), fD, dM);
+      goto decode_success_vfp;
+   }
+
+   /* FAILURE */
+   return False;
+
+  decode_success_vfp:
+   /* Check that any accepted insn really is a CP10 or CP11 insn, iow,
+      assert that we aren't accepting, in this fn, insns that actually
+      should be handled somewhere else. */
+   vassert(INSN(11,9) == BITS3(1,0,1)); // 11:8 = 1010 or 1011
+   return True;  
+
+#  undef INSN
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Instructions in NV (never) space                     ---*/
+/*------------------------------------------------------------*/
+
+/* ARM only */
+/* Translate a NV space instruction.  If successful, returns True and
+   *dres may or may not be updated.  If failure, returns False and
+   doesn't change *dres nor create any IR.
+
+   Note that all NEON instructions (in ARM mode) are handled through
+   here, since they are all in NV space.
+*/
+static Bool decode_NV_instruction ( /*MOD*/DisResult* dres, UInt insn )
+{
+#  define INSN(_bMax,_bMin)  SLICE_UInt(insn, (_bMax), (_bMin))
+#  define INSN_COND          SLICE_UInt(insn, 31, 28)
+
+   HChar dis_buf[128];
+
+   // Should only be called for NV instructions
+   vassert(BITS4(1,1,1,1) == INSN_COND);
+
+   /* ------------------------ pld ------------------------ */
+   if (BITS8(0,1,0,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
+       && BITS4(1,1,1,1) == INSN(15,12)) {
+      UInt rN    = INSN(19,16);
+      UInt imm12 = INSN(11,0);
+      UInt bU    = INSN(23,23);
+      DIP("pld [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12);
+      return True;
+   }
+
+   if (BITS8(0,1,1,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
+       && BITS4(1,1,1,1) == INSN(15,12)
+       && 0 == INSN(4,4)) {
+      UInt rN   = INSN(19,16);
+      UInt rM   = INSN(3,0);
+      UInt imm5 = INSN(11,7);
+      UInt sh2  = INSN(6,5);
+      UInt bU   = INSN(23,23);
+      if (rM != 15) {
+         IRExpr* eaE = mk_EA_reg_plusminus_shifted_reg(rN, bU, rM,
+                                                       sh2, imm5, dis_buf);
+         IRTemp eaT = newTemp(Ity_I32);
+         /* Bind eaE to a temp merely for debugging-vex purposes, so we
+            can check it's a plausible decoding.  It will get removed
+            by iropt a little later on. */
+         vassert(eaE);
+         assign(eaT, eaE);
+         DIP("pld %s\n", dis_buf);
+         return True;
+      }
+      /* fall through */
+   }
+
+   /* --------------------- Interworking branches --------------------- */
+
+   // BLX (1), viz, unconditional branch and link to R15+simm24
+   // and set CPSR.T = 1, that is, switch to Thumb mode
+   if (INSN(31,25) == BITS7(1,1,1,1,1,0,1)) {
+      UInt bitH   = INSN(24,24);
+      Int  uimm24 = INSN(23,0);
+      Int  simm24 = (((uimm24 << 8) >> 8) << 2) + (bitH << 1);
+      /* Now this is a bit tricky.  Since we're decoding an ARM insn,
+         it is implies that CPSR.T == 0.  Hence the current insn's
+         address is guaranteed to be of the form X--(30)--X00.  So, no
+         need to mask any bits off it.  But need to set the lowest bit
+         to 1 to denote we're in Thumb mode after this, since
+         guest_R15T has CPSR.T as the lowest bit.  And we can't chase
+         into the call, so end the block at this point. */
+      UInt dst = guest_R15_curr_instr_notENC + 8 + (simm24 | 1);
+      putIRegA( 14, mkU32(guest_R15_curr_instr_notENC + 4),
+                    IRTemp_INVALID/*because AL*/, Ijk_Boring );
+      irsb->next     = mkU32(dst);
+      irsb->jumpkind = Ijk_Call;
+      dres->whatNext = Dis_StopHere;
+      DIP("blx 0x%x (and switch to Thumb mode)\n", dst - 1);
+      return True;
+   }
+
+   /* ------------------- v7 barrier insns ------------------- */
+   switch (insn) {
+      case 0xF57FF06F: /* ISB */
+         stmt( IRStmt_MBE(Imbe_Fence) );
+         DIP("ISB\n");
+         return True;
+      case 0xF57FF04F: /* DSB */
+         stmt( IRStmt_MBE(Imbe_Fence) );
+         DIP("DSB\n");
+         return True;
+      case 0xF57FF05F: /* DMB */
+         stmt( IRStmt_MBE(Imbe_Fence) );
+         DIP("DMB\n");
+         return True;
+      default:
+         break;
+   }
+
+   /* ------------------- NEON ------------------- */
+   Bool ok = decode_NEON_instruction(
+                dres, insn, IRTemp_INVALID/*unconditional*/, 
+                False/*!isT*/
+             );
+   if (ok)
+      return True;
+
+   // unrecognised
+   return False;
+
+#  undef INSN_COND
+#  undef INSN
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Disassemble a single ARM instruction                 ---*/
+/*------------------------------------------------------------*/
+
+/* Disassemble a single ARM instruction into IR.  The instruction is
+   located in host memory at guest_instr, and has (decoded) guest IP
+   of guest_R15_curr_instr_notENC, which will have been set before the
+   call here. */
+
+static
+DisResult disInstr_ARM_WRK (
+             Bool         put_IP,
+             Bool         (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+             Bool         resteerCisOk,
+             void*        callback_opaque,
+             UChar*       guest_instr,
+             VexArchInfo* archinfo,
+             VexAbiInfo*  abiinfo
+          )
+{
+   // A macro to fish bits out of 'insn'.
+#  define INSN(_bMax,_bMin)  SLICE_UInt(insn, (_bMax), (_bMin))
+#  define INSN_COND          SLICE_UInt(insn, 31, 28)
+
+   DisResult dres;
+   UInt      insn;
+   //Bool      allow_VFP = False;
+   //UInt      hwcaps = archinfo->hwcaps;
+   IRTemp    condT; /* :: Ity_I32 */
+   UInt      summary;
+   HChar     dis_buf[128];  // big enough to hold LDMIA etc text
+
+   /* What insn variants are we supporting today? */
+   //allow_VFP  = (0 != (hwcaps & VEX_HWCAPS_ARM_VFP));
+   // etc etc
+
+   /* Set result defaults. */
+   dres.whatNext   = Dis_Continue;
+   dres.len        = 4;
+   dres.continueAt = 0;
+
+   /* Set default actions for post-insn handling of writes to r15, if
+      required. */
+   r15written = False;
+   r15guard   = IRTemp_INVALID; /* unconditional */
+   r15kind    = Ijk_Boring;
+
+   /* At least this is simple on ARM: insns are all 4 bytes long, and
+      4-aligned.  So just fish the whole thing out of memory right now
+      and have done. */
+   insn = getUIntLittleEndianly( guest_instr );
+
+   if (0) vex_printf("insn: 0x%x\n", insn);
+
+   DIP("\t(arm) 0x%x:  ", (UInt)guest_R15_curr_instr_notENC);
+
+   /* We may be asked to update the guest R15 before going further. */
+   vassert(0 == (guest_R15_curr_instr_notENC & 3));
+   if (put_IP) {
+      llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC) );
+   }
+
+   /* ----------------------------------------------------------- */
+
+   /* Spot "Special" instructions (see comment at top of file). */
+   {
+      UChar* code = (UChar*)guest_instr;
+      /* Spot the 16-byte preamble: 
+
+         e1a0c1ec  mov r12, r12, ROR #3
+         e1a0c6ec  mov r12, r12, ROR #13
+         e1a0ceec  mov r12, r12, ROR #29
+         e1a0c9ec  mov r12, r12, ROR #19
+      */
+      UInt word1 = 0xE1A0C1EC;
+      UInt word2 = 0xE1A0C6EC;
+      UInt word3 = 0xE1A0CEEC;
+      UInt word4 = 0xE1A0C9EC;
+      if (getUIntLittleEndianly(code+ 0) == word1 &&
+          getUIntLittleEndianly(code+ 4) == word2 &&
+          getUIntLittleEndianly(code+ 8) == word3 &&
+          getUIntLittleEndianly(code+12) == word4) {
+         /* Got a "Special" instruction preamble.  Which one is it? */
+         if (getUIntLittleEndianly(code+16) == 0xE18AA00A
+                                               /* orr r10,r10,r10 */) {
+            /* R3 = client_request ( R4 ) */
+            DIP("r3 = client_request ( %%r4 )\n");
+            irsb->next     = mkU32( guest_R15_curr_instr_notENC + 20 );
+            irsb->jumpkind = Ijk_ClientReq;
+            dres.whatNext  = Dis_StopHere;
+            goto decode_success;
+         }
+         else
+         if (getUIntLittleEndianly(code+16) == 0xE18BB00B
+                                               /* orr r11,r11,r11 */) {
+            /* R3 = guest_NRADDR */
+            DIP("r3 = guest_NRADDR\n");
+            dres.len = 20;
+            llPutIReg(3, IRExpr_Get( OFFB_NRADDR, Ity_I32 ));
+            goto decode_success;
+         }
+         else
+         if (getUIntLittleEndianly(code+16) == 0xE18CC00C
+                                               /* orr r12,r12,r12 */) {
+            /*  branch-and-link-to-noredir R4 */
+            DIP("branch-and-link-to-noredir r4\n");
+            llPutIReg(14, mkU32( guest_R15_curr_instr_notENC + 20) );
+            irsb->next     = llGetIReg(4);
+            irsb->jumpkind = Ijk_NoRedir;
+            dres.whatNext  = Dis_StopHere;
+            goto decode_success;
+         }
+         /* We don't know what it is.  Set opc1/opc2 so decode_failure
+            can print the insn following the Special-insn preamble. */
+         insn = getUIntLittleEndianly(code+16);
+         goto decode_failure;
+         /*NOTREACHED*/
+      }
+
+   }
+
+   /* ----------------------------------------------------------- */
+
+   /* Main ARM instruction decoder starts here. */
+
+   /* Deal with the condition.  Strategy is to merely generate a
+      condition temporary at this point (or IRTemp_INVALID, meaning
+      unconditional).  We leave it to lower-level instruction decoders
+      to decide whether they can generate straight-line code, or
+      whether they must generate a side exit before the instruction.
+      condT :: Ity_I32 and is always either zero or one. */
+   condT = IRTemp_INVALID;
+   switch ( (ARMCondcode)INSN_COND ) {
+      case ARMCondNV: {
+         // Illegal instruction prior to v5 (see ARM ARM A3-5), but
+         // some cases are acceptable
+         Bool ok = decode_NV_instruction(&dres, insn);
+         if (ok)
+            goto decode_success;
+         else
+         goto decode_failure;
+      }
+      case ARMCondAL: // Always executed
+         break;
+      case ARMCondEQ: case ARMCondNE: case ARMCondHS: case ARMCondLO:
+      case ARMCondMI: case ARMCondPL: case ARMCondVS: case ARMCondVC:
+      case ARMCondHI: case ARMCondLS: case ARMCondGE: case ARMCondLT:
+      case ARMCondGT: case ARMCondLE:
+         condT = newTemp(Ity_I32);
+         assign( condT, mk_armg_calculate_condition( INSN_COND ));
+         break;
+   }
+
+   /* ----------------------------------------------------------- */
+   /* -- ARMv5 integer instructions                            -- */
+   /* ----------------------------------------------------------- */
+
+   /* ---------------- Data processing ops ------------------- */
+
+   if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0))
+       && !(INSN(25,25) == 0 && INSN(7,7) == 1 && INSN(4,4) == 1)) {
+      IRTemp  shop = IRTemp_INVALID; /* shifter operand */
+      IRTemp  shco = IRTemp_INVALID; /* shifter carry out */
+      UInt    rD   = (insn >> 12) & 0xF; /* 15:12 */
+      UInt    rN   = (insn >> 16) & 0xF; /* 19:16 */
+      UInt    bitS = (insn >> 20) & 1; /* 20:20 */
+      IRTemp  rNt  = IRTemp_INVALID;
+      IRTemp  res  = IRTemp_INVALID;
+      IRTemp  oldV = IRTemp_INVALID;
+      IRTemp  oldC = IRTemp_INVALID;
+      HChar*  name = NULL;
+      IROp    op   = Iop_INVALID;
+      Bool    ok;
+
+      switch (INSN(24,21)) {
+
+         /* --------- ADD, SUB, AND, OR --------- */
+         case BITS4(0,1,0,0): /* ADD:  Rd = Rn + shifter_operand */
+            name = "add"; op = Iop_Add32; goto rd_eq_rn_op_SO;
+         case BITS4(0,0,1,0): /* SUB:  Rd = Rn - shifter_operand */
+            name = "sub"; op = Iop_Sub32; goto rd_eq_rn_op_SO;
+         case BITS4(0,0,1,1): /* RSB:  Rd = shifter_operand - Rn */
+            name = "rsb"; op = Iop_Sub32; goto rd_eq_rn_op_SO;
+         case BITS4(0,0,0,0): /* AND:  Rd = Rn & shifter_operand */
+            name = "and"; op = Iop_And32; goto rd_eq_rn_op_SO;
+         case BITS4(1,1,0,0): /* OR:   Rd = Rn | shifter_operand */
+            name = "orr"; op = Iop_Or32; goto rd_eq_rn_op_SO;
+         case BITS4(0,0,0,1): /* EOR:  Rd = Rn ^ shifter_operand */
+            name = "eor"; op = Iop_Xor32; goto rd_eq_rn_op_SO;
+         case BITS4(1,1,1,0): /* BIC:  Rd = Rn & ~shifter_operand */
+            name = "bic"; op = Iop_And32; goto rd_eq_rn_op_SO;
+         rd_eq_rn_op_SO: {
+            Bool isRSB = False;
+            Bool isBIC = False;
+            switch (INSN(24,21)) {
+               case BITS4(0,0,1,1):
+                  vassert(op == Iop_Sub32); isRSB = True; break;
+               case BITS4(1,1,1,0):
+                  vassert(op == Iop_And32); isBIC = True; break;
+               default:
+                  break;
+            }
+            rNt = newTemp(Ity_I32);
+            assign(rNt, getIRegA(rN));
+            ok = mk_shifter_operand(
+                    INSN(25,25), INSN(11,0), 
+                    &shop, bitS ? &shco : NULL, dis_buf
+                 );
+            if (!ok)
+               break;
+            res = newTemp(Ity_I32);
+            // compute the main result
+            if (isRSB) {
+               // reverse-subtract: shifter_operand - Rn
+               vassert(op == Iop_Sub32);
+               assign(res, binop(op, mkexpr(shop), mkexpr(rNt)) );
+            } else if (isBIC) {
+               // andn: shifter_operand & ~Rn
+               vassert(op == Iop_And32);
+               assign(res, binop(op, mkexpr(rNt),
+                                     unop(Iop_Not32, mkexpr(shop))) );
+            } else {
+               // normal: Rn op shifter_operand
+               assign(res, binop(op, mkexpr(rNt), mkexpr(shop)) );
+            }
+            // but don't commit it until after we've finished
+            // all necessary reads from the guest state
+            if (bitS
+                && (op == Iop_And32 || op == Iop_Or32 || op == Iop_Xor32)) {
+               oldV = newTemp(Ity_I32);
+               assign( oldV, mk_armg_calculate_flag_v() );
+            }
+            // can't safely read guest state after here
+            // now safe to put the main result
+            putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
+            // XXXX!! not safe to read any guest state after
+            // this point (I think the code below doesn't do that).
+            if (!bitS)
+               vassert(shco == IRTemp_INVALID);
+            /* Update the flags thunk if necessary */
+            if (bitS) {
+               vassert(shco != IRTemp_INVALID);
+               switch (op) {
+                  case Iop_Add32:
+                     setFlags_D1_D2( ARMG_CC_OP_ADD, rNt, shop, condT );
+                     break;
+                  case Iop_Sub32:
+                     if (isRSB) {
+                        setFlags_D1_D2( ARMG_CC_OP_SUB, shop, rNt, condT );
+                     } else {
+                        setFlags_D1_D2( ARMG_CC_OP_SUB, rNt, shop, condT );
+                     }
+                     break;
+                  case Iop_And32: /* BIC and AND set the flags the same */
+                  case Iop_Or32:
+                  case Iop_Xor32:
+                     // oldV has been read just above
+                     setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC,
+                                        res, shco, oldV, condT );
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            DIP("%s%s%s r%u, r%u, %s\n",
+                name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
+            goto decode_success;
+         }
+
+         /* --------- MOV, MVN --------- */
+         case BITS4(1,1,0,1):   /* MOV: Rd = shifter_operand */
+         case BITS4(1,1,1,1): { /* MVN: Rd = not(shifter_operand) */
+            Bool isMVN = INSN(24,21) == BITS4(1,1,1,1);
+            if (rN != 0)
+               break; /* rN must be zero */
+            ok = mk_shifter_operand(
+                    INSN(25,25), INSN(11,0), 
+                    &shop, bitS ? &shco : NULL, dis_buf
+                 );
+            if (!ok)
+               break;
+            res = newTemp(Ity_I32);
+            assign( res, isMVN ? unop(Iop_Not32, mkexpr(shop))
+                               : mkexpr(shop) );
+            if (bitS) {
+               vassert(shco != IRTemp_INVALID);
+               oldV = newTemp(Ity_I32);
+               assign( oldV, mk_armg_calculate_flag_v() );
+            } else {
+               vassert(shco == IRTemp_INVALID);
+            }
+            // can't safely read guest state after here
+            putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
+            /* Update the flags thunk if necessary */
+            if (bitS) {
+               setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, 
+                                  res, shco, oldV, condT );
+            }
+            DIP("%s%s%s r%u, %s\n",
+                isMVN ? "mvn" : "mov",
+                nCC(INSN_COND), bitS ? "s" : "", rD, dis_buf );
+            goto decode_success;
+         }
+
+         /* --------- CMP --------- */
+         case BITS4(1,0,1,0):   /* CMP:  (void) Rn - shifter_operand */
+         case BITS4(1,0,1,1): { /* CMN:  (void) Rn + shifter_operand */
+            Bool isCMN = INSN(24,21) == BITS4(1,0,1,1);
+            if (rD != 0)
+               break; /* rD must be zero */
+            if (bitS == 0)
+               break; /* if S (bit 20) is not set, it's not CMP/CMN */
+            rNt = newTemp(Ity_I32);
+            assign(rNt, getIRegA(rN));
+            ok = mk_shifter_operand(
+                    INSN(25,25), INSN(11,0), 
+                    &shop, NULL, dis_buf
+                 );
+            if (!ok)
+               break;
+            // can't safely read guest state after here
+            /* Update the flags thunk. */
+            setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB,
+                            rNt, shop, condT );
+            DIP("%s%s r%u, %s\n",
+                isCMN ? "cmn" : "cmp",
+                nCC(INSN_COND), rN, dis_buf );
+            goto decode_success;
+         }
+
+         /* --------- TST --------- */
+         case BITS4(1,0,0,0):   /* TST:  (void) Rn & shifter_operand */
+         case BITS4(1,0,0,1): { /* TEQ:  (void) Rn ^ shifter_operand */
+            Bool isTEQ = INSN(24,21) == BITS4(1,0,0,1);
+            if (rD != 0)
+               break; /* rD must be zero */
+            if (bitS == 0)
+               break; /* if S (bit 20) is not set, it's not TST/TEQ */
+            rNt = newTemp(Ity_I32);
+            assign(rNt, getIRegA(rN));
+            ok = mk_shifter_operand(
+                    INSN(25,25), INSN(11,0), 
+                    &shop, &shco, dis_buf
+                 );
+            if (!ok)
+               break;
+            /* Update the flags thunk. */
+            res = newTemp(Ity_I32);
+            assign( res, binop(isTEQ ? Iop_Xor32 : Iop_And32, 
+                               mkexpr(rNt), mkexpr(shop)) );
+            oldV = newTemp(Ity_I32);
+            assign( oldV, mk_armg_calculate_flag_v() );
+            // can't safely read guest state after here
+            setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC,
+                               res, shco, oldV, condT );
+            DIP("%s%s r%u, %s\n",
+                isTEQ ? "teq" : "tst",
+                nCC(INSN_COND), rN, dis_buf );
+            goto decode_success;
+         }
+
+         /* --------- ADC, SBC, RSC --------- */
+         case BITS4(0,1,0,1): /* ADC:  Rd = Rn + shifter_operand + oldC */
+            name = "adc"; goto rd_eq_rn_op_SO_op_oldC;
+         case BITS4(0,1,1,0): /* SBC:  Rd = Rn - shifter_operand - (oldC ^ 1) */
+            name = "sbc"; goto rd_eq_rn_op_SO_op_oldC;
+         case BITS4(0,1,1,1): /* RSC:  Rd = shifter_operand - Rn - (oldC ^ 1) */
+            name = "rsc"; goto rd_eq_rn_op_SO_op_oldC;
+         rd_eq_rn_op_SO_op_oldC: {
+            // FIXME: shco isn't used for anything.  Get rid of it.
+            rNt = newTemp(Ity_I32);
+            assign(rNt, getIRegA(rN));
+            ok = mk_shifter_operand(
+                    INSN(25,25), INSN(11,0), 
+                    &shop, bitS ? &shco : NULL, dis_buf
+                 );
+            if (!ok)
+               break;
+            oldC = newTemp(Ity_I32);
+            assign( oldC, mk_armg_calculate_flag_c() );
+            res = newTemp(Ity_I32);
+            // compute the main result
+            switch (INSN(24,21)) {
+               case BITS4(0,1,0,1): /* ADC */
+                  assign(res,
+                         binop(Iop_Add32,
+                               binop(Iop_Add32, mkexpr(rNt), mkexpr(shop)),
+                               mkexpr(oldC) ));
+                  break;
+               case BITS4(0,1,1,0): /* SBC */
+                  assign(res,
+                         binop(Iop_Sub32,
+                               binop(Iop_Sub32, mkexpr(rNt), mkexpr(shop)),
+                               binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) ));
+                  break;
+               case BITS4(0,1,1,1): /* RSC */
+                  assign(res,
+                         binop(Iop_Sub32,
+                               binop(Iop_Sub32, mkexpr(shop), mkexpr(rNt)),
+                               binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) ));
+                  break;
+               default:
+                  vassert(0);
+            }
+            // but don't commit it until after we've finished
+            // all necessary reads from the guest state
+            // now safe to put the main result
+            putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
+            // XXXX!! not safe to read any guest state after
+            // this point (I think the code below doesn't do that).
+            if (!bitS)
+               vassert(shco == IRTemp_INVALID);
+            /* Update the flags thunk if necessary */
+            if (bitS) {
+               vassert(shco != IRTemp_INVALID);
+               switch (INSN(24,21)) {
+                  case BITS4(0,1,0,1): /* ADC */
+                     setFlags_D1_D2_ND( ARMG_CC_OP_ADC,
+                                        rNt, shop, oldC, condT );
+                     break;
+                  case BITS4(0,1,1,0): /* SBC */
+                     setFlags_D1_D2_ND( ARMG_CC_OP_SBB,
+                                        rNt, shop, oldC, condT );
+                     break;
+                  case BITS4(0,1,1,1): /* RSC */
+                     setFlags_D1_D2_ND( ARMG_CC_OP_SBB,
+                                        shop, rNt, oldC, condT );
+                     break;
+                  default:
+                     vassert(0);
+               }
+            }
+            DIP("%s%s%s r%u, r%u, %s\n",
+                name, nCC(INSN_COND), bitS ? "s" : "", rD, rN, dis_buf );
+            goto decode_success;
+         }
+
+         /* --------- ??? --------- */
+         default:
+            break;
+      }
+   } /* if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0)) */
+
+   /* --------------------- Load/store (ubyte & word) -------- */
+   // LDR STR LDRB STRB
+   /*                 31   27   23   19 15 11    6   4 3  # highest bit
+                        28   24   20 16 12
+      A5-20   1 | 16  cond 0101 UB0L Rn Rd imm12
+      A5-22   1 | 32  cond 0111 UBOL Rn Rd imm5  sh2 0 Rm

       A5-24   2 | 16  cond 0101 UB1L Rn Rd imm12
       A5-26   2 | 32  cond 0111 UB1L Rn Rd imm5  sh2 0 Rm
       A5-28   3 | 16  cond 0100 UB0L Rn Rd imm12
       A5-24   2 | 16  cond 0101 UB1L Rn Rd imm12
       A5-26   2 | 32  cond 0111 UB1L Rn Rd imm5  sh2 0 Rm
       A5-28   3 | 16  cond 0100 UB0L Rn Rd imm12


@@ -2038,208 +10036,1240 @@ DisResult disInstr_ARM_WRK (
              16  Rn +/- imm12
              32  Rn +/- Rm sh2 imm5
    */
              16  Rn +/- imm12
              32  Rn +/- Rm sh2 imm5
    */

-   /* Quickly skip over all of this for hopefully most instructions */
-   if ((INSN(27,24) & BITS4(1,1,0,0)) != BITS4(0,1,0,0))
-      goto after_load_store_ubyte_or_word;
+   /* Quickly skip over all of this for hopefully most instructions */
+   if ((INSN(27,24) & BITS4(1,1,0,0)) != BITS4(0,1,0,0))
+      goto after_load_store_ubyte_or_word;
+
+   summary = 0;
+   
+   /**/ if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 0) {
+      summary = 1 | 16;
+   }
+   else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 0
+                                          && INSN(4,4) == 0) {
+      summary = 1 | 32;
+   }
+   else if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 1) {
+      summary = 2 | 16;
+   }
+   else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 1
+                                          && INSN(4,4) == 0) {
+      summary = 2 | 32;
+   }
+   else if (INSN(27,24) == BITS4(0,1,0,0) && INSN(21,21) == 0) {
+      summary = 3 | 16;
+   }
+   else if (INSN(27,24) == BITS4(0,1,1,0) && INSN(21,21) == 0
+                                          && INSN(4,4) == 0) {
+      summary = 3 | 32;
+   }
+   else goto after_load_store_ubyte_or_word;
+
+   { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
+     UInt rD = (insn >> 12) & 0xF; /* 15:12 */
+     UInt rM = (insn >> 0)  & 0xF; /*  3:0  */
+     UInt bU = (insn >> 23) & 1;      /* 23 */
+     UInt bB = (insn >> 22) & 1;      /* 22 */
+     UInt bL = (insn >> 20) & 1;      /* 20 */
+     UInt imm12 = (insn >> 0) & 0xFFF; /* 11:0 */
+     UInt imm5  = (insn >> 7) & 0x1F;  /* 11:7 */
+     UInt sh2   = (insn >> 5) & 3;     /* 6:5 */
+
+     /* Skip some invalid cases, which would lead to two competing
+        updates to the same register, or which are otherwise
+        disallowed by the spec. */
+     switch (summary) {
+        case 1 | 16:
+           break;
+        case 1 | 32: 
+           if (rM == 15) goto after_load_store_ubyte_or_word;
+           break;
+        case 2 | 16: case 3 | 16:
+           if (rN == 15) goto after_load_store_ubyte_or_word;
+           if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
+           break;
+        case 2 | 32: case 3 | 32:
+           if (rM == 15) goto after_load_store_ubyte_or_word;
+           if (rN == 15) goto after_load_store_ubyte_or_word;
+           if (rN == rM) goto after_load_store_ubyte_or_word;
+           if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
+           break;
+        default:
+           vassert(0);
+     }
+
+     /* Now, we can't do a conditional load or store, since that very
+        likely will generate an exception.  So we have to take a side
+        exit at this point if the condition is false. */
+     if (condT != IRTemp_INVALID) {
+        mk_skip_over_A32_if_cond_is_false( condT );
+        condT = IRTemp_INVALID;
+     }
+     /* Ok, now we're unconditional.  Do the load or store. */
+
+     /* compute the effective address.  Bind it to a tmp since we
+        may need to use it twice. */
+     IRExpr* eaE = NULL;
+     switch (summary & 0xF0) {
+        case 16:
+           eaE = mk_EA_reg_plusminus_imm12( rN, bU, imm12, dis_buf );
+           break;
+        case 32:
+           eaE = mk_EA_reg_plusminus_shifted_reg( rN, bU, rM, sh2, imm5,
+                                                  dis_buf );
+           break;
+     }
+     vassert(eaE);
+     IRTemp eaT = newTemp(Ity_I32);
+     assign(eaT, eaE);
+
+     /* get the old Rn value */
+     IRTemp rnT = newTemp(Ity_I32);
+     assign(rnT, getIRegA(rN));
+
+     /* decide on the transfer address */
+     IRTemp taT = IRTemp_INVALID;
+     switch (summary & 0x0F) {
+        case 1: case 2: taT = eaT; break;
+        case 3:         taT = rnT; break;
+     }
+     vassert(taT != IRTemp_INVALID);
+
+     if (bL == 0) {
+       /* Store.  If necessary, update the base register before the
+          store itself, so that the common idiom of "str rX, [sp,
+          #-4]!" (store rX at sp-4, then do new sp = sp-4, a.k.a "push
+          rX") doesn't cause Memcheck to complain that the access is
+          below the stack pointer.  Also, not updating sp before the
+          store confuses Valgrind's dynamic stack-extending logic.  So
+          do it before the store.  Hence we need to snarf the store
+          data before doing the basereg update. */
+
+        /* get hold of the data to be stored */
+        IRTemp rDt = newTemp(Ity_I32);
+        assign(rDt, getIRegA(rD));
+
+        /* Update Rn if necessary. */
+        switch (summary & 0x0F) {
+           case 2: case 3:
+              putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
+              break;
+        }
+
+        /* generate the transfer */
+        if (bB == 0) { // word store
+           storeLE( mkexpr(taT), mkexpr(rDt) );
+        } else { // byte store
+           vassert(bB == 1);
+           storeLE( mkexpr(taT), unop(Iop_32to8, mkexpr(rDt)) );
+        }
+
+     } else {
+        /* Load */
+        vassert(bL == 1);
+
+        /* generate the transfer */
+        if (bB == 0) { // word load
+           putIRegA( rD, loadLE(Ity_I32, mkexpr(taT)),
+                     IRTemp_INVALID, Ijk_Boring );
+        } else { // byte load
+           vassert(bB == 1);
+           putIRegA( rD, unop(Iop_8Uto32, loadLE(Ity_I8, mkexpr(taT))),
+                     IRTemp_INVALID, Ijk_Boring );
+        }
+
+        /* Update Rn if necessary. */
+        switch (summary & 0x0F) {
+           case 2: case 3:
+              // should be assured by logic above:
+              if (bL == 1)
+                 vassert(rD != rN); /* since we just wrote rD */
+              putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
+              break;
+        }
+     }
+ 
+     switch (summary & 0x0F) {
+        case 1:  DIP("%sr%s%s r%u, %s\n",
+                     bL == 0 ? "st" : "ld",
+                     bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
+                 break;
+        case 2:  DIP("%sr%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
+                     bL == 0 ? "st" : "ld",
+                     bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
+                 break;
+        case 3:  DIP("%sr%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
+                     bL == 0 ? "st" : "ld",
+                     bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
+                 break;
+        default: vassert(0);
+     }
+
+     /* XXX deal with alignment constraints */
+
+     goto decode_success;
+
+     /* Complications:
+
+        For all loads: if the Amode specifies base register
+        writeback, and the same register is specified for Rd and Rn,
+        the results are UNPREDICTABLE.
+
+        For all loads and stores: if R15 is written, branch to
+        that address afterwards.
+
+        STRB: straightforward
+        LDRB: loaded data is zero extended
+        STR:  lowest 2 bits of address are ignored
+        LDR:  if the lowest 2 bits of the address are nonzero
+              then the loaded value is rotated right by 8 * the lowest 2 bits
+     */
+   }
+
+  after_load_store_ubyte_or_word:
+
+   /* --------------------- Load/store (sbyte & hword) -------- */
+   // LDRH LDRSH STRH LDRSB
+   /*                 31   27   23   19 15 11   7    3     # highest bit
+                        28   24   20 16 12    8    4    0
+      A5-36   1 | 16  cond 0001 U10L Rn Rd im4h 1SH1 im4l
+      A5-38   1 | 32  cond 0001 U00L Rn Rd 0000 1SH1 Rm
+      A5-40   2 | 16  cond 0001 U11L Rn Rd im4h 1SH1 im4l
+      A5-42   2 | 32  cond 0001 U01L Rn Rd 0000 1SH1 Rm
+      A5-44   3 | 16  cond 0000 U10L Rn Rd im4h 1SH1 im4l
+      A5-46   3 | 32  cond 0000 U00L Rn Rd 0000 1SH1 Rm
+   */
+   /* case coding:
+             1   at-ea               (access at ea)
+             2   at-ea-then-upd      (access at ea, then Rn = ea)
+             3   at-Rn-then-upd      (access at Rn, then Rn = ea)
+      ea coding
+             16  Rn +/- imm8
+             32  Rn +/- Rm
+   */
+   /* Quickly skip over all of this for hopefully most instructions */
+   if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0))
+      goto after_load_store_sbyte_or_hword;
+
+   /* Check the "1SH1" thing. */
+   if ((INSN(7,4) & BITS4(1,0,0,1)) != BITS4(1,0,0,1))
+      goto after_load_store_sbyte_or_hword;
+
+   summary = 0;
+
+   /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,0)) {
+      summary = 1 | 16;
+   }
+   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,0)) {
+      summary = 1 | 32;
+   }
+   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,1)) {
+      summary = 2 | 16;
+   }
+   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,1)) {
+      summary = 2 | 32;
+   }
+   else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(1,0)) {
+      summary = 3 | 16;
+   }
+   else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(0,0)) {
+      summary = 3 | 32;
+   }
+   else goto after_load_store_sbyte_or_hword;
+
+   { UInt rN   = (insn >> 16) & 0xF; /* 19:16 */
+     UInt rD   = (insn >> 12) & 0xF; /* 15:12 */
+     UInt rM   = (insn >> 0)  & 0xF; /*  3:0  */
+     UInt bU   = (insn >> 23) & 1;   /* 23 U=1 offset+, U=0 offset- */
+     UInt bL   = (insn >> 20) & 1;   /* 20 L=1 load, L=0 store */
+     UInt bH   = (insn >> 5) & 1;    /* H=1 halfword, H=0 byte */
+     UInt bS   = (insn >> 6) & 1;    /* S=1 signed, S=0 unsigned */
+     UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */
+
+     /* Skip combinations that are either meaningless or already
+        handled by main word-or-unsigned-byte load-store
+        instructions. */
+     if (bS == 0 && bH == 0) /* "unsigned byte" */
+        goto after_load_store_sbyte_or_hword;
+     if (bS == 1 && bL == 0) /* "signed store" */
+        goto after_load_store_sbyte_or_hword;
+
+     /* Require 11:8 == 0 for Rn +/- Rm cases */
+     if ((summary & 32) != 0 && (imm8 & 0xF0) != 0)
+        goto after_load_store_sbyte_or_hword;
+
+     /* Skip some invalid cases, which would lead to two competing
+        updates to the same register, or which are otherwise
+        disallowed by the spec. */
+     switch (summary) {
+        case 1 | 16:
+           break;
+        case 1 | 32: 
+           if (rM == 15) goto after_load_store_sbyte_or_hword;
+           break;
+        case 2 | 16: case 3 | 16:
+           if (rN == 15) goto after_load_store_sbyte_or_hword;
+           if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
+           break;
+        case 2 | 32: case 3 | 32:
+           if (rM == 15) goto after_load_store_sbyte_or_hword;
+           if (rN == 15) goto after_load_store_sbyte_or_hword;
+           if (rN == rM) goto after_load_store_sbyte_or_hword;
+           if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
+           break;
+        default:
+           vassert(0);
+     }
+
+     /* Now, we can't do a conditional load or store, since that very
+        likely will generate an exception.  So we have to take a side
+        exit at this point if the condition is false. */
+     if (condT != IRTemp_INVALID) {
+        mk_skip_over_A32_if_cond_is_false( condT );
+        condT = IRTemp_INVALID;
+     }
+     /* Ok, now we're unconditional.  Do the load or store. */
+
+     /* compute the effective address.  Bind it to a tmp since we
+        may need to use it twice. */
+     IRExpr* eaE = NULL;
+     switch (summary & 0xF0) {
+        case 16:
+           eaE = mk_EA_reg_plusminus_imm8( rN, bU, imm8, dis_buf );
+           break;
+        case 32:
+           eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
+           break;
+     }
+     vassert(eaE);
+     IRTemp eaT = newTemp(Ity_I32);
+     assign(eaT, eaE);
+
+     /* get the old Rn value */
+     IRTemp rnT = newTemp(Ity_I32);
+     assign(rnT, getIRegA(rN));
+
+     /* decide on the transfer address */
+     IRTemp taT = IRTemp_INVALID;
+     switch (summary & 0x0F) {
+        case 1: case 2: taT = eaT; break;
+        case 3:         taT = rnT; break;
+     }
+     vassert(taT != IRTemp_INVALID);
+
+     /* halfword store  H 1  L 0  S 0
+        uhalf load      H 1  L 1  S 0
+        shalf load      H 1  L 1  S 1
+        sbyte load      H 0  L 1  S 1
+     */
+     HChar* name = NULL;
+     /* generate the transfer */
+     /**/ if (bH == 1 && bL == 0 && bS == 0) { // halfword store
+        storeLE( mkexpr(taT), unop(Iop_32to16, getIRegA(rD)) );
+        name = "strh";
+     }
+     else if (bH == 1 && bL == 1 && bS == 0) { // uhalf load
+        putIRegA( rD, unop(Iop_16Uto32, loadLE(Ity_I16, mkexpr(taT))),
+                  IRTemp_INVALID, Ijk_Boring );
+        name = "ldrh";
+     }
+     else if (bH == 1 && bL == 1 && bS == 1) { // shalf load
+        putIRegA( rD, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(taT))),
+                  IRTemp_INVALID, Ijk_Boring );
+        name = "ldrsh";
+     }
+     else if (bH == 0 && bL == 1 && bS == 1) { // sbyte load
+        putIRegA( rD, unop(Iop_8Sto32, loadLE(Ity_I8, mkexpr(taT))),
+                  IRTemp_INVALID, Ijk_Boring );
+        name = "ldrsb";
+     }
+     else
+        vassert(0); // should be assured by logic above
+
+     /* Update Rn if necessary. */
+     switch (summary & 0x0F) {
+        case 2: case 3:
+           // should be assured by logic above:
+           if (bL == 1)
+              vassert(rD != rN); /* since we just wrote rD */
+           putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
+           break;
+     }
+
+     switch (summary & 0x0F) {
+        case 1:  DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
+                 break;
+        case 2:  DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
+                     name, nCC(INSN_COND), rD, dis_buf);
+                 break;
+        case 3:  DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
+                     name, nCC(INSN_COND), rD, dis_buf);
+                 break;
+        default: vassert(0);
+     }
+
+     /* XXX deal with alignment constraints */
+
+     goto decode_success;
+
+     /* Complications:
+
+        For all loads: if the Amode specifies base register
+        writeback, and the same register is specified for Rd and Rn,
+        the results are UNPREDICTABLE.
+
+        For all loads and stores: if R15 is written, branch to
+        that address afterwards.
+
+        Misaligned halfword stores => Unpredictable
+        Misaligned halfword loads  => Unpredictable
+     */
+   }
+
+  after_load_store_sbyte_or_hword:
+
+   /* --------------------- Load/store multiple -------------- */
+   // LD/STMIA LD/STMIB LD/STMDA LD/STMDB
+   // Remarkably complex and difficult to get right
+   // match 27:20 as 100XX0WL
+   if (BITS8(1,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))) {
+      // A5-50 LD/STMIA  cond 1000 10WL Rn RegList
+      // A5-51 LD/STMIB  cond 1001 10WL Rn RegList
+      // A5-53 LD/STMDA  cond 1000 00WL Rn RegList
+      // A5-53 LD/STMDB  cond 1001 00WL Rn RegList
+      //                   28   24   20 16       0
+
+      UInt bINC    = (insn >> 23) & 1;
+      UInt bBEFORE = (insn >> 24) & 1;
+
+      UInt bL      = (insn >> 20) & 1;  /* load=1, store=0 */
+      UInt bW      = (insn >> 21) & 1;  /* Rn wback=1, no wback=0 */
+      UInt rN      = (insn >> 16) & 0xF;
+      UInt regList = insn & 0xFFFF;
+      /* Skip some invalid cases, which would lead to two competing
+         updates to the same register, or which are otherwise
+         disallowed by the spec.  Note the test above has required
+         that S == 0, since that looks like a kernel-mode only thing.
+         Done by forcing the real pattern, viz 100XXSWL to actually be
+         100XX0WL. */
+      if (rN == 15) goto after_load_store_multiple;
+      // reglist can't be empty
+      if (regList == 0) goto after_load_store_multiple;
+      // if requested to writeback Rn, and this is a load instruction,
+      // then Rn can't appear in RegList, since we'd have two competing
+      // new values for Rn.  We do however accept this case for store
+      // instructions.
+      if (bW == 1 && bL == 1 && ((1 << rN) & regList) > 0)
+         goto after_load_store_multiple;
+
+      /* Now, we can't do a conditional load or store, since that very
+         likely will generate an exception.  So we have to take a side
+         exit at this point if the condition is false. */
+      if (condT != IRTemp_INVALID) {
+         mk_skip_over_A32_if_cond_is_false( condT );
+         condT = IRTemp_INVALID;
+      }
+
+      /* Ok, now we're unconditional.  Generate the IR. */
+      mk_ldm_stm( True/*arm*/, rN, bINC, bBEFORE, bW, bL, regList );
+
+      DIP("%sm%c%c%s r%u%s, {0x%04x}\n",
+          bL == 1 ? "ld" : "st", bINC ? 'i' : 'd', bBEFORE ? 'b' : 'a',
+          nCC(INSN_COND),
+          rN, bW ? "!" : "", regList);
+
+      goto decode_success;
+   }
+
+  after_load_store_multiple:
+
+   /* --------------------- Control flow --------------------- */
+   // B, BL (Branch, or Branch-and-Link, to immediate offset)
+   //
+   if (BITS8(1,0,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))) {
+      UInt link   = (insn >> 24) & 1;
+      UInt uimm24 = insn & ((1<<24)-1);
+      Int  simm24 = (Int)uimm24;
+      UInt dst    = guest_R15_curr_instr_notENC + 8
+                    + (((simm24 << 8) >> 8) << 2);
+      IRJumpKind jk = link ? Ijk_Call : Ijk_Boring;
+      if (link) {
+         putIRegA(14, mkU32(guest_R15_curr_instr_notENC + 4),
+                      condT, Ijk_Boring);
+      }
+      if (condT == IRTemp_INVALID) {
+         /* unconditional transfer to 'dst'.  See if we can simply
+            continue tracing at the destination. */
+         if (resteerOkFn( callback_opaque, (Addr64)dst )) {
+            /* yes */
+            dres.whatNext   = Dis_ResteerU;
+            dres.continueAt = (Addr64)dst;
+         } else {
+            /* no; terminate the SB at this point. */
+            irsb->next     = mkU32(dst);
+            irsb->jumpkind = jk;
+            dres.whatNext  = Dis_StopHere;
+         }
+         DIP("b%s 0x%x\n", link ? "l" : "", dst);
+      } else {
+         /* conditional transfer to 'dst' */
+         HChar* comment = "";
+
+         /* First see if we can do some speculative chasing into one
+            arm or the other.  Be conservative and only chase if
+            !link, that is, this is a normal conditional branch to a
+            known destination. */
+         if (!link
+             && resteerCisOk
+             && vex_control.guest_chase_cond
+             && dst < guest_R15_curr_instr_notENC
+             && resteerOkFn( callback_opaque, (Addr64)(Addr32)dst) ) {
+            /* Speculation: assume this backward branch is taken.  So
+               we need to emit a side-exit to the insn following this
+               one, on the negation of the condition, and continue at
+               the branch target address (dst). */
+            stmt( IRStmt_Exit( unop(Iop_Not1,
+                                    unop(Iop_32to1, mkexpr(condT))),
+                               Ijk_Boring,
+                               IRConst_U32(guest_R15_curr_instr_notENC+4) ));
+            dres.whatNext   = Dis_ResteerC;
+            dres.continueAt = (Addr64)(Addr32)dst;
+            comment = "(assumed taken)";
+         }
+         else
+         if (!link
+             && resteerCisOk
+             && vex_control.guest_chase_cond
+             && dst >= guest_R15_curr_instr_notENC
+             && resteerOkFn( callback_opaque, 
+                             (Addr64)(Addr32)
+                                     (guest_R15_curr_instr_notENC+4)) ) {
+            /* Speculation: assume this forward branch is not taken.
+               So we need to emit a side-exit to dst (the dest) and
+               continue disassembling at the insn immediately
+               following this one. */
+            stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(condT)),
+                               Ijk_Boring,
+                               IRConst_U32(dst) ));
+            dres.whatNext   = Dis_ResteerC;
+            dres.continueAt = (Addr64)(Addr32)
+                                      (guest_R15_curr_instr_notENC+4);
+            comment = "(assumed not taken)";
+         }
+         else {
+            /* Conservative default translation - end the block at
+               this point. */
+         stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(condT)),
+                            jk, IRConst_U32(dst) ));
+         irsb->next     = mkU32(guest_R15_curr_instr_notENC + 4);
+         irsb->jumpkind = jk;
+         dres.whatNext  = Dis_StopHere;
+         }
+         DIP("b%s%s 0x%x %s\n", link ? "l" : "", nCC(INSN_COND),
+             dst, comment);
+      }
+      goto decode_success;
+   }
+
+   // B, BL (Branch, or Branch-and-Link, to a register)
+   // NB: interworking branch
+   if (INSN(27,20) == BITS8(0,0,0,1,0,0,1,0)
+       && INSN(19,12) == BITS8(1,1,1,1,1,1,1,1)
+       && (INSN(11,4) == BITS8(1,1,1,1,0,0,1,1)
+           || INSN(11,4) == BITS8(1,1,1,1,0,0,0,1))) {
+      IRExpr* dst;
+      UInt    link = (INSN(11,4) >> 1) & 1;
+      UInt    rM   = INSN(3,0);
+      // we don't decode the case (link && rM == 15), as that's
+      // Unpredictable.
+      if (!(link && rM == 15)) {
+         if (condT != IRTemp_INVALID) {
+            mk_skip_over_A32_if_cond_is_false( condT );
+         }
+         // rM contains an interworking address exactly as we require
+         // (with continuation CPSR.T in bit 0), so we can use it
+         // as-is, with no masking.
+         dst = getIRegA(rM);
+         if (link) {
+            putIRegA( 14, mkU32(guest_R15_curr_instr_notENC + 4),
+                      IRTemp_INVALID/*because AL*/, Ijk_Boring );
+         }
+         irsb->next     = dst;
+         irsb->jumpkind = link ? Ijk_Call
+                               : (rM == 14 ? Ijk_Ret : Ijk_Boring);
+         dres.whatNext  = Dis_StopHere;
+         if (condT == IRTemp_INVALID) {
+            DIP("b%sx r%u\n", link ? "l" : "", rM);
+         } else {
+            DIP("b%sx%s r%u\n", link ? "l" : "", nCC(INSN_COND), rM);
+         }
+         goto decode_success;
+      }
+      /* else: (link && rM == 15): just fall through */
+   }
+
+   /* --- NB: ARM interworking branches are in NV space, hence
+      are handled elsewhere by decode_NV_instruction.
+      ---
+   */

 
 

-   summary = 0;
-   
-   /**/ if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 0) {
-      summary = 1 | 16;
+   /* --------------------- Clz --------------------- */
+   // CLZ
+   if (INSN(27,20) == BITS8(0,0,0,1,0,1,1,0)
+       && INSN(19,16) == BITS4(1,1,1,1)
+       && INSN(11,4) == BITS8(1,1,1,1,0,0,0,1)) {
+      UInt rD = INSN(15,12);
+      UInt rM = INSN(3,0);
+      IRTemp arg = newTemp(Ity_I32);
+      IRTemp res = newTemp(Ity_I32);
+      assign(arg, getIRegA(rM));
+      assign(res, IRExpr_Mux0X(
+                     unop(Iop_1Uto8,binop(Iop_CmpEQ32, mkexpr(arg),
+                                                       mkU32(0))),
+                     unop(Iop_Clz32, mkexpr(arg)),
+                     mkU32(32)
+            ));
+      putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
+      DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
+      goto decode_success;

    }
    }

-   else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 0
-                                          && INSN(4,4) == 0) {
-      summary = 1 | 32;
+
+   /* --------------------- Mul etc --------------------- */
+   // MUL
+   if (BITS8(0,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
+       && INSN(15,12) == BITS4(0,0,0,0)
+       && INSN(7,4) == BITS4(1,0,0,1)) {
+      UInt bitS = (insn >> 20) & 1; /* 20:20 */
+      UInt rD = INSN(19,16);
+      UInt rS = INSN(11,8);
+      UInt rM = INSN(3,0);
+      if (rD == 15 || rM == 15 || rS == 15) {
+         /* Unpredictable; don't decode; fall through */
+      } else {
+         IRTemp argL = newTemp(Ity_I32);
+         IRTemp argR = newTemp(Ity_I32);
+         IRTemp res  = newTemp(Ity_I32);
+         IRTemp oldC = IRTemp_INVALID;
+         IRTemp oldV = IRTemp_INVALID;
+         assign( argL, getIRegA(rM));
+         assign( argR, getIRegA(rS));
+         assign( res, binop(Iop_Mul32, mkexpr(argL), mkexpr(argR)) );
+         if (bitS) {
+            oldC = newTemp(Ity_I32);
+            assign(oldC, mk_armg_calculate_flag_c());
+            oldV = newTemp(Ity_I32);
+            assign(oldV, mk_armg_calculate_flag_v());
+         }
+         // now update guest state
+         putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
+         if (bitS) {
+            IRTemp pair = newTemp(Ity_I32);
+            assign( pair, binop(Iop_Or32,
+                                binop(Iop_Shl32, mkexpr(oldC), mkU8(1)),
+                                mkexpr(oldV)) );
+            setFlags_D1_ND( ARMG_CC_OP_MUL, res, pair, condT );
+         }
+         DIP("mul%c%s r%u, r%u, r%u\n",
+             bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
+         goto decode_success;
+      }
+      /* fall through */
+   }
+
+   // MLA, MLS
+   if (BITS8(0,0,0,0,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
+       && INSN(7,4) == BITS4(1,0,0,1)) {
+      UInt bitS  = (insn >> 20) & 1; /* 20:20 */
+      UInt isMLS = (insn >> 22) & 1; /* 22:22 */
+      UInt rD = INSN(19,16);
+      UInt rN = INSN(15,12);
+      UInt rS = INSN(11,8);
+      UInt rM = INSN(3,0);
+      if (bitS == 1 && isMLS == 1) {
+         /* This isn't allowed (MLS that sets flags).  don't decode;
+            fall through */
+      }
+      else
+      if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
+         /* Unpredictable; don't decode; fall through */
+      } else {
+         IRTemp argL = newTemp(Ity_I32);
+         IRTemp argR = newTemp(Ity_I32);
+         IRTemp argP = newTemp(Ity_I32);
+         IRTemp res  = newTemp(Ity_I32);
+         IRTemp oldC = IRTemp_INVALID;
+         IRTemp oldV = IRTemp_INVALID;
+         assign( argL, getIRegA(rM));
+         assign( argR, getIRegA(rS));
+         assign( argP, getIRegA(rN));
+         assign( res, binop(isMLS ? Iop_Sub32 : Iop_Add32,
+                            mkexpr(argP),
+                            binop(Iop_Mul32, mkexpr(argL), mkexpr(argR)) ));
+         if (bitS) {
+            vassert(!isMLS); // guaranteed above
+            oldC = newTemp(Ity_I32);
+            assign(oldC, mk_armg_calculate_flag_c());
+            oldV = newTemp(Ity_I32);
+            assign(oldV, mk_armg_calculate_flag_v());
+         }
+         // now update guest state
+         putIRegA( rD, mkexpr(res), condT, Ijk_Boring );
+         if (bitS) {
+            IRTemp pair = newTemp(Ity_I32);
+            assign( pair, binop(Iop_Or32,
+                                binop(Iop_Shl32, mkexpr(oldC), mkU8(1)),
+                                mkexpr(oldV)) );
+            setFlags_D1_ND( ARMG_CC_OP_MUL, res, pair, condT );
+         }
+         DIP("ml%c%c%s r%u, r%u, r%u, r%u\n",
+             isMLS ? 's' : 'a', bitS ? 's' : ' ',
+             nCC(INSN_COND), rD, rM, rS, rN);
+         goto decode_success;
+      }
+      /* fall through */
+   }
+
+   // SMULL, UMULL
+   if (BITS8(0,0,0,0,1,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
+       && INSN(7,4) == BITS4(1,0,0,1)) {
+      UInt bitS = (insn >> 20) & 1; /* 20:20 */
+      UInt rDhi = INSN(19,16);
+      UInt rDlo = INSN(15,12);
+      UInt rS   = INSN(11,8);
+      UInt rM   = INSN(3,0);
+      UInt isS  = (INSN(27,20) >> 2) & 1; /* 22:22 */
+      if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo)  {
+         /* Unpredictable; don't decode; fall through */
+      } else {
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         IRTemp res   = newTemp(Ity_I64);
+         IRTemp resHi = newTemp(Ity_I32);
+         IRTemp resLo = newTemp(Ity_I32);
+         IRTemp oldC  = IRTemp_INVALID;
+         IRTemp oldV  = IRTemp_INVALID;
+         IROp   mulOp = isS ? Iop_MullS32 : Iop_MullU32;
+         assign( argL, getIRegA(rM));
+         assign( argR, getIRegA(rS));
+         assign( res, binop(mulOp, mkexpr(argL), mkexpr(argR)) );
+         assign( resHi, unop(Iop_64HIto32, mkexpr(res)) );
+         assign( resLo, unop(Iop_64to32, mkexpr(res)) );
+         if (bitS) {
+            oldC = newTemp(Ity_I32);
+            assign(oldC, mk_armg_calculate_flag_c());
+            oldV = newTemp(Ity_I32);
+            assign(oldV, mk_armg_calculate_flag_v());
+         }
+         // now update guest state
+         putIRegA( rDhi, mkexpr(resHi), condT, Ijk_Boring );
+         putIRegA( rDlo, mkexpr(resLo), condT, Ijk_Boring );
+         if (bitS) {
+            IRTemp pair = newTemp(Ity_I32);
+            assign( pair, binop(Iop_Or32,
+                                binop(Iop_Shl32, mkexpr(oldC), mkU8(1)),
+                                mkexpr(oldV)) );
+            setFlags_D1_D2_ND( ARMG_CC_OP_MULL, resLo, resHi, pair, condT );
+         }
+         DIP("%cmull%c%s r%u, r%u, r%u, r%u\n",
+             isS ? 's' : 'u', bitS ? 's' : ' ',
+             nCC(INSN_COND), rDlo, rDhi, rM, rS);
+         goto decode_success;
+      }
+      /* fall through */
+   }
+
+   // SMLAL, UMLAL
+   if (BITS8(0,0,0,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
+       && INSN(7,4) == BITS4(1,0,0,1)) {
+      UInt bitS = (insn >> 20) & 1; /* 20:20 */
+      UInt rDhi = INSN(19,16);
+      UInt rDlo = INSN(15,12);
+      UInt rS   = INSN(11,8);
+      UInt rM   = INSN(3,0);
+      UInt isS  = (INSN(27,20) >> 2) & 1; /* 22:22 */
+      if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo)  {
+         /* Unpredictable; don't decode; fall through */
+      } else {
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         IRTemp old   = newTemp(Ity_I64);
+         IRTemp res   = newTemp(Ity_I64);
+         IRTemp resHi = newTemp(Ity_I32);
+         IRTemp resLo = newTemp(Ity_I32);
+         IRTemp oldC  = IRTemp_INVALID;
+         IRTemp oldV  = IRTemp_INVALID;
+         IROp   mulOp = isS ? Iop_MullS32 : Iop_MullU32;
+         assign( argL, getIRegA(rM));
+         assign( argR, getIRegA(rS));
+         assign( old, binop(Iop_32HLto64, getIRegA(rDhi), getIRegA(rDlo)) );
+         assign( res, binop(Iop_Add64,
+                            mkexpr(old),
+                            binop(mulOp, mkexpr(argL), mkexpr(argR))) );
+         assign( resHi, unop(Iop_64HIto32, mkexpr(res)) );
+         assign( resLo, unop(Iop_64to32, mkexpr(res)) );
+         if (bitS) {
+            oldC = newTemp(Ity_I32);
+            assign(oldC, mk_armg_calculate_flag_c());
+            oldV = newTemp(Ity_I32);
+            assign(oldV, mk_armg_calculate_flag_v());
+         }
+         // now update guest state
+         putIRegA( rDhi, mkexpr(resHi), condT, Ijk_Boring );
+         putIRegA( rDlo, mkexpr(resLo), condT, Ijk_Boring );
+         if (bitS) {
+            IRTemp pair = newTemp(Ity_I32);
+            assign( pair, binop(Iop_Or32,
+                                binop(Iop_Shl32, mkexpr(oldC), mkU8(1)),
+                                mkexpr(oldV)) );
+            setFlags_D1_D2_ND( ARMG_CC_OP_MULL, resLo, resHi, pair, condT );
+         }
+         DIP("%cmlal%c%s r%u, r%u, r%u, r%u\n",
+             isS ? 's' : 'u', bitS ? 's' : ' ', nCC(INSN_COND),
+             rDlo, rDhi, rM, rS);
+         goto decode_success;
+      }
+      /* fall through */

    }
    }

-   else if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 1) {
-      summary = 2 | 16;
+
+   /* --------------------- Msr etc --------------------- */
+
+   // MSR cpsr_f, #imm8  (immediate form, flags only)
+   if (BITS8(0,0,1,1,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && INSN(15,12) == BITS4(1,1,1,1)) {
+      UInt bitR = (insn >> 22) & 1;
+      if (bitR == 0 && INSN(19,16) == BITS4(1,0,0,0)) {
+         UInt   imm = (INSN(11,0) >> 0) & 0xFF;
+         UInt   rot = 2 * ((INSN(11,0) >> 8) & 0xF);
+         IRTemp immT = newTemp(Ity_I32);
+         vassert(rot <= 30);
+         imm = ROR32(imm, rot);
+         imm &= 0xFF000000;
+         imm &= (ARMG_CC_MASK_N | ARMG_CC_MASK_Z 
+                 | ARMG_CC_MASK_V | ARMG_CC_MASK_C | ARMG_CC_MASK_Q);
+         assign( immT, mkU32(imm & 0xF0000000) );
+         setFlags_D1(ARMG_CC_OP_COPY, immT, condT);
+         // Set QFLAG32 to a zero or nonzero value, depending on #imm8.
+         IRTemp qnewT = newTemp(Ity_I32);
+         assign(qnewT, mkU32( imm & ARMG_CC_MASK_Q ));
+         put_QFLAG32(qnewT, condT);
+         DIP("msr%s cpsr_f, #0x%08x\n", nCC(INSN_COND), imm);
+         goto decode_success;
+      }
+      /* fall through */

    }
    }

-   else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 1
-                                          && INSN(4,4) == 0) {
-      summary = 2 | 32;
+
+   // MSR cpsr_f, rM  (flags only)
+   if (BITS8(0,0,0,1,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && INSN(15,12) == BITS4(1,1,1,1)) {
+      UInt bitR = (insn >> 22) & 1;
+      if (bitR == 0 && INSN(19,16) == BITS4(1,0,0,0)
+          && INSN(11,4) == BITS8(0,0,0,0,0,0,0,0)
+          && INSN(3,0) != 15) {
+         UInt   rM  = INSN(3,0);
+         IRTemp rMt = newTemp(Ity_I32);
+         assign(rMt, getIRegA(rM));
+         IRTemp immT = newTemp(Ity_I32);
+         assign(immT, binop(Iop_And32, mkexpr(rMt), mkU32(0xF0000000)) );
+         setFlags_D1(ARMG_CC_OP_COPY, immT, condT);
+         IRTemp qnewT = newTemp(Ity_I32);
+         assign(qnewT, binop(Iop_And32, mkexpr(rMt), mkU32(ARMG_CC_MASK_Q)));
+         put_QFLAG32(qnewT, condT);
+         DIP("msr%s cpsr_f, r%u\n", nCC(INSN_COND), rM);
+         goto decode_success;
+      }
+      /* fall through */

    }
    }

-   else if (INSN(27,24) == BITS4(0,1,0,0) && INSN(21,21) == 0) {
-      summary = 3 | 16;
+
+   // MRS rD, cpsr
+   if (BITS8(0,0,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && INSN(19,16) == BITS4(1,1,1,1)
+       && INSN(11,0) == 0) {
+      UInt bitR = (insn >> 22) & 1;
+      UInt rD   = INSN(15,12);
+      if (bitR == 0 && rD != 15) {
+         IRTemp res1 = newTemp(Ity_I32);
+         // Get NZCV
+         assign( res1, mk_armg_calculate_flags_nzcv() );
+         /// OR in the Q value
+         IRTemp res2 = newTemp(Ity_I32);
+         assign(
+            res2,
+            binop(Iop_Or32,
+                  mkexpr(res1),
+                  binop(Iop_Shl32,
+                        unop(Iop_1Uto32,
+                             binop(Iop_CmpNE32,
+                                   mkexpr(get_QFLAG32()),
+                                   mkU32(0))),
+                        mkU8(ARMG_CC_SHIFT_Q)))
+         );
+         putIRegA( rD, mkexpr(res2), condT, Ijk_Boring );
+         DIP("mrs%s r%u, cpsr\n", nCC(INSN_COND), rD);
+         goto decode_success;
+      }
+      /* fall through */

    }
    }

-   else if (INSN(27,24) == BITS4(0,1,1,0) && INSN(21,21) == 0
-                                          && INSN(4,4) == 0) {
-      summary = 3 | 32;
+
+   /* --------------------- Svc --------------------- */
+   if (BITS8(1,1,1,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))) {
+      UInt imm24 = (insn >> 0) & 0xFFFFFF;
+      if (imm24 == 0) {
+         /* A syscall.  We can't do this conditionally, hence: */
+         if (condT != IRTemp_INVALID) {
+            mk_skip_over_A32_if_cond_is_false( condT );
+         }
+         // AL after here
+         irsb->next     = mkU32( guest_R15_curr_instr_notENC + 4 );
+         irsb->jumpkind = Ijk_Sys_syscall;
+         dres.whatNext  = Dis_StopHere;
+         DIP("svc%s #0x%08x\n", nCC(INSN_COND), imm24);
+         goto decode_success;
+      }
+      /* fall through */

    }
    }

-   else goto after_load_store_ubyte_or_word;

 
 

-   { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
-     UInt rD = (insn >> 12) & 0xF; /* 15:12 */
-     UInt rM = (insn >> 0)  & 0xF; /*  3:0  */
-     UInt bU = (insn >> 23) & 1;      /* 23 */
-     UInt bB = (insn >> 22) & 1;      /* 22 */
-     UInt bL = (insn >> 20) & 1;      /* 20 */
-     UInt imm12 = (insn >> 0) & 0xFFF; /* 11:0 */
-     UInt imm5  = (insn >> 7) & 0x1F;  /* 11:7 */
-     UInt sh2   = (insn >> 5) & 3;     /* 6:5 */
+   /* ------------------------ swp ------------------------ */

 
 

-     /* Skip some invalid cases, which would lead to two competing
-        updates to the same register, or which are otherwise
-        disallowed by the spec. */
-     switch (summary) {
-        case 1 | 16:
-           break;
-        case 1 | 32: 
-           if (rM == 15) goto after_load_store_ubyte_or_word;
-           break;
-        case 2 | 16: case 3 | 16:
-           if (rN == 15) goto after_load_store_ubyte_or_word;
-           if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
-           break;
-        case 2 | 32: case 3 | 32:
-           if (rM == 15) goto after_load_store_ubyte_or_word;
-           if (rN == 15) goto after_load_store_ubyte_or_word;
-           if (rN == rM) goto after_load_store_ubyte_or_word;
-           if (bL == 1 && rN == rD) goto after_load_store_ubyte_or_word;
-           break;
-        default:
-           vassert(0);
-     }
+   // SWP, SWPB
+   if (BITS8(0,0,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(0,0,0,0) == INSN(11,8)
+       && BITS4(1,0,0,1) == INSN(7,4)) {
+      UInt   rN   = INSN(19,16);
+      UInt   rD   = INSN(15,12);
+      UInt   rM   = INSN(3,0);
+      IRTemp tRn  = newTemp(Ity_I32);
+      IRTemp tNew = newTemp(Ity_I32);
+      IRTemp tOld = IRTemp_INVALID;
+      IRTemp tSC1 = newTemp(Ity_I1);
+      UInt   isB  = (insn >> 22) & 1;

 
 

-     /* Now, we can't do a conditional load or store, since that very
-        likely will generate an exception.  So we have to take a side
-        exit at this point if the condition is false. */
-     if (condT != IRTemp_INVALID) {
-        mk_skip_to_next_if_cond_is_false( condT );
-        condT = IRTemp_INVALID;
-     }
-     /* Ok, now we're unconditional.  Do the load or store. */
+      if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
+         /* undecodable; fall through */
+      } else {
+         /* make unconditional */
+         if (condT != IRTemp_INVALID) {
+            mk_skip_over_A32_if_cond_is_false( condT );
+            condT = IRTemp_INVALID;
+         }
+         /* Ok, now we're unconditional.  Generate a LL-SC loop. */
+         assign(tRn, getIRegA(rN));
+         assign(tNew, getIRegA(rM));
+         if (isB) {
+            /* swpb */
+            tOld = newTemp(Ity_I8);
+            stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn),
+                              NULL/*=>isLL*/) );
+            stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn),
+                              unop(Iop_32to8, mkexpr(tNew))) );
+         } else {
+            /* swp */
+            tOld = newTemp(Ity_I32);
+            stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn),
+                              NULL/*=>isLL*/) );
+            stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn),
+                              mkexpr(tNew)) );
+         }
+         stmt( IRStmt_Exit(unop(Iop_Not1, mkexpr(tSC1)),
+                           /*Ijk_NoRedir*/Ijk_Boring,
+                           IRConst_U32(guest_R15_curr_instr_notENC)) );
+         putIRegA(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
+                      IRTemp_INVALID, Ijk_Boring);
+         DIP("swp%s%s r%u, r%u, [r%u]\n",
+             isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
+         goto decode_success;
+      }
+      /* fall through */
+   }

 
 

-     /* compute the effective address.  Bind it to a tmp since we
-        may need to use it twice. */
-     IRExpr* eaE = NULL;
-     switch (summary & 0xF0) {
-        case 16:
-           eaE = mk_EA_reg_plusminus_imm12( rN, bU, imm12, dis_buf );
-           break;
-        case 32:
-           eaE = mk_EA_reg_plusminus_shifted_reg( rN, bU, rM, sh2, imm5,
-                                                  dis_buf );
-           break;
-     }
-     vassert(eaE);
-     IRTemp eaT = newTemp(Ity_I32);
-     assign(eaT, eaE);
+   /* ----------------------------------------------------------- */
+   /* -- ARMv6 instructions                                    -- */
+   /* ----------------------------------------------------------- */

 
 

-     /* get the old Rn value */
-     IRTemp rnT = newTemp(Ity_I32);
-     assign(rnT, getIReg(rN));
+   /* --------------------- ldrex, strex --------------------- */

 
 

-     /* decide on the transfer address */
-     IRTemp taT = IRTemp_INVALID;
-     switch (summary & 0x0F) {
-        case 1: case 2: taT = eaT; break;
-        case 3:         taT = rnT; break;
-     }
-     vassert(taT != IRTemp_INVALID);
+   // LDREX
+   if (0x01900F9F == (insn & 0x0FF00FFF)) {
+      UInt rT = INSN(15,12);
+      UInt rN = INSN(19,16);
+      if (rT == 15 || rN == 15 || rT == 14 /* || (rT & 1)*/) {
+         /* undecodable; fall through */
+      } else {
+         IRTemp res;
+         /* make unconditional */
+         if (condT != IRTemp_INVALID) {
+            mk_skip_over_A32_if_cond_is_false( condT );
+            condT = IRTemp_INVALID;
+         }
+         /* Ok, now we're unconditional.  Do the load. */
+         res = newTemp(Ity_I32);
+         stmt( IRStmt_LLSC(Iend_LE, res, getIRegA(rN),
+                           NULL/*this is a load*/) );
+         putIRegA(rT, mkexpr(res), IRTemp_INVALID, Ijk_Boring);
+         DIP("ldrex%s r%u, [r%u]\n", nCC(INSN_COND), rT, rN);
+         goto decode_success;
+      }
+      /* fall through */
+   }

 
 

-     if (bL == 0) {
-       /* Store.  If necessary, update the base register before the
-          store itself, so that the common idiom of "str rX, [sp,
-          #-4]!" (store rX at sp-4, then do new sp = sp-4, a.k.a "push
-          rX") doesn't cause Memcheck to complain that the access is
-          below the stack pointer.  Also, not updating sp before the
-          store confuses Valgrind's dynamic stack-extending logic.  So
-          do it before the store.  Hence we need to snarf the store
-          data before doing the basereg update. */
+   // STREX
+   if (0x01800F90 == (insn & 0x0FF00FF0)) {
+      UInt rT = INSN(3,0);
+      UInt rN = INSN(19,16);
+      UInt rD = INSN(15,12);
+      if (rT == 15 || rN == 15 || rD == 15
+          || rT == 14 /* || (rT & 1)*/
+          || rD == rT || rN == rT) {
+         /* undecodable; fall through */
+      } else {
+         IRTemp resSC1, resSC32;
+
+         /* make unconditional */
+         if (condT != IRTemp_INVALID) {
+            mk_skip_over_A32_if_cond_is_false( condT );
+            condT = IRTemp_INVALID;
+         }
+
+         /* Ok, now we're unconditional.  Do the store. */
+         resSC1 = newTemp(Ity_I1);
+         stmt( IRStmt_LLSC(Iend_LE, resSC1, getIRegA(rN), getIRegA(rT)) );
+
+         /* Set rD to 1 on failure, 0 on success.  Currently we have
+            resSC1 == 0 on failure, 1 on success. */
+         resSC32 = newTemp(Ity_I32);
+         assign(resSC32,
+                unop(Iop_1Uto32, unop(Iop_Not1, mkexpr(resSC1))));
+
+         putIRegA(rD, mkexpr(resSC32),
+                      IRTemp_INVALID, Ijk_Boring);
+         DIP("strex%s r%u, r%u, [r%u]\n", nCC(INSN_COND), rD, rT, rN);
+         goto decode_success;
+      }
+      /* fall through */
+   }
+
+   /* --------------------- movw, movt --------------------- */
+   if (0x03000000 == (insn & 0x0FF00000)
+       || 0x03400000 == (insn & 0x0FF00000)) /* pray for CSE */ {
+      UInt rD    = INSN(15,12);
+      UInt imm16 = (insn & 0xFFF) | ((insn >> 4) & 0x0000F000);
+      UInt isT   = (insn >> 22) & 1;
+      if (rD == 15) {
+         /* forget it */
+      } else {
+         if (isT) {
+            putIRegA(rD,
+                     binop(Iop_Or32,
+                           binop(Iop_And32, getIRegA(rD), mkU32(0xFFFF)),
+                           mkU32(imm16 << 16)),
+                     condT, Ijk_Boring);
+            DIP("movt%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
+            goto decode_success;
+         } else {
+            putIRegA(rD, mkU32(imm16), condT, Ijk_Boring);
+            DIP("movw%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
+            goto decode_success;
+         }
+      }
+      /* fall through */
+   }

 
 

-        /* get hold of the data to be stored */
-        IRTemp rDt = newTemp(Ity_I32);
-        assign(rDt, getIReg(rD));
+   /* ------------------- {u,s}xt{b,h}{,16} ------------------- */
+   if (BITS8(0,1,1,0,1, 0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,0,0))
+       && BITS4(1,1,1,1) == INSN(19,16)
+       && BITS4(0,1,1,1) == INSN(7,4)
+       && BITS4(0,0, 0,0) == (INSN(11,8) & BITS4(0,0,1,1))) {
+      UInt subopc = INSN(27,20) & BITS8(0,0,0,0,0, 1,1,1);
+      if (subopc != BITS4(0,0,0,1) && subopc != BITS4(0,1,0,1)) {
+         Int    rot  = (INSN(11,8) >> 2) & 3;
+         UInt   rM   = INSN(3,0);
+         UInt   rD   = INSN(15,12);
+         IRTemp srcT = newTemp(Ity_I32);
+         IRTemp rotT = newTemp(Ity_I32);
+         IRTemp dstT = newTemp(Ity_I32);
+         HChar* nm   = "???";
+         assign(srcT, getIRegA(rM));
+         assign(rotT, genROR32(srcT, 8 * rot)); /* 0, 8, 16 or 24 only */
+         switch (subopc) {
+            case BITS4(0,1,1,0): // UXTB
+               assign(dstT, unop(Iop_8Uto32, unop(Iop_32to8, mkexpr(rotT))));
+               nm = "uxtb";
+               break;
+            case BITS4(0,0,1,0): // SXTB
+               assign(dstT, unop(Iop_8Sto32, unop(Iop_32to8, mkexpr(rotT))));
+               nm = "sxtb";
+               break;
+            case BITS4(0,1,1,1): // UXTH
+               assign(dstT, unop(Iop_16Uto32, unop(Iop_32to16, mkexpr(rotT))));
+               nm = "uxth";
+               break;
+            case BITS4(0,0,1,1): // SXTH
+               assign(dstT, unop(Iop_16Sto32, unop(Iop_32to16, mkexpr(rotT))));
+               nm = "sxth";
+               break;
+            case BITS4(0,1,0,0): // UXTB16
+               assign(dstT, binop(Iop_And32, mkexpr(rotT), mkU32(0x00FF00FF)));
+               nm = "uxtb16";
+               break;
+            case BITS4(0,0,0,0): { // SXTB16
+               IRTemp lo32 = newTemp(Ity_I32);
+               IRTemp hi32 = newTemp(Ity_I32);
+               assign(lo32, binop(Iop_And32, mkexpr(rotT), mkU32(0xFF)));
+               assign(hi32, binop(Iop_Shr32, mkexpr(rotT), mkU8(16)));
+               assign(
+                  dstT,
+                  binop(Iop_Or32,
+                        binop(Iop_And32,
+                              unop(Iop_8Sto32,
+                                   unop(Iop_32to8, mkexpr(lo32))),
+                              mkU32(0xFFFF)),
+                        binop(Iop_Shl32,
+                              unop(Iop_8Sto32,
+                                   unop(Iop_32to8, mkexpr(hi32))),
+                              mkU8(16))
+               ));
+               nm = "uxtb16";
+               break;
+            }
+            default:
+               vassert(0); // guarded by "if" above
+         }
+         putIRegA(rD, mkexpr(dstT), condT, Ijk_Boring);
+         DIP("%s%s r%u, r%u, ROR #%u\n", nm, nCC(INSN_COND), rD, rM, rot);
+         goto decode_success;
+      }
+      /* fall through */
+   }

 
 

-        /* Update Rn if necessary. */
-        switch (summary & 0x0F) {
-           case 2: case 3:
-              putIReg( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
-              break;
-        }
+   /* ------------------- bfi, bfc ------------------- */
+   if (BITS8(0,1,1,1,1,1,0, 0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
+       && BITS4(0, 0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
+      UInt rD  = INSN(15,12);
+      UInt rN  = INSN(3,0);
+      UInt msb = (insn >> 16) & 0x1F; /* 20:16 */
+      UInt lsb = (insn >> 7) & 0x1F;  /* 11:7 */
+      if (rD == 15 || msb < lsb) {
+         /* undecodable; fall through */
+      } else {
+         IRTemp src    = newTemp(Ity_I32);
+         IRTemp olddst = newTemp(Ity_I32);
+         IRTemp newdst = newTemp(Ity_I32);
+         UInt   mask = 1 << (msb - lsb);
+         mask = (mask - 1) + mask;
+         vassert(mask != 0); // guaranteed by "msb < lsb" check above
+         mask <<= lsb;

 
 

-        /* generate the transfer */
-        if (bB == 0) { // word store
-           storeLE( mkexpr(taT), mkexpr(rDt) );
-        } else { // byte store
-           vassert(bB == 1);
-           storeLE( mkexpr(taT), unop(Iop_32to8, mkexpr(rDt)) );
-        }
+         assign(src, rN == 15 ? mkU32(0) : getIRegA(rN));
+         assign(olddst, getIRegA(rD));
+         assign(newdst,
+                binop(Iop_Or32,
+                   binop(Iop_And32,
+                         binop(Iop_Shl32, mkexpr(src), mkU8(lsb)), 
+                         mkU32(mask)),
+                   binop(Iop_And32,
+                         mkexpr(olddst),
+                         mkU32(~mask)))
+               );

 
 

-     } else {
-        /* Load */
-        vassert(bL == 1);
+         putIRegA(rD, mkexpr(newdst), condT, Ijk_Boring);

 
 

-        /* generate the transfer */
-        if (bB == 0) { // word load
-           putIReg( rD, loadLE(Ity_I32, mkexpr(taT)),
-                    IRTemp_INVALID, Ijk_Boring );
-        } else { // byte load
-          vassert(bB == 1);
-           putIReg( rD, unop(Iop_8Uto32, loadLE(Ity_I8, mkexpr(taT))),
-                    IRTemp_INVALID, Ijk_Boring );
-        }
+         if (rN == 15) {
+            DIP("bfc%s r%u, #%u, #%u\n",
+                nCC(INSN_COND), rD, lsb, msb-lsb+1);
+         } else {
+            DIP("bfi%s r%u, r%u, #%u, #%u\n",
+                nCC(INSN_COND), rD, rN, lsb, msb-lsb+1);
+         }
+         goto decode_success;
+      }
+      /* fall through */
+   }

 
 

-        /* Update Rn if necessary. */
-        switch (summary & 0x0F) {
-           case 2: case 3:
-              // should be assured by logic above:
-              if (bL == 1)
-                 vassert(rD != rN); /* since we just wrote rD */
-              putIReg( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
-              break;
-        }
-     }
- 
-     switch (summary & 0x0F) {
-        case 1:  DIP("%sr%s%s r%u, %s\n",
-                     bL == 0 ? "st" : "ld",
-                     bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
-                 break;
-        case 2:  DIP("%sr%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
-                     bL == 0 ? "st" : "ld",
-                     bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
-                 break;
-        case 3:  DIP("%sr%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
-                     bL == 0 ? "st" : "ld",
-                     bB == 0 ? "" : "b", nCC(INSN_COND), rD, dis_buf);
-                 break;
-        default: vassert(0);
-     }
+   /* ------------------- {u,s}bfx ------------------- */
+   if (BITS8(0,1,1,1,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
+       && BITS4(0,1,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
+      UInt rD  = INSN(15,12);
+      UInt rN  = INSN(3,0);
+      UInt wm1 = (insn >> 16) & 0x1F; /* 20:16 */
+      UInt lsb = (insn >> 7) & 0x1F;  /* 11:7 */
+      UInt msb = lsb + wm1;
+      UInt isU = (insn >> 22) & 1;    /* 22:22 */
+      if (rD == 15 || rN == 15 || msb >= 32) {
+         /* undecodable; fall through */
+      } else {
+         IRTemp src  = newTemp(Ity_I32);
+         IRTemp tmp  = newTemp(Ity_I32);
+         IRTemp res  = newTemp(Ity_I32);
+         UInt   mask = ((1 << wm1) - 1) + (1 << wm1);
+         vassert(msb >= 0 && msb <= 31);
+         vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive

 
 

-     /* XXX deal with alignment constraints */
+         assign(src, getIRegA(rN));
+         assign(tmp, binop(Iop_And32,
+                           binop(Iop_Shr32, mkexpr(src), mkU8(lsb)),
+                           mkU32(mask)));
+         assign(res, binop(isU ? Iop_Shr32 : Iop_Sar32,
+                           binop(Iop_Shl32, mkexpr(tmp), mkU8(31-wm1)),
+                           mkU8(31-wm1)));

 
 

-     goto decode_success;
+         putIRegA(rD, mkexpr(res), condT, Ijk_Boring);

 
 

-     /* Complications:
+         DIP("%s%s r%u, r%u, #%u, #%u\n",
+             isU ? "ubfx" : "sbfx",
+             nCC(INSN_COND), rD, rN, lsb, wm1 + 1);
+         goto decode_success;
+      }
+      /* fall through */
+   }

 
 

-        For all loads: if the Amode specifies base register
-        writeback, and the same register is specified for Rd and Rn,
-        the results are UNPREDICTABLE.
+   /* ------------------- smul{b,t}{b,t} ------------- */
+   if (BITS8(0,0,0,1,0,1,1,0) == INSN(27,20)
+       && BITS4(0,0,0,0) == INSN(15,12)
+       && BITS4(1,0,0,0) == (INSN(7,4) & BITS4(1,0,0,1))) {
+      UInt rD  = INSN(19,16);
+      UInt rM  = INSN(11,8);
+      UInt rN  = INSN(3,0);
+      UInt bM = (insn >> 6) & 1;
+      UInt bN = (insn >> 5) & 1;
+      if (bN == 0 && bM == 1) goto decode_failure; //ATC
+      if (bN == 1 && bM == 0) goto decode_failure; //ATC
+      if (bN == 1 && bM == 1) goto decode_failure; //ATC
+      if (rD == 15 || rN == 15 || rM == 15) {
+         /* undecodable; fall through */
+      } else {
+         IRTemp srcL = newTemp(Ity_I32);
+         IRTemp srcR = newTemp(Ity_I32);
+         IRTemp res  = newTemp(Ity_I32);

 
 

-        For all loads and stores: if R15 is written, branch to
-        that address afterwards.
+         /* Extract and sign extend the two 16-bit operands */
+         assign(srcL, binop(Iop_Sar32,
+                            binop(Iop_Shl32, getIRegA(rN),
+                                             mkU8(bN ? 0 : 16)),
+                            mkU8(16)));
+         assign(srcR, binop(Iop_Sar32,
+                            binop(Iop_Shl32, getIRegA(rM),
+                                             mkU8(bM ? 0 : 16)),
+                            mkU8(16)));

 
 

-        STRB: straightforward
-        LDRB: loaded data is zero extended
-        STR:  lowest 2 bits of address are ignored
-        LDR:  if the lowest 2 bits of the address are nonzero
-              then the loaded value is rotated right by 8 * the lowest 2 bits
-     */
-   }
+         assign(res, binop(Iop_Mul32, mkexpr(srcL), mkexpr(srcR)));
+         putIRegA(rD, mkexpr(res), condT, Ijk_Boring);

 
 

-  after_load_store_ubyte_or_word:
+         DIP("smul%c%c%s r%u, r%u, r%u\n",
+             bN ? 't' : 'b', bM ? 't' : 'b', nCC(INSN_COND), rD, rN, rM);
+         goto decode_success;
+      }
+      /* fall through */
+   }

 
 

-   /* --------------------- Load/store (sbyte & hword) -------- */
-   // LDRH LDRSH STRH LDRSB
+   /* --------------------- Load/store doubleword ------------- */
+   // LDRD STRD

    /*                 31   27   23   19 15 11   7    3     # highest bit
                         28   24   20 16 12    8    4    0
    /*                 31   27   23   19 15 11   7    3     # highest bit
                         28   24   20 16 12    8    4    0

-      A5-36   1 | 16  cond 0001 U10L Rn Rd im4h 1SH1 im4l
-      A5-38   1 | 32  cond 0001 U00L Rn Rd 0000 1SH1 Rm
-      A5-40   2 | 16  cond 0001 U11L Rn Rd im4h 1SH1 im4l
-      A5-42   2 | 32  cond 0001 U01L Rn Rd 0000 1SH1 Rm
-      A5-44   3 | 16  cond 0000 U10L Rn Rd im4h 1SH1 im4l
-      A5-46   3 | 32  cond 0000 U00L Rn Rd 0000 1SH1 Rm
+      A5-36   1 | 16  cond 0001 U100 Rn Rd im4h 11S1 im4l
+      A5-38   1 | 32  cond 0001 U000 Rn Rd 0000 11S1 Rm
+      A5-40   2 | 16  cond 0001 U110 Rn Rd im4h 11S1 im4l
+      A5-42   2 | 32  cond 0001 U010 Rn Rd 0000 11S1 Rm
+      A5-44   3 | 16  cond 0000 U100 Rn Rd im4h 11S1 im4l
+      A5-46   3 | 32  cond 0000 U000 Rn Rd 0000 11S1 Rm

    */
    /* case coding:
              1   at-ea               (access at ea)
    */
    /* case coding:
              1   at-ea               (access at ea)


@@ -2251,54 +11281,49 @@ DisResult disInstr_ARM_WRK (
    */
    /* Quickly skip over all of this for hopefully most instructions */
    if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0))
    */
    /* Quickly skip over all of this for hopefully most instructions */
    if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0))

-      goto after_load_store_sbyte_or_hword;
+      goto after_load_store_doubleword;

 
 

-   /* Check the "1SH1" thing. */
-   if ((INSN(7,4) & BITS4(1,0,0,1)) != BITS4(1,0,0,1))
-      goto after_load_store_sbyte_or_hword;
+   /* Check the "11S1" thing. */
+   if ((INSN(7,4) & BITS4(1,1,0,1)) != BITS4(1,1,0,1))
+      goto after_load_store_doubleword;

 
    summary = 0;
 
 
    summary = 0;
 

-   /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,0)) {
+   /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(1,0,0)) {

       summary = 1 | 16;
    }
       summary = 1 | 16;
    }

-   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,0)) {
+   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(0,0,0)) {

       summary = 1 | 32;
    }
       summary = 1 | 32;
    }

-   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,1)) {
+   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(1,1,0)) {

       summary = 2 | 16;
    }
       summary = 2 | 16;
    }

-   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,1)) {
+   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(0,1,0)) {

       summary = 2 | 32;
    }
       summary = 2 | 32;
    }

-   else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(1,0)) {
+   else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(1,0,0)) {

       summary = 3 | 16;
    }
       summary = 3 | 16;
    }

-   else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(0,0)) {
+   else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(0,0,0)) {

       summary = 3 | 32;
       summary = 3 | 32;

+      goto decode_failure; //ATC

    }
    }

-   else goto after_load_store_sbyte_or_hword;
+   else goto after_load_store_doubleword;

 
    { UInt rN   = (insn >> 16) & 0xF; /* 19:16 */
      UInt rD   = (insn >> 12) & 0xF; /* 15:12 */
      UInt rM   = (insn >> 0)  & 0xF; /*  3:0  */
      UInt bU   = (insn >> 23) & 1;   /* 23 U=1 offset+, U=0 offset- */
 
    { UInt rN   = (insn >> 16) & 0xF; /* 19:16 */
      UInt rD   = (insn >> 12) & 0xF; /* 15:12 */
      UInt rM   = (insn >> 0)  & 0xF; /*  3:0  */
      UInt bU   = (insn >> 23) & 1;   /* 23 U=1 offset+, U=0 offset- */

-     UInt bL   = (insn >> 20) & 1;   /* 20 L=1 load, L=0 store */
-     UInt bH   = (insn >> 5) & 1;    /* H=1 halfword, H=0 byte */
-     UInt bS   = (insn >> 6) & 1;    /* S=1 signed, S=0 unsigned */
+     UInt bS   = (insn >> 5) & 1;    /* S=1 store, S=0 load */

      UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */
 
      UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */
 

-     /* Skip combinations that are either meaningless or already
-        handled by main word-or-unsigned-byte load-store
-        instructions. */
-     if (bS == 0 && bH == 0) /* "unsigned byte" */
-        goto after_load_store_sbyte_or_hword;
-     if (bS == 1 && bL == 0) /* "signed store" */
-        goto after_load_store_sbyte_or_hword;
+     /* Require rD to be an even numbered register */
+     if ((rD & 1) != 0)
+        goto after_load_store_doubleword;

 
      /* Require 11:8 == 0 for Rn +/- Rm cases */
      if ((summary & 32) != 0 && (imm8 & 0xF0) != 0)
 
      /* Require 11:8 == 0 for Rn +/- Rm cases */
      if ((summary & 32) != 0 && (imm8 & 0xF0) != 0)

-        goto after_load_store_sbyte_or_hword;
+        goto after_load_store_doubleword;

 
      /* Skip some invalid cases, which would lead to two competing
         updates to the same register, or which are otherwise
 
      /* Skip some invalid cases, which would lead to two competing
         updates to the same register, or which are otherwise


@@ -2307,17 +11332,19 @@ DisResult disInstr_ARM_WRK (
         case 1 | 16:
            break;
         case 1 | 32: 
         case 1 | 16:
            break;
         case 1 | 32: 

-           if (rM == 15) goto after_load_store_sbyte_or_hword;
+           if (rM == 15) goto after_load_store_doubleword;

            break;
         case 2 | 16: case 3 | 16:
            break;
         case 2 | 16: case 3 | 16:

-           if (rN == 15) goto after_load_store_sbyte_or_hword;
-           if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
+           if (rN == 15) goto after_load_store_doubleword;
+           if (bS == 0 && (rN == rD || rN == rD+1))
+              goto after_load_store_doubleword;

            break;
         case 2 | 32: case 3 | 32:
            break;
         case 2 | 32: case 3 | 32:

-           if (rM == 15) goto after_load_store_sbyte_or_hword;
-           if (rN == 15) goto after_load_store_sbyte_or_hword;
-           if (rN == rM) goto after_load_store_sbyte_or_hword;
-           if (bL == 1 && rN == rD) goto after_load_store_sbyte_or_hword;
+           if (rM == 15) goto after_load_store_doubleword;
+           if (rN == 15) goto after_load_store_doubleword;
+           if (rN == rM) goto after_load_store_doubleword;
+           if (bS == 0 && (rN == rD || rN == rD+1))
+              goto after_load_store_doubleword;

            break;
         default:
            vassert(0);
            break;
         default:
            vassert(0);


@@ -2327,7 +11354,7 @@ DisResult disInstr_ARM_WRK (
         likely will generate an exception.  So we have to take a side
         exit at this point if the condition is false. */
      if (condT != IRTemp_INVALID) {
         likely will generate an exception.  So we have to take a side
         exit at this point if the condition is false. */
      if (condT != IRTemp_INVALID) {

-        mk_skip_to_next_if_cond_is_false( condT );
+        mk_skip_over_A32_if_cond_is_false( condT );

         condT = IRTemp_INVALID;
      }
      /* Ok, now we're unconditional.  Do the load or store. */
         condT = IRTemp_INVALID;
      }
      /* Ok, now we're unconditional.  Do the load or store. */


@@ -2349,7 +11376,7 @@ DisResult disInstr_ARM_WRK (
 
      /* get the old Rn value */
      IRTemp rnT = newTemp(Ity_I32);
 
      /* get the old Rn value */
      IRTemp rnT = newTemp(Ity_I32);

-     assign(rnT, getIReg(rN));
+     assign(rnT, getIRegA(rN));

 
      /* decide on the transfer address */
      IRTemp taT = IRTemp_INVALID;
 
      /* decide on the transfer address */
      IRTemp taT = IRTemp_INVALID;


@@ -2359,42 +11386,38 @@ DisResult disInstr_ARM_WRK (
      }
      vassert(taT != IRTemp_INVALID);
 
      }
      vassert(taT != IRTemp_INVALID);
 

-     /* halfword store  H 1  L 0  S 0
-        uhalf load      H 1  L 1  S 0
-        shalf load      H 1  L 1  S 1
-        sbyte load      H 0  L 1  S 1
+     /* XXX deal with alignment constraints */
+     /* XXX: but the A8 doesn't seem to trap for misaligned loads, so,
+        ignore alignment issues for the time being. */
+
+     /* doubleword store  S 1
+        doubleword load   S 0

      */
      HChar* name = NULL;
      */
      HChar* name = NULL;

-     /* generate the transfer */
-     /**/ if (bH == 1 && bL == 0 && bS == 0) { // halfword store
-        storeLE( mkexpr(taT), unop(Iop_32to16, getIReg(rD)) );
-        name = "strh";
-     }
-     else if (bH == 1 && bL == 1 && bS == 0) { // uhalf load
-        putIReg( rD, unop(Iop_16Uto32, loadLE(Ity_I16, mkexpr(taT))),
-                 IRTemp_INVALID, Ijk_Boring );
-        name = "ldrh";
-     }
-     else if (bH == 1 && bL == 1 && bS == 1) { // shalf load
-        putIReg( rD, unop(Iop_16Sto32, loadLE(Ity_I16, mkexpr(taT))),
-                 IRTemp_INVALID, Ijk_Boring );
-        name = "ldrsh";
-     }
-     else if (bH == 0 && bL == 1 && bS == 1) { // sbyte load
-        putIReg( rD, unop(Iop_8Sto32, loadLE(Ity_I8, mkexpr(taT))),
-                 IRTemp_INVALID, Ijk_Boring );
-        name = "ldrsb";
+     /* generate the transfers */
+     if (bS == 1) { // doubleword store
+        storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(0)), getIRegA(rD+0) );
+        storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(4)), getIRegA(rD+1) );
+        name = "strd";
+     } else { // doubleword load
+        putIRegA( rD+0,
+                  loadLE(Ity_I32, binop(Iop_Add32, mkexpr(taT), mkU32(0))),
+                  IRTemp_INVALID, Ijk_Boring );
+        putIRegA( rD+1,
+                  loadLE(Ity_I32, binop(Iop_Add32, mkexpr(taT), mkU32(4))),
+                  IRTemp_INVALID, Ijk_Boring );
+        name = "ldrd";

      }
      }

-     else
-        vassert(0); // should be assured by logic above

 
      /* Update Rn if necessary. */
      switch (summary & 0x0F) {
         case 2: case 3:
            // should be assured by logic above:
 
      /* Update Rn if necessary. */
      switch (summary & 0x0F) {
         case 2: case 3:
            // should be assured by logic above:

-           if (bL == 1)
-              vassert(rD != rN); /* since we just wrote rD */
-           putIReg( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
+           if (bS == 0) {
+              vassert(rD+0 != rN); /* since we just wrote rD+0 */
+              vassert(rD+1 != rN); /* since we just wrote rD+1 */
+           }
+           putIRegA( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );

            break;
      }
 
            break;
      }
 


@@ -2403,2347 +11426,3723 @@ DisResult disInstr_ARM_WRK (
                  break;
         case 2:  DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
                      name, nCC(INSN_COND), rD, dis_buf);
                  break;
         case 2:  DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
                      name, nCC(INSN_COND), rD, dis_buf);

-                 break;
-        case 3:  DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
-                     name, nCC(INSN_COND), rD, dis_buf);
-                 break;
-        default: vassert(0);
-     }
-
-     /* XXX deal with alignment constraints */
-
-     goto decode_success;
-
-     /* Complications:
-
-        For all loads: if the Amode specifies base register
-        writeback, and the same register is specified for Rd and Rn,
-        the results are UNPREDICTABLE.
-
-        For all loads and stores: if R15 is written, branch to
-        that address afterwards.
-
-        Misaligned halfword stores => Unpredictable
-        Misaligned halfword loads  => Unpredictable
-     */
-   }
-
-  after_load_store_sbyte_or_hword:
-
-   /* --------------------- Load/store multiple -------------- */
-   // LD/STMIA LD/STMIB LD/STMDA LD/STMDB
-   // Remarkably complex and difficult to get right
-   // match 27:20 as 100XX0WL
-   if (BITS8(1,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))) {
-      // A5-50 LD/STMIA  cond 1000 10WL Rn RegList
-      // A5-51 LD/STMIB  cond 1001 10WL Rn RegList
-      // A5-53 LD/STMDA  cond 1000 00WL Rn RegList
-      // A5-53 LD/STMDB  cond 1001 00WL Rn RegList
-      //                   28   24   20 16       0
-
-      Int  i, r, m, nRegs;
-
-      UInt bINC    = (insn >> 23) & 1;
-      UInt bBEFORE = (insn >> 24) & 1;
-
-      UInt bL      = (insn >> 20) & 1;  /* load=1, store=0 */
-      UInt bW      = (insn >> 21) & 1;  /* Rn wback=1, no wback=0 */
-      UInt rN      = (insn >> 16) & 0xF;
-      UInt regList = insn & 0xFFFF;
-      /* Skip some invalid cases, which would lead to two competing
-         updates to the same register, or which are otherwise
-         disallowed by the spec.  Note the test above has required
-         that S == 0, since that looks like a kernel-mode only thing.
-         Done by forcing the real pattern, viz 100XXSWL to actually be
-         100XX0WL. */
-      if (rN == 15) goto after_load_store_multiple;
-      // reglist can't be empty
-      if (regList == 0) goto after_load_store_multiple;
-      // if requested to writeback Rn, and this is a load instruction,
-      // then Rn can't appear in RegList, since we'd have two competing
-      // new values for Rn.  We do however accept this case for store
-      // instructions.
-      if (bW == 1 && bL == 1 && ((1 << rN) & regList) > 0)
-         goto after_load_store_multiple;
-
-      /* Now, we can't do a conditional load or store, since that very
-         likely will generate an exception.  So we have to take a side
-         exit at this point if the condition is false. */
-      if (condT != IRTemp_INVALID) {
-         mk_skip_to_next_if_cond_is_false( condT );
-         condT = IRTemp_INVALID;
-      }
-      /* Ok, now we're unconditional.  Do the load or store. */
-
-      /* Get hold of the old Rn value.  We might need to write its
-         value to memory during a store, and if it's also the
-         writeback register then we need to get its value now.  We
-         can't treat it exactly like the other registers we're going
-         to transfer, because for xxMDA and xxMDB writeback forms, the
-         generated IR updates Rn in the guest state before any
-         transfers take place.  We have to do this as per comments
-         below, in order that if Rn is the stack pointer then it
-         always has a value is below or equal to any of the transfer
-         addresses.  Ick. */
-      IRTemp oldRnT = newTemp(Ity_I32);
-      assign(oldRnT, getIReg(rN));
-
-      IRTemp anchorT = newTemp(Ity_I32);
-      /* The old (Addison-Wesley) ARM ARM seems to say that
-         LDMxx/STMxx ignore the bottom two bits of the address.
-         However, Cortex-A8 doesn't seem to care.  Hence: */
-      /* No .. don't force alignment .. */
-      /* assign(anchorT, binop(Iop_And32, mkexpr(oldRnT), mkU32(~3U))); */
-      /* Instead, use the potentially misaligned address directly. */
-      assign(anchorT, mkexpr(oldRnT));
-
-      IROp opADDorSUB = bINC ? Iop_Add32 : Iop_Sub32;
-      // bINC == 1:  xxMIA, xxMIB
-      // bINC == 0:  xxMDA, xxMDB
-
-      // For xxMDA and xxMDB, update Rn first if necessary.  We have
-      // to do this first so that, for the common idiom of the transfers
-      // faulting because we're pushing stuff onto a stack and the stack
-      // is growing down onto allocate-on-fault pages (as Valgrind simulates),
-      // we need to have the SP up-to-date "covering" (pointing below) the
-      // transfer area.  For the same reason, if we are doing xxMIA or xxMIB,
-      // do the transfer first, and then update rN afterwards.
-      nRegs = 0;
-      for (i = 0; i < 16; i++) {
-        if ((regList & (1 << i)) != 0)
-            nRegs++;
-      }
-      if (bW == 1 && !bINC) {
-         putIReg( rN, binop(opADDorSUB, mkexpr(oldRnT), mkU32(4*nRegs)),
-                  IRTemp_INVALID, Ijk_Boring );
-      }
-
-      // Make up a list of the registers to transfer, and their offsets
-      // in memory relative to the anchor.  If the base reg (Rn) is part
-      // of the transfer, then do it last for a load and first for a store.
-      UInt xReg[16], xOff[16];
-      Int  nX = 0;
-      m = 0;
-      for (i = 0; i < 16; i++) {
-         r = bINC ? i : (15-i);
-         if (0 == (regList & (1<<r)))
-            continue;
-         if (bBEFORE)
-            m++;
-         /* paranoia: check we aren't transferring the writeback
-            register during a load. Should be assured by decode-point
-            check above. */
-         if (bW == 1 && bL == 1)
-            vassert(r != rN);
-
-         xOff[nX] = 4 * m;
-         xReg[nX] = r;
-         nX++;
-
-         if (!bBEFORE)
-            m++;
-      }
-      vassert(m == nRegs);
-      vassert(nX == nRegs);
-      vassert(nX <= 16);
-
-      if (bW == 0 && (regList & (1<<rN)) != 0) {
-         /* Non-writeback, and basereg is to be transferred.  Do its
-            transfer last for a load and first for a store.  Requires
-            reordering xOff/xReg. */
-         if (0) {
-            vex_printf("\nREG_LIST_PRE: (rN=%d)\n", rN);
-            for (i = 0; i < nX; i++)
-               vex_printf("reg %d   off %d\n", xReg[i], xOff[i]);
-            vex_printf("\n");
-         }
-
-         vassert(nX > 0);
-         for (i = 0; i < nX; i++) {
-            if (xReg[i] == rN)
-                break;
-         }
-         vassert(i < nX); /* else we didn't find it! */
-         UInt tReg = xReg[i];
-         UInt tOff = xOff[i];
-         if (bL == 1) {
-            /* load; make this transfer happen last */
-            if (i < nX-1) {
-               for (m = i+1; m < nX; m++) {
-                  xReg[m-1] = xReg[m];
-                  xOff[m-1] = xOff[m];
-               }
-               vassert(m == nX);
-               xReg[m-1] = tReg;
-               xOff[m-1] = tOff;
-            }
-         } else {
-            /* store; make this transfer happen first */
-            if (i > 0) {
-               for (m = i-1; m >= 0; m--) {
-                  xReg[m+1] = xReg[m];
-                  xOff[m+1] = xOff[m];
-               }
-               vassert(m == -1);
-               xReg[0] = tReg;
-               xOff[0] = tOff;
-            }
-         }
-
-         if (0) {
-            vex_printf("REG_LIST_POST:\n");
-            for (i = 0; i < nX; i++)
-               vex_printf("reg %d   off %d\n", xReg[i], xOff[i]);
-            vex_printf("\n");
-         }
-      }
-
-      /* Actually generate the transfers */
-      for (i = 0; i < nX; i++) {
-         r = xReg[i];
-         if (bL == 1) {
-            putIReg( r, loadLE(Ity_I32,
-                               binop(opADDorSUB, mkexpr(anchorT),
-                                                 mkU32(xOff[i]))),
-                     IRTemp_INVALID, Ijk_Ret );
-         } else {
-            /* if we're storing Rn, make sure we use the correct
-               value, as per extensive comments above */
-            storeLE( binop(opADDorSUB, mkexpr(anchorT), mkU32(xOff[i])),
-                     r == rN ? mkexpr(oldRnT) : getIReg(r) );
-         }
-      }
-
-      // If we are doing xxMIA or xxMIB,
-      // do the transfer first, and then update rN afterwards.
-      if (bW == 1 && bINC) {
-         putIReg( rN, binop(opADDorSUB, mkexpr(oldRnT), mkU32(4*nRegs)),
-                  IRTemp_INVALID, Ijk_Boring );
-      }
-
-      //if (vex_traceflags & VEX_TRACE_FE) {
-      //}
-      DIP("%sm%c%c%s r%u%s, {0x%04x}\n",
-          bL == 1 ? "ld" : "st", bINC ? 'i' : 'd', bBEFORE ? 'b' : 'a',
-          nCC(INSN_COND),
-          rN, bW ? "!" : "", regList);
-
-      goto decode_success;
-   }
-
-  after_load_store_multiple:
-
-   /* --------------------- Control flow --------------------- */
-   // B, BL (Branch, or Branch-and-Link, to immediate offset)
-   //
-   if (BITS8(1,0,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))) {
-      UInt link   = (insn >> 24) & 1;
-      UInt uimm24 = insn & ((1<<24)-1);
-      Int  simm24 = (Int)uimm24;
-      UInt dst    = guest_R15_curr_instr + 8 + (((simm24 << 8) >> 8) << 2);
-      IRJumpKind jk = link ? Ijk_Call : Ijk_Boring;
-      if (link) {
-         putIReg(14, mkU32(guest_R15_curr_instr + 4), condT, Ijk_Boring);
-      }
-      if (condT == IRTemp_INVALID) {
-         /* unconditional transfer to 'dst'.  See if we can simply
-            continue tracing at the destination. */
-         if (resteerOkFn( callback_opaque, (Addr64)dst )) {
-            /* yes */
-            dres.whatNext   = Dis_ResteerU;
-            dres.continueAt = (Addr64)dst;
-         } else {
-            /* no; terminate the SB at this point. */
-            irsb->next     = mkU32(dst);
-            irsb->jumpkind = jk;
-            dres.whatNext  = Dis_StopHere;
-         }
-         DIP("b%s 0x%x\n", link ? "l" : "", dst);
-      } else {
-         /* conditional transfer to 'dst' */
-         HChar* comment = "";
-
-         /* First see if we can do some speculative chasing into one
-            arm or the other.  Be conservative and only chase if
-            !link, that is, this is a normal conditional branch to a
-            known destination. */
-         if (!link
-             && resteerCisOk
-             && vex_control.guest_chase_cond
-             && dst < guest_R15_curr_instr
-             && resteerOkFn( callback_opaque, (Addr64)(Addr32)dst) ) {
-            /* Speculation: assume this backward branch is taken.  So
-               we need to emit a side-exit to the insn following this
-               one, on the negation of the condition, and continue at
-               the branch target address (dst). */
-            stmt( IRStmt_Exit( unop(Iop_Not1,
-                                    unop(Iop_32to1, mkexpr(condT))),
-                               Ijk_Boring,
-                               IRConst_U32(guest_R15_curr_instr+4) ));
-            dres.whatNext   = Dis_ResteerC;
-            dres.continueAt = (Addr64)(Addr32)dst;
-            comment = "(assumed taken)";
-         }
-         else
-         if (!link
-             && resteerCisOk
-             && vex_control.guest_chase_cond
-             && dst >= guest_R15_curr_instr
-             && resteerOkFn( callback_opaque, 
-                             (Addr64)(Addr32)(guest_R15_curr_instr+4)) ) {
-            /* Speculation: assume this forward branch is not taken.
-               So we need to emit a side-exit to dst (the dest) and
-               continue disassembling at the insn immediately
-               following this one. */
-            stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(condT)),
-                               Ijk_Boring,
-                               IRConst_U32(dst) ));
-            dres.whatNext   = Dis_ResteerC;
-            dres.continueAt = (Addr64)(Addr32)(guest_R15_curr_instr+4);
-            comment = "(assumed not taken)";
-         }
-         else {
-            /* Conservative default translation - end the block at
-               this point. */
-         stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(condT)),
-                            jk, IRConst_U32(dst) ));
-         irsb->next     = mkU32(guest_R15_curr_instr + 4);
-         irsb->jumpkind = jk;
-         dres.whatNext  = Dis_StopHere;
-         }
-         DIP("b%s%s 0x%x %s\n", link ? "l" : "", nCC(INSN_COND),
-             dst, comment);
-      }
-      goto decode_success;
-   }
+                 break;
+        case 3:  DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
+                     name, nCC(INSN_COND), rD, dis_buf);
+                 break;
+        default: vassert(0);
+     }

 
 

-   // BX, BLX (Branch, or Branch-and-Link, to a register)
-   //
-   if (INSN(27,20) == BITS8(0,0,0,1,0,0,1,0)
-       && INSN(19,12) == BITS8(1,1,1,1,1,1,1,1)
-       && (INSN(11,4) == BITS8(1,1,1,1,0,0,1,1)
-           || INSN(11,4) == BITS8(1,1,1,1,0,0,0,1))) {
-      IRExpr* dst;
-      UInt    link = (INSN(11,4) >> 1) & 1;
-      UInt    rM   = INSN(3,0);
-      // we don't decode the case (link && rM == 15), as that's
-      // Unpredictable.
-      if (!(link && rM == 15)) {
-         if (condT != IRTemp_INVALID) {
-            mk_skip_to_next_if_cond_is_false( condT );
-         }
-         // AL after here
-         // pretend no Thumb, hence ~3 instead of ~1
-         dst = binop(Iop_And32, getIReg(rM), mkU32(~3));
-         if (link) {
-            putIReg( 14, mkU32(guest_R15_curr_instr + 4),
-                     IRTemp_INVALID/*because AL*/, Ijk_Boring );
-         }
-         irsb->next     = dst;
-         irsb->jumpkind = link ? Ijk_Call
-                               : (rM == 14 ? Ijk_Ret : Ijk_Boring);
-         dres.whatNext  = Dis_StopHere;
-         if (condT == IRTemp_INVALID) {
-            DIP("b%sx r%u\n", link ? "l" : "", rM);
-         } else {
-            DIP("b%sx%s r%u\n", link ? "l" : "", nCC(INSN_COND), rM);
-         }
-         goto decode_success;
-      }
-      /* else: (link && rM == 15): just fall through */
+     goto decode_success;

    }
 
    }
 

-   /* --------------------- Clz --------------------- */
-   // CLZ
-   if (INSN(27,20) == BITS8(0,0,0,1,0,1,1,0)
-       && INSN(19,16) == BITS4(1,1,1,1)
-       && INSN(11,4) == BITS8(1,1,1,1,0,0,0,1)) {
-      UInt rD = INSN(15,12);
-      UInt rM = INSN(3,0);
-      IRTemp arg = newTemp(Ity_I32);
-      IRTemp res = newTemp(Ity_I32);
-      assign(arg, getIReg(rM));
-      assign(res, IRExpr_Mux0X(
-                     unop(Iop_1Uto8,binop(Iop_CmpEQ32, mkexpr(arg),
-                                                       mkU32(0))),
-                     unop(Iop_Clz32, mkexpr(arg)),
-                     mkU32(32)
-            ));
-      putIReg(rD, mkexpr(res), condT, Ijk_Boring);
-      DIP("clz%s r%u, r%u\n", nCC(INSN_COND), rD, rM);
-      goto decode_success;
-   }
+  after_load_store_doubleword:

 
 

-   /* --------------------- Mul etc --------------------- */
-   // MUL
-   if (BITS8(0,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
-       && INSN(15,12) == BITS4(0,0,0,0)
-       && INSN(7,4) == BITS4(1,0,0,1)) {
-      UInt bitS = (insn >> 20) & 1; /* 20:20 */
-      UInt rD = INSN(19,16);
-      UInt rS = INSN(11,8);
-      UInt rM = INSN(3,0);
-      if (rD == 15 || rM == 15 || rS == 15) {
-         /* Unpredictable; don't decode; fall through */
+   /* ------------------- {s,u}xtab ------------- */
+   if (BITS8(0,1,1,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(0,0,0,0) == (INSN(11,8) & BITS4(0,0,1,1))
+       && BITS4(0,1,1,1) == INSN(7,4)) {
+      UInt rN  = INSN(19,16);
+      UInt rD  = INSN(15,12);
+      UInt rM  = INSN(3,0);
+      UInt rot = (insn >> 10) & 3;
+      UInt isU = INSN(22,22);
+      if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
+         /* undecodable; fall through */

       } else {
       } else {

-         IRTemp argL = newTemp(Ity_I32);
-         IRTemp argR = newTemp(Ity_I32);
+         IRTemp srcL = newTemp(Ity_I32);
+         IRTemp srcR = newTemp(Ity_I32);

          IRTemp res  = newTemp(Ity_I32);
          IRTemp res  = newTemp(Ity_I32);

-         IRTemp oldC = IRTemp_INVALID;
-         IRTemp oldV = IRTemp_INVALID;
-         assign( argL, getIReg(rM));
-         assign( argR, getIReg(rS));
-         assign( res, binop(Iop_Mul32, mkexpr(argL), mkexpr(argR)) );
-         if (bitS) {
-            oldC = newTemp(Ity_I32);
-            assign(oldC, mk_armg_calculate_flag_c());
-            oldV = newTemp(Ity_I32);
-            assign(oldV, mk_armg_calculate_flag_v());
-         }
-         // now update guest state
-         putIReg( rD, mkexpr(res), condT, Ijk_Boring );
-         if (bitS) {
-            IRTemp pair = newTemp(Ity_I32);
-            assign( pair, binop(Iop_Or32,
-                                binop(Iop_Shl32, mkexpr(oldC), mkU8(1)),
-                                mkexpr(oldV)) );
-            setFlags_D1_ND( ARMG_CC_OP_MUL, res, pair, condT );
-         }
-         DIP("mul%c%s r%u, r%u, r%u\n",
-             bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS);
+         assign(srcR, getIRegA(rM));
+         assign(srcL, getIRegA(rN));
+         assign(res,  binop(Iop_Add32,
+                            mkexpr(srcL),
+                            unop(isU ? Iop_8Uto32 : Iop_8Sto32,
+                                 unop(Iop_32to8, 
+                                      genROR32(srcR, 8 * rot)))));
+         putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
+         DIP("%cxtab%s r%u, r%u, r%u, ror #%u\n",
+             isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);

          goto decode_success;
       }
       /* fall through */
    }
 
          goto decode_success;
       }
       /* fall through */
    }
 

-   // MLA, MLS
-   if (BITS8(0,0,0,0,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
-       && INSN(7,4) == BITS4(1,0,0,1)) {
-      UInt bitS  = (insn >> 20) & 1; /* 20:20 */
-      UInt isMLS = (insn >> 22) & 1; /* 22:22 */
-      UInt rD = INSN(19,16);
-      UInt rN = INSN(15,12);
-      UInt rS = INSN(11,8);
-      UInt rM = INSN(3,0);
-      if (bitS == 1 && isMLS == 1) {
-         /* This isn't allowed (MLS that sets flags).  don't decode;
-            fall through */
-      }
-      else
-      if (rD == 15 || rM == 15 || rS == 15 || rN == 15) {
-         /* Unpredictable; don't decode; fall through */
+   /* ------------------- {s,u}xtah ------------- */
+   if (BITS8(0,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
+       && BITS4(0,0,0,0) == (INSN(11,8) & BITS4(0,0,1,1))
+       && BITS4(0,1,1,1) == INSN(7,4)) {
+      UInt rN  = INSN(19,16);
+      UInt rD  = INSN(15,12);
+      UInt rM  = INSN(3,0);
+      UInt rot = (insn >> 10) & 3;
+      UInt isU = INSN(22,22);
+      if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
+         /* undecodable; fall through */

       } else {
       } else {

-         IRTemp argL = newTemp(Ity_I32);
-         IRTemp argR = newTemp(Ity_I32);
-         IRTemp argP = newTemp(Ity_I32);
+         IRTemp srcL = newTemp(Ity_I32);
+         IRTemp srcR = newTemp(Ity_I32);

          IRTemp res  = newTemp(Ity_I32);
          IRTemp res  = newTemp(Ity_I32);

-         IRTemp oldC = IRTemp_INVALID;
-         IRTemp oldV = IRTemp_INVALID;
-         assign( argL, getIReg(rM));
-         assign( argR, getIReg(rS));
-         assign( argP, getIReg(rN));
-         assign( res, binop(isMLS ? Iop_Sub32 : Iop_Add32,
-                            mkexpr(argP),
-                            binop(Iop_Mul32, mkexpr(argL), mkexpr(argR)) ));
-         if (bitS) {
-            vassert(!isMLS); // guaranteed above
-            oldC = newTemp(Ity_I32);
-            assign(oldC, mk_armg_calculate_flag_c());
-            oldV = newTemp(Ity_I32);
-            assign(oldV, mk_armg_calculate_flag_v());
-         }
-         // now update guest state
-         putIReg( rD, mkexpr(res), condT, Ijk_Boring );
-         if (bitS) {
-            IRTemp pair = newTemp(Ity_I32);
-            assign( pair, binop(Iop_Or32,
-                                binop(Iop_Shl32, mkexpr(oldC), mkU8(1)),
-                                mkexpr(oldV)) );
-            setFlags_D1_ND( ARMG_CC_OP_MUL, res, pair, condT );
-         }
-         DIP("ml%c%c%s r%u, r%u, r%u, r%u\n",
-             isMLS ? 's' : 'a', bitS ? 's' : ' ', nCC(INSN_COND), rD, rM, rS, rN);
-         goto decode_success;
-      }
-      /* fall through */
-   }
-
-   // SMULL, UMULL
-   if (BITS8(0,0,0,0,1,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
-       && INSN(7,4) == BITS4(1,0,0,1)) {
-      UInt bitS = (insn >> 20) & 1; /* 20:20 */
-      UInt rDhi = INSN(19,16);
-      UInt rDlo = INSN(15,12);
-      UInt rS   = INSN(11,8);
-      UInt rM   = INSN(3,0);
-      UInt isS  = (INSN(27,20) >> 2) & 1; /* 22:22 */
-      if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo)  {
-         /* Unpredictable; don't decode; fall through */
-      } else {
-         IRTemp argL  = newTemp(Ity_I32);
-         IRTemp argR  = newTemp(Ity_I32);
-         IRTemp res   = newTemp(Ity_I64);
-         IRTemp resHi = newTemp(Ity_I32);
-         IRTemp resLo = newTemp(Ity_I32);
-         IRTemp oldC  = IRTemp_INVALID;
-         IRTemp oldV  = IRTemp_INVALID;
-         IROp   mulOp = isS ? Iop_MullS32 : Iop_MullU32;
-         assign( argL, getIReg(rM));
-         assign( argR, getIReg(rS));
-         assign( res, binop(mulOp, mkexpr(argL), mkexpr(argR)) );
-         assign( resHi, unop(Iop_64HIto32, mkexpr(res)) );
-         assign( resLo, unop(Iop_64to32, mkexpr(res)) );
-         if (bitS) {
-            oldC = newTemp(Ity_I32);
-            assign(oldC, mk_armg_calculate_flag_c());
-            oldV = newTemp(Ity_I32);
-            assign(oldV, mk_armg_calculate_flag_v());
-         }
-         // now update guest state
-         putIReg( rDhi, mkexpr(resHi), condT, Ijk_Boring );
-         putIReg( rDlo, mkexpr(resLo), condT, Ijk_Boring );
-         if (bitS) {
-            IRTemp pair = newTemp(Ity_I32);
-            assign( pair, binop(Iop_Or32,
-                                binop(Iop_Shl32, mkexpr(oldC), mkU8(1)),
-                                mkexpr(oldV)) );
-            setFlags_D1_D2_ND( ARMG_CC_OP_MULL, resLo, resHi, pair, condT );
-         }
-         DIP("%cmull%c%s r%u, r%u, r%u, r%u\n",
-             isS ? 's' : 'u', bitS ? 's' : ' ',
-             nCC(INSN_COND), rDlo, rDhi, rM, rS);
-         goto decode_success;
-      }
-      /* fall through */
-   }
-
-   // SMLAL, UMLAL
-   if (BITS8(0,0,0,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
-       && INSN(7,4) == BITS4(1,0,0,1)) {
-      UInt bitS = (insn >> 20) & 1; /* 20:20 */
-      UInt rDhi = INSN(19,16);
-      UInt rDlo = INSN(15,12);
-      UInt rS   = INSN(11,8);
-      UInt rM   = INSN(3,0);
-      UInt isS  = (INSN(27,20) >> 2) & 1; /* 22:22 */
-      if (rDhi == 15 || rDlo == 15 || rM == 15 || rS == 15 || rDhi == rDlo)  {
-         /* Unpredictable; don't decode; fall through */
-      } else {
-         IRTemp argL  = newTemp(Ity_I32);
-         IRTemp argR  = newTemp(Ity_I32);
-         IRTemp old   = newTemp(Ity_I64);
-         IRTemp res   = newTemp(Ity_I64);
-         IRTemp resHi = newTemp(Ity_I32);
-         IRTemp resLo = newTemp(Ity_I32);
-         IRTemp oldC  = IRTemp_INVALID;
-         IRTemp oldV  = IRTemp_INVALID;
-         IROp   mulOp = isS ? Iop_MullS32 : Iop_MullU32;
-         assign( argL, getIReg(rM));
-         assign( argR, getIReg(rS));
-         assign( old, binop(Iop_32HLto64, getIReg(rDhi), getIReg(rDlo)) );
-         assign( res, binop(Iop_Add64,
-                            mkexpr(old),
-                            binop(mulOp, mkexpr(argL), mkexpr(argR))) );
-         assign( resHi, unop(Iop_64HIto32, mkexpr(res)) );
-         assign( resLo, unop(Iop_64to32, mkexpr(res)) );
-         if (bitS) {
-            oldC = newTemp(Ity_I32);
-            assign(oldC, mk_armg_calculate_flag_c());
-            oldV = newTemp(Ity_I32);
-            assign(oldV, mk_armg_calculate_flag_v());
-         }
-         // now update guest state
-         putIReg( rDhi, mkexpr(resHi), condT, Ijk_Boring );
-         putIReg( rDlo, mkexpr(resLo), condT, Ijk_Boring );
-         if (bitS) {
-            IRTemp pair = newTemp(Ity_I32);
-            assign( pair, binop(Iop_Or32,
-                                binop(Iop_Shl32, mkexpr(oldC), mkU8(1)),
-                                mkexpr(oldV)) );
-            setFlags_D1_D2_ND( ARMG_CC_OP_MULL, resLo, resHi, pair, condT );
-         }
-         DIP("%cmlal%c%s r%u, r%u, r%u, r%u\n",
-             isS ? 's' : 'u', bitS ? 's' : ' ', nCC(INSN_COND),
-             rDlo, rDhi, rM, rS);
+         assign(srcR, getIRegA(rM));
+         assign(srcL, getIRegA(rN));
+         assign(res,  binop(Iop_Add32,
+                            mkexpr(srcL),
+                            unop(isU ? Iop_16Uto32 : Iop_16Sto32,
+                                 unop(Iop_32to16, 
+                                      genROR32(srcR, 8 * rot)))));
+         putIRegA(rD, mkexpr(res), condT, Ijk_Boring);
+
+         DIP("%cxtah%s r%u, r%u, r%u, ror #%u\n",
+             isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);

          goto decode_success;
       }
       /* fall through */
    }
 
          goto decode_success;
       }
       /* fall through */
    }
 

-   /* --------------------- Msr etc --------------------- */
+   /* ----------------------------------------------------------- */
+   /* -- ARMv7 instructions                                    -- */
+   /* ----------------------------------------------------------- */

 
 

-   // MSR (immediate form, flags only)
-   if (BITS8(0,0,1,1,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && INSN(15,12) == BITS4(1,1,1,1)) {
-      UInt bitR = (insn >> 22) & 1;
-      if (bitR == 0 && INSN(19,16) == BITS4(1,0,0,0)) {
-         UInt   imm = (INSN(11,0) >> 0) & 0xFF;
-         UInt   rot = 2 * ((INSN(11,0) >> 8) & 0xF);
-         IRTemp immT = newTemp(Ity_I32);
-         vassert(rot <= 30);
-         imm = ROR32(imm, rot);
-         imm &= 0xFF000000;
-         imm &= (ARMG_CC_MASK_N | ARMG_CC_MASK_Z 
-                 | ARMG_CC_MASK_V | ARMG_CC_MASK_C);
-         assign( immT, mkU32(imm & 0xF0000000) );
-         setFlags_D1(ARMG_CC_OP_COPY, immT, condT);
-         DIP("msr%s cpsr_f, #0x%08x\n", nCC(INSN_COND), imm);
+   /* -------------- read CP15 TPIDRURO register ------------- */
+   /* mrc     p15, 0, r0, c13, c0, 3  up to
+      mrc     p15, 0, r14, c13, c0, 3
+   */
+   /* I don't know whether this is really v7-only.  But anyway, we
+      have to support it since arm-linux uses TPIDRURO as a thread
+      state register. */
+   if (0x0E1D0F70 == (insn & 0x0FFF0FFF)) {
+      UInt rD = INSN(15,12);
+      if (rD <= 14) {
+         /* skip r15, that's too stupid to handle */
+         putIRegA(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32),
+                      condT, Ijk_Boring);
+         DIP("mrc%s p15,0, r%u, c13, c0, 3\n", nCC(INSN_COND), rD);

          goto decode_success;
       }
       /* fall through */
    }
 
          goto decode_success;
       }
       /* fall through */
    }
 

-   // MRS
-   if (BITS8(0,0,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && INSN(19,16) == BITS4(1,1,1,1)
-       && INSN(11,0) == 0) {
-      UInt bitR = (insn >> 22) & 1;
-      UInt rD   = INSN(15,12);
-      if (bitR == 0 && rD != 15) {
-         IRTemp res = newTemp(Ity_I32);
-         assign( res, mk_armg_calculate_flags_nzcv() );
-         putIReg( rD, mkexpr(res), condT, Ijk_Boring );
-         DIP("mrs%s r%u, cpsr\n", nCC(INSN_COND), rD);
+   /* Handle various kinds of barriers.  This is rather indiscriminate
+      in the sense that they are all turned into an IR Fence, which
+      means we don't know which they are, so the back end has to
+      re-emit them all when it comes acrosss an IR Fence.
+   */
+   switch (insn) {
+      case 0xEE070F9A: /* v6 */
+         /* mcr 15, 0, r0, c7, c10, 4 (v6) equiv to DSB (v7).  Data
+            Synch Barrier -- ensures completion of memory accesses. */
+         stmt( IRStmt_MBE(Imbe_Fence) );
+         DIP("mcr 15, 0, r0, c7, c10, 4 (data synch barrier)\n");

          goto decode_success;
          goto decode_success;

-      }
-      /* fall through */
+      case 0xEE070FBA: /* v6 */
+         /* mcr 15, 0, r0, c7, c10, 5 (v6) equiv to DMB (v7).  Data
+            Memory Barrier -- ensures ordering of memory accesses. */
+         stmt( IRStmt_MBE(Imbe_Fence) );
+         DIP("mcr 15, 0, r0, c7, c10, 5 (data memory barrier)\n");
+         goto decode_success;
+      case 0xEE070F95: /* v6 */
+         /* mcr 15, 0, r0, c7, c5, 4 (v6) equiv to ISB (v7).
+            Instruction Synchronisation Barrier (or Flush Prefetch
+            Buffer) -- a pipe flush, I think.  I suspect we could
+            ignore those, but to be on the safe side emit a fence
+            anyway. */
+         stmt( IRStmt_MBE(Imbe_Fence) );
+         DIP("mcr 15, 0, r0, c7, c5, 4 (insn synch barrier)\n");
+         goto decode_success;
+      default:
+         break;

    }
 
    }
 

-   /* --------------------- Svc --------------------- */
-   if (BITS8(1,1,1,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))) {
-      UInt imm24 = (insn >> 0) & 0xFFFFFF;
-      if (imm24 == 0) {
-         /* A syscall.  We can't do this conditionally, hence: */
-         if (condT != IRTemp_INVALID) {
-            mk_skip_to_next_if_cond_is_false( condT );
-         }
-         // AL after here
-         irsb->next     = mkU32( guest_R15_curr_instr + 4 );
-         irsb->jumpkind = Ijk_Sys_syscall;
-         dres.whatNext  = Dis_StopHere;
-         DIP("svc%s #0x%08x\n", nCC(INSN_COND), imm24);
+   /* ----------------------------------------------------------- */
+   /* -- VFP (CP 10, CP 11) instructions (in ARM mode)         -- */
+   /* ----------------------------------------------------------- */
+
+   if (INSN_COND != ARMCondNV) {
+      Bool ok_vfp = decode_CP10_CP11_instruction (
+                       &dres, INSN(27,0), condT, INSN_COND,
+                       False/*!isT*/
+                    );
+      if (ok_vfp)

          goto decode_success;
          goto decode_success;

-      }
-      /* fall through */

    }
 
    }
 

-   /* ------------------------ swp ------------------------ */
+   /* ----------------------------------------------------------- */
+   /* -- NEON instructions (in ARM mode)                       -- */
+   /* ----------------------------------------------------------- */

 
 

-   // SWP, SWPB
-   if (BITS8(0,0,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(0,0,0,0) == INSN(11,8)
-       && BITS4(1,0,0,1) == INSN(7,4)) {
-      UInt   rN   = INSN(19,16);
-      UInt   rD   = INSN(15,12);
-      UInt   rM   = INSN(3,0);
-      IRTemp tRn  = newTemp(Ity_I32);
-      IRTemp tNew = newTemp(Ity_I32);
-      IRTemp tOld = IRTemp_INVALID;
-      IRTemp tSC1 = newTemp(Ity_I1);
-      UInt   isB  = (insn >> 22) & 1;
+   /* These are all in NV space, and so are taken care of (far) above,
+      by a call from this function to decode_NV_instruction(). */

 
 

-      if (rD == 15 || rN == 15 || rM == 15 || rN == rM || rN == rD) {
-         /* undecodable; fall through */
+   /* ----------------------------------------------------------- */
+   /* -- Undecodable                                           -- */
+   /* ----------------------------------------------------------- */
+
+   goto decode_failure;
+   /*NOTREACHED*/
+
+  decode_failure:
+   /* All decode failures end up here. */
+   vex_printf("disInstr(arm): unhandled instruction: "
+              "0x%x\n", insn);
+   vex_printf("                 cond=%d(0x%x) 27:20=%u(0x%02x) "
+                                "4:4=%d "
+                                "3:0=%u(0x%x)\n",
+              (Int)INSN_COND, (UInt)INSN_COND,
+              (Int)INSN(27,20), (UInt)INSN(27,20),
+              (Int)INSN(4,4),
+              (Int)INSN(3,0), (UInt)INSN(3,0) );
+
+   /* Tell the dispatcher that this insn cannot be decoded, and so has
+      not been executed, and (is currently) the next to be executed.
+      R15 should be up-to-date since it made so at the start of each
+      insn, but nevertheless be paranoid and update it again right
+      now. */
+   vassert(0 == (guest_R15_curr_instr_notENC & 3));
+   llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC) );
+   irsb->next     = mkU32(guest_R15_curr_instr_notENC);
+   irsb->jumpkind = Ijk_NoDecode;
+   dres.whatNext  = Dis_StopHere;
+   dres.len       = 0;
+   return dres;
+
+  decode_success:
+   /* All decode successes end up here. */
+   DIP("\n");
+
+   vassert(dres.len == 4 || dres.len == 20);
+
+   /* Now then.  Do we have an implicit jump to r15 to deal with? */
+   if (r15written) {
+      /* If we get jump to deal with, we assume that there's been no
+         other competing branch stuff previously generated for this
+         insn.  That's reasonable, in the sense that the ARM insn set
+         appears to declare as "Unpredictable" any instruction which
+         generates more than one possible new value for r15.  Hence
+         just assert.  The decoders themselves should check against
+         all such instructions which are thusly Unpredictable, and
+         decline to decode them.  Hence we should never get here if we
+         have competing new values for r15, and hence it is safe to
+         assert here. */
+      vassert(dres.whatNext == Dis_Continue);
+      vassert(irsb->next == NULL);
+      vassert(irsb->jumpkind = Ijk_Boring);
+      /* If r15 is unconditionally written, terminate the block by
+         jumping to it.  If it's conditionally written, still
+         terminate the block (a shame, but we can't do side exits to
+         arbitrary destinations), but first jump to the next
+         instruction if the condition doesn't hold. */
+      /* We can't use getIReg(15) to get the destination, since that
+         will produce r15+8, which isn't what we want.  Must use
+         llGetIReg(15) instead. */
+      if (r15guard == IRTemp_INVALID) {
+         /* unconditional */

       } else {
       } else {

-         /* make unconditional */
-         if (condT != IRTemp_INVALID) {
-            mk_skip_to_next_if_cond_is_false( condT );
-            condT = IRTemp_INVALID;
-         }
-         /* Ok, now we're unconditional.  Generate a LL-SC loop. */
-         assign(tRn, getIReg(rN));
-         assign(tNew, getIReg(rM));
-         if (isB) {
-            /* swpb */
-            tOld = newTemp(Ity_I8);
-            stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn),
-                              NULL/*=>isLL*/) );
-            stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn),
-                              unop(Iop_32to8, mkexpr(tNew))) );
-         } else {
-            /* swp */
-            tOld = newTemp(Ity_I32);
-            stmt( IRStmt_LLSC(Iend_LE, tOld, mkexpr(tRn),
-                              NULL/*=>isLL*/) );
-            stmt( IRStmt_LLSC(Iend_LE, tSC1, mkexpr(tRn),
-                              mkexpr(tNew)) );
+         /* conditional */
+         stmt( IRStmt_Exit(
+                  unop(Iop_32to1,
+                       binop(Iop_Xor32,
+                             mkexpr(r15guard), mkU32(1))),
+                  r15kind,
+                  IRConst_U32(guest_R15_curr_instr_notENC + 4)
+         ));
+      }
+      irsb->next     = llGetIReg(15);
+      irsb->jumpkind = r15kind;
+      dres.whatNext  = Dis_StopHere;
+   }
+
+   return dres;
+
+#  undef INSN_COND
+#  undef INSN
+}
+
+
+/*------------------------------------------------------------*/
+/*--- Disassemble a single Thumb2 instruction              ---*/
+/*------------------------------------------------------------*/
+
+/* NB: in Thumb mode we do fetches of regs with getIRegT, which
+   automagically adds 4 to fetches of r15.  However, writes to regs
+   are done with putIRegT, which disallows writes to r15.  Hence any
+   r15 writes and associated jumps have to be done "by hand". */
+
+/* Disassemble a single Thumb instruction into IR.  The instruction is
+   located in host memory at guest_instr, and has (decoded) guest IP
+   of guest_R15_curr_instr_notENC, which will have been set before the
+   call here. */
+
+static   
+DisResult disInstr_THUMB_WRK (
+             Bool         put_IP,
+             Bool         (*resteerOkFn) ( /*opaque*/void*, Addr64 ),
+             Bool         resteerCisOk,
+             void*        callback_opaque,
+             UChar*       guest_instr,
+             VexArchInfo* archinfo,
+             VexAbiInfo*  abiinfo
+          )
+{
+   /* A macro to fish bits out of insn0.  There's also INSN1, to fish
+      bits out of insn1, but that's defined only after the end of the
+      16-bit insn decoder, so as to stop it mistakenly being used
+      therein. */
+#  define INSN0(_bMax,_bMin)  SLICE_UInt(((UInt)insn0), (_bMax), (_bMin))
+
+   DisResult dres;
+   UShort    insn0; /* first 16 bits of the insn */
+   //Bool      allow_VFP = False;
+   //UInt      hwcaps = archinfo->hwcaps;
+   HChar     dis_buf[128];  // big enough to hold LDMIA etc text
+
+   /* What insn variants are we supporting today? */
+   //allow_VFP  = (0 != (hwcaps & VEX_HWCAPS_ARM_VFP));
+   // etc etc
+
+   /* Set result defaults. */
+   dres.whatNext   = Dis_Continue;
+   dres.len        = 2;
+   dres.continueAt = 0;
+
+   /* Set default actions for post-insn handling of writes to r15, if
+      required. */
+   r15written = False;
+   r15guard   = IRTemp_INVALID; /* unconditional */
+   r15kind    = Ijk_Boring;
+
+   /* Insns could be 2 or 4 bytes long.  Just get the first 16 bits at
+      this point.  If we need the second 16, get them later.  We can't
+      get them both out immediately because it risks a fault (very
+      unlikely, but ..) if the second 16 bits aren't actually
+      necessary. */
+   insn0 = getUShortLittleEndianly( guest_instr );
+
+   if (0) vex_printf("insn: 0x%x\n", insn0);
+
+   DIP("\t(thumb) 0x%x:  ", (UInt)guest_R15_curr_instr_notENC);
+
+   /* We may be asked to update the guest R15 before going further. */
+   vassert(0 == (guest_R15_curr_instr_notENC & 1));
+   if (put_IP) {
+      llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC | 1) );
+   }
+
+   /* ----------------------------------------------------------- */
+   /* Spot "Special" instructions (see comment at top of file). */
+   {
+      UChar* code = (UChar*)guest_instr;
+      /* Spot the 16-byte preamble: 
+
+         ea4f 0cfc  mov.w   ip, ip, ror #3
+         ea4f 3c7c  mov.w   ip, ip, ror #13
+         ea4f 7c7c  mov.w   ip, ip, ror #29
+         ea4f 4cfc  mov.w   ip, ip, ror #19
+      */
+      UInt word1 = 0x0CFCEA4F;
+      UInt word2 = 0x3C7CEA4F;
+      UInt word3 = 0x7C7CEA4F;
+      UInt word4 = 0x4CFCEA4F;
+      if (getUIntLittleEndianly(code+ 0) == word1 &&
+          getUIntLittleEndianly(code+ 4) == word2 &&
+          getUIntLittleEndianly(code+ 8) == word3 &&
+          getUIntLittleEndianly(code+12) == word4) {
+         /* Got a "Special" instruction preamble.  Which one is it? */
+         // 0x 0A 0A EA 4A
+         if (getUIntLittleEndianly(code+16) == 0x0A0AEA4A
+                                               /* orr.w r10,r10,r10 */) {
+            /* R3 = client_request ( R4 ) */
+            DIP("r3 = client_request ( %%r4 )\n");
+            irsb->next     = mkU32( (guest_R15_curr_instr_notENC + 20) | 1 );
+            irsb->jumpkind = Ijk_ClientReq;
+            dres.whatNext  = Dis_StopHere;
+            goto decode_success;

          }
          }

-         stmt( IRStmt_Exit(unop(Iop_Not1, mkexpr(tSC1)),
-                           /*Ijk_NoRedir*/Ijk_Boring,
-                           IRConst_U32(guest_R15_curr_instr)) );
-         putIReg(rD, isB ? unop(Iop_8Uto32, mkexpr(tOld)) : mkexpr(tOld),
-                     IRTemp_INVALID, Ijk_Boring);
-         DIP("swp%s%s r%u, r%u, [r%u]\n",
-             isB ? "b" : "", nCC(INSN_COND), rD, rM, rN);
-         goto decode_success;
+         else
+         // 0x 0B 0B EA 4B
+         if (getUIntLittleEndianly(code+16) == 0x0B0BEA4B
+                                               /* orr r11,r11,r11 */) {
+            /* R3 = guest_NRADDR */
+            DIP("r3 = guest_NRADDR\n");
+            dres.len = 20;
+            llPutIReg(3, IRExpr_Get( OFFB_NRADDR, Ity_I32 ));
+            goto decode_success;
+         }
+         else
+         // 0x 0C 0C EA 4C
+         if (getUIntLittleEndianly(code+16) == 0x0C0CEA4C
+                                               /* orr r12,r12,r12 */) {
+            /*  branch-and-link-to-noredir R4 */
+            DIP("branch-and-link-to-noredir r4\n");
+            llPutIReg(14, mkU32( (guest_R15_curr_instr_notENC + 20) | 1 ));
+            irsb->next     = getIRegT(4);
+            irsb->jumpkind = Ijk_NoRedir;
+            dres.whatNext  = Dis_StopHere;
+            goto decode_success;
+         }
+         /* We don't know what it is.  Set insn0 so decode_failure
+            can print the insn following the Special-insn preamble. */
+         insn0 = getUShortLittleEndianly(code+16);
+         goto decode_failure;
+         /*NOTREACHED*/

       }
       }

-      /* fall through */
+

    }
 
    /* ----------------------------------------------------------- */
    }
 
    /* ----------------------------------------------------------- */

-   /* -- VFP instructions -- double precision (mostly)         -- */
-   /* ----------------------------------------------------------- */
-
-   /* --------------------- fldmx, fstmx --------------------- */
-   /*
-                                 31   27   23   19 15 11   7   0
-                                         P U WL
-      C4-100, C5-26  1  FSTMX    cond 1100 1000 Rn Dd 1011 offset
-      C4-100, C5-28  2  FSTMIAX  cond 1100 1010 Rn Dd 1011 offset
-      C4-100, C5-30  3  FSTMDBX  cond 1101 0010 Rn Dd 1011 offset
-
-      C4-42, C5-26   1  FLDMX    cond 1100 1001 Rn Dd 1011 offset
-      C4-42, C5-28   2  FLDMIAX  cond 1100 1011 Rn Dd 1011 offset
-      C4-42, C5-30   3  FLDMDBX  cond 1101 0011 Rn Dd 1011 offset
-
-      Regs transferred: Dd .. D(d + (offset-3)/2)
-      offset must be odd, must not imply a reg > 15
-      IA/DB: Rn is changed by (4 + 8 x # regs transferred)

 
 

-      case coding:
-         1  at-Rn   (access at Rn)
-         2  ia-Rn   (access at Rn, then Rn += 4+8n)
-         3  db-Rn   (Rn -= 4+8n,   then access at Rn)
+   /* Main Thumb instruction decoder starts here.  It's a series of
+      switches which examine ever longer bit sequences at the MSB of
+      the instruction word, first for 16-bit insns, then for 32-bit
+      insns. */
+
+   /* --- BEGIN optimisation --- */
+   /* This is a crucial optimisation for the ITState boilerplate that
+      follows.  Examine the 9 halfwords preceding this instruction,
+      and if we are absolutely sure that none of them constitute an
+      'it' instruction, then we can be sure that this instruction is
+      not under the control of any 'it' instruction, and so
+      guest_ITSTATE must be zero.  So write zero into ITSTATE right
+      now, so that iropt can fold out almost all of the resulting
+      junk.
+
+      If we aren't sure, we can always safely skip this step.  So be a
+      bit conservative about it: only poke around in the same page as
+      this instruction, lest we get a fault from the previous page
+      that would not otherwise have happened.  The saving grace is
+      that such skipping is pretty rare -- it only happens,
+      statistically, 18/4096ths of the time, so is judged unlikely to
+      be a performance problems.
+
+      FIXME: do better.  Take into account the number of insns covered
+      by any IT insns we find, to rule out cases where an IT clearly
+      cannot cover this instruction.  This would improve behaviour for
+      branch targets immediately following an IT-guarded group that is
+      not of full length.  Eg, (and completely ignoring issues of 16-
+      vs 32-bit insn length):
+
+             ite cond
+             insn1
+             insn2
+      label: insn3
+             insn4
+
+      The 'it' only conditionalises insn1 and insn2.  However, the
+      current analysis is conservative and considers insn3 and insn4
+      also possibly guarded.  Hence if 'label:' is the start of a hot
+      loop we will get a big performance hit.

    */
    */

-   if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))
-       && INSN(11,8) == BITS4(1,0,1,1)) {
-      UInt bP     = (insn >> 24) & 1;
-      UInt bU     = (insn >> 23) & 1;
-      UInt bW     = (insn >> 21) & 1;
-      UInt bL     = (insn >> 20) & 1;
-      UInt offset = (insn >> 0) & 0xFF;
-      UInt rN     = INSN(19,16);
-      UInt dD     = INSN(15,12);
-      UInt nRegs  = (offset - 1) / 2;
-      Int  i;
-
-      /**/ if (bP == 0 && bU == 1 && bW == 0) {
-         vassert(0); //ATC
-         summary = 1;
-      }
-      else if (bP == 0 && bU == 1 && bW == 1) {
-         summary = 2;
+   {
+      /* Summary result of this analysis: False == safe but
+         suboptimal. */
+      Bool forceZ = False;
+
+      UInt pc = guest_R15_curr_instr_notENC;
+      vassert(0 == (pc & 1));
+
+      UInt pageoff = pc & 0xFFF;
+      if (pageoff >= 18) {
+         /* It's safe to poke about in the 9 halfwords preceding this
+            insn.  So, have a look at them. */
+         forceZ = True; /* assume no 'it' insn found, till we do */
+
+         UShort* hwp = (UShort*)(HWord)pc;
+         Int i;
+         for (i = -1; i >= -9; i--) {
+            /* We're in the same page.  (True, but commented out due
+               to expense.) */
+            /*
+            vassert( ( ((UInt)(&hwp[i])) & 0xFFFFF000 )
+                      == ( pc & 0xFFFFF000 ) );
+            */
+            /* All valid IT instructions must have the form 0xBFxy,
+               where x can be anything, but y must be nonzero. */
+            if ((hwp[i] & 0xFF00) == 0xBF00 && (hwp[i] & 0xF) != 0) {
+               /* might be an 'it' insn.  Play safe. */
+               forceZ = False;
+               break;
+            }
+         }

       }
       }

-      else if (bP == 1 && bU == 0 && bW == 1) {
-         summary = 3;
+      /* So, did we get lucky? */
+      if (forceZ) {
+         IRTemp t = newTemp(Ity_I32);
+         assign(t, mkU32(0));
+         put_ITSTATE(t);

       }
       }

-      else goto after_vfp_fldmx_fstmx;
+   }
+   /* --- END optimisation --- */

 
 

-      /* no writebacks to r15 allowed */
-      if (rN == 15 && (summary == 2 || summary == 3))
-         goto after_vfp_fldmx_fstmx;
+   /* Generate the guarding condition for this insn, by examining
+      ITSTATE.  Assign it to condT.  Also, generate new
+      values for ITSTATE ready for stuffing back into the
+      guest state, but don't actually do the Put yet, since it will
+      need to stuffed back in only after the instruction gets to a
+      point where it is sure to complete.  Mostly we let the code at
+      decode_success handle this, but in cases where the insn contains
+      a side exit, we have to update them before the exit. */

 
 

-      /* offset must be odd, and specify at least one register */
-      if (0 == (offset & 1) || offset < 3)
-         goto after_vfp_fldmx_fstmx;
+   IRTemp old_itstate = get_ITSTATE();

 
 

-      /* can't transfer regs after D15 */
-      if (dD + nRegs - 1 >= 16)
-         goto after_vfp_fldmx_fstmx;
+   IRTemp new_itstate = newTemp(Ity_I32);
+   assign(new_itstate, binop(Iop_Shr32, mkexpr(old_itstate), mkU8(8)));

 
 

-      /* Now, we can't do a conditional load or store, since that very
-         likely will generate an exception.  So we have to take a side
-         exit at this point if the condition is false. */
-      if (condT != IRTemp_INVALID) {
-         mk_skip_to_next_if_cond_is_false( condT );
-         condT = IRTemp_INVALID;
-      }
-      /* Ok, now we're unconditional.  Do the load or store. */
+   put_ITSTATE(new_itstate);

 
 

-      /* get the old Rn value */
-      IRTemp rnT = newTemp(Ity_I32);
-      assign(rnT, getIReg(rN));
+   /* Same strategy as for ARM insns: generate a condition temporary
+      at this point  (or IRTemp_INVALID, meaning
+      unconditional).  We leave it to lower-level instruction decoders
+      to decide whether they can generate straight-line code, or
+      whether they must generate a side exit before the instruction.
+      condT :: Ity_I32 and is always either zero or one. */
+   IRTemp condT1 = newTemp(Ity_I32);
+   assign(condT1,
+          mk_armg_calculate_condition_dyn(
+             binop(Iop_Xor32,
+                   binop(Iop_And32, mkexpr(old_itstate), mkU32(0xF0)),
+                   mkU32(0xE0))
+          )
+   );
+
+   /* This is a bit complex, but needed to make Memcheck understand
+      that, if the condition in old_itstate[7:4] denotes AL (that is,
+      if this instruction is to be executed unconditionally), then
+      condT does not depend on the results of calling the helper.
+
+      We test explicitly for old_itstate[7:4] == AL ^ 0xE, and in that
+      case set condT directly to 1.  Else we use the results of the
+      helper.  Since old_itstate is always defined and because
+      Memcheck does lazy V-bit propagation through Mux0X, this will
+      cause condT to always be a defined 1 if the condition is 'AL'.
+      From an execution semantics point of view this is irrelevant
+      since we're merely duplicating part of the behaviour of the
+      helper.  But it makes it clear to Memcheck, in this case, that
+      condT does not in fact depend on the contents of the condition
+      code thunk.  Without it, we get quite a lot of false errors.
+
+      So, just to clarify: from a straight semantics point of view, we
+      can simply do "assign(condT, mkexpr(condT1))", and the simulator
+      still runs fine.  It's just that we get loads of false errors
+      from Memcheck. */
+   IRTemp condT = newTemp(Ity_I32);
+   assign(condT, IRExpr_Mux0X(
+                    unop(Iop_32to8, binop(Iop_And32,
+                                          mkexpr(old_itstate),
+                                          mkU32(0xF0))),
+                    mkU32(1),
+                    mkexpr(condT1)
+         ));

 
 

-      /* make a new value for Rn, post-insn */
-      IRTemp rnTnew = IRTemp_INVALID;
-      if (summary == 2 || summary == 3) {
-         rnTnew = newTemp(Ity_I32);
-         assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32,
-                              mkexpr(rnT),
-                              mkU32(4 + 8 * nRegs)));
-      }
+   /* Something we don't have in ARM: generate a 0 or 1 value
+      indicating whether or not we are in an IT block (NB: 0 = in IT
+      block, 1 = not in IT block).  This is used to gate condition
+      code updates in 16-bit Thumb instructions. */
+   IRTemp notInITt = newTemp(Ity_I32);
+   assign(notInITt,
+          binop(Iop_Xor32,
+                binop(Iop_And32, mkexpr(old_itstate), mkU32(1)),
+                mkU32(1)));
+
+   /* Compute 'condT && notInITt' -- that is, the instruction is going
+      to execute, and we're not in an IT block.  This is the gating
+      condition for updating condition codes in 16-bit Thumb
+      instructions, except for CMP, CMN and TST. */
+   IRTemp cond_AND_notInIT_T = newTemp(Ity_I32);
+   assign(cond_AND_notInIT_T,
+          binop(Iop_And32, mkexpr(notInITt), mkexpr(condT)));
+
+   /* At this point:
+      * ITSTATE has been updated
+      * condT holds the guarding condition for this instruction (0 or 1),
+      * notInITt is 1 if we're in "normal" code, 0 if in an IT block
+      * cond_AND_notInIT_T is the AND of the above two.
+
+      If the instruction proper can't trap, then there's nothing else
+      to do w.r.t. ITSTATE -- just go and and generate IR for the
+      insn, taking into account the guarding condition.
+
+      If, however, the instruction might trap, then we must back up
+      ITSTATE to the old value, and re-update it after the potentially
+      trapping IR section.  A trap can happen either via a memory
+      reference or because we need to throw SIGILL.
+
+      If an instruction has a side exit, we need to be sure that any
+      ITSTATE backup is re-updated before the side exit.
+   */

 
 

-      /* decide on the base transfer address */
-      IRTemp taT = newTemp(Ity_I32);
-      assign(taT,  summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT));
+   /* ----------------------------------------------------------- */
+   /* --                                                       -- */
+   /* -- Thumb 16-bit integer instructions                     -- */
+   /* --                                                       -- */
+   /* -- IMPORTANT: references to insn1 or INSN1 are           -- */
+   /* --            not allowed in this section                -- */
+   /* --                                                       -- */
+   /* ----------------------------------------------------------- */

 
 

-      /* update Rn if necessary -- in case 3, we're moving it down, so
-         update before any memory reference, in order to keep Memcheck
-         and V's stack-extending logic (on linux) happy */
-      if (summary == 3)
-         putIReg(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+   /* 16-bit instructions inside an IT block, apart from CMP, CMN and
+      TST, do not set the condition codes.  Hence we must dynamically
+      test for this case for every condition code update. */
+
+   IROp   anOp   = Iop_INVALID;
+   HChar* anOpNm = NULL;
+
+   /* ================ 16-bit 15:6 cases ================ */
+
+   switch (INSN0(15,6)) {
+
+   case 0x10a:   // CMP
+   case 0x10b: { // CMN
+      /* ---------------- CMP Rn, Rm ---------------- */
+      Bool   isCMN = INSN0(15,6) == 0x10b;
+      UInt   rN    = INSN0(2,0);
+      UInt   rM    = INSN0(5,3);
+      IRTemp argL  = newTemp(Ity_I32);
+      IRTemp argR  = newTemp(Ity_I32);
+      assign( argL, getIRegT(rN) );
+      assign( argR, getIRegT(rM) );
+      /* Update flags regardless of whether in an IT block or not. */
+      setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB,
+                      argL, argR, condT );
+      DIP("%s r%u, r%u\n", isCMN ? "cmn" : "cmp", rN, rM);
+      goto decode_success;
+   }

 
 

-      /* generate the transfers */
-      for (i = 0; i < nRegs; i++) {
-         IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(8*i));
-         if (bL) {
-            putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID);
-         } else {
-            storeLE(addr, getDReg(dD + i));
-         }
-      }
+   case 0x108: {
+      /* ---------------- TST Rn, Rm ---------------- */
+      UInt   rN   = INSN0(2,0);
+      UInt   rM   = INSN0(5,3);
+      IRTemp oldC = newTemp(Ity_I32);
+      IRTemp oldV = newTemp(Ity_I32);
+      IRTemp res  = newTemp(Ity_I32);
+      assign( oldC, mk_armg_calculate_flag_c() );
+      assign( oldV, mk_armg_calculate_flag_v() );
+      assign( res,  binop(Iop_And32, getIRegT(rN), getIRegT(rM)) );
+      /* Update flags regardless of whether in an IT block or not. */
+      setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, condT );
+      DIP("tst r%u, r%u\n", rN, rM);
+      goto decode_success;
+   }

 
 

-      /* update Rn if necessary -- in case 2, we're moving it up, so
-         update after any memory reference, in order to keep Memcheck
-         and V's stack-extending logic (on linux) happy */
-      if (summary == 2)
-         putIReg(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+   case 0x109: {
+      /* ---------------- NEGS Rd, Rm ---------------- */
+      /* Rd = -Rm */
+      UInt   rM   = INSN0(5,3);
+      UInt   rD   = INSN0(2,0);
+      IRTemp arg  = newTemp(Ity_I32);
+      IRTemp zero = newTemp(Ity_I32);
+      assign(arg, getIRegT(rM));
+      assign(zero, mkU32(0));
+      // rD can never be r15
+      putIRegT(rD, binop(Iop_Sub32, mkexpr(zero), mkexpr(arg)), condT);
+      setFlags_D1_D2( ARMG_CC_OP_SUB, zero, arg, cond_AND_notInIT_T);
+      DIP("negs r%u, r%u\n", rD, rM);
+      goto decode_success;
+   }

 
 

-      HChar* nm = bL==1 ? "ld" : "st";
-      switch (summary) {
-         case 1:  DIP("f%smx%s r%u, {d%u-d%u}\n", 
-                      nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
-                  break;
-         case 2:  DIP("f%smiax%s r%u!, {d%u-d%u}\n", 
-                      nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
-                  break;
-         case 3:  DIP("f%smdbx%s r%u!, {d%u-d%u}\n", 
-                      nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
-                  break;
-         default: vassert(0);
-      }
+   case 0x10F: {
+      /* ---------------- MVNS Rd, Rm ---------------- */
+      /* Rd = ~Rm */
+      UInt   rM   = INSN0(5,3);
+      UInt   rD   = INSN0(2,0);
+      IRTemp oldV = newTemp(Ity_I32);
+      IRTemp oldC = newTemp(Ity_I32);
+      IRTemp res  = newTemp(Ity_I32);
+      assign( oldV, mk_armg_calculate_flag_v() );
+      assign( oldC, mk_armg_calculate_flag_c() );
+      assign(res, unop(Iop_Not32, getIRegT(rM)));
+      // rD can never be r15
+      putIRegT(rD, mkexpr(res), condT);
+      setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                         cond_AND_notInIT_T );
+      DIP("mvns r%u, r%u\n", rD, rM);
+      goto decode_success;
+   }

 
 

+   case 0x10C:
+      /* ---------------- ORRS Rd, Rm ---------------- */
+      anOp = Iop_Or32; anOpNm = "orr"; goto and_orr_eor_mul;
+   case 0x100:
+      /* ---------------- ANDS Rd, Rm ---------------- */
+      anOp = Iop_And32; anOpNm = "and"; goto and_orr_eor_mul;
+   case 0x101:
+      /* ---------------- EORS Rd, Rm ---------------- */
+      anOp = Iop_Xor32; anOpNm = "eor"; goto and_orr_eor_mul;
+   case 0x10d:
+      /* ---------------- MULS Rd, Rm ---------------- */
+      anOp = Iop_Mul32; anOpNm = "mul"; goto and_orr_eor_mul;
+   and_orr_eor_mul: {
+      /* Rd = Rd `op` Rm */
+      UInt   rM   = INSN0(5,3);
+      UInt   rD   = INSN0(2,0);
+      IRTemp res  = newTemp(Ity_I32);
+      IRTemp oldV = newTemp(Ity_I32);
+      IRTemp oldC = newTemp(Ity_I32);
+      assign( oldV, mk_armg_calculate_flag_v() );
+      assign( oldC, mk_armg_calculate_flag_c() );
+      assign( res, binop(anOp, getIRegT(rD), getIRegT(rM) ));
+      // not safe to read guest state after here
+      // rD can never be r15
+      putIRegT(rD, mkexpr(res), condT);
+      setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                         cond_AND_notInIT_T );
+      DIP("%s r%u, r%u\n", anOpNm, rD, rM);
+      goto decode_success;
+   }

 
 

+   case 0x10E: {
+      /* ---------------- BICS Rd, Rm ---------------- */
+      /* Rd = Rd & ~Rm */
+      UInt   rM   = INSN0(5,3);
+      UInt   rD   = INSN0(2,0);
+      IRTemp res  = newTemp(Ity_I32);
+      IRTemp oldV = newTemp(Ity_I32);
+      IRTemp oldC = newTemp(Ity_I32);
+      assign( oldV, mk_armg_calculate_flag_v() );
+      assign( oldC, mk_armg_calculate_flag_c() );
+      assign( res, binop(Iop_And32, getIRegT(rD),
+                                    unop(Iop_Not32, getIRegT(rM) )));
+      // not safe to read guest state after here
+      // rD can never be r15
+      putIRegT(rD, mkexpr(res), condT);
+      setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                         cond_AND_notInIT_T );
+      DIP("bics r%u, r%u\n", rD, rM);

       goto decode_success;
       goto decode_success;

-      /* FIXME alignment constraints? */

    }
 
    }
 

-  after_vfp_fldmx_fstmx:
+   case 0x105: {
+      /* ---------------- ADCS Rd, Rm ---------------- */
+      /* Rd = Rd + Rm + oldC */
+      UInt   rM   = INSN0(5,3);
+      UInt   rD   = INSN0(2,0);
+      IRTemp argL = newTemp(Ity_I32);
+      IRTemp argR = newTemp(Ity_I32);
+      IRTemp oldC = newTemp(Ity_I32);
+      IRTemp res  = newTemp(Ity_I32);
+      assign(argL, getIRegT(rD));
+      assign(argR, getIRegT(rM));
+      assign(oldC, mk_armg_calculate_flag_c());
+      assign(res, binop(Iop_Add32,
+                        binop(Iop_Add32, mkexpr(argL), mkexpr(argR)),
+                        mkexpr(oldC)));
+      // rD can never be r15
+      putIRegT(rD, mkexpr(res), condT);
+      setFlags_D1_D2_ND( ARMG_CC_OP_ADC, argL, argR, oldC,
+                         cond_AND_notInIT_T );
+      DIP("adcs r%u, r%u\n", rD, rM);
+      goto decode_success;
+   }

 
 

-   /* --------------------- fldmd, fstmd --------------------- */
-   /*
-                                 31   27   23   19 15 11   7   0
-                                         P U WL
-      C4-96, C5-26   1  FSTMD    cond 1100 1000 Rn Dd 1011 offset
-      C4-96, C5-28   2  FSTMDIA  cond 1100 1010 Rn Dd 1011 offset
-      C4-96, C5-30   3  FSTMDDB  cond 1101 0010 Rn Dd 1011 offset
+   case 0x106: {
+      /* ---------------- SBCS Rd, Rm ---------------- */
+      /* Rd = Rd - Rm - (oldC ^ 1) */
+      UInt   rM   = INSN0(5,3);
+      UInt   rD   = INSN0(2,0);
+      IRTemp argL = newTemp(Ity_I32);
+      IRTemp argR = newTemp(Ity_I32);
+      IRTemp oldC = newTemp(Ity_I32);
+      IRTemp res  = newTemp(Ity_I32);
+      assign(argL, getIRegT(rD));
+      assign(argR, getIRegT(rM));
+      assign(oldC, mk_armg_calculate_flag_c());
+      assign(res, binop(Iop_Sub32,
+                        binop(Iop_Sub32, mkexpr(argL), mkexpr(argR)),
+                        binop(Iop_Xor32, mkexpr(oldC), mkU32(1))));
+      // rD can never be r15
+      putIRegT(rD, mkexpr(res), condT);
+      setFlags_D1_D2_ND( ARMG_CC_OP_SBB, argL, argR, oldC,
+                         cond_AND_notInIT_T );
+      DIP("sbcs r%u, r%u\n", rD, rM);
+      goto decode_success;
+   }

 
 

-      C4-38, C5-26   1  FLDMD    cond 1100 1001 Rn Dd 1011 offset
-      C4-38, C5-28   2  FLDMIAD  cond 1100 1011 Rn Dd 1011 offset
-      C4-38, C5-30   3  FLDMDBD  cond 1101 0011 Rn Dd 1011 offset
+   case 0x2CB: {
+      /* ---------------- UXTB Rd, Rm ---------------- */
+      /* Rd = 8Uto32(Rm) */
+      UInt rM = INSN0(5,3);
+      UInt rD = INSN0(2,0);
+      putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFF)),
+                   condT);
+      DIP("uxtb r%u, r%u\n", rD, rM);
+      goto decode_success;
+   }

 
 

-      Regs transferred: Dd .. D(d + (offset-2)/2)
-      offset must be even, must not imply a reg > 15
-      IA/DB: Rn is changed by (8 x # regs transferred)
+   case 0x2C9: {
+      /* ---------------- SXTB Rd, Rm ---------------- */
+      /* Rd = 8Sto32(Rm) */
+      UInt rM = INSN0(5,3);
+      UInt rD = INSN0(2,0);
+      putIRegT(rD, binop(Iop_Sar32,
+                         binop(Iop_Shl32, getIRegT(rM), mkU8(24)),
+                         mkU8(24)),
+                   condT);
+      DIP("sxtb r%u, r%u\n", rD, rM);
+      goto decode_success;
+   }

 
 

-      case coding:
-         1  at-Rn   (access at Rn)
-         2  ia-Rn   (access at Rn, then Rn += 8n)
-         3  db-Rn   (Rn -= 8n,     then access at Rn)
-   */
-   if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))
-       && INSN(11,8) == BITS4(1,0,1,1)) {
-      UInt bP     = (insn >> 24) & 1;
-      UInt bU     = (insn >> 23) & 1;
-      UInt bW     = (insn >> 21) & 1;
-      UInt bL     = (insn >> 20) & 1;
-      UInt offset = (insn >> 0) & 0xFF;
-      UInt rN     = INSN(19,16);
-      UInt dD     = INSN(15,12);
-      UInt nRegs  = offset / 2;
-      Int  i;
+   case 0x2CA: {
+      /* ---------------- UXTH Rd, Rm ---------------- */
+      /* Rd = 16Uto32(Rm) */
+      UInt rM = INSN0(5,3);
+      UInt rD = INSN0(2,0);
+      putIRegT(rD, binop(Iop_And32, getIRegT(rM), mkU32(0xFFFF)),
+                   condT);
+      DIP("uxth r%u, r%u\n", rD, rM);
+      goto decode_success;
+   }

 
 

-      /**/ if (bP == 0 && bU == 1 && bW == 0) {
-         vassert(0); //ATC
-         summary = 1;
-      }
-      else if (bP == 0 && bU == 1 && bW == 1) {
-         summary = 2;
-      }
-      else if (bP == 1 && bU == 0 && bW == 1) {
-         summary = 3;
-      }
-      else goto after_vfp_fldmd_fstmd;
+   case 0x2C8: {
+      /* ---------------- SXTH Rd, Rm ---------------- */
+      /* Rd = 16Sto32(Rm) */
+      UInt rM = INSN0(5,3);
+      UInt rD = INSN0(2,0);
+      putIRegT(rD, binop(Iop_Sar32,
+                         binop(Iop_Shl32, getIRegT(rM), mkU8(16)),
+                         mkU8(16)),
+                   condT);
+      DIP("sxth r%u, r%u\n", rD, rM);
+      goto decode_success;
+   }

 
 

-      /* no writebacks to r15 allowed */
-      if (rN == 15 && (summary == 2 || summary == 3))
-         goto after_vfp_fldmd_fstmd;
+   case 0x102:   // LSLS
+   case 0x103:   // LSRS
+   case 0x104:   // ASRS
+   case 0x107: { // RORS
+      /* ---------------- LSLS Rs, Rd ---------------- */
+      /* ---------------- LSRS Rs, Rd ---------------- */
+      /* ---------------- ASRS Rs, Rd ---------------- */
+      /* ---------------- RORS Rs, Rd ---------------- */
+      /* Rd = Rd `op` Rs, and set flags */
+      UInt   rS   = INSN0(5,3);
+      UInt   rD   = INSN0(2,0);
+      IRTemp oldV = newTemp(Ity_I32);
+      IRTemp rDt  = newTemp(Ity_I32);
+      IRTemp rSt  = newTemp(Ity_I32);
+      IRTemp res  = newTemp(Ity_I32);
+      IRTemp resC = newTemp(Ity_I32);
+      HChar* wot  = "???";
+      assign(rSt, getIRegT(rS));
+      assign(rDt, getIRegT(rD));
+      assign(oldV, mk_armg_calculate_flag_v());
+      /* Does not appear to be the standard 'how' encoding. */
+      switch (INSN0(15,6)) {
+         case 0x102:
+            compute_result_and_C_after_LSL_by_reg(
+               dis_buf, &res, &resC, rDt, rSt, rD, rS
+            );
+            wot = "lsl";
+            break;
+         case 0x103:
+            compute_result_and_C_after_LSR_by_reg(
+               dis_buf, &res, &resC, rDt, rSt, rD, rS
+            );
+            wot = "lsr";
+            break;
+         case 0x104:
+            compute_result_and_C_after_ASR_by_reg(
+               dis_buf, &res, &resC, rDt, rSt, rD, rS
+            );
+            wot = "asr";
+            break;
+         case 0x107:
+            compute_result_and_C_after_ROR_by_reg(
+               dis_buf, &res, &resC, rDt, rSt, rD, rS
+            );
+            wot = "ror";
+            break;
+         default:
+            /*NOTREACHED*/vassert(0);
+      }
+      // not safe to read guest state after this point
+      putIRegT(rD, mkexpr(res), condT);
+      setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, resC, oldV,
+                         cond_AND_notInIT_T );
+      DIP("%ss r%u, r%u\n", wot, rS, rD);
+      goto decode_success;
+   }

 
 

-      /* offset must be even, and specify at least one register */
-      if (1 == (offset & 1) || offset < 2)
-         goto after_vfp_fldmd_fstmd;
+   default:
+      break; /* examine the next shortest prefix */

 
 

-      /* can't transfer regs after D15 */
-      if (dD + nRegs - 1 >= 16)
-         goto after_vfp_fldmd_fstmd;
+   }

 
 

-      /* Now, we can't do a conditional load or store, since that very
-         likely will generate an exception.  So we have to take a side
-         exit at this point if the condition is false. */
-      if (condT != IRTemp_INVALID) {
-         mk_skip_to_next_if_cond_is_false( condT );
-         condT = IRTemp_INVALID;
-      }
-      /* Ok, now we're unconditional.  Do the load or store. */

 
 

-      /* get the old Rn value */
-      IRTemp rnT = newTemp(Ity_I32);
-      assign(rnT, getIReg(rN));
+   /* ================ 16-bit 15:7 cases ================ */

 
 

-      /* make a new value for Rn, post-insn */
-      IRTemp rnTnew = IRTemp_INVALID;
-      if (summary == 2 || summary == 3) {
-         rnTnew = newTemp(Ity_I32);
-         assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32,
-                              mkexpr(rnT),
-                              mkU32(8 * nRegs)));
-      }
+   switch (INSN0(15,7)) {

 
 

-      /* decide on the base transfer address */
-      IRTemp taT = newTemp(Ity_I32);
-      assign(taT, summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT));
+   case BITS9(1,0,1,1,0,0,0,0,0): {
+      /* ------------ ADD SP, #imm7 * 4 ------------ */
+      UInt uimm7 = INSN0(6,0);
+      putIRegT(13, binop(Iop_Add32, getIRegT(13), mkU32(uimm7 * 4)),
+                   condT);
+      DIP("add sp, #%u\n", uimm7 * 4);
+      goto decode_success;
+   }

 
 

-      /* update Rn if necessary -- in case 3, we're moving it down, so
-         update before any memory reference, in order to keep Memcheck
-         and V's stack-extending logic (on linux) happy */
-      if (summary == 3)
-         putIReg(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+   case BITS9(1,0,1,1,0,0,0,0,1): {
+      /* ------------ SUB SP, #imm7 * 4 ------------ */
+      UInt uimm7 = INSN0(6,0);
+      putIRegT(13, binop(Iop_Sub32, getIRegT(13), mkU32(uimm7 * 4)),
+                   condT);
+      DIP("sub sp, #%u\n", uimm7 * 4);
+      goto decode_success;
+   }

 
 

-      /* generate the transfers */
-      for (i = 0; i < nRegs; i++) {
-         IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(8*i));
-         if (bL) {
-            putDReg(dD + i, loadLE(Ity_F64, addr), IRTemp_INVALID);
+   case BITS9(0,1,0,0,0,1,1,1,0): {
+      /* ---------------- BX rM ---------------- */
+      /* Branch to reg, and optionally switch modes.  Reg contains a
+         suitably encoded address therefore (w CPSR.T at the bottom).
+         Have to special-case r15, as usual. */
+      UInt rM = (INSN0(6,6) << 3) | INSN0(5,3);
+      if (BITS3(0,0,0) == INSN0(2,0) &&/*atc*/rM != 15) {
+         IRTemp dst = newTemp(Ity_I32);
+         gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+         mk_skip_over_T16_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         // now uncond
+         if (rM <= 14) {
+            assign( dst, getIRegT(rM) );

          } else {
          } else {

-            storeLE(addr, getDReg(dD + i));
+            break; // ATC
+            vassert(rM == 15);
+            assign( dst, mkU32(guest_R15_curr_instr_notENC + 4) );

          }
          }

+         irsb->next     = mkexpr(dst);
+         irsb->jumpkind = Ijk_Boring;
+         dres.whatNext  = Dis_StopHere;
+         DIP("bx r%u (possibly switch to ARM mode)\n", rM);
+         goto decode_success;

       }
       }

+      break;
+   }

 
 

-      /* update Rn if necessary -- in case 2, we're moving it up, so
-         update after any memory reference, in order to keep Memcheck
-         and V's stack-extending logic (on linux) happy */
-      if (summary == 2)
-         putIReg(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
-
-      HChar* nm = bL==1 ? "ld" : "st";
-      switch (summary) {
-         case 1:  DIP("f%smd%s r%u, {d%u-d%u}\n", 
-                      nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
-                  break;
-         case 2:  DIP("f%smiad%s r%u!, {d%u-d%u}\n", 
-                      nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
-                  break;
-         case 3:  DIP("f%smdbd%s r%u!, {d%u-d%u}\n", 
-                      nm, nCC(INSN_COND), rN, dD, dD + nRegs - 1);
-                  break;
-         default: vassert(0);
+   /* ---------------- BLX rM ---------------- */
+   /* Branch and link to interworking address in rM. */
+   case BITS9(0,1,0,0,0,1,1,1,1): {
+      if (BITS3(0,0,0) == INSN0(2,0)) {
+         UInt rM = (INSN0(6,6) << 3) | INSN0(5,3);
+         IRTemp dst = newTemp(Ity_I32);
+         if (rM <= 14) {
+            gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+            mk_skip_over_T16_if_cond_is_false(condT);
+            condT = IRTemp_INVALID;
+            // now uncond
+            /* We're returning to Thumb code, hence "| 1" */
+            assign( dst, getIRegT(rM) );
+            putIRegT( 14, mkU32( (guest_R15_curr_instr_notENC + 2) | 1 ),
+                          IRTemp_INVALID );
+            irsb->next     = mkexpr(dst);
+            irsb->jumpkind = Ijk_Boring;
+            dres.whatNext  = Dis_StopHere;
+            DIP("blx r%u (possibly switch to ARM mode)\n", rM);
+            goto decode_success;
+         }
+         /* else unpredictable, fall through */

       }
       }

+      break;
+   }
+
+   default:
+      break; /* examine the next shortest prefix */

 
 

-      goto decode_success;
-      /* FIXME alignment constraints? */

    }
 
    }
 

-  after_vfp_fldmd_fstmd:

 
 

-   /* ------------------- fmrx, fmxr ------------------- */
-   if (BITS8(1,1,1,0,1,1,1,1) == INSN(27,20)
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS8(0,0,0,1,0,0,0,0) == (insn & 0xFF)) {
-      UInt rD  = INSN(15,12);
-      UInt reg = INSN(19,16);
-      if (reg == BITS4(0,0,0,1)) {
-         if (rD == 15) {
-            IRTemp nzcvT = newTemp(Ity_I32);
-            /* When rD is 15, we are copying the top 4 bits of FPSCR
-               into CPSR.  That is, set the flags thunk to COPY and
-               install FPSCR[31:28] as the value to copy. */
-            assign(nzcvT, binop(Iop_And32,
-                                IRExpr_Get(OFFB_FPSCR, Ity_I32),
-                                mkU32(0xF0000000)));
-            setFlags_D1(ARMG_CC_OP_COPY, nzcvT, condT);
-            DIP("fmstat%s\n", nCC(INSN_COND));
+   /* ================ 16-bit 15:8 cases ================ */
+
+   switch (INSN0(15,8)) {
+
+   case BITS8(1,1,0,1,1,1,1,1): {
+      /* ---------------- SVC ---------------- */
+      UInt imm8 = INSN0(7,0);
+      if (imm8 == 0) {
+         /* A syscall.  We can't do this conditionally, hence: */
+         mk_skip_over_T16_if_cond_is_false( condT );
+         // FIXME: what if we have to back up and restart this insn?
+         // then ITSTATE will be wrong (we'll have it as "used")
+         // when it isn't.  Correct is to save ITSTATE in a 
+         // stash pseudo-reg, and back up from that if we have to
+         // restart.
+         // uncond after here
+         irsb->next     = mkU32( (guest_R15_curr_instr_notENC + 2) | 1 );
+         irsb->jumpkind = Ijk_Sys_syscall;
+         dres.whatNext  = Dis_StopHere;
+         DIP("svc #0x%08x\n", imm8);
+         goto decode_success;
+      }
+      /* else fall through */
+      break;
+   }
+
+   case BITS8(0,1,0,0,0,1,0,0): {
+      /* ---------------- ADD(HI) Rd, Rm ---------------- */
+      UInt h1 = INSN0(7,7);
+      UInt h2 = INSN0(6,6);
+      UInt rM = (h2 << 3) | INSN0(5,3);
+      UInt rD = (h1 << 3) | INSN0(2,0);
+      //if (h1 == 0 && h2 == 0) { // Original T1 was more restrictive
+      if (rD == 15 && rM == 15) {
+         // then it's invalid
+      } else {
+         IRTemp res = newTemp(Ity_I32);
+         assign( res, binop(Iop_Add32, getIRegT(rD), getIRegT(rM) ));
+         if (rD != 15) {
+            putIRegT( rD, mkexpr(res), condT );

          } else {
          } else {

-            /* Otherwise, merely transfer FPSCR to r0 .. r14. */
-            putIReg(rD, IRExpr_Get(OFFB_FPSCR, Ity_I32), 
-                        condT, Ijk_Boring);
-            DIP("fmrx%s r%u, fpscr\n", nCC(INSN_COND), rD);
+            /* Only allowed outside or last-in IT block; SIGILL if not so. */
+            gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+            /* jump over insn if not selected */
+            mk_skip_over_T16_if_cond_is_false(condT);
+            condT = IRTemp_INVALID;
+            // now uncond
+            /* non-interworking branch */
+            irsb->next = binop(Iop_Or32, mkexpr(res), mkU32(1));
+            irsb->jumpkind = Ijk_Boring;
+            dres.whatNext = Dis_StopHere;

          }
          }

+         DIP("add(hi) r%u, r%u\n", rD, rM);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */
+      break;

    }
 
    }
 

-   if (BITS8(1,1,1,0,1,1,1,0) == INSN(27,20)
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS8(0,0,0,1,0,0,0,0) == (insn & 0xFF)) {
-      UInt rD  = INSN(15,12);
-      UInt reg = INSN(19,16);
-      if (reg == BITS4(0,0,0,1)) {
-         putMiscReg32(OFFB_FPSCR, getIReg(rD), condT);
-         DIP("fmxr%s fpscr, r%u\n", nCC(INSN_COND), rD);
+   case BITS8(0,1,0,0,0,1,0,1): {
+      /* ---------------- CMP(HI) Rd, Rm ---------------- */
+      UInt h1 = INSN0(7,7);
+      UInt h2 = INSN0(6,6);
+      UInt rM = (h2 << 3) | INSN0(5,3);
+      UInt rN = (h1 << 3) | INSN0(2,0);
+      if (h1 != 0 || h2 != 0) {
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         assign( argL, getIRegT(rN) );
+         assign( argR, getIRegT(rM) );
+         /* Update flags regardless of whether in an IT block or not. */
+         setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT );
+         DIP("cmphi r%u, r%u\n", rN, rM);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */
+      break;

    }
 
    }
 

-   /* --------------------- vmov --------------------- */
-   // VMOV dM, rD, rN
-   if (0x0C400B10 == (insn & 0x0FF00FF0)) {
-      UInt dM = INSN(3,0);
-      UInt rD = INSN(15,12); /* lo32 */
-      UInt rN = INSN(19,16); /* hi32 */
-      if (rD == 15 || rN == 15) {
-         /* fall through */
-      } else {
-         putDReg(dM,
-                 unop(Iop_ReinterpI64asF64,
-                      binop(Iop_32HLto64, getIReg(rN), getIReg(rD))),
-                 condT);
-         DIP("vmov%s d%u, r%u, r%u\n", nCC(INSN_COND), dM, rD, rN);
+   case BITS8(0,1,0,0,0,1,1,0): {
+      /* ---------------- MOV(HI) Rd, Rm ---------------- */
+      UInt h1 = INSN0(7,7);
+      UInt h2 = INSN0(6,6);
+      UInt rM = (h2 << 3) | INSN0(5,3);
+      UInt rD = (h1 << 3) | INSN0(2,0);
+      /* The old ARM ARM seems to disallow the case where both Rd and
+         Rm are "low" registers, but newer versions allow it. */
+      if (1 /*h1 != 0 || h2 != 0*/) {
+         IRTemp val = newTemp(Ity_I32);
+         assign( val, getIRegT(rM) );
+         if (rD != 15) {
+            putIRegT( rD, mkexpr(val), condT );
+         } else {
+            /* Only allowed outside or last-in IT block; SIGILL if not so. */
+            gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+            /* jump over insn if not selected */
+            mk_skip_over_T16_if_cond_is_false(condT);
+            condT = IRTemp_INVALID;
+            // now uncond
+            /* non-interworking branch */
+            irsb->next = binop(Iop_Or32, mkexpr(val), mkU32(1));
+            irsb->jumpkind = Ijk_Boring;
+            dres.whatNext = Dis_StopHere;
+         }
+         DIP("mov r%u, r%u\n", rD, rM);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */
+      break;

    }
 
    }
 

-   // VMOV rD, rN, dM
-   if (0x0C500B10 == (insn & 0x0FF00FF0)) {
-      UInt dM = INSN(3,0);
-      UInt rD = INSN(15,12); /* lo32 */
-      UInt rN = INSN(19,16); /* hi32 */
-      if (rD == 15 || rN == 15 || rD == rN) {
-         /* fall through */
-      } else {
-         IRTemp i64 = newTemp(Ity_I64);
-         assign(i64, unop(Iop_ReinterpF64asI64, getDReg(dM)));
-         putIReg(rN, unop(Iop_64HIto32, mkexpr(i64)), condT, Ijk_Boring);
-         putIReg(rD, unop(Iop_64to32,   mkexpr(i64)), condT, Ijk_Boring);
-         DIP("vmov%s r%u, r%u, d%u\n", nCC(INSN_COND), rD, rN, dM);
+   case BITS8(1,0,1,1,1,1,1,1): {
+      /* ---------------- IT (if-then) ---------------- */
+      UInt firstcond = INSN0(7,4);
+      UInt mask = INSN0(3,0);
+      UInt newITSTATE = 0;
+      /* This is the ITSTATE represented as described in
+         libvex_guest_arm.h.  It is not the ARM ARM representation. */
+      UChar c1 = '.';
+      UChar c2 = '.';
+      UChar c3 = '.';
+      Bool valid = compute_ITSTATE( &newITSTATE, &c1, &c2, &c3,
+                                    firstcond, mask );
+      if (valid && firstcond != 0xF/*NV*/) {
+         /* Not allowed in an IT block; SIGILL if so. */
+         gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+
+         IRTemp t = newTemp(Ity_I32);
+         assign(t, mkU32(newITSTATE));
+         put_ITSTATE(t);
+
+         DIP("it%c%c%c %s\n", c1, c2, c3, nCC(firstcond));

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */
+      break;

    }
 
    }
 

-   /* --------------------- f{ld,st}d --------------------- */
-   // FLDD, FSTD
-   if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,0))
-       && BITS4(1,0,1,1) == INSN(11,8)) {
-      UInt dD     = INSN(15,12);
-      UInt rN     = INSN(19,16);
-      UInt offset = (insn & 0xFF) << 2;
-      UInt bU     = (insn >> 23) & 1; /* 1: +offset  0: -offset */
-      UInt bL     = (insn >> 20) & 1; /* 1: load  0: store */
-      /* make unconditional */
-      if (condT != IRTemp_INVALID) {
-         mk_skip_to_next_if_cond_is_false( condT );
-         condT = IRTemp_INVALID;
-      }
-      IRTemp ea = newTemp(Ity_I32);
-      assign(ea, binop(bU ? Iop_Add32 : Iop_Sub32,
-                       getIReg(rN), mkU32(offset)));
-      if (bL) {
-         putDReg(dD, loadLE(Ity_F64,mkexpr(ea)), IRTemp_INVALID);
-      } else {
-         storeLE(mkexpr(ea), getDReg(dD));
-      }
-      DIP("f%sd%s d%u, [r%u, %c#%u]\n",
-          bL ? "ld" : "st", nCC(INSN_COND), dD, rN,
-          bU ? '+' : '-', offset);
+   case BITS8(1,0,1,1,0,0,0,1):
+   case BITS8(1,0,1,1,0,0,1,1):
+   case BITS8(1,0,1,1,1,0,0,1):
+   case BITS8(1,0,1,1,1,0,1,1): {
+      /* ---------------- CB{N}Z ---------------- */
+      UInt rN    = INSN0(2,0);
+      UInt bOP   = INSN0(11,11);
+      UInt imm32 = (INSN0(9,9) << 6) | (INSN0(7,3) << 1);
+      gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+      /* It's a conditional branch forward. */
+      IRTemp kond = newTemp(Ity_I1);
+      assign( kond, binop(bOP ? Iop_CmpNE32 : Iop_CmpEQ32,
+                          getIRegT(rN), mkU32(0)) );
+
+      vassert(0 == (guest_R15_curr_instr_notENC & 1));
+      /* Looks like the nearest insn we can branch to is the one after
+         next.  That makes sense, as there's no point in being able to
+         encode a conditional branch to the next instruction. */
+      UInt dst = (guest_R15_curr_instr_notENC + 4 + imm32) | 1;
+      stmt(IRStmt_Exit( mkexpr(kond),
+                        Ijk_Boring,
+                        IRConst_U32(toUInt(dst)) ));
+      DIP("cb%s r%u, 0x%x\n", bOP ? "nz" : "z", rN, dst - 1);

       goto decode_success;
    }
 
       goto decode_success;
    }
 

-   /* --------------------- dp insns (D) --------------------- */
-   if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,1,0,0))
-       && BITS4(1,0,1,1) == INSN(11,8)
-       && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(1,0,1,1))) {
-      UInt    dM  = INSN(3,0);   /* argR */
-      UInt    dD  = INSN(15,12); /* dst/acc */
-      UInt    dN  = INSN(19,16); /* argL */
-      UInt    bP  = (insn >> 23) & 1;
-      UInt    bQ  = (insn >> 21) & 1;
-      UInt    bR  = (insn >> 20) & 1;
-      UInt    bS  = (insn >> 6) & 1;
-      UInt    opc = (bP << 3) | (bQ << 2) | (bR << 1) | bS;
-      IRExpr* rm  = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
-      switch (opc) {
-         case BITS4(0,0,0,0): /* MAC: d + n * m */
-            putDReg(dD, triop(Iop_AddF64, rm,
-                              getDReg(dD),
-                              triop(Iop_MulF64, rm, getDReg(dN),
-                                                    getDReg(dM))),
-                        condT);
-            DIP("fmacd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         case BITS4(0,0,0,1): /* NMAC: d - n * m */
-            putDReg(dD, triop(Iop_SubF64, rm,
-                              getDReg(dD),
-                              triop(Iop_MulF64, rm, getDReg(dN),
-                                                    getDReg(dM))),
-                        condT);
-            DIP("fnmacd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         case BITS4(0,0,1,0): /* MSC: - d + n * m */
-            putDReg(dD, triop(Iop_AddF64, rm,
-                              unop(Iop_NegF64, getDReg(dD)),
-                              triop(Iop_MulF64, rm, getDReg(dN),
-                                                    getDReg(dM))),
-                        condT);
-            DIP("fmscd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         case BITS4(0,0,1,1): /* NMSC: - d - n * m */
-            putDReg(dD, triop(Iop_SubF64, rm,
-                              unop(Iop_NegF64, getDReg(dD)),
-                              triop(Iop_MulF64, rm, getDReg(dN),
-                                                    getDReg(dM))),
-                        condT);
-            DIP("fnmscd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         case BITS4(0,1,0,0): /* MUL: n * m */
-            putDReg(dD, triop(Iop_MulF64, rm, getDReg(dN), getDReg(dM)),
-                        condT);
-            DIP("fmuld%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         case BITS4(0,1,0,1): /* NMUL: - n * m */
-            putDReg(dD, unop(Iop_NegF64,
-                             triop(Iop_MulF64, rm, getDReg(dN),
-                                                   getDReg(dM))),
-                    condT);
-            DIP("fnmuld%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         case BITS4(0,1,1,0): /* ADD: n + m */
-            putDReg(dD, triop(Iop_AddF64, rm, getDReg(dN), getDReg(dM)),
-                        condT);
-            DIP("faddd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         case BITS4(0,1,1,1): /* SUB: n - m */
-            putDReg(dD, triop(Iop_SubF64, rm, getDReg(dN), getDReg(dM)),
-                        condT);
-            DIP("fsubd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         case BITS4(1,0,0,0): /* DIV: n / m */
-            putDReg(dD, triop(Iop_DivF64, rm, getDReg(dN), getDReg(dM)),
-                        condT);
-            DIP("fdivd%s d%u, d%u, d%u\n", nCC(INSN_COND), dD, dN, dM);
-            goto decode_success;
-         default:
-            break;
-      }
-   }
+   default:
+      break; /* examine the next shortest prefix */

 
 

-   /* --------------------- compares (D) --------------------- */
-   /*          31   27   23   19   15 11   7    3
-                 28   24   20   16 12    8    4    0 
-      FCMPD    cond 1110 1011 0100 Dd 1011 0100 Dm
-      FCMPED   cond 1110 1011 0100 Dd 1011 1100 Dm
-      FCMPZD   cond 1110 1011 0101 Dd 1011 0100 0000
-      FCMPZED  cond 1110 1011 0101 Dd 1011 1100 0000
-                                 Z         N
+   }

 
 

-      Z=0 Compare Dd vs Dm     and set FPSCR 31:28 accordingly
-      Z=1 Compare Dd vs zero

 
 

-      N=1 generates Invalid Operation exn if either arg is any kind of NaN
-      N=0 generates Invalid Operation exn if either arg is a signalling NaN
-      (Not that we pay any attention to N here)
-   */
-   if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
-       && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
-       && BITS4(1,0,1,1) == INSN(11,8)
-       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
-      UInt bZ = (insn >> 16) & 1;
-      UInt bN = (insn >> 7) & 1;
-      UInt dD = INSN(15,12);
-      UInt dM = INSN(3,0);
-      if (bZ && INSN(3,0) != 0) {
-         /* does not decode; fall through */
-      } else {
-         IRTemp argL = newTemp(Ity_F64);
-         IRTemp argR = newTemp(Ity_F64);
-         IRTemp irRes = newTemp(Ity_I32);
-         assign(argL, getDReg(dD));
-         assign(argR, bZ ? IRExpr_Const(IRConst_F64i(0)) : getDReg(dM));
-         assign(irRes, binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR)));
+   /* ================ 16-bit 15:9 cases ================ */

 
 

-         IRTemp nzcv     = IRTemp_INVALID;
-         IRTemp oldFPSCR = newTemp(Ity_I32);
-         IRTemp newFPSCR = newTemp(Ity_I32);
+   switch (INSN0(15,9)) {

 
 

-         /* This is where the fun starts.  We have to convert 'irRes'
-            from an IR-convention return result (IRCmpF64Result) to an
-            ARM-encoded (N,Z,C,V) group.  The final result is in the
-            bottom 4 bits of 'nzcv'. */
-         /* Map compare result from IR to ARM(nzcv) */
-         /*
-            FP cmp result | IR   | ARM(nzcv)
-            --------------------------------
-            UN              0x45   0011
-            LT              0x01   1000
-            GT              0x00   0010
-            EQ              0x40   0110
-         */
-         nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes);
+   case BITS7(1,0,1,1,0,1,0): {
+      /* ---------------- PUSH ---------------- */
+      /* This is a bit like STMxx, but way simpler. Complications we
+         don't have to deal with:
+         * SP being one of the transferred registers
+         * direction (increment vs decrement)
+         * before-vs-after-ness
+      */
+      Int  i, nRegs;
+      UInt bitR    = INSN0(8,8);
+      UInt regList = INSN0(7,0);
+      if (bitR) regList |= (1 << 14);
+   
+      if (regList != 0) {
+         /* Since we can't generate a guaranteed non-trapping IR
+            sequence, (1) jump over the insn if it is gated false, and
+            (2) back out the ITSTATE update. */
+         mk_skip_over_T16_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         put_ITSTATE(old_itstate);
+         // now uncond

 
 

-         /* And update FPSCR accordingly */
-         assign(oldFPSCR, IRExpr_Get(OFFB_FPSCR, Ity_I32));
-         assign(newFPSCR, 
-                binop(Iop_Or32, 
-                      binop(Iop_And32, mkexpr(oldFPSCR), mkU32(0x0FFFFFFF)),
-                      binop(Iop_Shl32, mkexpr(nzcv), mkU8(28))));
+         nRegs = 0;
+         for (i = 0; i < 16; i++) {
+            if ((regList & (1 << i)) != 0)
+               nRegs++;
+         }
+         vassert(nRegs >= 1 && nRegs <= 8);
+
+         /* Move SP down first of all, so we're "covered".  And don't
+            mess with its alignment. */
+         IRTemp newSP = newTemp(Ity_I32);
+         assign(newSP, binop(Iop_Sub32, getIRegT(13), mkU32(4 * nRegs)));
+         putIRegT(13, mkexpr(newSP), IRTemp_INVALID);
+
+         /* Generate a transfer base address as a forced-aligned
+            version of the final SP value. */
+         IRTemp base = newTemp(Ity_I32);
+         assign(base, binop(Iop_And32, mkexpr(newSP), mkU32(~3)));
+
+         /* Now the transfers */
+         nRegs = 0;
+         for (i = 0; i < 16; i++) {
+            if ((regList & (1 << i)) != 0) {
+               storeLE( binop(Iop_Add32, mkexpr(base), mkU32(4 * nRegs)),
+                        getIRegT(i) );
+               nRegs++;
+            }
+         }

 
 

-         putMiscReg32(OFFB_FPSCR, mkexpr(newFPSCR), condT);
+         /* Reinstate the ITSTATE update. */
+         put_ITSTATE(new_itstate);

 
 

-         if (bZ) {
-            DIP("fcmpz%sd%s d%u\n", bN ? "e" : "", nCC(INSN_COND), dD);
-         } else {
-            DIP("fcmp%sd%s d%u, d%u\n", bN ? "e" : "", nCC(INSN_COND), dD, dM);
-         }
+         DIP("push {%s0x%04x}\n", bitR ? "lr," : "", regList & 0xFF);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */
-   }  
+      break;
+   }

 
 

-   /* --------------------- unary (D) --------------------- */
-   if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
-       && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
-       && BITS4(1,0,1,1) == INSN(11,8)
-       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
-      UInt dD  = INSN(15,12);
-      UInt dM  = INSN(3,0);
-      UInt b16 = (insn >> 16) & 1;
-      UInt b7  = (insn >> 7) & 1;
-      /**/ if (b16 == 0 && b7 == 0) {
-         // FCPYD
-         putDReg(dD, getDReg(dM), condT);
-         DIP("fcpyd%s d%u, d%u\n", nCC(INSN_COND), dD, dM);
-         goto decode_success;
-      }
-      else if (b16 == 0 && b7 == 1) {
-         // FABSD
-         putDReg(dD, unop(Iop_AbsF64, getDReg(dM)), condT);
-         DIP("fabsd%s d%u, d%u\n", nCC(INSN_COND), dD, dM);
-         goto decode_success;
-      }
-      else if (b16 == 1 && b7 == 0) {
-         // FNEGD
-         putDReg(dD, unop(Iop_NegF64, getDReg(dM)), condT);
-         DIP("fnegd%s d%u, d%u\n", nCC(INSN_COND), dD, dM);
-         goto decode_success;
-      }
-      else if (b16 == 1 && b7 == 1) {
-         // FSQRTD
-         IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
-         putDReg(dD, binop(Iop_SqrtF64, rm, getDReg(dM)), condT);
-         DIP("fsqrtd%s d%u, d%u\n", nCC(INSN_COND), dD, dM);
+   case BITS7(1,0,1,1,1,1,0): {
+      /* ---------------- POP ---------------- */
+      Int  i, nRegs;
+      UInt bitR    = INSN0(8,8);
+      UInt regList = INSN0(7,0);
+   
+      if (regList != 0 || bitR) {
+         /* Since we can't generate a guaranteed non-trapping IR
+            sequence, (1) jump over the insn if it is gated false, and
+            (2) back out the ITSTATE update. */
+         mk_skip_over_T16_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         put_ITSTATE(old_itstate);
+         // now uncond
+
+         nRegs = 0;
+         for (i = 0; i < 8; i++) {
+            if ((regList & (1 << i)) != 0)
+               nRegs++;
+         }
+         vassert(nRegs >= 0 && nRegs <= 7);
+         vassert(bitR == 0 || bitR == 1);
+
+         IRTemp oldSP = newTemp(Ity_I32);
+         assign(oldSP, getIRegT(13));
+
+         /* Generate a transfer base address as a forced-aligned
+            version of the original SP value. */
+         IRTemp base = newTemp(Ity_I32);
+         assign(base, binop(Iop_And32, mkexpr(oldSP), mkU32(~3)));
+
+         /* Compute a new value for SP, but don't install it yet, so
+            that we're "covered" until all the transfers are done.
+            And don't mess with its alignment. */
+         IRTemp newSP = newTemp(Ity_I32);
+         assign(newSP, binop(Iop_Add32, mkexpr(oldSP),
+                                        mkU32(4 * (nRegs + bitR))));
+
+         /* Now the transfers, not including PC */
+         nRegs = 0;
+         for (i = 0; i < 8; i++) {
+            if ((regList & (1 << i)) != 0) {
+               putIRegT(i, loadLE( Ity_I32,
+                                   binop(Iop_Add32, mkexpr(base),
+                                                    mkU32(4 * nRegs))),
+                           IRTemp_INVALID );
+               nRegs++;
+            }
+         }
+
+         IRTemp newPC = IRTemp_INVALID;
+         if (bitR) {
+            newPC = newTemp(Ity_I32);
+            assign( newPC, loadLE( Ity_I32,
+                                   binop(Iop_Add32, mkexpr(base),
+                                                    mkU32(4 * nRegs))));
+         }
+
+         /* Now we can safely install the new SP value */
+         putIRegT(13, mkexpr(newSP), IRTemp_INVALID);
+
+         /* Reinstate the ITSTATE update. */
+         put_ITSTATE(new_itstate);
+
+         /* now, do we also have to do a branch?  If so, it turns out
+            that the new PC value is encoded exactly as we need it to
+            be -- with CPSR.T in the bottom bit.  So we can simply use
+            it as is, no need to mess with it.  Note, therefore, this
+            is an interworking return. */
+         if (bitR) {
+            irsb->next     = mkexpr(newPC);
+            irsb->jumpkind = Ijk_Ret;
+            dres.whatNext  = Dis_StopHere;
+         }
+
+         DIP("pop {%s0x%04x}\n", bitR ? "pc," : "", regList & 0xFF);

          goto decode_success;
       }
          goto decode_success;
       }

-      else
-         vassert(0);
+      break;
+   }

 
 

-      /* fall through */
+   case BITS7(0,0,0,1,1,1,0):   /* ADDS */
+   case BITS7(0,0,0,1,1,1,1): { /* SUBS */
+      /* ---------------- ADDS Rd, Rn, #uimm3 ---------------- */
+      /* ---------------- SUBS Rd, Rn, #uimm3 ---------------- */
+      UInt   uimm3 = INSN0(8,6);
+      UInt   rN    = INSN0(5,3);
+      UInt   rD    = INSN0(2,0);
+      UInt   isSub = INSN0(9,9);
+      IRTemp argL  = newTemp(Ity_I32);
+      IRTemp argR  = newTemp(Ity_I32);
+      assign( argL, getIRegT(rN) );
+      assign( argR, mkU32(uimm3) );
+      putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
+                         mkexpr(argL), mkexpr(argR)),
+                   condT);
+      setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
+                      argL, argR, cond_AND_notInIT_T );
+      DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3);
+      goto decode_success;

    }
 
    }
 

-   /* ----------------- I <-> D conversions ----------------- */
+   case BITS7(0,0,0,1,1,0,0):   /* ADDS */
+   case BITS7(0,0,0,1,1,0,1): { /* SUBS */
+      /* ---------------- ADDS Rd, Rn, Rm ---------------- */
+      /* ---------------- SUBS Rd, Rn, Rm ---------------- */
+      UInt   rM    = INSN0(8,6);
+      UInt   rN    = INSN0(5,3);
+      UInt   rD    = INSN0(2,0);
+      UInt   isSub = INSN0(9,9);
+      IRTemp argL  = newTemp(Ity_I32);
+      IRTemp argR  = newTemp(Ity_I32);
+      assign( argL, getIRegT(rN) );
+      assign( argR, getIRegT(rM) );
+      putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
+                          mkexpr(argL), mkexpr(argR)),
+                    condT );
+      setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
+                      argL, argR, cond_AND_notInIT_T );
+      DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
+      goto decode_success;
+   }

 
 

-   // F{S,U}ITOD dD, fM
-   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,1))
-       && BITS4(1,0,0,0) == (INSN(19,16) & BITS4(1,1,1,1))
-       && BITS4(1,0,1,1) == INSN(11,8)
-       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
-      UInt bM    = (insn >> 5) & 1;
-      UInt fM    = (INSN(3,0) << 1) | bM;
-      UInt dD    = INSN(15,12);
-      UInt syned = (insn >> 7) & 1;
-      if (syned) {
-         // FSITOD
-         putDReg(dD, unop(Iop_I32StoF64,
-                          unop(Iop_ReinterpF32asI32, getFReg(fM))),
-                 condT);
-         DIP("fsitod%s d%u, s%u\n", nCC(INSN_COND), dD, fM);
+   case BITS7(0,1,0,1,0,0,0):   /* STR */
+   case BITS7(0,1,0,1,1,0,0): { /* LDR */
+      /* ------------- LDR Rd, [Rn, Rm] ------------- */
+      /* ------------- STR Rd, [Rn, Rm] ------------- */
+      /* LDR/STR Rd, [Rn + Rm] */
+      UInt    rD   = INSN0(2,0);
+      UInt    rN   = INSN0(5,3);
+      UInt    rM   = INSN0(8,6);
+      UInt    isLD = INSN0(11,11);
+
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+
+      IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
+      put_ITSTATE(old_itstate); // backout
+      if (isLD) {
+         putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID);

       } else {
       } else {

-         // FUITOD
-         putDReg(dD, unop(Iop_I32UtoF64,
-                          unop(Iop_ReinterpF32asI32, getFReg(fM))),
-                 condT);
-         DIP("fuitod%s d%u, s%u\n", nCC(INSN_COND), dD, fM);
+         storeLE(ea, getIRegT(rD));

       }
       }

+      put_ITSTATE(new_itstate); // restore
+
+      DIP("%s r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);

       goto decode_success;
    }
 
       goto decode_success;
    }
 

-   // FTO{S,U}ID fD, dM
-   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
-       && BITS4(1,0,1,1) == INSN(11,8)
-       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,1,1))) {
-      UInt   bD    = (insn >> 22) & 1;
-      UInt   fD    = (INSN(15,12) << 1) | bD;
-      UInt   dM    = INSN(3,0);
-      UInt   bZ    = (insn >> 7) & 1;
-      UInt   syned = (insn >> 16) & 1;
-      IRTemp rmode = newTemp(Ity_I32);
-      assign(rmode, bZ ? mkU32(Irrm_ZERO)
-                       : mkexpr(mk_get_IR_rounding_mode()));
-      if (syned) {
-         // FTOSID
-         putFReg(fD, unop(Iop_ReinterpI32asF32,
-                          binop(Iop_F64toI32S, mkexpr(rmode),
-                                getDReg(dM))),
-                 condT);
-         DIP("ftosi%sd%s s%u, d%u\n", bZ ? "z" : "",
-             nCC(INSN_COND), fD, dM);
+   case BITS7(0,1,0,1,0,0,1):
+   case BITS7(0,1,0,1,1,0,1): {
+      /* ------------- LDRH Rd, [Rn, Rm] ------------- */
+      /* ------------- STRH Rd, [Rn, Rm] ------------- */
+      /* LDRH/STRH Rd, [Rn + Rm] */
+      UInt    rD   = INSN0(2,0);
+      UInt    rN   = INSN0(5,3);
+      UInt    rM   = INSN0(8,6);
+      UInt    isLD = INSN0(11,11);
+
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+
+      IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
+      put_ITSTATE(old_itstate); // backout
+      if (isLD) {
+         putIRegT(rD, unop(Iop_16Uto32, loadLE(Ity_I16, ea)),
+                      IRTemp_INVALID);

       } else {
       } else {

-         // FTOUID
-         putFReg(fD, unop(Iop_ReinterpI32asF32,
-                          binop(Iop_F64toI32U, mkexpr(rmode),
-                                getDReg(dM))),
-                 condT);
-         DIP("ftoui%sd%s s%u, d%u\n", bZ ? "z" : "",
-             nCC(INSN_COND), fD, dM);
+         storeLE( ea, unop(Iop_32to16, getIRegT(rD)) );

       }
       }

+      put_ITSTATE(new_itstate); // restore
+
+      DIP("%sh r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);

       goto decode_success;
    }
 
       goto decode_success;
    }
 

-   /* ----------------------------------------------------------- */
-   /* -- VFP instructions -- single precision                  -- */
-   /* ----------------------------------------------------------- */
-
-   /* --------------------- fldms, fstms --------------------- */
-   /*
-                                 31   27   23   19 15 11   7   0
-                                         P UDWL
-      C4-98, C5-26   1  FSTMD    cond 1100 1x00 Rn Fd 1010 offset
-      C4-98, C5-28   2  FSTMDIA  cond 1100 1x10 Rn Fd 1010 offset
-      C4-98, C5-30   3  FSTMDDB  cond 1101 0x10 Rn Fd 1010 offset
+   case BITS7(0,1,0,1,1,1,1): {
+      /* ------------- LDRSH Rd, [Rn, Rm] ------------- */
+      /* LDRSH Rd, [Rn + Rm] */
+      UInt    rD = INSN0(2,0);
+      UInt    rN = INSN0(5,3);
+      UInt    rM = INSN0(8,6);

 
 

-      C4-40, C5-26   1  FLDMD    cond 1100 1x01 Rn Fd 1010 offset
-      C4-40, C5-26   2  FLDMIAD  cond 1100 1x11 Rn Fd 1010 offset
-      C4-40, C5-26   3  FLDMDBD  cond 1101 0x11 Rn Fd 1010 offset
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond

 
 

-      Regs transferred: F(Fd:D) .. F(Fd:d + offset)
-      offset must not imply a reg > 15
-      IA/DB: Rn is changed by (4 x # regs transferred)
+      IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
+      put_ITSTATE(old_itstate); // backout
+      putIRegT(rD, unop(Iop_16Sto32, loadLE(Ity_I16, ea)),
+                   IRTemp_INVALID);
+      put_ITSTATE(new_itstate); // restore

 
 

-      case coding:
-         1  at-Rn   (access at Rn)
-         2  ia-Rn   (access at Rn, then Rn += 4n)
-         3  db-Rn   (Rn -= 4n,     then access at Rn)
-   */
-   if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))
-       && INSN(11,8) == BITS4(1,0,1,0)) {
-      UInt bP     = (insn >> 24) & 1;
-      UInt bU     = (insn >> 23) & 1;
-      UInt bW     = (insn >> 21) & 1;
-      UInt bL     = (insn >> 20) & 1;
-      UInt bD     = (insn >> 22) & 1;
-      UInt offset = (insn >> 0) & 0xFF;
-      UInt rN     = INSN(19,16);
-      UInt fD     = (INSN(15,12) << 1) | bD;
-      UInt nRegs  = offset;
-      Int  i;
+      DIP("ldrsh r%u, [r%u, r%u]\n", rD, rN, rM);
+      goto decode_success;
+   }

 
 

-      /**/ if (bP == 0 && bU == 1 && bW == 0) {
-         vassert(0); //ATC
-         summary = 1;
-      }
-      else if (bP == 0 && bU == 1 && bW == 1) {
-         summary = 2;
-      }
-      else if (bP == 1 && bU == 0 && bW == 1) {
-         summary = 3;
-      }
-      else goto after_vfp_fldms_fstms;
+   case BITS7(0,1,0,1,0,1,1): {
+      /* ------------- LDRSB Rd, [Rn, Rm] ------------- */
+      /* LDRSB Rd, [Rn + Rm] */
+      UInt    rD = INSN0(2,0);
+      UInt    rN = INSN0(5,3);
+      UInt    rM = INSN0(8,6);

 
 

-      /* no writebacks to r15 allowed */
-      if (rN == 15 && (summary == 2 || summary == 3))
-         goto after_vfp_fldms_fstms;
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond

 
 

-      /* offset must specify at least one register */
-      if (offset < 1)
-         goto after_vfp_fldms_fstms;
+      IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
+      put_ITSTATE(old_itstate); // backout
+      putIRegT(rD, unop(Iop_8Sto32, loadLE(Ity_I8, ea)),
+                   IRTemp_INVALID);
+      put_ITSTATE(new_itstate); // restore

 
 

-      /* can't transfer regs after S31 */
-      if (fD + nRegs - 1 >= 32)
-         goto after_vfp_fldms_fstms;
+      DIP("ldrsb r%u, [r%u, r%u]\n", rD, rN, rM);
+      goto decode_success;
+   }

 
 

-      /* Now, we can't do a conditional load or store, since that very
-         likely will generate an exception.  So we have to take a side
-         exit at this point if the condition is false. */
-      if (condT != IRTemp_INVALID) {
-         mk_skip_to_next_if_cond_is_false( condT );
-         condT = IRTemp_INVALID;
+   case BITS7(0,1,0,1,0,1,0):
+   case BITS7(0,1,0,1,1,1,0): {
+      /* ------------- LDRB Rd, [Rn, Rm] ------------- */
+      /* ------------- STRB Rd, [Rn, Rm] ------------- */
+      /* LDRB/STRB Rd, [Rn + Rm] */
+      UInt    rD   = INSN0(2,0);
+      UInt    rN   = INSN0(5,3);
+      UInt    rM   = INSN0(8,6);
+      UInt    isLD = INSN0(11,11);
+
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+
+      IRExpr* ea = binop(Iop_Add32, getIRegT(rN), getIRegT(rM));
+      put_ITSTATE(old_itstate); // backout
+      if (isLD) {
+         putIRegT(rD, unop(Iop_8Uto32, loadLE(Ity_I8, ea)),
+                  IRTemp_INVALID);
+      } else {
+         storeLE( ea, unop(Iop_32to8, getIRegT(rD)) );

       }
       }

-      /* Ok, now we're unconditional.  Do the load or store. */
+      put_ITSTATE(new_itstate); // restore

 
 

-      /* get the old Rn value */
-      IRTemp rnT = newTemp(Ity_I32);
-      assign(rnT, getIReg(rN));
+      DIP("%sb r%u, [r%u, r%u]\n", isLD ? "ldr" : "str", rD, rN, rM);
+      goto decode_success;
+   }

 
 

-      /* make a new value for Rn, post-insn */
-      IRTemp rnTnew = IRTemp_INVALID;
-      if (summary == 2 || summary == 3) {
-         rnTnew = newTemp(Ity_I32);
-         assign(rnTnew, binop(summary == 2 ? Iop_Add32 : Iop_Sub32,
-                              mkexpr(rnT),
-                              mkU32(4 * nRegs)));
-      }
+   default:
+      break; /* examine the next shortest prefix */

 
 

-      /* decide on the base transfer address */
-      IRTemp taT = newTemp(Ity_I32);
-      assign(taT, summary == 3 ? mkexpr(rnTnew) : mkexpr(rnT));
+   }

 
 

-      /* update Rn if necessary -- in case 3, we're moving it down, so
-         update before any memory reference, in order to keep Memcheck
-         and V's stack-extending logic (on linux) happy */
-      if (summary == 3)
-         putIReg(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);

 
 

-      /* generate the transfers */
-      for (i = 0; i < nRegs; i++) {
-         IRExpr* addr = binop(Iop_Add32, mkexpr(taT), mkU32(4*i));
-         if (bL) {
-            putFReg(fD + i, loadLE(Ity_F32, addr), IRTemp_INVALID);
-         } else {
-            storeLE(addr, getFReg(fD + i));
-         }
-      }
+   /* ================ 16-bit 15:11 cases ================ */
+
+   switch (INSN0(15,11)) {
+
+   case BITS5(0,0,1,1,0):
+   case BITS5(0,0,1,1,1): {
+      /* ---------------- ADDS Rn, #uimm8 ---------------- */
+      /* ---------------- SUBS Rn, #uimm8 ---------------- */
+      UInt   isSub = INSN0(11,11);
+      UInt   rN    = INSN0(10,8);
+      UInt   uimm8 = INSN0(7,0);
+      IRTemp argL  = newTemp(Ity_I32);
+      IRTemp argR  = newTemp(Ity_I32);
+      assign( argL, getIRegT(rN) );
+      assign( argR, mkU32(uimm8) );
+      putIRegT( rN, binop(isSub ? Iop_Sub32 : Iop_Add32,
+                          mkexpr(argL), mkexpr(argR)), condT );
+      setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
+                      argL, argR, cond_AND_notInIT_T );
+      DIP("%s r%u, #%u\n", isSub ? "subs" : "adds", rN, uimm8);
+      goto decode_success;
+   }

 
 

-      /* update Rn if necessary -- in case 2, we're moving it up, so
-         update after any memory reference, in order to keep Memcheck
-         and V's stack-extending logic (on linux) happy */
-      if (summary == 2)
-         putIReg(rN, mkexpr(rnTnew), IRTemp_INVALID, Ijk_Boring);
+   case BITS5(1,0,1,0,0): {
+      /* ---------------- ADD rD, PC, #imm8 * 4 ---------------- */
+      /* a.k.a. ADR */
+      /* rD = align4(PC) + imm8 * 4 */
+      UInt rD   = INSN0(10,8);
+      UInt imm8 = INSN0(7,0);
+      putIRegT(rD, binop(Iop_Add32, 
+                         binop(Iop_And32, getIRegT(15), mkU32(~3U)),
+                         mkU32(imm8 * 4)),
+                   condT);
+      DIP("add r%u, pc, #%u\n", rD, imm8 * 4);
+      goto decode_success;
+   }

 
 

-      HChar* nm = bL==1 ? "ld" : "st";
-      switch (summary) {
-         case 1:  DIP("f%sms%s r%u, {s%u-s%u}\n", 
-                      nm, nCC(INSN_COND), rN, fD, fD + nRegs - 1);
-                  break;
-         case 2:  DIP("f%smias%s r%u!, {s%u-s%u}\n", 
-                      nm, nCC(INSN_COND), rN, fD, fD + nRegs - 1);
-                  break;
-         case 3:  DIP("f%smdbs%s r%u!, {s%u-s%u}\n", 
-                      nm, nCC(INSN_COND), rN, fD, fD + nRegs - 1);
-                  break;
-         default: vassert(0);
-      }
+   case BITS5(1,0,1,0,1): {
+      /* ---------------- ADD rD, SP, #imm8 * 4 ---------------- */
+      UInt rD   = INSN0(10,8);
+      UInt imm8 = INSN0(7,0);
+      putIRegT(rD, binop(Iop_Add32, getIRegT(13), mkU32(imm8 * 4)),
+                   condT);
+      DIP("add r%u, r13, #%u\n", rD, imm8 * 4);
+      goto decode_success;
+   }

 
 

+   case BITS5(0,0,1,0,1): {
+      /* ---------------- CMP Rn, #uimm8 ---------------- */
+      UInt   rN    = INSN0(10,8);
+      UInt   uimm8 = INSN0(7,0);
+      IRTemp argL  = newTemp(Ity_I32);
+      IRTemp argR  = newTemp(Ity_I32);
+      assign( argL, getIRegT(rN) );
+      assign( argR, mkU32(uimm8) );
+      /* Update flags regardless of whether in an IT block or not. */
+      setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT );
+      DIP("cmp r%u, #%u\n", rN, uimm8);

       goto decode_success;
       goto decode_success;

-      /* FIXME alignment constraints? */

    }
 
    }
 

-  after_vfp_fldms_fstms:
+   case BITS5(0,0,1,0,0): {
+      /* -------------- (T1) MOVS Rn, #uimm8 -------------- */
+      UInt   rD    = INSN0(10,8);
+      UInt   uimm8 = INSN0(7,0);
+      IRTemp oldV  = newTemp(Ity_I32);
+      IRTemp oldC  = newTemp(Ity_I32);
+      IRTemp res   = newTemp(Ity_I32);
+      assign( oldV, mk_armg_calculate_flag_v() );
+      assign( oldC, mk_armg_calculate_flag_c() );
+      assign( res, mkU32(uimm8) );
+      putIRegT(rD, mkexpr(res), condT);
+      setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                         cond_AND_notInIT_T );
+      DIP("movs r%u, #%u\n", rD, uimm8);
+      goto decode_success;
+   }

 
 

-   /* --------------------- fmsr, fmrs --------------------- */
-   if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS4(0,0,0,0) == INSN(3,0)
-       && BITS4(0,0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
-      UInt rD  = INSN(15,12);
-      UInt b7  = (insn >> 7) & 1;
-      UInt fN  = (INSN(19,16) << 1) | b7;
-      UInt b20 = (insn >> 20) & 1;
-      if (rD == 15) {
-         /* fall through */
-         /* Let's assume that no sane person would want to do
-            floating-point transfers to or from the program counter,
-            and simply decline to decode the instruction.  The ARM ARM
-            doesn't seem to explicitly disallow this case, though. */
+   case BITS5(0,1,0,0,1): {
+      /* ------------- LDR Rd, [PC, #imm8 * 4] ------------- */
+      /* LDR Rd, [align4(PC) + imm8 * 4] */
+      UInt   rD   = INSN0(10,8);
+      UInt   imm8 = INSN0(7,0);
+      IRTemp ea   = newTemp(Ity_I32);
+
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+
+      assign(ea, binop(Iop_Add32, 
+                       binop(Iop_And32, getIRegT(15), mkU32(~3U)),
+                       mkU32(imm8 * 4)));
+      put_ITSTATE(old_itstate); // backout
+      putIRegT(rD, loadLE(Ity_I32, mkexpr(ea)),
+                   IRTemp_INVALID);
+      put_ITSTATE(new_itstate); // restore
+
+      DIP("ldr r%u, [pc, #%u]\n", rD, imm8 * 4);
+      goto decode_success;
+   }
+
+   case BITS5(0,1,1,0,0):   /* STR */
+   case BITS5(0,1,1,0,1): { /* LDR */
+      /* ------------- LDR Rd, [Rn, #imm5 * 4] ------------- */
+      /* ------------- STR Rd, [Rn, #imm5 * 4] ------------- */
+      /* LDR/STR Rd, [Rn + imm5 * 4] */
+      UInt    rD   = INSN0(2,0);
+      UInt    rN   = INSN0(5,3);
+      UInt    imm5 = INSN0(10,6);
+      UInt    isLD = INSN0(11,11);
+
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+
+      IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5 * 4));
+      put_ITSTATE(old_itstate); // backout
+      if (isLD) {
+         putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID);

       } else {
       } else {

-         if (b20) {
-            putIReg(rD, unop(Iop_ReinterpF32asI32, getFReg(fN)),
-                        condT, Ijk_Boring);
-            DIP("fmrs%s r%u, s%u\n", nCC(INSN_COND), rD, fN);
-         } else {
-            putFReg(fN, unop(Iop_ReinterpI32asF32, getIReg(rD)), condT);
-            DIP("fmsr%s s%u, r%u\n", nCC(INSN_COND), fN, rD);
-         }
-         goto decode_success;
+         storeLE( ea, getIRegT(rD) );

       }
       }

-      /* fall through */
+      put_ITSTATE(new_itstate); // restore
+
+      DIP("%s r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 4);
+      goto decode_success;

    }
 
    }
 

-   /* --------------------- f{ld,st}s --------------------- */
-   // FLDS, FSTS
-   if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,1,0))
-       && BITS4(1,0,1,0) == INSN(11,8)) {
-      UInt bD     = (insn >> 22) & 1;
-      UInt fD     = (INSN(15,12) << 1) | bD;
-      UInt rN     = INSN(19,16);
-      UInt offset = (insn & 0xFF) << 2;
-      UInt bU     = (insn >> 23) & 1; /* 1: +offset  0: -offset */
-      UInt bL     = (insn >> 20) & 1; /* 1: load  0: store */
-      /* make unconditional */
-      if (condT != IRTemp_INVALID) {
-         mk_skip_to_next_if_cond_is_false( condT );
-         condT = IRTemp_INVALID;
+   case BITS5(1,0,0,0,0):   /* STRH */
+   case BITS5(1,0,0,0,1): { /* LDRH */
+      /* ------------- LDRH Rd, [Rn, #imm5 * 2] ------------- */
+      /* ------------- STRH Rd, [Rn, #imm5 * 2] ------------- */
+      /* LDRH/STRH Rd, [Rn + imm5 * 2] */
+      UInt    rD   = INSN0(2,0);
+      UInt    rN   = INSN0(5,3);
+      UInt    imm5 = INSN0(10,6);
+      UInt    isLD = INSN0(11,11);
+
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+
+      IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5 * 2));
+      put_ITSTATE(old_itstate); // backout
+      if (isLD) {
+         putIRegT(rD, unop(Iop_16Uto32, loadLE(Ity_I16, ea)),
+                  IRTemp_INVALID);
+      } else {
+         storeLE( ea, unop(Iop_32to16, getIRegT(rD)) );

       }
       }

-      IRTemp ea = newTemp(Ity_I32);
-      assign(ea, binop(bU ? Iop_Add32 : Iop_Sub32,
-                       getIReg(rN), mkU32(offset)));
-      if (bL) {
-         putFReg(fD, loadLE(Ity_F32,mkexpr(ea)), IRTemp_INVALID);
+      put_ITSTATE(new_itstate); // restore
+
+      DIP("%sh r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5 * 2);
+      goto decode_success;
+   }
+
+   case BITS5(0,1,1,1,0):   /* STRB */
+   case BITS5(0,1,1,1,1): { /* LDRB */
+      /* ------------- LDRB Rd, [Rn, #imm5] ------------- */
+      /* ------------- STRB Rd, [Rn, #imm5] ------------- */
+      /* LDRB/STRB Rd, [Rn + imm5] */
+      UInt    rD   = INSN0(2,0);
+      UInt    rN   = INSN0(5,3);
+      UInt    imm5 = INSN0(10,6);
+      UInt    isLD = INSN0(11,11);
+
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+
+      IRExpr* ea = binop(Iop_Add32, getIRegT(rN), mkU32(imm5));
+      put_ITSTATE(old_itstate); // backout
+      if (isLD) {
+         putIRegT(rD, unop(Iop_8Uto32, loadLE(Ity_I8, ea)),
+                  IRTemp_INVALID);

       } else {
       } else {

-         storeLE(mkexpr(ea), getFReg(fD));
+         storeLE( ea, unop(Iop_32to8, getIRegT(rD)) );

       }
       }

-      DIP("f%ss%s s%u, [r%u, %c#%u]\n",
-          bL ? "ld" : "st", nCC(INSN_COND), fD, rN,
-          bU ? '+' : '-', offset);
+      put_ITSTATE(new_itstate); // restore
+
+      DIP("%sb r%u, [r%u, #%u]\n", isLD ? "ldr" : "str", rD, rN, imm5);

       goto decode_success;
    }
 
       goto decode_success;
    }
 

-   /* --------------------- dp insns (F) --------------------- */
-   if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(0,0,0,1))) {
-      UInt    bM  = (insn >> 5) & 1;
-      UInt    bD  = (insn >> 22) & 1;
-      UInt    bN  = (insn >> 7) & 1;
-      UInt    fM  = (INSN(3,0) << 1) | bM;   /* argR */
-      UInt    fD  = (INSN(15,12) << 1) | bD; /* dst/acc */
-      UInt    fN  = (INSN(19,16) << 1) | bN; /* argL */
-      UInt    bP  = (insn >> 23) & 1;
-      UInt    bQ  = (insn >> 21) & 1;
-      UInt    bR  = (insn >> 20) & 1;
-      UInt    bS  = (insn >> 6) & 1;
-      UInt    opc = (bP << 3) | (bQ << 2) | (bR << 1) | bS;
-      IRExpr* rm  = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
-      switch (opc) {
-         case BITS4(0,0,0,0): /* MAC: d + n * m */
-            putFReg(fD, triop(Iop_AddF32, rm,
-                              getFReg(fD),
-                              triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
-                        condT);
-            DIP("fmacs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
-            goto decode_success;
-         case BITS4(0,0,0,1): /* NMAC: d - n * m */
-            putFReg(fD, triop(Iop_SubF32, rm,
-                              getFReg(fD),
-                              triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
-                        condT);
-            DIP("fnmacs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
-            goto decode_success;
-         case BITS4(0,0,1,0): /* MSC: - d + n * m */
-            putFReg(fD, triop(Iop_AddF32, rm,
-                              unop(Iop_NegF32, getFReg(fD)),
-                              triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM))),
-                        condT);
-            DIP("fmscs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
-            goto decode_success;
-         case BITS4(0,0,1,1): /* NMSC: - d - n * m */
-            break; //ATC
-         case BITS4(0,1,0,0): /* MUL: n * m */
-            putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
-                        condT);
-            DIP("fmuls%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
-            goto decode_success;
-         case BITS4(0,1,0,1): /* NMUL: - n * m */
-            putFReg(fD, unop(Iop_NegF32,
-                             triop(Iop_MulF32, rm, getFReg(fN),
-                                                   getFReg(fM))),
-                    condT);
-            DIP("fnmuls%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
-            goto decode_success;
-         case BITS4(0,1,1,0): /* ADD: n + m */
-            putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
-                        condT);
-            DIP("fadds%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
-            goto decode_success;
-         case BITS4(0,1,1,1): /* SUB: n - m */
-            putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
-                        condT);
-            DIP("fsubs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
-            goto decode_success;
-         case BITS4(1,0,0,0): /* DIV: n / m */
-            putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
-                        condT);
-            DIP("fdivs%s s%u, s%u, s%u\n", nCC(INSN_COND), fD, fN, fM);
-            goto decode_success;
-         default:
+   case BITS5(1,0,0,1,0):   /* STR */
+   case BITS5(1,0,0,1,1): { /* LDR */
+      /* ------------- LDR Rd, [SP, #imm8 * 4] ------------- */
+      /* ------------- STR Rd, [SP, #imm8 * 4] ------------- */
+      /* LDR/STR Rd, [SP + imm8 * 4] */
+      UInt rD    = INSN0(10,8);
+      UInt imm8  = INSN0(7,0);
+      UInt isLD  = INSN0(11,11);
+
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+
+      IRExpr* ea = binop(Iop_Add32, getIRegT(13), mkU32(imm8 * 4));
+      put_ITSTATE(old_itstate); // backout
+      if (isLD) {
+         putIRegT(rD, loadLE(Ity_I32, ea), IRTemp_INVALID);
+      } else {
+         storeLE(ea, getIRegT(rD));
+      }
+      put_ITSTATE(new_itstate); // restore
+
+      DIP("%s r%u, [sp, #%u]\n", isLD ? "ldr" : "str", rD, imm8 * 4);
+      goto decode_success;
+   }
+
+   case BITS5(1,1,0,0,1): {
+      /* ------------- LDMIA Rn!, {reglist} ------------- */
+      Int i, nRegs = 0;
+      UInt rN   = INSN0(10,8);
+      UInt list = INSN0(7,0);
+      /* Empty lists aren't allowed. */
+      if (list != 0) {
+         mk_skip_over_T16_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         put_ITSTATE(old_itstate);
+         // now uncond
+
+         IRTemp oldRn = newTemp(Ity_I32);
+         IRTemp base  = newTemp(Ity_I32);
+         assign(oldRn, getIRegT(rN));
+         assign(base, binop(Iop_And32, mkexpr(oldRn), mkU32(~3U)));
+         for (i = 0; i < 8; i++) {
+            if (0 == (list & (1 << i)))
+               continue;
+            nRegs++;
+            putIRegT(
+               i, loadLE(Ity_I32,
+                         binop(Iop_Add32, mkexpr(base),
+                                          mkU32(nRegs * 4 - 4))),
+               IRTemp_INVALID
+            );
+         }
+         /* Only do the writeback for rN if it isn't in the list of
+            registers to be transferred. */
+         if (0 == (list & (1 << rN))) {
+            putIRegT(rN,
+                     binop(Iop_Add32, mkexpr(oldRn),
+                                      mkU32(nRegs * 4)),
+                     IRTemp_INVALID
+            );
+         }
+
+         /* Reinstate the ITSTATE update. */
+         put_ITSTATE(new_itstate);
+
+         DIP("ldmia r%u!, {0x%04x}\n", rN, list);
+         goto decode_success;
+      }
+      break;
+   }
+
+   case BITS5(1,1,0,0,0): {
+      /* ------------- STMIA Rn!, {reglist} ------------- */
+      Int i, nRegs = 0;
+      UInt rN   = INSN0(10,8);
+      UInt list = INSN0(7,0);
+      /* Empty lists aren't allowed.  Also, if rN is in the list then
+         it must be the lowest numbered register in the list. */
+      Bool valid = list != 0;
+      if (valid && 0 != (list & (1 << rN))) {
+         for (i = 0; i < rN; i++) {
+            if (0 != (list & (1 << i)))
+               valid = False;
+         }
+      }
+      if (valid) {
+         mk_skip_over_T16_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         put_ITSTATE(old_itstate);
+         // now uncond
+
+         IRTemp oldRn = newTemp(Ity_I32);
+         IRTemp base = newTemp(Ity_I32);
+         assign(oldRn, getIRegT(rN));
+         assign(base, binop(Iop_And32, mkexpr(oldRn), mkU32(~3U)));
+         for (i = 0; i < 8; i++) {
+            if (0 == (list & (1 << i)))
+               continue;
+            nRegs++;
+            storeLE( binop(Iop_Add32, mkexpr(base), mkU32(nRegs * 4 - 4)),
+                     getIRegT(i) );
+         }
+         /* Always do the writeback. */
+         putIRegT(rN,
+                  binop(Iop_Add32, mkexpr(oldRn),
+                                   mkU32(nRegs * 4)),
+                  IRTemp_INVALID);
+
+         /* Reinstate the ITSTATE update. */
+         put_ITSTATE(new_itstate);
+
+         DIP("stmia r%u!, {0x%04x}\n", rN, list);
+         goto decode_success;
+      }
+      break;
+   }
+
+   case BITS5(0,0,0,0,0):   /* LSLS */
+   case BITS5(0,0,0,0,1):   /* LSRS */
+   case BITS5(0,0,0,1,0): { /* ASRS */
+      /* ---------------- LSLS Rd, Rm, #imm5 ---------------- */
+      /* ---------------- LSRS Rd, Rm, #imm5 ---------------- */
+      /* ---------------- ASRS Rd, Rm, #imm5 ---------------- */
+      UInt   rD   = INSN0(2,0);
+      UInt   rM   = INSN0(5,3);
+      UInt   imm5 = INSN0(10,6);
+      IRTemp res  = newTemp(Ity_I32);
+      IRTemp resC = newTemp(Ity_I32);
+      IRTemp rMt  = newTemp(Ity_I32);
+      IRTemp oldV = newTemp(Ity_I32);
+      HChar* wot  = "???";
+      assign(rMt, getIRegT(rM));
+      assign(oldV, mk_armg_calculate_flag_v());
+      /* Looks like INSN0(12,11) are the standard 'how' encoding.
+         Could compactify if the ROR case later appears. */
+      switch (INSN0(15,11)) {
+         case BITS5(0,0,0,0,0):
+            compute_result_and_C_after_LSL_by_imm5(
+               dis_buf, &res, &resC, rMt, imm5, rM
+            );
+            wot = "lsl";
+            break;
+         case BITS5(0,0,0,0,1):
+            compute_result_and_C_after_LSR_by_imm5(
+               dis_buf, &res, &resC, rMt, imm5, rM
+            );
+            wot = "lsr";
+            break;
+         case BITS5(0,0,0,1,0):
+            compute_result_and_C_after_ASR_by_imm5(
+               dis_buf, &res, &resC, rMt, imm5, rM
+            );
+            wot = "asr";

             break;
             break;

+         default:
+            /*NOTREACHED*/vassert(0);

       }
       }

+      // not safe to read guest state after this point
+      putIRegT(rD, mkexpr(res), condT);
+      setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, resC, oldV,
+                         cond_AND_notInIT_T );
+      /* ignore buf and roll our own output */
+      DIP("%ss r%u, r%u, #%u\n", wot, rD, rM, imm5);
+      goto decode_success;

    }
 
    }
 

-   /* --------------------- compares (S) --------------------- */
-   /*          31   27   23   19   15 11   7    3
-                 28   24   20   16 12    8    4    0 
-      FCMPS    cond 1110 1D11 0100 Fd 1010 01M0 Fm
-      FCMPES   cond 1110 1D11 0100 Fd 1010 11M0 Fm
-      FCMPZS   cond 1110 1D11 0101 Fd 1010 0100 0000
-      FCMPZED  cond 1110 1D11 0101 Fd 1010 1100 0000
-                                 Z         N
+   case BITS5(1,1,1,0,0): {
+      /* ---------------- B #simm11 ---------------- */
+      Int  simm11 = INSN0(10,0);
+           simm11 = (simm11 << 21) >> 20;
+      UInt dst    = simm11 + guest_R15_curr_instr_notENC + 4;
+      /* Only allowed outside or last-in IT block; SIGILL if not so. */
+      gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+      // and skip this insn if not selected; being cleverer is too
+      // difficult
+      mk_skip_over_T16_if_cond_is_false(condT);
+      condT = IRTemp_INVALID;
+      // now uncond
+      irsb->next     = mkU32( dst | 1 /*CPSR.T*/ );
+      irsb->jumpkind = Ijk_Boring;
+      dres.whatNext  = Dis_StopHere;
+      DIP("b 0x%x\n", dst);
+      goto decode_success;
+   }

 
 

-      Z=0 Compare Fd:D vs Fm:M     and set FPSCR 31:28 accordingly
-      Z=1 Compare Fd:D vs zero
+   default:
+      break; /* examine the next shortest prefix */

 
 

-      N=1 generates Invalid Operation exn if either arg is any kind of NaN
-      N=0 generates Invalid Operation exn if either arg is a signalling NaN
-      (Not that we pay any attention to N here)
-   */
-   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
-      UInt bZ = (insn >> 16) & 1;
-      UInt bN = (insn >> 7) & 1;
-      UInt bD = (insn >> 22) & 1;
-      UInt bM = (insn >> 5) & 1;
-      UInt fD = (INSN(15,12) << 1) | bD;
-      UInt fM = (INSN(3,0) << 1) | bM;
-      if (bZ && (INSN(3,0) != 0 || (INSN(7,4) & 3) != 0)) {
-         /* does not decode; fall through */
-      } else {
-         IRTemp argL = newTemp(Ity_F64);
-         IRTemp argR = newTemp(Ity_F64);
-         IRTemp irRes = newTemp(Ity_I32);
+   }

 
 

-         assign(argL, unop(Iop_F32toF64, getFReg(fD)));
-         assign(argR, bZ ? IRExpr_Const(IRConst_F64i(0))
-                         : unop(Iop_F32toF64, getFReg(fM)));
-         assign(irRes, binop(Iop_CmpF64, mkexpr(argL), mkexpr(argR)));

 
 

-         IRTemp nzcv     = IRTemp_INVALID;
-         IRTemp oldFPSCR = newTemp(Ity_I32);
-         IRTemp newFPSCR = newTemp(Ity_I32);
+   /* ================ 16-bit 15:12 cases ================ */
+
+   switch (INSN0(15,12)) {
+
+   case BITS4(1,1,0,1): {
+      /* ---------------- Bcond #simm8 ---------------- */
+      UInt cond  = INSN0(11,8);
+      Int  simm8 = INSN0(7,0);
+           simm8 = (simm8 << 24) >> 23;
+      UInt dst   = simm8 + guest_R15_curr_instr_notENC + 4;
+      if (cond != ARMCondAL && cond != ARMCondNV) {
+         /* Not allowed in an IT block; SIGILL if so. */
+         gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+
+         IRTemp kondT = newTemp(Ity_I32);
+         assign( kondT, mk_armg_calculate_condition(cond) );
+         stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(kondT)),
+                            Ijk_Boring,
+                            IRConst_U32(dst | 1/*CPSR.T*/) ));
+         irsb->next = mkU32( (guest_R15_curr_instr_notENC + 2) 
+                             | 1 /*CPSR.T*/ );
+         irsb->jumpkind = Ijk_Boring;
+         dres.whatNext  = Dis_StopHere;
+         DIP("b%s 0x%x\n", nCC(cond), dst);
+         goto decode_success;
+      }
+      break;
+   }

 
 

-         /* This is where the fun starts.  We have to convert 'irRes'
-            from an IR-convention return result (IRCmpF64Result) to an
-            ARM-encoded (N,Z,C,V) group.  The final result is in the
-            bottom 4 bits of 'nzcv'. */
-         /* Map compare result from IR to ARM(nzcv) */
-         /*
-            FP cmp result | IR   | ARM(nzcv)
-            --------------------------------
-            UN              0x45   0011
-            LT              0x01   1000
-            GT              0x00   0010
-            EQ              0x40   0110
-         */
-         nzcv = mk_convert_IRCmpF64Result_to_NZCV(irRes);
+   default:
+      break; /* hmm, nothing matched */

 
 

-         /* And update FPSCR accordingly */
-         assign(oldFPSCR, IRExpr_Get(OFFB_FPSCR, Ity_I32));
-         assign(newFPSCR, 
-                binop(Iop_Or32, 
-                      binop(Iop_And32, mkexpr(oldFPSCR), mkU32(0x0FFFFFFF)),
-                      binop(Iop_Shl32, mkexpr(nzcv), mkU8(28))));
+   }

 
 

-         putMiscReg32(OFFB_FPSCR, mkexpr(newFPSCR), condT);
+   /* ================ 16-bit misc cases ================ */

 
 

-         if (bZ) {
-            DIP("fcmpz%ss%s s%u\n", bN ? "e" : "", nCC(INSN_COND), fD);
+   /* ------ NOP ------ */
+   if (INSN0(15,0) == 0xBF00) {
+      DIP("nop");
+      goto decode_success;
+   }
+
+   /* ----------------------------------------------------------- */
+   /* --                                                       -- */
+   /* -- Thumb 32-bit integer instructions                     -- */
+   /* --                                                       -- */
+   /* ----------------------------------------------------------- */
+
+#  define INSN1(_bMax,_bMin)  SLICE_UInt(((UInt)insn1), (_bMax), (_bMin))
+
+   /* second 16 bits of the instruction, if any */
+   UShort insn1 = getUShortLittleEndianly( guest_instr+2 );
+
+   anOp   = Iop_INVALID; /* paranoia */
+   anOpNm = NULL;        /* paranoia */
+
+   /* Change result defaults to suit 32-bit insns. */
+   vassert(dres.whatNext   == Dis_Continue);
+   vassert(dres.len        == 2);
+   vassert(dres.continueAt == 0);
+   dres.len = 4;
+
+   /* ---------------- BL/BLX simm26 ---------------- */
+   if (BITS5(1,1,1,1,0) == INSN0(15,11) && BITS2(1,1) == INSN1(15,14)) {
+      UInt isBL = INSN1(12,12);
+      UInt bS   = INSN0(10,10);
+      UInt bJ1  = INSN1(13,13);
+      UInt bJ2  = INSN1(11,11);
+      UInt bI1  = 1 ^ (bJ1 ^ bS);
+      UInt bI2  = 1 ^ (bJ2 ^ bS);
+      Int simm25
+         =   (bS          << (1 + 1 + 10 + 11 + 1))
+           | (bI1         << (1 + 10 + 11 + 1))
+           | (bI2         << (10 + 11 + 1))
+           | (INSN0(9,0)  << (11 + 1))
+           | (INSN1(10,0) << 1);
+      simm25 = (simm25 << 7) >> 7;
+
+      vassert(0 == (guest_R15_curr_instr_notENC & 1));
+      UInt dst = simm25 + guest_R15_curr_instr_notENC + 4;
+
+      /* One further validity case to check: in the case of BLX
+         (not-BL), that insn1[0] must be zero. */
+      Bool valid = True;
+      if (isBL == 0 && INSN1(0,0) == 1) valid = False;
+      if (valid) {
+         /* Only allowed outside or last-in IT block; SIGILL if not so. */
+         gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+         // and skip this insn if not selected; being cleverer is too
+         // difficult
+         mk_skip_over_T32_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         // now uncond
+
+         /* We're returning to Thumb code, hence "| 1" */
+         putIRegT( 14, mkU32( (guest_R15_curr_instr_notENC + 4) | 1 ),
+                   IRTemp_INVALID);
+         if (isBL) {
+            /* BL: unconditional T -> T call */
+            /* we're calling Thumb code, hence "| 1" */
+            irsb->next = mkU32( dst | 1 );
+            DIP("bl 0x%x (stay in Thumb mode)\n", dst);

          } else {
          } else {

-            DIP("fcmp%ss%s s%u, s%u\n", bN ? "e" : "",
-                nCC(INSN_COND), fD, fM);
+            /* BLX: unconditional T -> A call */
+            /* we're calling ARM code, hence "& 3" to align to a
+               valid ARM insn address */
+            irsb->next = mkU32( dst & ~3 );
+            DIP("blx 0x%x (switch to ARM mode)\n", dst & ~3);

          }
          }

+         irsb->jumpkind = Ijk_Call;
+         dres.whatNext = Dis_StopHere;

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */
-   }  
+   }
+
+   /* ---------------- {LD,ST}M{IA,DB} ---------------- */
+   if (0x3a2 == INSN0(15,6) // {LD,ST}MIA
+       || 0x3a4 == INSN0(15,6)) { // {LD,ST}MDB
+      UInt bW      = INSN0(5,5); /* writeback Rn ? */
+      UInt bL      = INSN0(4,4);
+      UInt rN      = INSN0(3,0);
+      UInt bP      = INSN1(15,15); /* reglist entry for r15 */
+      UInt bM      = INSN1(14,14); /* reglist entry for r14 */
+      UInt rLmost  = INSN1(12,0);  /* reglist entry for r0 .. 12 */
+      UInt rL13    = INSN1(13,13); /* must be zero */
+      UInt regList = 0;
+      Bool valid   = True;
+
+      UInt bINC    = 1;
+      UInt bBEFORE = 0;
+      if (INSN0(15,6) == 0x3a4) {
+         bINC    = 0;
+         bBEFORE = 1;
+      }
+
+      /* detect statically invalid cases, and construct the final
+         reglist */
+      if (rL13 == 1)
+         valid = False;
+
+      if (bL == 1) {
+         regList = (bP << 15) | (bM << 14) | rLmost;
+         if (rN == 15)                       valid = False;
+         if (popcount32(regList) < 2)        valid = False;
+         if (bP == 1 && bM == 1)             valid = False;
+         if (bW == 1 && (regList & (1<<rN))) valid = False;
+      } else {
+         regList = (bM << 14) | rLmost;
+         if (bP == 1)                        valid = False;
+         if (rN == 15)                       valid = False;
+         if (popcount32(regList) < 2)        valid = False;
+         if (bW == 1 && (regList & (1<<rN))) valid = False;
+         if (regList & (1<<rN)) {
+            UInt i;
+            /* if Rn is in the list, then it must be the
+               lowest numbered entry */
+            for (i = 0; i < rN; i++) {
+               if (regList & (1<<i))
+                  valid = False;
+            }
+         }
+      }
+
+      if (valid) {
+         if (bL == 1 && bP == 1) {
+            // We'll be writing the PC.  Hence:
+            /* Only allowed outside or last-in IT block; SIGILL if not so. */
+            gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+         }
+
+         /* Go uncond: */
+         mk_skip_over_T32_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         // now uncond
+
+         /* Generate the IR.  This might generate a write to R15, */
+         mk_ldm_stm(False/*!arm*/, rN, bINC, bBEFORE, bW, bL, regList);
+
+         if (bL == 1 && (regList & (1<<15))) {
+            // If we wrote to R15, we have an interworking return to
+            // deal with.
+            irsb->next     = llGetIReg(15);
+            irsb->jumpkind = Ijk_Ret;
+            dres.whatNext  = Dis_StopHere;
+         }
+
+         DIP("%sm%c%c r%u%s, {0x%04x}\n",
+              bL == 1 ? "ld" : "st", bINC ? 'i' : 'd', bBEFORE ? 'b' : 'a',
+              rN, bW ? "!" : "", regList);

 
 

-   /* --------------------- unary (S) --------------------- */
-   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
-      UInt bD = (insn >> 22) & 1;
-      UInt bM = (insn >> 5) & 1;
-      UInt fD  = (INSN(15,12) << 1) | bD;
-      UInt fM  = (INSN(3,0) << 1) | bM;
-      UInt b16 = (insn >> 16) & 1;
-      UInt b7  = (insn >> 7) & 1;
-      /**/ if (b16 == 0 && b7 == 0) {
-         // FCPYS
-         putFReg(fD, getFReg(fM), condT);
-         DIP("fcpys%s s%u, s%u\n", nCC(INSN_COND), fD, fM);

          goto decode_success;
       }
          goto decode_success;
       }

-      else if (b16 == 0 && b7 == 1) {
-         // FABSS
-         putFReg(fD, unop(Iop_AbsF32, getFReg(fM)), condT);
-         DIP("fabss%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
+   }
+
+   /* -------------- (T3) ADD{S}.W Rd, Rn, #constT -------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && INSN0(9,5) == BITS5(0,1,0,0,0)
+       && INSN1(15,15) == 0) {
+      UInt bS = INSN0(4,4);
+      UInt rN = INSN0(3,0);
+      UInt rD = INSN1(11,8);
+      Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
+      /* but allow "add.w reg, sp, #constT" */ 
+      if (!valid && rN == 13)
+         valid = True;
+      if (valid) {
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         IRTemp res   = newTemp(Ity_I32);
+         UInt   imm32 = thumbExpandImm_from_I0_I1(NULL, insn0, insn1);
+         assign(argL, getIRegT(rN));
+         assign(argR, mkU32(imm32));
+         assign(res,  binop(Iop_Add32, mkexpr(argL), mkexpr(argR)));
+         putIRegT(rD, mkexpr(res), condT);
+         if (bS == 1)
+            setFlags_D1_D2( ARMG_CC_OP_ADD, argL, argR, condT );
+         DIP("add%s.w r%u, r%u, #%u\n",
+             bS == 1 ? "s" : "", rD, rN, imm32);

          goto decode_success;
       }
          goto decode_success;
       }

-      else if (b16 == 1 && b7 == 0) {
-         // FNEGS
-         putFReg(fD, unop(Iop_NegF32, getFReg(fM)), condT);
-         DIP("fnegs%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
+   }
+
+   /* ---------------- (T2) CMP.W Rn, #constT ---------------- */
+   /* ---------------- (T2) CMN.W Rn, #constT ---------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && (   INSN0(9,4) == BITS6(0,1,1,0,1,1)  // CMP
+           || INSN0(9,4) == BITS6(0,1,0,0,0,1)) // CMN
+       && INSN1(15,15) == 0
+       && INSN1(11,8) == BITS4(1,1,1,1)) {
+      UInt rN = INSN0(3,0);
+      if (rN != 15) {
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         Bool   isCMN = INSN0(9,4) == BITS6(0,1,0,0,0,1);
+         UInt   imm32 = thumbExpandImm_from_I0_I1(NULL, insn0, insn1);
+         assign(argL, getIRegT(rN));
+         assign(argR, mkU32(imm32));
+         setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB,
+                         argL, argR, condT );
+         DIP("%s.w r%u, #%u\n", isCMN ? "cmn" : "cmp", rN, imm32);

          goto decode_success;
       }
          goto decode_success;
       }

-      else if (b16 == 1 && b7 == 1) {
-         // FSQRTS
-         IRExpr* rm = get_FAKE_roundingmode(); /* XXXROUNDINGFIXME */
-         putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT);
-         DIP("fsqrts%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
+   }
+
+   /* -------------- (T1) TST.W Rn, #constT -------------- */
+   /* -------------- (T1) TEQ.W Rn, #constT -------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && (   INSN0(9,4) == BITS6(0,0,0,0,0,1)  // TST
+           || INSN0(9,4) == BITS6(0,0,1,0,0,1)) // TEQ
+       && INSN1(15,15) == 0
+       && INSN1(11,8) == BITS4(1,1,1,1)) {
+      UInt rN = INSN0(3,0);
+      if (!isBadRegT(rN)) { // yes, really, it's inconsistent with CMP.W
+         Bool  isTST  = INSN0(9,4) == BITS6(0,0,0,0,0,1);
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         IRTemp res   = newTemp(Ity_I32);
+         IRTemp oldV  = newTemp(Ity_I32);
+         IRTemp oldC  = newTemp(Ity_I32);
+         Bool   updC  = False;
+         UInt   imm32 = thumbExpandImm_from_I0_I1(&updC, insn0, insn1);
+         assign(argL, getIRegT(rN));
+         assign(argR, mkU32(imm32));
+         assign(res,  binop(isTST ? Iop_And32 : Iop_Xor32,
+                            mkexpr(argL), mkexpr(argR)));
+         assign( oldV, mk_armg_calculate_flag_v() );
+         assign( oldC, updC 
+                       ? mkU32((imm32 >> 31) & 1)
+                       : mk_armg_calculate_flag_c() );
+         setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, condT );
+         DIP("%s.w r%u, #%u\n", isTST ? "tst" : "teq", rN, imm32);

          goto decode_success;
       }
          goto decode_success;
       }

-      else
-         vassert(0);
+   }

 
 

-      /* fall through */
+   /* -------------- (T3) SUB{S}.W Rd, Rn, #constT -------------- */
+   /* -------------- (T3) RSB{S}.W Rd, Rn, #constT -------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && (INSN0(9,5) == BITS5(0,1,1,0,1) // SUB
+           || INSN0(9,5) == BITS5(0,1,1,1,0)) // RSB
+       && INSN1(15,15) == 0) {
+      Bool isRSB = INSN0(9,5) == BITS5(0,1,1,1,0);
+      UInt bS    = INSN0(4,4);
+      UInt rN    = INSN0(3,0);
+      UInt rD    = INSN1(11,8);
+      Bool valid = !isBadRegT(rN) && !isBadRegT(rD);
+      /* but allow "sub.w sp, sp, #constT" */
+      if (!valid && !isRSB && rN == 13 && rD == 13)
+         valid = True;
+      if (valid) {
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         IRTemp res   = newTemp(Ity_I32);
+         UInt   imm32 = thumbExpandImm_from_I0_I1(NULL, insn0, insn1);
+         assign(argL, getIRegT(rN));
+         assign(argR, mkU32(imm32));
+         assign(res,  isRSB
+                      ? binop(Iop_Sub32, mkexpr(argR), mkexpr(argL))
+                      : binop(Iop_Sub32, mkexpr(argL), mkexpr(argR)));
+         putIRegT(rD, mkexpr(res), condT);
+         if (bS == 1) {
+            if (isRSB)
+               setFlags_D1_D2( ARMG_CC_OP_SUB, argR, argL, condT );
+            else
+               setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT );
+         }
+         DIP("%s%s.w r%u, r%u, #%u\n",
+             isRSB ? "rsb" : "sub", bS == 1 ? "s" : "", rD, rN, imm32);
+         goto decode_success;
+      }

    }
 
    }
 

-   /* ----------------- I <-> S conversions ----------------- */
+   /* -------------- (T1) ADC{S}.W Rd, Rn, #constT -------------- */
+   /* -------------- (T1) SBC{S}.W Rd, Rn, #constT -------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && (   INSN0(9,5) == BITS5(0,1,0,1,0)  // ADC
+           || INSN0(9,5) == BITS5(0,1,0,1,1)) // SBC
+       && INSN1(15,15) == 0) {
+      /* ADC:  Rd = Rn + constT + oldC */
+      /* SBC:  Rd = Rn - constT - (oldC ^ 1) */
+      UInt bS    = INSN0(4,4);
+      UInt rN    = INSN0(3,0);
+      UInt rD    = INSN1(11,8);
+      if (!isBadRegT(rN) && !isBadRegT(rD)) {
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         IRTemp res   = newTemp(Ity_I32);
+         IRTemp oldC  = newTemp(Ity_I32);
+         UInt   imm32 = thumbExpandImm_from_I0_I1(NULL, insn0, insn1);
+         assign(argL, getIRegT(rN));
+         assign(argR, mkU32(imm32));
+         assign(oldC, mk_armg_calculate_flag_c() );
+         HChar* nm  = "???";
+         switch (INSN0(9,5)) {
+            case BITS5(0,1,0,1,0): // ADC
+               nm = "adc";
+               assign(res,
+                      binop(Iop_Add32,
+                            binop(Iop_Add32, mkexpr(argL), mkexpr(argR)),
+                            mkexpr(oldC) ));
+               putIRegT(rD, mkexpr(res), condT);
+               if (bS)
+                  setFlags_D1_D2_ND( ARMG_CC_OP_ADC,
+                                     argL, argR, oldC, condT );
+               break;
+            case BITS5(0,1,0,1,1): // SBC
+               nm = "sbc";
+               assign(res,
+                      binop(Iop_Sub32,
+                            binop(Iop_Sub32, mkexpr(argL), mkexpr(argR)),
+                            binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) ));
+               putIRegT(rD, mkexpr(res), condT);
+               if (bS)
+                  setFlags_D1_D2_ND( ARMG_CC_OP_SBB,
+                                     argL, argR, oldC, condT );
+               break;
+            default:
+              vassert(0);
+         }
+         DIP("%s%s.w r%u, r%u, #%u\n",
+             nm, bS == 1 ? "s" : "", rD, rN, imm32);
+         goto decode_success;
+      }
+   }

 
 

-   // F{S,U}ITOS fD, fM
-   /* These are more complex than FSITOD/FUITOD.  In the D cases, a 32
-      bit int will always fit within the 53 bit mantissa, so there's
-      no possibility of a loss of precision, but that's obviously not
-      the case here.  Hence this case possibly requires rounding, and
-      so it drags in the current rounding mode. */
-   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(1,0,0,0) == (INSN(19,16) & BITS4(1,1,1,1))
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
-      UInt bM    = (insn >> 5) & 1;
-      UInt bD    = (insn >> 22) & 1;
-      UInt fM    = (INSN(3,0) << 1) | bM;
-      UInt fD    = (INSN(15,12) << 1) | bD;
-      UInt syned = (insn >> 7) & 1;
-      IRTemp rmode = newTemp(Ity_I32);
-      assign(rmode, mkexpr(mk_get_IR_rounding_mode()));
-      if (syned) {
-         // FSITOS
-         putFReg(fD, binop(Iop_F64toF32,
-                           mkexpr(rmode),
-                           unop(Iop_I32StoF64,
-                                unop(Iop_ReinterpF32asI32, getFReg(fM)))),
-                 condT);
-         DIP("fsitos%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
-      } else {
-         // FUITOS
-         putFReg(fD, binop(Iop_F64toF32,
-                           mkexpr(rmode),
-                           unop(Iop_I32UtoF64,
-                                unop(Iop_ReinterpF32asI32, getFReg(fM)))),
-                 condT);
-         DIP("fuitos%s s%u, s%u\n", nCC(INSN_COND), fD, fM);
+   /* -------------- (T1) ORR{S}.W Rd, Rn, #constT -------------- */
+   /* -------------- (T1) AND{S}.W Rd, Rn, #constT -------------- */
+   /* -------------- (T1) BIC{S}.W Rd, Rn, #constT -------------- */
+   /* -------------- (T1) EOR{S}.W Rd, Rn, #constT -------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && (   INSN0(9,5) == BITS5(0,0,0,1,0)  // ORR
+           || INSN0(9,5) == BITS5(0,0,0,0,0)  // AND
+           || INSN0(9,5) == BITS5(0,0,0,0,1)  // BIC
+           || INSN0(9,5) == BITS5(0,0,1,0,0)) // EOR
+       && INSN1(15,15) == 0) {
+      UInt bS = INSN0(4,4);
+      UInt rN = INSN0(3,0);
+      UInt rD = INSN1(11,8);
+      if (!isBadRegT(rN) && !isBadRegT(rD)) {
+         Bool   isBIC = False;
+         IROp   op    = Iop_INVALID;
+         HChar* nm    = "???";
+         switch (INSN0(9,5)) {
+            case BITS5(0,0,0,1,0): op = Iop_Or32;  nm = "orr"; break;
+            case BITS5(0,0,0,0,0): op = Iop_And32; nm = "and"; break;
+            case BITS5(0,0,0,0,1): op = Iop_And32; nm = "bic";
+                                   isBIC = True; break;
+            case BITS5(0,0,1,0,0): op = Iop_Xor32;  nm = "eor"; break;
+            default: vassert(0);
+         }
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         IRTemp res   = newTemp(Ity_I32);
+         Bool   updC  = False;
+         UInt   imm32 = thumbExpandImm_from_I0_I1(&updC, insn0, insn1);
+         assign(argL, getIRegT(rN));
+         assign(argR, mkU32(isBIC ? ~imm32 : imm32));
+         assign(res,  binop(op, mkexpr(argL), mkexpr(argR)));
+         putIRegT(rD, mkexpr(res), condT);
+         if (bS) {
+            IRTemp oldV = newTemp(Ity_I32);
+            IRTemp oldC = newTemp(Ity_I32);
+            assign( oldV, mk_armg_calculate_flag_v() );
+            assign( oldC, updC 
+                          ? mkU32((imm32 >> 31) & 1)
+                          : mk_armg_calculate_flag_c() );
+            setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                               condT );
+         }
+         DIP("%s%s.w r%u, r%u, #%u\n",
+             nm, bS == 1 ? "s" : "", rD, rN, imm32);
+         goto decode_success;

       }
       }

-      goto decode_success;

    }
 
    }
 

-   // FTO{S,U}IS fD, fM
-   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
-      UInt   bM    = (insn >> 5) & 1;
-      UInt   bD    = (insn >> 22) & 1;
-      UInt   fD    = (INSN(15,12) << 1) | bD;
-      UInt   fM    = (INSN(3,0) << 1) | bM;
-      UInt   bZ    = (insn >> 7) & 1;
-      UInt   syned = (insn >> 16) & 1;
-      IRTemp rmode = newTemp(Ity_I32);
-      assign(rmode, bZ ? mkU32(Irrm_ZERO)
-                       : mkexpr(mk_get_IR_rounding_mode()));
-      if (syned) {
-         // FTOSIS
-         putFReg(fD, unop(Iop_ReinterpI32asF32,
-                          binop(Iop_F64toI32S, mkexpr(rmode),
-                                unop(Iop_F32toF64, getFReg(fM)))),
-                 condT);
-         DIP("ftosi%ss%s s%u, d%u\n", bZ ? "z" : "",
-             nCC(INSN_COND), fD, fM);
+   /* ---------- (T3) ADD{S}.W Rd, Rn, Rm, {shift} ---------- */
+   /* ---------- (T3) SUB{S}.W Rd, Rn, Rm, {shift} ---------- */
+   /* ---------- (T3) RSB{S}.W Rd, Rn, Rm, {shift} ---------- */
+   if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1)
+       && (   INSN0(8,5) == BITS4(1,0,0,0)  // add subopc
+           || INSN0(8,5) == BITS4(1,1,0,1)  // sub subopc
+           || INSN0(8,5) == BITS4(1,1,1,0)) // rsb subopc
+       && INSN1(15,15) == 0) {
+      UInt rN   = INSN0(3,0);
+      UInt rD   = INSN1(11,8);
+      UInt rM   = INSN1(3,0);
+      UInt bS   = INSN0(4,4);
+      UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6);
+      UInt how  = INSN1(5,4);
+
+      Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
+      /* but allow "add.w reg, sp, reg   w/ no shift */
+      if (!valid && INSN0(8,5) == BITS4(1,0,0,0) // add
+          && rN == 13 && imm5 == 0 && how == 0) {
+         valid = True;
+      }
+      /* also allow "sub.w sp, sp, reg   w/ no shift */
+      if (!valid && INSN0(8,5) == BITS4(1,1,0,1) // add
+          && rD == 13 && rN == 13 && imm5 == 0 && how == 0) {
+         valid = True;
+      }
+      if (valid) {
+         Bool   swap = False;
+         IROp   op   = Iop_INVALID;
+         HChar* nm   = "???";
+         switch (INSN0(8,5)) {
+            case BITS4(1,0,0,0): op = Iop_Add32; nm = "add"; break;
+            case BITS4(1,1,0,1): op = Iop_Sub32; nm = "sub"; break;
+            case BITS4(1,1,1,0): op = Iop_Sub32; nm = "rsb"; 
+                                 swap = True; break;
+            default: vassert(0);
+         }
+
+         IRTemp argL = newTemp(Ity_I32);
+         assign(argL, getIRegT(rN));
+
+         IRTemp rMt = newTemp(Ity_I32);
+         assign(rMt, getIRegT(rM));
+
+         IRTemp argR = newTemp(Ity_I32);
+         compute_result_and_C_after_shift_by_imm5(
+            dis_buf, &argR, NULL, rMt, how, imm5, rM
+         );
+
+         IRTemp res = newTemp(Ity_I32);
+         assign(res, swap 
+                     ? binop(op, mkexpr(argR), mkexpr(argL))
+                     : binop(op, mkexpr(argL), mkexpr(argR)));
+
+         putIRegT(rD, mkexpr(res), condT);
+         if (bS) {
+            switch (op) {
+               case Iop_Add32:
+                  setFlags_D1_D2( ARMG_CC_OP_ADD, argL, argR, condT );
+                  break;
+               case Iop_Sub32:
+                  if (swap)
+                     setFlags_D1_D2( ARMG_CC_OP_SUB, argR, argL, condT );
+                  else
+                     setFlags_D1_D2( ARMG_CC_OP_SUB, argL, argR, condT );
+                  break;
+               default:
+                  vassert(0);
+            }
+         }
+
+         DIP("%s%s.w r%u, r%u, %s\n",
+             nm, bS ? "s" : "", rD, rN, dis_buf);

          goto decode_success;
          goto decode_success;

-      } else {
-         // FTOUIS
-         putFReg(fD, unop(Iop_ReinterpI32asF32,
-                          binop(Iop_F64toI32U, mkexpr(rmode),
-                                unop(Iop_F32toF64, getFReg(fM)))),
-                 condT);
-         DIP("ftoui%ss%s s%u, d%u\n", bZ ? "z" : "",
-             nCC(INSN_COND), fD, fM);
+      }
+   }
+
+   /* ---------- (T3) ADC{S}.W Rd, Rn, Rm, {shift} ---------- */
+   /* ---------- (T2) SBC{S}.W Rd, Rn, Rm, {shift} ---------- */
+   if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1)
+       && (   INSN0(8,5) == BITS4(1,0,1,0)   // adc subopc
+           || INSN0(8,5) == BITS4(1,0,1,1))  // sbc subopc
+       && INSN1(15,15) == 0) {
+      /* ADC:  Rd = Rn + shifter_operand + oldC */
+      /* SBC:  Rd = Rn - shifter_operand - (oldC ^ 1) */
+      UInt rN = INSN0(3,0);
+      UInt rD = INSN1(11,8);
+      UInt rM = INSN1(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
+         UInt bS   = INSN0(4,4);
+         UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6);
+         UInt how  = INSN1(5,4);
+
+         IRTemp argL = newTemp(Ity_I32);
+         assign(argL, getIRegT(rN));
+
+         IRTemp rMt = newTemp(Ity_I32);
+         assign(rMt, getIRegT(rM));
+
+         IRTemp oldC = newTemp(Ity_I32);
+         assign(oldC, mk_armg_calculate_flag_c());
+
+         IRTemp argR = newTemp(Ity_I32);
+         compute_result_and_C_after_shift_by_imm5(
+            dis_buf, &argR, NULL, rMt, how, imm5, rM
+         );
+
+         HChar* nm  = "???";
+         IRTemp res = newTemp(Ity_I32);
+         switch (INSN0(8,5)) {
+            case BITS4(1,0,1,0): // ADC
+               nm = "adc";
+               assign(res,
+                      binop(Iop_Add32,
+                            binop(Iop_Add32, mkexpr(argL), mkexpr(argR)),
+                            mkexpr(oldC) ));
+               putIRegT(rD, mkexpr(res), condT);
+               if (bS)
+                  setFlags_D1_D2_ND( ARMG_CC_OP_ADC,
+                                     argL, argR, oldC, condT );
+               break;
+            case BITS4(1,0,1,1): // SBC
+               nm = "sbc";
+               assign(res,
+                      binop(Iop_Sub32,
+                            binop(Iop_Sub32, mkexpr(argL), mkexpr(argR)),
+                            binop(Iop_Xor32, mkexpr(oldC), mkU32(1)) ));
+               putIRegT(rD, mkexpr(res), condT);
+               if (bS)
+                  setFlags_D1_D2_ND( ARMG_CC_OP_SBB,
+                                     argL, argR, oldC, condT );
+               break;
+            default:
+               vassert(0);
+         }
+
+         DIP("%s%s.w r%u, r%u, %s\n",
+             nm, bS ? "s" : "", rD, rN, dis_buf);

          goto decode_success;
       }
    }
 
          goto decode_success;
       }
    }
 

-   /* ----------------- S <-> D conversions ----------------- */
+   /* ---------- (T3) AND{S}.W Rd, Rn, Rm, {shift} ---------- */
+   /* ---------- (T3) ORR{S}.W Rd, Rn, Rm, {shift} ---------- */
+   /* ---------- (T3) EOR{S}.W Rd, Rn, Rm, {shift} ---------- */
+   /* ---------- (T3) BIC{S}.W Rd, Rn, Rm, {shift} ---------- */
+   if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1)
+       && (   INSN0(8,5) == BITS4(0,0,0,0)  // and subopc
+           || INSN0(8,5) == BITS4(0,0,1,0)  // orr subopc
+           || INSN0(8,5) == BITS4(0,1,0,0)  // eor subopc
+           || INSN0(8,5) == BITS4(0,0,0,1)) // bic subopc
+       && INSN1(15,15) == 0) {
+      UInt rN = INSN0(3,0);
+      UInt rD = INSN1(11,8);
+      UInt rM = INSN1(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
+         Bool isBIC = False;
+         IROp op    = Iop_INVALID;
+         HChar* nm  = "???";
+         switch (INSN0(8,5)) {
+            case BITS4(0,0,0,0): op = Iop_And32; nm = "and"; break;
+            case BITS4(0,0,1,0): op = Iop_Or32;  nm = "orr"; break;
+            case BITS4(0,1,0,0): op = Iop_Xor32; nm = "eor"; break;
+            case BITS4(0,0,0,1): op = Iop_And32; nm = "bic";
+                                 isBIC = True; break;
+            default: vassert(0);
+         }
+         UInt bS   = INSN0(4,4);
+         UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6);
+         UInt how  = INSN1(5,4);

 
 

-   // FCVTDS
-   if (BITS8(1,1,1,0,1,0,1,1) == INSN(27,20)
-       && BITS4(0,1,1,1) == INSN(19,16)
-       && BITS4(1,0,1,0) == INSN(11,8)
-       && BITS4(1,1,0,0) == (INSN(7,4) & BITS4(1,1,0,1))) {
-      UInt dD = INSN(15,12);
-      UInt bM = (insn >> 5) & 1;
-      UInt fM = (INSN(3,0) << 1) | bM;
-      putDReg(dD, unop(Iop_F32toF64, getFReg(fM)), condT);
-      DIP("fcvtds%s d%u, s%u\n", nCC(INSN_COND), dD, fM);
-      goto decode_success;
+         IRTemp rNt = newTemp(Ity_I32);
+         assign(rNt, getIRegT(rN));
+
+         IRTemp rMt = newTemp(Ity_I32);
+         assign(rMt, getIRegT(rM));
+
+         IRTemp argR = newTemp(Ity_I32);
+         IRTemp oldC = bS ? newTemp(Ity_I32) : IRTemp_INVALID;
+
+         compute_result_and_C_after_shift_by_imm5(
+            dis_buf, &argR, bS ? &oldC : NULL, rMt, how, imm5, rM
+         );
+
+         IRTemp res = newTemp(Ity_I32);
+         if (isBIC) {
+            vassert(op == Iop_And32);
+            assign(res, binop(op, mkexpr(rNt),
+                                  unop(Iop_Not32, mkexpr(argR))));
+         } else {
+            assign(res, binop(op, mkexpr(rNt), mkexpr(argR)));
+         }
+
+         putIRegT(rD, mkexpr(res), condT);
+         if (bS) {
+            IRTemp oldV = newTemp(Ity_I32);
+            assign( oldV, mk_armg_calculate_flag_v() );
+            setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                               condT );
+         }
+
+         DIP("%s%s.w r%u, r%u, %s\n",
+             nm, bS ? "s" : "", rD, rN, dis_buf);
+         goto decode_success;
+      }

    }
 
    }
 

-   // FCVTSD
-   if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(0,1,1,1) == INSN(19,16)
-       && BITS4(1,0,1,1) == INSN(11,8)
-       && BITS4(1,1,0,0) == INSN(7,4)) {
-      UInt   bD    = (insn >> 22) & 1;
-      UInt   fD    = (INSN(15,12) << 1) | bD;
-      UInt   dM    = INSN(3,0);
-      IRTemp rmode = newTemp(Ity_I32);
-      assign(rmode, mkexpr(mk_get_IR_rounding_mode()));
-      putFReg(fD, binop(Iop_F64toF32, mkexpr(rmode), getDReg(dM)),
-                  condT);
-      DIP("fcvtsd%s s%u, d%u\n", nCC(INSN_COND), fD, dM);
-      goto decode_success;
+   /* -------------- (T?) LSL{S}.W Rd, Rn, Rm -------------- */
+   /* -------------- (T?) LSR{S}.W Rd, Rn, Rm -------------- */
+   /* -------------- (T?) ASR{S}.W Rd, Rn, Rm -------------- */
+   /* -------------- (T?) ROR{S}.W Rd, Rn, Rm -------------- */
+   if (INSN0(15,7) == BITS9(1,1,1,1,1,0,1,0,0)
+       && INSN1(15,12) == BITS4(1,1,1,1)
+       && INSN1(7,4) == BITS4(0,0,0,0)) {
+      UInt how = INSN0(6,5); // standard encoding
+      UInt rN  = INSN0(3,0);
+      UInt rD  = INSN1(11,8);
+      UInt rM  = INSN1(3,0);
+      UInt bS  = INSN0(4,4);
+      Bool valid = !isBadRegT(rN) && !isBadRegT(rM) && !isBadRegT(rD);
+      if (how == 3) valid = False; //ATC
+      if (valid) {
+         IRTemp rNt    = newTemp(Ity_I32);
+         IRTemp rMt    = newTemp(Ity_I32);
+         IRTemp res    = newTemp(Ity_I32);
+         IRTemp oldC   = bS ? newTemp(Ity_I32) : IRTemp_INVALID;
+         IRTemp oldV   = bS ? newTemp(Ity_I32) : IRTemp_INVALID;
+         HChar* nms[4] = { "lsl", "lsr", "asr", "ror" };
+         HChar* nm     = nms[how];
+         assign(rNt, getIRegT(rN));
+         assign(rMt, getIRegT(rM));
+         compute_result_and_C_after_shift_by_reg(
+            dis_buf, &res, bS ? &oldC : NULL,
+            rNt, how, rMt, rN, rM
+         );
+         if (bS)
+            assign(oldV, mk_armg_calculate_flag_v());
+         putIRegT(rD, mkexpr(res), condT);
+         if (bS) {
+            setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                               condT );
+         }
+         DIP("%s%s.w r%u, r%u, r%u\n",
+             nm, bS ? "s" : "", rD, rN, rM);
+         goto decode_success;
+      }

    }
 
    }
 

-   /* ----------------------------------------------------------- */
-   /* -- ARMv6 instructions                                    -- */
-   /* ----------------------------------------------------------- */
+   /* ------------ (T?) MOV{S}.W Rd, Rn, {shift} ------------ */
+   /* ------------ (T?) MVN{S}.W Rd, Rn, {shift} ------------ */
+   if ((INSN0(15,0) & 0xFFCF) == 0xEA4F
+       && INSN1(15,15) == 0) {
+      UInt rD = INSN1(11,8);
+      UInt rN = INSN1(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rN)) {
+         UInt bS    = INSN0(4,4);
+         UInt isMVN = INSN0(5,5);
+         UInt imm5  = (INSN1(14,12) << 2) | INSN1(7,6);
+         UInt how   = INSN1(5,4);
+
+         IRTemp rNt = newTemp(Ity_I32);
+         assign(rNt, getIRegT(rN));
+
+         IRTemp oldRn = newTemp(Ity_I32);
+         IRTemp oldC  = bS ? newTemp(Ity_I32) : IRTemp_INVALID;
+         compute_result_and_C_after_shift_by_imm5(
+            dis_buf, &oldRn, bS ? &oldC : NULL, rNt, how, imm5, rN
+         );

 
 

-   /* --------------------- ldrex, strex --------------------- */
+         IRTemp res = newTemp(Ity_I32);
+         assign(res, isMVN ? unop(Iop_Not32, mkexpr(oldRn))
+                           : mkexpr(oldRn));

 
 

-   // LDREX
-   if (0x01900F9F == (insn & 0x0FF00FFF)) {
-      UInt rT = INSN(15,12);
-      UInt rN = INSN(19,16);
-      if (rT == 15 || rN == 15 || rT == 14 /* || (rT & 1)*/) {
-         /* undecodable; fall through */
-      } else {
-         IRTemp res;
-         /* make unconditional */
-         if (condT != IRTemp_INVALID) {
-            mk_skip_to_next_if_cond_is_false( condT );
-            condT = IRTemp_INVALID;
+         putIRegT(rD, mkexpr(res), condT);
+         if (bS) {
+            IRTemp oldV = newTemp(Ity_I32);
+            assign( oldV, mk_armg_calculate_flag_v() );
+            setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV, condT);

          }
          }

-         /* Ok, now we're unconditional.  Do the load. */
-         res = newTemp(Ity_I32);
-         stmt( IRStmt_LLSC(Iend_LE, res, getIReg(rN), NULL/*this is a load*/) );
-         putIReg(rT, mkexpr(res), IRTemp_INVALID, Ijk_Boring);
-         DIP("ldrex%s r%u, [r%u]\n", nCC(INSN_COND), rT, rN);
+         DIP("%s%s.w r%u, %s\n",
+             isMVN ? "mvn" : "mov", bS ? "s" : "", rD, dis_buf);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   // STREX
-   if (0x01800F90 == (insn & 0x0FF00FF0)) {
-      UInt rT = INSN(3,0);
-      UInt rN = INSN(19,16);
-      UInt rD = INSN(15,12);
-      if (rT == 15 || rN == 15 || rD == 15
-          || rT == 14 /* || (rT & 1)*/
-          || rD == rT || rN == rT) {
-         /* undecodable; fall through */
-      } else {
-         IRTemp resSC1, resSC32;
+   /* -------------- (T?) TST.W Rn, Rm, {shift} -------------- */
+   /* -------------- (T?) TEQ.W Rn, Rm, {shift} -------------- */
+   if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1)
+       && (   INSN0(8,4) == BITS5(0,0,0,0,1)  // TST
+           || INSN0(8,4) == BITS5(0,1,0,0,1)) // TEQ
+       && INSN1(15,15) == 0
+       && INSN1(11,8) == BITS4(1,1,1,1)) {
+      UInt rN = INSN0(3,0);
+      UInt rM = INSN1(3,0);
+      if (!isBadRegT(rN) && !isBadRegT(rM)) {
+         Bool isTST = INSN0(8,4) == BITS5(0,0,0,0,1);
+
+         UInt how  = INSN1(5,4);
+         UInt imm5 = (INSN1(14,12) << 2) | INSN1(7,6);

 
 

-         /* make unconditional */
-         if (condT != IRTemp_INVALID) {
-            mk_skip_to_next_if_cond_is_false( condT );
-            condT = IRTemp_INVALID;
-         }
+         IRTemp argL = newTemp(Ity_I32);
+         assign(argL, getIRegT(rN));

 
 

-         /* Ok, now we're unconditional.  Do the store. */
-         resSC1 = newTemp(Ity_I1);
-         stmt( IRStmt_LLSC(Iend_LE, resSC1, getIReg(rN), getIReg(rT)) );
+         IRTemp rMt = newTemp(Ity_I32);
+         assign(rMt, getIRegT(rM));

 
 

-         /* Set rD to 1 on failure, 0 on success.  Currently we have
-            resSC1 == 0 on failure, 1 on success. */
-         resSC32 = newTemp(Ity_I32);
-         assign(resSC32,
-                unop(Iop_1Uto32, unop(Iop_Not1, mkexpr(resSC1))));
+         IRTemp argR = newTemp(Ity_I32);
+         IRTemp oldC = newTemp(Ity_I32);
+         compute_result_and_C_after_shift_by_imm5(
+            dis_buf, &argR, &oldC, rMt, how, imm5, rM
+         );

 
 

-         putIReg(rD, mkexpr(resSC32),
-                     IRTemp_INVALID, Ijk_Boring);
-         DIP("strex%s r%u, r%u, [r%u]\n", nCC(INSN_COND), rD, rT, rN);
+         IRTemp oldV = newTemp(Ity_I32);
+         assign( oldV, mk_armg_calculate_flag_v() );
+
+         IRTemp res = newTemp(Ity_I32);
+         assign(res, binop(isTST ? Iop_And32 : Iop_Xor32,
+                           mkexpr(argL), mkexpr(argR)));
+
+         setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                            condT );
+         DIP("%s.w r%u, %s\n", isTST ? "tst" : "teq", rN, dis_buf);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   /* --------------------- movw, movt --------------------- */
-   if (0x03000000 == (insn & 0x0FF00000)
-       || 0x03400000 == (insn & 0x0FF00000)) /* pray for CSE */ {
-      UInt rD    = INSN(15,12);
-      UInt imm16 = (insn & 0xFFF) | ((insn >> 4) & 0x0000F000);
-      UInt isT   = (insn >> 22) & 1;
-      if (rD == 15) {
-         /* forget it */
-      } else {
-         if (isT) {
-            putIReg(rD,
-                    binop(Iop_Or32,
-                          binop(Iop_And32, getIReg(rD), mkU32(0xFFFF)),
-                          mkU32(imm16 << 16)),
-                    condT, Ijk_Boring);
-            DIP("movt%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
-            goto decode_success;
-         } else {
-            putIReg(rD, mkU32(imm16), condT, Ijk_Boring);
-            DIP("movw%s r%u, #0x%04x\n", nCC(INSN_COND), rD, imm16);
-            goto decode_success;
-         }
+   /* -------------- (T3) CMP.W Rn, Rm, {shift} -------------- */
+   /* -------------- (T2) CMN.W Rn, Rm, {shift} -------------- */
+   if (INSN0(15,9) == BITS7(1,1,1,0,1,0,1)
+       && (   INSN0(8,4) == BITS5(1,1,0,1,1)  // CMP
+           || INSN0(8,4) == BITS5(1,0,0,0,1)) // CMN
+       && INSN1(15,15) == 0
+       && INSN1(11,8) == BITS4(1,1,1,1)) {
+      UInt rN = INSN0(3,0);
+      UInt rM = INSN1(3,0);
+      if (!isBadRegT(rN) && !isBadRegT(rM)) {
+         Bool isCMN = INSN0(8,4) == BITS5(1,0,0,0,1);
+         UInt how   = INSN1(5,4);
+         UInt imm5  = (INSN1(14,12) << 2) | INSN1(7,6);
+
+         IRTemp argL = newTemp(Ity_I32);
+         assign(argL, getIRegT(rN));
+
+         IRTemp rMt = newTemp(Ity_I32);
+         assign(rMt, getIRegT(rM));
+
+         IRTemp argR = newTemp(Ity_I32);
+         compute_result_and_C_after_shift_by_imm5(
+            dis_buf, &argR, NULL, rMt, how, imm5, rM
+         );
+
+         setFlags_D1_D2( isCMN ? ARMG_CC_OP_ADD : ARMG_CC_OP_SUB,
+                         argL, argR, condT );
+
+         DIP("%s.w r%u, %s\n", isCMN ? "cmn" : "cmp", rN, dis_buf);
+         goto decode_success;

       }
       }

-      /* fall through */

    }
 
    }
 

-   /* ------------------- {u,s}xt{b,h}{,16} ------------------- */
-   if (BITS8(0,1,1,0,1, 0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,0,0))
-       && BITS4(1,1,1,1) == INSN(19,16)
-       && BITS4(0,1,1,1) == INSN(7,4)
-       && BITS4(0,0, 0,0) == (INSN(11,8) & BITS4(0,0,1,1))) {
-      UInt subopc = INSN(27,20) & BITS8(0,0,0,0,0, 1,1,1);
-      if (subopc != BITS4(0,0,0,1) && subopc != BITS4(0,1,0,1)) {
-         Int    rot  = (INSN(11,8) >> 2) & 3;
-         UInt   rM   = INSN(3,0);
-         UInt   rD   = INSN(15,12);
-         IRTemp srcT = newTemp(Ity_I32);
-         IRTemp rotT = newTemp(Ity_I32);
-         IRTemp dstT = newTemp(Ity_I32);
-         HChar* nm   = "???";
-         assign(srcT, getIReg(rM));
-         assign(rotT, genROR32(srcT, 8 * rot)); /* 0, 8, 16 or 24 only */
-         switch (subopc) {
-            case BITS4(0,1,1,0): // UXTB
-               assign(dstT, unop(Iop_8Uto32, unop(Iop_32to8, mkexpr(rotT))));
-               nm = "uxtb";
-               break;
-            case BITS4(0,0,1,0): // SXTB
-               assign(dstT, unop(Iop_8Sto32, unop(Iop_32to8, mkexpr(rotT))));
-               nm = "sxtb";
-               break;
-            case BITS4(0,1,1,1): // UXTH
-               assign(dstT, unop(Iop_16Uto32, unop(Iop_32to16, mkexpr(rotT))));
-               nm = "uxth";
-               break;
-            case BITS4(0,0,1,1): // SXTH
-               assign(dstT, unop(Iop_16Sto32, unop(Iop_32to16, mkexpr(rotT))));
-               nm = "sxth";
-               break;
-            case BITS4(0,1,0,0): // UXTB16
-               assign(dstT, binop(Iop_And32, mkexpr(rotT), mkU32(0x00FF00FF)));
-               nm = "uxtb16";
-               break;
-            case BITS4(0,0,0,0): { // SXTB16
-               IRTemp lo32 = newTemp(Ity_I32);
-               IRTemp hi32 = newTemp(Ity_I32);
-               assign(lo32, binop(Iop_And32, mkexpr(rotT), mkU32(0xFF)));
-               assign(hi32, binop(Iop_Shr32, mkexpr(rotT), mkU8(16)));
-               assign(
-                  dstT,
-                  binop(Iop_Or32,
-                        binop(Iop_And32,
-                              unop(Iop_8Sto32,
-                                   unop(Iop_32to8, mkexpr(lo32))),
-                              mkU32(0xFFFF)),
-                        binop(Iop_Shl32,
-                              unop(Iop_8Sto32,
-                                   unop(Iop_32to8, mkexpr(hi32))),
-                              mkU8(16))
-               ));
-               nm = "uxtb16";
-               break;
-            }
-            default:
-               vassert(0); // guarded by "if" above
+   /* -------------- (T2) MOV{S}.W Rd, #constT -------------- */
+   /* -------------- (T2) MVN{S}.W Rd, #constT -------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && (   INSN0(9,5) == BITS5(0,0,0,1,0)  // MOV
+           || INSN0(9,5) == BITS5(0,0,0,1,1)) // MVN
+       && INSN0(3,0) == BITS4(1,1,1,1)
+       && INSN1(15,15) == 0) {
+      UInt rD = INSN1(11,8);
+      if (!isBadRegT(rD)) {
+         Bool   updC  = False;
+         UInt   bS    = INSN0(4,4);
+         Bool   isMVN = INSN0(5,5) == 1;
+         UInt   imm32 = thumbExpandImm_from_I0_I1(&updC, insn0, insn1);
+         IRTemp res   = newTemp(Ity_I32);
+         assign(res, mkU32(isMVN ? ~imm32 : imm32));
+         putIRegT(rD, mkexpr(res), condT);
+         if (bS) {
+            IRTemp oldV = newTemp(Ity_I32);
+            IRTemp oldC = newTemp(Ity_I32);
+            assign( oldV, mk_armg_calculate_flag_v() );
+            assign( oldC, updC 
+                          ? mkU32((imm32 >> 31) & 1)
+                          : mk_armg_calculate_flag_c() );
+            setFlags_D1_D2_ND( ARMG_CC_OP_LOGIC, res, oldC, oldV,
+                               condT );

          }
          }

-         putIReg(rD, mkexpr(dstT), condT, Ijk_Boring);
-         DIP("%s%s r%u, r%u, ROR #%u\n", nm, nCC(INSN_COND), rD, rM, rot);
+         DIP("%s%s.w r%u, #%u\n",
+             isMVN ? "mvn" : "mov", bS ? "s" : "", rD, imm32);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   /* ------------------- bfi, bfc ------------------- */
-   if (BITS8(0,1,1,1,1,1,0, 0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
-       && BITS4(0, 0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
-      UInt rD  = INSN(15,12);
-      UInt rN  = INSN(3,0);
-      UInt msb = (insn >> 16) & 0x1F; /* 20:16 */
-      UInt lsb = (insn >> 7) & 0x1F;  /* 11:7 */
-      if (rD == 15 || msb < lsb) {
-         /* undecodable; fall through */
-      } else {
-         IRTemp src    = newTemp(Ity_I32);
-         IRTemp olddst = newTemp(Ity_I32);
-         IRTemp newdst = newTemp(Ity_I32);
-         UInt   mask = 1 << (msb - lsb);
-         mask = (mask - 1) + mask;
-         vassert(mask != 0); // guaranteed by "msb < lsb" check above
-         mask <<= lsb;
+   /* -------------- (T3) MOVW Rd, #imm16 -------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && INSN0(9,4) == BITS6(1,0,0,1,0,0)
+       && INSN1(15,15) == 0) {
+      UInt rD = INSN1(11,8);
+      if (!isBadRegT(rD)) {
+         UInt imm16 = (INSN0(3,0) << 12) | (INSN0(10,10) << 11)
+                      | (INSN1(14,12) << 8) | INSN1(7,0);
+         putIRegT(rD, mkU32(imm16), condT);
+         DIP("movw r%u, #%u\n", rD, imm16);
+         goto decode_success;
+      }
+   }

 
 

-         assign(src, rN == 15 ? mkU32(0) : getIReg(rN));
-         assign(olddst, getIReg(rD));
-         assign(newdst,
+   /* ---------------- MOVT Rd, #imm16 ---------------- */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && INSN0(9,4) == BITS6(1,0,1,1,0,0)
+       && INSN1(15,15) == 0) {
+      UInt rD = INSN1(11,8);
+      if (!isBadRegT(rD)) {
+         UInt imm16 = (INSN0(3,0) << 12) | (INSN0(10,10) << 11)
+                      | (INSN1(14,12) << 8) | INSN1(7,0);
+         IRTemp res = newTemp(Ity_I32);
+         assign(res,

                 binop(Iop_Or32,
                 binop(Iop_Or32,

-                   binop(Iop_And32,
-                         binop(Iop_Shl32, mkexpr(src), mkU8(lsb)), 
-                         mkU32(mask)),
-                   binop(Iop_And32,
-                         mkexpr(olddst),
-                         mkU32(~mask)))
-               );
+                      binop(Iop_And32, getIRegT(rD), mkU32(0xFFFF)),
+                      mkU32(imm16 << 16)));
+         putIRegT(rD, mkexpr(res), condT);
+         DIP("movt r%u, #%u\n", rD, imm16);
+         goto decode_success;
+      }
+   }
+
+   /* ---------------- LD/ST reg+/-#imm8 ---------------- */
+   /* Loads and stores of the form:
+         op  Rt, [Rn, #-imm8]      or
+         op  Rt, [Rn], #+/-imm8    or
+         op  Rt, [Rn, #+/-imm8]!  
+      where op is one of
+         ldrb ldrh ldr  ldrsb ldrsh
+         strb strh str
+   */
+   if (INSN0(15,9) == BITS7(1,1,1,1,1,0,0) && INSN1(11,11) == 1) {
+      Bool   valid  = True;
+      Bool   syned  = False;
+      Bool   isST   = False;
+      IRType ty     = Ity_I8;
+      HChar* nm     = "???";
+
+      switch (INSN0(8,4)) {
+         case BITS5(0,0,0,0,0):   // strb
+            nm = "strb"; isST = True; break;
+         case BITS5(0,0,0,0,1):   // ldrb
+            nm = "ldrb"; break;
+         case BITS5(1,0,0,0,1):   // ldrsb
+            nm = "ldrsb"; syned = True; break;
+         case BITS5(0,0,0,1,0):   // strh
+            nm = "strh"; ty = Ity_I16; isST = True; break;
+         case BITS5(0,0,0,1,1):   // ldrh
+            nm = "ldrh"; ty = Ity_I16; break;
+         case BITS5(1,0,0,1,1):   // ldrsh
+            nm = "ldrsh"; ty = Ity_I16; syned = True; break;
+         case BITS5(0,0,1,0,0):   // str
+            nm = "str"; ty = Ity_I32; isST = True; break;
+         case BITS5(0,0,1,0,1):
+            nm = "ldr"; ty = Ity_I32; break;  // ldr
+         default:
+            valid = False; break;
+      }
+
+      UInt rN      = INSN0(3,0);
+      UInt rT      = INSN1(15,12);
+      UInt bP      = INSN1(10,10);
+      UInt bU      = INSN1(9,9);
+      UInt bW      = INSN1(8,8);
+      UInt imm8    = INSN1(7,0);
+      Bool loadsPC = False;
+
+      if (valid) {
+         if (bP == 1 && bU == 1 && bW == 0)
+            valid = False;
+         if (bP == 0 && bW == 0)
+            valid = False;
+         if (rN == 15)
+            valid = False;
+         if (bW == 1 && rN == rT)
+            valid = False;
+         if (ty == Ity_I8 || ty == Ity_I16) {
+            if (isBadRegT(rT))
+               valid = False;
+         } else {
+            /* ty == Ity_I32 */
+            if (isST && rT == 15)
+               valid = False;
+            if (!isST && rT == 15)
+               loadsPC = True;
+         }
+      }
+
+      if (valid) {
+         // if it's a branch, it can't happen in the middle of an IT block
+         if (loadsPC)
+            gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+         // go uncond
+         mk_skip_over_T32_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         // now uncond
+
+         IRTemp preAddr = newTemp(Ity_I32);
+         assign(preAddr, getIRegT(rN));
+
+         IRTemp postAddr = newTemp(Ity_I32);
+         assign(postAddr, binop(bU == 1 ? Iop_Add32 : Iop_Sub32,
+                                mkexpr(preAddr), mkU32(imm8)));
+
+         IRTemp transAddr = bP == 1 ? postAddr : preAddr;
+
+         if (isST) {
+
+             /* Store.  If necessary, update the base register before
+                the store itself, so that the common idiom of "str rX,
+                [sp, #-4]!" (store rX at sp-4, then do new sp = sp-4,
+                a.k.a "push rX") doesn't cause Memcheck to complain
+                that the access is below the stack pointer.  Also, not
+                updating sp before the store confuses Valgrind's
+                dynamic stack-extending logic.  So do it before the
+                store.  Hence we need to snarf the store data before
+                doing the basereg update. */
+
+            /* get hold of the data to be stored */
+            IRTemp oldRt = newTemp(Ity_I32);
+            assign(oldRt, getIRegT(rT));
+
+            /* Update Rn if necessary. */
+            if (bW == 1) {
+               vassert(rN != rT); // assured by validity check above
+               putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID);
+            }
+
+            /* generate the transfer */
+            switch (ty) {
+               case Ity_I8:
+                  storeLE(mkexpr(transAddr),
+                                 unop(Iop_32to8, mkexpr(oldRt)));
+                  break;
+               case Ity_I16:
+                  storeLE(mkexpr(transAddr),
+                          unop(Iop_32to16, mkexpr(oldRt)));
+                  break;
+              case Ity_I32:
+                  storeLE(mkexpr(transAddr), mkexpr(oldRt));
+                  break;
+              default:
+                 vassert(0);
+            }
+
+         } else {
+
+            /* Load. */
+
+            /* generate the transfer */
+            IRTemp newRt = newTemp(Ity_I32);
+            IROp   widen = Iop_INVALID;
+            switch (ty) {
+               case Ity_I8:
+                  widen = syned ? Iop_8Sto32 : Iop_8Uto32; break;
+               case Ity_I16:
+                  widen = syned ? Iop_16Sto32 : Iop_16Uto32; break;
+               case Ity_I32:
+                  break;
+               default:
+                  vassert(0);
+            }
+            if (widen == Iop_INVALID) {
+               assign(newRt, loadLE(ty, mkexpr(transAddr)));
+            } else {
+               assign(newRt, unop(widen, loadLE(ty, mkexpr(transAddr))));
+            }
+            if (loadsPC) {
+               vassert(rT == 15);
+               llPutIReg(rT, mkexpr(newRt));
+            } else {
+               putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
+            }

 
 

-         putIReg(rD, mkexpr(newdst), condT, Ijk_Boring);
+            if (loadsPC) {
+               /* Presumably this is an interworking branch. */
+               irsb->next = mkexpr(newRt);
+               irsb->jumpkind = Ijk_Boring;  /* or _Ret ? */
+               dres.whatNext  = Dis_StopHere;
+            }

 
 

-         if (rN == 15) {
-            DIP("bfc%s r%u, #%u, #%u\n",
-                nCC(INSN_COND), rD, lsb, msb-lsb+1);
-         } else {
-            DIP("bfi%s r%u, r%u, #%u, #%u\n",
-                nCC(INSN_COND), rD, rN, lsb, msb-lsb+1);
+            /* Update Rn if necessary. */
+            if (bW == 1) {
+               vassert(rN != rT); // assured by validity check above
+               putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID);
+            }
+         }
+
+         if (bP == 1 && bW == 0) {
+            DIP("%s.w r%u, [r%u, #%c%u]\n",
+                nm, rT, rN, bU ? '+' : '-', imm8);
+         }
+         else if (bP == 1 && bW == 1) {
+            DIP("%s.w r%u, [r%u, #%c%u]!\n",
+                nm, rT, rN, bU ? '+' : '-', imm8);
+         }
+         else {
+            vassert(bP == 0 && bW == 1);
+            DIP("%s.w r%u, [r%u], #%c%u\n",
+                nm, rT, rN, bU ? '+' : '-', imm8);

          }
          }

+

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   /* ------------------- {u,s}bfx ------------------- */
-   if (BITS8(0,1,1,1,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
-       && BITS4(0,1,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
-      UInt rD  = INSN(15,12);
-      UInt rN  = INSN(3,0);
-      UInt wm1 = (insn >> 16) & 0x1F; /* 20:16 */
-      UInt lsb = (insn >> 7) & 0x1F;  /* 11:7 */
-      UInt msb = lsb + wm1;
-      UInt isU = (insn >> 22) & 1;    /* 22:22 */
-      if (rD == 15 || rN == 15 || msb >= 32) {
-         /* undecodable; fall through */
+   /* ------------- LD/ST reg+(reg<<imm2) ------------- */
+   /* Loads and stores of the form:
+         op  Rt, [Rn, Rm, LSL #imm8]
+      where op is one of
+         ldrb ldrh ldr  ldrsb ldrsh
+         strb strh str
+   */
+   if (INSN0(15,9) == BITS7(1,1,1,1,1,0,0)
+       && INSN1(11,6) == BITS6(0,0,0,0,0,0)) {
+      Bool   valid  = True;
+      Bool   syned  = False;
+      Bool   isST   = False;
+      IRType ty     = Ity_I8;
+      HChar* nm     = "???";
+
+      switch (INSN0(8,4)) {
+         case BITS5(0,0,0,0,0):   // strb
+            nm = "strb"; isST = True; break;
+         case BITS5(0,0,0,0,1):   // ldrb
+            nm = "ldrb"; break;
+         case BITS5(1,0,0,0,1):   // ldrsb
+            nm = "ldrsb"; syned = True; break;
+         case BITS5(0,0,0,1,0):   // strh
+            nm = "strh"; ty = Ity_I16; isST = True; break;
+         case BITS5(0,0,0,1,1):   // ldrh
+            nm = "ldrh"; ty = Ity_I16; break;
+         case BITS5(1,0,0,1,1):   // ldrsh
+            nm = "ldrsh"; ty = Ity_I16; syned = True; break;
+         case BITS5(0,0,1,0,0):   // str
+            nm = "str"; ty = Ity_I32; isST = True; break;
+         case BITS5(0,0,1,0,1):
+            nm = "ldr"; ty = Ity_I32; break;  // ldr
+         default:
+            valid = False; break;
+      }
+
+      UInt rN      = INSN0(3,0);
+      UInt rM      = INSN1(3,0);
+      UInt rT      = INSN1(15,12);
+      UInt imm2    = INSN1(5,4);
+      Bool loadsPC = False;
+
+      if (ty == Ity_I8 || ty == Ity_I16) {
+         /* all 8- and 16-bit load and store cases have the
+            same exclusion set. */
+         if (rN == 15 || isBadRegT(rT) || isBadRegT(rM))
+            valid = False;

       } else {
       } else {

-         IRTemp src  = newTemp(Ity_I32);
-         IRTemp tmp  = newTemp(Ity_I32);
-         IRTemp res  = newTemp(Ity_I32);
-         UInt   mask = ((1 << wm1) - 1) + (1 << wm1);
-         vassert(msb >= 0 && msb <= 31);
-         vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive
+         vassert(ty == Ity_I32);
+         if (rN == 15 || isBadRegT(rM))
+            valid = False;
+         if (isST && rT == 15)
+            valid = False;
+         /* If it is a load and rT is 15, that's only allowable if we
+            not in an IT block, or are the last in it.  Need to insert
+            a dynamic check for that. */
+         if (!isST && rT == 15)
+            loadsPC = True;
+      }

 
 

-         assign(src, getIReg(rN));
-         assign(tmp, binop(Iop_And32,
-                           binop(Iop_Shr32, mkexpr(src), mkU8(lsb)),
-                           mkU32(mask)));
-         assign(res, binop(isU ? Iop_Shr32 : Iop_Sar32,
-                           binop(Iop_Shl32, mkexpr(tmp), mkU8(31-wm1)),
-                           mkU8(31-wm1)));
+      if (valid) {
+         // if it's a branch, it can't happen in the middle of an IT block
+         if (loadsPC)
+            gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+         // go uncond
+         mk_skip_over_T32_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         // now uncond
+
+         IRTemp transAddr = newTemp(Ity_I32);
+         assign(transAddr,
+                binop( Iop_Add32,
+                       getIRegT(rN),
+                       binop(Iop_Shl32, getIRegT(rM), mkU8(imm2)) ));
+
+         if (isST) {
+            IRTemp oldRt = newTemp(Ity_I32);
+            assign(oldRt, getIRegT(rT));
+            switch (ty) {
+               case Ity_I8:
+                  storeLE(mkexpr(transAddr),
+                                 unop(Iop_32to8, mkexpr(oldRt)));
+                  break;
+               case Ity_I16:
+                  storeLE(mkexpr(transAddr),
+                          unop(Iop_32to16, mkexpr(oldRt)));
+                  break;
+              case Ity_I32:
+                  storeLE(mkexpr(transAddr), mkexpr(oldRt));
+                  break;
+              default:
+                 vassert(0);
+            }
+         } else {
+            IRTemp newRt = newTemp(Ity_I32);
+            IROp   widen = Iop_INVALID;
+            switch (ty) {
+               case Ity_I8:
+                  widen = syned ? Iop_8Sto32 : Iop_8Uto32; break;
+               case Ity_I16:
+                  widen = syned ? Iop_16Sto32 : Iop_16Uto32; break;
+               case Ity_I32:
+                  break;
+               default:
+                  vassert(0);
+            }
+            if (widen == Iop_INVALID) {
+               assign(newRt, loadLE(ty, mkexpr(transAddr)));
+            } else {
+               assign(newRt, unop(widen, loadLE(ty, mkexpr(transAddr))));
+            }

 
 

-         putIReg(rD, mkexpr(res), condT, Ijk_Boring);
+            /* If we're loading the PC, putIRegT will assert.  So go
+               direct via llPutIReg.  In all other cases use putIRegT
+               as it is safer (although could simply use llPutIReg for
+               _all_ cases here.) */
+            if (loadsPC) {
+               vassert(rT == 15);
+               llPutIReg(rT, mkexpr(newRt));
+            } else {
+               putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
+            }
+
+            if (loadsPC) {
+               /* Presumably this is an interworking branch. */
+               irsb->next = mkexpr(newRt);
+               irsb->jumpkind = Ijk_Boring;  /* or _Ret ? */
+               dres.whatNext  = Dis_StopHere;
+            }
+         }
+
+         DIP("%s.w r%u, [r%u, r%u, LSL #%u]\n",
+             nm, rT, rN, rM, imm2);

 
 

-         DIP("%s%s r%u, r%u, #%u, #%u\n",
-             isU ? "ubfx" : "sbfx",
-             nCC(INSN_COND), rD, rN, lsb, wm1 + 1);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   /* ------------------- smul{b,t}{b,t} ------------- */
-   if (BITS8(0,0,0,1,0,1,1,0) == INSN(27,20)
-       && BITS4(0,0,0,0) == INSN(15,12)
-       && BITS4(1,0,0,0) == (INSN(7,4) & BITS4(1,0,0,1))) {
-      UInt rD  = INSN(19,16);
-      UInt rM  = INSN(11,8);
-      UInt rN  = INSN(3,0);
-      UInt bM = (insn >> 6) & 1;
-      UInt bN = (insn >> 5) & 1;
-      if (bN == 0 && bM == 1) goto decode_failure; //ATC
-      if (bN == 1 && bM == 0) goto decode_failure; //ATC
-      if (bN == 1 && bM == 1) goto decode_failure; //ATC
-      if (rD == 15 || rN == 15 || rM == 15) {
-         /* undecodable; fall through */
+   /* --------------- LD/ST reg+imm12 --------------- */
+   /* Loads and stores of the form:
+         op  Rt, [Rn, +#imm12]
+      where op is one of
+         ldrb ldrh ldr  ldrsb ldrsh
+         strb strh str
+   */
+   if (INSN0(15,9) == BITS7(1,1,1,1,1,0,0)) {
+      Bool   valid  = True;
+      Bool   syned  = False;
+      Bool   isST   = False;
+      IRType ty     = Ity_I8;
+      HChar* nm     = "???";
+
+      switch (INSN0(8,4)) {
+         case BITS5(0,1,0,0,0):   // strb
+            nm = "strb"; isST = True; break;
+         case BITS5(0,1,0,0,1):   // ldrb
+            nm = "ldrb"; break;
+         case BITS5(1,1,0,0,1):   // ldrsb
+            nm = "ldrsb"; syned = True; break;
+         case BITS5(0,1,0,1,0):   // strh
+            nm = "strh"; ty = Ity_I16; isST = True; break;
+         case BITS5(0,1,0,1,1):   // ldrh
+            nm = "ldrh"; ty = Ity_I16; break;
+         case BITS5(1,1,0,1,1):   // ldrsh
+            nm = "ldrsh"; ty = Ity_I16; syned = True; break;
+         case BITS5(0,1,1,0,0):   // str
+            nm = "str"; ty = Ity_I32; isST = True; break;
+         case BITS5(0,1,1,0,1):
+            nm = "ldr"; ty = Ity_I32; break;  // ldr
+         default:
+            valid = False; break;
+      }
+
+      UInt rN      = INSN0(3,0);
+      UInt rT      = INSN1(15,12);
+      UInt imm12   = INSN1(11,0);
+      Bool loadsPC = False;
+
+      if (ty == Ity_I8 || ty == Ity_I16) {
+         /* all 8- and 16-bit load and store cases have the
+            same exclusion set. */
+         if (rN == 15 || isBadRegT(rT))
+            valid = False;

       } else {
       } else {

-         IRTemp srcL = newTemp(Ity_I32);
-         IRTemp srcR = newTemp(Ity_I32);
-         IRTemp res  = newTemp(Ity_I32);
+         vassert(ty == Ity_I32);
+         if (isST) {
+            if (rN == 15 || rT == 15)
+               valid = False;
+         } else {
+            /* For a 32-bit load, rT == 15 is only allowable if we not
+               in an IT block, or are the last in it.  Need to insert
+               a dynamic check for that.  Also, in this particular
+               case, rN == 15 is allowable.  In this case however, the
+               value obtained for rN is (apparently)
+               "word-align(address of current insn + 4)". */
+            if (rT == 15)
+               loadsPC = True;
+         }
+      }

 
 

-         /* Extract and sign extend the two 16-bit operands */
-         assign(srcL, binop(Iop_Sar32,
-                            binop(Iop_Shl32, getIReg(rN),
-                                             mkU8(bN ? 0 : 16)),
-                            mkU8(16)));
-         assign(srcR, binop(Iop_Sar32,
-                            binop(Iop_Shl32, getIReg(rM),
-                                             mkU8(bM ? 0 : 16)),
-                            mkU8(16)));
+      if (valid) {
+         // if it's a branch, it can't happen in the middle of an IT block
+         if (loadsPC)
+            gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+         // go uncond
+         mk_skip_over_T32_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         // now uncond

 
 

-         assign(res, binop(Iop_Mul32, mkexpr(srcL), mkexpr(srcR)));
-         putIReg(rD, mkexpr(res), condT, Ijk_Boring);
+         IRTemp rNt = newTemp(Ity_I32);
+         if (rN == 15) {
+            vassert(ty == Ity_I32 && !isST);
+            assign(rNt, binop(Iop_And32, getIRegT(rN), mkU32(~3)));
+         } else {
+            assign(rNt, getIRegT(rN));
+         }
+
+         IRTemp transAddr = newTemp(Ity_I32);
+         assign(transAddr,
+                binop( Iop_Add32, mkexpr(rNt), mkU32(imm12) ));
+
+         if (isST) {
+            IRTemp oldRt = newTemp(Ity_I32);
+            assign(oldRt, getIRegT(rT));
+            switch (ty) {
+               case Ity_I8:
+                  storeLE(mkexpr(transAddr),
+                                 unop(Iop_32to8, mkexpr(oldRt)));
+                  break;
+               case Ity_I16:
+                  storeLE(mkexpr(transAddr),
+                          unop(Iop_32to16, mkexpr(oldRt)));
+                  break;
+              case Ity_I32:
+                  storeLE(mkexpr(transAddr), mkexpr(oldRt));
+                  break;
+              default:
+                 vassert(0);
+            }
+         } else {
+            IRTemp newRt = newTemp(Ity_I32);
+            IROp   widen = Iop_INVALID;
+            switch (ty) {
+               case Ity_I8:
+                  widen = syned ? Iop_8Sto32 : Iop_8Uto32; break;
+               case Ity_I16:
+                  widen = syned ? Iop_16Sto32 : Iop_16Uto32; break;
+               case Ity_I32:
+                  break;
+               default:
+                  vassert(0);
+            }
+            if (widen == Iop_INVALID) {
+               assign(newRt, loadLE(ty, mkexpr(transAddr)));
+            } else {
+               assign(newRt, unop(widen, loadLE(ty, mkexpr(transAddr))));
+            }
+            putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
+
+            if (loadsPC) {
+               /* Presumably this is an interworking branch. */
+               irsb->next = mkexpr(newRt);
+               irsb->jumpkind = Ijk_Boring;  /* or _Ret ? */
+               dres.whatNext  = Dis_StopHere;
+            }
+         }
+
+         DIP("%s.w r%u, [r%u, +#%u]\n", nm, rT, rN, imm12);

 
 

-         DIP("smul%c%c%s r%u, r%u, r%u\n",
-             bN ? 't' : 'b', bM ? 't' : 'b', nCC(INSN_COND), rD, rN, rM);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   /* --------------------- Load/store doubleword ------------- */
-   // LDRD STRD
-   /*                 31   27   23   19 15 11   7    3     # highest bit
-                        28   24   20 16 12    8    4    0
-      A5-36   1 | 16  cond 0001 U100 Rn Rd im4h 11S1 im4l
-      A5-38   1 | 32  cond 0001 U000 Rn Rd 0000 11S1 Rm
-      A5-40   2 | 16  cond 0001 U110 Rn Rd im4h 11S1 im4l
-      A5-42   2 | 32  cond 0001 U010 Rn Rd 0000 11S1 Rm
-      A5-44   3 | 16  cond 0000 U100 Rn Rd im4h 11S1 im4l
-      A5-46   3 | 32  cond 0000 U000 Rn Rd 0000 11S1 Rm
-   */
-   /* case coding:
-             1   at-ea               (access at ea)
-             2   at-ea-then-upd      (access at ea, then Rn = ea)
-             3   at-Rn-then-upd      (access at Rn, then Rn = ea)
-      ea coding
-             16  Rn +/- imm8
-             32  Rn +/- Rm
+   /* -------------- LDRD/STRD reg+/-#imm8 -------------- */
+   /* Doubleword loads and stores of the form:
+         ldrd/strd  Rt, Rt2, [Rn, #-imm8]      or
+         ldrd/strd  Rt, Rt2, [Rn], #+/-imm8    or
+         ldrd/strd  Rt, Rt2, [Rn, #+/-imm8]!  

    */
    */

-   /* Quickly skip over all of this for hopefully most instructions */
-   if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0))
-      goto after_load_store_doubleword;
+   if (INSN0(15,9) == BITS7(1,1,1,0,1,0,0) && INSN0(6,6) == 1) {
+      UInt bP   = INSN0(8,8);
+      UInt bU   = INSN0(7,7);
+      UInt bW   = INSN0(5,5);
+      UInt bL   = INSN0(4,4);  // 1: load  0: store
+      UInt rN   = INSN0(3,0);
+      UInt rT   = INSN1(15,12);
+      UInt rT2  = INSN1(11,8);
+      UInt imm8 = INSN1(7,0);
+
+      Bool valid = True;
+      if (bP == 0 && bW == 0)                 valid = False;
+      if (bW == 1 && (rN == rT || rN == rT2)) valid = False;
+      if (isBadRegT(rT) || isBadRegT(rT2))    valid = False;
+      if (rN == 15)                           valid = False;
+      if (bL == 1 && rT == rT2)               valid = False;
+
+      if (valid) {
+         // go uncond
+         mk_skip_over_T32_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         // now uncond
+
+         IRTemp preAddr = newTemp(Ity_I32);
+         assign(preAddr, getIRegT(rN));
+
+         IRTemp postAddr = newTemp(Ity_I32);
+         assign(postAddr, binop(bU == 1 ? Iop_Add32 : Iop_Sub32,
+                                mkexpr(preAddr), mkU32(imm8 << 2)));
+
+         IRTemp transAddr = bP == 1 ? postAddr : preAddr;
+
+         if (bL == 0) {
+            IRTemp oldRt  = newTemp(Ity_I32);
+            IRTemp oldRt2 = newTemp(Ity_I32);
+            assign(oldRt,  getIRegT(rT));
+            assign(oldRt2, getIRegT(rT2));
+            storeLE(mkexpr(transAddr),
+                    mkexpr(oldRt));
+            storeLE(binop(Iop_Add32, mkexpr(transAddr), mkU32(4)),
+                    mkexpr(oldRt2));
+         } else {
+            IRTemp newRt  = newTemp(Ity_I32);
+            IRTemp newRt2 = newTemp(Ity_I32);
+            assign(newRt,
+                   loadLE(Ity_I32,
+                          mkexpr(transAddr)));
+            assign(newRt2,
+                   loadLE(Ity_I32,
+                          binop(Iop_Add32, mkexpr(transAddr), mkU32(4))));
+            putIRegT(rT,  mkexpr(newRt), IRTemp_INVALID);
+            putIRegT(rT2, mkexpr(newRt2), IRTemp_INVALID);
+         }

 
 

-   /* Check the "11S1" thing. */
-   if ((INSN(7,4) & BITS4(1,1,0,1)) != BITS4(1,1,0,1))
-      goto after_load_store_doubleword;
+         if (bW == 1) {
+            putIRegT(rN, mkexpr(postAddr), IRTemp_INVALID);
+         }

 
 

-   summary = 0;
+         HChar* nm = bL ? "ldrd" : "strd";

 
 

-   /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(1,0,0)) {
-      summary = 1 | 16;
-   }
-   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(0,0,0)) {
-      summary = 1 | 32;
-   }
-   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(1,1,0)) {
-      summary = 2 | 16;
-   }
-   else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(0,1,0)) {
-      summary = 2 | 32;
-   }
-   else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(1,0,0)) {
-      summary = 3 | 16;
+         if (bP == 1 && bW == 0) {
+            DIP("%s.w r%u, r%u, [r%u, #%c%u]\n",
+                nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
+         }
+         else if (bP == 1 && bW == 1) {
+            DIP("%s.w r%u, r%u, [r%u, #%c%u]!\n",
+                nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
+         }
+         else {
+            vassert(bP == 0 && bW == 1);
+            DIP("%s.w r%u, r%u, [r%u], #%c%u\n",
+                nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
+         }
+
+         goto decode_success;
+      }

    }
    }

-   else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(0,0,0)) {
-      summary = 3 | 32;
-      goto decode_failure; //ATC
+
+   /* -------------- (T3) Bcond.W label -------------- */
+   /* This variant carries its own condition, so can't be part of an
+      IT block ... */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && INSN1(15,14) == BITS2(1,0)
+       && INSN1(12,12) == 0) {
+      UInt cond = INSN0(9,6);
+      if (cond != ARMCondAL && cond != ARMCondNV) {
+         Int simm21
+            =   (INSN0(10,10) << (1 + 1 + 6 + 11 + 1))
+              | (INSN1(11,11) << (1 + 6 + 11 + 1))
+              | (INSN1(13,13) << (6 + 11 + 1))
+              | (INSN0(5,0)   << (11 + 1))
+              | (INSN1(10,0)  << 1);
+         simm21 = (simm21 << 11) >> 11;
+
+         vassert(0 == (guest_R15_curr_instr_notENC & 1));
+         UInt dst = simm21 + guest_R15_curr_instr_notENC + 4;
+
+         /* Not allowed in an IT block; SIGILL if so. */
+         gen_SIGILL_T_if_in_ITBlock(old_itstate, new_itstate);
+
+         IRTemp kondT = newTemp(Ity_I32);
+         assign( kondT, mk_armg_calculate_condition(cond) );
+         stmt( IRStmt_Exit( unop(Iop_32to1, mkexpr(kondT)),
+                            Ijk_Boring,
+                            IRConst_U32(dst | 1/*CPSR.T*/) ));
+         irsb->next = mkU32( (guest_R15_curr_instr_notENC + 4) 
+                             | 1 /*CPSR.T*/ );
+         irsb->jumpkind = Ijk_Boring;
+         dres.whatNext  = Dis_StopHere;
+         DIP("b%s.w 0x%x\n", nCC(cond), dst);
+         goto decode_success;
+      }

    }
    }

-   else goto after_load_store_doubleword;

 
 

-   { UInt rN   = (insn >> 16) & 0xF; /* 19:16 */
-     UInt rD   = (insn >> 12) & 0xF; /* 15:12 */
-     UInt rM   = (insn >> 0)  & 0xF; /*  3:0  */
-     UInt bU   = (insn >> 23) & 1;   /* 23 U=1 offset+, U=0 offset- */
-     UInt bS   = (insn >> 5) & 1;    /* S=1 store, S=0 load */
-     UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */
+   /* ---------------- (T4) B.W label ---------------- */
+   /* ... whereas this variant doesn't carry its own condition, so it
+      has to be either unconditional or the conditional by virtue of
+      being the last in an IT block.  The upside is that there's 4
+      more bits available for the jump offset, so it has a 16-times
+      greater branch range than the T3 variant. */
+   if (INSN0(15,11) == BITS5(1,1,1,1,0)
+       && INSN1(15,14) == BITS2(1,0)
+       && INSN1(12,12) == 1) {
+      if (1) {
+         UInt bS  = INSN0(10,10);
+         UInt bJ1 = INSN1(13,13);
+         UInt bJ2 = INSN1(11,11);
+         UInt bI1 = 1 ^ (bJ1 ^ bS);
+         UInt bI2 = 1 ^ (bJ2 ^ bS);
+         Int simm25
+            =   (bS          << (1 + 1 + 10 + 11 + 1))
+              | (bI1         << (1 + 10 + 11 + 1))
+              | (bI2         << (10 + 11 + 1))
+              | (INSN0(9,0)  << (11 + 1))
+              | (INSN1(10,0) << 1);
+         simm25 = (simm25 << 7) >> 7;
+
+         vassert(0 == (guest_R15_curr_instr_notENC & 1));
+         UInt dst = simm25 + guest_R15_curr_instr_notENC + 4;
+
+         /* If in an IT block, must be the last insn. */
+         gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+
+         // go uncond
+         mk_skip_over_T32_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;
+         // now uncond

 
 

-     /* Require rD to be an even numbered register */
-     if ((rD & 1) != 0)
-        goto after_load_store_doubleword;
+         // branch to dst
+         irsb->next = mkU32( dst | 1 /*CPSR.T*/ );
+         irsb->jumpkind = Ijk_Boring;
+         dres.whatNext  = Dis_StopHere;
+         DIP("b.w 0x%x\n", dst);
+         goto decode_success;
+      }
+   }

 
 

-     /* Require 11:8 == 0 for Rn +/- Rm cases */
-     if ((summary & 32) != 0 && (imm8 & 0xF0) != 0)
-        goto after_load_store_doubleword;
+   /* ------------------ TBB, TBH ------------------ */
+   if (INSN0(15,4) == 0xE8D && INSN1(15,5) == 0x780) {
+      UInt rN = INSN0(3,0);
+      UInt rM = INSN1(3,0);
+      UInt bH = INSN1(4,4);
+      if (bH/*ATC*/ || (rN != 13 && !isBadRegT(rM))) {
+         /* Must be last or not-in IT block */
+         gen_SIGILL_T_if_in_but_NLI_ITBlock(old_itstate, new_itstate);
+         /* Go uncond */
+         mk_skip_over_T32_if_cond_is_false(condT);
+         condT = IRTemp_INVALID;

 
 

-     /* Skip some invalid cases, which would lead to two competing
-        updates to the same register, or which are otherwise
-        disallowed by the spec. */
-     switch (summary) {
-        case 1 | 16:
-           break;
-        case 1 | 32: 
-           if (rM == 15) goto after_load_store_doubleword;
-           break;
-        case 2 | 16: case 3 | 16:
-           if (rN == 15) goto after_load_store_doubleword;
-           if (bS == 0 && (rN == rD || rN == rD+1))
-              goto after_load_store_doubleword;
-           break;
-        case 2 | 32: case 3 | 32:
-           if (rM == 15) goto after_load_store_doubleword;
-           if (rN == 15) goto after_load_store_doubleword;
-           if (rN == rM) goto after_load_store_doubleword;
-           if (bS == 0 && (rN == rD || rN == rD+1))
-              goto after_load_store_doubleword;
-           break;
-        default:
-           vassert(0);
-     }
+         IRExpr* ea
+             = binop(Iop_Add32,
+                     getIRegT(rN),
+                     bH ? binop(Iop_Shl32, getIRegT(rM), mkU8(1))
+                        : getIRegT(rM));

 
 

-     /* Now, we can't do a conditional load or store, since that very
-        likely will generate an exception.  So we have to take a side
-        exit at this point if the condition is false. */
-     if (condT != IRTemp_INVALID) {
-        mk_skip_to_next_if_cond_is_false( condT );
-        condT = IRTemp_INVALID;
-     }
-     /* Ok, now we're unconditional.  Do the load or store. */
+         IRTemp delta = newTemp(Ity_I32);
+         if (bH) {
+            assign(delta, unop(Iop_16Uto32, loadLE(Ity_I16, ea)));
+         } else {
+            assign(delta, unop(Iop_8Uto32, loadLE(Ity_I8, ea)));
+         }

 
 

-     /* compute the effective address.  Bind it to a tmp since we
-        may need to use it twice. */
-     IRExpr* eaE = NULL;
-     switch (summary & 0xF0) {
-        case 16:
-           eaE = mk_EA_reg_plusminus_imm8( rN, bU, imm8, dis_buf );
-           break;
-        case 32:
-           eaE = mk_EA_reg_plusminus_reg( rN, bU, rM, dis_buf );
-           break;
-     }
-     vassert(eaE);
-     IRTemp eaT = newTemp(Ity_I32);
-     assign(eaT, eaE);
+         irsb->next
+            = binop(Iop_Or32,
+                    binop(Iop_Add32,
+                          getIRegT(15),
+                          binop(Iop_Shl32, mkexpr(delta), mkU8(1))
+                    ),
+                    mkU32(1)
+              );
+         irsb->jumpkind = Ijk_Boring;
+         dres.whatNext = Dis_StopHere;
+         DIP("tb%c [r%u, r%u%s]\n",
+             bH ? 'h' : 'b', rN, rM, bH ? ", LSL #1" : "");
+         goto decode_success;
+      }
+   }
+
+   /* ------------------ UBFX ------------------ */
+   /* ------------------ SBFX ------------------ */
+   /* There's also ARM versions of same, but it doesn't seem worth the
+      hassle to common up the handling (it's only a couple of C
+      statements). */
+   if ((INSN0(15,4) == 0xF3C // UBFX
+        || INSN0(15,4) == 0xF34) // SBFX
+       && INSN1(15,15) == 0 && INSN1(5,5) == 0) {
+      UInt rN  = INSN0(3,0);
+      UInt rD  = INSN1(11,8);
+      UInt lsb = (INSN1(14,12) << 2) | INSN1(7,6);
+      UInt wm1 = INSN1(4,0);
+      UInt msb =  lsb + wm1;
+      if (!isBadRegT(rD) && !isBadRegT(rN) && msb <= 31) {
+         Bool   isU  = INSN0(15,4) == 0xF3C;
+         IRTemp src  = newTemp(Ity_I32);
+         IRTemp tmp  = newTemp(Ity_I32);
+         IRTemp res  = newTemp(Ity_I32);
+         UInt   mask = ((1 << wm1) - 1) + (1 << wm1);
+         vassert(msb >= 0 && msb <= 31);
+         vassert(mask != 0); // guaranteed by msb being in 0 .. 31 inclusive

 
 

-     /* get the old Rn value */
-     IRTemp rnT = newTemp(Ity_I32);
-     assign(rnT, getIReg(rN));
+         assign(src, getIRegT(rN));
+         assign(tmp, binop(Iop_And32,
+                           binop(Iop_Shr32, mkexpr(src), mkU8(lsb)),
+                           mkU32(mask)));
+         assign(res, binop(isU ? Iop_Shr32 : Iop_Sar32,
+                           binop(Iop_Shl32, mkexpr(tmp), mkU8(31-wm1)),
+                           mkU8(31-wm1)));

 
 

-     /* decide on the transfer address */
-     IRTemp taT = IRTemp_INVALID;
-     switch (summary & 0x0F) {
-        case 1: case 2: taT = eaT; break;
-        case 3:         taT = rnT; break;
-     }
-     vassert(taT != IRTemp_INVALID);
+         putIRegT(rD, mkexpr(res), condT);

 
 

-     /* XXX deal with alignment constraints */
-     /* XXX: but the A8 doesn't seem to trap for misaligned loads, so,
-        ignore alignment issues for the time being. */
+         DIP("%s r%u, r%u, #%u, #%u\n",
+             isU ? "ubfx" : "sbfx", rD, rN, lsb, wm1 + 1);
+         goto decode_success;
+      }
+   }

 
 

-     /* doubleword store  S 1
-        doubleword load   S 0
-     */
-     HChar* name = NULL;
-     /* generate the transfers */
-     if (bS == 1) { // doubleword store
-        storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(0)), getIReg(rD+0) );
-        storeLE( binop(Iop_Add32, mkexpr(taT), mkU32(4)), getIReg(rD+1) );
-        name = "strd";
-     } else { // doubleword load
-        putIReg( rD+0,
-                 loadLE(Ity_I32, binop(Iop_Add32, mkexpr(taT), mkU32(0))),
-                 IRTemp_INVALID, Ijk_Boring );
-        putIReg( rD+1,
-                 loadLE(Ity_I32, binop(Iop_Add32, mkexpr(taT), mkU32(4))),
-                 IRTemp_INVALID, Ijk_Boring );
-        name = "ldrd";
-     }
+   /* ------------------ UXTB ------------------ */
+   /* ------------------ UXTH ------------------ */
+   /* ------------------ SXTB ------------------ */
+   /* ------------------ SXTH ------------------ */
+   if ((INSN0(15,0) == 0xFA5F     // UXTB
+        || INSN0(15,0) == 0xFA1F  // UXTH
+        || INSN0(15,0) == 0xFA4F  // SXTB
+        || INSN0(15,0) == 0xFA0F) // SXTH
+       && INSN1(15,12) == BITS4(1,1,1,1)
+       && INSN1(7,6) == BITS2(1,0)) {
+      UInt rD = INSN1(11,8);
+      UInt rM = INSN1(3,0);
+      UInt rot = INSN1(5,4);
+      if (!isBadRegT(rD) && !isBadRegT(rM)) {
+         HChar* nm = "???";
+         IRTemp srcT = newTemp(Ity_I32);
+         IRTemp rotT = newTemp(Ity_I32);
+         IRTemp dstT = newTemp(Ity_I32);
+         assign(srcT, getIRegT(rM));
+         assign(rotT, genROR32(srcT, 8 * rot));
+         switch (INSN0(15,0)) {
+            case 0xFA5F: // UXTB
+               nm = "uxtb";
+               assign(dstT, unop(Iop_8Uto32,
+                                 unop(Iop_32to8, mkexpr(rotT))));
+               break;
+            case 0xFA1F: // UXTH
+               nm = "uxth";
+               assign(dstT, unop(Iop_16Uto32,
+                                 unop(Iop_32to16, mkexpr(rotT))));
+               break;
+            case 0xFA4F: // SXTB
+               nm = "sxtb";
+               assign(dstT, unop(Iop_8Sto32,
+                                 unop(Iop_32to8, mkexpr(rotT))));
+               break;
+            case 0xFA0F: // SXTH
+               nm = "sxth";
+               assign(dstT, unop(Iop_16Sto32,
+                                 unop(Iop_32to16, mkexpr(rotT))));
+               break;
+            default:
+               vassert(0);
+         }
+         putIRegT(rD, mkexpr(dstT), condT);
+         DIP("%s r%u, r%u, ror #%u\n", nm, rD, rM, 8 * rot);
+         goto decode_success;
+      }
+   }

 
 

-     /* Update Rn if necessary. */
-     switch (summary & 0x0F) {
-        case 2: case 3:
-           // should be assured by logic above:
-           if (bS == 0) {
-              vassert(rD+0 != rN); /* since we just wrote rD+0 */
-              vassert(rD+1 != rN); /* since we just wrote rD+1 */
-           }
-           putIReg( rN, mkexpr(eaT), IRTemp_INVALID, Ijk_Boring );
-           break;
-     }
+   /* -------------- MUL.W Rd, Rn, Rm -------------- */
+   if (INSN0(15,4) == 0xFB0
+       && (INSN1(15,0) & 0xF0F0) == 0xF000) {
+      UInt rN = INSN0(3,0);
+      UInt rD = INSN1(11,8);
+      UInt rM = INSN1(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
+         IRTemp res = newTemp(Ity_I32);
+         assign(res, binop(Iop_Mul32, getIRegT(rN), getIRegT(rM)));
+         putIRegT(rD, mkexpr(res), condT);
+         DIP("mul.w r%u, r%u, r%u\n", rD, rN, rM);
+         goto decode_success;
+      }
+   }

 
 

-     switch (summary & 0x0F) {
-        case 1:  DIP("%s%s r%u, %s\n", name, nCC(INSN_COND), rD, dis_buf);
-                 break;
-        case 2:  DIP("%s%s r%u, %s! (at-EA-then-Rn=EA)\n",
-                     name, nCC(INSN_COND), rD, dis_buf);
-                 break;
-        case 3:  DIP("%s%s r%u, %s! (at-Rn-then-Rn=EA)\n",
-                     name, nCC(INSN_COND), rD, dis_buf);
-                 break;
-        default: vassert(0);
-     }
+   /* ------------------ {U,S}MULL ------------------ */
+   if ((INSN0(15,4) == 0xFB8 || INSN0(15,4) == 0xFBA)
+       && INSN1(7,4) == BITS4(0,0,0,0)) {
+      UInt isU  = INSN0(5,5);
+      UInt rN   = INSN0(3,0);
+      UInt rDlo = INSN1(15,12);
+      UInt rDhi = INSN1(11,8);
+      UInt rM   = INSN1(3,0);
+      if (!isBadRegT(rDhi) && !isBadRegT(rDlo)
+          && !isBadRegT(rN) && !isBadRegT(rM) && rDlo != rDhi) {
+         IRTemp res   = newTemp(Ity_I64);
+         assign(res, binop(isU ? Iop_MullU32 : Iop_MullS32,
+                           getIRegT(rN), getIRegT(rM)));
+         putIRegT( rDhi, unop(Iop_64HIto32, mkexpr(res)), condT );
+         putIRegT( rDlo, unop(Iop_64to32, mkexpr(res)), condT );
+         DIP("%cmull r%u, r%u, r%u, r%u\n",
+             isU ? 'u' : 's', rDlo, rDhi, rN, rM);
+         goto decode_success;
+      }
+   }

 
 

-     goto decode_success;
+   /* ------------------ ML{A,S} ------------------ */
+   if (INSN0(15,4) == 0xFB0
+       && (   INSN1(7,4) == BITS4(0,0,0,0)    // MLA
+           || INSN1(7,4) == BITS4(0,0,0,1))) { // MLS
+      UInt rN = INSN0(3,0);
+      UInt rA = INSN1(15,12);
+      UInt rD = INSN1(11,8);
+      UInt rM = INSN1(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rN)
+          && !isBadRegT(rM) && !isBadRegT(rA)) {
+         Bool   isMLA = INSN1(7,4) == BITS4(0,0,0,0);
+         IRTemp res   = newTemp(Ity_I32);
+         assign(res,
+                binop(isMLA ? Iop_Add32 : Iop_Sub32,
+                      getIRegT(rA),
+                      binop(Iop_Mul32, getIRegT(rN), getIRegT(rM))));
+         putIRegT(rD, mkexpr(res), condT);
+         DIP("%s r%u, r%u, r%u, r%u\n",
+             isMLA ? "mla" : "mls", rD, rN, rM, rA);
+         goto decode_success;
+      }

    }
 
    }
 

-  after_load_store_doubleword:
+   /* ------------------ (T3) ADR ------------------ */
+   if ((INSN0(15,0) == 0xF20F || INSN0(15,0) == 0xF60F)
+       && INSN1(15,15) == 0) {
+      /* rD = align4(PC) + imm32 */
+      UInt rD = INSN1(11,8);
+      if (!isBadRegT(rD)) {
+         UInt imm32 = (INSN0(10,10) << 11)
+                      | (INSN1(14,12) << 8) | INSN1(7,0);
+         putIRegT(rD, binop(Iop_Add32, 
+                            binop(Iop_And32, getIRegT(15), mkU32(~3U)),
+                            mkU32(imm32)),
+                      condT);
+         DIP("add r%u, pc, #%u\n", rD, imm32);
+         goto decode_success;
+      }
+   }

 
 

-   /* ------------------- {s,u}xtab ------------- */
-   if (BITS8(0,1,1,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(0,0,0,0) == (INSN(11,8) & BITS4(0,0,1,1))
-       && BITS4(0,1,1,1) == INSN(7,4)) {
-      UInt rN  = INSN(19,16);
-      UInt rD  = INSN(15,12);
-      UInt rM  = INSN(3,0);
-      UInt rot = (insn >> 10) & 3;
-      UInt isU = INSN(22,22);
-      if (rN == 15/*it's {S,U}XTB*/ || rD == 15 || rM == 15) {
+   /* ----------------- (T1) UMLAL ----------------- */
+   /* ----------------- (T1) SMLAL ----------------- */
+   if ((INSN0(15,4) == 0xFBE // UMLAL
+        || INSN0(15,4) == 0xFBC) // SMLAL
+       && INSN1(7,4) == BITS4(0,0,0,0)) {
+      UInt rN   = INSN0(3,0);
+      UInt rDlo = INSN1(15,12);
+      UInt rDhi = INSN1(11,8);
+      UInt rM   = INSN1(3,0);
+      if (!isBadRegT(rDlo) && !isBadRegT(rDhi) && !isBadRegT(rN)
+          && !isBadRegT(rM) && rDhi != rDlo) {
+         Bool   isS   = INSN0(15,4) == 0xFBC;
+         IRTemp argL  = newTemp(Ity_I32);
+         IRTemp argR  = newTemp(Ity_I32);
+         IRTemp old   = newTemp(Ity_I64);
+         IRTemp res   = newTemp(Ity_I64);
+         IRTemp resHi = newTemp(Ity_I32);
+         IRTemp resLo = newTemp(Ity_I32);
+         IROp   mulOp = isS ? Iop_MullS32 : Iop_MullU32;
+         assign( argL, getIRegT(rM));
+         assign( argR, getIRegT(rN));
+         assign( old, binop(Iop_32HLto64, getIRegT(rDhi), getIRegT(rDlo)) );
+         assign( res, binop(Iop_Add64,
+                            mkexpr(old),
+                            binop(mulOp, mkexpr(argL), mkexpr(argR))) );
+         assign( resHi, unop(Iop_64HIto32, mkexpr(res)) );
+         assign( resLo, unop(Iop_64to32, mkexpr(res)) );
+         putIRegT( rDhi, mkexpr(resHi), condT );
+         putIRegT( rDlo, mkexpr(resLo), condT );
+         DIP("%cmlal r%u, r%u, r%u, r%u\n",
+             isS ? 's' : 'u', rDlo, rDhi, rN, rM);
+         goto decode_success;
+      }
+   }
+
+   /* ------------------ (T2) ADR ------------------ */
+   if ((INSN0(15,0) == 0xF2AF || INSN0(15,0) == 0xF6AF)
+       && INSN1(15,15) == 0) {
+      /* rD = align4(PC) - imm32 */
+      UInt rD = INSN1(11,8);
+      if (!isBadRegT(rD)) {
+         UInt imm32 = (INSN0(10,10) << 11)
+                      | (INSN1(14,12) << 8) | INSN1(7,0);
+         putIRegT(rD, binop(Iop_Sub32, 
+                            binop(Iop_And32, getIRegT(15), mkU32(~3U)),
+                            mkU32(imm32)),
+                      condT);
+         DIP("sub r%u, pc, #%u\n", rD, imm32);
+         goto decode_success;
+      }
+   }
+
+   /* ------------------- (T1) BFI ------------------- */
+   /* ------------------- (T1) BFC ------------------- */
+   if (INSN0(15,4) == 0xF36 && INSN1(15,15) == 0 && INSN1(5,5) == 0) {
+      UInt rD  = INSN1(11,8);
+      UInt rN  = INSN0(3,0);
+      UInt msb = INSN1(4,0);
+      UInt lsb = (INSN1(14,12) << 2) | INSN1(7,6);
+      if (isBadRegT(rD) || rN == 13 || msb < lsb) {

          /* undecodable; fall through */
       } else {
          /* undecodable; fall through */
       } else {

+         IRTemp src    = newTemp(Ity_I32);
+         IRTemp olddst = newTemp(Ity_I32);
+         IRTemp newdst = newTemp(Ity_I32);
+         UInt   mask = 1 << (msb - lsb);
+         mask = (mask - 1) + mask;
+         vassert(mask != 0); // guaranteed by "msb < lsb" check above
+         mask <<= lsb;
+
+         assign(src, rN == 15 ? mkU32(0) : getIRegT(rN));
+         assign(olddst, getIRegT(rD));
+         assign(newdst,
+                binop(Iop_Or32,
+                   binop(Iop_And32,
+                         binop(Iop_Shl32, mkexpr(src), mkU8(lsb)), 
+                         mkU32(mask)),
+                   binop(Iop_And32,
+                         mkexpr(olddst),
+                         mkU32(~mask)))
+               );
+
+         putIRegT(rD, mkexpr(newdst), condT);
+
+         if (rN == 15) {
+            DIP("bfc r%u, #%u, #%u\n",
+                rD, lsb, msb-lsb+1);
+         } else {
+            DIP("bfi r%u, r%u, #%u, #%u\n",
+                rD, rN, lsb, msb-lsb+1);
+         }
+         goto decode_success;
+      }
+   }
+
+   /* ------------------- (T1) SMULBB ------------------- */
+   if (INSN0(15,4) == 0xFB1
+       && INSN1(15,12) == BITS4(1,1,1,1)
+       && INSN1(7,6) == BITS2(0,0)
+       && INSN1(5,4) == BITS2(0,0)) { // other values -> BT/TB/TT
+      UInt rN = INSN0(3,0);
+      UInt rD = INSN1(11,8);
+      UInt rM = INSN1(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {
+         putIRegT(rD,
+                  binop(Iop_Mul32,
+                        unop(Iop_16Sto32,
+                             unop(Iop_32to16, getIRegT(rN))),
+                        unop(Iop_16Sto32,
+                             unop(Iop_32to16, getIRegT(rM)))),
+                  condT);
+         DIP("smulbb r%u, r%u, r%u\n", rD, rN, rM);
+         goto decode_success;
+      }
+   }
+
+   /* ------------------- (T1) SXTAH ------------------- */
+   /* ------------------- (T1) UXTAH ------------------- */
+   if ((INSN0(15,4) == 0xFA1      // UXTAH
+        || INSN0(15,4) == 0xFA0)  // SXTAH
+       && INSN1(15,12) == BITS4(1,1,1,1)
+       && INSN1(7,6) == BITS2(1,0)) {
+      Bool isU = INSN0(15,4) == 0xFA1;
+      UInt rN  = INSN0(3,0);
+      UInt rD  = INSN1(11,8);
+      UInt rM  = INSN1(3,0);
+      UInt rot = INSN1(5,4);
+      if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {

          IRTemp srcL = newTemp(Ity_I32);
          IRTemp srcR = newTemp(Ity_I32);
          IRTemp res  = newTemp(Ity_I32);
          IRTemp srcL = newTemp(Ity_I32);
          IRTemp srcR = newTemp(Ity_I32);
          IRTemp res  = newTemp(Ity_I32);

-         assign(srcR, getIReg(rM));
-         assign(srcL, getIReg(rN));
+         assign(srcR, getIRegT(rM));
+         assign(srcL, getIRegT(rN));

          assign(res,  binop(Iop_Add32,
                             mkexpr(srcL),
          assign(res,  binop(Iop_Add32,
                             mkexpr(srcL),

-                            unop(isU ? Iop_8Uto32 : Iop_8Sto32,
-                                 unop(Iop_32to8, 
+                            unop(isU ? Iop_16Uto32 : Iop_16Sto32,
+                                 unop(Iop_32to16, 

                                       genROR32(srcR, 8 * rot)))));
                                       genROR32(srcR, 8 * rot)))));

-         putIReg(rD, mkexpr(res), condT, Ijk_Boring);
-         DIP("%cxtab%s r%u, r%u, r%u, ror #%u\n",
-             isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
+         putIRegT(rD, mkexpr(res), condT);
+         DIP("%cxtah r%u, r%u, r%u, ror #%u\n",
+             isU ? 'u' : 's', rD, rN, rM, rot);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   /* ------------------- {s,u}xtah ------------- */
-   if (BITS8(0,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
-       && BITS4(0,0,0,0) == (INSN(11,8) & BITS4(0,0,1,1))
-       && BITS4(0,1,1,1) == INSN(7,4)) {
-      UInt rN  = INSN(19,16);
-      UInt rD  = INSN(15,12);
-      UInt rM  = INSN(3,0);
-      UInt rot = (insn >> 10) & 3;
-      UInt isU = INSN(22,22);
-      if (rN == 15/*it's {S,U}XTH*/ || rD == 15 || rM == 15) {
-         /* undecodable; fall through */
-      } else {
+   /* ------------------- (T1) SXTAB ------------------- */
+   /* ------------------- (T1) UXTAB ------------------- */
+   if ((INSN0(15,4) == 0xFA5      // UXTAB
+        || INSN0(15,4) == 0xFA4)  // SXTAB
+       && INSN1(15,12) == BITS4(1,1,1,1)
+       && INSN1(7,6) == BITS2(1,0)) {
+      Bool isU = INSN0(15,4) == 0xFA5;
+      UInt rN  = INSN0(3,0);
+      UInt rD  = INSN1(11,8);
+      UInt rM  = INSN1(3,0);
+      UInt rot = INSN1(5,4);
+      if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM)) {

          IRTemp srcL = newTemp(Ity_I32);
          IRTemp srcR = newTemp(Ity_I32);
          IRTemp res  = newTemp(Ity_I32);
          IRTemp srcL = newTemp(Ity_I32);
          IRTemp srcR = newTemp(Ity_I32);
          IRTemp res  = newTemp(Ity_I32);

-         assign(srcR, getIReg(rM));
-         assign(srcL, getIReg(rN));
+         assign(srcR, getIRegT(rM));
+         assign(srcL, getIRegT(rN));

          assign(res,  binop(Iop_Add32,
                             mkexpr(srcL),
          assign(res,  binop(Iop_Add32,
                             mkexpr(srcL),

-                            unop(isU ? Iop_16Uto32 : Iop_16Sto32,
-                                 unop(Iop_32to16, 
+                            unop(isU ? Iop_8Uto32 : Iop_8Sto32,
+                                 unop(Iop_32to8, 

                                       genROR32(srcR, 8 * rot)))));
                                       genROR32(srcR, 8 * rot)))));

-         putIReg(rD, mkexpr(res), condT, Ijk_Boring);
-
-         DIP("%cxtah%s r%u, r%u, r%u, ror #%u\n",
-             isU ? 'u' : 's', nCC(INSN_COND), rD, rN, rM, rot);
+         putIRegT(rD, mkexpr(res), condT);
+         DIP("%cxtab r%u, r%u, r%u, ror #%u\n",
+             isU ? 'u' : 's', rD, rN, rM, rot);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   /* ----------------------------------------------------------- */
-   /* -- ARMv7 instructions                                    -- */
-   /* ----------------------------------------------------------- */
-
-   /* -------------- read CP15 TPIDRURO register ------------- */
-   /* mrc     p15, 0, r0, c13, c0, 3  up to
-      mrc     p15, 0, r14, c13, c0, 3
-   */
-   /* I don't know whether this is really v7-only.  But anyway, we
-      have to support it since arm-linux uses TPIDRURO as a thread
-      state register. */
-   if (0x0E1D0F70 == (insn & 0x0FFF0FFF)) {
-      UInt rD = INSN(15,12);
-      if (rD <= 14) {
-         /* skip r15, that's too stupid to handle */
-         putIReg(rD, IRExpr_Get(OFFB_TPIDRURO, Ity_I32),
-                     condT, Ijk_Boring);
-         DIP("mrc%s p15,0, r%u, c13, c0, 3\n", nCC(INSN_COND), rD);
+   /* ------------------- (T1) CLZ ------------------- */
+   if (INSN0(15,4) == 0xFAB
+       && INSN1(15,12) == BITS4(1,1,1,1)
+       && INSN1(7,4) == BITS4(1,0,0,0)) {
+      UInt rM1 = INSN0(3,0);
+      UInt rD = INSN1(11,8);
+      UInt rM2 = INSN1(3,0);
+      if (!isBadRegT(rD) && !isBadRegT(rM1) && rM1 == rM2) {
+         IRTemp arg = newTemp(Ity_I32);
+         IRTemp res = newTemp(Ity_I32);
+         assign(arg, getIRegT(rM1));
+         assign(res, IRExpr_Mux0X(
+                        unop(Iop_1Uto8,binop(Iop_CmpEQ32,
+                                             mkexpr(arg),
+                                             mkU32(0))),
+                        unop(Iop_Clz32, mkexpr(arg)),
+                        mkU32(32)
+         ));
+         putIRegT(rD, mkexpr(res), condT);
+         DIP("clz r%u, r%u\n", rD, rM1);

          goto decode_success;
       }
          goto decode_success;
       }

-      /* fall through */

    }
 
    }
 

-   /* Handle various kinds of barriers.  This is rather indiscriminate
-      in the sense that they are all turned into an IR Fence, which
-      means we don't know which they are, so the back end has to
-      re-emit them all when it comes acrosss an IR Fence.
-   */
-   switch (insn) {
-      case 0xEE070F9A: /* v6 */
-         /* mcr 15, 0, r0, c7, c10, 4 (v6) equiv to DSB (v7).  Data
-            Synch Barrier -- ensures completion of memory accesses. */
-         stmt( IRStmt_MBE(Imbe_Fence) );
-         DIP("mcr 15, 0, r0, c7, c10, 4 (data synch barrier)\n");
+   /* -------------- (T1) MSR apsr, reg -------------- */
+   if (INSN0(15,4) == 0xF38 
+       && INSN1(15,12) == BITS4(1,0,0,0) && INSN1(9,0) == 0x000) {
+      UInt rN          = INSN0(3,0);
+      UInt write_ge    = INSN1(10,10);
+      UInt write_nzcvq = INSN1(11,11);
+      if (!isBadRegT(rN) && write_nzcvq && !write_ge) {
+         IRTemp rNt = newTemp(Ity_I32);
+         assign(rNt, getIRegT(rN));
+         // Do NZCV
+         IRTemp immT = newTemp(Ity_I32);
+         assign(immT, binop(Iop_And32, mkexpr(rNt), mkU32(0xF0000000)) );
+         setFlags_D1(ARMG_CC_OP_COPY, immT, condT);
+         // Do Q
+         IRTemp qnewT = newTemp(Ity_I32);
+         assign(qnewT, binop(Iop_And32, mkexpr(rNt), mkU32(ARMG_CC_MASK_Q)));
+         put_QFLAG32(qnewT, condT);
+         // 
+         DIP("msr cpsr_f, r%u\n", rN);

          goto decode_success;
          goto decode_success;

-      case 0xEE070FBA: /* v6 */
-         /* mcr 15, 0, r0, c7, c10, 5 (v6) equiv to DMB (v7).  Data
-            Memory Barrier -- ensures ordering of memory accesses. */
-         stmt( IRStmt_MBE(Imbe_Fence) );
-         DIP("mcr 15, 0, r0, c7, c10, 5 (data memory barrier)\n");
+      }
+   }
+
+   /* -------------- (T1) MRS reg, apsr -------------- */
+   if (INSN0(15,0) == 0xF3EF
+       && INSN1(15,12) == BITS4(1,0,0,0) && INSN1(7,0) == 0x00) {
+      UInt rD = INSN1(11,8);
+      if (!isBadRegT(rD)) {
+         IRTemp res1 = newTemp(Ity_I32);
+         // Get NZCV
+         assign( res1, mk_armg_calculate_flags_nzcv() );
+         /// OR in the Q value
+         IRTemp res2 = newTemp(Ity_I32);
+         assign(
+            res2,
+            binop(Iop_Or32,
+                  mkexpr(res1),
+                  binop(Iop_Shl32,
+                        unop(Iop_1Uto32,
+                             binop(Iop_CmpNE32,
+                                   mkexpr(get_QFLAG32()),
+                                   mkU32(0))),
+                        mkU8(ARMG_CC_SHIFT_Q)))
+         );
+         putIRegT( rD, mkexpr(res2), condT );
+         DIP("mrs r%u, cpsr\n", rD);

          goto decode_success;
          goto decode_success;

-      case 0xEE070F95: /* v6 */
-         /* mcr 15, 0, r0, c7, c5, 4 (v6) equiv to ISB (v7).
-            Instruction Synchronisation Barrier (or Flush Prefetch
-            Buffer) -- a pipe flush, I think.  I suspect we could
-            ignore those, but to be on the safe side emit a fence
-            anyway. */
-         stmt( IRStmt_MBE(Imbe_Fence) );
-         DIP("mcr 15, 0, r0, c7, c5, 4 (insn synch barrier)\n");
+      }
+   }
+
+   /* ----------------------------------------------------------- */
+   /* -- VFP (CP 10, CP 11) instructions (in Thumb mode)       -- */
+   /* ----------------------------------------------------------- */
+
+   if (INSN0(15,12) == BITS4(1,1,1,0)) {
+      UInt insn28 = (INSN0(11,0) << 16) | INSN1(15,0);
+      Bool ok_vfp = decode_CP10_CP11_instruction (
+                       &dres, insn28, condT, ARMCondAL/*bogus*/,
+                       True/*isT*/
+                    );
+      if (ok_vfp)

          goto decode_success;
          goto decode_success;

-      default:
-         break;
+   }
+
+   /* ----------------------------------------------------------- */
+   /* -- NEON instructions (in Thumb mode)                     -- */
+   /* ----------------------------------------------------------- */
+
+   { UInt insn32 = (INSN0(15,0) << 16) | INSN1(15,0);
+     Bool ok_neon = decode_NEON_instruction(
+                       &dres, insn32, condT, True/*isT*/
+                    );
+     if (ok_neon)
+        goto decode_success;

    }
 
    /* ----------------------------------------------------------- */
    }
 
    /* ----------------------------------------------------------- */


@@ -4755,24 +15154,21 @@ DisResult disInstr_ARM_WRK (
 
   decode_failure:
    /* All decode failures end up here. */
 
   decode_failure:
    /* All decode failures end up here. */

-   vex_printf("disInstr(arm): unhandled instruction: "
-              "0x%x\n", insn);
-   vex_printf("                 cond=%d(0x%x) 27:20=%u(0x%02x) "
-                                "4:4=%d "
-                                "3:0=%u(0x%x)\n",
-              (Int)INSN_COND, (UInt)INSN_COND,
-              (Int)INSN(27,20), (UInt)INSN(27,20),
-              (Int)INSN(4,4),
-              (Int)INSN(3,0), (UInt)INSN(3,0) );
+   vex_printf("disInstr(thumb): unhandled instruction: "
+              "0x%04x 0x%04x\n", (UInt)insn0, (UInt)insn1);

 
 

+   /* Back up ITSTATE to the initial value for this instruction.
+      If we don't do that, any subsequent restart of the instruction
+      will restart with the wrong value. */
+   put_ITSTATE(old_itstate);

    /* Tell the dispatcher that this insn cannot be decoded, and so has
       not been executed, and (is currently) the next to be executed.
       R15 should be up-to-date since it made so at the start of each
       insn, but nevertheless be paranoid and update it again right
       now. */
    /* Tell the dispatcher that this insn cannot be decoded, and so has
       not been executed, and (is currently) the next to be executed.
       R15 should be up-to-date since it made so at the start of each
       insn, but nevertheless be paranoid and update it again right
       now. */

-   vassert(0 == (guest_R15_curr_instr & 3));
-   llPutIReg( 15, mkU32(guest_R15_curr_instr) );
-   irsb->next     = mkU32(guest_R15_curr_instr);
+   vassert(0 == (guest_R15_curr_instr_notENC & 1));
+   llPutIReg( 15, mkU32(guest_R15_curr_instr_notENC | 1) );
+   irsb->next     = mkU32(guest_R15_curr_instr_notENC | 1 /* CPSR.T */);

    irsb->jumpkind = Ijk_NoDecode;
    dres.whatNext  = Dis_StopHere;
    dres.len       = 0;
    irsb->jumpkind = Ijk_NoDecode;
    dres.whatNext  = Dis_StopHere;
    dres.len       = 0;


@@ -4782,8 +15178,10 @@ DisResult disInstr_ARM_WRK (
    /* All decode successes end up here. */
    DIP("\n");
 
    /* All decode successes end up here. */
    DIP("\n");
 

-   vassert(dres.len == 4 || dres.len == 20);
+   vassert(dres.len == 2 || dres.len == 4 || dres.len == 20);

 
 

+#if 0
+   // XXX is this necessary on Thumb?

    /* Now then.  Do we have an implicit jump to r15 to deal with? */
    if (r15written) {
       /* If we get jump to deal with, we assume that there's been no
    /* Now then.  Do we have an implicit jump to r15 to deal with? */
    if (r15written) {
       /* If we get jump to deal with, we assume that there's been no


@@ -4804,29 +15202,31 @@ DisResult disInstr_ARM_WRK (
          terminate the block (a shame, but we can't do side exits to
          arbitrary destinations), but first jump to the next
          instruction if the condition doesn't hold. */
          terminate the block (a shame, but we can't do side exits to
          arbitrary destinations), but first jump to the next
          instruction if the condition doesn't hold. */

-      /* We can't use getIReg(15) to get the destination, since that
-         will produce r15+8, which isn't what we want.  Must use
+      /* We can't use getIRegT(15) to get the destination, since that
+         will produce r15+4, which isn't what we want.  Must use

          llGetIReg(15) instead. */
       if (r15guard == IRTemp_INVALID) {
          /* unconditional */
       } else {
          /* conditional */
          llGetIReg(15) instead. */
       if (r15guard == IRTemp_INVALID) {
          /* unconditional */
       } else {
          /* conditional */

-         stmt( IRStmt_Exit( unop(Iop_32to1,
-                                 binop(Iop_Xor32,
-                                       mkexpr(r15guard), mkU32(1))),
-                            r15kind,
-                            IRConst_U32(guest_R15_curr_instr + 4)
+         stmt( IRStmt_Exit(
+                  unop(Iop_32to1,
+                       binop(Iop_Xor32,
+                             mkexpr(r15guard), mkU32(1))),
+                  r15kind,
+                  IRConst_U32(guest_R15_curr_instr_notENC + 4)

          ));
       }
       irsb->next     = llGetIReg(15);
       irsb->jumpkind = r15kind;
       dres.whatNext  = Dis_StopHere;
    }
          ));
       }
       irsb->next     = llGetIReg(15);
       irsb->jumpkind = r15kind;
       dres.whatNext  = Dis_StopHere;
    }

+#endif

 
    return dres;
 
 
    return dres;
 

-#  undef INSN_COND
-#  undef INSN
+#  undef INSN0
+#  undef INSN1

 }
 
 #undef DIP
 }
 
 #undef DIP


@@ -4846,25 +15246,40 @@ DisResult disInstr_ARM ( IRSB*        irsb_IN,
                          Bool         resteerCisOk,
                          void*        callback_opaque,
                          UChar*       guest_code_IN,
                          Bool         resteerCisOk,
                          void*        callback_opaque,
                          UChar*       guest_code_IN,

-                         Long         delta,
-                         Addr64       guest_IP,
+                         Long         delta_ENCODED,
+                         Addr64       guest_IP_ENCODED,

                          VexArch      guest_arch,
                          VexArchInfo* archinfo,
                          VexAbiInfo*  abiinfo,
                          Bool         host_bigendian_IN )
 {
    DisResult dres;
                          VexArch      guest_arch,
                          VexArchInfo* archinfo,
                          VexAbiInfo*  abiinfo,
                          Bool         host_bigendian_IN )
 {
    DisResult dres;

+   Bool isThumb = (Bool)(guest_IP_ENCODED & 1);

 
    /* Set globals (see top of this file) */
    vassert(guest_arch == VexArchARM);
 
    /* Set globals (see top of this file) */
    vassert(guest_arch == VexArchARM);

-   irsb                 = irsb_IN;
-   host_is_bigendian    = host_bigendian_IN;
-   guest_R15_curr_instr = (Addr32)guest_IP;
-
-   dres = disInstr_ARM_WRK ( put_IP, resteerOkFn,
-                             resteerCisOk, callback_opaque,
-                             &guest_code_IN[delta],
-                             archinfo, abiinfo );
+
+   irsb              = irsb_IN;
+   host_is_bigendian = host_bigendian_IN;
+   __curr_is_Thumb   = isThumb;
+
+   if (isThumb) {
+      guest_R15_curr_instr_notENC = (Addr32)guest_IP_ENCODED - 1;
+   } else {
+      guest_R15_curr_instr_notENC = (Addr32)guest_IP_ENCODED;
+   }
+
+   if (isThumb) {
+      dres = disInstr_THUMB_WRK ( put_IP, resteerOkFn,
+                                  resteerCisOk, callback_opaque,
+                                  &guest_code_IN[delta_ENCODED - 1],
+                                  archinfo, abiinfo );
+   } else {
+      dres = disInstr_ARM_WRK ( put_IP, resteerOkFn,
+                                resteerCisOk, callback_opaque,
+                                &guest_code_IN[delta_ENCODED],
+                                archinfo, abiinfo );
+   }

 
    return dres;
 }
 
    return dres;
 }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_generic_x87.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_generic_x87.c
index f022f80ae10be430b7afeaa553fa50143c5fd11e..4204893bdd23c8a642ffee5ef67862f84bf070c7 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_generic_x87.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_generic_x87.c
@@ -453,13 +453,13 @@ ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp )
    const ULong bit52   = 1ULL << 52;
    const ULong sigMask = bit52 - 1;
 
    const ULong bit52   = 1ULL << 52;
    const ULong sigMask = bit52 - 1;
 

-   /* Mimic PIII behaviour for special cases. */
+   /* Mimic Core i5 behaviour for special cases. */

    if (arg == posInf)
       return getExp ? posInf : posInf;
    if (arg == negInf)
       return getExp ? posInf : negInf;
    if ((arg & nanMask) == nanMask)
    if (arg == posInf)
       return getExp ? posInf : posInf;
    if (arg == negInf)
       return getExp ? posInf : negInf;
    if ((arg & nanMask) == nanMask)

-      return qNan;
+      return qNan | (arg & (1ULL << 63));

    if (arg == posZero)
       return getExp ? negInf : posZero;
    if (arg == negZero)
    if (arg == posZero)
       return getExp ? negInf : posZero;
    if (arg == negZero)


@@ -535,6 +535,354 @@ ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp )
 }
 
 
 }
 
 

+
+/*---------------------------------------------------------*/
+/*--- SSE4.2 PCMP{E,I}STR{I,M} helpers                  ---*/
+/*---------------------------------------------------------*/
+
+/* We need the definitions for OSZACP eflags/rflags offsets.
+   #including guest_{amd64,x86}_defs.h causes chaos, so just copy the
+   required values directly.  They are not going to change in the
+   foreseeable future :-)
+*/
+
+#define SHIFT_O   11
+#define SHIFT_S   7
+#define SHIFT_Z   6
+#define SHIFT_A   4
+#define SHIFT_C   0
+#define SHIFT_P   2
+
+#define MASK_O    (1 << SHIFT_O)
+#define MASK_S    (1 << SHIFT_S)
+#define MASK_Z    (1 << SHIFT_Z)
+#define MASK_A    (1 << SHIFT_A)
+#define MASK_C    (1 << SHIFT_C)
+#define MASK_P    (1 << SHIFT_P)
+
+
+/* Count leading zeroes, w/ 0-produces-32 semantics, a la Hacker's
+   Delight. */
+static UInt clz32 ( UInt x )
+{
+   Int y, m, n;
+   y = -(x >> 16);
+   m = (y >> 16) & 16;
+   n = 16 - m;
+   x = x >> m;
+   y = x - 0x100;
+   m = (y >> 16) & 8;
+   n = n + m;
+   x = x << m;
+   y = x - 0x1000;
+   m = (y >> 16) & 4;
+   n = n + m;
+   x = x << m;
+   y = x - 0x4000;
+   m = (y >> 16) & 2;
+   n = n + m;
+   x = x << m;
+   y = x >> 14;
+   m = y & ~(y >> 1);
+   return n + 2 - m;
+}
+
+static UInt ctz32 ( UInt x )
+{
+   return 32 - clz32((~x) & (x-1));
+}
+
+/* Convert a 4-bit value to a 32-bit value by cloning each bit 8
+   times.  There's surely a better way to do this, but I don't know
+   what it is. */
+static UInt bits4_to_bytes4 ( UInt bits4 )
+{
+   UInt r = 0;
+   r |= (bits4 & 1) ? 0x000000FF : 0;
+   r |= (bits4 & 2) ? 0x0000FF00 : 0;
+   r |= (bits4 & 4) ? 0x00FF0000 : 0;
+   r |= (bits4 & 8) ? 0xFF000000 : 0;
+   return r;
+}
+
+
+/* Given partial results from a pcmpXstrX operation (intRes1,
+   basically), generate an I- or M-format output value, also the new
+   OSZACP flags.  */
+static
+void compute_PCMPxSTRx_gen_output (/*OUT*/V128* resV,
+                                   /*OUT*/UInt* resOSZACP,
+                                   UInt intRes1,
+                                   UInt zmaskL, UInt zmaskR,
+                                   UInt validL,
+                                   UInt pol, UInt idx,
+                                   Bool isxSTRM )
+{
+   vassert((pol >> 2) == 0);
+   vassert((idx >> 1) == 0);
+
+   UInt intRes2 = 0;
+   switch (pol) {
+      case 0: intRes2 = intRes1;          break; // pol +
+      case 1: intRes2 = ~intRes1;         break; // pol -
+      case 2: intRes2 = intRes1;          break; // pol m+
+      case 3: intRes2 = intRes1 ^ validL; break; // pol m-
+   }
+   intRes2 &= 0xFFFF;
+
+   if (isxSTRM) {
+ 
+      // generate M-format output (a bit or byte mask in XMM0)
+      if (idx) {
+         resV->w32[0] = bits4_to_bytes4( (intRes2 >>  0) & 0xF );
+         resV->w32[1] = bits4_to_bytes4( (intRes2 >>  4) & 0xF );
+         resV->w32[2] = bits4_to_bytes4( (intRes2 >>  8) & 0xF );
+         resV->w32[3] = bits4_to_bytes4( (intRes2 >> 12) & 0xF );
+      } else {
+         resV->w32[0] = intRes2 & 0xFFFF;
+         resV->w32[1] = 0;
+         resV->w32[2] = 0;
+         resV->w32[3] = 0;
+      }
+
+   } else {
+
+      // generate I-format output (an index in ECX)
+      // generate ecx value
+      UInt newECX = 0;
+      if (idx) {
+         // index of ms-1-bit
+         newECX = intRes2 == 0 ? 16 : (31 - clz32(intRes2));
+      } else {
+         // index of ls-1-bit
+         newECX = intRes2 == 0 ? 16 : ctz32(intRes2);
+      }
+
+      resV->w32[0] = newECX;
+      resV->w32[1] = 0;
+      resV->w32[2] = 0;
+      resV->w32[3] = 0;
+
+   }
+
+   // generate new flags, common to all ISTRI and ISTRM cases
+   *resOSZACP    // A, P are zero
+     = ((intRes2 == 0) ? 0 : MASK_C) // C == 0 iff intRes2 == 0
+     | ((zmaskL == 0)  ? 0 : MASK_Z) // Z == 1 iff any in argL is 0
+     | ((zmaskR == 0)  ? 0 : MASK_S) // S == 1 iff any in argR is 0
+     | ((intRes2 & 1) << SHIFT_O);   // O == IntRes2[0]
+}
+
+
+/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M}
+   variants.
+
+   For xSTRI variants, the new ECX value is placed in the 32 bits
+   pointed to by *resV, and the top 96 bits are zeroed.  For xSTRM
+   variants, the result is a 128 bit value and is placed at *resV in
+   the obvious way.
+
+   For all variants, the new OSZACP value is placed at *resOSZACP.
+
+   argLV and argRV are the vector args.  The caller must prepare a
+   16-bit mask for each, zmaskL and zmaskR.  For ISTRx variants this
+   must be 1 for each zero byte of of the respective arg.  For ESTRx
+   variants this is derived from the explicit length indication, and
+   must be 0 in all places except at the bit index corresponding to
+   the valid length (0 .. 16).  If the valid length is 16 then the
+   mask must be all zeroes.  In all cases, bits 31:16 must be zero.
+
+   imm8 is the original immediate from the instruction.  isSTRM
+   indicates whether this is a xSTRM or xSTRI variant, which controls
+   how much of *res is written.
+
+   If the given imm8 case can be handled, the return value is True.
+   If not, False is returned, and neither *res not *resOSZACP are
+   altered.
+*/
+
+Bool compute_PCMPxSTRx ( /*OUT*/V128* resV,
+                         /*OUT*/UInt* resOSZACP,
+                         V128* argLV,  V128* argRV,
+                         UInt zmaskL, UInt zmaskR,
+                         UInt imm8,   Bool isxSTRM )
+{
+   vassert(imm8 < 0x80);
+   vassert((zmaskL >> 16) == 0);
+   vassert((zmaskR >> 16) == 0);
+
+   /* Explicitly reject any imm8 values that haven't been validated,
+      even if they would probably work.  Life is too short to have
+      unvalidated cases in the code base. */
+   switch (imm8) {
+      case 0x02: case 0x08: case 0x0A: case 0x0C: case 0x12:
+      case 0x1A: case 0x3A: case 0x44: case 0x4A:
+         break;
+      default:
+         return False;
+   }
+
+   UInt fmt = (imm8 >> 0) & 3; // imm8[1:0]  data format
+   UInt agg = (imm8 >> 2) & 3; // imm8[3:2]  aggregation fn
+   UInt pol = (imm8 >> 4) & 3; // imm8[5:4]  polarity
+   UInt idx = (imm8 >> 6) & 1; // imm8[6]    1==msb/bytemask
+
+   /*----------------------------------------*/
+   /*-- strcmp on byte data                --*/
+   /*----------------------------------------*/
+
+   if (agg == 2/*equal each, aka strcmp*/
+       && (fmt == 0/*ub*/ || fmt == 2/*sb*/)) {
+      Int    i;
+      UChar* argL = (UChar*)argLV;
+      UChar* argR = (UChar*)argRV;
+      UInt boolResII = 0;
+      for (i = 15; i >= 0; i--) {
+         UChar cL  = argL[i];
+         UChar cR  = argR[i];
+         boolResII = (boolResII << 1) | (cL == cR ? 1 : 0);
+      }
+      UInt validL = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt validR = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+
+      // do invalidation, common to all equal-each cases
+      UInt intRes1
+         = (boolResII & validL & validR)  // if both valid, use cmpres
+           | (~ (validL | validR));       // if both invalid, force 1
+                                          // else force 0
+      intRes1 &= 0xFFFF;
+
+      // generate I-format output
+      compute_PCMPxSTRx_gen_output(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+      );
+
+      return True;
+   }
+
+   /*----------------------------------------*/
+   /*-- set membership on byte data        --*/
+   /*----------------------------------------*/
+
+   if (agg == 0/*equal any, aka find chars in a set*/
+       && (fmt == 0/*ub*/ || fmt == 2/*sb*/)) {
+      /* argL: the string,  argR: charset */
+      UInt   si, ci;
+      UChar* argL    = (UChar*)argLV;
+      UChar* argR    = (UChar*)argRV;
+      UInt   boolRes = 0;
+      UInt   validL  = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt   validR  = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+
+      for (si = 0; si < 16; si++) {
+         if ((validL & (1 << si)) == 0)
+            // run off the end of the string.
+            break;
+         UInt m = 0;
+         for (ci = 0; ci < 16; ci++) {
+            if ((validR & (1 << ci)) == 0) break;
+            if (argR[ci] == argL[si]) { m = 1; break; }
+         }
+         boolRes |= (m << si);
+      }
+
+      // boolRes is "pre-invalidated"
+      UInt intRes1 = boolRes & 0xFFFF;
+   
+      // generate I-format output
+      compute_PCMPxSTRx_gen_output(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+      );
+
+      return True;
+   }
+
+   /*----------------------------------------*/
+   /*-- substring search on byte data      --*/
+   /*----------------------------------------*/
+
+   if (agg == 3/*equal ordered, aka substring search*/
+       && (fmt == 0/*ub*/ || fmt == 2/*sb*/)) {
+
+      /* argL: haystack,  argR: needle */
+      UInt   ni, hi;
+      UChar* argL    = (UChar*)argLV;
+      UChar* argR    = (UChar*)argRV;
+      UInt   boolRes = 0;
+      UInt   validL  = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt   validR  = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+      for (hi = 0; hi < 16; hi++) {
+         if ((validL & (1 << hi)) == 0)
+            // run off the end of the haystack
+            break;
+         UInt m = 1;
+         for (ni = 0; ni < 16; ni++) {
+            if ((validR & (1 << ni)) == 0) break;
+            UInt i = ni + hi;
+            if (i >= 16) break;
+            if (argL[i] != argR[ni]) { m = 0; break; }
+         }
+         boolRes |= (m << hi);
+      }
+
+      // boolRes is "pre-invalidated"
+      UInt intRes1 = boolRes & 0xFFFF;
+
+      // generate I-format output
+      compute_PCMPxSTRx_gen_output(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+      );
+
+      return True;
+   }
+
+   /*----------------------------------------*/
+   /*-- ranges, unsigned byte data         --*/
+   /*----------------------------------------*/
+
+   if (agg == 1/*ranges*/
+       && fmt == 0/*ub*/) {
+
+      /* argL: string,  argR: range-pairs */
+      UInt   ri, si;
+      UChar* argL    = (UChar*)argLV;
+      UChar* argR    = (UChar*)argRV;
+      UInt   boolRes = 0;
+      UInt   validL  = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt   validR  = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+      for (si = 0; si < 16; si++) {
+         if ((validL & (1 << si)) == 0)
+            // run off the end of the string
+            break;
+         UInt m = 0;
+         for (ri = 0; ri < 16; ri += 2) {
+            if ((validR & (3 << ri)) != (3 << ri)) break;
+            if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) { 
+               m = 1; break;
+            }
+         }
+         boolRes |= (m << si);
+      }
+
+      // boolRes is "pre-invalidated"
+      UInt intRes1 = boolRes & 0xFFFF;
+
+      // generate I-format output
+      compute_PCMPxSTRx_gen_output(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx, isxSTRM
+      );
+
+      return True;
+   }
+
+   return False;
+}
+
+

 /*---------------------------------------------------------------*/
 /*--- end                                 guest_generic_x87.c ---*/
 /*---------------------------------------------------------------*/
 /*---------------------------------------------------------------*/
 /*--- end                                 guest_generic_x87.c ---*/
 /*---------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_generic_x87.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_generic_x87.h
index dc6b066e561c39be2f4c64c404f54436e7ebc943..9cbe23b38dcb2e6dcad40fd1138e76fded0a982a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_generic_x87.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_generic_x87.h
@@ -94,10 +94,18 @@ typedef
 #define FP_REG(ii)    (10*(7-(ii)))
 
 
 #define FP_REG(ii)    (10*(7-(ii)))
 
 

-/* Do the computations for x86/amd64 FXTRACT */
+/* Do the computations for x86/amd64 FXTRACT.  Called directly from
+   generated code.  CLEAN HELPER. */

 extern ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp );
 
 extern ULong x86amd64g_calculate_FXTRACT ( ULong arg, HWord getExp );
 

-
+/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M}
+   variants.  See bigger comment on implementation of this function
+   for details on call/return conventions. */
+extern Bool compute_PCMPxSTRx ( /*OUT*/V128* resV,
+                                /*OUT*/UInt* resOSZACP,
+                                V128* argLV,  V128* argRV,
+                                UInt zmaskL, UInt zmaskR,
+                                UInt imm8,   Bool isxSTRM );

 
 #endif /* ndef __VEX_GUEST_GENERIC_X87_H */
 
 
 #endif /* ndef __VEX_GUEST_GENERIC_X87_H */
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_ppc_defs.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_ppc_defs.h
index 36dbbc697458aceae47dffd0d19574a7cd26454d..dd3c62e7c8b671e31a99dc630afe378f48e53637 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_ppc_defs.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_ppc_defs.h
@@ -62,12 +62,16 @@ DisResult disInstr_PPC ( IRSB*        irbb,
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern

-IRExpr* guest_ppc32_spechelper ( HChar* function_name,
-                                 IRExpr** args );
+IRExpr* guest_ppc32_spechelper ( HChar*   function_name,
+                                 IRExpr** args,
+                                 IRStmt** precedingStmts,
+                                 Int      n_precedingStmts );

 
 extern
 
 extern

-IRExpr* guest_ppc64_spechelper ( HChar* function_name,
-                                 IRExpr** args );
+IRExpr* guest_ppc64_spechelper ( HChar*   function_name,
+                                 IRExpr** args,
+                                 IRStmt** precedingStmts,
+                                 Int      n_precedingStmts );

 
 /* Describes to the optimser which part of the guest state require
    precise memory exceptions.  This is logically part of the guest
 
 /* Describes to the optimser which part of the guest state require
    precise memory exceptions.  This is logically part of the guest

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_ppc_helpers.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_ppc_helpers.c
index d3b046dfc9e6fc03d910d21d9d456299f82ad5bc..e056a65328c4b804fe11c5433648495d69bc7f5a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_ppc_helpers.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_ppc_helpers.c
@@ -182,13 +182,17 @@ void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst,
 /* Helper-function specialiser. */
 
 IRExpr* guest_ppc32_spechelper ( HChar* function_name,
 /* Helper-function specialiser. */
 
 IRExpr* guest_ppc32_spechelper ( HChar* function_name,

-                                 IRExpr** args )
+                                 IRExpr** args,
+                                 IRStmt** precedingStmts,
+                                 Int      n_precedingStmts )

 {
    return NULL;
 }
 
 IRExpr* guest_ppc64_spechelper ( HChar* function_name,
 {
    return NULL;
 }
 
 IRExpr* guest_ppc64_spechelper ( HChar* function_name,

-                                 IRExpr** args )
+                                 IRExpr** args,
+                                 IRStmt** precedingStmts,
+                                 Int      n_precedingStmts )

 {
    return NULL;
 }
 {
    return NULL;
 }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_defs.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_defs.h
index a6953c8815163fb5f08986ea53a143466d735a89..09d647a9d9db8dbed9332493effde46387337fe5 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_defs.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_defs.h
@@ -61,8 +61,10 @@ DisResult disInstr_X86 ( IRSB*        irbb,
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern
 
 /* Used by the optimiser to specialise calls to helpers. */
 extern

-IRExpr* guest_x86_spechelper ( HChar* function_name,
-                               IRExpr** args );
+IRExpr* guest_x86_spechelper ( HChar*   function_name,
+                               IRExpr** args,
+                               IRStmt** precedingStmts,
+                               Int      n_precedingStmts );

 
 /* Describes to the optimiser which part of the guest state require
    precise memory exceptions.  This is logically part of the guest
 
 /* Describes to the optimiser which part of the guest state require
    precise memory exceptions.  This is logically part of the guest


@@ -153,6 +155,9 @@ extern UInt x86g_dirtyhelper_IN  ( UInt portno, UInt sz/*1,2 or 4*/ );
 extern void x86g_dirtyhelper_OUT ( UInt portno, UInt data, 
                                    UInt sz/*1,2 or 4*/ );
 
 extern void x86g_dirtyhelper_OUT ( UInt portno, UInt data, 
                                    UInt sz/*1,2 or 4*/ );
 

+extern void x86g_dirtyhelper_SxDT ( void* address,
+                                    UInt op /* 0 or 1 */ );
+

 extern VexEmWarn
             x86g_dirtyhelper_FXRSTOR ( VexGuestX86State*, HWord );
 
 extern VexEmWarn
             x86g_dirtyhelper_FXRSTOR ( VexGuestX86State*, HWord );
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_helpers.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_helpers.c
index 8178842ad792052830079fd08940a39f62483a91..7aa7a3392a15400c3503f8ff81bc3e2413cbbb4b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_helpers.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_helpers.c
@@ -772,8 +772,10 @@ static inline Bool isU32 ( IRExpr* e, UInt n )
               && e->Iex.Const.con->Ico.U32 == n );
 }
 
               && e->Iex.Const.con->Ico.U32 == n );
 }
 

-IRExpr* guest_x86_spechelper ( HChar* function_name,
-                               IRExpr** args )
+IRExpr* guest_x86_spechelper ( HChar*   function_name,
+                               IRExpr** args,
+                               IRStmt** precedingStmts,
+                               Int      n_precedingStmts )

 {
 #  define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
 #  define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))
 {
 #  define unop(_op,_a1) IRExpr_Unop((_op),(_a1))
 #  define binop(_op,_a1,_a2) IRExpr_Binop((_op),(_a1),(_a2))


@@ -2353,6 +2355,30 @@ void x86g_dirtyhelper_OUT ( UInt portno, UInt data, UInt sz/*1,2 or 4*/ )
 #  endif
 }
 
 #  endif
 }
 

+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack.  On non-x86 platforms, do nothing. */
+/* op = 0: call the native SGDT instruction.
+   op = 1: call the native SIDT instruction.
+*/
+void x86g_dirtyhelper_SxDT ( void *address, UInt op ) {
+#  if defined(__i386__)
+   switch (op) {
+      case 0:
+         __asm__ __volatile__("sgdt (%0)" : : "r" (address) : "memory");
+         break;
+      case 1:
+         __asm__ __volatile__("sidt (%0)" : : "r" (address) : "memory");
+         break;
+      default:
+         vpanic("x86g_dirtyhelper_SxDT");
+   }
+#  else
+   /* do nothing */
+   UChar* p = (UChar*)address;
+   p[0] = p[1] = p[2] = p[3] = p[4] = p[5] = 0;
+#  endif
+}

 
 /*---------------------------------------------------------------*/
 /*--- Helpers for MMX/SSE/SSE2.                               ---*/
 
 /*---------------------------------------------------------------*/
 /*--- Helpers for MMX/SSE/SSE2.                               ---*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_toIR.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_toIR.c
index a877a49169dc87cbcb83072b805562ca200cc9a8..761cd7f94fe7d044074547e939117abf6b997037 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_toIR.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/guest_x86_toIR.c
@@ -3362,6 +3362,40 @@ UInt dis_imul_I_E_G ( UChar       sorb,
 }
 
 
 }
 
 

+/* Generate an IR sequence to do a count-leading-zeroes operation on
+   the supplied IRTemp, and return a new IRTemp holding the result.
+   'ty' may be Ity_I16 or Ity_I32 only.  In the case where the
+   argument is zero, return the number of bits in the word (the
+   natural semantics). */
+static IRTemp gen_LZCNT ( IRType ty, IRTemp src )
+{
+   vassert(ty == Ity_I32 || ty == Ity_I16);
+
+   IRTemp src32 = newTemp(Ity_I32);
+   assign(src32, widenUto32( mkexpr(src) ));
+
+   IRTemp src32x = newTemp(Ity_I32);
+   assign(src32x, 
+          binop(Iop_Shl32, mkexpr(src32),
+                           mkU8(32 - 8 * sizeofIRType(ty))));
+
+   // Clz32 has undefined semantics when its input is zero, so
+   // special-case around that.
+   IRTemp res32 = newTemp(Ity_I32);
+   assign(res32,
+          IRExpr_Mux0X(
+             unop(Iop_1Uto8,
+                  binop(Iop_CmpEQ32, mkexpr(src32x), mkU32(0))),
+             unop(Iop_Clz32, mkexpr(src32x)),
+             mkU32(8 * sizeofIRType(ty))
+   ));
+
+   IRTemp res = newTemp(ty);
+   assign(res, narrowTo(ty, mkexpr(res32)));
+   return res;
+}
+
+

 /*------------------------------------------------------------*/
 /*---                                                      ---*/
 /*--- x87 FLOATING POINT INSTRUCTIONS                      ---*/
 /*------------------------------------------------------------*/
 /*---                                                      ---*/
 /*--- x87 FLOATING POINT INSTRUCTIONS                      ---*/


@@ -6127,7 +6161,8 @@ static HChar* nameBtOp ( BtOp op )
 
 
 static
 
 
 static

-UInt dis_bt_G_E ( UChar sorb, Bool locked, Int sz, Int delta, BtOp op )
+UInt dis_bt_G_E ( VexAbiInfo* vbi,
+                  UChar sorb, Bool locked, Int sz, Int delta, BtOp op )

 {
    HChar  dis_buf[50];
    UChar  modrm;
 {
    HChar  dis_buf[50];
    UChar  modrm;


@@ -6157,7 +6192,12 @@ UInt dis_bt_G_E ( UChar sorb, Bool locked, Int sz, Int delta, BtOp op )
       t_esp = newTemp(Ity_I32);
       t_addr0 = newTemp(Ity_I32);
 
       t_esp = newTemp(Ity_I32);
       t_addr0 = newTemp(Ity_I32);
 

-      assign( t_esp, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(sz)) );
+      /* For the choice of the value 128, see comment in dis_bt_G_E in
+         guest_amd64_toIR.c.  We point out here only that 128 is
+         fast-cased in Memcheck and is > 0, so seems like a good
+         choice. */
+      vassert(vbi->guest_stack_redzone_size == 0);
+      assign( t_esp, binop(Iop_Sub32, getIReg(4, R_ESP), mkU32(128)) );

       putIReg(4, R_ESP, mkexpr(t_esp));
 
       storeLE( mkexpr(t_esp), getIReg(sz, eregOfRM(modrm)) );
       putIReg(4, R_ESP, mkexpr(t_esp));
 
       storeLE( mkexpr(t_esp), getIReg(sz, eregOfRM(modrm)) );


@@ -6252,7 +6292,7 @@ UInt dis_bt_G_E ( UChar sorb, Bool locked, Int sz, Int delta, BtOp op )
    if (epartIsReg(modrm)) {
       /* t_esp still points at it. */
       putIReg(sz, eregOfRM(modrm), loadLE(szToITy(sz), mkexpr(t_esp)) );
    if (epartIsReg(modrm)) {
       /* t_esp still points at it. */
       putIReg(sz, eregOfRM(modrm), loadLE(szToITy(sz), mkexpr(t_esp)) );

-      putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t_esp), mkU32(sz)) );
+      putIReg(4, R_ESP, binop(Iop_Add32, mkexpr(t_esp), mkU32(128)) );

    }
 
    DIP("bt%s%c %s, %s\n",
    }
 
    DIP("bt%s%c %s, %s\n",


@@ -6615,7 +6655,8 @@ UInt dis_xadd_G_E ( UChar sorb, Bool locked, Int sz, Int delta0,
 
    /* There are 3 cases to consider:
 
 
    /* There are 3 cases to consider:
 

-      reg-reg: currently unhandled
+      reg-reg: ignore any lock prefix,
+               generate 'naive' (non-atomic) sequence

 
       reg-mem, not locked: ignore any lock prefix, generate 'naive'
                            (non-atomic) sequence
 
       reg-mem, not locked: ignore any lock prefix, generate 'naive'
                            (non-atomic) sequence


@@ -6625,9 +6666,18 @@ UInt dis_xadd_G_E ( UChar sorb, Bool locked, Int sz, Int delta0,
 
    if (epartIsReg(rm)) {
       /* case 1 */
 
    if (epartIsReg(rm)) {
       /* case 1 */

-      *decodeOK = False;
-      return delta0;
-      /* Currently we don't handle xadd_G_E with register operand. */
+      assign( tmpd,  getIReg(sz, eregOfRM(rm)));
+      assign( tmpt0, getIReg(sz, gregOfRM(rm)) );
+      assign( tmpt1, binop(mkSizedOp(ty,Iop_Add8),
+                           mkexpr(tmpd), mkexpr(tmpt0)) );
+      setFlags_DEP1_DEP2( Iop_Add8, tmpd, tmpt0, ty );
+      putIReg(sz, eregOfRM(rm), mkexpr(tmpt1));
+      putIReg(sz, gregOfRM(rm), mkexpr(tmpd));
+      DIP("xadd%c %s, %s\n",
+          nameISize(sz), nameIReg(sz,gregOfRM(rm)), 
+                                        nameIReg(sz,eregOfRM(rm)));
+      *decodeOK = True;
+      return 1+delta0;

    }
    else if (!epartIsReg(rm) && !locked) {
       /* case 2 */
    }
    else if (!epartIsReg(rm) && !locked) {
       /* case 2 */


@@ -7797,7 +7847,8 @@ DisResult disInstr_X86_WRK (
              Bool         resteerCisOk,
              void*        callback_opaque,
              Long         delta64,
              Bool         resteerCisOk,
              void*        callback_opaque,
              Long         delta64,

-             VexArchInfo* archinfo 
+             VexArchInfo* archinfo,
+             VexAbiInfo*  vbi

           )
 {
    IRType    ty;
           )
 {
    IRType    ty;


@@ -12596,6 +12647,126 @@ DisResult disInstr_X86_WRK (
    /* --- end of the SSSE3 decoder.                    --- */
    /* ---------------------------------------------------- */
 
    /* --- end of the SSSE3 decoder.                    --- */
    /* ---------------------------------------------------- */
 

+   /* ---------------------------------------------------- */
+   /* --- start of the SSE4 decoder                    --- */
+   /* ---------------------------------------------------- */
+
+   /* 66 0F 3A 0B /r ib = ROUNDSD imm8, xmm2/m64, xmm1
+      (Partial implementation only -- only deal with cases where
+      the rounding mode is specified directly by the immediate byte.)
+      66 0F 3A 0A /r ib = ROUNDSS imm8, xmm2/m32, xmm1
+      (Limitations ditto)
+   */
+   if (sz == 2 
+       && insn[0] == 0x0F && insn[1] == 0x3A
+       && (/*insn[2] == 0x0B || */insn[2] == 0x0A)) {
+
+      Bool   isD = insn[2] == 0x0B;
+      IRTemp src = newTemp(isD ? Ity_F64 : Ity_F32);
+      IRTemp res = newTemp(isD ? Ity_F64 : Ity_F32);
+      Int    imm = 0;
+
+      modrm = insn[3];
+
+      if (epartIsReg(modrm)) {
+         assign( src, 
+                 isD ? getXMMRegLane64F( eregOfRM(modrm), 0 )
+                     : getXMMRegLane32F( eregOfRM(modrm), 0 ) );
+         imm = insn[3+1];
+         if (imm & ~3) goto decode_failure;
+         delta += 3+1+1;
+         DIP( "rounds%c $%d,%s,%s\n",
+              isD ? 'd' : 's',
+              imm, nameXMMReg( eregOfRM(modrm) ),
+                   nameXMMReg( gregOfRM(modrm) ) );
+      } else {
+         addr = disAMode( &alen, sorb, delta+3, dis_buf );
+         assign( src, loadLE( isD ? Ity_F64 : Ity_F32, mkexpr(addr) ));
+         imm = insn[3+alen];
+         if (imm & ~3) goto decode_failure;
+         delta += 3+alen+1;
+         DIP( "roundsd $%d,%s,%s\n",
+              imm, dis_buf, nameXMMReg( gregOfRM(modrm) ) );
+      }
+
+      /* (imm & 3) contains an Intel-encoded rounding mode.  Because
+         that encoding is the same as the encoding for IRRoundingMode,
+         we can use that value directly in the IR as a rounding
+         mode. */
+      assign(res, binop(isD ? Iop_RoundF64toInt : Iop_RoundF32toInt,
+                  mkU32(imm & 3), mkexpr(src)) );
+
+      if (isD)
+         putXMMRegLane64F( gregOfRM(modrm), 0, mkexpr(res) );
+      else
+         putXMMRegLane32F( gregOfRM(modrm), 0, mkexpr(res) );
+
+      goto decode_success;
+   }
+
+   /* F3 0F BD -- LZCNT (count leading zeroes.  An AMD extension,
+      which we can only decode if we're sure this is an AMD cpu that
+      supports LZCNT, since otherwise it's BSR, which behaves
+      differently. */
+   if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xBD
+       && 0 != (archinfo->hwcaps & VEX_HWCAPS_X86_LZCNT)) {
+      vassert(sz == 2 || sz == 4);
+      /*IRType*/ ty  = szToITy(sz);
+      IRTemp     src = newTemp(ty);
+      modrm = insn[3];
+      if (epartIsReg(modrm)) {
+         assign(src, getIReg(sz, eregOfRM(modrm)));
+         delta += 3+1;
+         DIP("lzcnt%c %s, %s\n", nameISize(sz),
+             nameIReg(sz, eregOfRM(modrm)),
+             nameIReg(sz, gregOfRM(modrm)));
+      } else {
+         addr = disAMode( &alen, sorb, delta+3, dis_buf );
+         assign(src, loadLE(ty, mkexpr(addr)));
+         delta += 3+alen;
+         DIP("lzcnt%c %s, %s\n", nameISize(sz), dis_buf,
+             nameIReg(sz, gregOfRM(modrm)));
+      }
+
+      IRTemp res = gen_LZCNT(ty, src);
+      putIReg(sz, gregOfRM(modrm), mkexpr(res));
+
+      // Update flags.  This is pretty lame .. perhaps can do better
+      // if this turns out to be performance critical.
+      // O S A P are cleared.  Z is set if RESULT == 0.
+      // C is set if SRC is zero.
+      IRTemp src32 = newTemp(Ity_I32);
+      IRTemp res32 = newTemp(Ity_I32);
+      assign(src32, widenUto32(mkexpr(src)));
+      assign(res32, widenUto32(mkexpr(res)));
+
+      IRTemp oszacp = newTemp(Ity_I32);
+      assign(
+         oszacp,
+         binop(Iop_Or32,
+               binop(Iop_Shl32,
+                     unop(Iop_1Uto32,
+                          binop(Iop_CmpEQ32, mkexpr(res32), mkU32(0))),
+                     mkU8(X86G_CC_SHIFT_Z)),
+               binop(Iop_Shl32,
+                     unop(Iop_1Uto32,
+                          binop(Iop_CmpEQ32, mkexpr(src32), mkU32(0))),
+                     mkU8(X86G_CC_SHIFT_C))
+         )
+      );
+
+      stmt( IRStmt_Put( OFFB_CC_OP,   mkU32(X86G_CC_OP_COPY) ));
+      stmt( IRStmt_Put( OFFB_CC_DEP2, mkU32(0) ));
+      stmt( IRStmt_Put( OFFB_CC_NDEP, mkU32(0) ));
+      stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(oszacp) ));
+
+      goto decode_success;
+   }
+
+   /* ---------------------------------------------------- */
+   /* --- end of the SSE4 decoder                      --- */
+   /* ---------------------------------------------------- */
+

    after_sse_decoders:
 
    /* ---------------------------------------------------- */
    after_sse_decoders:
 
    /* ---------------------------------------------------- */


@@ -14284,16 +14455,16 @@ DisResult disInstr_X86_WRK (
       /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */
 
       case 0xA3: /* BT Gv,Ev */
       /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */
 
       case 0xA3: /* BT Gv,Ev */

-         delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpNone );
+         delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpNone );

          break;
       case 0xB3: /* BTR Gv,Ev */
          break;
       case 0xB3: /* BTR Gv,Ev */

-         delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpReset );
+         delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpReset );

          break;
       case 0xAB: /* BTS Gv,Ev */
          break;
       case 0xAB: /* BTS Gv,Ev */

-         delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpSet );
+         delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpSet );

          break;
       case 0xBB: /* BTC Gv,Ev */
          break;
       case 0xBB: /* BTC Gv,Ev */

-         delta = dis_bt_G_E ( sorb, pfx_lock, sz, delta, BtOpComp );
+         delta = dis_bt_G_E ( vbi, sorb, pfx_lock, sz, delta, BtOpComp );

          break;
 
       /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */
          break;
 
       /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */


@@ -14880,6 +15051,41 @@ DisResult disInstr_X86_WRK (
          DIP("emms\n");
          break;
 
          DIP("emms\n");
          break;
 

+      /* =-=-=-=-=-=-=-=-=- SGDT and SIDT =-=-=-=-=-=-=-=-=-=-= */
+      case 0x01: /* 0F 01 /0 -- SGDT */
+                 /* 0F 01 /1 -- SIDT */
+      {
+          /* This is really revolting, but ... since each processor
+             (core) only has one IDT and one GDT, just let the guest
+             see it (pass-through semantics).  I can't see any way to
+             construct a faked-up value, so don't bother to try. */
+         modrm = getUChar(delta);
+         addr = disAMode ( &alen, sorb, delta, dis_buf );
+         delta += alen;
+         if (epartIsReg(modrm)) goto decode_failure;
+         if (gregOfRM(modrm) != 0 && gregOfRM(modrm) != 1)
+            goto decode_failure;
+         switch (gregOfRM(modrm)) {
+            case 0: DIP("sgdt %s\n", dis_buf); break;
+            case 1: DIP("sidt %s\n", dis_buf); break;
+            default: vassert(0); /*NOTREACHED*/
+         }
+
+         IRDirty* d = unsafeIRDirty_0_N (
+                          0/*regparms*/,
+                          "x86g_dirtyhelper_SxDT",
+                          &x86g_dirtyhelper_SxDT,
+                          mkIRExprVec_2( mkexpr(addr),
+                                         mkU32(gregOfRM(modrm)) )
+                      );
+         /* declare we're writing memory */
+         d->mFx   = Ifx_Write;
+         d->mAddr = mkexpr(addr);
+         d->mSize = 6;
+         stmt( IRStmt_Dirty(d) );
+         break;
+      }
+

       /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */
 
       default:
       /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */
 
       default:


@@ -14966,7 +15172,8 @@ DisResult disInstr_X86 ( IRSB*        irsb_IN,
    expect_CAS = False;
    dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn,
                              resteerCisOk,
    expect_CAS = False;
    dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn,
                              resteerCisOk,

-                             callback_opaque, delta, archinfo );
+                             callback_opaque,
+                             delta, archinfo, abiinfo );

    x2 = irsb_IN->stmts_used;
    vassert(x2 >= x1);
 
    x2 = irsb_IN->stmts_used;
    vassert(x2 >= x1);
 


@@ -14985,7 +15192,8 @@ DisResult disInstr_X86 ( IRSB*        irsb_IN,
       vex_traceflags |= VEX_TRACE_FE;
       dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn,
                                 resteerCisOk,
       vex_traceflags |= VEX_TRACE_FE;
       dres = disInstr_X86_WRK ( &expect_CAS, put_IP, resteerOkFn,
                                 resteerCisOk,

-                                callback_opaque, delta, archinfo );
+                                callback_opaque,
+                                delta, archinfo, abiinfo );

       for (i = x1; i < x2; i++) {
          vex_printf("\t\t");
          ppIRStmt(irsb_IN->stmts[i]);
       for (i = x1; i < x2; i++) {
          vex_printf("\t\t");
          ppIRStmt(irsb_IN->stmts[i]);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_defs.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_defs.c
index eccf940853a6402cd418201b12a6ad4bc34edf66..1c3d012f7d465780250f7dc8a2bf87809c5a1e2e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_defs.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_defs.c
@@ -809,12 +809,14 @@ AMD64Instr* AMD64Instr_A87Free ( Int nregs )
    vassert(nregs >= 1 && nregs <= 7);
    return i;
 }
    vassert(nregs >= 1 && nregs <= 7);
    return i;
 }

-AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush )
+AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB )

 {
    AMD64Instr* i            = LibVEX_Alloc(sizeof(AMD64Instr));
    i->tag                   = Ain_A87PushPop;
    i->Ain.A87PushPop.addr   = addr;
    i->Ain.A87PushPop.isPush = isPush;
 {
    AMD64Instr* i            = LibVEX_Alloc(sizeof(AMD64Instr));
    i->tag                   = Ain_A87PushPop;
    i->Ain.A87PushPop.addr   = addr;
    i->Ain.A87PushPop.isPush = isPush;

+   i->Ain.A87PushPop.szB    = szB;
+   vassert(szB == 8 || szB == 4);

    return i;
 }
 AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op )
    return i;
 }
 AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op )


@@ -1195,7 +1197,8 @@ void ppAMD64Instr ( AMD64Instr* i, Bool mode64 )
          vex_printf("ffree %%st(7..%d)", 8 - i->Ain.A87Free.nregs );
          break;
       case Ain_A87PushPop:
          vex_printf("ffree %%st(7..%d)", 8 - i->Ain.A87Free.nregs );
          break;
       case Ain_A87PushPop:

-         vex_printf(i->Ain.A87PushPop.isPush ? "fldl " : "fstpl ");
+         vex_printf(i->Ain.A87PushPop.isPush ? "fld%c " : "fstp%c ",
+                    i->Ain.A87PushPop.szB == 4 ? 's' : 'l');

          ppAMD64AMode(i->Ain.A87PushPop.addr);
          break;
       case Ain_A87FpOp:
          ppAMD64AMode(i->Ain.A87PushPop.addr);
          break;
       case Ain_A87FpOp:


@@ -2948,17 +2951,18 @@ Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* i,
       goto done;
 
    case Ain_A87PushPop:
       goto done;
 
    case Ain_A87PushPop:

+      vassert(i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4);

       if (i->Ain.A87PushPop.isPush) {
       if (i->Ain.A87PushPop.isPush) {

-         /* Load from memory into %st(0): fldl amode */
+         /* Load from memory into %st(0): flds/fldl amode */

          *p++ = clearWBit(
                    rexAMode_M(fake(0), i->Ain.A87PushPop.addr) );
          *p++ = clearWBit(
                    rexAMode_M(fake(0), i->Ain.A87PushPop.addr) );

-         *p++ = 0xDD;
+         *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;

         p = doAMode_M(p, fake(0)/*subopcode*/, i->Ain.A87PushPop.addr);
       } else {
         p = doAMode_M(p, fake(0)/*subopcode*/, i->Ain.A87PushPop.addr);
       } else {

-         /* Dump %st(0) to memory: fstpl amode */
+         /* Dump %st(0) to memory: fstps/fstpl amode */

          *p++ = clearWBit(
                    rexAMode_M(fake(3), i->Ain.A87PushPop.addr) );
          *p++ = clearWBit(
                    rexAMode_M(fake(3), i->Ain.A87PushPop.addr) );

-         *p++ = 0xDD;
+         *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;

          p = doAMode_M(p, fake(3)/*subopcode*/, i->Ain.A87PushPop.addr);
          goto done;
       }
          p = doAMode_M(p, fake(3)/*subopcode*/, i->Ain.A87PushPop.addr);
          goto done;
       }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_defs.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_defs.h
index 21965cd31acbca20fc24eaac97dbdcb8604c7a33..cf49ae148c6f0ef30913b1ffd3e78938aec8ff4b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_defs.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_defs.h
@@ -546,12 +546,13 @@ typedef
             Int nregs; /* 1 <= nregs <= 7 */
          } A87Free;
 
             Int nregs; /* 1 <= nregs <= 7 */
          } A87Free;
 

-         /* Push a 64-bit FP value from memory onto the stack, or move
-            a value from the stack to memory and remove it from the
-            stack. */
+         /* Push a 32- or 64-bit FP value from memory onto the stack,
+            or move a value from the stack to memory and remove it
+            from the stack. */

          struct {
             AMD64AMode* addr;
             Bool        isPush;
          struct {
             AMD64AMode* addr;
             Bool        isPush;

+            UChar       szB; /* 4 or 8 */

          } A87PushPop;
 
          /* Do an operation on the top-of-stack.  This can be unary, in
          } A87PushPop;
 
          /* Do an operation on the top-of-stack.  This can be unary, in


@@ -694,7 +695,7 @@ extern AMD64Instr* AMD64Instr_ACAS       ( AMD64AMode* addr, UChar sz );
 extern AMD64Instr* AMD64Instr_DACAS      ( AMD64AMode* addr, UChar sz );
 
 extern AMD64Instr* AMD64Instr_A87Free    ( Int nregs );
 extern AMD64Instr* AMD64Instr_DACAS      ( AMD64AMode* addr, UChar sz );
 
 extern AMD64Instr* AMD64Instr_A87Free    ( Int nregs );

-extern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush );
+extern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB );

 extern AMD64Instr* AMD64Instr_A87FpOp    ( A87FpOp op );
 extern AMD64Instr* AMD64Instr_A87LdCW    ( AMD64AMode* addr );
 extern AMD64Instr* AMD64Instr_A87StSW    ( AMD64AMode* addr );
 extern AMD64Instr* AMD64Instr_A87FpOp    ( A87FpOp op );
 extern AMD64Instr* AMD64Instr_A87LdCW    ( AMD64AMode* addr );
 extern AMD64Instr* AMD64Instr_A87StSW    ( AMD64AMode* addr );

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_isel.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_isel.c
index 0a0a3a621b27f66886962e592007144accbe3885..1e719e715100e0a314d14de7dcb46cf504a2ec49 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_isel.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_amd64_isel.c
@@ -42,6 +42,7 @@
 #include "main_globals.h"
 #include "host_generic_regs.h"
 #include "host_generic_simd64.h"
 #include "main_globals.h"
 #include "host_generic_regs.h"
 #include "host_generic_simd64.h"

+#include "host_generic_simd128.h"

 #include "host_amd64_defs.h"
 
 
 #include "host_amd64_defs.h"
 
 


@@ -787,6 +788,21 @@ static HReg do_sse_NotV128 ( ISelEnv* env, HReg src )
 }
 
 
 }
 
 

+/* Expand the given byte into a 64-bit word, by cloning each bit
+   8 times. */
+static ULong bitmask8_to_bytemask64 ( UShort w8 )
+{
+   vassert(w8 == (w8 & 0xFF));
+   ULong w64 = 0;
+   Int i;
+   for (i = 0; i < 8; i++) {
+      if (w8 & (1<<i))
+         w64 |= (0xFFULL << (8 * i));
+   }
+   return w64;
+}
+
+

 //.. /* Round an x87 FPU value to 53-bit-mantissa precision, to be used
 //..    after most non-simple FPU operations (simple = +, -, *, / and
 //..    sqrt).
 //.. /* Round an x87 FPU value to 53-bit-mantissa precision, to be used
 //..    after most non-simple FPU operations (simple = +, -, *, / and
 //..    sqrt).


@@ -1775,11 +1791,11 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
 
          /* one arg -> top of x87 stack */
          addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg2, m8_rsp));
 
          /* one arg -> top of x87 stack */
          addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg2, m8_rsp));

-         addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/));
+         addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));

 
          /* other arg -> top of x87 stack */
          addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg1, m8_rsp));
 
          /* other arg -> top of x87 stack */
          addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg1, m8_rsp));

-         addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/));
+         addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));

 
          switch (e->Iex.Triop.op) {
             case Iop_PRemC3210F64:
 
          switch (e->Iex.Triop.op) {
             case Iop_PRemC3210F64:


@@ -2793,6 +2809,30 @@ static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
        return dst;
    }
 
        return dst;
    }
 

+   if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_RoundF32toInt) {
+      AMD64AMode* m8_rsp = AMD64AMode_IR(-8, hregAMD64_RSP());
+      HReg        arg    = iselFltExpr(env, e->Iex.Binop.arg2);
+      HReg        dst    = newVRegV(env);
+
+      /* rf now holds the value to be rounded.  The first thing to do
+         is set the FPU's rounding mode accordingly. */
+
+      /* Set host x87 rounding mode */
+      set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
+
+      addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, arg, m8_rsp));
+      addInstr(env, AMD64Instr_A87Free(1));
+      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 4));
+      addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND));
+      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 4));
+      addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 4, dst, m8_rsp));
+
+      /* Restore default x87 rounding. */
+      set_FPU_rounding_default( env );
+
+      return dst;
+   }
+

    ppIRExpr(e);
    vpanic("iselFltExpr_wrk");
 }
    ppIRExpr(e);
    vpanic("iselFltExpr_wrk");
 }


@@ -2936,9 +2976,9 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
 
       addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp));
       addInstr(env, AMD64Instr_A87Free(1));
 
       addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp));
       addInstr(env, AMD64Instr_A87Free(1));

-      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/));
+      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));

       addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND));
       addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND));

-      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/));
+      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));

       addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
 
       /* Restore default x87 rounding. */
       addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
 
       /* Restore default x87 rounding. */


@@ -2967,12 +3007,12 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
       /* one arg -> top of x87 stack */
       addInstr(env, AMD64Instr_SseLdSt(
                        False/*store*/, 8, arg2first ? arg2 : arg1, m8_rsp));
       /* one arg -> top of x87 stack */
       addInstr(env, AMD64Instr_SseLdSt(
                        False/*store*/, 8, arg2first ? arg2 : arg1, m8_rsp));

-      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/));
+      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));

 
       /* other arg -> top of x87 stack */
       addInstr(env, AMD64Instr_SseLdSt(
                        False/*store*/, 8, arg2first ? arg1 : arg2, m8_rsp));
 
       /* other arg -> top of x87 stack */
       addInstr(env, AMD64Instr_SseLdSt(
                        False/*store*/, 8, arg2first ? arg1 : arg2, m8_rsp));

-      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/));
+      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));

 
       /* do it */
       /* XXXROUNDINGFIXME */
 
       /* do it */
       /* XXXROUNDINGFIXME */


@@ -3001,7 +3041,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
       }
 
       /* save result */
       }
 
       /* save result */

-      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/));
+      addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));

       addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
       return dst;
    }
       addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
       return dst;
    }


@@ -3066,15 +3106,15 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
          Int     nNeeded    = e->Iex.Binop.op==Iop_TanF64 ? 2 : 1;
          addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp));
          addInstr(env, AMD64Instr_A87Free(nNeeded));
          Int     nNeeded    = e->Iex.Binop.op==Iop_TanF64 ? 2 : 1;
          addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp));
          addInstr(env, AMD64Instr_A87Free(nNeeded));

-         addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/));
+         addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));

          /* XXXROUNDINGFIXME */
          /* set roundingmode here */
          addInstr(env, AMD64Instr_A87FpOp(fpop));
          if (e->Iex.Binop.op==Iop_TanF64) {
             /* get rid of the extra 1.0 that fptan pushes */
          /* XXXROUNDINGFIXME */
          /* set roundingmode here */
          addInstr(env, AMD64Instr_A87FpOp(fpop));
          if (e->Iex.Binop.op==Iop_TanF64) {
             /* get rid of the extra 1.0 that fptan pushes */

-            addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/));
+            addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));

          }
          }

-         addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/));
+         addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));

          addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
          return dst;
       }
          addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
          return dst;
       }


@@ -3158,7 +3198,8 @@ static HReg iselVecExpr ( ISelEnv* env, IRExpr* e )
 /* DO NOT CALL THIS DIRECTLY */
 static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
 {
 /* DO NOT CALL THIS DIRECTLY */
 static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
 {

-   Bool     arg1isEReg = False;
+   HWord      fn = 0; /* address of helper fn, if required */
+   Bool       arg1isEReg = False;

    AMD64SseOp op = Asse_INVALID;
    IRType     ty = typeOfIRExpr(env->type_env,e);
    vassert(e);
    AMD64SseOp op = Asse_INVALID;
    IRType     ty = typeOfIRExpr(env->type_env,e);
    vassert(e);


@@ -3193,83 +3234,24 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
       switch (e->Iex.Const.con->Ico.V128) {
          case 0x0000:
             dst = generate_zeroes_V128(env);
       switch (e->Iex.Const.con->Ico.V128) {
          case 0x0000:
             dst = generate_zeroes_V128(env);

-            return dst;
+            break;

          case 0xFFFF:
             dst = generate_ones_V128(env);
          case 0xFFFF:
             dst = generate_ones_V128(env);

-            return dst;
-         default:
-            break;
-      }
-      AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP());
-      const ULong const_z64    = 0x0000000000000000ULL;
-      const ULong const_o64    = 0xFFFFFFFFFFFFFFFFULL;
-      const ULong const_z32o32 = 0x00000000FFFFFFFFULL;
-      const ULong const_o32z32 = 0xFFFFFFFF00000000ULL;
-      switch (e->Iex.Const.con->Ico.V128) {
-         case 0x0000: case 0xFFFF:
-            vassert(0); /* handled just above */
-         /* do push_uimm64 twice, first time for the high-order half. */
-         case 0x00F0:
-            push_uimm64(env, const_z64);
-            push_uimm64(env, const_o32z32);
-            break;
-         case 0x00FF:
-            push_uimm64(env, const_z64);
-            push_uimm64(env, const_o64);
-            break;
-         case 0x000F:
-            push_uimm64(env, const_z64);
-            push_uimm64(env, const_z32o32);
-            break;
-         case 0x0F00:
-            push_uimm64(env, const_z32o32);
-            push_uimm64(env, const_z64);
-            break;
-         case 0x0F0F:
-            push_uimm64(env, const_z32o32);
-            push_uimm64(env, const_z32o32);
-            break;
-         case 0x0FF0:
-            push_uimm64(env, const_z32o32);
-            push_uimm64(env, const_o32z32);
-            break;
-         case 0x0FFF:
-            push_uimm64(env, const_z32o32);
-            push_uimm64(env, const_o64);
-            break;
-         case 0xF000:
-            push_uimm64(env, const_o32z32);
-            push_uimm64(env, const_z64);
-            break;
-         case 0xF00F:
-            push_uimm64(env, const_o32z32);
-            push_uimm64(env, const_z32o32);
-            break;
-         case 0xF0F0:
-            push_uimm64(env, const_o32z32);
-            push_uimm64(env, const_o32z32);
-            break;
-         case 0xF0FF:
-            push_uimm64(env, const_o32z32);
-            push_uimm64(env, const_o64);
-            break;
-         case 0xFF00:
-            push_uimm64(env, const_o64);
-            push_uimm64(env, const_z64);

             break;
             break;

-         case 0xFF0F:
-            push_uimm64(env, const_o64);
-            push_uimm64(env, const_z32o32);
-            break;
-         case 0xFFF0:
-            push_uimm64(env, const_o64);
-            push_uimm64(env, const_o32z32);
+         default: {
+            AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP());
+            /* do push_uimm64 twice, first time for the high-order half. */
+            push_uimm64(env, bitmask8_to_bytemask64(
+                                (e->Iex.Const.con->Ico.V128 >> 8) & 0xFF
+                       ));
+            push_uimm64(env, bitmask8_to_bytemask64(
+                                (e->Iex.Const.con->Ico.V128 >> 0) & 0xFF
+                       ));
+            addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 ));
+            add_to_rsp(env, 16);

             break;
             break;

-         default:
-            goto vec_fail;
+         }

       }
       }

-      addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 ));
-      add_to_rsp(env, 16);

       return dst;
    }
 
       return dst;
    }
 


@@ -3614,6 +3596,73 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
          return dst;
       }
 
          return dst;
       }
 

+      case Iop_Mul32x4:    fn = (HWord)h_generic_calc_Mul32x4;
+                           goto do_SseAssistedBinary;
+      case Iop_Max32Sx4:   fn = (HWord)h_generic_calc_Max32Sx4;
+                           goto do_SseAssistedBinary;
+      case Iop_Min32Sx4:   fn = (HWord)h_generic_calc_Min32Sx4;
+                           goto do_SseAssistedBinary;
+      case Iop_Max32Ux4:   fn = (HWord)h_generic_calc_Max32Ux4;
+                           goto do_SseAssistedBinary;
+      case Iop_Min32Ux4:   fn = (HWord)h_generic_calc_Min32Ux4;
+                           goto do_SseAssistedBinary;
+      case Iop_Max16Ux8:   fn = (HWord)h_generic_calc_Max16Ux8;
+                           goto do_SseAssistedBinary;
+      case Iop_Min16Ux8:   fn = (HWord)h_generic_calc_Min16Ux8;
+                           goto do_SseAssistedBinary;
+      case Iop_Max8Sx16:   fn = (HWord)h_generic_calc_Max8Sx16;
+                           goto do_SseAssistedBinary;
+      case Iop_Min8Sx16:   fn = (HWord)h_generic_calc_Min8Sx16;
+                           goto do_SseAssistedBinary;
+      case Iop_CmpGT64Sx2: fn = (HWord)h_generic_calc_CmpGT64Sx2;
+                           goto do_SseAssistedBinary;
+      do_SseAssistedBinary: {
+         /* RRRufff!  RRRufff code is what we're generating here.  Oh
+            well. */
+         vassert(fn != 0);
+         HReg dst = newVRegV(env);
+         HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
+         HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
+         HReg argp = newVRegI(env);
+         /* subq $112, %rsp         -- make a space*/
+         sub_from_rsp(env, 112);
+         /* leaq 48(%rsp), %r_argp  -- point into it */
+         addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, hregAMD64_RSP()),
+                                        argp));
+         /* andq $-16, %r_argp      -- 16-align the pointer */
+         addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
+                                         AMD64RMI_Imm( ~(UInt)15 ), 
+                                         argp));
+         /* Prepare 3 arg regs:
+            leaq 0(%r_argp), %rdi
+            leaq 16(%r_argp), %rsi
+            leaq 32(%r_argp), %rdx
+         */
+         addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, argp),
+                                        hregAMD64_RDI()));
+         addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(16, argp),
+                                        hregAMD64_RSI()));
+         addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(32, argp),
+                                        hregAMD64_RDX()));
+         /* Store the two args, at (%rsi) and (%rdx):
+            movupd  %argL, 0(%rsi)
+            movupd  %argR, 0(%rdx)
+         */
+         addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argL,
+                                          AMD64AMode_IR(0, hregAMD64_RSI())));
+         addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argR,
+                                          AMD64AMode_IR(0, hregAMD64_RDX())));
+         /* call the helper */
+         addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 ));
+         /* fetch the result from memory, using %r_argp, which the
+            register allocator will keep alive across the call. */
+         addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dst,
+                                          AMD64AMode_IR(0, argp)));
+         /* and finally, clear the space */
+         add_to_rsp(env, 112);
+         return dst;
+      }
+

       default:
          break;
    } /* switch (e->Iex.Binop.op) */
       default:
          break;
    } /* switch (e->Iex.Binop.op) */


@@ -3630,7 +3679,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
       return dst;
    }
 
       return dst;
    }
 

-   vec_fail:
+   //vec_fail:

    vex_printf("iselVecExpr (amd64, subarch = %s): can't reduce\n",
               LibVEX_ppVexHwCaps(VexArchAMD64, env->hwcaps));
    ppIRExpr(e);
    vex_printf("iselVecExpr (amd64, subarch = %s): can't reduce\n",
               LibVEX_ppVexHwCaps(VexArchAMD64, env->hwcaps));
    ppIRExpr(e);


@@ -4029,8 +4078,10 @@ HInstrArray* iselSB_AMD64 ( IRSB* bb, VexArch      arch_host,
 
    /* sanity ... */
    vassert(arch_host == VexArchAMD64);
 
    /* sanity ... */
    vassert(arch_host == VexArchAMD64);

-   vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_AMD64_SSE3
-                                 |VEX_HWCAPS_AMD64_CX16)));
+   vassert(0 == (hwcaps_host
+                 & ~(VEX_HWCAPS_AMD64_SSE3
+                     | VEX_HWCAPS_AMD64_CX16
+                     | VEX_HWCAPS_AMD64_LZCNT)));

 
    /* Make up an initial environment to use. */
    env = LibVEX_Alloc(sizeof(ISelEnv));
 
    /* Make up an initial environment to use. */
    env = LibVEX_Alloc(sizeof(ISelEnv));

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_defs.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_defs.c
index 7fb7f98ae11963889d8fcae1104255c6d975d35d..832eb6ca5821f2d9fe0df4b7069baba2a42fe17c 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_defs.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_defs.c
@@ -9,6 +9,8 @@
 
    Copyright (C) 2004-2010 OpenWorks LLP
       info@open-works.net
 
    Copyright (C) 2004-2010 OpenWorks LLP
       info@open-works.net

+   Copyright (C) 2010-2010 Dmitry Zhurikhin
+      zhur@ispras.ru

 
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as
 
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as


@@ -36,6 +38,7 @@
 #include "host_generic_regs.h"
 #include "host_arm_defs.h"
 
 #include "host_generic_regs.h"
 #include "host_arm_defs.h"
 

+UInt arm_hwcaps = 0;

 
 
 /* --------- Registers. --------- */
 
 
 /* --------- Registers. --------- */


@@ -60,7 +63,7 @@ void ppHRegARM ( HReg reg )  {
          return;
       case HRcFlt64:
          r = hregNumber(reg);
          return;
       case HRcFlt64:
          r = hregNumber(reg);

-         vassert(r >= 0 && r < 16);
+         vassert(r >= 0 && r < 32);

          vex_printf("d%d", r);
          return;
       case HRcFlt32:
          vex_printf("d%d", r);
          return;
       case HRcFlt32:


@@ -68,6 +71,11 @@ void ppHRegARM ( HReg reg )  {
          vassert(r >= 0 && r < 32);
          vex_printf("s%d", r);
          return;
          vassert(r >= 0 && r < 32);
          vex_printf("s%d", r);
          return;

+      case HRcVec128:
+         r = hregNumber(reg);
+         vassert(r >= 0 && r < 16);
+         vex_printf("q%d", r);
+         return;

       default:
          vpanic("ppHRegARM");
    }
       default:
          vpanic("ppHRegARM");
    }


@@ -99,11 +107,19 @@ HReg hregARM_S27 ( void ) { return mkHReg(27, HRcFlt32, False); }
 HReg hregARM_S28 ( void ) { return mkHReg(28, HRcFlt32, False); }
 HReg hregARM_S29 ( void ) { return mkHReg(29, HRcFlt32, False); }
 HReg hregARM_S30 ( void ) { return mkHReg(30, HRcFlt32, False); }
 HReg hregARM_S28 ( void ) { return mkHReg(28, HRcFlt32, False); }
 HReg hregARM_S29 ( void ) { return mkHReg(29, HRcFlt32, False); }
 HReg hregARM_S30 ( void ) { return mkHReg(30, HRcFlt32, False); }

+HReg hregARM_Q8  ( void ) { return mkHReg(8,  HRcVec128, False); }
+HReg hregARM_Q9  ( void ) { return mkHReg(9,  HRcVec128, False); }
+HReg hregARM_Q10 ( void ) { return mkHReg(10, HRcVec128, False); }
+HReg hregARM_Q11 ( void ) { return mkHReg(11, HRcVec128, False); }
+HReg hregARM_Q12 ( void ) { return mkHReg(12, HRcVec128, False); }
+HReg hregARM_Q13 ( void ) { return mkHReg(13, HRcVec128, False); }
+HReg hregARM_Q14 ( void ) { return mkHReg(14, HRcVec128, False); }
+HReg hregARM_Q15 ( void ) { return mkHReg(15, HRcVec128, False); }

 
 void getAllocableRegs_ARM ( Int* nregs, HReg** arr )
 {
    Int i = 0;
 
 void getAllocableRegs_ARM ( Int* nregs, HReg** arr )
 {
    Int i = 0;

-   *nregs = 21;
+   *nregs = 29;

    *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
    // callee saves ones are listed first, since we prefer them
    // if they're available
    *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
    // callee saves ones are listed first, since we prefer them
    // if they're available


@@ -132,6 +148,16 @@ void getAllocableRegs_ARM ( Int* nregs, HReg** arr )
    (*arr)[i++] = hregARM_S28();
    (*arr)[i++] = hregARM_S29();
    (*arr)[i++] = hregARM_S30();
    (*arr)[i++] = hregARM_S28();
    (*arr)[i++] = hregARM_S29();
    (*arr)[i++] = hregARM_S30();

+
+   (*arr)[i++] = hregARM_Q8();
+   (*arr)[i++] = hregARM_Q9();
+   (*arr)[i++] = hregARM_Q10();
+   (*arr)[i++] = hregARM_Q11();
+   (*arr)[i++] = hregARM_Q12();
+   (*arr)[i++] = hregARM_Q13();
+   (*arr)[i++] = hregARM_Q14();
+   (*arr)[i++] = hregARM_Q15();
+

    // unavail: r8 as GSP
    // r12 'cos we're not sure what it's for
    // r13 as SP
    // unavail: r8 as GSP
    // r12 'cos we're not sure what it's for
    // r13 as SP


@@ -343,6 +369,56 @@ static void mapRegs_ARMAModeV ( HRegRemap* m, ARMAModeV* am ) {
 }
 
 
 }
 
 

+/* --------- Mem AModes: Addressing Mode Neon ------- */
+
+ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) {
+   ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN));
+   am->tag = ARMamN_RR;
+   am->ARMamN.RR.rN = rN;
+   am->ARMamN.RR.rM = rM;
+   return am;
+}
+
+ARMAModeN *mkARMAModeN_R ( HReg rN ) {
+   ARMAModeN* am = LibVEX_Alloc(sizeof(ARMAModeN));
+   am->tag = ARMamN_R;
+   am->ARMamN.R.rN = rN;
+   return am;
+}
+
+static void addRegUsage_ARMAModeN ( HRegUsage* u, ARMAModeN* am ) {
+   if (am->tag == ARMamN_R) {
+      addHRegUse(u, HRmRead, am->ARMamN.R.rN);
+   } else {
+      addHRegUse(u, HRmRead, am->ARMamN.RR.rN);
+      addHRegUse(u, HRmRead, am->ARMamN.RR.rM);
+   }
+}
+
+static void mapRegs_ARMAModeN ( HRegRemap* m, ARMAModeN* am ) {
+   if (am->tag == ARMamN_R) {
+      am->ARMamN.R.rN = lookupHRegRemap(m, am->ARMamN.R.rN);
+   } else {
+      am->ARMamN.RR.rN = lookupHRegRemap(m, am->ARMamN.RR.rN);
+      am->ARMamN.RR.rM = lookupHRegRemap(m, am->ARMamN.RR.rM);
+   }
+}
+
+void ppARMAModeN ( ARMAModeN* am ) {
+   vex_printf("[");
+   if (am->tag == ARMamN_R) {
+      ppHRegARM(am->ARMamN.R.rN);
+   } else {
+      ppHRegARM(am->ARMamN.RR.rN);
+   }
+   vex_printf("]");
+   if (am->tag == ARMamN_RR) {
+      vex_printf(", ");
+      ppHRegARM(am->ARMamN.RR.rM);
+   }
+}
+
+

 /* --------- Reg or imm-8x4 operands --------- */
 
 static UInt ROR32 ( UInt x, UInt sh ) {
 /* --------- Reg or imm-8x4 operands --------- */
 
 static UInt ROR32 ( UInt x, UInt sh ) {


@@ -461,6 +537,135 @@ static void mapRegs_ARMRI5 ( HRegRemap* m, ARMRI5* ri5 ) {
    }
 }
 
    }
 }
 

+/* -------- Neon Immediate operatnd --------- */
+
+ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 ) {
+   ARMNImm* i = LibVEX_Alloc(sizeof(ARMNImm));
+   i->type = type;
+   i->imm8 = imm8;
+   return i;
+}
+
+ULong ARMNImm_to_Imm64 ( ARMNImm* imm ) {
+   int i, j;
+   ULong y, x = imm->imm8;
+   switch (imm->type) {
+      case 3:
+         x = x << 8;
+      case 2:
+         x = x << 8;
+      case 1:
+         x = x << 8;
+      case 0:
+         return (x << 32) | x;
+      case 5:
+      case 6:
+         if (imm->type == 5)
+            x = x << 8;
+         else
+            x = (x << 8) | x;
+      case 4:
+         x = (x << 16) | x;
+         return (x << 32) | x;
+      case 8:
+         x = (x << 8) | 0xFF;
+      case 7:
+         x = (x << 8) | 0xFF;
+         return (x << 32) | x;
+      case 9:
+         x = 0;
+         for (i = 7; i >= 0; i--) {
+            y = ((ULong)imm->imm8 >> i) & 1;
+            for (j = 0; j < 8; j++) {
+               x = (x << 1) | y;
+            }
+         }
+         return x;
+      case 10:
+         x |= (x & 0x80) << 5;
+         x |= ~(x & 0x40) << 5;
+         x &= 0x187F; /* 0001 1000 0111 1111 */
+         x |= (x & 0x40) << 4;
+         x |= (x & 0x40) << 3;
+         x |= (x & 0x40) << 2;
+         x |= (x & 0x40) << 1;
+         x = x << 19;
+         x = (x << 32) | x;
+         return x;
+      default:
+         vpanic("ARMNImm_to_Imm64");
+   }
+}
+
+ARMNImm* Imm64_to_ARMNImm ( ULong x ) {
+   ARMNImm tmp;
+   if ((x & 0xFFFFFFFF) == (x >> 32)) {
+      if ((x & 0xFFFFFF00) == 0)
+         return ARMNImm_TI(0, x & 0xFF);
+      if ((x & 0xFFFF00FF) == 0)
+         return ARMNImm_TI(1, (x >> 8) & 0xFF);
+      if ((x & 0xFF00FFFF) == 0)
+         return ARMNImm_TI(2, (x >> 16) & 0xFF);
+      if ((x & 0x00FFFFFF) == 0)
+         return ARMNImm_TI(3, (x >> 24) & 0xFF);
+      if ((x & 0xFFFF00FF) == 0xFF)
+         return ARMNImm_TI(7, (x >> 8) & 0xFF);
+      if ((x & 0xFF00FFFF) == 0xFFFF)
+         return ARMNImm_TI(8, (x >> 16) & 0xFF);
+      if ((x & 0xFFFF) == ((x >> 16) & 0xFFFF)) {
+         if ((x & 0xFF00) == 0)
+            return ARMNImm_TI(4, x & 0xFF);
+         if ((x & 0x00FF) == 0)
+            return ARMNImm_TI(5, (x >> 8) & 0xFF);
+         if ((x & 0xFF) == ((x >> 8) & 0xFF))
+            return ARMNImm_TI(6, x & 0xFF);
+      }
+      if ((x & 0x7FFFF) == 0) {
+         tmp.type = 10;
+         tmp.imm8 = ((x >> 19) & 0x7F) | ((x >> 24) & 0x80);
+         if (ARMNImm_to_Imm64(&tmp) == x)
+            return ARMNImm_TI(tmp.type, tmp.imm8);
+      }
+   } else {
+      /* This can only be type 9. */
+      tmp.imm8 = (((x >> 56) & 1) << 7)
+               | (((x >> 48) & 1) << 6)
+               | (((x >> 40) & 1) << 5)
+               | (((x >> 32) & 1) << 4)
+               | (((x >> 24) & 1) << 3)
+               | (((x >> 16) & 1) << 2)
+               | (((x >>  8) & 1) << 1)
+               | (((x >>  0) & 1) << 0);
+      tmp.type = 9;
+      if (ARMNImm_to_Imm64 (&tmp) == x)
+         return ARMNImm_TI(tmp.type, tmp.imm8);
+   }
+   return NULL;
+}
+
+void ppARMNImm (ARMNImm* i) {
+   ULong x = ARMNImm_to_Imm64(i);
+   vex_printf("0x%llX%llX", x, x);
+}
+
+/* -- Register or scalar operand --- */
+
+ARMNRS* mkARMNRS(ARMNRS_tag tag, HReg reg, UInt index)
+{
+   ARMNRS *p = LibVEX_Alloc(sizeof(ARMNRS));
+   p->tag = tag;
+   p->reg = reg;
+   p->index = index;
+   return p;
+}
+
+void ppARMNRS(ARMNRS *p)
+{
+   ppHRegARM(p->reg);
+   if (p->tag == ARMNRS_Scalar) {
+      vex_printf("[%d]", p->index);
+   }
+}

 
 /* --------- Instructions. --------- */
 
 
 /* --------- Instructions. --------- */
 


@@ -527,6 +732,365 @@ HChar* showARMVfpUnaryOp ( ARMVfpUnaryOp op ) {
    }
 }
 
    }
 }
 

+HChar* showARMNeonBinOp ( ARMNeonBinOp op ) {
+   switch (op) {
+      case ARMneon_VAND: return "vand";
+      case ARMneon_VORR: return "vorr";
+      case ARMneon_VXOR: return "veor";
+      case ARMneon_VADD: return "vadd";
+      case ARMneon_VRHADDS: return "vrhadd";
+      case ARMneon_VRHADDU: return "vrhadd";
+      case ARMneon_VADDFP: return "vadd";
+      case ARMneon_VPADDFP: return "vpadd";
+      case ARMneon_VABDFP: return "vabd";
+      case ARMneon_VSUB: return "vsub";
+      case ARMneon_VSUBFP: return "vsub";
+      case ARMneon_VMINU: return "vmin";
+      case ARMneon_VMINS: return "vmin";
+      case ARMneon_VMINF: return "vmin";
+      case ARMneon_VMAXU: return "vmax";
+      case ARMneon_VMAXS: return "vmax";
+      case ARMneon_VMAXF: return "vmax";
+      case ARMneon_VQADDU: return "vqadd";
+      case ARMneon_VQADDS: return "vqadd";
+      case ARMneon_VQSUBU: return "vqsub";
+      case ARMneon_VQSUBS: return "vqsub";
+      case ARMneon_VCGTU:  return "vcgt";
+      case ARMneon_VCGTS:  return "vcgt";
+      case ARMneon_VCGTF:  return "vcgt";
+      case ARMneon_VCGEF:  return "vcgt";
+      case ARMneon_VCGEU:  return "vcge";
+      case ARMneon_VCGES:  return "vcge";
+      case ARMneon_VCEQ:  return "vceq";
+      case ARMneon_VCEQF:  return "vceq";
+      case ARMneon_VPADD:   return "vpadd";
+      case ARMneon_VPMINU:   return "vpmin";
+      case ARMneon_VPMINS:   return "vpmin";
+      case ARMneon_VPMINF:   return "vpmin";
+      case ARMneon_VPMAXU:   return "vpmax";
+      case ARMneon_VPMAXS:   return "vpmax";
+      case ARMneon_VPMAXF:   return "vpmax";
+      case ARMneon_VEXT:   return "vext";
+      case ARMneon_VMUL:   return "vmuli";
+      case ARMneon_VMULLU:   return "vmull";
+      case ARMneon_VMULLS:   return "vmull";
+      case ARMneon_VMULP:  return "vmul";
+      case ARMneon_VMULFP:  return "vmul";
+      case ARMneon_VMULLP:  return "vmul";
+      case ARMneon_VQDMULH: return "vqdmulh";
+      case ARMneon_VQRDMULH: return "vqrdmulh";
+      case ARMneon_VQDMULL: return "vqdmull";
+      case ARMneon_VTBL: return "vtbl";
+      case ARMneon_SETELEM: return "vmov";
+      case ARMneon_VABSFP: return "vabsfp";
+      case ARMneon_VRSQRTEFP: return "vrsqrtefp";
+      case ARMneon_VRSQRTE: return "vrsqrte";
+      /* ... */
+      default: vpanic("showARMNeonBinOp");
+   }
+}
+
+HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op ) {
+   switch (op) {
+      case ARMneon_VAND:
+      case ARMneon_VORR:
+      case ARMneon_VXOR:
+         return "";
+      case ARMneon_VADD:
+      case ARMneon_VSUB:
+      case ARMneon_VEXT:
+      case ARMneon_VMUL:
+      case ARMneon_SETELEM:
+      case ARMneon_VPADD:
+      case ARMneon_VTBL:
+      case ARMneon_VCEQ:
+         return ".i";
+      case ARMneon_VRHADDU:
+      case ARMneon_VMINU:
+      case ARMneon_VMAXU:
+      case ARMneon_VQADDU:
+      case ARMneon_VQSUBU:
+      case ARMneon_VCGTU:
+      case ARMneon_VCGEU:
+      case ARMneon_VMULLU:
+      case ARMneon_VPMINU:
+      case ARMneon_VPMAXU:
+      case ARMneon_VRSQRTE:
+         return ".u";
+      case ARMneon_VRHADDS:
+      case ARMneon_VMINS:
+      case ARMneon_VMAXS:
+      case ARMneon_VQADDS:
+      case ARMneon_VQSUBS:
+      case ARMneon_VCGTS:
+      case ARMneon_VCGES:
+      case ARMneon_VQDMULL:
+      case ARMneon_VMULLS:
+      case ARMneon_VPMINS:
+      case ARMneon_VPMAXS:
+      case ARMneon_VQDMULH:
+      case ARMneon_VQRDMULH:
+         return ".s";
+      case ARMneon_VMULP:
+      case ARMneon_VMULLP:
+         return ".p";
+      case ARMneon_VADDFP:
+      case ARMneon_VABDFP:
+      case ARMneon_VPADDFP:
+      case ARMneon_VSUBFP:
+      case ARMneon_VMULFP:
+      case ARMneon_VMINF:
+      case ARMneon_VMAXF:
+      case ARMneon_VABSFP:
+      case ARMneon_VRSQRTEFP:
+      case ARMneon_VPMINF:
+      case ARMneon_VPMAXF:
+      case ARMneon_VCGTF:
+      case ARMneon_VCGEF:
+      case ARMneon_VCEQF:
+         return ".f";
+      /* ... */
+      default: vpanic("showARMNeonBinOpDataType");
+   }
+}
+
+HChar* showARMNeonUnOp ( ARMNeonUnOp op ) {
+   switch (op) {
+      case ARMneon_COPY: return "vmov";
+      case ARMneon_COPYLS: return "vmov";
+      case ARMneon_COPYLU: return "vmov";
+      case ARMneon_COPYN: return "vmov";
+      case ARMneon_COPYQNSS: return "vqmovn";
+      case ARMneon_COPYQNUS: return "vqmovun";
+      case ARMneon_COPYQNUU: return "vqmovn";
+      case ARMneon_NOT: return "vmvn";
+      case ARMneon_EQZ: return "vceq";
+      case ARMneon_CNT: return "vcnt";
+      case ARMneon_CLS: return "vcls";
+      case ARMneon_CLZ: return "vclz";
+      case ARMneon_DUP: return "vdup";
+      case ARMneon_PADDLS: return "vpaddl";
+      case ARMneon_PADDLU: return "vpaddl";
+      case ARMneon_VQSHLNSS: return "vqshl";
+      case ARMneon_VQSHLNUU: return "vqshl";
+      case ARMneon_VQSHLNUS: return "vqshlu";
+      case ARMneon_REV16: return "vrev16";
+      case ARMneon_REV32: return "vrev32";
+      case ARMneon_REV64: return "vrev64";
+      case ARMneon_VCVTFtoU: return "vcvt";
+      case ARMneon_VCVTFtoS: return "vcvt";
+      case ARMneon_VCVTUtoF: return "vcvt";
+      case ARMneon_VCVTStoF: return "vcvt";
+      case ARMneon_VCVTFtoFixedU: return "vcvt";
+      case ARMneon_VCVTFtoFixedS: return "vcvt";
+      case ARMneon_VCVTFixedUtoF: return "vcvt";
+      case ARMneon_VCVTFixedStoF: return "vcvt";
+      case ARMneon_VCVTF32toF16: return "vcvt";
+      case ARMneon_VCVTF16toF32: return "vcvt";
+      case ARMneon_VRECIP: return "vrecip";
+      case ARMneon_VRECIPF: return "vrecipf";
+      case ARMneon_VRECPS: return "vrecps";
+      case ARMneon_VNEGF: return "vneg";
+      case ARMneon_VRSQRTS: return "vrecps";
+      case ARMneon_ABS: return "vabs";
+      /* ... */
+      default: vpanic("showARMNeonUnOp");
+   }
+}
+
+HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op ) {
+   switch (op) {
+      case ARMneon_COPY:
+      case ARMneon_NOT:
+         return "";
+      case ARMneon_COPYN:
+      case ARMneon_EQZ:
+      case ARMneon_CNT:
+      case ARMneon_DUP:
+      case ARMneon_REV16:
+      case ARMneon_REV32:
+      case ARMneon_REV64:
+         return ".i";
+      case ARMneon_COPYLU:
+      case ARMneon_PADDLU:
+      case ARMneon_COPYQNUU:
+      case ARMneon_VQSHLNUU:
+      case ARMneon_VRECIP:
+         return ".u";
+      case ARMneon_CLS:
+      case ARMneon_CLZ:
+      case ARMneon_COPYLS:
+      case ARMneon_PADDLS:
+      case ARMneon_COPYQNSS:
+      case ARMneon_COPYQNUS:
+      case ARMneon_VQSHLNSS:
+      case ARMneon_VQSHLNUS:
+      case ARMneon_ABS:
+         return ".s";
+      case ARMneon_VRECIPF:
+      case ARMneon_VRECPS:
+      case ARMneon_VNEGF:
+      case ARMneon_VRSQRTS:
+         return ".f";
+      case ARMneon_VCVTFtoU: return ".u32.f32";
+      case ARMneon_VCVTFtoS: return ".s32.f32";
+      case ARMneon_VCVTUtoF: return ".f32.u32";
+      case ARMneon_VCVTStoF: return ".f32.s32";
+      case ARMneon_VCVTF16toF32: return ".f32.f16";
+      case ARMneon_VCVTF32toF16: return ".f16.f32";
+      case ARMneon_VCVTFtoFixedU: return ".u32.f32";
+      case ARMneon_VCVTFtoFixedS: return ".s32.f32";
+      case ARMneon_VCVTFixedUtoF: return ".f32.u32";
+      case ARMneon_VCVTFixedStoF: return ".f32.s32";
+      /* ... */
+      default: vpanic("showARMNeonUnOpDataType");
+   }
+}
+
+HChar* showARMNeonUnOpS ( ARMNeonUnOpS op ) {
+   switch (op) {
+      case ARMneon_SETELEM: return "vmov";
+      case ARMneon_GETELEMU: return "vmov";
+      case ARMneon_GETELEMS: return "vmov";
+      case ARMneon_VDUP: return "vdup";
+      /* ... */
+      default: vpanic("showARMNeonUnarySOp");
+   }
+}
+
+HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op ) {
+   switch (op) {
+      case ARMneon_SETELEM:
+      case ARMneon_VDUP:
+         return ".i";
+      case ARMneon_GETELEMS:
+         return ".s";
+      case ARMneon_GETELEMU:
+         return ".u";
+      /* ... */
+      default: vpanic("showARMNeonUnarySOp");
+   }
+}
+
+HChar* showARMNeonShiftOp ( ARMNeonShiftOp op ) {
+   switch (op) {
+      case ARMneon_VSHL: return "vshl";
+      case ARMneon_VSAL: return "vshl";
+      case ARMneon_VQSHL: return "vqshl";
+      case ARMneon_VQSAL: return "vqshl";
+      /* ... */
+      default: vpanic("showARMNeonShiftOp");
+   }
+}
+
+HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op ) {
+   switch (op) {
+      case ARMneon_VSHL:
+      case ARMneon_VQSHL:
+         return ".u";
+      case ARMneon_VSAL:
+      case ARMneon_VQSAL:
+         return ".s";
+      /* ... */
+      default: vpanic("showARMNeonShiftOpDataType");
+   }
+}
+
+HChar* showARMNeonDualOp ( ARMNeonDualOp op ) {
+   switch (op) {
+      case ARMneon_TRN: return "vtrn";
+      case ARMneon_ZIP: return "vzip";
+      case ARMneon_UZP: return "vuzp";
+      /* ... */
+      default: vpanic("showARMNeonDualOp");
+   }
+}
+
+HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op ) {
+   switch (op) {
+      case ARMneon_TRN:
+      case ARMneon_ZIP:
+      case ARMneon_UZP:
+         return "i";
+      /* ... */
+      default: vpanic("showARMNeonDualOp");
+   }
+}
+
+static HChar* showARMNeonDataSize_wrk ( UInt size )
+{
+   switch (size) {
+      case 0: return "8";
+      case 1: return "16";
+      case 2: return "32";
+      case 3: return "64";
+      default: vpanic("showARMNeonDataSize");
+   }
+}
+
+static HChar* showARMNeonDataSize ( ARMInstr* i )
+{
+   switch (i->tag) {
+      case ARMin_NBinary:
+         if (i->ARMin.NBinary.op == ARMneon_VEXT)
+            return "8";
+         if (i->ARMin.NBinary.op == ARMneon_VAND ||
+             i->ARMin.NBinary.op == ARMneon_VORR ||
+             i->ARMin.NBinary.op == ARMneon_VXOR)
+            return "";
+         return showARMNeonDataSize_wrk(i->ARMin.NBinary.size);
+      case ARMin_NUnary:
+         if (i->ARMin.NUnary.op == ARMneon_COPY ||
+             i->ARMin.NUnary.op == ARMneon_NOT ||
+             i->ARMin.NUnary.op == ARMneon_VCVTF32toF16||
+             i->ARMin.NUnary.op == ARMneon_VCVTF16toF32||
+             i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS ||
+             i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU ||
+             i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF ||
+             i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF ||
+             i->ARMin.NUnary.op == ARMneon_VCVTFtoS ||
+             i->ARMin.NUnary.op == ARMneon_VCVTFtoU ||
+             i->ARMin.NUnary.op == ARMneon_VCVTStoF ||
+             i->ARMin.NUnary.op == ARMneon_VCVTUtoF)
+            return "";
+         if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS ||
+             i->ARMin.NUnary.op == ARMneon_VQSHLNUU ||
+             i->ARMin.NUnary.op == ARMneon_VQSHLNUS) {
+            UInt size;
+            size = i->ARMin.NUnary.size;
+            if (size & 0x40)
+               return "64";
+            if (size & 0x20)
+               return "32";
+            if (size & 0x10)
+               return "16";
+            if (size & 0x08)
+               return "8";
+            vpanic("showARMNeonDataSize");
+         }
+         return showARMNeonDataSize_wrk(i->ARMin.NUnary.size);
+      case ARMin_NUnaryS:
+         if (i->ARMin.NUnaryS.op == ARMneon_VDUP) {
+            int size;
+            size = i->ARMin.NUnaryS.size;
+            if ((size & 1) == 1)
+               return "8";
+            if ((size & 3) == 2)
+               return "16";
+            if ((size & 7) == 4)
+               return "32";
+            vpanic("showARMNeonDataSize");
+         }
+         return showARMNeonDataSize_wrk(i->ARMin.NUnaryS.size);
+      case ARMin_NShift:
+         return showARMNeonDataSize_wrk(i->ARMin.NShift.size);
+      case ARMin_NDual:
+         return showARMNeonDataSize_wrk(i->ARMin.NDual.size);
+      default:
+         vpanic("showARMNeonDataSize");
+   }
+}
+

 ARMInstr* ARMInstr_Alu ( ARMAluOp op,
                          HReg dst, HReg argL, ARMRI84* argR ) {
    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
 ARMInstr* ARMInstr_Alu ( ARMAluOp op,
                          HReg dst, HReg argL, ARMRI84* argR ) {
    ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));


@@ -772,6 +1336,143 @@ ARMInstr* ARMInstr_MFence ( void ) {
    return i;
 }
 
    return i;
 }
 

+ARMInstr* ARMInstr_NLdStQ ( Bool isLoad, HReg dQ, ARMAModeN *amode ) {
+   ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag                  = ARMin_NLdStQ;
+   i->ARMin.NLdStQ.isLoad  = isLoad;
+   i->ARMin.NLdStQ.dQ      = dQ;
+   i->ARMin.NLdStQ.amode   = amode;
+   return i;
+}
+
+ARMInstr* ARMInstr_NLdStD ( Bool isLoad, HReg dD, ARMAModeN *amode ) {
+   ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag                  = ARMin_NLdStD;
+   i->ARMin.NLdStD.isLoad  = isLoad;
+   i->ARMin.NLdStD.dD      = dD;
+   i->ARMin.NLdStD.amode   = amode;
+   return i;
+}
+
+ARMInstr* ARMInstr_NUnary ( ARMNeonUnOp op, HReg dQ, HReg nQ,
+                            UInt size, Bool Q ) {
+   ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag                = ARMin_NUnary;
+   i->ARMin.NUnary.op   = op;
+   i->ARMin.NUnary.src  = nQ;
+   i->ARMin.NUnary.dst  = dQ;
+   i->ARMin.NUnary.size = size;
+   i->ARMin.NUnary.Q    = Q;
+   return i;
+}
+
+ARMInstr* ARMInstr_NUnaryS ( ARMNeonUnOp op, ARMNRS* dst, ARMNRS* src,
+                             UInt size, Bool Q ) {
+   ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag                = ARMin_NUnaryS;
+   i->ARMin.NUnaryS.op   = op;
+   i->ARMin.NUnaryS.src  = src;
+   i->ARMin.NUnaryS.dst  = dst;
+   i->ARMin.NUnaryS.size = size;
+   i->ARMin.NUnaryS.Q    = Q;
+   return i;
+}
+
+ARMInstr* ARMInstr_NDual ( ARMNeonDualOp op, HReg nQ, HReg mQ,
+                           UInt size, Bool Q ) {
+   ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag                = ARMin_NDual;
+   i->ARMin.NDual.op   = op;
+   i->ARMin.NDual.arg1 = nQ;
+   i->ARMin.NDual.arg2 = mQ;
+   i->ARMin.NDual.size = size;
+   i->ARMin.NDual.Q    = Q;
+   return i;
+}
+
+ARMInstr* ARMInstr_NBinary ( ARMNeonBinOp op,
+                             HReg dst, HReg argL, HReg argR,
+                             UInt size, Bool Q ) {
+   ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag                = ARMin_NBinary;
+   i->ARMin.NBinary.op   = op;
+   i->ARMin.NBinary.argL = argL;
+   i->ARMin.NBinary.argR = argR;
+   i->ARMin.NBinary.dst  = dst;
+   i->ARMin.NBinary.size = size;
+   i->ARMin.NBinary.Q    = Q;
+   return i;
+}
+
+ARMInstr* ARMInstr_NeonImm (HReg dst, ARMNImm* imm ) {
+   ARMInstr *i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag         = ARMin_NeonImm;
+   i->ARMin.NeonImm.dst = dst;
+   i->ARMin.NeonImm.imm = imm;
+   return i;
+}
+
+ARMInstr* ARMInstr_NCMovQ ( ARMCondCode cond, HReg dst, HReg src ) {
+   ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag               = ARMin_NCMovQ;
+   i->ARMin.NCMovQ.cond = cond;
+   i->ARMin.NCMovQ.dst  = dst;
+   i->ARMin.NCMovQ.src  = src;
+   vassert(cond != ARMcc_AL);
+   return i;
+}
+
+ARMInstr* ARMInstr_NShift ( ARMNeonShiftOp op,
+                            HReg dst, HReg argL, HReg argR,
+                            UInt size, Bool Q ) {
+   ARMInstr* i = LibVEX_Alloc(sizeof(ARMInstr));
+   i->tag                = ARMin_NShift;
+   i->ARMin.NShift.op   = op;
+   i->ARMin.NShift.argL = argL;
+   i->ARMin.NShift.argR = argR;
+   i->ARMin.NShift.dst  = dst;
+   i->ARMin.NShift.size = size;
+   i->ARMin.NShift.Q    = Q;
+   return i;
+}
+
+/* Helper copy-pasted from isel.c */
+static Bool fitsIn8x4 ( UInt* u8, UInt* u4, UInt u )
+{
+   UInt i;
+   for (i = 0; i < 16; i++) {
+      if (0 == (u & 0xFFFFFF00)) {
+         *u8 = u;
+         *u4 = i;
+         return True;
+      }
+      u = ROR32(u, 30);
+   }
+   vassert(i == 16);
+   return False;
+}
+
+ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) {
+   UInt u8, u4;
+   ARMInstr *i = LibVEX_Alloc(sizeof(ARMInstr));
+   /* Try to generate single ADD if possible */
+   if (fitsIn8x4(&u8, &u4, imm32)) {
+      i->tag            = ARMin_Alu;
+      i->ARMin.Alu.op   = ARMalu_ADD;
+      i->ARMin.Alu.dst  = rD;
+      i->ARMin.Alu.argL = rN;
+      i->ARMin.Alu.argR = ARMRI84_I84(u8, u4);
+   } else {
+      i->tag               = ARMin_Add32;
+      i->ARMin.Add32.rD    = rD;
+      i->ARMin.Add32.rN    = rN;
+      i->ARMin.Add32.imm32 = imm32;
+   }
+   return i;
+}
+
+/* ... */
+

 void ppARMInstr ( ARMInstr* i ) {
    switch (i->tag) {
       case ARMin_Alu:
 void ppARMInstr ( ARMInstr* i ) {
    switch (i->tag) {
       case ARMin_Alu:


@@ -1043,13 +1744,122 @@ void ppARMInstr ( ARMInstr* i ) {
          vex_printf("mfence (mcr 15,0,r0,c7,c10,4; 15,0,r0,c7,c10,5; "
                     "15,0,r0,c7,c5,4)");
          return;
          vex_printf("mfence (mcr 15,0,r0,c7,c10,4; 15,0,r0,c7,c10,5; "
                     "15,0,r0,c7,c5,4)");
          return;

-
+      case ARMin_NLdStQ:
+         if (i->ARMin.NLdStQ.isLoad)
+            vex_printf("vld1.32 {");
+         else
+            vex_printf("vst1.32 {");
+         ppHRegARM(i->ARMin.NLdStQ.dQ);
+         vex_printf("} ");
+         ppARMAModeN(i->ARMin.NLdStQ.amode);
+         return;
+      case ARMin_NLdStD:
+         if (i->ARMin.NLdStD.isLoad)
+            vex_printf("vld1.32 {");
+         else
+            vex_printf("vst1.32 {");
+         ppHRegARM(i->ARMin.NLdStD.dD);
+         vex_printf("} ");
+         ppARMAModeN(i->ARMin.NLdStD.amode);
+         return;
+      case ARMin_NUnary:
+         vex_printf("%s%s%s  ",
+                    showARMNeonUnOp(i->ARMin.NUnary.op),
+                    showARMNeonUnOpDataType(i->ARMin.NUnary.op),
+                    showARMNeonDataSize(i));
+         ppHRegARM(i->ARMin.NUnary.dst);
+         vex_printf(", ");
+         ppHRegARM(i->ARMin.NUnary.src);
+         if (i->ARMin.NUnary.op == ARMneon_EQZ)
+            vex_printf(", #0");
+         if (i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedS ||
+             i->ARMin.NUnary.op == ARMneon_VCVTFtoFixedU ||
+             i->ARMin.NUnary.op == ARMneon_VCVTFixedStoF ||
+             i->ARMin.NUnary.op == ARMneon_VCVTFixedUtoF) {
+            vex_printf(", #%d", i->ARMin.NUnary.size);
+         }
+         if (i->ARMin.NUnary.op == ARMneon_VQSHLNSS ||
+             i->ARMin.NUnary.op == ARMneon_VQSHLNUU ||
+             i->ARMin.NUnary.op == ARMneon_VQSHLNUS) {
+            UInt size;
+            size = i->ARMin.NUnary.size;
+            if (size & 0x40) {
+               vex_printf(", #%d", size - 64);
+            } else if (size & 0x20) {
+               vex_printf(", #%d", size - 32);
+            } else if (size & 0x10) {
+               vex_printf(", #%d", size - 16);
+            } else if (size & 0x08) {
+               vex_printf(", #%d", size - 8);
+            }
+         }
+         return;
+      case ARMin_NUnaryS:
+         vex_printf("%s%s%s  ",
+                    showARMNeonUnOpS(i->ARMin.NUnary.op),
+                    showARMNeonUnOpSDataType(i->ARMin.NUnary.op),
+                    showARMNeonDataSize(i));
+         ppARMNRS(i->ARMin.NUnaryS.dst);
+         vex_printf(", ");
+         ppARMNRS(i->ARMin.NUnaryS.src);
+         return;
+      case ARMin_NShift:
+         vex_printf("%s%s%s  ",
+                    showARMNeonShiftOp(i->ARMin.NShift.op),
+                    showARMNeonShiftOpDataType(i->ARMin.NShift.op),
+                    showARMNeonDataSize(i));
+         ppHRegARM(i->ARMin.NShift.dst);
+         vex_printf(", ");
+         ppHRegARM(i->ARMin.NShift.argL);
+         vex_printf(", ");
+         ppHRegARM(i->ARMin.NShift.argR);
+         return;
+      case ARMin_NDual:
+         vex_printf("%s%s%s  ",
+                    showARMNeonDualOp(i->ARMin.NDual.op),
+                    showARMNeonDualOpDataType(i->ARMin.NDual.op),
+                    showARMNeonDataSize(i));
+         ppHRegARM(i->ARMin.NDual.arg1);
+         vex_printf(", ");
+         ppHRegARM(i->ARMin.NDual.arg2);
+         return;
+      case ARMin_NBinary:
+         vex_printf("%s%s%s",
+                    showARMNeonBinOp(i->ARMin.NBinary.op),
+                    showARMNeonBinOpDataType(i->ARMin.NBinary.op),
+                    showARMNeonDataSize(i));
+         vex_printf("  ");
+         ppHRegARM(i->ARMin.NBinary.dst);
+         vex_printf(", ");
+         ppHRegARM(i->ARMin.NBinary.argL);
+         vex_printf(", ");
+         ppHRegARM(i->ARMin.NBinary.argR);
+         return;
+      case ARMin_NeonImm:
+         vex_printf("vmov  ");
+         ppHRegARM(i->ARMin.NeonImm.dst);
+         vex_printf(", ");
+         ppARMNImm(i->ARMin.NeonImm.imm);
+         return;
+      case ARMin_NCMovQ:
+         vex_printf("vmov%s ", showARMCondCode(i->ARMin.NCMovQ.cond));
+         ppHRegARM(i->ARMin.NCMovQ.dst);
+         vex_printf(", ");
+         ppHRegARM(i->ARMin.NCMovQ.src);
+         return;
+      case ARMin_Add32:
+         vex_printf("add32 ");
+         ppHRegARM(i->ARMin.Add32.rD);
+         vex_printf(", ");
+         ppHRegARM(i->ARMin.Add32.rN);
+         vex_printf(", ");
+         vex_printf("%d", i->ARMin.Add32.imm32);
+         return;
+      default:

       unhandled:
          vex_printf("ppARMInstr: unhandled case (tag %d)", (Int)i->tag);
          vpanic("ppARMInstr(1)");
          return;
       unhandled:
          vex_printf("ppARMInstr: unhandled case (tag %d)", (Int)i->tag);
          vpanic("ppARMInstr(1)");
          return;

-      default:
-         vpanic("ppARMInstr(2)");

    }
 }
 
    }
 }
 


@@ -1268,6 +2078,58 @@ void getRegUsage_ARMInstr ( HRegUsage* u, ARMInstr* i, Bool mode64 )
          return;
       case ARMin_MFence:
          return;
          return;
       case ARMin_MFence:
          return;

+      case ARMin_NLdStQ:
+         if (i->ARMin.NLdStQ.isLoad)
+            addHRegUse(u, HRmWrite, i->ARMin.NLdStQ.dQ);
+         else
+            addHRegUse(u, HRmRead, i->ARMin.NLdStQ.dQ);
+         addRegUsage_ARMAModeN(u, i->ARMin.NLdStQ.amode);
+         return;
+      case ARMin_NLdStD:
+         if (i->ARMin.NLdStD.isLoad)
+            addHRegUse(u, HRmWrite, i->ARMin.NLdStD.dD);
+         else
+            addHRegUse(u, HRmRead, i->ARMin.NLdStD.dD);
+         addRegUsage_ARMAModeN(u, i->ARMin.NLdStD.amode);
+         return;
+      case ARMin_NUnary:
+         addHRegUse(u, HRmWrite, i->ARMin.NUnary.dst);
+         addHRegUse(u, HRmRead, i->ARMin.NUnary.src);
+         return;
+      case ARMin_NUnaryS:
+         addHRegUse(u, HRmWrite, i->ARMin.NUnaryS.dst->reg);
+         addHRegUse(u, HRmRead, i->ARMin.NUnaryS.src->reg);
+         return;
+      case ARMin_NShift:
+         addHRegUse(u, HRmWrite, i->ARMin.NShift.dst);
+         addHRegUse(u, HRmRead, i->ARMin.NShift.argL);
+         addHRegUse(u, HRmRead, i->ARMin.NShift.argR);
+         return;
+      case ARMin_NDual:
+         addHRegUse(u, HRmWrite, i->ARMin.NDual.arg1);
+         addHRegUse(u, HRmWrite, i->ARMin.NDual.arg2);
+         addHRegUse(u, HRmRead, i->ARMin.NDual.arg1);
+         addHRegUse(u, HRmRead, i->ARMin.NDual.arg2);
+         return;
+      case ARMin_NBinary:
+         addHRegUse(u, HRmWrite, i->ARMin.NBinary.dst);
+         /* TODO: sometimes dst is also being read! */
+         // XXX fix this
+         addHRegUse(u, HRmRead, i->ARMin.NBinary.argL);
+         addHRegUse(u, HRmRead, i->ARMin.NBinary.argR);
+         return;
+      case ARMin_NeonImm:
+         addHRegUse(u, HRmWrite, i->ARMin.NeonImm.dst);
+         return;
+      case ARMin_NCMovQ:
+         addHRegUse(u, HRmWrite, i->ARMin.NCMovQ.dst);
+         addHRegUse(u, HRmRead,  i->ARMin.NCMovQ.dst);
+         addHRegUse(u, HRmRead,  i->ARMin.NCMovQ.src);
+         return;
+      case ARMin_Add32:
+         addHRegUse(u, HRmWrite, i->ARMin.Add32.rD);
+         addHRegUse(u, HRmRead, i->ARMin.Add32.rN);
+         return;

       unhandled:
       default:
          ppARMInstr(i);
       unhandled:
       default:
          ppARMInstr(i);


@@ -1394,6 +2256,48 @@ void mapRegs_ARMInstr ( HRegRemap* m, ARMInstr* i, Bool mode64 )
          return;
       case ARMin_MFence:
          return;
          return;
       case ARMin_MFence:
          return;

+      case ARMin_NLdStQ:
+         i->ARMin.NLdStQ.dQ = lookupHRegRemap(m, i->ARMin.NLdStQ.dQ);
+         mapRegs_ARMAModeN(m, i->ARMin.NLdStQ.amode);
+         return;
+      case ARMin_NLdStD:
+         i->ARMin.NLdStD.dD = lookupHRegRemap(m, i->ARMin.NLdStD.dD);
+         mapRegs_ARMAModeN(m, i->ARMin.NLdStD.amode);
+         return;
+      case ARMin_NUnary:
+         i->ARMin.NUnary.src = lookupHRegRemap(m, i->ARMin.NUnary.src);
+         i->ARMin.NUnary.dst = lookupHRegRemap(m, i->ARMin.NUnary.dst);
+         return;
+      case ARMin_NUnaryS:
+         i->ARMin.NUnaryS.src->reg
+            = lookupHRegRemap(m, i->ARMin.NUnaryS.src->reg);
+         i->ARMin.NUnaryS.dst->reg
+            = lookupHRegRemap(m, i->ARMin.NUnaryS.dst->reg);
+         return;
+      case ARMin_NShift:
+         i->ARMin.NShift.dst = lookupHRegRemap(m, i->ARMin.NShift.dst);
+         i->ARMin.NShift.argL = lookupHRegRemap(m, i->ARMin.NShift.argL);
+         i->ARMin.NShift.argR = lookupHRegRemap(m, i->ARMin.NShift.argR);
+         return;
+      case ARMin_NDual:
+         i->ARMin.NDual.arg1 = lookupHRegRemap(m, i->ARMin.NDual.arg1);
+         i->ARMin.NDual.arg2 = lookupHRegRemap(m, i->ARMin.NDual.arg2);
+         return;
+      case ARMin_NBinary:
+         i->ARMin.NBinary.argL = lookupHRegRemap(m, i->ARMin.NBinary.argL);
+         i->ARMin.NBinary.argR = lookupHRegRemap(m, i->ARMin.NBinary.argR);
+         i->ARMin.NBinary.dst  = lookupHRegRemap(m, i->ARMin.NBinary.dst);
+         return;
+      case ARMin_NeonImm:
+         i->ARMin.NeonImm.dst = lookupHRegRemap(m, i->ARMin.NeonImm.dst);
+         return;
+      case ARMin_NCMovQ:
+         i->ARMin.NCMovQ.dst = lookupHRegRemap(m, i->ARMin.NCMovQ.dst);
+         i->ARMin.NCMovQ.src = lookupHRegRemap(m, i->ARMin.NCMovQ.src);
+         return;
+      case ARMin_Add32:
+         i->ARMin.Add32.rD = lookupHRegRemap(m, i->ARMin.Add32.rD);
+         i->ARMin.Add32.rN = lookupHRegRemap(m, i->ARMin.Add32.rN);

       unhandled:
       default:
          ppARMInstr(i);
       unhandled:
       default:
          ppARMInstr(i);


@@ -1483,7 +2387,14 @@ void genSpill_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
          }
          return;
       }
          }
          return;
       }

-      default: 
+      case HRcVec128: {
+         HReg r8  = hregARM_R8();
+         HReg r12 = hregARM_R12();
+         *i1 = ARMInstr_Add32(r12, r8, offsetB);
+         *i2 = ARMInstr_NLdStQ(False, rreg, mkARMAModeN_R(r12));
+         return;
+      }
+      default:

          ppHRegClass(rclass);
          vpanic("genSpill_ARM: unimplemented regclass");
    }
          ppHRegClass(rclass);
          vpanic("genSpill_ARM: unimplemented regclass");
    }


@@ -1529,7 +2440,14 @@ void genReload_ARM ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2,
          }
          return;
       }
          }
          return;
       }

-      default: 
+      case HRcVec128: {
+         HReg r8  = hregARM_R8();
+         HReg r12 = hregARM_R12();
+         *i1 = ARMInstr_Add32(r12, r8, offsetB);
+         *i2 = ARMInstr_NLdStQ(True, rreg, mkARMAModeN_R(r12));
+         return;
+      }
+      default:

          ppHRegClass(rclass);
          vpanic("genReload_ARM: unimplemented regclass");
    }
          ppHRegClass(rclass);
          vpanic("genReload_ARM: unimplemented regclass");
    }


@@ -1553,10 +2471,12 @@ static inline UChar iregNo ( HReg r )
 static inline UChar dregNo ( HReg r )
 {
    UInt n;
 static inline UChar dregNo ( HReg r )
 {
    UInt n;

+   if (hregClass(r) != HRcFlt64)
+      ppHRegClass(hregClass(r));

    vassert(hregClass(r) == HRcFlt64);
    vassert(!hregIsVirtual(r));
    n = hregNumber(r);
    vassert(hregClass(r) == HRcFlt64);
    vassert(!hregIsVirtual(r));
    n = hregNumber(r);

-   vassert(n <= 15);
+   vassert(n <= 31);

    return toUChar(n);
 }
 
    return toUChar(n);
 }
 


@@ -1570,6 +2490,16 @@ static inline UChar fregNo ( HReg r )
    return toUChar(n);
 }
 
    return toUChar(n);
 }
 

+static inline UChar qregNo ( HReg r )
+{
+   UInt n;
+   vassert(hregClass(r) == HRcVec128);
+   vassert(!hregIsVirtual(r));
+   n = hregNumber(r);
+   vassert(n <= 15);
+   return toUChar(n);
+}
+

 #define BITS4(zzb3,zzb2,zzb1,zzb0) \
    (((zzb3) << 3) | ((zzb2) << 2) | ((zzb1) << 1) | (zzb0))
 #define X0000  BITS4(0,0,0,0)
 #define BITS4(zzb3,zzb2,zzb1,zzb0) \
    (((zzb3) << 3) | ((zzb2) << 2) | ((zzb1) << 1) | (zzb0))
 #define X0000  BITS4(0,0,0,0)


@@ -1677,19 +2607,57 @@ static UInt* imm32_to_iregNo ( UInt* p, Int rD, UInt imm32 )
       *p++ = imm32;
    }
 #else
       *p++ = imm32;
    }
 #else

-   /* Generate movw rD, #low16.  Then, if the high 16 are
-      nonzero, generate movt rD, #high16. */
-   UInt lo16 = imm32 & 0xFFFF;
-   UInt hi16 = (imm32 >> 16) & 0xFFFF;
-   instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
-                    (lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF,
-                    lo16 & 0xF);
-   *p++ = instr;
-   if (hi16 != 0) {
-      instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
-                       (hi16 >> 8) & 0xF, (hi16 >> 4) & 0xF,
-                       hi16 & 0xF);
+   if (VEX_ARM_ARCHLEVEL(arm_hwcaps) > 6) {
+      /* Generate movw rD, #low16.  Then, if the high 16 are
+         nonzero, generate movt rD, #high16. */
+      UInt lo16 = imm32 & 0xFFFF;
+      UInt hi16 = (imm32 >> 16) & 0xFFFF;
+      instr = XXXXXXXX(0xE, 0x3, 0x0, (lo16 >> 12) & 0xF, rD,
+                       (lo16 >> 8) & 0xF, (lo16 >> 4) & 0xF,
+                       lo16 & 0xF);

       *p++ = instr;
       *p++ = instr;

+      if (hi16 != 0) {
+         instr = XXXXXXXX(0xE, 0x3, 0x4, (hi16 >> 12) & 0xF, rD,
+                          (hi16 >> 8) & 0xF, (hi16 >> 4) & 0xF,
+                          hi16 & 0xF);
+         *p++ = instr;
+      }
+   } else {
+      UInt imm, rot;
+      UInt op = X1010;
+      UInt rN = 0;
+      if ((imm32 & 0xFF) || (imm32 == 0)) {
+         imm = imm32 & 0xFF;
+         rot = 0;
+         instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
+         *p++ = instr;
+         op = X1000;
+         rN = rD;
+      }
+      if (imm32 & 0xFF000000) {
+         imm = (imm32 >> 24) & 0xFF;
+         rot = 4;
+         instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
+         *p++ = instr;
+         op = X1000;
+         rN = rD;
+      }
+      if (imm32 & 0xFF0000) {
+         imm = (imm32 >> 16) & 0xFF;
+         rot = 8;
+         instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
+         *p++ = instr;
+         op = X1000;
+         rN = rD;
+      }
+      if (imm32 & 0xFF00) {
+         imm = (imm32 >> 8) & 0xFF;
+         rot = 12;
+         instr = XXXXXXXX(0xE, 0x3, op, rN, rD, rot, imm >> 4, imm & 0xF);
+         *p++ = instr;
+         op = X1000;
+         rN = rD;
+      }

    }
 #endif
    return p;
    }
 #endif
    return p;


@@ -1728,7 +2696,8 @@ Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr* i,
          instr = skeletal_RI84(argR);
          instr |= XXXXX___(X1110, (1 & (subopc >> 3)),
                            (subopc << 1) & 0xF, rN, rD);
          instr = skeletal_RI84(argR);
          instr |= XXXXX___(X1110, (1 & (subopc >> 3)),
                            (subopc << 1) & 0xF, rN, rD);

-         if (i->ARMin.Alu.op == ARMalu_ADDS || i->ARMin.Alu.op == ARMalu_SUBS) {
+         if (i->ARMin.Alu.op == ARMalu_ADDS
+             || i->ARMin.Alu.op == ARMalu_SUBS) {

             instr |= 1<<20;  /* set the S bit */
          }
          *p++ = instr;
             instr |= 1<<20;  /* set the S bit */
          }
          *p++ = instr;


@@ -2282,6 +3251,802 @@ Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr* i,
          *p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4  (ISB) */
          goto done;
       }
          *p++ = 0xEE070F95; /* mcr 15,0,r0,c7,c5,4  (ISB) */
          goto done;
       }

+      case ARMin_NLdStQ: {
+         UInt regD = qregNo(i->ARMin.NLdStQ.dQ) << 1;
+         UInt regN, regM;
+         UInt D = regD >> 4;
+         UInt bL = i->ARMin.NLdStQ.isLoad ? 1 : 0;
+         UInt insn;
+         vassert(hregClass(i->ARMin.NLdStQ.dQ) == HRcVec128);
+         regD &= 0xF;
+         if (i->ARMin.NLdStQ.amode->tag == ARMamN_RR) {
+            regN = iregNo(i->ARMin.NLdStQ.amode->ARMamN.RR.rN);
+            regM = iregNo(i->ARMin.NLdStQ.amode->ARMamN.RR.rM);
+         } else {
+            regN = iregNo(i->ARMin.NLdStQ.amode->ARMamN.R.rN);
+            regM = 15;
+         }
+         insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
+                              regN, regD, X1010, X1000, regM);
+         *p++ = insn;
+         goto done;
+      }
+      case ARMin_NLdStD: {
+         UInt regD = dregNo(i->ARMin.NLdStD.dD);
+         UInt regN, regM;
+         UInt D = regD >> 4;
+         UInt bL = i->ARMin.NLdStD.isLoad ? 1 : 0;
+         UInt insn;
+         vassert(hregClass(i->ARMin.NLdStD.dD) == HRcFlt64);
+         regD &= 0xF;
+         if (i->ARMin.NLdStD.amode->tag == ARMamN_RR) {
+            regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rN);
+            regM = iregNo(i->ARMin.NLdStD.amode->ARMamN.RR.rM);
+         } else {
+            regN = iregNo(i->ARMin.NLdStD.amode->ARMamN.R.rN);
+            regM = 15;
+         }
+         insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0),
+                              regN, regD, X0111, X1000, regM);
+         *p++ = insn;
+         goto done;
+      }
+      case ARMin_NUnaryS: {
+         UInt Q = i->ARMin.NUnaryS.Q ? 1 : 0;
+         UInt regD, D;
+         UInt regM, M;
+         UInt size = i->ARMin.NUnaryS.size;
+         UInt insn;
+         UInt opc, opc1, opc2;
+         switch (i->ARMin.NUnaryS.op) {
+            case ARMneon_VDUP:
+               if (i->ARMin.NUnaryS.size >= 16)
+                  goto bad;
+               if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Reg)
+                  goto bad;
+               if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar)
+                  goto bad;
+               regD = (hregClass(i->ARMin.NUnaryS.dst->reg) == HRcVec128)
+                        ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1)
+                        : dregNo(i->ARMin.NUnaryS.dst->reg);
+               regM = (hregClass(i->ARMin.NUnaryS.src->reg) == HRcVec128)
+                        ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1)
+                        : dregNo(i->ARMin.NUnaryS.src->reg);
+               D = regD >> 4;
+               M = regM >> 4;
+               regD &= 0xf;
+               regM &= 0xf;
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1),
+                               (i->ARMin.NUnaryS.size & 0xf), regD,
+                               X1100, BITS4(0,Q,M,0), regM);
+               *p++ = insn;
+               goto done;
+            case ARMneon_SETELEM:
+               regD = Q ? (qregNo(i->ARMin.NUnaryS.dst->reg) << 1) :
+                                dregNo(i->ARMin.NUnaryS.dst->reg);
+               regM = iregNo(i->ARMin.NUnaryS.src->reg);
+               M = regM >> 4;
+               D = regD >> 4;
+               regM &= 0xF;
+               regD &= 0xF;
+               if (i->ARMin.NUnaryS.dst->tag != ARMNRS_Scalar)
+                  goto bad;
+               switch (size) {
+                  case 0:
+                     if (i->ARMin.NUnaryS.dst->index > 7)
+                        goto bad;
+                     opc = X1000 | i->ARMin.NUnaryS.dst->index;
+                     break;
+                  case 1:
+                     if (i->ARMin.NUnaryS.dst->index > 3)
+                        goto bad;
+                     opc = X0001 | (i->ARMin.NUnaryS.dst->index << 1);
+                     break;
+                  case 2:
+                     if (i->ARMin.NUnaryS.dst->index > 1)
+                        goto bad;
+                     opc = X0000 | (i->ARMin.NUnaryS.dst->index << 2);
+                     break;
+                  default:
+                     goto bad;
+               }
+               opc1 = (opc >> 2) & 3;
+               opc2 = opc & 3;
+               insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),0),
+                               regD, regM, X1011,
+                               BITS4(D,(opc2 >> 1),(opc2 & 1),1), X0000);
+               *p++ = insn;
+               goto done;
+            case ARMneon_GETELEMU:
+               regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) :
+                                dregNo(i->ARMin.NUnaryS.src->reg);
+               regD = iregNo(i->ARMin.NUnaryS.dst->reg);
+               M = regM >> 4;
+               D = regD >> 4;
+               regM &= 0xF;
+               regD &= 0xF;
+               if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar)
+                  goto bad;
+               switch (size) {
+                  case 0:
+                     if (Q && i->ARMin.NUnaryS.src->index > 7) {
+                        regM++;
+                        i->ARMin.NUnaryS.src->index -= 8;
+                     }
+                     if (i->ARMin.NUnaryS.src->index > 7)
+                        goto bad;
+                     opc = X1000 | i->ARMin.NUnaryS.src->index;
+                     break;
+                  case 1:
+                     if (Q && i->ARMin.NUnaryS.src->index > 3) {
+                        regM++;
+                        i->ARMin.NUnaryS.src->index -= 4;
+                     }
+                     if (i->ARMin.NUnaryS.src->index > 3)
+                        goto bad;
+                     opc = X0001 | (i->ARMin.NUnaryS.src->index << 1);
+                     break;
+                  case 2:
+                     goto bad;
+                  default:
+                     goto bad;
+               }
+               opc1 = (opc >> 2) & 3;
+               opc2 = opc & 3;
+               insn = XXXXXXXX(0xE, X1110, BITS4(1,(opc1 >> 1),(opc1 & 1),1),
+                               regM, regD, X1011,
+                               BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000);
+               *p++ = insn;
+               goto done;
+            case ARMneon_GETELEMS:
+               regM = Q ? (qregNo(i->ARMin.NUnaryS.src->reg) << 1) :
+                                dregNo(i->ARMin.NUnaryS.src->reg);
+               regD = iregNo(i->ARMin.NUnaryS.dst->reg);
+               M = regM >> 4;
+               D = regD >> 4;
+               regM &= 0xF;
+               regD &= 0xF;
+               if (i->ARMin.NUnaryS.src->tag != ARMNRS_Scalar)
+                  goto bad;
+               switch (size) {
+                  case 0:
+                     if (Q && i->ARMin.NUnaryS.src->index > 7) {
+                        regM++;
+                        i->ARMin.NUnaryS.src->index -= 8;
+                     }
+                     if (i->ARMin.NUnaryS.src->index > 7)
+                        goto bad;
+                     opc = X1000 | i->ARMin.NUnaryS.src->index;
+                     break;
+                  case 1:
+                     if (Q && i->ARMin.NUnaryS.src->index > 3) {
+                        regM++;
+                        i->ARMin.NUnaryS.src->index -= 4;
+                     }
+                     if (i->ARMin.NUnaryS.src->index > 3)
+                        goto bad;
+                     opc = X0001 | (i->ARMin.NUnaryS.src->index << 1);
+                     break;
+                  case 2:
+                     if (Q && i->ARMin.NUnaryS.src->index > 1) {
+                        regM++;
+                        i->ARMin.NUnaryS.src->index -= 2;
+                     }
+                     if (i->ARMin.NUnaryS.src->index > 1)
+                        goto bad;
+                     opc = X0000 | (i->ARMin.NUnaryS.src->index << 2);
+                     break;
+                  default:
+                     goto bad;
+               }
+               opc1 = (opc >> 2) & 3;
+               opc2 = opc & 3;
+               insn = XXXXXXXX(0xE, X1110, BITS4(0,(opc1 >> 1),(opc1 & 1),1),
+                               regM, regD, X1011,
+                               BITS4(M,(opc2 >> 1),(opc2 & 1),1), X0000);
+               *p++ = insn;
+               goto done;
+            default:
+               goto bad;
+         }
+      }
+      case ARMin_NUnary: {
+         UInt Q = i->ARMin.NUnary.Q ? 1 : 0;
+         UInt regD = (hregClass(i->ARMin.NUnary.dst) == HRcVec128)
+                       ? (qregNo(i->ARMin.NUnary.dst) << 1)
+                       : dregNo(i->ARMin.NUnary.dst);
+         UInt regM, M;
+         UInt D = regD >> 4;
+         UInt sz1 = i->ARMin.NUnary.size >> 1;
+         UInt sz2 = i->ARMin.NUnary.size & 1;
+         UInt sz = i->ARMin.NUnary.size;
+         UInt insn;
+         UInt F = 0; /* TODO: floating point EQZ ??? */
+         if (i->ARMin.NUnary.op != ARMneon_DUP) {
+            regM = (hregClass(i->ARMin.NUnary.src) == HRcVec128) 
+                     ? (qregNo(i->ARMin.NUnary.src) << 1)
+                     : dregNo(i->ARMin.NUnary.src);
+            M = regM >> 4;
+         } else {
+            regM = iregNo(i->ARMin.NUnary.src);
+            M = regM >> 4;
+         }
+         regD &= 0xF;
+         regM &= 0xF;
+         switch (i->ARMin.NUnary.op) {
+            case ARMneon_COPY: /* VMOV reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regM, regD, X0001,
+                               BITS4(M,Q,M,1), regM);
+               break;
+            case ARMneon_COPYN: /* VMOVN regD, regQ */
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
+                               regD, X0010, BITS4(0,0,M,0), regM);
+               break;
+            case ARMneon_COPYQNSS: /* VQMOVN regD, regQ */
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
+                               regD, X0010, BITS4(1,0,M,0), regM);
+               break;
+            case ARMneon_COPYQNUS: /* VQMOVUN regD, regQ */
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
+                               regD, X0010, BITS4(0,1,M,0), regM);
+               break;
+            case ARMneon_COPYQNUU: /* VQMOVN regD, regQ */
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
+                               regD, X0010, BITS4(1,1,M,0), regM);
+               break;
+            case ARMneon_COPYLS: /* VMOVL regQ, regD */
+               if (sz >= 3)
+                  goto bad;
+               insn = XXXXXXXX(0xF, X0010,
+                               BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0),
+                               BITS4((sz == 0) ? 1 : 0,0,0,0),
+                               regD, X1010, BITS4(0,0,M,1), regM);
+               break;
+            case ARMneon_COPYLU: /* VMOVL regQ, regD */
+               if (sz >= 3)
+                  goto bad;
+               insn = XXXXXXXX(0xF, X0011,
+                               BITS4(1,D,(sz == 2) ? 1 : 0,(sz == 1) ? 1 : 0),
+                               BITS4((sz == 0) ? 1 : 0,0,0,0),
+                               regD, X1010, BITS4(0,0,M,1), regM);
+               break;
+            case ARMneon_NOT: /* VMVN reg, reg*/
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101,
+                               BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_EQZ:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1),
+                               regD, BITS4(0,F,0,1), BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_CNT:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0000, regD, X0101,
+                               BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_CLZ:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
+                               regD, X0100, BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_CLS:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
+                               regD, X0100, BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_ABS:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,1),
+                               regD, X0011, BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_DUP:
+               sz1 = i->ARMin.NUnary.size == 0 ? 1 : 0;
+               sz2 = i->ARMin.NUnary.size == 1 ? 1 : 0;
+               vassert(sz1 + sz2 < 2);
+               insn = XXXXXXXX(0xE, X1110, BITS4(1, sz1, Q, 0), regD, regM,
+                               X1011, BITS4(D,0,sz2,1), X0000);
+               break;
+            case ARMneon_REV16:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
+                               regD, BITS4(0,0,0,1), BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_REV32:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
+                               regD, BITS4(0,0,0,0), BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_REV64:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
+                               regD, BITS4(0,0,0,0), BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_PADDLU:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
+                               regD, X0010, BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_PADDLS:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,0,0),
+                               regD, X0010, BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_VQSHLNUU:
+               insn = XXXXXXXX(0xF, X0011,
+                               (1 << 3) | (D << 2) | ((sz >> 4) & 3),
+                               sz & 0xf, regD, X0111,
+                               BITS4(sz >> 6,Q,M,1), regM);
+               break;
+            case ARMneon_VQSHLNSS:
+               insn = XXXXXXXX(0xF, X0010,
+                               (1 << 3) | (D << 2) | ((sz >> 4) & 3),
+                               sz & 0xf, regD, X0111,
+                               BITS4(sz >> 6,Q,M,1), regM);
+               break;
+            case ARMneon_VQSHLNUS:
+               insn = XXXXXXXX(0xF, X0011,
+                               (1 << 3) | (D << 2) | ((sz >> 4) & 3),
+                               sz & 0xf, regD, X0110,
+                               BITS4(sz >> 6,Q,M,1), regM);
+               break;
+            case ARMneon_VCVTFtoS:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111,
+                               BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_VCVTFtoU:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0111,
+                               BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_VCVTStoF:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110,
+                               BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_VCVTUtoF:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0110,
+                               BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_VCVTFtoFixedU:
+               sz1 = (sz >> 5) & 1;
+               sz2 = (sz >> 4) & 1;
+               sz &= 0xf;
+               insn = XXXXXXXX(0xF, X0011,
+                               BITS4(1,D,sz1,sz2), sz, regD, X1111,
+                               BITS4(0,Q,M,1), regM);
+               break;
+            case ARMneon_VCVTFtoFixedS:
+               sz1 = (sz >> 5) & 1;
+               sz2 = (sz >> 4) & 1;
+               sz &= 0xf;
+               insn = XXXXXXXX(0xF, X0010,
+                               BITS4(1,D,sz1,sz2), sz, regD, X1111,
+                               BITS4(0,Q,M,1), regM);
+               break;
+            case ARMneon_VCVTFixedUtoF:
+               sz1 = (sz >> 5) & 1;
+               sz2 = (sz >> 4) & 1;
+               sz &= 0xf;
+               insn = XXXXXXXX(0xF, X0011,
+                               BITS4(1,D,sz1,sz2), sz, regD, X1110,
+                               BITS4(0,Q,M,1), regM);
+               break;
+            case ARMneon_VCVTFixedStoF:
+               sz1 = (sz >> 5) & 1;
+               sz2 = (sz >> 4) & 1;
+               sz &= 0xf;
+               insn = XXXXXXXX(0xF, X0010,
+                               BITS4(1,D,sz1,sz2), sz, regD, X1110,
+                               BITS4(0,Q,M,1), regM);
+               break;
+            case ARMneon_VCVTF32toF16:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0110,
+                               BITS4(0,0,M,0), regM);
+               break;
+            case ARMneon_VCVTF16toF32:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X0110, regD, X0111,
+                               BITS4(0,0,M,0), regM);
+               break;
+            case ARMneon_VRECIP:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100,
+                               BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_VRECIPF:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101,
+                               BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_VABSFP:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111,
+                               BITS4(0,Q,M,0), regM);
+               break;
+            case ARMneon_VRSQRTEFP:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0101,
+                               BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_VRSQRTE:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100,
+                               BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_VNEGF:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1001, regD, X0111,
+                               BITS4(1,Q,M,0), regM);
+               break;
+            default:
+               goto bad;
+         }
+         *p++ = insn;
+         goto done;
+      }
+      case ARMin_NDual: {
+         UInt Q = i->ARMin.NDual.Q ? 1 : 0;
+         UInt regD = (hregClass(i->ARMin.NDual.arg1) == HRcVec128)
+                       ? (qregNo(i->ARMin.NDual.arg1) << 1)
+                       : dregNo(i->ARMin.NDual.arg1);
+         UInt regM = (hregClass(i->ARMin.NDual.arg2) == HRcVec128)
+                       ? (qregNo(i->ARMin.NDual.arg2) << 1)
+                       : dregNo(i->ARMin.NDual.arg2);
+         UInt D = regD >> 4;
+         UInt M = regM >> 4;
+         UInt sz1 = i->ARMin.NDual.size >> 1;
+         UInt sz2 = i->ARMin.NDual.size & 1;
+         UInt insn;
+         regD &= 0xF;
+         regM &= 0xF;
+         switch (i->ARMin.NDual.op) {
+            case ARMneon_TRN: /* VTRN reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
+                               regD, X0000, BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_ZIP: /* VZIP reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
+                               regD, X0001, BITS4(1,Q,M,0), regM);
+               break;
+            case ARMneon_UZP: /* VUZP reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), BITS4(sz1,sz2,1,0),
+                               regD, X0001, BITS4(0,Q,M,0), regM);
+               break;
+            default:
+               goto bad;
+         }
+         *p++ = insn;
+         goto done;
+      }
+      case ARMin_NBinary: {
+         UInt Q = i->ARMin.NBinary.Q ? 1 : 0;
+         UInt regD = (hregClass(i->ARMin.NBinary.dst) == HRcVec128)
+                       ? (qregNo(i->ARMin.NBinary.dst) << 1)
+                       : dregNo(i->ARMin.NBinary.dst);
+         UInt regN = (hregClass(i->ARMin.NBinary.argL) == HRcVec128)
+                       ? (qregNo(i->ARMin.NBinary.argL) << 1)
+                       : dregNo(i->ARMin.NBinary.argL);
+         UInt regM = (hregClass(i->ARMin.NBinary.argR) == HRcVec128)
+                       ? (qregNo(i->ARMin.NBinary.argR) << 1)
+                       : dregNo(i->ARMin.NBinary.argR);
+         UInt sz1 = i->ARMin.NBinary.size >> 1;
+         UInt sz2 = i->ARMin.NBinary.size & 1;
+         UInt D = regD >> 4;
+         UInt N = regN >> 4;
+         UInt M = regM >> 4;
+         UInt insn;
+         regD &= 0xF;
+         regM &= 0xF;
+         regN &= 0xF;
+         switch (i->ARMin.NBinary.op) {
+            case ARMneon_VAND: /* VAND reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X0001,
+                               BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VORR: /* VORR reg, reg, reg*/
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X0001,
+                               BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VXOR: /* VEOR reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X0001,
+                               BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VADD: /* VADD reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1000, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VSUB: /* VSUB reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1000, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VMINU: /* VMIN.Uxx reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0110, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VMINS: /* VMIN.Sxx reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0110, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VMAXU: /* VMAX.Uxx reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0110, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VMAXS: /* VMAX.Sxx reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0110, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VRHADDS: /* VRHADD.Sxx reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0001, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VRHADDU: /* VRHADD.Uxx reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0001, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VQADDU: /* VQADD unsigned reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0000, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VQADDS: /* VQADD signed reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0000, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VQSUBU: /* VQSUB unsigned reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0010, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VQSUBS: /* VQSUB signed reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0010, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VCGTU: /* VCGT unsigned reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0011, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VCGTS: /* VCGT signed reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0011, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VCGEU: /* VCGE unsigned reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0011, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VCGES: /* VCGE signed reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0011, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VCEQ: /* VCEQ reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1000, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VEXT: /* VEXT.8 reg, reg, #imm4*/
+               if (i->ARMin.NBinary.size >= 16)
+                  goto bad;
+               insn = XXXXXXXX(0xF, X0010, BITS4(1,D,1,1), regN, regD,
+                               i->ARMin.NBinary.size & 0xf, BITS4(N,Q,M,0),
+                               regM);
+               break;
+            case ARMneon_VMUL:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1001, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VMULLU:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,sz1,sz2), regN, regD,
+                               X1100, BITS4(N,0,M,0), regM);
+               break;
+            case ARMneon_VMULLS:
+               insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD,
+                               X1100, BITS4(N,0,M,0), regM);
+               break;
+            case ARMneon_VMULP:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1001, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VMULFP:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD,
+                               X1101, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VMULLP:
+               insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD,
+                               X1110, BITS4(N,0,M,0), regM);
+               break;
+            case ARMneon_VQDMULH:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1011, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VQRDMULH:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1011, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VQDMULL:
+               insn = XXXXXXXX(0xF, X0010, BITS4(1,D,sz1,sz2), regN, regD,
+                               X1101, BITS4(N,0,M,0), regM);
+               break;
+            case ARMneon_VTBL:
+               insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), regN, regD,
+                               X1000, BITS4(N,0,M,0), regM);
+               break;
+            case ARMneon_VPADD:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1011, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VPADDFP:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD,
+                               X1101, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VPMINU:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1010, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VPMINS:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1010, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VPMAXU:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1010, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VPMAXS:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X1010, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VADDFP: /* VADD reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD,
+                               X1101, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VSUBFP: /* VADD reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD,
+                               X1101, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VABDFP: /* VABD reg, reg, reg */
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD,
+                               X1101, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VMINF:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD,
+                               X1111, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VMAXF:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD,
+                               X1111, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VPMINF:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD,
+                               X1111, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VPMAXF:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD,
+                               X1111, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VRECPS:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1111,
+                               BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VCGTF:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,1,0), regN, regD, X1110,
+                               BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VCGEF:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,0,0), regN, regD, X1110,
+                               BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VCEQF:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,0,0), regN, regD, X1110,
+                               BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VRSQRTS:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regN, regD, X1111,
+                               BITS4(N,Q,M,1), regM);
+               break;
+            default:
+               goto bad;
+         }
+         *p++ = insn;
+         goto done;
+      }
+      case ARMin_NShift: {
+         UInt Q = i->ARMin.NShift.Q ? 1 : 0;
+         UInt regD = (hregClass(i->ARMin.NShift.dst) == HRcVec128)
+                       ? (qregNo(i->ARMin.NShift.dst) << 1)
+                       : dregNo(i->ARMin.NShift.dst);
+         UInt regM = (hregClass(i->ARMin.NShift.argL) == HRcVec128)
+                       ? (qregNo(i->ARMin.NShift.argL) << 1)
+                       : dregNo(i->ARMin.NShift.argL);
+         UInt regN = (hregClass(i->ARMin.NShift.argR) == HRcVec128)
+                       ? (qregNo(i->ARMin.NShift.argR) << 1)
+                       : dregNo(i->ARMin.NShift.argR);
+         UInt sz1 = i->ARMin.NShift.size >> 1;
+         UInt sz2 = i->ARMin.NShift.size & 1;
+         UInt D = regD >> 4;
+         UInt N = regN >> 4;
+         UInt M = regM >> 4;
+         UInt insn;
+         regD &= 0xF;
+         regM &= 0xF;
+         regN &= 0xF;
+         switch (i->ARMin.NShift.op) {
+            case ARMneon_VSHL:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0100, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VSAL:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0100, BITS4(N,Q,M,0), regM);
+               break;
+            case ARMneon_VQSHL:
+               insn = XXXXXXXX(0xF, X0011, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0100, BITS4(N,Q,M,1), regM);
+               break;
+            case ARMneon_VQSAL:
+               insn = XXXXXXXX(0xF, X0010, BITS4(0,D,sz1,sz2), regN, regD,
+                               X0100, BITS4(N,Q,M,1), regM);
+               break;
+            default:
+               goto bad;
+         }
+         *p++ = insn;
+         goto done;
+      }
+      case ARMin_NeonImm: {
+         UInt Q = (hregClass(i->ARMin.NeonImm.dst) == HRcVec128) ? 1 : 0;
+         UInt regD = Q ? (qregNo(i->ARMin.NeonImm.dst) << 1) :
+                          dregNo(i->ARMin.NeonImm.dst);
+         UInt D = regD >> 4;
+         UInt imm = i->ARMin.NeonImm.imm->imm8;
+         UInt tp = i->ARMin.NeonImm.imm->type;
+         UInt j = imm >> 7;
+         UInt imm3 = (imm >> 4) & 0x7;
+         UInt imm4 = imm & 0xF;
+         UInt cmode, op;
+         UInt insn;
+         regD &= 0xF;
+         if (tp == 9)
+            op = 1;
+         else
+            op = 0;
+         switch (tp) {
+            case 0:
+            case 1:
+            case 2:
+            case 3:
+            case 4:
+            case 5:
+               cmode = tp << 1;
+               break;
+            case 9:
+            case 6:
+               cmode = 14;
+               break;
+            case 7:
+               cmode = 12;
+               break;
+            case 8:
+               cmode = 13;
+               break;
+            case 10:
+               cmode = 15;
+               break;
+            default:
+               vpanic("ARMin_NeonImm");
+
+         }
+         insn = XXXXXXXX(0xF, BITS4(0,0,1,j), BITS4(1,D,0,0), imm3, regD,
+                         cmode, BITS4(0,Q,op,1), imm4);
+         *p++ = insn;
+         goto done;
+      }
+      case ARMin_NCMovQ: {
+         UInt cc = (UInt)i->ARMin.NCMovQ.cond;
+         UInt qM = qregNo(i->ARMin.NCMovQ.src) << 1;
+         UInt qD = qregNo(i->ARMin.NCMovQ.dst) << 1;
+         UInt vM = qM & 0xF;
+         UInt vD = qD & 0xF;
+         UInt M  = (qM >> 4) & 1;
+         UInt D  = (qD >> 4) & 1;
+         vassert(cc < 16 && cc != ARMcc_AL && cc != ARMcc_NV);
+         /* b!cc here+8: !cc A00 0000 */
+         UInt insn = XXXXXXXX(cc ^ 1, 0xA, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0);
+         *p++ = insn;
+         /* vmov qD, qM */
+         insn = XXXXXXXX(0xF, 0x2, BITS4(0,D,1,0),
+                         vM, vD, BITS4(0,0,0,1), BITS4(M,1,M,1), vM);
+         *p++ = insn;
+         goto done;
+      }
+      case ARMin_Add32: {
+         UInt regD = iregNo(i->ARMin.Add32.rD);
+         UInt regN = iregNo(i->ARMin.Add32.rN);
+         UInt imm32 = i->ARMin.Add32.imm32;
+         vassert(regD != regN);
+         /* MOV regD, imm32 */
+         p = imm32_to_iregNo((UInt *)p, regD, imm32);
+         /* ADD regD, regN, regD */
+         UInt insn = XXXXXXXX(0xE, 0, X1000, regN, regD, 0, 0, regD);
+         *p++ = insn;
+         goto done;
+      }
+      /* ... */

       default: 
          goto bad;
     }
       default: 
          goto bad;
     }


@@ -2290,7 +4055,7 @@ Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr* i,
    ppARMInstr(i);
    vpanic("emit_ARMInstr");
    /*NOTREACHED*/
    ppARMInstr(i);
    vpanic("emit_ARMInstr");
    /*NOTREACHED*/

-    
+

   done:
    vassert(((UChar*)p) - &buf[0] <= 32);
    return ((UChar*)p) - &buf[0];
   done:
    vassert(((UChar*)p) - &buf[0] <= 32);
    return ((UChar*)p) - &buf[0];

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_defs.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_defs.h
index bc3831228e0ab5064bcb538a479c296b4a9830e1..f775ce6016175089654049698f3c25fe420d6007 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_defs.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_defs.h
@@ -31,6 +31,8 @@
 #ifndef __VEX_HOST_ARM_DEFS_H
 #define __VEX_HOST_ARM_DEFS_H
 
 #ifndef __VEX_HOST_ARM_DEFS_H
 #define __VEX_HOST_ARM_DEFS_H
 

+extern UInt arm_hwcaps;
+

 
 /* --------- Registers. --------- */
 
 
 /* --------- Registers. --------- */
 


@@ -66,6 +68,14 @@ extern HReg hregARM_S27 ( void );
 extern HReg hregARM_S28 ( void );
 extern HReg hregARM_S29 ( void );
 extern HReg hregARM_S30 ( void );
 extern HReg hregARM_S28 ( void );
 extern HReg hregARM_S29 ( void );
 extern HReg hregARM_S30 ( void );

+extern HReg hregARM_Q8  ( void );
+extern HReg hregARM_Q9  ( void );
+extern HReg hregARM_Q10 ( void );
+extern HReg hregARM_Q11 ( void );
+extern HReg hregARM_Q12 ( void );
+extern HReg hregARM_Q13 ( void );
+extern HReg hregARM_Q14 ( void );
+extern HReg hregARM_Q15 ( void );

 
 /* Number of registers used arg passing in function calls */
 #define ARM_N_ARGREGS 4   /* r0, r1, r2, r3 */
 
 /* Number of registers used arg passing in function calls */
 #define ARM_N_ARGREGS 4   /* r0, r1, r2, r3 */


@@ -182,6 +192,34 @@ extern ARMAModeV* mkARMAModeV ( HReg reg, Int simm11 );
 
 extern void ppARMAModeV ( ARMAModeV* );
 
 
 extern void ppARMAModeV ( ARMAModeV* );
 

+/* --- Addressing Mode suitable for Neon --- */
+typedef
+   enum {
+      ARMamN_R,
+      ARMamN_RR
+      /* ... */
+   }
+   ARMAModeNTag;
+
+typedef
+   struct {
+      ARMAModeNTag tag;
+      union {
+         struct {
+            HReg rN;
+            HReg rM;
+         } RR;
+         struct {
+            HReg rN;
+         } R;
+         /* ... */
+      } ARMamN;
+   }
+   ARMAModeN;
+
+extern ARMAModeN* mkARMAModeN_RR ( HReg, HReg );
+extern ARMAModeN* mkARMAModeN_R ( HReg );
+extern void ppARMAModeN ( ARMAModeN* );

 
 /* --------- Reg or imm-8x4 operands --------- */
 /* a.k.a (a very restricted form of) Shifter Operand,
 
 /* --------- Reg or imm-8x4 operands --------- */
 /* a.k.a (a very restricted form of) Shifter Operand,


@@ -242,6 +280,62 @@ extern ARMRI5* ARMRI5_R  ( HReg );
 
 extern void ppARMRI5 ( ARMRI5* );
 
 
 extern void ppARMRI5 ( ARMRI5* );
 

+/* -------- Neon Immediate operand -------- */
+
+/* imm8 = abcdefgh, B = NOT(b);
+
+type | value (64bit binary)
+-----+-------------------------------------------------------------------------
+   0 | 00000000 00000000 00000000 abcdefgh 00000000 00000000 00000000 abcdefgh
+   1 | 00000000 00000000 abcdefgh 00000000 00000000 00000000 abcdefgh 00000000
+   2 | 00000000 abcdefgh 00000000 00000000 00000000 abcdefgh 00000000 00000000
+   3 | abcdefgh 00000000 00000000 00000000 abcdefgh 00000000 00000000 00000000
+   4 | 00000000 abcdefgh 00000000 abcdefgh 00000000 abcdefgh 00000000 abcdefgh
+   5 | abcdefgh 00000000 abcdefgh 00000000 abcdefgh 00000000 abcdefgh 00000000
+   6 | abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
+   7 | 00000000 00000000 abcdefgh 11111111 00000000 00000000 abcdefgh 11111111
+   8 | 00000000 abcdefgh 11111111 11111111 00000000 abcdefgh 11111111 11111111
+   9 | aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
+  10 | aBbbbbbc defgh000 00000000 00000000 aBbbbbbc defgh000 00000000 00000000
+-----+-------------------------------------------------------------------------
+
+Type 10 is:
+   (-1)^S * 2^exp * mantissa
+where S = a, exp = UInt(B:c:d) - 3, mantissa = (16 + UInt(e:f:g:h)) / 16
+*/
+
+typedef
+   struct {
+      UInt type;
+      UInt imm8;
+   }
+   ARMNImm;
+
+extern ARMNImm* ARMNImm_TI ( UInt type, UInt imm8 );
+extern ULong ARMNImm_to_Imm64 ( ARMNImm* );
+extern ARMNImm* Imm64_to_ARMNImm ( ULong );
+
+extern void ppARMNImm ( ARMNImm* );
+
+/* ------ Neon Register or Scalar Operand ------ */
+
+typedef
+   enum {
+      ARMNRS_Reg,
+      ARMNRS_Scalar
+   }
+   ARMNRS_tag;
+
+typedef
+   struct {
+      ARMNRS_tag tag;
+      HReg reg;
+      UInt index;
+   }
+   ARMNRS;
+
+extern ARMNRS* mkARMNRS(ARMNRS_tag, HReg reg, UInt index);
+extern void ppARMNRS ( ARMNRS* );

 
 /* --------- Instructions. --------- */
 
 
 /* --------- Instructions. --------- */
 


@@ -320,6 +414,143 @@ typedef
 
 extern HChar* showARMVfpUnaryOp ( ARMVfpUnaryOp op );
 
 
 extern HChar* showARMVfpUnaryOp ( ARMVfpUnaryOp op );
 

+typedef
+   enum {
+      ARMneon_VAND=70,
+      ARMneon_VORR,
+      ARMneon_VXOR,
+      ARMneon_VADD,
+      ARMneon_VADDFP,
+      ARMneon_VRHADDS,
+      ARMneon_VRHADDU,
+      ARMneon_VPADDFP,
+      ARMneon_VABDFP,
+      ARMneon_VSUB,
+      ARMneon_VSUBFP,
+      ARMneon_VMAXU,
+      ARMneon_VMAXS,
+      ARMneon_VMAXF,
+      ARMneon_VMINU,
+      ARMneon_VMINS,
+      ARMneon_VMINF,
+      ARMneon_VQADDU,
+      ARMneon_VQADDS,
+      ARMneon_VQSUBU,
+      ARMneon_VQSUBS,
+      ARMneon_VCGTU,
+      ARMneon_VCGTS,
+      ARMneon_VCGEU,
+      ARMneon_VCGES,
+      ARMneon_VCGTF,
+      ARMneon_VCGEF,
+      ARMneon_VCEQ,
+      ARMneon_VCEQF,
+      ARMneon_VEXT,
+      ARMneon_VMUL,
+      ARMneon_VMULFP,
+      ARMneon_VMULLU,
+      ARMneon_VMULLS,
+      ARMneon_VMULP,
+      ARMneon_VMULLP,
+      ARMneon_VQDMULH,
+      ARMneon_VQRDMULH,
+      ARMneon_VPADD,
+      ARMneon_VPMINU,
+      ARMneon_VPMINS,
+      ARMneon_VPMINF,
+      ARMneon_VPMAXU,
+      ARMneon_VPMAXS,
+      ARMneon_VPMAXF,
+      ARMneon_VTBL,
+      ARMneon_VQDMULL,
+      ARMneon_VDUP,
+      ARMneon_VRECIP,
+      ARMneon_VRECPS,
+      ARMneon_VRECIPF,
+      ARMneon_VRSQRTS,
+      ARMneon_VABSFP,
+      ARMneon_VRSQRTEFP,
+      ARMneon_VRSQRTE
+      /* ... */
+   }
+   ARMNeonBinOp;
+
+typedef
+   enum {
+      ARMneon_VSHL,
+      ARMneon_VSAL, /* Yah, not SAR but SAL */
+      ARMneon_VQSHL,
+      ARMneon_VQSAL
+   }
+   ARMNeonShiftOp;
+
+typedef
+   enum {
+      ARMneon_COPY,
+      ARMneon_COPYLU,
+      ARMneon_COPYLS,
+      ARMneon_COPYN,
+      ARMneon_COPYQNSS,
+      ARMneon_COPYQNUS,
+      ARMneon_COPYQNUU,
+      ARMneon_NOT,
+      ARMneon_EQZ,
+      ARMneon_DUP,
+      ARMneon_PADDLS,
+      ARMneon_PADDLU,
+      ARMneon_CNT,
+      ARMneon_CLZ,
+      ARMneon_CLS,
+      ARMneon_VCVTxFPxINT,
+      ARMneon_VQSHLNSS,
+      ARMneon_VQSHLNUU,
+      ARMneon_VQSHLNUS,
+      ARMneon_VCVTFtoU,
+      ARMneon_VCVTFtoS,
+      ARMneon_VCVTUtoF,
+      ARMneon_VCVTStoF,
+      ARMneon_VCVTFtoFixedU,
+      ARMneon_VCVTFtoFixedS,
+      ARMneon_VCVTFixedUtoF,
+      ARMneon_VCVTFixedStoF,
+      ARMneon_VCVTF16toF32,
+      ARMneon_VCVTF32toF16,
+      ARMneon_REV16,
+      ARMneon_REV32,
+      ARMneon_REV64,
+      ARMneon_ABS,
+      ARMneon_VNEGF,
+      /* ... */
+   }
+   ARMNeonUnOp;
+
+typedef
+   enum {
+      ARMneon_SETELEM,
+      ARMneon_GETELEMU,
+      ARMneon_GETELEMS
+   }
+   ARMNeonUnOpS;
+
+typedef
+   enum {
+      ARMneon_TRN=100,
+      ARMneon_ZIP,
+      ARMneon_UZP
+      /* ... */
+   }
+   ARMNeonDualOp;
+
+extern HChar* showARMNeonBinOp ( ARMNeonBinOp op );
+extern HChar* showARMNeonUnOp ( ARMNeonUnOp op );
+extern HChar* showARMNeonUnOpS ( ARMNeonUnOpS op );
+extern HChar* showARMNeonShiftOp ( ARMNeonShiftOp op );
+extern HChar* showARMNeonDualOp ( ARMNeonDualOp op );
+extern HChar* showARMNeonBinOpDataType ( ARMNeonBinOp op );
+extern HChar* showARMNeonUnOpDataType ( ARMNeonUnOp op );
+extern HChar* showARMNeonUnOpSDataType ( ARMNeonUnOpS op );
+extern HChar* showARMNeonShiftOpDataType ( ARMNeonShiftOp op );
+extern HChar* showARMNeonDualOpDataType ( ARMNeonDualOp op );

 
 typedef
    enum {
 
 typedef
    enum {


@@ -355,7 +586,27 @@ typedef
       ARMin_VXferS,
       ARMin_VCvtID,
       ARMin_FPSCR,
       ARMin_VXferS,
       ARMin_VCvtID,
       ARMin_FPSCR,

-      ARMin_MFence
+      ARMin_MFence,
+      /* Neon */
+      ARMin_NLdStQ,
+      ARMin_NLdStD,
+      ARMin_NUnary,
+      ARMin_NUnaryS,
+      ARMin_NDual,
+      ARMin_NBinary,
+      ARMin_NBinaryS,
+      ARMin_NShift,
+      ARMin_NeonImm,
+      ARMin_NCMovQ,
+      /* This is not a NEON instruction. Actually there is no corresponding
+         instruction in ARM instruction set at all. We need this one to
+         generate spill/reload of 128-bit registers since current register
+         allocator demands them to consist of no more than two instructions.
+         We will split this instruction into 2 or 3 ARM instructions on the
+         emiting phase.
+
+         NOTE: source and destination registers should be different! */
+      ARMin_Add32

    }
    ARMInstrTag;
 
    }
    ARMInstrTag;
 


@@ -573,7 +824,81 @@ typedef
          */
          struct {
          } MFence;
          */
          struct {
          } MFence;

-
+         /* Neon data processing instruction: 3 registers of the same
+            length */
+         struct {
+            ARMNeonBinOp op;
+            HReg dst;
+            HReg argL;
+            HReg argR;
+            UInt size;
+            Bool Q;
+         } NBinary;
+         struct {
+            ARMNeonBinOp op;
+            ARMNRS* dst;
+            ARMNRS* argL;
+            ARMNRS* argR;
+            UInt size;
+            Bool Q;
+         } NBinaryS;
+         struct {
+            ARMNeonShiftOp op;
+            HReg dst;
+            HReg argL;
+            HReg argR;
+            UInt size;
+            Bool Q;
+         } NShift;
+         struct {
+            Bool isLoad;
+            HReg dQ;
+            ARMAModeN *amode;
+         } NLdStQ;
+         struct {
+            Bool isLoad;
+            HReg dD;
+            ARMAModeN *amode;
+         } NLdStD;
+         struct {
+            ARMNeonUnOp op;
+            ARMNRS*  dst;
+            ARMNRS*  src;
+            UInt size;
+            Bool Q;
+         } NUnaryS;
+         struct {
+            ARMNeonUnOp op;
+            HReg  dst;
+            HReg  src;
+            UInt size;
+            Bool Q;
+         } NUnary;
+         /* Takes two arguments and modifies them both. */
+         struct {
+            ARMNeonDualOp op;
+            HReg  arg1;
+            HReg  arg2;
+            UInt size;
+            Bool Q;
+         } NDual;
+         struct {
+            HReg dst;
+            ARMNImm* imm;
+         } NeonImm;
+         /* 128-bit Neon move src to dst on the given condition, which
+            may not be ARMcc_AL. */
+         struct {
+            ARMCondCode cond;
+            HReg        dst;
+            HReg        src;
+         } NCMovQ;
+         struct {
+            /* Note: rD != rN */
+            HReg rD;
+            HReg rN;
+            UInt imm32;
+         } Add32;

       } ARMin;
    }
    ARMInstr;
       } ARMin;
    }
    ARMInstr;


@@ -612,6 +937,19 @@ extern ARMInstr* ARMInstr_VCvtID   ( Bool iToD, Bool syned,
                                      HReg dst, HReg src );
 extern ARMInstr* ARMInstr_FPSCR    ( Bool toFPSCR, HReg iReg );
 extern ARMInstr* ARMInstr_MFence   ( void );
                                      HReg dst, HReg src );
 extern ARMInstr* ARMInstr_FPSCR    ( Bool toFPSCR, HReg iReg );
 extern ARMInstr* ARMInstr_MFence   ( void );

+extern ARMInstr* ARMInstr_NLdStQ   ( Bool isLoad, HReg, ARMAModeN* );
+extern ARMInstr* ARMInstr_NLdStD   ( Bool isLoad, HReg, ARMAModeN* );
+extern ARMInstr* ARMInstr_NUnary   ( ARMNeonUnOp, HReg, HReg, UInt, Bool );
+extern ARMInstr* ARMInstr_NUnaryS  ( ARMNeonUnOp, ARMNRS*, ARMNRS*,
+                                     UInt, Bool );
+extern ARMInstr* ARMInstr_NDual    ( ARMNeonDualOp, HReg, HReg, UInt, Bool );
+extern ARMInstr* ARMInstr_NBinary  ( ARMNeonBinOp, HReg, HReg, HReg,
+                                     UInt, Bool );
+extern ARMInstr* ARMInstr_NShift   ( ARMNeonShiftOp, HReg, HReg, HReg,
+                                     UInt, Bool );
+extern ARMInstr* ARMInstr_NeonImm  ( HReg, ARMNImm* );
+extern ARMInstr* ARMInstr_NCMovQ   ( ARMCondCode, HReg, HReg );
+extern ARMInstr* ARMInstr_Add32    ( HReg rD, HReg rN, UInt imm32 );

 
 extern void ppARMInstr ( ARMInstr* );
 
 
 extern void ppARMInstr ( ARMInstr* );
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_isel.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_isel.c
index ed41b8e91e64478e3e4ca6e546b38940ebbf0b69..28dfc684f9b532f429e8b56576e4e3ac12fb902d 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_isel.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_arm_isel.c
@@ -9,6 +9,8 @@
 
    Copyright (C) 2004-2010 OpenWorks LLP
       info@open-works.net
 
    Copyright (C) 2004-2010 OpenWorks LLP
       info@open-works.net

+   Copyright (C) 2010-2010 Dmitry Zhurikhin
+      zhur@ispras.ru

 
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as
 
    This program is free software; you can redistribute it and/or
    modify it under the terms of the GNU General Public License as


@@ -31,6 +33,7 @@
 #include "libvex_basictypes.h"
 #include "libvex_ir.h"
 #include "libvex.h"
 #include "libvex_basictypes.h"
 #include "libvex_ir.h"
 #include "libvex.h"

+#include "ir_match.h"

 
 #include "main_util.h"
 #include "main_globals.h"
 
 #include "main_util.h"
 #include "main_globals.h"


@@ -130,6 +133,14 @@ static void addInstr ( ISelEnv* env, ARMInstr* instr )
       ppARMInstr(instr);
       vex_printf("\n");
    }
       ppARMInstr(instr);
       vex_printf("\n");
    }

+#if 0
+   if (instr->tag == ARMin_NUnary || instr->tag == ARMin_NBinary
+         || instr->tag == ARMin_NUnaryS || instr->tag == ARMin_NBinaryS
+         || instr->tag == ARMin_NDual || instr->tag == ARMin_NShift) {
+      ppARMInstr(instr);
+      vex_printf("\n");
+   }
+#endif

 }
 
 static HReg newVRegI ( ISelEnv* env )
 }
 
 static HReg newVRegI ( ISelEnv* env )


@@ -153,6 +164,29 @@ static HReg newVRegF ( ISelEnv* env )
    return reg;
 }
 
    return reg;
 }
 

+static HReg newVRegV ( ISelEnv* env )
+{
+   HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/);
+   env->vreg_ctr++;
+   return reg;
+}
+
+/* These are duplicated in guest_arm_toIR.c */
+static IRExpr* unop ( IROp op, IRExpr* a )
+{
+   return IRExpr_Unop(op, a);
+}
+
+static IRExpr* binop ( IROp op, IRExpr* a1, IRExpr* a2 )
+{
+   return IRExpr_Binop(op, a1, a2);
+}
+
+static IRExpr* bind ( Int binder )
+{
+   return IRExpr_Binder(binder);
+}
+

 
 /*---------------------------------------------------------*/
 /*--- ISEL: Forward declarations                        ---*/
 
 /*---------------------------------------------------------*/
 /*--- ISEL: Forward declarations                        ---*/


@@ -173,6 +207,9 @@ static ARMAMode2*  iselIntExpr_AMode2     ( ISelEnv* env, IRExpr* e );
 static ARMAModeV*  iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e );
 static ARMAModeV*  iselIntExpr_AModeV     ( ISelEnv* env, IRExpr* e );
 
 static ARMAModeV*  iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e );
 static ARMAModeV*  iselIntExpr_AModeV     ( ISelEnv* env, IRExpr* e );
 

+static ARMAModeN* iselIntExpr_AModeN_wrk  ( ISelEnv* env, IRExpr* e );
+static ARMAModeN* iselIntExpr_AModeN      ( ISelEnv* env, IRExpr* e );
+

 static ARMRI84*    iselIntExpr_RI84_wrk
         ( /*OUT*/Bool* didInv, Bool mayInv, ISelEnv* env, IRExpr* e );
 static ARMRI84*    iselIntExpr_RI84
 static ARMRI84*    iselIntExpr_RI84_wrk
         ( /*OUT*/Bool* didInv, Bool mayInv, ISelEnv* env, IRExpr* e );
 static ARMRI84*    iselIntExpr_RI84


@@ -198,6 +235,11 @@ static HReg        iselDblExpr            ( ISelEnv* env, IRExpr* e );
 static HReg        iselFltExpr_wrk        ( ISelEnv* env, IRExpr* e );
 static HReg        iselFltExpr            ( ISelEnv* env, IRExpr* e );
 
 static HReg        iselFltExpr_wrk        ( ISelEnv* env, IRExpr* e );
 static HReg        iselFltExpr            ( ISelEnv* env, IRExpr* e );
 

+static HReg        iselNeon64Expr_wrk     ( ISelEnv* env, IRExpr* e );
+static HReg        iselNeon64Expr         ( ISelEnv* env, IRExpr* e );
+
+static HReg        iselNeonExpr_wrk       ( ISelEnv* env, IRExpr* e );
+static HReg        iselNeonExpr           ( ISelEnv* env, IRExpr* e );

 
 /*---------------------------------------------------------*/
 /*--- ISEL: Misc helpers                                ---*/
 
 /*---------------------------------------------------------*/
 /*--- ISEL: Misc helpers                                ---*/


@@ -767,6 +809,19 @@ static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e )
 
 }
 
 
 }
 

+/* -------------------- AModeN -------------------- */
+
+static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e )
+{
+   return iselIntExpr_AModeN_wrk(env, e);
+}
+
+static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e )
+{
+   HReg reg = iselIntExpr_R(env, e);
+   return mkARMAModeN_R(reg);
+}
+

 
 /* --------------------- RI84 --------------------- */
 
 
 /* --------------------- RI84 --------------------- */
 


@@ -892,7 +947,7 @@ static ARMRI5* iselIntExpr_RI5_wrk ( ISelEnv* env, IRExpr* e )
 static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e )
 {
    ARMCondCode cc = iselCondCode_wrk(env,e);
 static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e )
 {
    ARMCondCode cc = iselCondCode_wrk(env,e);

-   vassert(cc != ARMcc_AL && cc != ARMcc_NV);
+   vassert(cc != ARMcc_NV);

    return cc;
 }
 
    return cc;
 }
 


@@ -982,6 +1037,16 @@ static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
       }
    }
 
       }
    }
 

+   /* --- CasCmpEQ* --- */
+   /* Ist_Cas has a dummy argument to compare with, so comparison is
+      always true. */
+   if (e->tag == Iex_Binop
+       && (e->Iex.Binop.op == Iop_CasCmpEQ32
+           || e->Iex.Binop.op == Iop_CasCmpEQ16
+           || e->Iex.Binop.op == Iop_CasCmpEQ8)) {
+      return ARMcc_AL;
+   }
+

    ppIRExpr(e);
    vpanic("iselCondCode");
 }
    ppIRExpr(e);
    vpanic("iselCondCode");
 }


@@ -1006,6 +1071,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
 {
    IRType ty = typeOfIRExpr(env->type_env,e);
    vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);
 {
    IRType ty = typeOfIRExpr(env->type_env,e);
    vassert(ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);

+//   vassert(ty == Ity_I64 || ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8);

 
    switch (e->tag) {
 
 
    switch (e->tag) {
 


@@ -1144,7 +1210,8 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
          HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
          HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
          HReg dst  = newVRegI(env);
          HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
          HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
          HReg dst  = newVRegI(env);

-         addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL, ARMRI84_R(argR)));
+         addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL,
+                                         ARMRI84_R(argR)));

          addInstr(env, mk_iMOVds_RR(dst, argL));
          addInstr(env, ARMInstr_CMov(ARMcc_LO, dst, ARMRI84_R(argR)));
          return dst;
          addInstr(env, mk_iMOVds_RR(dst, argL));
          addInstr(env, ARMInstr_CMov(ARMcc_LO, dst, ARMRI84_R(argR)));
          return dst;


@@ -1187,6 +1254,56 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
          return dst;
       }
 
          return dst;
       }
 

+      if (e->Iex.Binop.op == Iop_GetElem8x8
+          || e->Iex.Binop.op == Iop_GetElem16x4
+          || e->Iex.Binop.op == Iop_GetElem32x2) {
+         HReg res = newVRegI(env);
+         HReg arg = iselNeon64Expr(env, e->Iex.Triop.arg1);
+         UInt index, size;
+         if (e->Iex.Binop.arg2->tag != Iex_Const ||
+             typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+            vpanic("ARM target supports GetElem with constant "
+                   "second argument only\n");
+         }
+         index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+         switch (e->Iex.Binop.op) {
+            case Iop_GetElem8x8: vassert(index < 8); size = 0; break;
+            case Iop_GetElem16x4: vassert(index < 4); size = 1; break;
+            case Iop_GetElem32x2: vassert(index < 2); size = 2; break;
+            default: vassert(0);
+         }
+         addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS,
+                                        mkARMNRS(ARMNRS_Reg, res, 0),
+                                        mkARMNRS(ARMNRS_Scalar, arg, index),
+                                        size, False));
+         return res;
+      }
+
+      if (e->Iex.Binop.op == Iop_GetElem8x16
+          || e->Iex.Binop.op == Iop_GetElem16x8
+          || e->Iex.Binop.op == Iop_GetElem32x4) {
+         HReg res = newVRegI(env);
+         HReg arg = iselNeonExpr(env, e->Iex.Triop.arg1);
+         UInt index, size;
+         if (e->Iex.Binop.arg2->tag != Iex_Const ||
+             typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+            vpanic("ARM target supports GetElem with constant "
+                   "second argument only\n");
+         }
+         index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+         switch (e->Iex.Binop.op) {
+            case Iop_GetElem8x16: vassert(index < 16); size = 0; break;
+            case Iop_GetElem16x8: vassert(index < 8); size = 1; break;
+            case Iop_GetElem32x4: vassert(index < 4); size = 2; break;
+            default: vassert(0);
+         }
+         addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS,
+                                        mkARMNRS(ARMNRS_Reg, res, 0),
+                                        mkARMNRS(ARMNRS_Scalar, arg, index),
+                                        size, True));
+         return res;
+      }
+

       break;
    }
 
       break;
    }
 


@@ -1335,6 +1452,20 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
             iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
             return rLo; /* similar stupid comment to the above ... */
          }
             iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
             return rLo; /* similar stupid comment to the above ... */
          }

+         case Iop_64to8: {
+            HReg rHi, rLo;
+            if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+               HReg tHi = newVRegI(env);
+               HReg tLo = newVRegI(env);
+               HReg tmp = iselNeon64Expr(env, e->Iex.Unop.arg);
+               addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
+               rHi = tHi;
+               rLo = tLo;
+            } else {
+               iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
+            }
+            return rLo;
+         }

 //zz         case Iop_16HIto8:
 //zz         case Iop_32HIto16: {
 //zz            HReg dst  = newVRegI(env);
 //zz         case Iop_16HIto8:
 //zz         case Iop_32HIto16: {
 //zz            HReg dst  = newVRegI(env);


@@ -1436,7 +1567,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
             /* These are no-ops. */
             return iselIntExpr_R(env, e->Iex.Unop.arg);
 
             /* These are no-ops. */
             return iselIntExpr_R(env, e->Iex.Unop.arg);
 

-         default: 
+         default:

             break;
       }
       break;
             break;
       }
       break;


@@ -1512,7 +1643,7 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
          case Ico_U32: u = e->Iex.Const.con->Ico.U32; break;
          case Ico_U16: u = 0xFFFF & (e->Iex.Const.con->Ico.U16); break;
          case Ico_U8:  u = 0xFF   & (e->Iex.Const.con->Ico.U8); break;
          case Ico_U32: u = e->Iex.Const.con->Ico.U32; break;
          case Ico_U16: u = 0xFFFF & (e->Iex.Const.con->Ico.U16); break;
          case Ico_U8:  u = 0xFF   & (e->Iex.Const.con->Ico.U8); break;

-         default: vpanic("iselIntExpr_R.Iex_Const(arm)");
+         default: ppIRExpr(e); vpanic("iselIntExpr_R.Iex_Const(arm)");

       }
       addInstr(env, ARMInstr_Imm32(dst, u));
       return dst;
       }
       addInstr(env, ARMInstr_Imm32(dst, u));
       return dst;


@@ -1607,7 +1738,16 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
 
    /* read 64-bit IRTemp */
    if (e->tag == Iex_RdTmp) {
 
    /* read 64-bit IRTemp */
    if (e->tag == Iex_RdTmp) {

-      lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp);
+      if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+         HReg tHi = newVRegI(env);
+         HReg tLo = newVRegI(env);
+         HReg tmp = iselNeon64Expr(env, e);
+         addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
+         *rHi = tHi;
+         *rLo = tLo;
+      } else {
+         lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp);
+      }

       return;
    }
 
       return;
    }
 


@@ -1725,9 +1865,11 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
             /* zero = 0 */
             addInstr(env, ARMInstr_Imm32(zero, 0));
             /* tLo = 0 - yLo, and set carry */
             /* zero = 0 */
             addInstr(env, ARMInstr_Imm32(zero, 0));
             /* tLo = 0 - yLo, and set carry */

-            addInstr(env, ARMInstr_Alu(ARMalu_SUBS, tLo, zero, ARMRI84_R(yLo)));
+            addInstr(env, ARMInstr_Alu(ARMalu_SUBS,
+                                       tLo, zero, ARMRI84_R(yLo)));

             /* tHi = 0 - yHi - carry */
             /* tHi = 0 - yHi - carry */

-            addInstr(env, ARMInstr_Alu(ARMalu_SBC,  tHi, zero, ARMRI84_R(yHi)));
+            addInstr(env, ARMInstr_Alu(ARMalu_SBC,
+                                       tHi, zero, ARMRI84_R(yHi)));

             /* So now we have tHi:tLo = -arg.  To finish off, or 'arg'
                back in, so as to give the final result 
                tHi:tLo = arg | -arg. */
             /* So now we have tHi:tLo = -arg.  To finish off, or 'arg'
                back in, so as to give the final result 
                tHi:tLo = arg | -arg. */


@@ -1802,243 +1944,3457 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
       return;
    }
 
       return;
    }
 

+   /* It is convenient sometimes to call iselInt64Expr even when we
+      have NEON support (e.g. in do_helper_call we need 64-bit
+      arguments as 2 x 32 regs). */
+   if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+      HReg tHi = newVRegI(env);
+      HReg tLo = newVRegI(env);
+      HReg tmp = iselNeon64Expr(env, e);
+      addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
+      *rHi = tHi;
+      *rLo = tLo;
+      return ;
+   }
+

    ppIRExpr(e);
    vpanic("iselInt64Expr");
 }
 
 
 /*---------------------------------------------------------*/
    ppIRExpr(e);
    vpanic("iselInt64Expr");
 }
 
 
 /*---------------------------------------------------------*/

-/*--- ISEL: Floating point expressions (64 bit)         ---*/
+/*--- ISEL: Vector (NEON) expressions (64 or 128 bit)   ---*/

 /*---------------------------------------------------------*/
 
 /*---------------------------------------------------------*/
 

-/* Compute a 64-bit floating point value into a register, the identity
-   of which is returned.  As with iselIntExpr_R, the reg may be either
-   real or virtual; in any case it must not be changed by subsequent
-   code emitted by the caller.  */
-
-static HReg iselDblExpr ( ISelEnv* env, IRExpr* e )
+static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e )

 {
 {

-   HReg r = iselDblExpr_wrk( env, e );
-#  if 0
-   vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
-#  endif
+   HReg r = iselNeon64Expr_wrk( env, e );

    vassert(hregClass(r) == HRcFlt64);
    vassert(hregIsVirtual(r));
    return r;
 }
 
 /* DO NOT CALL THIS DIRECTLY */
    vassert(hregClass(r) == HRcFlt64);
    vassert(hregIsVirtual(r));
    return r;
 }
 
 /* DO NOT CALL THIS DIRECTLY */

-static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
+static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e )

 {
 {

-   IRType ty = typeOfIRExpr(env->type_env,e);
+   IRType ty = typeOfIRExpr(env->type_env, e);
+   MatchInfo mi;

    vassert(e);
    vassert(e);

-   vassert(ty == Ity_F64);
+   vassert(ty == Ity_I64);

 
    if (e->tag == Iex_RdTmp) {
       return lookupIRTemp(env, e->Iex.RdTmp.tmp);
    }
 
    if (e->tag == Iex_Const) {
 
    if (e->tag == Iex_RdTmp) {
       return lookupIRTemp(env, e->Iex.RdTmp.tmp);
    }
 
    if (e->tag == Iex_Const) {

-      /* Just handle the zero case. */
-      IRConst* con = e->Iex.Const.con;
-      if (con->tag == Ico_F64i && con->Ico.F64i == 0ULL) {
-         HReg z32 = newVRegI(env);
-         HReg dst = newVRegD(env);
-         addInstr(env, ARMInstr_Imm32(z32, 0));
-         addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, z32, z32));
-         return dst;
-      }
+      HReg rLo, rHi;
+      HReg res = newVRegD(env);
+      iselInt64Expr(&rHi, &rLo, env, e);
+      addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
+      return res;

    }
 
    }
 

+   /* 64-bit load */

    if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
    if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {

-      ARMAModeV* am;

       HReg res = newVRegD(env);
       HReg res = newVRegD(env);

-      vassert(e->Iex.Load.ty == Ity_F64);
-      am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
-      addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am));
+      ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr);
+      vassert(ty == Ity_I64);
+      addInstr(env, ARMInstr_NLdStD(True, res, am));

       return res;
    }
 
       return res;
    }
 

+   /* 64-bit GET */

    if (e->tag == Iex_Get) {
    if (e->tag == Iex_Get) {

-      // XXX This won't work if offset > 1020 or is not 0 % 4.
-      // In which case we'll have to generate more longwinded code.
-      ARMAModeV* am  = mkARMAModeV(hregARM_R8(), e->Iex.Get.offset);
-      HReg       res = newVRegD(env);
-      addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am));
+      HReg addr = newVRegI(env);
+      HReg res = newVRegD(env);
+      vassert(ty == Ity_I64);
+      addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset));
+      addInstr(env, ARMInstr_NLdStD(True, res, mkARMAModeN_R(addr)));

       return res;
    }
 
       return res;
    }
 

-   if (e->tag == Iex_Unop) {
-      switch (e->Iex.Unop.op) {
-         case Iop_ReinterpI64asF64: {
-            HReg srcHi, srcLo;
-            HReg dst = newVRegD(env);
-            iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
-            addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, srcHi, srcLo));
-            return dst;
-         }
-         case Iop_NegF64: {
-            HReg src = iselDblExpr(env, e->Iex.Unop.arg);
-            HReg dst = newVRegD(env);
-            addInstr(env, ARMInstr_VUnaryD(ARMvfpu_NEG, dst, src));
-            return dst;
+   /* --------- BINARY ops --------- */
+   if (e->tag == Iex_Binop) {
+      switch (e->Iex.Binop.op) {
+
+         /* 32 x 32 -> 64 multiply */
+         case Iop_MullS32:
+         case Iop_MullU32: {
+            HReg rLo, rHi;
+            HReg res = newVRegD(env);
+            iselInt64Expr(&rHi, &rLo, env, e);
+            addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
+            return res;

          }
          }

-         case Iop_AbsF64: {
-            HReg src = iselDblExpr(env, e->Iex.Unop.arg);
-            HReg dst = newVRegD(env);
-            addInstr(env, ARMInstr_VUnaryD(ARMvfpu_ABS, dst, src));
-            return dst;
+
+         case Iop_And64: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
+                                           res, argL, argR, 4, False));
+            return res;

          }
          }

-         case Iop_F32toF64: {
-            HReg src = iselFltExpr(env, e->Iex.Unop.arg);
-            HReg dst = newVRegD(env);
-            addInstr(env, ARMInstr_VCvtSD(True/*sToD*/, dst, src));
-            return dst;
+         case Iop_Or64: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
+                                           res, argL, argR, 4, False));
+            return res;

          }
          }

-         case Iop_I32UtoF64:
-         case Iop_I32StoF64: {
-            HReg src   = iselIntExpr_R(env, e->Iex.Unop.arg);
-            HReg f32   = newVRegF(env);
-            HReg dst   = newVRegD(env);
-            Bool syned = e->Iex.Unop.op == Iop_I32StoF64;
-            /* VMOV f32, src */
-            addInstr(env, ARMInstr_VXferS(True/*toS*/, f32, src));
-            /* FSITOD dst, f32 */
-            addInstr(env, ARMInstr_VCvtID(True/*iToD*/, syned,
-                                          dst, f32));
-            return dst;
+         case Iop_Xor64: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VXOR,
+                                           res, argL, argR, 4, False));
+            return res;

          }
          }

-         default:
-            break;
-      }
-   }

 
 

-   if (e->tag == Iex_Binop) {
-      switch (e->Iex.Binop.op) {
-         case Iop_SqrtF64: {
-            /* first arg is rounding mode; we ignore it. */
-            HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
-            HReg dst = newVRegD(env);
-            addInstr(env, ARMInstr_VUnaryD(ARMvfpu_SQRT, dst, src));
-            return dst;
+         /* 32HLto64(e1,e2) */
+         case Iop_32HLto64: {
+            HReg rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
+            HReg rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
+            HReg res = newVRegD(env);
+            addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
+            return res;

          }
          }

-         default:
-            break;
-      }
-   }

 
 

-   if (e->tag == Iex_Triop) {
-      switch (e->Iex.Triop.op) {
-         case Iop_DivF64:
-         case Iop_MulF64:
-         case Iop_AddF64:
-         case Iop_SubF64: {
-            ARMVfpOp op = 0; /*INVALID*/
-            HReg argL = iselDblExpr(env, e->Iex.Triop.arg2);
-            HReg argR = iselDblExpr(env, e->Iex.Triop.arg3);
-            HReg dst  = newVRegD(env);
-            switch (e->Iex.Triop.op) {
-               case Iop_DivF64: op = ARMvfp_DIV; break;
-               case Iop_MulF64: op = ARMvfp_MUL; break;
-               case Iop_AddF64: op = ARMvfp_ADD; break;
-               case Iop_SubF64: op = ARMvfp_SUB; break;
+         case Iop_Add8x8:
+         case Iop_Add16x4:
+         case Iop_Add32x2:
+         case Iop_Add64: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Add8x8: size = 0; break;
+               case Iop_Add16x4: size = 1; break;
+               case Iop_Add32x2: size = 2; break;
+               case Iop_Add64: size = 3; break;

                default: vassert(0);
             }
                default: vassert(0);
             }

-            addInstr(env, ARMInstr_VAluD(op, dst, argL, argR));
-            return dst;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VADD,
+                                           res, argL, argR, size, False));
+            return res;

          }
          }

-         default:
-            break;
-      }
-   }
-
-   if (e->tag == Iex_Mux0X) {
-      if (ty == Ity_F64
-          && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) {
-         HReg r8;
-         HReg rX  = iselDblExpr(env, e->Iex.Mux0X.exprX);
-         HReg r0  = iselDblExpr(env, e->Iex.Mux0X.expr0);
-         HReg dst = newVRegD(env);
-         addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, rX));
-         r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
-         addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8,
-                                         ARMRI84_I84(0xFF,0)));
-         addInstr(env, ARMInstr_VCMovD(ARMcc_EQ, dst, r0));
-         return dst;
-      }
-   }
-
-   ppIRExpr(e);
-   vpanic("iselDblExpr_wrk");
-}
-
-
-/*---------------------------------------------------------*/
-/*--- ISEL: Floating point expressions (32 bit)         ---*/
-/*---------------------------------------------------------*/
-
-/* Compute a 64-bit floating point value into a register, the identity
-   of which is returned.  As with iselIntExpr_R, the reg may be either
-   real or virtual; in any case it must not be changed by subsequent
-   code emitted by the caller.  */
-
-static HReg iselFltExpr ( ISelEnv* env, IRExpr* e )
-{
-   HReg r = iselFltExpr_wrk( env, e );
-#  if 0
-   vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
-#  endif
-   vassert(hregClass(r) == HRcFlt32);
-   vassert(hregIsVirtual(r));
-   return r;
-}
-
-/* DO NOT CALL THIS DIRECTLY */
-static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
-{
-   IRType ty = typeOfIRExpr(env->type_env,e);
-   vassert(e);
-   vassert(ty == Ity_F32);
-
-   if (e->tag == Iex_RdTmp) {
-      return lookupIRTemp(env, e->Iex.RdTmp.tmp);
-   }
-
-   if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
-      ARMAModeV* am;
-      HReg res = newVRegF(env);
-      vassert(e->Iex.Load.ty == Ity_F32);
-      am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
-      addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
-      return res;
-   }
-
-   if (e->tag == Iex_Get) {
-      // XXX This won't work if offset > 1020 or is not 0 % 4.
-      // In which case we'll have to generate more longwinded code.
-      ARMAModeV* am  = mkARMAModeV(hregARM_R8(), e->Iex.Get.offset);
-      HReg       res = newVRegF(env);
-      addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
-      return res;
-   }
-
-   if (e->tag == Iex_Unop) {
-      switch (e->Iex.Unop.op) {
-         case Iop_ReinterpI32asF32: {
-            HReg dst = newVRegF(env);
-            HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-            addInstr(env, ARMInstr_VXferS(True/*toS*/, dst, src));
-            return dst;
+         case Iop_Add32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP,
+                                           res, argL, argR, size, False));
+            return res;

          }
          }

-         case Iop_NegF32: {
-            HReg src = iselFltExpr(env, e->Iex.Unop.arg);
-            HReg dst = newVRegF(env);
-            addInstr(env, ARMInstr_VUnaryS(ARMvfpu_NEG, dst, src));
-            return dst;
+         case Iop_Recps32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS,
+                                           res, argL, argR, size, False));
+            return res;

          }
          }

-         case Iop_AbsF32: {
-            HReg src = iselFltExpr(env, e->Iex.Unop.arg);
-            HReg dst = newVRegF(env);
+         case Iop_Rsqrts32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_InterleaveOddLanes8x8:
+         case Iop_InterleaveOddLanes16x4:
+         case Iop_InterleaveLO32x2:
+         case Iop_InterleaveEvenLanes8x8:
+         case Iop_InterleaveEvenLanes16x4:
+         case Iop_InterleaveHI32x2: {
+            HReg tmp = newVRegD(env);
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            UInt is_lo;
+            switch (e->Iex.Binop.op) {
+               case Iop_InterleaveOddLanes8x8: is_lo = 1; size = 0; break;
+               case Iop_InterleaveEvenLanes8x8: is_lo = 0; size = 0; break;
+               case Iop_InterleaveOddLanes16x4: is_lo = 1; size = 1; break;
+               case Iop_InterleaveEvenLanes16x4: is_lo = 0; size = 1; break;
+               case Iop_InterleaveLO32x2: is_lo = 1; size = 2; break;
+               case Iop_InterleaveHI32x2: is_lo = 0; size = 2; break;
+               default: vassert(0);
+            }
+            if (is_lo) {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argL, 4, False));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argR, 4, False));
+               addInstr(env, ARMInstr_NDual(ARMneon_TRN,
+                                            res, tmp, size, False));
+            } else {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argR, 4, False));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argL, 4, False));
+               addInstr(env, ARMInstr_NDual(ARMneon_TRN,
+                                            tmp, res, size, False));
+            }
+            return res;
+         }
+         case Iop_InterleaveHI8x8:
+         case Iop_InterleaveHI16x4:
+         case Iop_InterleaveLO8x8:
+         case Iop_InterleaveLO16x4: {
+            HReg tmp = newVRegD(env);
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            UInt is_lo;
+            switch (e->Iex.Binop.op) {
+               case Iop_InterleaveHI8x8: is_lo = 1; size = 0; break;
+               case Iop_InterleaveLO8x8: is_lo = 0; size = 0; break;
+               case Iop_InterleaveHI16x4: is_lo = 1; size = 1; break;
+               case Iop_InterleaveLO16x4: is_lo = 0; size = 1; break;
+               default: vassert(0);
+            }
+            if (is_lo) {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argL, 4, False));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argR, 4, False));
+               addInstr(env, ARMInstr_NDual(ARMneon_ZIP,
+                                            res, tmp, size, False));
+            } else {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argR, 4, False));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argL, 4, False));
+               addInstr(env, ARMInstr_NDual(ARMneon_ZIP,
+                                            tmp, res, size, False));
+            }
+            return res;
+         }
+         case Iop_CatOddLanes8x8:
+         case Iop_CatOddLanes16x4:
+         case Iop_CatEvenLanes8x8:
+         case Iop_CatEvenLanes16x4: {
+            HReg tmp = newVRegD(env);
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            UInt is_lo;
+            switch (e->Iex.Binop.op) {
+               case Iop_CatOddLanes8x8: is_lo = 1; size = 0; break;
+               case Iop_CatEvenLanes8x8: is_lo = 0; size = 0; break;
+               case Iop_CatOddLanes16x4: is_lo = 1; size = 1; break;
+               case Iop_CatEvenLanes16x4: is_lo = 0; size = 1; break;
+               default: vassert(0);
+            }
+            if (is_lo) {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argL, 4, False));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argR, 4, False));
+               addInstr(env, ARMInstr_NDual(ARMneon_UZP,
+                                            res, tmp, size, False));
+            } else {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argR, 4, False));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argL, 4, False));
+               addInstr(env, ARMInstr_NDual(ARMneon_UZP,
+                                            tmp, res, size, False));
+            }
+            return res;
+         }
+         case Iop_QAdd8Ux8:
+         case Iop_QAdd16Ux4:
+         case Iop_QAdd32Ux2:
+         case Iop_QAdd64Ux1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QAdd8Ux8: size = 0; break;
+               case Iop_QAdd16Ux4: size = 1; break;
+               case Iop_QAdd32Ux2: size = 2; break;
+               case Iop_QAdd64Ux1: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_QAdd8Sx8:
+         case Iop_QAdd16Sx4:
+         case Iop_QAdd32Sx2:
+         case Iop_QAdd64Sx1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QAdd8Sx8: size = 0; break;
+               case Iop_QAdd16Sx4: size = 1; break;
+               case Iop_QAdd32Sx2: size = 2; break;
+               case Iop_QAdd64Sx1: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Sub8x8:
+         case Iop_Sub16x4:
+         case Iop_Sub32x2:
+         case Iop_Sub64: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Sub8x8: size = 0; break;
+               case Iop_Sub16x4: size = 1; break;
+               case Iop_Sub32x2: size = 2; break;
+               case Iop_Sub64: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Sub32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_QSub8Ux8:
+         case Iop_QSub16Ux4:
+         case Iop_QSub32Ux2:
+         case Iop_QSub64Ux1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QSub8Ux8: size = 0; break;
+               case Iop_QSub16Ux4: size = 1; break;
+               case Iop_QSub32Ux2: size = 2; break;
+               case Iop_QSub64Ux1: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_QSub8Sx8:
+         case Iop_QSub16Sx4:
+         case Iop_QSub32Sx2:
+         case Iop_QSub64Sx1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QSub8Sx8: size = 0; break;
+               case Iop_QSub16Sx4: size = 1; break;
+               case Iop_QSub32Sx2: size = 2; break;
+               case Iop_QSub64Sx1: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Max8Ux8:
+         case Iop_Max16Ux4:
+         case Iop_Max32Ux2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Max8Ux8: size = 0; break;
+               case Iop_Max16Ux4: size = 1; break;
+               case Iop_Max32Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Max8Sx8:
+         case Iop_Max16Sx4:
+         case Iop_Max32Sx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Max8Sx8: size = 0; break;
+               case Iop_Max16Sx4: size = 1; break;
+               case Iop_Max32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Min8Ux8:
+         case Iop_Min16Ux4:
+         case Iop_Min32Ux2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Min8Ux8: size = 0; break;
+               case Iop_Min16Ux4: size = 1; break;
+               case Iop_Min32Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMINU,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Min8Sx8:
+         case Iop_Min16Sx4:
+         case Iop_Min32Sx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Min8Sx8: size = 0; break;
+               case Iop_Min16Sx4: size = 1; break;
+               case Iop_Min32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMINS,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Sar8x8:
+         case Iop_Sar16x4:
+         case Iop_Sar32x2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            HReg argR2 = newVRegD(env);
+            HReg zero = newVRegD(env);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Sar8x8: size = 0; break;
+               case Iop_Sar16x4: size = 1; break;
+               case Iop_Sar32x2: size = 2; break;
+               case Iop_Sar64: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
+                                           argR2, zero, argR, size, False));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
+                                          res, argL, argR2, size, False));
+            return res;
+         }
+         case Iop_Sal8x8:
+         case Iop_Sal16x4:
+         case Iop_Sal32x2:
+         case Iop_Sal64x1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Sal8x8: size = 0; break;
+               case Iop_Sal16x4: size = 1; break;
+               case Iop_Sal32x2: size = 2; break;
+               case Iop_Sal64x1: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
+                                          res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Shr8x8:
+         case Iop_Shr16x4:
+         case Iop_Shr32x2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            HReg argR2 = newVRegD(env);
+            HReg zero = newVRegD(env);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Shr8x8: size = 0; break;
+               case Iop_Shr16x4: size = 1; break;
+               case Iop_Shr32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
+                                           argR2, zero, argR, size, False));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          res, argL, argR2, size, False));
+            return res;
+         }
+         case Iop_Shl8x8:
+         case Iop_Shl16x4:
+         case Iop_Shl32x2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Shl8x8: size = 0; break;
+               case Iop_Shl16x4: size = 1; break;
+               case Iop_Shl32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_QShl8x8:
+         case Iop_QShl16x4:
+         case Iop_QShl32x2:
+         case Iop_QShl64x1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QShl8x8: size = 0; break;
+               case Iop_QShl16x4: size = 1; break;
+               case Iop_QShl32x2: size = 2; break;
+               case Iop_QShl64x1: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NShift(ARMneon_VQSHL,
+                                          res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_QSal8x8:
+         case Iop_QSal16x4:
+         case Iop_QSal32x2:
+         case Iop_QSal64x1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QSal8x8: size = 0; break;
+               case Iop_QSal16x4: size = 1; break;
+               case Iop_QSal32x2: size = 2; break;
+               case Iop_QSal64x1: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NShift(ARMneon_VQSAL,
+                                          res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_QShlN8x8:
+         case Iop_QShlN16x4:
+         case Iop_QShlN32x2:
+         case Iop_QShlN64x1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            UInt size, imm;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+               vpanic("ARM taget supports Iop_QShlNAxB with constant "
+                      "second argument only\n");
+            }
+            imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            switch (e->Iex.Binop.op) {
+               case Iop_QShlN8x8: size = 8 | imm; break;
+               case Iop_QShlN16x4: size = 16 | imm; break;
+               case Iop_QShlN32x2: size = 32 | imm; break;
+               case Iop_QShlN64x1: size = 64 | imm; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU,
+                                          res, argL, size, False));
+            return res;
+         }
+         case Iop_QShlN8Sx8:
+         case Iop_QShlN16Sx4:
+         case Iop_QShlN32Sx2:
+         case Iop_QShlN64Sx1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            UInt size, imm;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+               vpanic("ARM taget supports Iop_QShlNAxB with constant "
+                      "second argument only\n");
+            }
+            imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            switch (e->Iex.Binop.op) {
+               case Iop_QShlN8Sx8: size = 8 | imm; break;
+               case Iop_QShlN16Sx4: size = 16 | imm; break;
+               case Iop_QShlN32Sx2: size = 32 | imm; break;
+               case Iop_QShlN64Sx1: size = 64 | imm; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS,
+                                          res, argL, size, False));
+            return res;
+         }
+         case Iop_QSalN8x8:
+         case Iop_QSalN16x4:
+         case Iop_QSalN32x2:
+         case Iop_QSalN64x1: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            UInt size, imm;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+               vpanic("ARM taget supports Iop_QShlNAxB with constant "
+                      "second argument only\n");
+            }
+            imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            switch (e->Iex.Binop.op) {
+               case Iop_QSalN8x8: size = 8 | imm; break;
+               case Iop_QSalN16x4: size = 16 | imm; break;
+               case Iop_QSalN32x2: size = 32 | imm; break;
+               case Iop_QSalN64x1: size = 64 | imm; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS,
+                                          res, argL, size, False));
+            return res;
+         }
+         case Iop_ShrN8x8:
+         case Iop_ShrN16x4:
+         case Iop_ShrN32x2:
+         case Iop_Shr64: {
+            HReg res = newVRegD(env);
+            HReg tmp = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
+            HReg argR2 = newVRegI(env);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_ShrN8x8: size = 0; break;
+               case Iop_ShrN16x4: size = 1; break;
+               case Iop_ShrN32x2: size = 2; break;
+               case Iop_Shr64: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
+            addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          res, argL, tmp, size, False));
+            return res;
+         }
+         case Iop_ShlN8x8:
+         case Iop_ShlN16x4:
+         case Iop_ShlN32x2:
+         case Iop_Shl64: {
+            HReg res = newVRegD(env);
+            HReg tmp = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_ShlN8x8: size = 0; break;
+               case Iop_ShlN16x4: size = 1; break;
+               case Iop_ShlN32x2: size = 2; break;
+               case Iop_Shl64: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR, 0, False));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          res, argL, tmp, size, False));
+            return res;
+         }
+         case Iop_SarN8x8:
+         case Iop_SarN16x4:
+         case Iop_SarN32x2:
+         case Iop_Sar64: {
+            HReg res = newVRegD(env);
+            HReg tmp = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
+            HReg argR2 = newVRegI(env);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_SarN8x8: size = 0; break;
+               case Iop_SarN16x4: size = 1; break;
+               case Iop_SarN32x2: size = 2; break;
+               case Iop_Sar64: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
+            addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
+                                          res, argL, tmp, size, False));
+            return res;
+         }
+         case Iop_CmpGT8Ux8:
+         case Iop_CmpGT16Ux4:
+         case Iop_CmpGT32Ux2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_CmpGT8Ux8: size = 0; break;
+               case Iop_CmpGT16Ux4: size = 1; break;
+               case Iop_CmpGT32Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_CmpGT8Sx8:
+         case Iop_CmpGT16Sx4:
+         case Iop_CmpGT32Sx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_CmpGT8Sx8: size = 0; break;
+               case Iop_CmpGT16Sx4: size = 1; break;
+               case Iop_CmpGT32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_CmpEQ8x8:
+         case Iop_CmpEQ16x4:
+         case Iop_CmpEQ32x2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_CmpEQ8x8: size = 0; break;
+               case Iop_CmpEQ16x4: size = 1; break;
+               case Iop_CmpEQ32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Mul8x8:
+         case Iop_Mul16x4:
+         case Iop_Mul32x2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Mul8x8: size = 0; break;
+               case Iop_Mul16x4: size = 1; break;
+               case Iop_Mul32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMUL,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Mul32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_QDMulHi16Sx4:
+         case Iop_QDMulHi32Sx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_QDMulHi16Sx4: size = 1; break;
+               case Iop_QDMulHi32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+
+         case Iop_QRDMulHi16Sx4:
+         case Iop_QRDMulHi32Sx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_QRDMulHi16Sx4: size = 1; break;
+               case Iop_QRDMulHi32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+
+         case Iop_PwAdd8x8:
+         case Iop_PwAdd16x4:
+         case Iop_PwAdd32x2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwAdd8x8: size = 0; break;
+               case Iop_PwAdd16x4: size = 1; break;
+               case Iop_PwAdd32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPADD,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_PwAdd32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPADDFP,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_PwMin8Ux8:
+         case Iop_PwMin16Ux4:
+         case Iop_PwMin32Ux2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwMin8Ux8: size = 0; break;
+               case Iop_PwMin16Ux4: size = 1; break;
+               case Iop_PwMin32Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPMINU,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_PwMin8Sx8:
+         case Iop_PwMin16Sx4:
+         case Iop_PwMin32Sx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwMin8Sx8: size = 0; break;
+               case Iop_PwMin16Sx4: size = 1; break;
+               case Iop_PwMin32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPMINS,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_PwMax8Ux8:
+         case Iop_PwMax16Ux4:
+         case Iop_PwMax32Ux2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwMax8Ux8: size = 0; break;
+               case Iop_PwMax16Ux4: size = 1; break;
+               case Iop_PwMax32Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXU,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_PwMax8Sx8:
+         case Iop_PwMax16Sx4:
+         case Iop_PwMax32Sx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwMax8Sx8: size = 0; break;
+               case Iop_PwMax16Sx4: size = 1; break;
+               case Iop_PwMax32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXS,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Perm8x8: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VTBL,
+                                           res, argL, argR, 0, False));
+            return res;
+         }
+         case Iop_PolynomialMul8x8: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMULP,
+                                           res, argL, argR, size, False));
+            return res;
+         }
+         case Iop_Max32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF,
+                                           res, argL, argR, 2, False));
+            return res;
+         }
+         case Iop_Min32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMINF,
+                                           res, argL, argR, 2, False));
+            return res;
+         }
+         case Iop_PwMax32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF,
+                                           res, argL, argR, 2, False));
+            return res;
+         }
+         case Iop_PwMin32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF,
+                                           res, argL, argR, 2, False));
+            return res;
+         }
+         case Iop_CmpGT32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF,
+                                           res, argL, argR, 2, False));
+            return res;
+         }
+         case Iop_CmpGE32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF,
+                                           res, argL, argR, 2, False));
+            return res;
+         }
+         case Iop_CmpEQ32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF,
+                                           res, argL, argR, 2, False));
+            return res;
+         }
+         case Iop_F32ToFixed32Ux2_RZ:
+         case Iop_F32ToFixed32Sx2_RZ:
+         case Iop_Fixed32UToF32x2_RN:
+         case Iop_Fixed32SToF32x2_RN: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            ARMNeonUnOp op;
+            UInt imm6;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+               typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+                  vpanic("ARM supports FP <-> Fixed conversion with constant "
+                         "second argument less than 33 only\n");
+            }
+            imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            vassert(imm6 <= 32 && imm6 > 0);
+            imm6 = 64 - imm6;
+            switch(e->Iex.Binop.op) {
+               case Iop_F32ToFixed32Ux2_RZ: op = ARMneon_VCVTFtoFixedU; break;
+               case Iop_F32ToFixed32Sx2_RZ: op = ARMneon_VCVTFtoFixedS; break;
+               case Iop_Fixed32UToF32x2_RN: op = ARMneon_VCVTFixedUtoF; break;
+               case Iop_Fixed32SToF32x2_RN: op = ARMneon_VCVTFixedStoF; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False));
+            return res;
+         }
+         /*
+         FIXME: is this here or not?
+         case Iop_VDup8x8:
+         case Iop_VDup16x4:
+         case Iop_VDup32x2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            UInt index;
+            UInt imm4;
+            UInt size = 0;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+               typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+                  vpanic("ARM supports Iop_VDup with constant "
+                         "second argument less than 16 only\n");
+            }
+            index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            switch(e->Iex.Binop.op) {
+               case Iop_VDup8x8: imm4 = (index << 1) + 1; break;
+               case Iop_VDup16x4: imm4 = (index << 2) + 2; break;
+               case Iop_VDup32x2: imm4 = (index << 3) + 4; break;
+               default: vassert(0);
+            }
+            if (imm4 >= 16) {
+               vpanic("ARM supports Iop_VDup with constant "
+                      "second argument less than 16 only\n");
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_VDUP,
+                                          res, argL, imm4, False));
+            return res;
+         }
+         */
+         default:
+            break;
+      }
+   }
+
+   /* --------- UNARY ops --------- */
+   if (e->tag == Iex_Unop) {
+      switch (e->Iex.Unop.op) {
+
+         /* ReinterpF64asI64 */
+         case Iop_ReinterpF64asI64:
+         /* Left64(e) */
+         case Iop_Left64:
+         /* CmpwNEZ64(e) */
+         //case Iop_CmpwNEZ64:
+         case Iop_1Sto64: {
+            HReg rLo, rHi;
+            HReg res = newVRegD(env);
+            iselInt64Expr(&rHi, &rLo, env, e);
+            addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
+            return res;
+         }
+         case Iop_Not64: {
+            DECLARE_PATTERN(p_veqz_8x8);
+            DECLARE_PATTERN(p_veqz_16x4);
+            DECLARE_PATTERN(p_veqz_32x2);
+            DECLARE_PATTERN(p_vcge_8sx8);
+            DECLARE_PATTERN(p_vcge_16sx4);
+            DECLARE_PATTERN(p_vcge_32sx2);
+            DECLARE_PATTERN(p_vcge_8ux8);
+            DECLARE_PATTERN(p_vcge_16ux4);
+            DECLARE_PATTERN(p_vcge_32ux2);
+            DEFINE_PATTERN(p_veqz_8x8,
+                  unop(Iop_Not64, unop(Iop_CmpNEZ8x8, bind(0))));
+            DEFINE_PATTERN(p_veqz_16x4,
+                  unop(Iop_Not64, unop(Iop_CmpNEZ16x4, bind(0))));
+            DEFINE_PATTERN(p_veqz_32x2,
+                  unop(Iop_Not64, unop(Iop_CmpNEZ32x2, bind(0))));
+            DEFINE_PATTERN(p_vcge_8sx8,
+                  unop(Iop_Not64, binop(Iop_CmpGT8Sx8, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_16sx4,
+                  unop(Iop_Not64, binop(Iop_CmpGT16Sx4, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_32sx2,
+                  unop(Iop_Not64, binop(Iop_CmpGT32Sx2, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_8ux8,
+                  unop(Iop_Not64, binop(Iop_CmpGT8Ux8, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_16ux4,
+                  unop(Iop_Not64, binop(Iop_CmpGT16Ux4, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_32ux2,
+                  unop(Iop_Not64, binop(Iop_CmpGT32Ux2, bind(1), bind(0))));
+            if (matchIRExpr(&mi, p_veqz_8x8, e)) {
+               HReg res = newVRegD(env);
+               HReg arg = iselNeon64Expr(env, mi.bindee[0]);
+               addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, False));
+               return res;
+            } else if (matchIRExpr(&mi, p_veqz_16x4, e)) {
+               HReg res = newVRegD(env);
+               HReg arg = iselNeon64Expr(env, mi.bindee[0]);
+               addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, False));
+               return res;
+            } else if (matchIRExpr(&mi, p_veqz_32x2, e)) {
+               HReg res = newVRegD(env);
+               HReg arg = iselNeon64Expr(env, mi.bindee[0]);
+               addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, False));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_8sx8, e)) {
+               HReg res = newVRegD(env);
+               HReg argL = iselNeon64Expr(env, mi.bindee[0]);
+               HReg argR = iselNeon64Expr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
+                                              res, argL, argR, 0, False));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_16sx4, e)) {
+               HReg res = newVRegD(env);
+               HReg argL = iselNeon64Expr(env, mi.bindee[0]);
+               HReg argR = iselNeon64Expr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
+                                              res, argL, argR, 1, False));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_32sx2, e)) {
+               HReg res = newVRegD(env);
+               HReg argL = iselNeon64Expr(env, mi.bindee[0]);
+               HReg argR = iselNeon64Expr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
+                                              res, argL, argR, 2, False));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_8ux8, e)) {
+               HReg res = newVRegD(env);
+               HReg argL = iselNeon64Expr(env, mi.bindee[0]);
+               HReg argR = iselNeon64Expr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
+                                              res, argL, argR, 0, False));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_16ux4, e)) {
+               HReg res = newVRegD(env);
+               HReg argL = iselNeon64Expr(env, mi.bindee[0]);
+               HReg argR = iselNeon64Expr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
+                                              res, argL, argR, 1, False));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_32ux2, e)) {
+               HReg res = newVRegD(env);
+               HReg argL = iselNeon64Expr(env, mi.bindee[0]);
+               HReg argR = iselNeon64Expr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
+                                              res, argL, argR, 2, False));
+               return res;
+            } else {
+               HReg res = newVRegD(env);
+               HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+               addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, False));
+               return res;
+            }
+         }
+         case Iop_Dup8x8:
+         case Iop_Dup16x4:
+         case Iop_Dup32x2: {
+            HReg res, arg;
+            UInt size;
+            DECLARE_PATTERN(p_vdup_8x8);
+            DECLARE_PATTERN(p_vdup_16x4);
+            DECLARE_PATTERN(p_vdup_32x2);
+            DEFINE_PATTERN(p_vdup_8x8,
+                  unop(Iop_Dup8x8, binop(Iop_GetElem8x8, bind(0), bind(1))));
+            DEFINE_PATTERN(p_vdup_16x4,
+                  unop(Iop_Dup16x4, binop(Iop_GetElem16x4, bind(0), bind(1))));
+            DEFINE_PATTERN(p_vdup_32x2,
+                  unop(Iop_Dup32x2, binop(Iop_GetElem32x2, bind(0), bind(1))));
+            if (matchIRExpr(&mi, p_vdup_8x8, e)) {
+               UInt index;
+               UInt imm4;
+               if (mi.bindee[1]->tag == Iex_Const &&
+                  typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
+                  index = mi.bindee[1]->Iex.Const.con->Ico.U8;
+                  imm4 = (index << 1) + 1;
+                  if (index < 8) {
+                     res = newVRegD(env);
+                     arg = iselNeon64Expr(env, mi.bindee[0]);
+                     addInstr(env, ARMInstr_NUnaryS(
+                                      ARMneon_VDUP,
+                                      mkARMNRS(ARMNRS_Reg, res, 0),
+                                      mkARMNRS(ARMNRS_Scalar, arg, index),
+                                      imm4, False
+                             ));
+                     return res;
+                  }
+               }
+            } else if (matchIRExpr(&mi, p_vdup_16x4, e)) {
+               UInt index;
+               UInt imm4;
+               if (mi.bindee[1]->tag == Iex_Const &&
+                  typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
+                  index = mi.bindee[1]->Iex.Const.con->Ico.U8;
+                  imm4 = (index << 2) + 2;
+                  if (index < 4) {
+                     res = newVRegD(env);
+                     arg = iselNeon64Expr(env, mi.bindee[0]);
+                     addInstr(env, ARMInstr_NUnaryS(
+                                      ARMneon_VDUP,
+                                      mkARMNRS(ARMNRS_Reg, res, 0),
+                                      mkARMNRS(ARMNRS_Scalar, arg, index),
+                                      imm4, False
+                             ));
+                     return res;
+                  }
+               }
+            } else if (matchIRExpr(&mi, p_vdup_32x2, e)) {
+               UInt index;
+               UInt imm4;
+               if (mi.bindee[1]->tag == Iex_Const &&
+                  typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
+                  index = mi.bindee[1]->Iex.Const.con->Ico.U8;
+                  imm4 = (index << 3) + 4;
+                  if (index < 2) {
+                     res = newVRegD(env);
+                     arg = iselNeon64Expr(env, mi.bindee[0]);
+                     addInstr(env, ARMInstr_NUnaryS(
+                                      ARMneon_VDUP,
+                                      mkARMNRS(ARMNRS_Reg, res, 0),
+                                      mkARMNRS(ARMNRS_Scalar, arg, index),
+                                      imm4, False
+                             ));
+                     return res;
+                  }
+               }
+            }
+            arg = iselIntExpr_R(env, e->Iex.Unop.arg);
+            res = newVRegD(env);
+            switch (e->Iex.Unop.op) {
+               case Iop_Dup8x8: size = 0; break;
+               case Iop_Dup16x4: size = 1; break;
+               case Iop_Dup32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, False));
+            return res;
+         }
+         case Iop_Abs8x8:
+         case Iop_Abs16x4:
+         case Iop_Abs32x2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Abs8x8: size = 0; break;
+               case Iop_Abs16x4: size = 1; break;
+               case Iop_Abs32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, False));
+            return res;
+         }
+         case Iop_Reverse64_8x8:
+         case Iop_Reverse64_16x4:
+         case Iop_Reverse64_32x2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Reverse64_8x8: size = 0; break;
+               case Iop_Reverse64_16x4: size = 1; break;
+               case Iop_Reverse64_32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_REV64,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_Reverse32_8x8:
+         case Iop_Reverse32_16x4: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Reverse32_8x8: size = 0; break;
+               case Iop_Reverse32_16x4: size = 1; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_REV32,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_Reverse16_8x8: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NUnary(ARMneon_REV16,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_CmpwNEZ64: {
+            HReg x_lsh = newVRegD(env);
+            HReg x_rsh = newVRegD(env);
+            HReg lsh_amt = newVRegD(env);
+            HReg rsh_amt = newVRegD(env);
+            HReg zero = newVRegD(env);
+            HReg tmp = newVRegD(env);
+            HReg tmp2 = newVRegD(env);
+            HReg res = newVRegD(env);
+            HReg x = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, False));
+            addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, False));
+            addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32)));
+            addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0)));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
+                                           rsh_amt, zero, lsh_amt, 2, False));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          x_lsh, x, lsh_amt, 3, False));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          x_rsh, x, rsh_amt, 3, False));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
+                                           tmp, x_lsh, x_rsh, 0, False));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
+                                           res, tmp, x, 0, False));
+            return res;
+         }
+         case Iop_CmpNEZ8x8:
+         case Iop_CmpNEZ16x4:
+         case Iop_CmpNEZ32x2: {
+            HReg res = newVRegD(env);
+            HReg tmp = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size;
+            switch (e->Iex.Unop.op) {
+               case Iop_CmpNEZ8x8: size = 0; break;
+               case Iop_CmpNEZ16x4: size = 1; break;
+               case Iop_CmpNEZ32x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, False));
+            addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, False));
+            return res;
+         }
+         case Iop_Shorten16x8:
+         case Iop_Shorten32x4:
+         case Iop_Shorten64x2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Shorten16x8: size = 0; break;
+               case Iop_Shorten32x4: size = 1; break;
+               case Iop_Shorten64x2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_COPYN,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_QShortenS16Sx8:
+         case Iop_QShortenS32Sx4:
+         case Iop_QShortenS64Sx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_QShortenS16Sx8: size = 0; break;
+               case Iop_QShortenS32Sx4: size = 1; break;
+               case Iop_QShortenS64Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNSS,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_QShortenU16Sx8:
+         case Iop_QShortenU32Sx4:
+         case Iop_QShortenU64Sx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_QShortenU16Sx8: size = 0; break;
+               case Iop_QShortenU32Sx4: size = 1; break;
+               case Iop_QShortenU64Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUS,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_QShortenU16Ux8:
+         case Iop_QShortenU32Ux4:
+         case Iop_QShortenU64Ux2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_QShortenU16Ux8: size = 0; break;
+               case Iop_QShortenU32Ux4: size = 1; break;
+               case Iop_QShortenU64Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUU,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_PwAddL8Sx8:
+         case Iop_PwAddL16Sx4:
+         case Iop_PwAddL32Sx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwAddL8Sx8: size = 0; break;
+               case Iop_PwAddL16Sx4: size = 1; break;
+               case Iop_PwAddL32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_PwAddL8Ux8:
+         case Iop_PwAddL16Ux4:
+         case Iop_PwAddL32Ux2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwAddL8Ux8: size = 0; break;
+               case Iop_PwAddL16Ux4: size = 1; break;
+               case Iop_PwAddL32Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_Cnt8x8: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NUnary(ARMneon_CNT,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_Clz8Sx8:
+         case Iop_Clz16Sx4:
+         case Iop_Clz32Sx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Clz8Sx8: size = 0; break;
+               case Iop_Clz16Sx4: size = 1; break;
+               case Iop_Clz32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_CLZ,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_Cls8Sx8:
+         case Iop_Cls16Sx4:
+         case Iop_Cls32Sx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Cls8Sx8: size = 0; break;
+               case Iop_Cls16Sx4: size = 1; break;
+               case Iop_Cls32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_CLS,
+                                          res, arg, size, False));
+            return res;
+         }
+         case Iop_FtoI32Sx2_RZ: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
+                                          res, arg, 2, False));
+            return res;
+         }
+         case Iop_FtoI32Ux2_RZ: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
+                                          res, arg, 2, False));
+            return res;
+         }
+         case Iop_I32StoFx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
+                                          res, arg, 2, False));
+            return res;
+         }
+         case Iop_I32UtoFx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
+                                          res, arg, 2, False));
+            return res;
+         }
+         case Iop_F32toF16x4: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF32toF16,
+                                          res, arg, 2, False));
+            return res;
+         }
+         case Iop_Recip32Fx2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF,
+                                          res, argL, 0, False));
+            return res;
+         }
+         case Iop_Recip32x2: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP,
+                                          res, argL, 0, False));
+            return res;
+         }
+         case Iop_Abs32Fx2: {
+            DECLARE_PATTERN(p_vabd_32fx2);
+            DEFINE_PATTERN(p_vabd_32fx2,
+                           unop(Iop_Abs32Fx2,
+                                binop(Iop_Sub32Fx2,
+                                      bind(0),
+                                      bind(1))));
+            if (matchIRExpr(&mi, p_vabd_32fx2, e)) {
+               HReg res = newVRegD(env);
+               HReg argL = iselNeon64Expr(env, mi.bindee[0]);
+               HReg argR = iselNeon64Expr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP,
+                                              res, argL, argR, 0, False));
+               return res;
+            } else {
+               HReg res = newVRegD(env);
+               HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+               addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
+                                             res, arg, 0, False));
+               return res;
+            }
+         }
+         case Iop_Rsqrte32Fx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP,
+                                          res, arg, 0, False));
+            return res;
+         }
+         case Iop_Rsqrte32x2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE,
+                                          res, arg, 0, False));
+            return res;
+         }
+         case Iop_Neg32Fx2: {
+            HReg res = newVRegD(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF,
+                                          res, arg, 0, False));
+            return res;
+         }
+         default:
+            break;
+      }
+   } /* if (e->tag == Iex_Unop) */
+
+   if (e->tag == Iex_Triop) {
+      switch (e->Iex.Triop.op) {
+         case Iop_Extract64: {
+            HReg res = newVRegD(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Triop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Triop.arg2);
+            UInt imm4;
+            if (e->Iex.Triop.arg3->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Triop.arg3) != Ity_I8) {
+               vpanic("ARM target supports Iop_Extract64 with constant "
+                      "third argument less than 16 only\n");
+            }
+            imm4 = e->Iex.Triop.arg3->Iex.Const.con->Ico.U8;
+            if (imm4 >= 8) {
+               vpanic("ARM target supports Iop_Extract64 with constant "
+                      "third argument less than 16 only\n");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VEXT,
+                                           res, argL, argR, imm4, False));
+            return res;
+         }
+         case Iop_SetElem8x8:
+         case Iop_SetElem16x4:
+         case Iop_SetElem32x2: {
+            HReg res = newVRegD(env);
+            HReg dreg = iselNeon64Expr(env, e->Iex.Triop.arg1);
+            HReg arg = iselIntExpr_R(env, e->Iex.Triop.arg3);
+            UInt index, size;
+            if (e->Iex.Triop.arg2->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Triop.arg2) != Ity_I8) {
+               vpanic("ARM target supports SetElem with constant "
+                      "second argument only\n");
+            }
+            index = e->Iex.Triop.arg2->Iex.Const.con->Ico.U8;
+            switch (e->Iex.Triop.op) {
+               case Iop_SetElem8x8: vassert(index < 8); size = 0; break;
+               case Iop_SetElem16x4: vassert(index < 4); size = 1; break;
+               case Iop_SetElem32x2: vassert(index < 2); size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_COPY, res, dreg, 4, False));
+            addInstr(env, ARMInstr_NUnaryS(ARMneon_SETELEM,
+                                           mkARMNRS(ARMNRS_Scalar, res, index),
+                                           mkARMNRS(ARMNRS_Reg, arg, 0),
+                                           size, False));
+            return res;
+         }
+         default:
+            break;
+      }
+   }
+
+   /* --------- MULTIPLEX --------- */
+   if (e->tag == Iex_Mux0X) {
+      HReg rLo, rHi;
+      HReg res = newVRegD(env);
+      iselInt64Expr(&rHi, &rLo, env, e);
+      addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
+      return res;
+   }
+
+   ppIRExpr(e);
+   vpanic("iselNeon64Expr");
+}
+
+static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e )
+{
+   HReg r = iselNeonExpr_wrk( env, e );
+   vassert(hregClass(r) == HRcVec128);
+   vassert(hregIsVirtual(r));
+   return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e )
+{
+   IRType ty = typeOfIRExpr(env->type_env, e);
+   MatchInfo mi;
+   vassert(e);
+   vassert(ty == Ity_V128);
+
+   if (e->tag == Iex_RdTmp) {
+      return lookupIRTemp(env, e->Iex.RdTmp.tmp);
+   }
+
+   if (e->tag == Iex_Const) {
+      /* At the moment there should be no 128-bit constants in IR for ARM
+         generated during disassemble. They are represented as Iop_64HLtoV128
+         binary operation and are handled among binary ops. */
+      /* But zero can be created by valgrind internal optimizer */
+      if (e->Iex.Const.con->Ico.V128 == 0) {
+         HReg res = newVRegV(env);
+         addInstr(env, ARMInstr_NeonImm(res, ARMNImm_TI(0, 0)));
+         return res;
+      }
+      ppIRExpr(e);
+      vpanic("128-bit constant is not implemented");
+   }
+
+   if (e->tag == Iex_Load) {
+      HReg res = newVRegV(env);
+      ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr);
+      vassert(ty == Ity_V128);
+      addInstr(env, ARMInstr_NLdStQ(True, res, am));
+      return res;
+   }
+
+   if (e->tag == Iex_Get) {
+      HReg addr = newVRegI(env);
+      HReg res = newVRegV(env);
+      vassert(ty == Ity_V128);
+      addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset));
+      addInstr(env, ARMInstr_NLdStQ(True, res, mkARMAModeN_R(addr)));
+      return res;
+   }
+
+   if (e->tag == Iex_Unop) {
+      switch (e->Iex.Unop.op) {
+         case Iop_NotV128: {
+            DECLARE_PATTERN(p_veqz_8x16);
+            DECLARE_PATTERN(p_veqz_16x8);
+            DECLARE_PATTERN(p_veqz_32x4);
+            DECLARE_PATTERN(p_vcge_8sx16);
+            DECLARE_PATTERN(p_vcge_16sx8);
+            DECLARE_PATTERN(p_vcge_32sx4);
+            DECLARE_PATTERN(p_vcge_8ux16);
+            DECLARE_PATTERN(p_vcge_16ux8);
+            DECLARE_PATTERN(p_vcge_32ux4);
+            DEFINE_PATTERN(p_veqz_8x16,
+                  unop(Iop_NotV128, unop(Iop_CmpNEZ8x16, bind(0))));
+            DEFINE_PATTERN(p_veqz_16x8,
+                  unop(Iop_NotV128, unop(Iop_CmpNEZ16x8, bind(0))));
+            DEFINE_PATTERN(p_veqz_32x4,
+                  unop(Iop_NotV128, unop(Iop_CmpNEZ32x4, bind(0))));
+            DEFINE_PATTERN(p_vcge_8sx16,
+                  unop(Iop_NotV128, binop(Iop_CmpGT8Sx16, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_16sx8,
+                  unop(Iop_NotV128, binop(Iop_CmpGT16Sx8, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_32sx4,
+                  unop(Iop_NotV128, binop(Iop_CmpGT32Sx4, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_8ux16,
+                  unop(Iop_NotV128, binop(Iop_CmpGT8Ux16, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_16ux8,
+                  unop(Iop_NotV128, binop(Iop_CmpGT16Ux8, bind(1), bind(0))));
+            DEFINE_PATTERN(p_vcge_32ux4,
+                  unop(Iop_NotV128, binop(Iop_CmpGT32Ux4, bind(1), bind(0))));
+            if (matchIRExpr(&mi, p_veqz_8x16, e)) {
+               HReg res = newVRegV(env);
+               HReg arg = iselNeonExpr(env, mi.bindee[0]);
+               addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, True));
+               return res;
+            } else if (matchIRExpr(&mi, p_veqz_16x8, e)) {
+               HReg res = newVRegV(env);
+               HReg arg = iselNeonExpr(env, mi.bindee[0]);
+               addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, True));
+               return res;
+            } else if (matchIRExpr(&mi, p_veqz_32x4, e)) {
+               HReg res = newVRegV(env);
+               HReg arg = iselNeonExpr(env, mi.bindee[0]);
+               addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, True));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_8sx16, e)) {
+               HReg res = newVRegV(env);
+               HReg argL = iselNeonExpr(env, mi.bindee[0]);
+               HReg argR = iselNeonExpr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
+                                              res, argL, argR, 0, True));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_16sx8, e)) {
+               HReg res = newVRegV(env);
+               HReg argL = iselNeonExpr(env, mi.bindee[0]);
+               HReg argR = iselNeonExpr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
+                                              res, argL, argR, 1, True));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_32sx4, e)) {
+               HReg res = newVRegV(env);
+               HReg argL = iselNeonExpr(env, mi.bindee[0]);
+               HReg argR = iselNeonExpr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
+                                              res, argL, argR, 2, True));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_8ux16, e)) {
+               HReg res = newVRegV(env);
+               HReg argL = iselNeonExpr(env, mi.bindee[0]);
+               HReg argR = iselNeonExpr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
+                                              res, argL, argR, 0, True));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_16ux8, e)) {
+               HReg res = newVRegV(env);
+               HReg argL = iselNeonExpr(env, mi.bindee[0]);
+               HReg argR = iselNeonExpr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
+                                              res, argL, argR, 1, True));
+               return res;
+            } else if (matchIRExpr(&mi, p_vcge_32ux4, e)) {
+               HReg res = newVRegV(env);
+               HReg argL = iselNeonExpr(env, mi.bindee[0]);
+               HReg argR = iselNeonExpr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
+                                              res, argL, argR, 2, True));
+               return res;
+            } else {
+               HReg res = newVRegV(env);
+               HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+               addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, True));
+               return res;
+            }
+         }
+         case Iop_Dup8x16:
+         case Iop_Dup16x8:
+         case Iop_Dup32x4: {
+            HReg res, arg;
+            UInt size;
+            DECLARE_PATTERN(p_vdup_8x16);
+            DECLARE_PATTERN(p_vdup_16x8);
+            DECLARE_PATTERN(p_vdup_32x4);
+            DEFINE_PATTERN(p_vdup_8x16,
+                  unop(Iop_Dup8x16, binop(Iop_GetElem8x8, bind(0), bind(1))));
+            DEFINE_PATTERN(p_vdup_16x8,
+                  unop(Iop_Dup16x8, binop(Iop_GetElem16x4, bind(0), bind(1))));
+            DEFINE_PATTERN(p_vdup_32x4,
+                  unop(Iop_Dup32x4, binop(Iop_GetElem32x2, bind(0), bind(1))));
+            if (matchIRExpr(&mi, p_vdup_8x16, e)) {
+               UInt index;
+               UInt imm4;
+               if (mi.bindee[1]->tag == Iex_Const &&
+                  typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
+                  index = mi.bindee[1]->Iex.Const.con->Ico.U8;
+                  imm4 = (index << 1) + 1;
+                  if (index < 8) {
+                     res = newVRegV(env);
+                     arg = iselNeon64Expr(env, mi.bindee[0]);
+                     addInstr(env, ARMInstr_NUnaryS(
+                                      ARMneon_VDUP,
+                                      mkARMNRS(ARMNRS_Reg, res, 0),
+                                      mkARMNRS(ARMNRS_Scalar, arg, index),
+                                      imm4, True
+                             ));
+                     return res;
+                  }
+               }
+            } else if (matchIRExpr(&mi, p_vdup_16x8, e)) {
+               UInt index;
+               UInt imm4;
+               if (mi.bindee[1]->tag == Iex_Const &&
+                  typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
+                  index = mi.bindee[1]->Iex.Const.con->Ico.U8;
+                  imm4 = (index << 2) + 2;
+                  if (index < 4) {
+                     res = newVRegV(env);
+                     arg = iselNeon64Expr(env, mi.bindee[0]);
+                     addInstr(env, ARMInstr_NUnaryS(
+                                      ARMneon_VDUP,
+                                      mkARMNRS(ARMNRS_Reg, res, 0),
+                                      mkARMNRS(ARMNRS_Scalar, arg, index),
+                                      imm4, True
+                             ));
+                     return res;
+                  }
+               }
+            } else if (matchIRExpr(&mi, p_vdup_32x4, e)) {
+               UInt index;
+               UInt imm4;
+               if (mi.bindee[1]->tag == Iex_Const &&
+                  typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
+                  index = mi.bindee[1]->Iex.Const.con->Ico.U8;
+                  imm4 = (index << 3) + 4;
+                  if (index < 2) {
+                     res = newVRegV(env);
+                     arg = iselNeon64Expr(env, mi.bindee[0]);
+                     addInstr(env, ARMInstr_NUnaryS(
+                                      ARMneon_VDUP,
+                                      mkARMNRS(ARMNRS_Reg, res, 0),
+                                      mkARMNRS(ARMNRS_Scalar, arg, index),
+                                      imm4, True
+                             ));
+                     return res;
+                  }
+               }
+            }
+            arg = iselIntExpr_R(env, e->Iex.Unop.arg);
+            res = newVRegV(env);
+            switch (e->Iex.Unop.op) {
+               case Iop_Dup8x16: size = 0; break;
+               case Iop_Dup16x8: size = 1; break;
+               case Iop_Dup32x4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, True));
+            return res;
+         }
+         case Iop_Abs8x16:
+         case Iop_Abs16x8:
+         case Iop_Abs32x4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Abs8x16: size = 0; break;
+               case Iop_Abs16x8: size = 1; break;
+               case Iop_Abs32x4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, True));
+            return res;
+         }
+         case Iop_Reverse64_8x16:
+         case Iop_Reverse64_16x8:
+         case Iop_Reverse64_32x4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Reverse64_8x16: size = 0; break;
+               case Iop_Reverse64_16x8: size = 1; break;
+               case Iop_Reverse64_32x4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_REV64,
+                                          res, arg, size, True));
+            return res;
+         }
+         case Iop_Reverse32_8x16:
+         case Iop_Reverse32_16x8: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Reverse32_8x16: size = 0; break;
+               case Iop_Reverse32_16x8: size = 1; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_REV32,
+                                          res, arg, size, True));
+            return res;
+         }
+         case Iop_Reverse16_8x16: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NUnary(ARMneon_REV16,
+                                          res, arg, size, True));
+            return res;
+         }
+         case Iop_CmpNEZ64x2: {
+            HReg x_lsh = newVRegV(env);
+            HReg x_rsh = newVRegV(env);
+            HReg lsh_amt = newVRegV(env);
+            HReg rsh_amt = newVRegV(env);
+            HReg zero = newVRegV(env);
+            HReg tmp = newVRegV(env);
+            HReg tmp2 = newVRegV(env);
+            HReg res = newVRegV(env);
+            HReg x = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, True));
+            addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, True));
+            addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32)));
+            addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0)));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
+                                           rsh_amt, zero, lsh_amt, 2, True));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          x_lsh, x, lsh_amt, 3, True));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          x_rsh, x, rsh_amt, 3, True));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
+                                           tmp, x_lsh, x_rsh, 0, True));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
+                                           res, tmp, x, 0, True));
+            return res;
+         }
+         case Iop_CmpNEZ8x16:
+         case Iop_CmpNEZ16x8:
+         case Iop_CmpNEZ32x4: {
+            HReg res = newVRegV(env);
+            HReg tmp = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size;
+            switch (e->Iex.Unop.op) {
+               case Iop_CmpNEZ8x16: size = 0; break;
+               case Iop_CmpNEZ16x8: size = 1; break;
+               case Iop_CmpNEZ32x4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, True));
+            addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, True));
+            return res;
+         }
+         case Iop_Longen8Ux8:
+         case Iop_Longen16Ux4:
+         case Iop_Longen32Ux2: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size;
+            switch (e->Iex.Unop.op) {
+               case Iop_Longen8Ux8: size = 0; break;
+               case Iop_Longen16Ux4: size = 1; break;
+               case Iop_Longen32Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_COPYLU,
+                                          res, arg, size, True));
+            return res;
+         }
+         case Iop_Longen8Sx8:
+         case Iop_Longen16Sx4:
+         case Iop_Longen32Sx2: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            UInt size;
+            switch (e->Iex.Unop.op) {
+               case Iop_Longen8Sx8: size = 0; break;
+               case Iop_Longen16Sx4: size = 1; break;
+               case Iop_Longen32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_COPYLS,
+                                          res, arg, size, True));
+            return res;
+         }
+         case Iop_PwAddL8Sx16:
+         case Iop_PwAddL16Sx8:
+         case Iop_PwAddL32Sx4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwAddL8Sx16: size = 0; break;
+               case Iop_PwAddL16Sx8: size = 1; break;
+               case Iop_PwAddL32Sx4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS,
+                                          res, arg, size, True));
+            return res;
+         }
+         case Iop_PwAddL8Ux16:
+         case Iop_PwAddL16Ux8:
+         case Iop_PwAddL32Ux4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwAddL8Ux16: size = 0; break;
+               case Iop_PwAddL16Ux8: size = 1; break;
+               case Iop_PwAddL32Ux4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU,
+                                          res, arg, size, True));
+            return res;
+         }
+         case Iop_Cnt8x16: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NUnary(ARMneon_CNT, res, arg, size, True));
+            return res;
+         }
+         case Iop_Clz8Sx16:
+         case Iop_Clz16Sx8:
+         case Iop_Clz32Sx4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Clz8Sx16: size = 0; break;
+               case Iop_Clz16Sx8: size = 1; break;
+               case Iop_Clz32Sx4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, res, arg, size, True));
+            return res;
+         }
+         case Iop_Cls8Sx16:
+         case Iop_Cls16Sx8:
+         case Iop_Cls32Sx4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Cls8Sx16: size = 0; break;
+               case Iop_Cls16Sx8: size = 1; break;
+               case Iop_Cls32Sx4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True));
+            return res;
+         }
+         case Iop_FtoI32Sx4_RZ: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
+                                          res, arg, 2, True));
+            return res;
+         }
+         case Iop_FtoI32Ux4_RZ: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
+                                          res, arg, 2, True));
+            return res;
+         }
+         case Iop_I32StoFx4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
+                                          res, arg, 2, True));
+            return res;
+         }
+         case Iop_I32UtoFx4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
+                                          res, arg, 2, True));
+            return res;
+         }
+         case Iop_F16toF32x4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF16toF32,
+                                          res, arg, 2, True));
+            return res;
+         }
+         case Iop_Recip32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF,
+                                          res, argL, 0, True));
+            return res;
+         }
+         case Iop_Recip32x4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP,
+                                          res, argL, 0, True));
+            return res;
+         }
+         case Iop_Abs32Fx4: {
+            DECLARE_PATTERN(p_vabd_32fx4);
+            DEFINE_PATTERN(p_vabd_32fx4,
+                           unop(Iop_Abs32Fx4,
+                                binop(Iop_Sub32Fx4,
+                                      bind(0),
+                                      bind(1))));
+            if (matchIRExpr(&mi, p_vabd_32fx4, e)) {
+               HReg res = newVRegV(env);
+               HReg argL = iselNeonExpr(env, mi.bindee[0]);
+               HReg argR = iselNeonExpr(env, mi.bindee[1]);
+               addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP,
+                                              res, argL, argR, 0, True));
+               return res;
+            } else {
+               HReg res = newVRegV(env);
+               HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
+               addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
+                                             res, argL, 0, True));
+               return res;
+            }
+         }
+         case Iop_Rsqrte32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP,
+                                          res, argL, 0, True));
+            return res;
+         }
+         case Iop_Rsqrte32x4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE,
+                                          res, argL, 0, True));
+            return res;
+         }
+         case Iop_Neg32Fx4: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF,
+                                          res, arg, 0, True));
+            return res;
+         }
+         /* ... */
+         default:
+            break;
+      }
+   }
+
+   if (e->tag == Iex_Binop) {
+      switch (e->Iex.Binop.op) {
+         case Iop_64HLtoV128:
+            /* Try to match into single "VMOV reg, imm" instruction */
+            if (e->Iex.Binop.arg1->tag == Iex_Const &&
+                e->Iex.Binop.arg2->tag == Iex_Const &&
+                typeOfIRExpr(env->type_env, e->Iex.Binop.arg1) == Ity_I64 &&
+                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) == Ity_I64 &&
+                e->Iex.Binop.arg1->Iex.Const.con->Ico.U64 ==
+                           e->Iex.Binop.arg2->Iex.Const.con->Ico.U64) {
+               ULong imm64 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U64;
+               ARMNImm *imm = Imm64_to_ARMNImm(imm64);
+               if (imm) {
+                  HReg res = newVRegV(env);
+                  addInstr(env, ARMInstr_NeonImm(res, imm));
+                  return res;
+               }
+               if ((imm64 >> 32) == 0LL &&
+                   (imm = Imm64_to_ARMNImm(imm64 | (imm64 << 32))) != NULL) {
+                  HReg tmp1 = newVRegV(env);
+                  HReg tmp2 = newVRegV(env);
+                  HReg res = newVRegV(env);
+                  if (imm->type < 10) {
+                     addInstr(env, ARMInstr_NeonImm(tmp1, ARMNImm_TI(9,0x0f)));
+                     addInstr(env, ARMInstr_NeonImm(tmp2, imm));
+                     addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
+                                                    res, tmp1, tmp2, 4, True));
+                     return res;
+                  }
+               }
+               if ((imm64 & 0xFFFFFFFFLL) == 0LL &&
+                   (imm = Imm64_to_ARMNImm(imm64 | (imm64 >> 32))) != NULL) {
+                  HReg tmp1 = newVRegV(env);
+                  HReg tmp2 = newVRegV(env);
+                  HReg res = newVRegV(env);
+                  if (imm->type < 10) {
+                     addInstr(env, ARMInstr_NeonImm(tmp1, ARMNImm_TI(9,0xf0)));
+                     addInstr(env, ARMInstr_NeonImm(tmp2, imm));
+                     addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
+                                                    res, tmp1, tmp2, 4, True));
+                     return res;
+                  }
+               }
+            }
+            /* Does not match "VMOV Reg, Imm" form */
+            goto neon_expr_bad;
+         case Iop_AndV128: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
+                                           res, argL, argR, 4, True));
+            return res;
+         }
+         case Iop_OrV128: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
+                                           res, argL, argR, 4, True));
+            return res;
+         }
+         case Iop_XorV128: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VXOR,
+                                           res, argL, argR, 4, True));
+            return res;
+         }
+         case Iop_Add8x16:
+         case Iop_Add16x8:
+         case Iop_Add32x4:
+         case Iop_Add64x2: {
+            /* 
+            FIXME: remove this if not used
+            DECLARE_PATTERN(p_vrhadd_32sx4);
+            ULong one = (1LL << 32) | 1LL;
+            DEFINE_PATTERN(p_vrhadd_32sx4,
+                  binop(Iop_Add32x4,
+                        binop(Iop_Add32x4,
+                              binop(Iop_SarN32x4,
+                                    bind(0),
+                                    mkU8(1)),
+                              binop(Iop_SarN32x4,
+                                    bind(1),
+                                    mkU8(1))),
+                        binop(Iop_SarN32x4,
+                              binop(Iop_Add32x4,
+                                    binop(Iop_Add32x4,
+                                          binop(Iop_AndV128,
+                                                bind(0),
+                                                mkU128(one)),
+                                          binop(Iop_AndV128,
+                                                bind(1),
+                                                mkU128(one))),
+                                    mkU128(one)),
+                              mkU8(1))));
+            */
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Add8x16: size = 0; break;
+               case Iop_Add16x8: size = 1; break;
+               case Iop_Add32x4: size = 2; break;
+               case Iop_Add64x2: size = 3; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VADD");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VADD,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Add32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Recps32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Rsqrts32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_InterleaveEvenLanes8x16:
+         case Iop_InterleaveEvenLanes16x8:
+         case Iop_InterleaveEvenLanes32x4:
+         case Iop_InterleaveOddLanes8x16:
+         case Iop_InterleaveOddLanes16x8:
+         case Iop_InterleaveOddLanes32x4: {
+            HReg tmp = newVRegV(env);
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            UInt is_lo;
+            switch (e->Iex.Binop.op) {
+               case Iop_InterleaveEvenLanes8x16: is_lo = 0; size = 0; break;
+               case Iop_InterleaveOddLanes8x16: is_lo = 1; size = 0; break;
+               case Iop_InterleaveEvenLanes16x8: is_lo = 0; size = 1; break;
+               case Iop_InterleaveOddLanes16x8: is_lo = 1; size = 1; break;
+               case Iop_InterleaveEvenLanes32x4: is_lo = 0; size = 2; break;
+               case Iop_InterleaveOddLanes32x4: is_lo = 1; size = 2; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VTRN");
+            }
+            if (is_lo) {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argL, 4, True));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argR, 4, True));
+               addInstr(env, ARMInstr_NDual(ARMneon_TRN,
+                                            res, tmp, size, True));
+            } else {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argR, 4, True));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argL, 4, True));
+               addInstr(env, ARMInstr_NDual(ARMneon_TRN,
+                                            tmp, res, size, True));
+            }
+            return res;
+         }
+         case Iop_InterleaveHI8x16:
+         case Iop_InterleaveHI16x8:
+         case Iop_InterleaveHI32x4:
+         case Iop_InterleaveLO8x16:
+         case Iop_InterleaveLO16x8:
+         case Iop_InterleaveLO32x4: {
+            HReg tmp = newVRegV(env);
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            UInt is_lo;
+            switch (e->Iex.Binop.op) {
+               case Iop_InterleaveHI8x16: is_lo = 1; size = 0; break;
+               case Iop_InterleaveLO8x16: is_lo = 0; size = 0; break;
+               case Iop_InterleaveHI16x8: is_lo = 1; size = 1; break;
+               case Iop_InterleaveLO16x8: is_lo = 0; size = 1; break;
+               case Iop_InterleaveHI32x4: is_lo = 1; size = 2; break;
+               case Iop_InterleaveLO32x4: is_lo = 0; size = 2; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VZIP");
+            }
+            if (is_lo) {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argL, 4, True));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argR, 4, True));
+               addInstr(env, ARMInstr_NDual(ARMneon_ZIP,
+                                            res, tmp, size, True));
+            } else {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argR, 4, True));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argL, 4, True));
+               addInstr(env, ARMInstr_NDual(ARMneon_ZIP,
+                                            tmp, res, size, True));
+            }
+            return res;
+         }
+         case Iop_CatOddLanes8x16:
+         case Iop_CatOddLanes16x8:
+         case Iop_CatOddLanes32x4:
+         case Iop_CatEvenLanes8x16:
+         case Iop_CatEvenLanes16x8:
+         case Iop_CatEvenLanes32x4: {
+            HReg tmp = newVRegV(env);
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            UInt is_lo;
+            switch (e->Iex.Binop.op) {
+               case Iop_CatOddLanes8x16: is_lo = 1; size = 0; break;
+               case Iop_CatEvenLanes8x16: is_lo = 0; size = 0; break;
+               case Iop_CatOddLanes16x8: is_lo = 1; size = 1; break;
+               case Iop_CatEvenLanes16x8: is_lo = 0; size = 1; break;
+               case Iop_CatOddLanes32x4: is_lo = 1; size = 2; break;
+               case Iop_CatEvenLanes32x4: is_lo = 0; size = 2; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VUZP");
+            }
+            if (is_lo) {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argL, 4, True));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argR, 4, True));
+               addInstr(env, ARMInstr_NDual(ARMneon_UZP,
+                                            res, tmp, size, True));
+            } else {
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             tmp, argR, 4, True));
+               addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
+                                             res, argL, 4, True));
+               addInstr(env, ARMInstr_NDual(ARMneon_UZP,
+                                            tmp, res, size, True));
+            }
+            return res;
+         }
+         case Iop_QAdd8Ux16:
+         case Iop_QAdd16Ux8:
+         case Iop_QAdd32Ux4:
+         case Iop_QAdd64Ux2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QAdd8Ux16: size = 0; break;
+               case Iop_QAdd16Ux8: size = 1; break;
+               case Iop_QAdd32Ux4: size = 2; break;
+               case Iop_QAdd64Ux2: size = 3; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VQADDU");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_QAdd8Sx16:
+         case Iop_QAdd16Sx8:
+         case Iop_QAdd32Sx4:
+         case Iop_QAdd64Sx2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QAdd8Sx16: size = 0; break;
+               case Iop_QAdd16Sx8: size = 1; break;
+               case Iop_QAdd32Sx4: size = 2; break;
+               case Iop_QAdd64Sx2: size = 3; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VQADDS");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Sub8x16:
+         case Iop_Sub16x8:
+         case Iop_Sub32x4:
+         case Iop_Sub64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Sub8x16: size = 0; break;
+               case Iop_Sub16x8: size = 1; break;
+               case Iop_Sub32x4: size = 2; break;
+               case Iop_Sub64x2: size = 3; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VSUB");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Sub32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_QSub8Ux16:
+         case Iop_QSub16Ux8:
+         case Iop_QSub32Ux4:
+         case Iop_QSub64Ux2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QSub8Ux16: size = 0; break;
+               case Iop_QSub16Ux8: size = 1; break;
+               case Iop_QSub32Ux4: size = 2; break;
+               case Iop_QSub64Ux2: size = 3; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VQSUBU");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_QSub8Sx16:
+         case Iop_QSub16Sx8:
+         case Iop_QSub32Sx4:
+         case Iop_QSub64Sx2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QSub8Sx16: size = 0; break;
+               case Iop_QSub16Sx8: size = 1; break;
+               case Iop_QSub32Sx4: size = 2; break;
+               case Iop_QSub64Sx2: size = 3; break;
+               default:
+                  ppIROp(e->Iex.Binop.op);
+                  vpanic("Illegal element size in VQSUBS");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Max8Ux16:
+         case Iop_Max16Ux8:
+         case Iop_Max32Ux4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Max8Ux16: size = 0; break;
+               case Iop_Max16Ux8: size = 1; break;
+               case Iop_Max32Ux4: size = 2; break;
+               default: vpanic("Illegal element size in VMAXU");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Max8Sx16:
+         case Iop_Max16Sx8:
+         case Iop_Max32Sx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Max8Sx16: size = 0; break;
+               case Iop_Max16Sx8: size = 1; break;
+               case Iop_Max32Sx4: size = 2; break;
+               default: vpanic("Illegal element size in VMAXU");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Min8Ux16:
+         case Iop_Min16Ux8:
+         case Iop_Min32Ux4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Min8Ux16: size = 0; break;
+               case Iop_Min16Ux8: size = 1; break;
+               case Iop_Min32Ux4: size = 2; break;
+               default: vpanic("Illegal element size in VMAXU");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMINU,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Min8Sx16:
+         case Iop_Min16Sx8:
+         case Iop_Min32Sx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Min8Sx16: size = 0; break;
+               case Iop_Min16Sx8: size = 1; break;
+               case Iop_Min32Sx4: size = 2; break;
+               default: vpanic("Illegal element size in VMAXU");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMINS,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Sar8x16:
+         case Iop_Sar16x8:
+         case Iop_Sar32x4:
+         case Iop_Sar64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            HReg argR2 = newVRegV(env);
+            HReg zero = newVRegV(env);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Sar8x16: size = 0; break;
+               case Iop_Sar16x8: size = 1; break;
+               case Iop_Sar32x4: size = 2; break;
+               case Iop_Sar64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
+                                           argR2, zero, argR, size, True));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
+                                          res, argL, argR2, size, True));
+            return res;
+         }
+         case Iop_Sal8x16:
+         case Iop_Sal16x8:
+         case Iop_Sal32x4:
+         case Iop_Sal64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Sal8x16: size = 0; break;
+               case Iop_Sal16x8: size = 1; break;
+               case Iop_Sal32x4: size = 2; break;
+               case Iop_Sal64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
+                                          res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Shr8x16:
+         case Iop_Shr16x8:
+         case Iop_Shr32x4:
+         case Iop_Shr64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            HReg argR2 = newVRegV(env);
+            HReg zero = newVRegV(env);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Shr8x16: size = 0; break;
+               case Iop_Shr16x8: size = 1; break;
+               case Iop_Shr32x4: size = 2; break;
+               case Iop_Shr64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
+            addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
+                                           argR2, zero, argR, size, True));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          res, argL, argR2, size, True));
+            return res;
+         }
+         case Iop_Shl8x16:
+         case Iop_Shl16x8:
+         case Iop_Shl32x4:
+         case Iop_Shl64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_Shl8x16: size = 0; break;
+               case Iop_Shl16x8: size = 1; break;
+               case Iop_Shl32x4: size = 2; break;
+               case Iop_Shl64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_QShl8x16:
+         case Iop_QShl16x8:
+         case Iop_QShl32x4:
+         case Iop_QShl64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QShl8x16: size = 0; break;
+               case Iop_QShl16x8: size = 1; break;
+               case Iop_QShl32x4: size = 2; break;
+               case Iop_QShl64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NShift(ARMneon_VQSHL,
+                                          res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_QSal8x16:
+         case Iop_QSal16x8:
+         case Iop_QSal32x4:
+         case Iop_QSal64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_QSal8x16: size = 0; break;
+               case Iop_QSal16x8: size = 1; break;
+               case Iop_QSal32x4: size = 2; break;
+               case Iop_QSal64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NShift(ARMneon_VQSAL,
+                                          res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_QShlN8x16:
+         case Iop_QShlN16x8:
+         case Iop_QShlN32x4:
+         case Iop_QShlN64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            UInt size, imm;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+               vpanic("ARM taget supports Iop_QShlNAxB with constant "
+                      "second argument only\n");
+            }
+            imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            switch (e->Iex.Binop.op) {
+               case Iop_QShlN8x16: size = 8 | imm; break;
+               case Iop_QShlN16x8: size = 16 | imm; break;
+               case Iop_QShlN32x4: size = 32 | imm; break;
+               case Iop_QShlN64x2: size = 64 | imm; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU,
+                                          res, argL, size, True));
+            return res;
+         }
+         case Iop_QShlN8Sx16:
+         case Iop_QShlN16Sx8:
+         case Iop_QShlN32Sx4:
+         case Iop_QShlN64Sx2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            UInt size, imm;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+               vpanic("ARM taget supports Iop_QShlNASxB with constant "
+                      "second argument only\n");
+            }
+            imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            switch (e->Iex.Binop.op) {
+               case Iop_QShlN8Sx16: size = 8 | imm; break;
+               case Iop_QShlN16Sx8: size = 16 | imm; break;
+               case Iop_QShlN32Sx4: size = 32 | imm; break;
+               case Iop_QShlN64Sx2: size = 64 | imm; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS,
+                                          res, argL, size, True));
+            return res;
+         }
+         case Iop_QSalN8x16:
+         case Iop_QSalN16x8:
+         case Iop_QSalN32x4:
+         case Iop_QSalN64x2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            UInt size, imm;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+               vpanic("ARM taget supports Iop_QShlNAxB with constant "
+                      "second argument only\n");
+            }
+            imm = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            switch (e->Iex.Binop.op) {
+               case Iop_QSalN8x16: size = 8 | imm; break;
+               case Iop_QSalN16x8: size = 16 | imm; break;
+               case Iop_QSalN32x4: size = 32 | imm; break;
+               case Iop_QSalN64x2: size = 64 | imm; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS,
+                                          res, argL, size, True));
+            return res;
+         }
+         case Iop_ShrN8x16:
+         case Iop_ShrN16x8:
+         case Iop_ShrN32x4:
+         case Iop_ShrN64x2: {
+            HReg res = newVRegV(env);
+            HReg tmp = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
+            HReg argR2 = newVRegI(env);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_ShrN8x16: size = 0; break;
+               case Iop_ShrN16x8: size = 1; break;
+               case Iop_ShrN32x4: size = 2; break;
+               case Iop_ShrN64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
+            addInstr(env, ARMInstr_NUnary(ARMneon_DUP,
+                                          tmp, argR2, 0, True));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          res, argL, tmp, size, True));
+            return res;
+         }
+         case Iop_ShlN8x16:
+         case Iop_ShlN16x8:
+         case Iop_ShlN32x4:
+         case Iop_ShlN64x2: {
+            HReg res = newVRegV(env);
+            HReg tmp = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_ShlN8x16: size = 0; break;
+               case Iop_ShlN16x8: size = 1; break;
+               case Iop_ShlN32x4: size = 2; break;
+               case Iop_ShlN64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR, 0, True));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
+                                          res, argL, tmp, size, True));
+            return res;
+         }
+         case Iop_SarN8x16:
+         case Iop_SarN16x8:
+         case Iop_SarN32x4:
+         case Iop_SarN64x2: {
+            HReg res = newVRegV(env);
+            HReg tmp = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
+            HReg argR2 = newVRegI(env);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_SarN8x16: size = 0; break;
+               case Iop_SarN16x8: size = 1; break;
+               case Iop_SarN32x4: size = 2; break;
+               case Iop_SarN64x2: size = 3; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
+            addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, True));
+            addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
+                                          res, argL, tmp, size, True));
+            return res;
+         }
+         case Iop_CmpGT8Ux16:
+         case Iop_CmpGT16Ux8:
+         case Iop_CmpGT32Ux4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_CmpGT8Ux16: size = 0; break;
+               case Iop_CmpGT16Ux8: size = 1; break;
+               case Iop_CmpGT32Ux4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_CmpGT8Sx16:
+         case Iop_CmpGT16Sx8:
+         case Iop_CmpGT32Sx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_CmpGT8Sx16: size = 0; break;
+               case Iop_CmpGT16Sx8: size = 1; break;
+               case Iop_CmpGT32Sx4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_CmpEQ8x16:
+         case Iop_CmpEQ16x8:
+         case Iop_CmpEQ32x4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size;
+            switch (e->Iex.Binop.op) {
+               case Iop_CmpEQ8x16: size = 0; break;
+               case Iop_CmpEQ16x8: size = 1; break;
+               case Iop_CmpEQ32x4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Mul8x16:
+         case Iop_Mul16x8:
+         case Iop_Mul32x4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Mul8x16: size = 0; break;
+               case Iop_Mul16x8: size = 1; break;
+               case Iop_Mul32x4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMUL,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Mul32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Mull8Ux8:
+         case Iop_Mull16Ux4:
+         case Iop_Mull32Ux2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Mull8Ux8: size = 0; break;
+               case Iop_Mull16Ux4: size = 1; break;
+               case Iop_Mull32Ux2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMULLU,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+
+         case Iop_Mull8Sx8:
+         case Iop_Mull16Sx4:
+         case Iop_Mull32Sx2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_Mull8Sx8: size = 0; break;
+               case Iop_Mull16Sx4: size = 1; break;
+               case Iop_Mull32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMULLS,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+
+         case Iop_QDMulHi16Sx8:
+         case Iop_QDMulHi32Sx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_QDMulHi16Sx8: size = 1; break;
+               case Iop_QDMulHi32Sx4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+
+         case Iop_QRDMulHi16Sx8:
+         case Iop_QRDMulHi32Sx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_QRDMulHi16Sx8: size = 1; break;
+               case Iop_QRDMulHi32Sx4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+
+         case Iop_QDMulLong16Sx4:
+         case Iop_QDMulLong32Sx2: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_QDMulLong16Sx4: size = 1; break;
+               case Iop_QDMulLong32Sx2: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULL,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_PolynomialMul8x16: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMULP,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_Max32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF,
+                                           res, argL, argR, 2, True));
+            return res;
+         }
+         case Iop_Min32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMINF,
+                                           res, argL, argR, 2, True));
+            return res;
+         }
+         case Iop_PwMax32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF,
+                                           res, argL, argR, 2, True));
+            return res;
+         }
+         case Iop_PwMin32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF,
+                                           res, argL, argR, 2, True));
+            return res;
+         }
+         case Iop_CmpGT32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF,
+                                           res, argL, argR, 2, True));
+            return res;
+         }
+         case Iop_CmpGE32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF,
+                                           res, argL, argR, 2, True));
+            return res;
+         }
+         case Iop_CmpEQ32Fx4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF,
+                                           res, argL, argR, 2, True));
+            return res;
+         }
+
+         case Iop_PolynomialMull8x8: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            addInstr(env, ARMInstr_NBinary(ARMneon_VMULLP,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         case Iop_F32ToFixed32Ux4_RZ:
+         case Iop_F32ToFixed32Sx4_RZ:
+         case Iop_Fixed32UToF32x4_RN:
+         case Iop_Fixed32SToF32x4_RN: {
+            HReg res = newVRegV(env);
+            HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1);
+            ARMNeonUnOp op;
+            UInt imm6;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+               typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+                  vpanic("ARM supports FP <-> Fixed conversion with constant "
+                         "second argument less than 33 only\n");
+            }
+            imm6 = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            vassert(imm6 <= 32 && imm6 > 0);
+            imm6 = 64 - imm6;
+            switch(e->Iex.Binop.op) {
+               case Iop_F32ToFixed32Ux4_RZ: op = ARMneon_VCVTFtoFixedU; break;
+               case Iop_F32ToFixed32Sx4_RZ: op = ARMneon_VCVTFtoFixedS; break;
+               case Iop_Fixed32UToF32x4_RN: op = ARMneon_VCVTFixedUtoF; break;
+               case Iop_Fixed32SToF32x4_RN: op = ARMneon_VCVTFixedStoF; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True));
+            return res;
+         }
+         /*
+         FIXME remove if not used
+         case Iop_VDup8x16:
+         case Iop_VDup16x8:
+         case Iop_VDup32x4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
+            UInt imm4;
+            UInt index;
+            if (e->Iex.Binop.arg2->tag != Iex_Const ||
+               typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
+                  vpanic("ARM supports Iop_VDup with constant "
+                         "second argument less than 16 only\n");
+            }
+            index = e->Iex.Binop.arg2->Iex.Const.con->Ico.U8;
+            switch(e->Iex.Binop.op) {
+               case Iop_VDup8x16: imm4 = (index << 1) + 1; break;
+               case Iop_VDup16x8: imm4 = (index << 2) + 2; break;
+               case Iop_VDup32x4: imm4 = (index << 3) + 4; break;
+               default: vassert(0);
+            }
+            if (imm4 >= 16) {
+               vpanic("ARM supports Iop_VDup with constant "
+                      "second argument less than 16 only\n");
+            }
+            addInstr(env, ARMInstr_NUnary(ARMneon_VDUP,
+                                          res, argL, imm4, True));
+            return res;
+         }
+         */
+         case Iop_PwAdd8x16:
+         case Iop_PwAdd16x8:
+         case Iop_PwAdd32x4: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
+            UInt size = 0;
+            switch(e->Iex.Binop.op) {
+               case Iop_PwAdd8x16: size = 0; break;
+               case Iop_PwAdd16x8: size = 1; break;
+               case Iop_PwAdd32x4: size = 2; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VPADD,
+                                           res, argL, argR, size, True));
+            return res;
+         }
+         /* ... */
+         default:
+            break;
+      }
+   }
+
+   if (e->tag == Iex_Triop) {
+      switch (e->Iex.Triop.op) {
+         case Iop_ExtractV128: {
+            HReg res = newVRegV(env);
+            HReg argL = iselNeonExpr(env, e->Iex.Triop.arg1);
+            HReg argR = iselNeonExpr(env, e->Iex.Triop.arg2);
+            UInt imm4;
+            if (e->Iex.Triop.arg3->tag != Iex_Const ||
+                typeOfIRExpr(env->type_env, e->Iex.Triop.arg3) != Ity_I8) {
+               vpanic("ARM target supports Iop_ExtractV128 with constant "
+                      "third argument less than 16 only\n");
+            }
+            imm4 = e->Iex.Triop.arg3->Iex.Const.con->Ico.U8;
+            if (imm4 >= 16) {
+               vpanic("ARM target supports Iop_ExtractV128 with constant "
+                      "third argument less than 16 only\n");
+            }
+            addInstr(env, ARMInstr_NBinary(ARMneon_VEXT,
+                                           res, argL, argR, imm4, True));
+            return res;
+         }
+         default:
+            break;
+      }
+   }
+
+   if (e->tag == Iex_Mux0X) {
+      HReg r8;
+      HReg rX  = iselNeonExpr(env, e->Iex.Mux0X.exprX);
+      HReg r0  = iselNeonExpr(env, e->Iex.Mux0X.expr0);
+      HReg dst = newVRegV(env);
+      addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, rX, 4, True));
+      r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
+      addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8,
+                                      ARMRI84_I84(0xFF,0)));
+      addInstr(env, ARMInstr_NCMovQ(ARMcc_EQ, dst, r0));
+      return dst;
+   }
+
+  neon_expr_bad:
+   ppIRExpr(e);
+   vpanic("iselNeonExpr_wrk");
+}
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Floating point expressions (64 bit)         ---*/
+/*---------------------------------------------------------*/
+
+/* Compute a 64-bit floating point value into a register, the identity
+   of which is returned.  As with iselIntExpr_R, the reg may be either
+   real or virtual; in any case it must not be changed by subsequent
+   code emitted by the caller.  */
+
+static HReg iselDblExpr ( ISelEnv* env, IRExpr* e )
+{
+   HReg r = iselDblExpr_wrk( env, e );
+#  if 0
+   vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
+#  endif
+   vassert(hregClass(r) == HRcFlt64);
+   vassert(hregIsVirtual(r));
+   return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
+{
+   IRType ty = typeOfIRExpr(env->type_env,e);
+   vassert(e);
+   vassert(ty == Ity_F64);
+
+   if (e->tag == Iex_RdTmp) {
+      return lookupIRTemp(env, e->Iex.RdTmp.tmp);
+   }
+
+   if (e->tag == Iex_Const) {
+      /* Just handle the zero case. */
+      IRConst* con = e->Iex.Const.con;
+      if (con->tag == Ico_F64i && con->Ico.F64i == 0ULL) {
+         HReg z32 = newVRegI(env);
+         HReg dst = newVRegD(env);
+         addInstr(env, ARMInstr_Imm32(z32, 0));
+         addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, z32, z32));
+         return dst;
+      }
+   }
+
+   if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
+      ARMAModeV* am;
+      HReg res = newVRegD(env);
+      vassert(e->Iex.Load.ty == Ity_F64);
+      am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
+      addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am));
+      return res;
+   }
+
+   if (e->tag == Iex_Get) {
+      // XXX This won't work if offset > 1020 or is not 0 % 4.
+      // In which case we'll have to generate more longwinded code.
+      ARMAModeV* am  = mkARMAModeV(hregARM_R8(), e->Iex.Get.offset);
+      HReg       res = newVRegD(env);
+      addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am));
+      return res;
+   }
+
+   if (e->tag == Iex_Unop) {
+      switch (e->Iex.Unop.op) {
+         case Iop_ReinterpI64asF64: {
+            if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+               return iselNeon64Expr(env, e->Iex.Unop.arg);
+            } else {
+               HReg srcHi, srcLo;
+               HReg dst = newVRegD(env);
+               iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
+               addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, srcHi, srcLo));
+               return dst;
+            }
+         }
+         case Iop_NegF64: {
+            HReg src = iselDblExpr(env, e->Iex.Unop.arg);
+            HReg dst = newVRegD(env);
+            addInstr(env, ARMInstr_VUnaryD(ARMvfpu_NEG, dst, src));
+            return dst;
+         }
+         case Iop_AbsF64: {
+            HReg src = iselDblExpr(env, e->Iex.Unop.arg);
+            HReg dst = newVRegD(env);
+            addInstr(env, ARMInstr_VUnaryD(ARMvfpu_ABS, dst, src));
+            return dst;
+         }
+         case Iop_F32toF64: {
+            HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+            HReg dst = newVRegD(env);
+            addInstr(env, ARMInstr_VCvtSD(True/*sToD*/, dst, src));
+            return dst;
+         }
+         case Iop_I32UtoF64:
+         case Iop_I32StoF64: {
+            HReg src   = iselIntExpr_R(env, e->Iex.Unop.arg);
+            HReg f32   = newVRegF(env);
+            HReg dst   = newVRegD(env);
+            Bool syned = e->Iex.Unop.op == Iop_I32StoF64;
+            /* VMOV f32, src */
+            addInstr(env, ARMInstr_VXferS(True/*toS*/, f32, src));
+            /* FSITOD dst, f32 */
+            addInstr(env, ARMInstr_VCvtID(True/*iToD*/, syned,
+                                          dst, f32));
+            return dst;
+         }
+         default:
+            break;
+      }
+   }
+
+   if (e->tag == Iex_Binop) {
+      switch (e->Iex.Binop.op) {
+         case Iop_SqrtF64: {
+            /* first arg is rounding mode; we ignore it. */
+            HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
+            HReg dst = newVRegD(env);
+            addInstr(env, ARMInstr_VUnaryD(ARMvfpu_SQRT, dst, src));
+            return dst;
+         }
+         default:
+            break;
+      }
+   }
+
+   if (e->tag == Iex_Triop) {
+      switch (e->Iex.Triop.op) {
+         case Iop_DivF64:
+         case Iop_MulF64:
+         case Iop_AddF64:
+         case Iop_SubF64: {
+            ARMVfpOp op = 0; /*INVALID*/
+            HReg argL = iselDblExpr(env, e->Iex.Triop.arg2);
+            HReg argR = iselDblExpr(env, e->Iex.Triop.arg3);
+            HReg dst  = newVRegD(env);
+            switch (e->Iex.Triop.op) {
+               case Iop_DivF64: op = ARMvfp_DIV; break;
+               case Iop_MulF64: op = ARMvfp_MUL; break;
+               case Iop_AddF64: op = ARMvfp_ADD; break;
+               case Iop_SubF64: op = ARMvfp_SUB; break;
+               default: vassert(0);
+            }
+            addInstr(env, ARMInstr_VAluD(op, dst, argL, argR));
+            return dst;
+         }
+         default:
+            break;
+      }
+   }
+
+   if (e->tag == Iex_Mux0X) {
+      if (ty == Ity_F64
+          && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) {
+         HReg r8;
+         HReg rX  = iselDblExpr(env, e->Iex.Mux0X.exprX);
+         HReg r0  = iselDblExpr(env, e->Iex.Mux0X.expr0);
+         HReg dst = newVRegD(env);
+         addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, rX));
+         r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
+         addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8,
+                                         ARMRI84_I84(0xFF,0)));
+         addInstr(env, ARMInstr_VCMovD(ARMcc_EQ, dst, r0));
+         return dst;
+      }
+   }
+
+   ppIRExpr(e);
+   vpanic("iselDblExpr_wrk");
+}
+
+
+/*---------------------------------------------------------*/
+/*--- ISEL: Floating point expressions (32 bit)         ---*/
+/*---------------------------------------------------------*/
+
+/* Compute a 64-bit floating point value into a register, the identity
+   of which is returned.  As with iselIntExpr_R, the reg may be either
+   real or virtual; in any case it must not be changed by subsequent
+   code emitted by the caller.  */
+
+static HReg iselFltExpr ( ISelEnv* env, IRExpr* e )
+{
+   HReg r = iselFltExpr_wrk( env, e );
+#  if 0
+   vex_printf("\n"); ppIRExpr(e); vex_printf("\n");
+#  endif
+   vassert(hregClass(r) == HRcFlt32);
+   vassert(hregIsVirtual(r));
+   return r;
+}
+
+/* DO NOT CALL THIS DIRECTLY */
+static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
+{
+   IRType ty = typeOfIRExpr(env->type_env,e);
+   vassert(e);
+   vassert(ty == Ity_F32);
+
+   if (e->tag == Iex_RdTmp) {
+      return lookupIRTemp(env, e->Iex.RdTmp.tmp);
+   }
+
+   if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
+      ARMAModeV* am;
+      HReg res = newVRegF(env);
+      vassert(e->Iex.Load.ty == Ity_F32);
+      am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
+      addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
+      return res;
+   }
+
+   if (e->tag == Iex_Get) {
+      // XXX This won't work if offset > 1020 or is not 0 % 4.
+      // In which case we'll have to generate more longwinded code.
+      ARMAModeV* am  = mkARMAModeV(hregARM_R8(), e->Iex.Get.offset);
+      HReg       res = newVRegF(env);
+      addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
+      return res;
+   }
+
+   if (e->tag == Iex_Unop) {
+      switch (e->Iex.Unop.op) {
+         case Iop_ReinterpI32asF32: {
+            HReg dst = newVRegF(env);
+            HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
+            addInstr(env, ARMInstr_VXferS(True/*toS*/, dst, src));
+            return dst;
+         }
+         case Iop_NegF32: {
+            HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+            HReg dst = newVRegF(env);
+            addInstr(env, ARMInstr_VUnaryS(ARMvfpu_NEG, dst, src));
+            return dst;
+         }
+         case Iop_AbsF32: {
+            HReg src = iselFltExpr(env, e->Iex.Unop.arg);
+            HReg dst = newVRegF(env);

             addInstr(env, ARMInstr_VUnaryS(ARMvfpu_ABS, dst, src));
             return dst;
          }
             addInstr(env, ARMInstr_VUnaryS(ARMvfpu_ABS, dst, src));
             return dst;
          }


@@ -2159,13 +5515,19 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
          return;
       }
       if (tyd == Ity_I64) {
          return;
       }
       if (tyd == Ity_I64) {

-         HReg rDhi, rDlo, rA;
-         iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data);
-         rA = iselIntExpr_R(env, stmt->Ist.Store.addr);
-         addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDhi,
-                                       ARMAMode1_RI(rA,4)));
-         addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDlo,
-                                       ARMAMode1_RI(rA,0)));
+         if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+            HReg dD = iselNeon64Expr(env, stmt->Ist.Store.data);
+            ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
+            addInstr(env, ARMInstr_NLdStD(False, dD, am));
+         } else {
+            HReg rDhi, rDlo, rA;
+            iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data);
+            rA = iselIntExpr_R(env, stmt->Ist.Store.addr);
+            addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDhi,
+                                          ARMAMode1_RI(rA,4)));
+            addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDlo,
+                                          ARMAMode1_RI(rA,0)));
+         }

          return;
       }
       if (tyd == Ity_F64) {
          return;
       }
       if (tyd == Ity_F64) {


@@ -2180,6 +5542,12 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
          addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, fD, am));
          return;
       }
          addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, fD, am));
          return;
       }

+      if (tyd == Ity_V128) {
+         HReg       qD = iselNeonExpr(env, stmt->Ist.Store.data);
+         ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
+         addInstr(env, ARMInstr_NLdStQ(False, qD, am));
+         return;
+      }

 
       break;
    }
 
       break;
    }


@@ -2196,12 +5564,22 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
            return;
        }
        if (tyd == Ity_I64) {
            return;
        }
        if (tyd == Ity_I64) {

-          HReg rDhi, rDlo;
-          ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(), stmt->Ist.Put.offset + 0);
-          ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(), stmt->Ist.Put.offset + 4);
-          iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data);
-          addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDhi, am4));
-          addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDlo, am0));
+          if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+             HReg addr = newVRegI(env);
+             HReg qD = iselNeon64Expr(env, stmt->Ist.Put.data);
+             addInstr(env, ARMInstr_Add32(addr, hregARM_R8(),
+                                                stmt->Ist.Put.offset));
+             addInstr(env, ARMInstr_NLdStD(False, qD, mkARMAModeN_R(addr)));
+          } else {
+             HReg rDhi, rDlo;
+             ARMAMode1* am0 = ARMAMode1_RI(hregARM_R8(),
+                                           stmt->Ist.Put.offset + 0);
+             ARMAMode1* am4 = ARMAMode1_RI(hregARM_R8(),
+                                           stmt->Ist.Put.offset + 4);
+             iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data);
+             addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDhi, am4));
+             addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDlo, am0));
+          }

           return;
        }
        if (tyd == Ity_F64) {
           return;
        }
        if (tyd == Ity_F64) {


@@ -2220,6 +5598,14 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
           addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, rD, am));
           return;
        }
           addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, rD, am));
           return;
        }

+       if (tyd == Ity_V128) {
+          HReg addr = newVRegI(env);
+          HReg qD = iselNeonExpr(env, stmt->Ist.Put.data);
+          addInstr(env, ARMInstr_Add32(addr, hregARM_R8(),
+                                       stmt->Ist.Put.offset));
+          addInstr(env, ARMInstr_NLdStQ(False, qD, mkARMAModeN_R(addr)));
+          return;
+       }

        break;
    }
 
        break;
    }
 


@@ -2263,11 +5649,17 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
          return;
       }
       if (ty == Ity_I64) {
          return;
       }
       if (ty == Ity_I64) {

-         HReg rHi, rLo, dstHi, dstLo;
-         iselInt64Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
-         lookupIRTemp64( &dstHi, &dstLo, env, tmp);
-         addInstr(env, mk_iMOVds_RR(dstHi, rHi) );
-         addInstr(env, mk_iMOVds_RR(dstLo, rLo) );
+         if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+            HReg src = iselNeon64Expr(env, stmt->Ist.WrTmp.data);
+            HReg dst = lookupIRTemp(env, tmp);
+            addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, src, 4, False));
+         } else {
+            HReg rHi, rLo, dstHi, dstLo;
+            iselInt64Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
+            lookupIRTemp64( &dstHi, &dstLo, env, tmp);
+            addInstr(env, mk_iMOVds_RR(dstHi, rHi) );
+            addInstr(env, mk_iMOVds_RR(dstLo, rLo) );
+         }

          return;
       }
       if (ty == Ity_F64) {
          return;
       }
       if (ty == Ity_F64) {


@@ -2282,6 +5674,12 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
          addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, src));
          return;
       }
          addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, src));
          return;
       }

+      if (ty == Ity_V128) {
+         HReg src = iselNeonExpr(env, stmt->Ist.WrTmp.data);
+         HReg dst = lookupIRTemp(env, tmp);
+         addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, src, 4, True));
+         return;
+      }

       break;
    }
 
       break;
    }
 


@@ -2310,12 +5708,18 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
       retty = typeOfIRTemp(env->type_env, d->tmp);
 
       if (retty == Ity_I64) {
       retty = typeOfIRTemp(env->type_env, d->tmp);
 
       if (retty == Ity_I64) {

-         HReg dstHi, dstLo;
-         /* The returned value is in r1:r0.  Park it in the
-            register-pair associated with tmp. */
-         lookupIRTemp64( &dstHi, &dstLo, env, d->tmp);
-         addInstr(env, mk_iMOVds_RR(dstHi, hregARM_R1()) );
-         addInstr(env, mk_iMOVds_RR(dstLo, hregARM_R0()) );
+         if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+            HReg tmp = lookupIRTemp(env, d->tmp);
+            addInstr(env, ARMInstr_VXferD(True, tmp, hregARM_R1(),
+                                                     hregARM_R0()));
+         } else {
+            HReg dstHi, dstLo;
+            /* The returned value is in r1:r0.  Park it in the
+               register-pair associated with tmp. */
+            lookupIRTemp64( &dstHi, &dstLo, env, d->tmp);
+            addInstr(env, mk_iMOVds_RR(dstHi, hregARM_R1()) );
+            addInstr(env, mk_iMOVds_RR(dstLo, hregARM_R0()) );
+         }

          return;
       }
       if (retty == Ity_I32 || retty == Ity_I16 || retty == Ity_I8) {
          return;
       }
       if (retty == Ity_I32 || retty == Ity_I16 || retty == Ity_I8) {


@@ -2458,10 +5862,14 @@ HInstrArray* iselSB_ARM ( IRSB* bb, VexArch      arch_host,
    HReg     hreg, hregHI;
    ISelEnv* env;
    UInt     hwcaps_host = archinfo_host->hwcaps;
    HReg     hreg, hregHI;
    ISelEnv* env;
    UInt     hwcaps_host = archinfo_host->hwcaps;

+   Bool     neon = False;
+   static UInt counter = 0;

 
    /* sanity ... */
    vassert(arch_host == VexArchARM);
 
    /* sanity ... */
    vassert(arch_host == VexArchARM);

-   vassert(0 == hwcaps_host);
+
+   /* hwcaps should not change from one ISEL call to another. */
+   arm_hwcaps = hwcaps_host;

 
    /* Make up an initial environment to use. */
    env = LibVEX_Alloc(sizeof(ISelEnv));
 
    /* Make up an initial environment to use. */
    env = LibVEX_Alloc(sizeof(ISelEnv));


@@ -2489,11 +5897,19 @@ HInstrArray* iselSB_ARM ( IRSB* bb, VexArch      arch_host,
          case Ity_I8:
          case Ity_I16:
          case Ity_I32:  hreg   = mkHReg(j++, HRcInt32, True); break;
          case Ity_I8:
          case Ity_I16:
          case Ity_I32:  hreg   = mkHReg(j++, HRcInt32, True); break;

-         case Ity_I64:  hregHI = mkHReg(j++, HRcInt32, True);
-                        hreg   = mkHReg(j++, HRcInt32, True); break;
+         case Ity_I64:
+            if (arm_hwcaps & VEX_HWCAPS_ARM_NEON) {
+               hreg = mkHReg(j++, HRcFlt64, True);
+               neon = True;
+            } else {
+               hregHI = mkHReg(j++, HRcInt32, True);
+               hreg   = mkHReg(j++, HRcInt32, True);
+            }
+            break;

          case Ity_F32:  hreg   = mkHReg(j++, HRcFlt32, True); break;
          case Ity_F64:  hreg   = mkHReg(j++, HRcFlt64, True); break;
          case Ity_F32:  hreg   = mkHReg(j++, HRcFlt32, True); break;
          case Ity_F64:  hreg   = mkHReg(j++, HRcFlt64, True); break;

-         //case Ity_V128: hreg   = mkHReg(j++, HRcVec128, True); break;
+         case Ity_V128: hreg   = mkHReg(j++, HRcVec128, True);
+                        neon   = True; break;

          default: ppIRType(bb->tyenv->types[i]);
                   vpanic("iselBB: IRTemp type");
       }
          default: ppIRType(bb->tyenv->types[i]);
                   vpanic("iselBB: IRTemp type");
       }


@@ -2516,6 +5932,7 @@ HInstrArray* iselSB_ARM ( IRSB* bb, VexArch      arch_host,
 
    /* record the number of vregs we used. */
    env->code->n_vregs = env->vreg_ctr;
 
    /* record the number of vregs we used. */
    env->code->n_vregs = env->vreg_ctr;

+   counter++;

    return env->code;
 }
 
    return env->code;
 }
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_generic_simd128.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_generic_simd128.c
new file mode 100644 (file)
index 0000000..8ed5166
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_generic_simd128.c
@@ -0,0 +1,220 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin                            host_generic_simd128.c ---*/
+/*---------------------------------------------------------------*/
+
+/*
+   This file is part of Valgrind, a dynamic binary instrumentation
+   framework.
+
+   Copyright (C) 2010-2010 OpenWorks GbR
+      info@open-works.net
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Generic helper functions for doing 128-bit SIMD arithmetic in cases
+   where the instruction selectors cannot generate code in-line.
+   These are purely back-end entities and cannot be seen/referenced
+   from IR. */
+
+#include "libvex_basictypes.h"
+#include "host_generic_simd128.h"
+
+
+/* Primitive helpers always take args of the real type (signed vs
+   unsigned) but return an unsigned result, so there's no conversion
+   weirdness when stuffing results back in the V128 union fields,
+   which are all unsigned. */
+
+static inline UInt mul32 ( Int xx, Int yy )
+{
+   Int t = ((Int)xx) * ((Int)yy);
+   return toUInt(t);
+}
+
+static inline UInt max32S ( Int xx, Int yy )
+{
+   return toUInt((xx > yy) ? xx : yy);
+}
+
+static inline UInt min32S ( Int xx, Int yy )
+{
+   return toUInt((xx < yy) ? xx : yy);
+}
+
+static inline UInt max32U ( UInt xx, UInt yy )
+{
+   return toUInt((xx > yy) ? xx : yy);
+}
+
+static inline UInt min32U ( UInt xx, UInt yy )
+{
+   return toUInt((xx < yy) ? xx : yy);
+}
+
+static inline UShort max16U ( UShort xx, UShort yy )
+{
+   return toUShort((xx > yy) ? xx : yy);
+}
+
+static inline UShort min16U ( UShort xx, UShort yy )
+{
+   return toUShort((xx < yy) ? xx : yy);
+}
+
+static inline UChar max8S ( Char xx, Char yy )
+{
+   return toUChar((xx > yy) ? xx : yy);
+}
+
+static inline UChar min8S ( Char xx, Char yy )
+{
+   return toUChar((xx < yy) ? xx : yy);
+}
+
+static inline ULong cmpGT64S ( Long xx, Long yy )
+{
+   return (((Long)xx) > ((Long)yy))
+             ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+}
+
+void h_generic_calc_Mul32x4 ( /*OUT*/V128* res,
+                              V128* argL, V128* argR )
+{
+   res->w32[0] = mul32(argL->w32[0], argR->w32[0]);
+   res->w32[1] = mul32(argL->w32[1], argR->w32[1]);
+   res->w32[2] = mul32(argL->w32[2], argR->w32[2]);
+   res->w32[3] = mul32(argL->w32[3], argR->w32[3]);
+}
+
+void h_generic_calc_Max32Sx4 ( /*OUT*/V128* res,
+                               V128* argL, V128* argR )
+{
+   res->w32[0] = max32S(argL->w32[0], argR->w32[0]);
+   res->w32[1] = max32S(argL->w32[1], argR->w32[1]);
+   res->w32[2] = max32S(argL->w32[2], argR->w32[2]);
+   res->w32[3] = max32S(argL->w32[3], argR->w32[3]);
+}
+
+void h_generic_calc_Min32Sx4 ( /*OUT*/V128* res,
+                               V128* argL, V128* argR )
+{
+   res->w32[0] = min32S(argL->w32[0], argR->w32[0]);
+   res->w32[1] = min32S(argL->w32[1], argR->w32[1]);
+   res->w32[2] = min32S(argL->w32[2], argR->w32[2]);
+   res->w32[3] = min32S(argL->w32[3], argR->w32[3]);
+}
+
+void h_generic_calc_Max32Ux4 ( /*OUT*/V128* res,
+                               V128* argL, V128* argR )
+{
+   res->w32[0] = max32U(argL->w32[0], argR->w32[0]);
+   res->w32[1] = max32U(argL->w32[1], argR->w32[1]);
+   res->w32[2] = max32U(argL->w32[2], argR->w32[2]);
+   res->w32[3] = max32U(argL->w32[3], argR->w32[3]);
+}
+
+void h_generic_calc_Min32Ux4 ( /*OUT*/V128* res,
+                               V128* argL, V128* argR )
+{
+   res->w32[0] = min32U(argL->w32[0], argR->w32[0]);
+   res->w32[1] = min32U(argL->w32[1], argR->w32[1]);
+   res->w32[2] = min32U(argL->w32[2], argR->w32[2]);
+   res->w32[3] = min32U(argL->w32[3], argR->w32[3]);
+}
+
+void h_generic_calc_Max16Ux8 ( /*OUT*/V128* res,
+                               V128* argL, V128* argR )
+{
+   res->w16[0] = max16U(argL->w16[0], argR->w16[0]);
+   res->w16[1] = max16U(argL->w16[1], argR->w16[1]);
+   res->w16[2] = max16U(argL->w16[2], argR->w16[2]);
+   res->w16[3] = max16U(argL->w16[3], argR->w16[3]);
+   res->w16[4] = max16U(argL->w16[4], argR->w16[4]);
+   res->w16[5] = max16U(argL->w16[5], argR->w16[5]);
+   res->w16[6] = max16U(argL->w16[6], argR->w16[6]);
+   res->w16[7] = max16U(argL->w16[7], argR->w16[7]);
+}
+
+void h_generic_calc_Min16Ux8 ( /*OUT*/V128* res,
+                               V128* argL, V128* argR )
+{
+   res->w16[0] = min16U(argL->w16[0], argR->w16[0]);
+   res->w16[1] = min16U(argL->w16[1], argR->w16[1]);
+   res->w16[2] = min16U(argL->w16[2], argR->w16[2]);
+   res->w16[3] = min16U(argL->w16[3], argR->w16[3]);
+   res->w16[4] = min16U(argL->w16[4], argR->w16[4]);
+   res->w16[5] = min16U(argL->w16[5], argR->w16[5]);
+   res->w16[6] = min16U(argL->w16[6], argR->w16[6]);
+   res->w16[7] = min16U(argL->w16[7], argR->w16[7]);
+}
+
+void h_generic_calc_Max8Sx16 ( /*OUT*/V128* res,
+                               V128* argL, V128* argR )
+{
+   res->w8[ 0] = max8S(argL->w8[ 0], argR->w8[ 0]);
+   res->w8[ 1] = max8S(argL->w8[ 1], argR->w8[ 1]);
+   res->w8[ 2] = max8S(argL->w8[ 2], argR->w8[ 2]);
+   res->w8[ 3] = max8S(argL->w8[ 3], argR->w8[ 3]);
+   res->w8[ 4] = max8S(argL->w8[ 4], argR->w8[ 4]);
+   res->w8[ 5] = max8S(argL->w8[ 5], argR->w8[ 5]);
+   res->w8[ 6] = max8S(argL->w8[ 6], argR->w8[ 6]);
+   res->w8[ 7] = max8S(argL->w8[ 7], argR->w8[ 7]);
+   res->w8[ 8] = max8S(argL->w8[ 8], argR->w8[ 8]);
+   res->w8[ 9] = max8S(argL->w8[ 9], argR->w8[ 9]);
+   res->w8[10] = max8S(argL->w8[10], argR->w8[10]);
+   res->w8[11] = max8S(argL->w8[11], argR->w8[11]);
+   res->w8[12] = max8S(argL->w8[12], argR->w8[12]);
+   res->w8[13] = max8S(argL->w8[13], argR->w8[13]);
+   res->w8[14] = max8S(argL->w8[14], argR->w8[14]);
+   res->w8[15] = max8S(argL->w8[15], argR->w8[15]);
+}
+
+void h_generic_calc_Min8Sx16 ( /*OUT*/V128* res,
+                               V128* argL, V128* argR )
+{
+   res->w8[ 0] = min8S(argL->w8[ 0], argR->w8[ 0]);
+   res->w8[ 1] = min8S(argL->w8[ 1], argR->w8[ 1]);
+   res->w8[ 2] = min8S(argL->w8[ 2], argR->w8[ 2]);
+   res->w8[ 3] = min8S(argL->w8[ 3], argR->w8[ 3]);
+   res->w8[ 4] = min8S(argL->w8[ 4], argR->w8[ 4]);
+   res->w8[ 5] = min8S(argL->w8[ 5], argR->w8[ 5]);
+   res->w8[ 6] = min8S(argL->w8[ 6], argR->w8[ 6]);
+   res->w8[ 7] = min8S(argL->w8[ 7], argR->w8[ 7]);
+   res->w8[ 8] = min8S(argL->w8[ 8], argR->w8[ 8]);
+   res->w8[ 9] = min8S(argL->w8[ 9], argR->w8[ 9]);
+   res->w8[10] = min8S(argL->w8[10], argR->w8[10]);
+   res->w8[11] = min8S(argL->w8[11], argR->w8[11]);
+   res->w8[12] = min8S(argL->w8[12], argR->w8[12]);
+   res->w8[13] = min8S(argL->w8[13], argR->w8[13]);
+   res->w8[14] = min8S(argL->w8[14], argR->w8[14]);
+   res->w8[15] = min8S(argL->w8[15], argR->w8[15]);
+}
+
+void h_generic_calc_CmpGT64Sx2 ( /*OUT*/V128* res,
+                                 V128* argL, V128* argR )
+{
+   res->w64[0] = cmpGT64S(argL->w64[0], argR->w64[0]);
+   res->w64[1] = cmpGT64S(argL->w64[1], argR->w64[1]);
+}
+
+
+/*---------------------------------------------------------------*/
+/*--- end                              host_generic_simd128.c ---*/
+/*---------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_generic_simd128.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_generic_simd128.h
new file mode 100644 (file)
index 0000000..53850cb
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_generic_simd128.h
@@ -0,0 +1,67 @@
+
+/*---------------------------------------------------------------*/
+/*--- begin                             host_generic_simd128.h ---*/
+/*---------------------------------------------------------------*/
+
+/*
+   This file is part of Valgrind, a dynamic binary instrumentation
+   framework.
+
+   Copyright (C) 2010-2010 OpenWorks GbR
+      info@open-works.net
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+   02110-1301, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+*/
+
+/* Generic helper functions for doing 128-bit SIMD arithmetic in cases
+   where the instruction selectors cannot generate code in-line.
+   These are purely back-end entities and cannot be seen/referenced
+   as clean helper functions from IR.
+
+   These will get called from generated code and therefore should be
+   well behaved -- no floating point or mmx insns, just straight
+   integer code.
+
+   Each function implements the correspondingly-named IR primop.
+*/
+
+#ifndef __VEX_HOST_GENERIC_SIMD128_H
+#define __VEX_HOST_GENERIC_SIMD128_H
+
+#include "libvex_basictypes.h"
+
+/* DO NOT MAKE THESE INTO REGPARM FNS!  THIS WILL BREAK CALLING
+   SEQUENCES GENERATED BY host-x86/isel.c. */
+
+extern void h_generic_calc_Mul32x4    ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_Max32Sx4   ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_Min32Sx4   ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_Max32Ux4   ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_Min32Ux4   ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_Max16Ux8   ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_Min16Ux8   ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_Max8Sx16   ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_Min8Sx16   ( /*OUT*/V128*, V128*, V128* );
+extern void h_generic_calc_CmpGT64Sx2 ( /*OUT*/V128*, V128*, V128* );
+
+
+#endif /* ndef __VEX_HOST_GENERIC_SIMD128_H */
+
+/*---------------------------------------------------------------*/
+/*--- end                              host_generic_simd128.h ---*/
+/*---------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_x86_defs.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_x86_defs.c
index ff5e5fbbd37c48a2847a03f36635449e599bd8f9..adb55189291d13f06ecc700359151bb1952a9fe1 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_x86_defs.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_x86_defs.c
@@ -703,8 +703,10 @@ X86Instr* X86Instr_MFence ( UInt hwcaps ) {
    X86Instr* i          = LibVEX_Alloc(sizeof(X86Instr));
    i->tag               = Xin_MFence;
    i->Xin.MFence.hwcaps = hwcaps;
    X86Instr* i          = LibVEX_Alloc(sizeof(X86Instr));
    i->tag               = Xin_MFence;
    i->Xin.MFence.hwcaps = hwcaps;

-   vassert(0 == (hwcaps & ~(VEX_HWCAPS_X86_SSE1|VEX_HWCAPS_X86_SSE2
-                                               |VEX_HWCAPS_X86_SSE3)));
+   vassert(0 == (hwcaps & ~(VEX_HWCAPS_X86_SSE1
+                            |VEX_HWCAPS_X86_SSE2
+                            |VEX_HWCAPS_X86_SSE3
+                            |VEX_HWCAPS_X86_LZCNT)));

    return i;
 }
 X86Instr* X86Instr_ACAS ( X86AMode* addr, UChar sz ) {
    return i;
 }
 X86Instr* X86Instr_ACAS ( X86AMode* addr, UChar sz ) {

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_x86_isel.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_x86_isel.c
index 02d83d8af8cea7da9aab9fbb2e802d267aa0d85a..e6d92e0e4935bddf3b44701a51bc45f16d77ae08 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_x86_isel.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/host_x86_isel.c
@@ -2776,6 +2776,25 @@ static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
       return dst;
    }
 
       return dst;
    }
 

+   if (e->tag == Iex_Binop && e->Iex.Binop.op == Iop_RoundF32toInt) {
+      HReg rf  = iselFltExpr(env, e->Iex.Binop.arg2);
+      HReg dst = newVRegF(env);
+
+      /* rf now holds the value to be rounded.  The first thing to do
+         is set the FPU's rounding mode accordingly. */
+
+      /* Set host rounding mode */
+      set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
+
+      /* grndint %rf, %dst */
+      addInstr(env, X86Instr_FpUnary(Xfp_ROUND, rf, dst));
+
+      /* Restore default FPU rounding. */
+      set_FPU_rounding_default( env );
+
+      return dst;
+   }
+

    ppIRExpr(e);
    vpanic("iselFltExpr_wrk");
 }
    ppIRExpr(e);
    vpanic("iselFltExpr_wrk");
 }


@@ -3981,9 +4000,11 @@ HInstrArray* iselSB_X86 ( IRSB* bb, VexArch      arch_host,
 
    /* sanity ... */
    vassert(arch_host == VexArchX86);
 
    /* sanity ... */
    vassert(arch_host == VexArchX86);

-   vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_X86_SSE1
-                                 |VEX_HWCAPS_X86_SSE2
-                                 |VEX_HWCAPS_X86_SSE3)));
+   vassert(0 == (hwcaps_host
+                 & ~(VEX_HWCAPS_X86_SSE1
+                     | VEX_HWCAPS_X86_SSE2
+                     | VEX_HWCAPS_X86_SSE3
+                     | VEX_HWCAPS_X86_LZCNT)));

 
    /* Make up an initial environment to use. */
    env = LibVEX_Alloc(sizeof(ISelEnv));
 
    /* Make up an initial environment to use. */
    env = LibVEX_Alloc(sizeof(ISelEnv));

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_defs.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_defs.c
index 6d658199db996189b589cdc918f3b27685a4c815..f84f11d0324e44fe1b3ed720bc72e4e16896c904 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_defs.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_defs.c
@@ -302,6 +302,7 @@ void ppIROp ( IROp op )
       case Iop_F64toF32: vex_printf("F64toF32"); return;
 
       case Iop_RoundF64toInt: vex_printf("RoundF64toInt"); return;
       case Iop_F64toF32: vex_printf("F64toF32"); return;
 
       case Iop_RoundF64toInt: vex_printf("RoundF64toInt"); return;

+      case Iop_RoundF32toInt: vex_printf("RoundF32toInt"); return;

       case Iop_RoundF64toF32: vex_printf("RoundF64toF32"); return;
 
       case Iop_ReinterpF64asI64: vex_printf("ReinterpF64asI64"); return;
       case Iop_RoundF64toF32: vex_printf("RoundF64toF32"); return;
 
       case Iop_ReinterpF64asI64: vex_printf("ReinterpF64asI64"); return;


@@ -312,47 +313,125 @@ void ppIROp ( IROp op )
       case Iop_I32UtoFx4: vex_printf("I32UtoFx4"); return;
       case Iop_I32StoFx4: vex_printf("I32StoFx4"); return;
 
       case Iop_I32UtoFx4: vex_printf("I32UtoFx4"); return;
       case Iop_I32StoFx4: vex_printf("I32StoFx4"); return;
 

+      case Iop_F32toF16x4: vex_printf("F32toF16x4"); return;
+      case Iop_F16toF32x4: vex_printf("F16toF32x4"); return;
+
+      case Iop_Rsqrte32Fx4: vex_printf("VRsqrte32Fx4"); return;
+      case Iop_Rsqrte32x4:  vex_printf("VRsqrte32x4"); return;
+      case Iop_Rsqrte32Fx2: vex_printf("VRsqrte32Fx2"); return;
+      case Iop_Rsqrte32x2:  vex_printf("VRsqrte32x2"); return;
+

       case Iop_QFtoI32Ux4_RZ: vex_printf("QFtoI32Ux4_RZ"); return;
       case Iop_QFtoI32Sx4_RZ: vex_printf("QFtoI32Sx4_RZ"); return;
 
       case Iop_QFtoI32Ux4_RZ: vex_printf("QFtoI32Ux4_RZ"); return;
       case Iop_QFtoI32Sx4_RZ: vex_printf("QFtoI32Sx4_RZ"); return;
 

+      case Iop_FtoI32Ux4_RZ: vex_printf("FtoI32Ux4_RZ"); return;
+      case Iop_FtoI32Sx4_RZ: vex_printf("FtoI32Sx4_RZ"); return;
+
+      case Iop_I32UtoFx2: vex_printf("I32UtoFx2"); return;
+      case Iop_I32StoFx2: vex_printf("I32StoFx2"); return;
+
+      case Iop_FtoI32Ux2_RZ: vex_printf("FtoI32Ux2_RZ"); return;
+      case Iop_FtoI32Sx2_RZ: vex_printf("FtoI32Sx2_RZ"); return;
+

       case Iop_RoundF32x4_RM: vex_printf("RoundF32x4_RM"); return;
       case Iop_RoundF32x4_RP: vex_printf("RoundF32x4_RP"); return;
       case Iop_RoundF32x4_RN: vex_printf("RoundF32x4_RN"); return;
       case Iop_RoundF32x4_RZ: vex_printf("RoundF32x4_RZ"); return;
 
       case Iop_RoundF32x4_RM: vex_printf("RoundF32x4_RM"); return;
       case Iop_RoundF32x4_RP: vex_printf("RoundF32x4_RP"); return;
       case Iop_RoundF32x4_RN: vex_printf("RoundF32x4_RN"); return;
       case Iop_RoundF32x4_RZ: vex_printf("RoundF32x4_RZ"); return;
 

+      case Iop_Abs8x8: vex_printf("Abs8x8"); return;
+      case Iop_Abs16x4: vex_printf("Abs16x4"); return;
+      case Iop_Abs32x2: vex_printf("Abs32x2"); return;

       case Iop_Add8x8: vex_printf("Add8x8"); return;
       case Iop_Add16x4: vex_printf("Add16x4"); return;
       case Iop_Add32x2: vex_printf("Add32x2"); return;
       case Iop_QAdd8Ux8: vex_printf("QAdd8Ux8"); return;
       case Iop_QAdd16Ux4: vex_printf("QAdd16Ux4"); return;
       case Iop_Add8x8: vex_printf("Add8x8"); return;
       case Iop_Add16x4: vex_printf("Add16x4"); return;
       case Iop_Add32x2: vex_printf("Add32x2"); return;
       case Iop_QAdd8Ux8: vex_printf("QAdd8Ux8"); return;
       case Iop_QAdd16Ux4: vex_printf("QAdd16Ux4"); return;

+      case Iop_QAdd32Ux2: vex_printf("QAdd32Ux2"); return;
+      case Iop_QAdd64Ux1: vex_printf("QAdd64Ux1"); return;

       case Iop_QAdd8Sx8: vex_printf("QAdd8Sx8"); return;
       case Iop_QAdd16Sx4: vex_printf("QAdd16Sx4"); return;
       case Iop_QAdd8Sx8: vex_printf("QAdd8Sx8"); return;
       case Iop_QAdd16Sx4: vex_printf("QAdd16Sx4"); return;

+      case Iop_QAdd32Sx2: vex_printf("QAdd32Sx2"); return;
+      case Iop_QAdd64Sx1: vex_printf("QAdd64Sx1"); return;
+      case Iop_PwAdd8x8: vex_printf("PwAdd8x8"); return;
+      case Iop_PwAdd16x4: vex_printf("PwAdd16x4"); return;
+      case Iop_PwAdd32x2: vex_printf("PwAdd32x2"); return;
+      case Iop_PwAdd32Fx2: vex_printf("PwAdd32Fx2"); return;
+      case Iop_PwAddL8Ux8: vex_printf("PwAddL8Ux8"); return;
+      case Iop_PwAddL16Ux4: vex_printf("PwAddL16Ux4"); return;
+      case Iop_PwAddL32Ux2: vex_printf("PwAddL32Ux2"); return;
+      case Iop_PwAddL8Sx8: vex_printf("PwAddL8Sx8"); return;
+      case Iop_PwAddL16Sx4: vex_printf("PwAddL16Sx4"); return;
+      case Iop_PwAddL32Sx2: vex_printf("PwAddL32Sx2"); return;

       case Iop_Sub8x8: vex_printf("Sub8x8"); return;
       case Iop_Sub16x4: vex_printf("Sub16x4"); return;
       case Iop_Sub32x2: vex_printf("Sub32x2"); return;
       case Iop_QSub8Ux8: vex_printf("QSub8Ux8"); return;
       case Iop_QSub16Ux4: vex_printf("QSub16Ux4"); return;
       case Iop_Sub8x8: vex_printf("Sub8x8"); return;
       case Iop_Sub16x4: vex_printf("Sub16x4"); return;
       case Iop_Sub32x2: vex_printf("Sub32x2"); return;
       case Iop_QSub8Ux8: vex_printf("QSub8Ux8"); return;
       case Iop_QSub16Ux4: vex_printf("QSub16Ux4"); return;

+      case Iop_QSub32Ux2: vex_printf("QSub32Ux2"); return;
+      case Iop_QSub64Ux1: vex_printf("QSub64Ux1"); return;

       case Iop_QSub8Sx8: vex_printf("QSub8Sx8"); return;
       case Iop_QSub16Sx4: vex_printf("QSub16Sx4"); return;
       case Iop_QSub8Sx8: vex_printf("QSub8Sx8"); return;
       case Iop_QSub16Sx4: vex_printf("QSub16Sx4"); return;

+      case Iop_QSub32Sx2: vex_printf("QSub32Sx2"); return;
+      case Iop_QSub64Sx1: vex_printf("QSub64Sx1"); return;
+      case Iop_Mul8x8: vex_printf("Mul8x8"); return;

       case Iop_Mul16x4: vex_printf("Mul16x4"); return;
       case Iop_Mul32x2: vex_printf("Mul32x2"); return;
       case Iop_Mul16x4: vex_printf("Mul16x4"); return;
       case Iop_Mul32x2: vex_printf("Mul32x2"); return;

+      case Iop_Mul32Fx2: vex_printf("Mul32Fx2"); return;
+      case Iop_PolynomialMul8x8: vex_printf("PolynomialMul8x8"); return;

       case Iop_MulHi16Ux4: vex_printf("MulHi16Ux4"); return;
       case Iop_MulHi16Sx4: vex_printf("MulHi16Sx4"); return;
       case Iop_MulHi16Ux4: vex_printf("MulHi16Ux4"); return;
       case Iop_MulHi16Sx4: vex_printf("MulHi16Sx4"); return;

+      case Iop_QDMulHi16Sx4: vex_printf("QDMulHi16Sx4"); return;
+      case Iop_QDMulHi32Sx2: vex_printf("QDMulHi32Sx2"); return;
+      case Iop_QRDMulHi16Sx4: vex_printf("QRDMulHi16Sx4"); return;
+      case Iop_QRDMulHi32Sx2: vex_printf("QRDMulHi32Sx2"); return;
+      case Iop_QDMulLong16Sx4: vex_printf("QDMulLong16Sx4"); return;
+      case Iop_QDMulLong32Sx2: vex_printf("QDMulLong32Sx2"); return;

       case Iop_Avg8Ux8: vex_printf("Avg8Ux8"); return;
       case Iop_Avg16Ux4: vex_printf("Avg16Ux4"); return;
       case Iop_Avg8Ux8: vex_printf("Avg8Ux8"); return;
       case Iop_Avg16Ux4: vex_printf("Avg16Ux4"); return;

+      case Iop_Max8Sx8: vex_printf("Max8Sx8"); return;

       case Iop_Max16Sx4: vex_printf("Max16Sx4"); return;
       case Iop_Max16Sx4: vex_printf("Max16Sx4"); return;

+      case Iop_Max32Sx2: vex_printf("Max32Sx2"); return;

       case Iop_Max8Ux8: vex_printf("Max8Ux8"); return;
       case Iop_Max8Ux8: vex_printf("Max8Ux8"); return;

+      case Iop_Max16Ux4: vex_printf("Max16Ux4"); return;
+      case Iop_Max32Ux2: vex_printf("Max32Ux2"); return;
+      case Iop_Min8Sx8: vex_printf("Min8Sx8"); return;

       case Iop_Min16Sx4: vex_printf("Min16Sx4"); return;
       case Iop_Min16Sx4: vex_printf("Min16Sx4"); return;

+      case Iop_Min32Sx2: vex_printf("Min32Sx2"); return;

       case Iop_Min8Ux8: vex_printf("Min8Ux8"); return;
       case Iop_Min8Ux8: vex_printf("Min8Ux8"); return;

+      case Iop_Min16Ux4: vex_printf("Min16Ux4"); return;
+      case Iop_Min32Ux2: vex_printf("Min32Ux2"); return;
+      case Iop_PwMax8Sx8: vex_printf("PwMax8Sx8"); return;
+      case Iop_PwMax16Sx4: vex_printf("PwMax16Sx4"); return;
+      case Iop_PwMax32Sx2: vex_printf("PwMax32Sx2"); return;
+      case Iop_PwMax8Ux8: vex_printf("PwMax8Ux8"); return;
+      case Iop_PwMax16Ux4: vex_printf("PwMax16Ux4"); return;
+      case Iop_PwMax32Ux2: vex_printf("PwMax32Ux2"); return;
+      case Iop_PwMin8Sx8: vex_printf("PwMin8Sx8"); return;
+      case Iop_PwMin16Sx4: vex_printf("PwMin16Sx4"); return;
+      case Iop_PwMin32Sx2: vex_printf("PwMin32Sx2"); return;
+      case Iop_PwMin8Ux8: vex_printf("PwMin8Ux8"); return;
+      case Iop_PwMin16Ux4: vex_printf("PwMin16Ux4"); return;
+      case Iop_PwMin32Ux2: vex_printf("PwMin32Ux2"); return;

       case Iop_CmpEQ8x8: vex_printf("CmpEQ8x8"); return;
       case Iop_CmpEQ16x4: vex_printf("CmpEQ16x4"); return;
       case Iop_CmpEQ32x2: vex_printf("CmpEQ32x2"); return;
       case Iop_CmpEQ8x8: vex_printf("CmpEQ8x8"); return;
       case Iop_CmpEQ16x4: vex_printf("CmpEQ16x4"); return;
       case Iop_CmpEQ32x2: vex_printf("CmpEQ32x2"); return;

+      case Iop_CmpGT8Ux8: vex_printf("CmpGT8Ux8"); return;
+      case Iop_CmpGT16Ux4: vex_printf("CmpGT16Ux4"); return;
+      case Iop_CmpGT32Ux2: vex_printf("CmpGT32Ux2"); return;

       case Iop_CmpGT8Sx8: vex_printf("CmpGT8Sx8"); return;
       case Iop_CmpGT16Sx4: vex_printf("CmpGT16Sx4"); return;
       case Iop_CmpGT32Sx2: vex_printf("CmpGT32Sx2"); return;
       case Iop_CmpGT8Sx8: vex_printf("CmpGT8Sx8"); return;
       case Iop_CmpGT16Sx4: vex_printf("CmpGT16Sx4"); return;
       case Iop_CmpGT32Sx2: vex_printf("CmpGT32Sx2"); return;

+      case Iop_Cnt8x8: vex_printf("Cnt8x8"); return;
+      case Iop_Clz8Sx8: vex_printf("Clz8Sx8"); return;
+      case Iop_Clz16Sx4: vex_printf("Clz16Sx4"); return;
+      case Iop_Clz32Sx2: vex_printf("Clz32Sx2"); return;
+      case Iop_Cls8Sx8: vex_printf("Cls8Sx8"); return;
+      case Iop_Cls16Sx4: vex_printf("Cls16Sx4"); return;
+      case Iop_Cls32Sx2: vex_printf("Cls32Sx2"); return;

       case Iop_ShlN8x8: vex_printf("ShlN8x8"); return;
       case Iop_ShlN16x4: vex_printf("ShlN16x4"); return;
       case Iop_ShlN32x2: vex_printf("ShlN32x2"); return;
       case Iop_ShlN8x8: vex_printf("ShlN8x8"); return;
       case Iop_ShlN16x4: vex_printf("ShlN16x4"); return;
       case Iop_ShlN32x2: vex_printf("ShlN32x2"); return;

+      case Iop_ShrN8x8: vex_printf("ShrN8x8"); return;

       case Iop_ShrN16x4: vex_printf("ShrN16x4"); return;
       case Iop_ShrN32x2: vex_printf("ShrN32x2"); return;
       case Iop_SarN8x8: vex_printf("SarN8x8"); return;
       case Iop_ShrN16x4: vex_printf("ShrN16x4"); return;
       case Iop_ShrN32x2: vex_printf("ShrN32x2"); return;
       case Iop_SarN8x8: vex_printf("SarN8x8"); return;


@@ -367,15 +446,62 @@ void ppIROp ( IROp op )
       case Iop_InterleaveLO8x8: vex_printf("InterleaveLO8x8"); return;
       case Iop_InterleaveLO16x4: vex_printf("InterleaveLO16x4"); return;
       case Iop_InterleaveLO32x2: vex_printf("InterleaveLO32x2"); return;
       case Iop_InterleaveLO8x8: vex_printf("InterleaveLO8x8"); return;
       case Iop_InterleaveLO16x4: vex_printf("InterleaveLO16x4"); return;
       case Iop_InterleaveLO32x2: vex_printf("InterleaveLO32x2"); return;

+      case Iop_CatOddLanes8x8: vex_printf("CatOddLanes8x8"); return;

       case Iop_CatOddLanes16x4: vex_printf("CatOddLanes16x4"); return;
       case Iop_CatOddLanes16x4: vex_printf("CatOddLanes16x4"); return;

+      case Iop_CatEvenLanes8x8: vex_printf("CatEvenLanes8x8"); return;

       case Iop_CatEvenLanes16x4: vex_printf("CatEvenLanes16x4"); return;
       case Iop_CatEvenLanes16x4: vex_printf("CatEvenLanes16x4"); return;

+      case Iop_InterleaveOddLanes8x8: vex_printf("InterleaveOddLanes8x8"); return;
+      case Iop_InterleaveOddLanes16x4: vex_printf("InterleaveOddLanes16x4"); return;
+      case Iop_InterleaveEvenLanes8x8: vex_printf("InterleaveEvenLanes8x8"); return;
+      case Iop_InterleaveEvenLanes16x4: vex_printf("InterleaveEvenLanes16x4"); return;
+      case Iop_Shl8x8: vex_printf("Shl8x8"); return;
+      case Iop_Shl16x4: vex_printf("Shl16x4"); return;
+      case Iop_Shl32x2: vex_printf("Shl32x2"); return;
+      case Iop_Shr8x8: vex_printf("Shr8x8"); return;
+      case Iop_Shr16x4: vex_printf("Shr16x4"); return;
+      case Iop_Shr32x2: vex_printf("Shr32x2"); return;
+      case Iop_QShl8x8: vex_printf("QShl8x8"); return;
+      case Iop_QShl16x4: vex_printf("QShl16x4"); return;
+      case Iop_QShl32x2: vex_printf("QShl32x2"); return;
+      case Iop_QShl64x1: vex_printf("QShl64x1"); return;
+      case Iop_QSal8x8: vex_printf("QSal8x8"); return;
+      case Iop_QSal16x4: vex_printf("QSal16x4"); return;
+      case Iop_QSal32x2: vex_printf("QSal32x2"); return;
+      case Iop_QSal64x1: vex_printf("QSal64x1"); return;
+      case Iop_QShlN8x8: vex_printf("QShlN8x8"); return;
+      case Iop_QShlN16x4: vex_printf("QShlN16x4"); return;
+      case Iop_QShlN32x2: vex_printf("QShlN32x2"); return;
+      case Iop_QShlN64x1: vex_printf("QShlN64x1"); return;
+      case Iop_QShlN8Sx8: vex_printf("QShlN8Sx8"); return;
+      case Iop_QShlN16Sx4: vex_printf("QShlN16Sx4"); return;
+      case Iop_QShlN32Sx2: vex_printf("QShlN32Sx2"); return;
+      case Iop_QShlN64Sx1: vex_printf("QShlN64Sx1"); return;
+      case Iop_QSalN8x8: vex_printf("QSalN8x8"); return;
+      case Iop_QSalN16x4: vex_printf("QSalN16x4"); return;
+      case Iop_QSalN32x2: vex_printf("QSalN32x2"); return;
+      case Iop_QSalN64x1: vex_printf("QSalN64x1"); return;
+      case Iop_Sar8x8: vex_printf("Sar8x8"); return;
+      case Iop_Sar16x4: vex_printf("Sar16x4"); return;
+      case Iop_Sar32x2: vex_printf("Sar32x2"); return;
+      case Iop_Sal8x8: vex_printf("Sal8x8"); return;
+      case Iop_Sal16x4: vex_printf("Sal16x4"); return;
+      case Iop_Sal32x2: vex_printf("Sal32x2"); return;
+      case Iop_Sal64x1: vex_printf("Sal64x1"); return;

       case Iop_Perm8x8: vex_printf("Perm8x8"); return;
       case Iop_Perm8x8: vex_printf("Perm8x8"); return;

+      case Iop_Reverse16_8x8: vex_printf("Reverse16_8x8"); return;
+      case Iop_Reverse32_8x8: vex_printf("Reverse32_8x8"); return;
+      case Iop_Reverse32_16x4: vex_printf("Reverse32_16x4"); return;
+      case Iop_Reverse64_8x8: vex_printf("Reverse64_8x8"); return;
+      case Iop_Reverse64_16x4: vex_printf("Reverse64_16x4"); return;
+      case Iop_Reverse64_32x2: vex_printf("Reverse64_32x2"); return;
+      case Iop_Abs32Fx2: vex_printf("Abs32Fx2"); return;

 
       case Iop_CmpNEZ32x2: vex_printf("CmpNEZ32x2"); return;
       case Iop_CmpNEZ16x4: vex_printf("CmpNEZ16x4"); return;
       case Iop_CmpNEZ8x8:  vex_printf("CmpNEZ8x8"); return;
 
       case Iop_Add32Fx4:  vex_printf("Add32Fx4"); return;
 
       case Iop_CmpNEZ32x2: vex_printf("CmpNEZ32x2"); return;
       case Iop_CmpNEZ16x4: vex_printf("CmpNEZ16x4"); return;
       case Iop_CmpNEZ8x8:  vex_printf("CmpNEZ8x8"); return;
 
       case Iop_Add32Fx4:  vex_printf("Add32Fx4"); return;

+      case Iop_Add32Fx2:  vex_printf("Add32Fx2"); return;

       case Iop_Add32F0x4: vex_printf("Add32F0x4"); return;
       case Iop_Add64Fx2:  vex_printf("Add64Fx2"); return;
       case Iop_Add64F0x2: vex_printf("Add64F0x2"); return;
       case Iop_Add32F0x4: vex_printf("Add32F0x4"); return;
       case Iop_Add64Fx2:  vex_printf("Add64Fx2"); return;
       case Iop_Add64F0x2: vex_printf("Add64F0x2"); return;


@@ -386,11 +512,17 @@ void ppIROp ( IROp op )
       case Iop_Div64F0x2: vex_printf("Div64F0x2"); return;
 
       case Iop_Max32Fx4:  vex_printf("Max32Fx4"); return;
       case Iop_Div64F0x2: vex_printf("Div64F0x2"); return;
 
       case Iop_Max32Fx4:  vex_printf("Max32Fx4"); return;

+      case Iop_Max32Fx2:  vex_printf("Max32Fx2"); return;
+      case Iop_PwMax32Fx4:  vex_printf("PwMax32Fx4"); return;
+      case Iop_PwMax32Fx2:  vex_printf("PwMax32Fx2"); return;

       case Iop_Max32F0x4: vex_printf("Max32F0x4"); return;
       case Iop_Max64Fx2:  vex_printf("Max64Fx2"); return;
       case Iop_Max64F0x2: vex_printf("Max64F0x2"); return;
 
       case Iop_Min32Fx4:  vex_printf("Min32Fx4"); return;
       case Iop_Max32F0x4: vex_printf("Max32F0x4"); return;
       case Iop_Max64Fx2:  vex_printf("Max64Fx2"); return;
       case Iop_Max64F0x2: vex_printf("Max64F0x2"); return;
 
       case Iop_Min32Fx4:  vex_printf("Min32Fx4"); return;

+      case Iop_Min32Fx2:  vex_printf("Min32Fx2"); return;
+      case Iop_PwMin32Fx4:  vex_printf("PwMin32Fx4"); return;
+      case Iop_PwMin32Fx2:  vex_printf("PwMin32Fx2"); return;

       case Iop_Min32F0x4: vex_printf("Min32F0x4"); return;
       case Iop_Min64Fx2:  vex_printf("Min64Fx2"); return;
       case Iop_Min64F0x2: vex_printf("Min64F0x2"); return;
       case Iop_Min32F0x4: vex_printf("Min32F0x4"); return;
       case Iop_Min64Fx2:  vex_printf("Min64Fx2"); return;
       case Iop_Min64F0x2: vex_printf("Min64F0x2"); return;


@@ -400,10 +532,18 @@ void ppIROp ( IROp op )
       case Iop_Mul64Fx2:  vex_printf("Mul64Fx2"); return;
       case Iop_Mul64F0x2: vex_printf("Mul64F0x2"); return;
 
       case Iop_Mul64Fx2:  vex_printf("Mul64Fx2"); return;
       case Iop_Mul64F0x2: vex_printf("Mul64F0x2"); return;
 

+      case Iop_Recip32x2: vex_printf("Recip32x2"); return;
+      case Iop_Recip32Fx2:  vex_printf("Recip32Fx2"); return;

       case Iop_Recip32Fx4:  vex_printf("Recip32Fx4"); return;
       case Iop_Recip32Fx4:  vex_printf("Recip32Fx4"); return;

+      case Iop_Recip32x4:  vex_printf("Recip32x4"); return;

       case Iop_Recip32F0x4: vex_printf("Recip32F0x4"); return;
       case Iop_Recip64Fx2:  vex_printf("Recip64Fx2"); return;
       case Iop_Recip64F0x2: vex_printf("Recip64F0x2"); return;
       case Iop_Recip32F0x4: vex_printf("Recip32F0x4"); return;
       case Iop_Recip64Fx2:  vex_printf("Recip64Fx2"); return;
       case Iop_Recip64F0x2: vex_printf("Recip64F0x2"); return;

+      case Iop_Recps32Fx2:  vex_printf("VRecps32Fx2"); return;
+      case Iop_Recps32Fx4:  vex_printf("VRecps32Fx4"); return;
+      case Iop_Abs32Fx4:  vex_printf("Abs32Fx4"); return;
+      case Iop_Rsqrts32Fx4:  vex_printf("VRsqrts32Fx4"); return;
+      case Iop_Rsqrts32Fx2:  vex_printf("VRsqrts32Fx2"); return;

 
       case Iop_RSqrt32Fx4:  vex_printf("RSqrt32Fx4"); return;
       case Iop_RSqrt32F0x4: vex_printf("RSqrt32F0x4"); return;
 
       case Iop_RSqrt32Fx4:  vex_printf("RSqrt32Fx4"); return;
       case Iop_RSqrt32F0x4: vex_printf("RSqrt32F0x4"); return;


@@ -416,6 +556,7 @@ void ppIROp ( IROp op )
       case Iop_Sqrt64F0x2: vex_printf("Sqrt64F0x2"); return;
 
       case Iop_Sub32Fx4:  vex_printf("Sub32Fx4"); return;
       case Iop_Sqrt64F0x2: vex_printf("Sqrt64F0x2"); return;
 
       case Iop_Sub32Fx4:  vex_printf("Sub32Fx4"); return;

+      case Iop_Sub32Fx2:  vex_printf("Sub32Fx2"); return;

       case Iop_Sub32F0x4: vex_printf("Sub32F0x4"); return;
       case Iop_Sub64Fx2:  vex_printf("Sub64Fx2"); return;
       case Iop_Sub64F0x2: vex_printf("Sub64F0x2"); return;
       case Iop_Sub32F0x4: vex_printf("Sub32F0x4"); return;
       case Iop_Sub64Fx2:  vex_printf("Sub64Fx2"); return;
       case Iop_Sub64F0x2: vex_printf("Sub64F0x2"); return;


@@ -430,6 +571,9 @@ void ppIROp ( IROp op )
       case Iop_CmpLT64Fx2: vex_printf("CmpLT64Fx2"); return;
       case Iop_CmpLE64Fx2: vex_printf("CmpLE64Fx2"); return;
       case Iop_CmpUN64Fx2: vex_printf("CmpUN64Fx2"); return;
       case Iop_CmpLT64Fx2: vex_printf("CmpLT64Fx2"); return;
       case Iop_CmpLE64Fx2: vex_printf("CmpLE64Fx2"); return;
       case Iop_CmpUN64Fx2: vex_printf("CmpUN64Fx2"); return;

+      case Iop_CmpGT32Fx2: vex_printf("CmpGT32Fx2"); return;
+      case Iop_CmpEQ32Fx2: vex_printf("CmpEQ32Fx2"); return;
+      case Iop_CmpGE32Fx2: vex_printf("CmpGE32Fx2"); return;

 
       case Iop_CmpEQ32F0x4: vex_printf("CmpEQ32F0x4"); return;
       case Iop_CmpLT32F0x4: vex_printf("CmpLT32F0x4"); return;
 
       case Iop_CmpEQ32F0x4: vex_printf("CmpEQ32F0x4"); return;
       case Iop_CmpLT32F0x4: vex_printf("CmpLT32F0x4"); return;


@@ -440,6 +584,9 @@ void ppIROp ( IROp op )
       case Iop_CmpLE64F0x2: vex_printf("CmpLE64F0x2"); return;
       case Iop_CmpUN64F0x2: vex_printf("CmpUN64F0x2"); return;
 
       case Iop_CmpLE64F0x2: vex_printf("CmpLE64F0x2"); return;
       case Iop_CmpUN64F0x2: vex_printf("CmpUN64F0x2"); return;
 

+      case Iop_Neg32Fx4: vex_printf("Neg32Fx4"); return;
+      case Iop_Neg32Fx2: vex_printf("Neg32Fx2"); return;
+

       case Iop_V128to64:   vex_printf("V128to64");   return;
       case Iop_V128HIto64: vex_printf("V128HIto64"); return;
       case Iop_64HLtoV128: vex_printf("64HLtoV128"); return;
       case Iop_V128to64:   vex_printf("V128to64");   return;
       case Iop_V128HIto64: vex_printf("V128HIto64"); return;
       case Iop_64HLtoV128: vex_printf("64HLtoV128"); return;


@@ -454,6 +601,9 @@ void ppIROp ( IROp op )
       case Iop_Dup8x16: vex_printf("Dup8x16"); return;
       case Iop_Dup16x8: vex_printf("Dup16x8"); return;
       case Iop_Dup32x4: vex_printf("Dup32x4"); return;
       case Iop_Dup8x16: vex_printf("Dup8x16"); return;
       case Iop_Dup16x8: vex_printf("Dup16x8"); return;
       case Iop_Dup32x4: vex_printf("Dup32x4"); return;

+      case Iop_Dup8x8: vex_printf("Dup8x8"); return;
+      case Iop_Dup16x4: vex_printf("Dup16x4"); return;
+      case Iop_Dup32x2: vex_printf("Dup32x2"); return;

 
       case Iop_NotV128:    vex_printf("NotV128"); return;
       case Iop_AndV128:    vex_printf("AndV128"); return;
 
       case Iop_NotV128:    vex_printf("NotV128"); return;
       case Iop_AndV128:    vex_printf("AndV128"); return;


@@ -465,6 +615,10 @@ void ppIROp ( IROp op )
       case Iop_CmpNEZ32x4: vex_printf("CmpNEZ32x4"); return;
       case Iop_CmpNEZ64x2: vex_printf("CmpNEZ64x2"); return;
 
       case Iop_CmpNEZ32x4: vex_printf("CmpNEZ32x4"); return;
       case Iop_CmpNEZ64x2: vex_printf("CmpNEZ64x2"); return;
 

+      case Iop_Abs8x16: vex_printf("Abs8x16"); return;
+      case Iop_Abs16x8: vex_printf("Abs16x8"); return;
+      case Iop_Abs32x4: vex_printf("Abs32x4"); return;
+

       case Iop_Add8x16:   vex_printf("Add8x16"); return;
       case Iop_Add16x8:   vex_printf("Add16x8"); return;
       case Iop_Add32x4:   vex_printf("Add32x4"); return;
       case Iop_Add8x16:   vex_printf("Add8x16"); return;
       case Iop_Add16x8:   vex_printf("Add16x8"); return;
       case Iop_Add32x4:   vex_printf("Add32x4"); return;


@@ -475,6 +629,17 @@ void ppIROp ( IROp op )
       case Iop_QAdd8Sx16: vex_printf("QAdd8Sx16"); return;
       case Iop_QAdd16Sx8: vex_printf("QAdd16Sx8"); return;
       case Iop_QAdd32Sx4: vex_printf("QAdd32Sx4"); return;
       case Iop_QAdd8Sx16: vex_printf("QAdd8Sx16"); return;
       case Iop_QAdd16Sx8: vex_printf("QAdd16Sx8"); return;
       case Iop_QAdd32Sx4: vex_printf("QAdd32Sx4"); return;

+      case Iop_QAdd64Ux2: vex_printf("QAdd64Ux2"); return;
+      case Iop_QAdd64Sx2: vex_printf("QAdd64Sx2"); return;
+      case Iop_PwAdd8x16: vex_printf("PwAdd8x16"); return;
+      case Iop_PwAdd16x8: vex_printf("PwAdd16x8"); return;
+      case Iop_PwAdd32x4: vex_printf("PwAdd32x4"); return;
+      case Iop_PwAddL8Ux16: vex_printf("PwAddL8Ux16"); return;
+      case Iop_PwAddL16Ux8: vex_printf("PwAddL16Ux8"); return;
+      case Iop_PwAddL32Ux4: vex_printf("PwAddL32Ux4"); return;
+      case Iop_PwAddL8Sx16: vex_printf("PwAddL8Sx16"); return;
+      case Iop_PwAddL16Sx8: vex_printf("PwAddL16Sx8"); return;
+      case Iop_PwAddL32Sx4: vex_printf("PwAddL32Sx4"); return;

 
       case Iop_Sub8x16:   vex_printf("Sub8x16"); return;
       case Iop_Sub16x8:   vex_printf("Sub16x8"); return;
 
       case Iop_Sub8x16:   vex_printf("Sub8x16"); return;
       case Iop_Sub16x8:   vex_printf("Sub16x8"); return;


@@ -486,12 +651,28 @@ void ppIROp ( IROp op )
       case Iop_QSub8Sx16: vex_printf("QSub8Sx16"); return;
       case Iop_QSub16Sx8: vex_printf("QSub16Sx8"); return;
       case Iop_QSub32Sx4: vex_printf("QSub32Sx4"); return;
       case Iop_QSub8Sx16: vex_printf("QSub8Sx16"); return;
       case Iop_QSub16Sx8: vex_printf("QSub16Sx8"); return;
       case Iop_QSub32Sx4: vex_printf("QSub32Sx4"); return;

+      case Iop_QSub64Ux2: vex_printf("QSub64Ux2"); return;
+      case Iop_QSub64Sx2: vex_printf("QSub64Sx2"); return;

 
 

+      case Iop_Mul8x16:    vex_printf("Mul8x16"); return;

       case Iop_Mul16x8:    vex_printf("Mul16x8"); return;
       case Iop_Mul16x8:    vex_printf("Mul16x8"); return;

+      case Iop_Mul32x4:    vex_printf("Mul32x4"); return;
+      case Iop_Mull8Ux8:    vex_printf("Mull8Ux8"); return;
+      case Iop_Mull8Sx8:    vex_printf("Mull8Sx8"); return;
+      case Iop_Mull16Ux4:    vex_printf("Mull16Ux4"); return;
+      case Iop_Mull16Sx4:    vex_printf("Mull16Sx4"); return;
+      case Iop_Mull32Ux2:    vex_printf("Mull32Ux2"); return;
+      case Iop_Mull32Sx2:    vex_printf("Mull32Sx2"); return;
+      case Iop_PolynomialMul8x16: vex_printf("PolynomialMul8x16"); return;
+      case Iop_PolynomialMull8x8: vex_printf("PolynomialMull8x8"); return;

       case Iop_MulHi16Ux8: vex_printf("MulHi16Ux8"); return;
       case Iop_MulHi32Ux4: vex_printf("MulHi32Ux4"); return;
       case Iop_MulHi16Sx8: vex_printf("MulHi16Sx8"); return;
       case Iop_MulHi32Sx4: vex_printf("MulHi32Sx4"); return;
       case Iop_MulHi16Ux8: vex_printf("MulHi16Ux8"); return;
       case Iop_MulHi32Ux4: vex_printf("MulHi32Ux4"); return;
       case Iop_MulHi16Sx8: vex_printf("MulHi16Sx8"); return;
       case Iop_MulHi32Sx4: vex_printf("MulHi32Sx4"); return;

+      case Iop_QDMulHi16Sx8: vex_printf("QDMulHi16Sx8"); return;
+      case Iop_QDMulHi32Sx4: vex_printf("QDMulHi32Sx4"); return;
+      case Iop_QRDMulHi16Sx8: vex_printf("QRDMulHi16Sx8"); return;
+      case Iop_QRDMulHi32Sx4: vex_printf("QRDMulHi32Sx4"); return;

 
       case Iop_MullEven8Ux16: vex_printf("MullEven8Ux16"); return;
       case Iop_MullEven16Ux8: vex_printf("MullEven16Ux8"); return;
 
       case Iop_MullEven8Ux16: vex_printf("MullEven8Ux16"); return;
       case Iop_MullEven16Ux8: vex_printf("MullEven16Ux8"); return;


@@ -525,10 +706,19 @@ void ppIROp ( IROp op )
       case Iop_CmpGT8Sx16: vex_printf("CmpGT8Sx16"); return;
       case Iop_CmpGT16Sx8: vex_printf("CmpGT16Sx8"); return;
       case Iop_CmpGT32Sx4: vex_printf("CmpGT32Sx4"); return;
       case Iop_CmpGT8Sx16: vex_printf("CmpGT8Sx16"); return;
       case Iop_CmpGT16Sx8: vex_printf("CmpGT16Sx8"); return;
       case Iop_CmpGT32Sx4: vex_printf("CmpGT32Sx4"); return;

+      case Iop_CmpGT64Sx2: vex_printf("CmpGT64Sx2"); return;

       case Iop_CmpGT8Ux16: vex_printf("CmpGT8Ux16"); return;
       case Iop_CmpGT16Ux8: vex_printf("CmpGT16Ux8"); return;
       case Iop_CmpGT32Ux4: vex_printf("CmpGT32Ux4"); return;
 
       case Iop_CmpGT8Ux16: vex_printf("CmpGT8Ux16"); return;
       case Iop_CmpGT16Ux8: vex_printf("CmpGT16Ux8"); return;
       case Iop_CmpGT32Ux4: vex_printf("CmpGT32Ux4"); return;
 

+      case Iop_Cnt8x16: vex_printf("Cnt8x16"); return;
+      case Iop_Clz8Sx16: vex_printf("Clz8Sx16"); return;
+      case Iop_Clz16Sx8: vex_printf("Clz16Sx8"); return;
+      case Iop_Clz32Sx4: vex_printf("Clz32Sx4"); return;
+      case Iop_Cls8Sx16: vex_printf("Cls8Sx16"); return;
+      case Iop_Cls16Sx8: vex_printf("Cls16Sx8"); return;
+      case Iop_Cls32Sx4: vex_printf("Cls32Sx4"); return;
+

       case Iop_ShlV128: vex_printf("ShlV128"); return;
       case Iop_ShrV128: vex_printf("ShrV128"); return;
 
       case Iop_ShlV128: vex_printf("ShlV128"); return;
       case Iop_ShrV128: vex_printf("ShrV128"); return;
 


@@ -543,16 +733,44 @@ void ppIROp ( IROp op )
       case Iop_SarN8x16: vex_printf("SarN8x16"); return;
       case Iop_SarN16x8: vex_printf("SarN16x8"); return;
       case Iop_SarN32x4: vex_printf("SarN32x4"); return;
       case Iop_SarN8x16: vex_printf("SarN8x16"); return;
       case Iop_SarN16x8: vex_printf("SarN16x8"); return;
       case Iop_SarN32x4: vex_printf("SarN32x4"); return;

+      case Iop_SarN64x2: vex_printf("SarN64x2"); return;

 
       case Iop_Shl8x16: vex_printf("Shl8x16"); return;
       case Iop_Shl16x8: vex_printf("Shl16x8"); return;
       case Iop_Shl32x4: vex_printf("Shl32x4"); return;
 
       case Iop_Shl8x16: vex_printf("Shl8x16"); return;
       case Iop_Shl16x8: vex_printf("Shl16x8"); return;
       case Iop_Shl32x4: vex_printf("Shl32x4"); return;

+      case Iop_Shl64x2: vex_printf("Shl64x2"); return;
+      case Iop_QSal8x16: vex_printf("QSal8x16"); return;
+      case Iop_QSal16x8: vex_printf("QSal16x8"); return;
+      case Iop_QSal32x4: vex_printf("QSal32x4"); return;
+      case Iop_QSal64x2: vex_printf("QSal64x2"); return;
+      case Iop_QShl8x16: vex_printf("QShl8x16"); return;
+      case Iop_QShl16x8: vex_printf("QShl16x8"); return;
+      case Iop_QShl32x4: vex_printf("QShl32x4"); return;
+      case Iop_QShl64x2: vex_printf("QShl64x2"); return;
+      case Iop_QSalN8x16: vex_printf("QSalN8x16"); return;
+      case Iop_QSalN16x8: vex_printf("QSalN16x8"); return;
+      case Iop_QSalN32x4: vex_printf("QSalN32x4"); return;
+      case Iop_QSalN64x2: vex_printf("QSalN64x2"); return;
+      case Iop_QShlN8x16: vex_printf("QShlN8x16"); return;
+      case Iop_QShlN16x8: vex_printf("QShlN16x8"); return;
+      case Iop_QShlN32x4: vex_printf("QShlN32x4"); return;
+      case Iop_QShlN64x2: vex_printf("QShlN64x2"); return;
+      case Iop_QShlN8Sx16: vex_printf("QShlN8Sx16"); return;
+      case Iop_QShlN16Sx8: vex_printf("QShlN16Sx8"); return;
+      case Iop_QShlN32Sx4: vex_printf("QShlN32Sx4"); return;
+      case Iop_QShlN64Sx2: vex_printf("QShlN64Sx2"); return;

       case Iop_Shr8x16: vex_printf("Shr8x16"); return;
       case Iop_Shr16x8: vex_printf("Shr16x8"); return;
       case Iop_Shr32x4: vex_printf("Shr32x4"); return;
       case Iop_Shr8x16: vex_printf("Shr8x16"); return;
       case Iop_Shr16x8: vex_printf("Shr16x8"); return;
       case Iop_Shr32x4: vex_printf("Shr32x4"); return;

+      case Iop_Shr64x2: vex_printf("Shr64x2"); return;

       case Iop_Sar8x16: vex_printf("Sar8x16"); return;
       case Iop_Sar16x8: vex_printf("Sar16x8"); return;
       case Iop_Sar32x4: vex_printf("Sar32x4"); return;
       case Iop_Sar8x16: vex_printf("Sar8x16"); return;
       case Iop_Sar16x8: vex_printf("Sar16x8"); return;
       case Iop_Sar32x4: vex_printf("Sar32x4"); return;

+      case Iop_Sar64x2: vex_printf("Sar64x2"); return;
+      case Iop_Sal8x16: vex_printf("Sal8x16"); return;
+      case Iop_Sal16x8: vex_printf("Sal16x8"); return;
+      case Iop_Sal32x4: vex_printf("Sal32x4"); return;
+      case Iop_Sal64x2: vex_printf("Sal64x2"); return;

       case Iop_Rol8x16: vex_printf("Rol8x16"); return;
       case Iop_Rol16x8: vex_printf("Rol16x8"); return;
       case Iop_Rol32x4: vex_printf("Rol32x4"); return;
       case Iop_Rol8x16: vex_printf("Rol8x16"); return;
       case Iop_Rol16x8: vex_printf("Rol16x8"); return;
       case Iop_Rol32x4: vex_printf("Rol32x4"); return;


@@ -563,6 +781,24 @@ void ppIROp ( IROp op )
       case Iop_QNarrow32Ux4: vex_printf("QNarrow32Ux4"); return;
       case Iop_QNarrow16Sx8: vex_printf("QNarrow16Sx8"); return;
       case Iop_QNarrow32Sx4: vex_printf("QNarrow32Sx4"); return;
       case Iop_QNarrow32Ux4: vex_printf("QNarrow32Ux4"); return;
       case Iop_QNarrow16Sx8: vex_printf("QNarrow16Sx8"); return;
       case Iop_QNarrow32Sx4: vex_printf("QNarrow32Sx4"); return;

+      case Iop_Shorten16x8: vex_printf("Shorten16x8"); return;
+      case Iop_Shorten32x4: vex_printf("Shorten32x4"); return;
+      case Iop_Shorten64x2: vex_printf("Shorten64x2"); return;
+      case Iop_QShortenU16Ux8: vex_printf("QShortenU16Ux8"); return;
+      case Iop_QShortenU32Ux4: vex_printf("QShortenU32Ux4"); return;
+      case Iop_QShortenU64Ux2: vex_printf("QShortenU64Ux2"); return;
+      case Iop_QShortenS16Sx8: vex_printf("QShortenS16Sx8"); return;
+      case Iop_QShortenS32Sx4: vex_printf("QShortenS32Sx4"); return;
+      case Iop_QShortenS64Sx2: vex_printf("QShortenS64Sx2"); return;
+      case Iop_QShortenU16Sx8: vex_printf("QShortenU16Sx8"); return;
+      case Iop_QShortenU32Sx4: vex_printf("QShortenU32Sx4"); return;
+      case Iop_QShortenU64Sx2: vex_printf("QShortenU64Sx2"); return;
+      case Iop_Longen8Ux8: vex_printf("Longen8Ux8"); return;
+      case Iop_Longen16Ux4: vex_printf("Longen16Ux4"); return;
+      case Iop_Longen32Ux2: vex_printf("Longen32Ux2"); return;
+      case Iop_Longen8Sx8: vex_printf("Longen8Sx8"); return;
+      case Iop_Longen16Sx4: vex_printf("Longen16Sx4"); return;
+      case Iop_Longen32Sx2: vex_printf("Longen32Sx2"); return;

 
       case Iop_InterleaveHI8x16: vex_printf("InterleaveHI8x16"); return;
       case Iop_InterleaveHI16x8: vex_printf("InterleaveHI16x8"); return;
 
       case Iop_InterleaveHI8x16: vex_printf("InterleaveHI8x16"); return;
       case Iop_InterleaveHI16x8: vex_printf("InterleaveHI16x8"); return;


@@ -573,7 +809,51 @@ void ppIROp ( IROp op )
       case Iop_InterleaveLO32x4: vex_printf("InterleaveLO32x4"); return;
       case Iop_InterleaveLO64x2: vex_printf("InterleaveLO64x2"); return;
 
       case Iop_InterleaveLO32x4: vex_printf("InterleaveLO32x4"); return;
       case Iop_InterleaveLO64x2: vex_printf("InterleaveLO64x2"); return;
 

+      case Iop_CatOddLanes8x16: vex_printf("CatOddLanes8x16"); return;
+      case Iop_CatOddLanes16x8: vex_printf("CatOddLanes16x8"); return;
+      case Iop_CatOddLanes32x4: vex_printf("CatOddLanes32x4"); return;
+      case Iop_CatEvenLanes8x16: vex_printf("CatEvenLanes8x16"); return;
+      case Iop_CatEvenLanes16x8: vex_printf("CatEvenLanes16x8"); return;
+      case Iop_CatEvenLanes32x4: vex_printf("CatEvenLanes32x4"); return;
+
+      case Iop_InterleaveOddLanes8x16: vex_printf("InterleaveOddLanes8x16"); return;
+      case Iop_InterleaveOddLanes16x8: vex_printf("InterleaveOddLanes16x8"); return;
+      case Iop_InterleaveOddLanes32x4: vex_printf("InterleaveOddLanes32x4"); return;
+      case Iop_InterleaveEvenLanes8x16: vex_printf("InterleaveEvenLanes8x16"); return;
+      case Iop_InterleaveEvenLanes16x8: vex_printf("InterleaveEvenLanes16x8"); return;
+      case Iop_InterleaveEvenLanes32x4: vex_printf("InterleaveEvenLanes32x4"); return;
+
+      case Iop_GetElem8x16: vex_printf("GetElem8x16"); return;
+      case Iop_GetElem16x8: vex_printf("GetElem16x8"); return;
+      case Iop_GetElem32x4: vex_printf("GetElem32x4"); return;
+      case Iop_GetElem64x2: vex_printf("GetElem64x2"); return;
+
+      case Iop_GetElem8x8: vex_printf("GetElem8x8"); return;
+      case Iop_GetElem16x4: vex_printf("GetElem16x4"); return;
+      case Iop_GetElem32x2: vex_printf("GetElem32x2"); return;
+      case Iop_SetElem8x8: vex_printf("SetElem8x8"); return;
+      case Iop_SetElem16x4: vex_printf("SetElem16x4"); return;
+      case Iop_SetElem32x2: vex_printf("SetElem32x2"); return;
+
+      case Iop_Extract64: vex_printf("Extract64"); return;
+      case Iop_ExtractV128: vex_printf("ExtractV128"); return;
+

       case Iop_Perm8x16: vex_printf("Perm8x16"); return;
       case Iop_Perm8x16: vex_printf("Perm8x16"); return;

+      case Iop_Reverse16_8x16: vex_printf("Reverse16_8x16"); return;
+      case Iop_Reverse32_8x16: vex_printf("Reverse32_8x16"); return;
+      case Iop_Reverse32_16x8: vex_printf("Reverse32_16x8"); return;
+      case Iop_Reverse64_8x16: vex_printf("Reverse64_8x16"); return;
+      case Iop_Reverse64_16x8: vex_printf("Reverse64_16x8"); return;
+      case Iop_Reverse64_32x4: vex_printf("Reverse64_32x4"); return;
+
+      case Iop_F32ToFixed32Ux4_RZ: vex_printf("F32ToFixed32Ux4_RZ"); return;
+      case Iop_F32ToFixed32Sx4_RZ: vex_printf("F32ToFixed32Sx4_RZ"); return;
+      case Iop_Fixed32UToF32x4_RN: vex_printf("Fixed32UToF32x4_RN"); return;
+      case Iop_Fixed32SToF32x4_RN: vex_printf("Fixed32SToF32x4_RN"); return;
+      case Iop_F32ToFixed32Ux2_RZ: vex_printf("F32ToFixed32Ux2_RZ"); return;
+      case Iop_F32ToFixed32Sx2_RZ: vex_printf("F32ToFixed32Sx2_RZ"); return;
+      case Iop_Fixed32UToF32x2_RN: vex_printf("Fixed32UToF32x2_RN"); return;
+      case Iop_Fixed32SToF32x2_RN: vex_printf("Fixed32SToF32x2_RN"); return;

 
       default: vpanic("ppIROp(1)");
    }
 
       default: vpanic("ppIROp(1)");
    }


@@ -1189,6 +1469,21 @@ IRExpr** mkIRExprVec_7 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3,
    vec[7] = NULL;
    return vec;
 }
    vec[7] = NULL;
    return vec;
 }

+IRExpr** mkIRExprVec_8 ( IRExpr* arg1, IRExpr* arg2, IRExpr* arg3,
+                         IRExpr* arg4, IRExpr* arg5, IRExpr* arg6,
+                         IRExpr* arg7, IRExpr* arg8 ) {
+   IRExpr** vec = LibVEX_Alloc(9 * sizeof(IRExpr*));
+   vec[0] = arg1;
+   vec[1] = arg2;
+   vec[2] = arg3;
+   vec[3] = arg4;
+   vec[4] = arg5;
+   vec[5] = arg6;
+   vec[6] = arg7;
+   vec[7] = arg8;
+   vec[8] = NULL;
+   return vec;
+}

 
 
 /* Constructors -- IRDirty */
 
 
 /* Constructors -- IRDirty */


@@ -1632,29 +1927,67 @@ void typeOfPrimop ( IROp op,
       case Iop_CmpORD64S:
       case Iop_Avg8Ux8: case Iop_Avg16Ux4:
       case Iop_Add8x8: case Iop_Add16x4: case Iop_Add32x2:
       case Iop_CmpORD64S:
       case Iop_Avg8Ux8: case Iop_Avg16Ux4:
       case Iop_Add8x8: case Iop_Add16x4: case Iop_Add32x2:

+      case Iop_Add32Fx2: case Iop_Sub32Fx2:

       case Iop_CmpEQ8x8: case Iop_CmpEQ16x4: case Iop_CmpEQ32x2:
       case Iop_CmpGT8Sx8: case Iop_CmpGT16Sx4: case Iop_CmpGT32Sx2:
       case Iop_CmpEQ8x8: case Iop_CmpEQ16x4: case Iop_CmpEQ32x2:
       case Iop_CmpGT8Sx8: case Iop_CmpGT16Sx4: case Iop_CmpGT32Sx2:

+      case Iop_CmpGT8Ux8: case Iop_CmpGT16Ux4: case Iop_CmpGT32Ux2:
+      case Iop_CmpGT32Fx2: case Iop_CmpEQ32Fx2: case Iop_CmpGE32Fx2:

       case Iop_InterleaveHI8x8: case Iop_InterleaveLO8x8:
       case Iop_InterleaveHI16x4: case Iop_InterleaveLO16x4:
       case Iop_InterleaveHI32x2: case Iop_InterleaveLO32x2:
       case Iop_InterleaveHI8x8: case Iop_InterleaveLO8x8:
       case Iop_InterleaveHI16x4: case Iop_InterleaveLO16x4:
       case Iop_InterleaveHI32x2: case Iop_InterleaveLO32x2:

+      case Iop_CatOddLanes8x8: case Iop_CatEvenLanes8x8:

       case Iop_CatOddLanes16x4: case Iop_CatEvenLanes16x4:
       case Iop_CatOddLanes16x4: case Iop_CatEvenLanes16x4:

+      case Iop_InterleaveOddLanes8x8: case Iop_InterleaveEvenLanes8x8:
+      case Iop_InterleaveOddLanes16x4: case Iop_InterleaveEvenLanes16x4:

       case Iop_Perm8x8:
       case Iop_Perm8x8:

-      case Iop_Max8Ux8: case Iop_Max16Sx4:
-      case Iop_Min8Ux8: case Iop_Min16Sx4:
-      case Iop_Mul16x4: case Iop_Mul32x2:
+      case Iop_Max8Ux8: case Iop_Max16Ux4: case Iop_Max32Ux2:
+      case Iop_Max8Sx8: case Iop_Max16Sx4: case Iop_Max32Sx2:
+      case Iop_Max32Fx2: case Iop_Min32Fx2:
+      case Iop_PwMax32Fx2: case Iop_PwMin32Fx2:
+      case Iop_Min8Ux8: case Iop_Min16Ux4: case Iop_Min32Ux2:
+      case Iop_Min8Sx8: case Iop_Min16Sx4: case Iop_Min32Sx2:
+      case Iop_PwMax8Ux8: case Iop_PwMax16Ux4: case Iop_PwMax32Ux2:
+      case Iop_PwMax8Sx8: case Iop_PwMax16Sx4: case Iop_PwMax32Sx2:
+      case Iop_PwMin8Ux8: case Iop_PwMin16Ux4: case Iop_PwMin32Ux2:
+      case Iop_PwMin8Sx8: case Iop_PwMin16Sx4: case Iop_PwMin32Sx2:
+      case Iop_Mul8x8: case Iop_Mul16x4: case Iop_Mul32x2:
+      case Iop_Mul32Fx2:
+      case Iop_PolynomialMul8x8:

       case Iop_MulHi16Sx4: case Iop_MulHi16Ux4:
       case Iop_MulHi16Sx4: case Iop_MulHi16Ux4:

+      case Iop_QDMulHi16Sx4: case Iop_QDMulHi32Sx2:
+      case Iop_QRDMulHi16Sx4: case Iop_QRDMulHi32Sx2:

       case Iop_QAdd8Sx8: case Iop_QAdd16Sx4:
       case Iop_QAdd8Sx8: case Iop_QAdd16Sx4:

+      case Iop_QAdd32Sx2: case Iop_QAdd64Sx1:

       case Iop_QAdd8Ux8: case Iop_QAdd16Ux4:
       case Iop_QAdd8Ux8: case Iop_QAdd16Ux4:

+      case Iop_QAdd32Ux2: case Iop_QAdd64Ux1:
+      case Iop_PwAdd8x8: case Iop_PwAdd16x4: case Iop_PwAdd32x2:
+      case Iop_PwAdd32Fx2:

       case Iop_QNarrow32Sx2:
       case Iop_QNarrow16Sx4: case Iop_QNarrow16Ux4:
       case Iop_Sub8x8: case Iop_Sub16x4: case Iop_Sub32x2:
       case Iop_QSub8Sx8: case Iop_QSub16Sx4:
       case Iop_QNarrow32Sx2:
       case Iop_QNarrow16Sx4: case Iop_QNarrow16Ux4:
       case Iop_Sub8x8: case Iop_Sub16x4: case Iop_Sub32x2:
       case Iop_QSub8Sx8: case Iop_QSub16Sx4:

+      case Iop_QSub32Sx2: case Iop_QSub64Sx1:

       case Iop_QSub8Ux8: case Iop_QSub16Ux4:
       case Iop_QSub8Ux8: case Iop_QSub16Ux4:

+      case Iop_QSub32Ux2: case Iop_QSub64Ux1:
+      case Iop_Shl8x8: case Iop_Shl16x4: case Iop_Shl32x2:
+      case Iop_Shr8x8: case Iop_Shr16x4: case Iop_Shr32x2:
+      case Iop_Sar8x8: case Iop_Sar16x4: case Iop_Sar32x2:
+      case Iop_Sal8x8: case Iop_Sal16x4: case Iop_Sal32x2: case Iop_Sal64x1:
+      case Iop_QShl8x8: case Iop_QShl16x4: case Iop_QShl32x2: case Iop_QShl64x1:
+      case Iop_QSal8x8: case Iop_QSal16x4: case Iop_QSal32x2: case Iop_QSal64x1:
+      case Iop_Recps32Fx2:
+      case Iop_Rsqrts32Fx2:

          BINARY(Ity_I64,Ity_I64, Ity_I64);
 
       case Iop_ShlN32x2: case Iop_ShlN16x4: case Iop_ShlN8x8:
          BINARY(Ity_I64,Ity_I64, Ity_I64);
 
       case Iop_ShlN32x2: case Iop_ShlN16x4: case Iop_ShlN8x8:

-      case Iop_ShrN32x2: case Iop_ShrN16x4:
+      case Iop_ShrN32x2: case Iop_ShrN16x4: case Iop_ShrN8x8:

       case Iop_SarN32x2: case Iop_SarN16x4: case Iop_SarN8x8:
       case Iop_SarN32x2: case Iop_SarN16x4: case Iop_SarN8x8:

+      case Iop_QShlN8x8: case Iop_QShlN16x4:
+      case Iop_QShlN32x2: case Iop_QShlN64x1:
+      case Iop_QShlN8Sx8: case Iop_QShlN16Sx4:
+      case Iop_QShlN32Sx2: case Iop_QShlN64Sx1:
+      case Iop_QSalN8x8: case Iop_QSalN16x4:
+      case Iop_QSalN32x2: case Iop_QSalN64x1:

          BINARY(Ity_I64,Ity_I8, Ity_I64);
 
       case Iop_Shl8: case Iop_Shr8: case Iop_Sar8:
          BINARY(Ity_I64,Ity_I8, Ity_I64);
 
       case Iop_Shl8: case Iop_Shr8: case Iop_Sar8:


@@ -1675,6 +2008,22 @@ void typeOfPrimop ( IROp op,
 
       case Iop_Not64:
       case Iop_CmpNEZ32x2: case Iop_CmpNEZ16x4: case Iop_CmpNEZ8x8:
 
       case Iop_Not64:
       case Iop_CmpNEZ32x2: case Iop_CmpNEZ16x4: case Iop_CmpNEZ8x8:

+      case Iop_Cnt8x8:
+      case Iop_Clz8Sx8: case Iop_Clz16Sx4: case Iop_Clz32Sx2:
+      case Iop_Cls8Sx8: case Iop_Cls16Sx4: case Iop_Cls32Sx2:
+      case Iop_PwAddL8Ux8: case Iop_PwAddL16Ux4: case Iop_PwAddL32Ux2:
+      case Iop_PwAddL8Sx8: case Iop_PwAddL16Sx4: case Iop_PwAddL32Sx2:
+      case Iop_Reverse64_8x8: case Iop_Reverse64_16x4: case Iop_Reverse64_32x2:
+      case Iop_Reverse32_8x8: case Iop_Reverse32_16x4:
+      case Iop_Reverse16_8x8:
+      case Iop_FtoI32Sx2_RZ: case Iop_FtoI32Ux2_RZ:
+      case Iop_I32StoFx2: case Iop_I32UtoFx2:
+      case Iop_Recip32x2: case Iop_Recip32Fx2:
+      case Iop_Abs32Fx2:
+      case Iop_Rsqrte32Fx2:
+      case Iop_Rsqrte32x2:
+      case Iop_Neg32Fx2:
+      case Iop_Abs8x8: case Iop_Abs16x4: case Iop_Abs32x2:

          UNARY(Ity_I64, Ity_I64);
 
       case Iop_CmpEQ8: case Iop_CmpNE8:
          UNARY(Ity_I64, Ity_I64);
 
       case Iop_CmpEQ8: case Iop_CmpNE8:


@@ -1804,6 +2153,7 @@ void typeOfPrimop ( IROp op,
          BINARY(ity_RMode,Ity_F64, Ity_F64);
 
       case Iop_SqrtF32:
          BINARY(ity_RMode,Ity_F64, Ity_F64);
 
       case Iop_SqrtF32:

+      case Iop_RoundF32toInt:

          BINARY(ity_RMode,Ity_F32, Ity_F32);
 
       case Iop_CmpF64:
          BINARY(ity_RMode,Ity_F32, Ity_F32);
 
       case Iop_CmpF64:


@@ -1859,16 +2209,31 @@ void typeOfPrimop ( IROp op,
       case Iop_I32StoFx4:
       case Iop_QFtoI32Ux4_RZ:
       case Iop_QFtoI32Sx4_RZ:
       case Iop_I32StoFx4:
       case Iop_QFtoI32Ux4_RZ:
       case Iop_QFtoI32Sx4_RZ:

+      case Iop_FtoI32Ux4_RZ:
+      case Iop_FtoI32Sx4_RZ:

       case Iop_RoundF32x4_RM:
       case Iop_RoundF32x4_RP:
       case Iop_RoundF32x4_RN:
       case Iop_RoundF32x4_RZ:
       case Iop_RoundF32x4_RM:
       case Iop_RoundF32x4_RP:
       case Iop_RoundF32x4_RN:
       case Iop_RoundF32x4_RZ:

+      case Iop_Abs32Fx4:
+      case Iop_Rsqrte32Fx4:
+      case Iop_Rsqrte32x4:

          UNARY(Ity_V128, Ity_V128);
 
       case Iop_64HLtoV128: BINARY(Ity_I64,Ity_I64, Ity_V128);
          UNARY(Ity_V128, Ity_V128);
 
       case Iop_64HLtoV128: BINARY(Ity_I64,Ity_I64, Ity_V128);

-      case Iop_V128to64: case Iop_V128HIto64: 
+      case Iop_V128to64: case Iop_V128HIto64:
+      case Iop_Shorten16x8: case Iop_Shorten32x4: case Iop_Shorten64x2:
+      case Iop_QShortenU16Ux8: case Iop_QShortenU32Ux4: case Iop_QShortenU64Ux2:
+      case Iop_QShortenS16Sx8: case Iop_QShortenS32Sx4: case Iop_QShortenS64Sx2:
+      case Iop_QShortenU16Sx8: case Iop_QShortenU32Sx4: case Iop_QShortenU64Sx2:
+      case Iop_F32toF16x4:

          UNARY(Ity_V128, Ity_I64);
 
          UNARY(Ity_V128, Ity_I64);
 

+      case Iop_Longen8Ux8: case Iop_Longen16Ux4: case Iop_Longen32Ux2:
+      case Iop_Longen8Sx8: case Iop_Longen16Sx4: case Iop_Longen32Sx2:
+      case Iop_F16toF32x4:
+         UNARY(Ity_I64, Ity_V128);
+

       case Iop_V128to32:    UNARY(Ity_V128, Ity_I32);
       case Iop_32UtoV128:   UNARY(Ity_I32, Ity_V128);
       case Iop_64UtoV128:   UNARY(Ity_I64, Ity_V128);
       case Iop_V128to32:    UNARY(Ity_V128, Ity_I32);
       case Iop_32UtoV128:   UNARY(Ity_I32, Ity_V128);
       case Iop_64UtoV128:   UNARY(Ity_I64, Ity_V128);


@@ -1878,6 +2243,9 @@ void typeOfPrimop ( IROp op,
       case Iop_Dup8x16: UNARY(Ity_I8, Ity_V128);
       case Iop_Dup16x8: UNARY(Ity_I16, Ity_V128);
       case Iop_Dup32x4: UNARY(Ity_I32, Ity_V128);
       case Iop_Dup8x16: UNARY(Ity_I8, Ity_V128);
       case Iop_Dup16x8: UNARY(Ity_I16, Ity_V128);
       case Iop_Dup32x4: UNARY(Ity_I32, Ity_V128);

+      case Iop_Dup8x8:  UNARY(Ity_I8, Ity_I64);
+      case Iop_Dup16x4: UNARY(Ity_I16, Ity_I64);
+      case Iop_Dup32x2: UNARY(Ity_I32, Ity_I64);

 
       case Iop_CmpEQ32Fx4: case Iop_CmpLT32Fx4:
       case Iop_CmpEQ64Fx2: case Iop_CmpLT64Fx2:
 
       case Iop_CmpEQ32Fx4: case Iop_CmpLT32Fx4:
       case Iop_CmpEQ64Fx2: case Iop_CmpLT64Fx2:


@@ -1893,6 +2261,7 @@ void typeOfPrimop ( IROp op,
       case Iop_Div32Fx4: case Iop_Div32F0x4:
       case Iop_Div64Fx2: case Iop_Div64F0x2:
       case Iop_Max32Fx4: case Iop_Max32F0x4:
       case Iop_Div32Fx4: case Iop_Div32F0x4:
       case Iop_Div64Fx2: case Iop_Div64F0x2:
       case Iop_Max32Fx4: case Iop_Max32F0x4:

+      case Iop_PwMax32Fx4: case Iop_PwMin32Fx4:

       case Iop_Max64Fx2: case Iop_Max64F0x2:
       case Iop_Min32Fx4: case Iop_Min32F0x4:
       case Iop_Min64Fx2: case Iop_Min64F0x2:
       case Iop_Max64Fx2: case Iop_Max64F0x2:
       case Iop_Min32Fx4: case Iop_Min32F0x4:
       case Iop_Min64Fx2: case Iop_Min64F0x2:


@@ -1903,15 +2272,23 @@ void typeOfPrimop ( IROp op,
       case Iop_AndV128: case Iop_OrV128: case Iop_XorV128:
       case Iop_Add8x16:   case Iop_Add16x8:   
       case Iop_Add32x4:   case Iop_Add64x2:
       case Iop_AndV128: case Iop_OrV128: case Iop_XorV128:
       case Iop_Add8x16:   case Iop_Add16x8:   
       case Iop_Add32x4:   case Iop_Add64x2:

-      case Iop_QAdd8Ux16: case Iop_QAdd16Ux8: case Iop_QAdd32Ux4:
-      case Iop_QAdd8Sx16: case Iop_QAdd16Sx8: case Iop_QAdd32Sx4:
+      case Iop_QAdd8Ux16: case Iop_QAdd16Ux8:
+      case Iop_QAdd32Ux4: //case Iop_QAdd64Ux2:
+      case Iop_QAdd8Sx16: case Iop_QAdd16Sx8:
+      case Iop_QAdd32Sx4: case Iop_QAdd64Sx2:
+      case Iop_PwAdd8x16: case Iop_PwAdd16x8: case Iop_PwAdd32x4:

       case Iop_Sub8x16:   case Iop_Sub16x8:
       case Iop_Sub32x4:   case Iop_Sub64x2:
       case Iop_Sub8x16:   case Iop_Sub16x8:
       case Iop_Sub32x4:   case Iop_Sub64x2:

-      case Iop_QSub8Ux16: case Iop_QSub16Ux8: case Iop_QSub32Ux4:
-      case Iop_QSub8Sx16: case Iop_QSub16Sx8: case Iop_QSub32Sx4:
-      case Iop_Mul16x8:
+      case Iop_QSub8Ux16: case Iop_QSub16Ux8:
+      case Iop_QSub32Ux4: //case Iop_QSub64Ux2:
+      case Iop_QSub8Sx16: case Iop_QSub16Sx8:
+      case Iop_QSub32Sx4: case Iop_QSub64Sx2:
+      case Iop_Mul8x16: case Iop_Mul16x8: case Iop_Mul32x4:
+      case Iop_PolynomialMul8x16:

       case Iop_MulHi16Ux8: case Iop_MulHi32Ux4: 
       case Iop_MulHi16Sx8: case Iop_MulHi32Sx4: 
       case Iop_MulHi16Ux8: case Iop_MulHi32Ux4: 
       case Iop_MulHi16Sx8: case Iop_MulHi32Sx4: 

+      case Iop_QDMulHi16Sx8: case Iop_QDMulHi32Sx4:
+      case Iop_QRDMulHi16Sx8: case Iop_QRDMulHi32Sx4:

       case Iop_MullEven8Ux16: case Iop_MullEven16Ux8:
       case Iop_MullEven8Sx16: case Iop_MullEven16Sx8:
       case Iop_Avg8Ux16: case Iop_Avg16Ux8: case Iop_Avg32Ux4:
       case Iop_MullEven8Ux16: case Iop_MullEven16Ux8:
       case Iop_MullEven8Sx16: case Iop_MullEven16Sx8:
       case Iop_Avg8Ux16: case Iop_Avg16Ux8: case Iop_Avg32Ux4:


@@ -1922,23 +2299,42 @@ void typeOfPrimop ( IROp op,
       case Iop_Min8Ux16: case Iop_Min16Ux8: case Iop_Min32Ux4:
       case Iop_CmpEQ8x16:  case Iop_CmpEQ16x8:  case Iop_CmpEQ32x4:
       case Iop_CmpGT8Sx16: case Iop_CmpGT16Sx8: case Iop_CmpGT32Sx4:
       case Iop_Min8Ux16: case Iop_Min16Ux8: case Iop_Min32Ux4:
       case Iop_CmpEQ8x16:  case Iop_CmpEQ16x8:  case Iop_CmpEQ32x4:
       case Iop_CmpGT8Sx16: case Iop_CmpGT16Sx8: case Iop_CmpGT32Sx4:

+      case Iop_CmpGT64Sx2:

       case Iop_CmpGT8Ux16: case Iop_CmpGT16Ux8: case Iop_CmpGT32Ux4:
       case Iop_CmpGT8Ux16: case Iop_CmpGT16Ux8: case Iop_CmpGT32Ux4:

-      case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4:
-      case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4:
-      case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4:
+      case Iop_Shl8x16: case Iop_Shl16x8: case Iop_Shl32x4: case Iop_Shl64x2:
+      case Iop_QShl8x16: case Iop_QShl16x8: case Iop_QShl32x4: case Iop_QShl64x2:
+      case Iop_QSal8x16: case Iop_QSal16x8: case Iop_QSal32x4: case Iop_QSal64x2:
+      case Iop_Shr8x16: case Iop_Shr16x8: case Iop_Shr32x4: case Iop_Shr64x2:
+      case Iop_Sar8x16: case Iop_Sar16x8: case Iop_Sar32x4: case Iop_Sar64x2:
+      case Iop_Sal8x16: case Iop_Sal16x8: case Iop_Sal32x4: case Iop_Sal64x2:

       case Iop_Rol8x16: case Iop_Rol16x8: case Iop_Rol32x4:
       case Iop_QNarrow16Ux8: case Iop_QNarrow32Ux4:
       case Iop_QNarrow16Sx8: case Iop_QNarrow32Sx4:
       case Iop_Narrow16x8:   case Iop_Narrow32x4:
       case Iop_InterleaveHI8x16: case Iop_InterleaveHI16x8:
       case Iop_InterleaveHI32x4: case Iop_InterleaveHI64x2:
       case Iop_Rol8x16: case Iop_Rol16x8: case Iop_Rol32x4:
       case Iop_QNarrow16Ux8: case Iop_QNarrow32Ux4:
       case Iop_QNarrow16Sx8: case Iop_QNarrow32Sx4:
       case Iop_Narrow16x8:   case Iop_Narrow32x4:
       case Iop_InterleaveHI8x16: case Iop_InterleaveHI16x8:
       case Iop_InterleaveHI32x4: case Iop_InterleaveHI64x2:

-      case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8: 
+      case Iop_InterleaveLO8x16: case Iop_InterleaveLO16x8:

       case Iop_InterleaveLO32x4: case Iop_InterleaveLO64x2:
       case Iop_InterleaveLO32x4: case Iop_InterleaveLO64x2:

+      case Iop_CatOddLanes8x16: case Iop_CatEvenLanes8x16:
+      case Iop_CatOddLanes16x8: case Iop_CatEvenLanes16x8:
+      case Iop_CatOddLanes32x4: case Iop_CatEvenLanes32x4:
+      case Iop_InterleaveOddLanes8x16: case Iop_InterleaveEvenLanes8x16:
+      case Iop_InterleaveOddLanes16x8: case Iop_InterleaveEvenLanes16x8:
+      case Iop_InterleaveOddLanes32x4: case Iop_InterleaveEvenLanes32x4:

       case Iop_Perm8x16:
       case Iop_Perm8x16:

+      case Iop_Recps32Fx4:
+      case Iop_Rsqrts32Fx4:

          BINARY(Ity_V128,Ity_V128, Ity_V128);
 
          BINARY(Ity_V128,Ity_V128, Ity_V128);
 

+      case Iop_PolynomialMull8x8:
+      case Iop_Mull8Ux8: case Iop_Mull8Sx8:
+      case Iop_Mull16Ux4: case Iop_Mull16Sx4:
+      case Iop_Mull32Ux2: case Iop_Mull32Sx2:
+         BINARY(Ity_I64, Ity_I64, Ity_V128);
+

       case Iop_NotV128:
       case Iop_Recip32Fx4: case Iop_Recip32F0x4:
       case Iop_NotV128:
       case Iop_Recip32Fx4: case Iop_Recip32F0x4:

+      case Iop_Recip32x4:

       case Iop_Recip64Fx2: case Iop_Recip64F0x2:
       case Iop_RSqrt32Fx4: case Iop_RSqrt32F0x4:
       case Iop_RSqrt64Fx2: case Iop_RSqrt64F0x2:
       case Iop_Recip64Fx2: case Iop_Recip64F0x2:
       case Iop_RSqrt32Fx4: case Iop_RSqrt32F0x4:
       case Iop_RSqrt64Fx2: case Iop_RSqrt64F0x2:


@@ -1946,6 +2342,16 @@ void typeOfPrimop ( IROp op,
       case Iop_Sqrt64Fx2:  case Iop_Sqrt64F0x2:
       case Iop_CmpNEZ8x16: case Iop_CmpNEZ16x8:
       case Iop_CmpNEZ32x4: case Iop_CmpNEZ64x2:
       case Iop_Sqrt64Fx2:  case Iop_Sqrt64F0x2:
       case Iop_CmpNEZ8x16: case Iop_CmpNEZ16x8:
       case Iop_CmpNEZ32x4: case Iop_CmpNEZ64x2:

+      case Iop_Cnt8x16:
+      case Iop_Clz8Sx16: case Iop_Clz16Sx8: case Iop_Clz32Sx4:
+      case Iop_Cls8Sx16: case Iop_Cls16Sx8: case Iop_Cls32Sx4:
+      case Iop_PwAddL8Ux16: case Iop_PwAddL16Ux8: case Iop_PwAddL32Ux4:
+      case Iop_PwAddL8Sx16: case Iop_PwAddL16Sx8: case Iop_PwAddL32Sx4:
+      case Iop_Reverse64_8x16: case Iop_Reverse64_16x8: case Iop_Reverse64_32x4:
+      case Iop_Reverse32_8x16: case Iop_Reverse32_16x8:
+      case Iop_Reverse16_8x16:
+      case Iop_Neg32Fx4:
+      case Iop_Abs8x16: case Iop_Abs16x8: case Iop_Abs32x4:

          UNARY(Ity_V128, Ity_V128);
 
       case Iop_ShlV128: case Iop_ShrV128:
          UNARY(Ity_V128, Ity_V128);
 
       case Iop_ShlV128: case Iop_ShrV128:


@@ -1953,9 +2359,57 @@ void typeOfPrimop ( IROp op,
       case Iop_ShlN32x4: case Iop_ShlN64x2:
       case Iop_ShrN8x16: case Iop_ShrN16x8: 
       case Iop_ShrN32x4: case Iop_ShrN64x2:
       case Iop_ShlN32x4: case Iop_ShlN64x2:
       case Iop_ShrN8x16: case Iop_ShrN16x8: 
       case Iop_ShrN32x4: case Iop_ShrN64x2:

-      case Iop_SarN8x16: case Iop_SarN16x8: case Iop_SarN32x4:
+      case Iop_SarN8x16: case Iop_SarN16x8:
+      case Iop_SarN32x4: case Iop_SarN64x2:
+      case Iop_QShlN8x16: case Iop_QShlN16x8:
+      case Iop_QShlN32x4: case Iop_QShlN64x2:
+      case Iop_QShlN8Sx16: case Iop_QShlN16Sx8:
+      case Iop_QShlN32Sx4: case Iop_QShlN64Sx2:
+      case Iop_QSalN8x16: case Iop_QSalN16x8:
+      case Iop_QSalN32x4: case Iop_QSalN64x2:

          BINARY(Ity_V128,Ity_I8, Ity_V128);
 
          BINARY(Ity_V128,Ity_I8, Ity_V128);
 

+      case Iop_F32ToFixed32Ux4_RZ:
+      case Iop_F32ToFixed32Sx4_RZ:
+      case Iop_Fixed32UToF32x4_RN:
+      case Iop_Fixed32SToF32x4_RN:
+         BINARY(Ity_V128, Ity_I8, Ity_V128);
+
+      case Iop_F32ToFixed32Ux2_RZ:
+      case Iop_F32ToFixed32Sx2_RZ:
+      case Iop_Fixed32UToF32x2_RN:
+      case Iop_Fixed32SToF32x2_RN:
+         BINARY(Ity_I64, Ity_I8, Ity_I64);
+
+      case Iop_GetElem8x16:
+         BINARY(Ity_V128, Ity_I8, Ity_I8);
+      case Iop_GetElem16x8:
+         BINARY(Ity_V128, Ity_I8, Ity_I16);
+      case Iop_GetElem32x4:
+         BINARY(Ity_V128, Ity_I8, Ity_I32);
+      case Iop_GetElem64x2:
+         BINARY(Ity_V128, Ity_I8, Ity_I64);
+      case Iop_GetElem8x8:
+         BINARY(Ity_I64, Ity_I8, Ity_I8);
+      case Iop_GetElem16x4:
+         BINARY(Ity_I64, Ity_I8, Ity_I16);
+      case Iop_GetElem32x2:
+         BINARY(Ity_I64, Ity_I8, Ity_I32);
+      case Iop_SetElem8x8:
+         TERNARY(Ity_I64, Ity_I8, Ity_I8, Ity_I64);
+      case Iop_SetElem16x4:
+         TERNARY(Ity_I64, Ity_I8, Ity_I16, Ity_I64);
+      case Iop_SetElem32x2:
+         TERNARY(Ity_I64, Ity_I8, Ity_I32, Ity_I64);
+
+      case Iop_Extract64:
+         TERNARY(Ity_I64, Ity_I64, Ity_I8, Ity_I64);
+      case Iop_ExtractV128:
+         TERNARY(Ity_V128, Ity_V128, Ity_I8, Ity_V128);
+
+      case Iop_QDMulLong16Sx4: case Iop_QDMulLong32Sx2:
+         BINARY(Ity_I64, Ity_I64, Ity_V128);
+

       default:
          ppIROp(op);
          vpanic("typeOfPrimop");
       default:
          ppIROp(op);
          vpanic("typeOfPrimop");

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_opt.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_opt.c
index 2b08efd37b90060026ce13430016532a883c2674..5696e22d5709d533f0c854a2f36f23b4c68cf5d2 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_opt.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_opt.c
@@ -931,6 +931,7 @@ static IRExpr* mkZeroForXor ( IROp op )
    switch (op) {
       case Iop_Xor8:  return IRExpr_Const(IRConst_U8(0));
       case Iop_Xor16: return IRExpr_Const(IRConst_U16(0));
    switch (op) {
       case Iop_Xor8:  return IRExpr_Const(IRConst_U8(0));
       case Iop_Xor16: return IRExpr_Const(IRConst_U16(0));

+      case Iop_Sub32:

       case Iop_Xor32: return IRExpr_Const(IRConst_U32(0));
       case Iop_Xor64: return IRExpr_Const(IRConst_U64(0));
       case Iop_XorV128: return IRExpr_Const(IRConst_V128(0));
       case Iop_Xor32: return IRExpr_Const(IRConst_U32(0));
       case Iop_Xor64: return IRExpr_Const(IRConst_U64(0));
       case Iop_XorV128: return IRExpr_Const(IRConst_V128(0));


@@ -1078,7 +1079,13 @@ static IRExpr* fold_Expr ( IRExpr* e )
                     0xFFFFFFFFULL 
                     & e->Iex.Unop.arg->Iex.Const.con->Ico.U32));
             break;
                     0xFFFFFFFFULL 
                     & e->Iex.Unop.arg->Iex.Const.con->Ico.U32));
             break;

-
+         case Iop_32Sto64: {
+            /* signed */ Long s64 = e->Iex.Unop.arg->Iex.Const.con->Ico.U32;
+            s64 <<= 32;
+            s64 >>= 32;
+            e2 = IRExpr_Const(IRConst_U64((ULong)s64));
+            break;
+         }

          case Iop_CmpNEZ8:
             e2 = IRExpr_Const(IRConst_U1(toBool(
                     0 != 
          case Iop_CmpNEZ8:
             e2 = IRExpr_Const(IRConst_U1(toBool(
                     0 != 


@@ -1578,11 +1585,13 @@ static IRExpr* fold_Expr ( IRExpr* e )
          }
 
          /* Xor8/16/32/64/V128(t,t) ==> 0, for some IRTemp t */
          }
 
          /* Xor8/16/32/64/V128(t,t) ==> 0, for some IRTemp t */

+         /* Sub32(t,t) ==> 0, for some IRTemp t */

          if (   (e->Iex.Binop.op == Iop_Xor64
               || e->Iex.Binop.op == Iop_Xor32
               || e->Iex.Binop.op == Iop_Xor16
               || e->Iex.Binop.op == Iop_Xor8
          if (   (e->Iex.Binop.op == Iop_Xor64
               || e->Iex.Binop.op == Iop_Xor32
               || e->Iex.Binop.op == Iop_Xor16
               || e->Iex.Binop.op == Iop_Xor8

-              || e->Iex.Binop.op == Iop_XorV128)
+              || e->Iex.Binop.op == Iop_XorV128
+              || e->Iex.Binop.op == Iop_Sub32)

              && sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
             e2 = mkZeroForXor(e->Iex.Binop.op);
          }
              && sameIRTemps(e->Iex.Binop.arg1, e->Iex.Binop.arg2)) {
             e2 = mkZeroForXor(e->Iex.Binop.op);
          }


@@ -2193,8 +2202,10 @@ static Bool isOneU1 ( IRExpr* e )
 /*---------------------------------------------------------------*/
 
 static 
 /*---------------------------------------------------------------*/
 
 static 

-IRSB* spec_helpers_BB ( IRSB* bb,
-                        IRExpr* (*specHelper) ( HChar*, IRExpr**) )   
+IRSB* spec_helpers_BB(
+         IRSB* bb,
+         IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int)
+      )

 {
    Int     i;
    IRStmt* st;
 {
    Int     i;
    IRStmt* st;


@@ -2209,7 +2220,8 @@ IRSB* spec_helpers_BB ( IRSB* bb,
          continue;
 
       ex = (*specHelper)( st->Ist.WrTmp.data->Iex.CCall.cee->name,
          continue;
 
       ex = (*specHelper)( st->Ist.WrTmp.data->Iex.CCall.cee->name,

-                          st->Ist.WrTmp.data->Iex.CCall.args );
+                          st->Ist.WrTmp.data->Iex.CCall.args,
+                          &bb->stmts[0], i );

       if (!ex)
         /* the front end can't think of a suitable replacement */
         continue;
       if (!ex)
         /* the front end can't think of a suitable replacement */
         continue;


@@ -4355,7 +4367,7 @@ static Bool iropt_verbose = False; /* True; */
 static 
 IRSB* cheap_transformations ( 
          IRSB* bb,
 static 
 IRSB* cheap_transformations ( 
          IRSB* bb,

-         IRExpr* (*specHelper) (HChar*, IRExpr**),
+         IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int),

          Bool (*preciseMemExnsFn)(Int,Int)
       )
 {
          Bool (*preciseMemExnsFn)(Int,Int)
       )
 {


@@ -4506,10 +4518,13 @@ static void considerExpensives ( /*OUT*/Bool* hasGetIorPutI,
 */
 
 
 */
 
 

-IRSB* do_iropt_BB ( IRSB* bb0,
-                    IRExpr* (*specHelper) (HChar*, IRExpr**),
-                    Bool (*preciseMemExnsFn)(Int,Int),
-                    Addr64 guest_addr )
+IRSB* do_iropt_BB(
+         IRSB* bb0,
+         IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int),
+         Bool (*preciseMemExnsFn)(Int,Int),
+         Addr64 guest_addr,
+         VexArch guest_arch
+      )

 {
    static Int n_total     = 0;
    static Int n_expensive = 0;
 {
    static Int n_total     = 0;
    static Int n_expensive = 0;


@@ -4540,6 +4555,15 @@ IRSB* do_iropt_BB ( IRSB* bb0,
 
    bb = cheap_transformations( bb, specHelper, preciseMemExnsFn );
 
 
    bb = cheap_transformations( bb, specHelper, preciseMemExnsFn );
 

+   if (guest_arch == VexArchARM) {
+      /* Translating Thumb2 code produces a lot of chaff.  We have to
+         work extra hard to get rid of it. */
+      bb = cprop_BB(bb);
+      bb = spec_helpers_BB ( bb, specHelper );
+      redundant_put_removal_BB ( bb, preciseMemExnsFn );
+      do_deadcode_BB( bb );
+   }
+

    if (vex_control.iropt_level > 1) {
 
       /* Peer at what we have, to decide how much more effort to throw
    if (vex_control.iropt_level > 1) {
 
       /* Peer at what we have, to decide how much more effort to throw

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_opt.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_opt.h
index c92b9532e1f35804af2eef1c3b274f307cd2869c..ecdb146b77cbc6b045a9b361f6570f0beaad34a7 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_opt.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/ir_opt.h
@@ -43,10 +43,13 @@
 /* Top level optimiser entry point.  Returns a new BB.  Operates
    under the control of the global "vex_control" struct. */
 extern 
 /* Top level optimiser entry point.  Returns a new BB.  Operates
    under the control of the global "vex_control" struct. */
 extern 

-IRSB* do_iropt_BB ( IRSB* bb,
-                    IRExpr* (*specHelper) (HChar*, IRExpr**),
-                    Bool (*preciseMemExnsFn)(Int,Int),
-                    Addr64 guest_addr );
+IRSB* do_iropt_BB(
+         IRSB* bb,
+         IRExpr* (*specHelper) (HChar*, IRExpr**, IRStmt**, Int),
+         Bool (*preciseMemExnsFn)(Int,Int),
+         Addr64 guest_addr,
+         VexArch guest_arch
+      );

 
 /* Do a constant folding/propagation pass. */
 extern
 
 /* Do a constant folding/propagation pass. */
 extern

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/main_main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/main_main.c
index 8eec2aff3985ab8db617142ce8d2ee9fad12faec..ea0e5d0f559c39bdfa30b2eb384d38296cb5b9ba 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/main_main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/priv/main_main.c
@@ -57,6 +57,8 @@
 #include "guest_arm_defs.h"
 #include "guest_ppc_defs.h"
 
 #include "guest_arm_defs.h"
 #include "guest_ppc_defs.h"
 

+#include "host_generic_simd128.h"
+

 
 /* This file contains the top level interface to the library. */
 
 
 /* This file contains the top level interface to the library. */
 


@@ -141,6 +143,7 @@ void LibVEX_Init (
    vassert(4 == sizeof(Addr32));
    vassert(8 == sizeof(Addr64));
    vassert(16 == sizeof(U128));
    vassert(4 == sizeof(Addr32));
    vassert(8 == sizeof(Addr64));
    vassert(16 == sizeof(U128));

+   vassert(16 == sizeof(V128));

 
    vassert(sizeof(void*) == 4 || sizeof(void*) == 8);
    vassert(sizeof(void*) == sizeof(int*));
 
    vassert(sizeof(void*) == 4 || sizeof(void*) == 8);
    vassert(sizeof(void*) == sizeof(int*));


@@ -180,7 +183,7 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta )
    HInstrArray* (*iselSB)       ( IRSB*, VexArch, VexArchInfo*, 
                                                   VexAbiInfo* );
    Int          (*emit)         ( UChar*, Int, HInstr*, Bool, void* );
    HInstrArray* (*iselSB)       ( IRSB*, VexArch, VexArchInfo*, 
                                                   VexAbiInfo* );
    Int          (*emit)         ( UChar*, Int, HInstr*, Bool, void* );

-   IRExpr*      (*specHelper)   ( HChar*, IRExpr** );
+   IRExpr*      (*specHelper)   ( HChar*, IRExpr**, IRStmt**, Int );

    Bool         (*preciseMemExnsFn) ( Int, Int );
 
    DisOneInstrFn disInstrFn;
    Bool         (*preciseMemExnsFn) ( Int, Int );
 
    DisOneInstrFn disInstrFn;


@@ -498,7 +501,8 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta )
 
    /* Clean it up, hopefully a lot. */
    irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, 
 
    /* Clean it up, hopefully a lot. */
    irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, 

-                              vta->guest_bytes_addr );
+                              vta->guest_bytes_addr,
+                              vta->arch_guest );

    sanityCheckIRSB( irsb, "after initial iropt", 
                     True/*must be flat*/, guest_word_type );
 
    sanityCheckIRSB( irsb, "after initial iropt", 
                     True/*must be flat*/, guest_word_type );
 


@@ -751,32 +755,53 @@ void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi )
 static HChar* show_hwcaps_x86 ( UInt hwcaps ) 
 {
    /* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */
 static HChar* show_hwcaps_x86 ( UInt hwcaps ) 
 {
    /* Monotonic, SSE3 > SSE2 > SSE1 > baseline. */

-   if (hwcaps == 0)
-      return "x86-sse0";
-   if (hwcaps == VEX_HWCAPS_X86_SSE1)
-      return "x86-sse1";
-   if (hwcaps == (VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2))
-      return "x86-sse1-sse2";
-   if (hwcaps == (VEX_HWCAPS_X86_SSE1 
-                  | VEX_HWCAPS_X86_SSE2 | VEX_HWCAPS_X86_SSE3))
-      return "x86-sse1-sse2-sse3";
-
-   return NULL;
+   switch (hwcaps) {
+      case 0:
+         return "x86-sse0";
+      case VEX_HWCAPS_X86_SSE1:
+         return "x86-sse1";
+      case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2:
+         return "x86-sse1-sse2";
+      case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2
+           | VEX_HWCAPS_X86_LZCNT:
+         return "x86-sse1-sse2-lzcnt";
+      case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2
+           | VEX_HWCAPS_X86_SSE3:
+         return "x86-sse1-sse2-sse3";
+      case VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2
+           | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT:
+         return "x86-sse1-sse2-sse3-lzcnt";
+      default:
+         return NULL;
+   }

 }
 
 static HChar* show_hwcaps_amd64 ( UInt hwcaps )
 {
    /* SSE3 and CX16 are orthogonal and > baseline, although we really
       don't expect to come across anything which can do SSE3 but can't
 }
 
 static HChar* show_hwcaps_amd64 ( UInt hwcaps )
 {
    /* SSE3 and CX16 are orthogonal and > baseline, although we really
       don't expect to come across anything which can do SSE3 but can't

-      do CX16.  Still, we can handle that case. */
-   const UInt SSE3 = VEX_HWCAPS_AMD64_SSE3;
-   const UInt CX16 = VEX_HWCAPS_AMD64_CX16;
-         UInt c    = hwcaps;
-   if (c == 0)           return "amd64-sse2";
-   if (c == SSE3)        return "amd64-sse3";
-   if (c == CX16)        return "amd64-sse2-cx16";
-   if (c == (SSE3|CX16)) return "amd64-sse3-cx16";
-   return NULL;
+      do CX16.  Still, we can handle that case.  LZCNT is similarly
+      orthogonal. */
+   switch (hwcaps) {
+      case 0:
+         return "amd64-sse2";
+      case VEX_HWCAPS_AMD64_SSE3:
+         return "amd64-sse3";
+      case VEX_HWCAPS_AMD64_CX16:
+         return "amd64-sse2-cx16";
+      case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16:
+         return "amd64-sse3-cx16";
+      case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_LZCNT:
+         return "amd64-sse3-lzcnt";
+      case VEX_HWCAPS_AMD64_CX16 | VEX_HWCAPS_AMD64_LZCNT:
+         return "amd64-sse2-cx16-lzcnt";
+      case VEX_HWCAPS_AMD64_SSE3 | VEX_HWCAPS_AMD64_CX16
+           | VEX_HWCAPS_AMD64_LZCNT:
+         return "amd64-sse3-cx16-lzcnt";
+
+      default:
+         return NULL;
+   }

 }
 
 static HChar* show_hwcaps_ppc32 ( UInt hwcaps )
 }
 
 static HChar* show_hwcaps_ppc32 ( UInt hwcaps )


@@ -821,7 +846,41 @@ static HChar* show_hwcaps_ppc64 ( UInt hwcaps )
 
 static HChar* show_hwcaps_arm ( UInt hwcaps )
 {
 
 static HChar* show_hwcaps_arm ( UInt hwcaps )
 {

-   if (hwcaps == 0) return "arm-baseline";
+   Bool N = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0);
+   Bool vfp = ((hwcaps & (VEX_HWCAPS_ARM_VFP |
+               VEX_HWCAPS_ARM_VFP2 | VEX_HWCAPS_ARM_VFP3)) != 0);
+   switch (VEX_ARM_ARCHLEVEL(hwcaps)) {
+      case 5:
+         if (N)
+            return NULL;
+         if (vfp)
+            return "ARMv5-vfp";
+         else
+            return "ARMv5";
+         return NULL;
+      case 6:
+         if (N)
+            return NULL;
+         if (vfp)
+            return "ARMv6-vfp";
+         else
+            return "ARMv6";
+         return NULL;
+      case 7:
+         if (vfp) {
+            if (N)
+               return "ARMv7-vfp-neon";
+            else
+               return "ARMv7-vfp";
+         } else {
+            if (N)
+               return "ARMv7-neon";
+            else
+               return "ARMv7";
+         }
+      default:
+         return NULL;
+   }

    return NULL;
 }
 
    return NULL;
 }
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex.h
index 97cd76bf901b47828c70b80cb896154e5b4ba0ef..edc9f17bcd0d9950c823a2b71011a0b4e25dc308 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex.h
@@ -69,31 +69,40 @@ typedef
 
 /* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE), with
    cmpxchg8b. */
 
 /* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE), with
    cmpxchg8b. */

-#define VEX_HWCAPS_X86_SSE1   (1<<1)  /* SSE1 support (Pentium III) */
-#define VEX_HWCAPS_X86_SSE2   (1<<2)  /* SSE2 support (Pentium 4) */
-#define VEX_HWCAPS_X86_SSE3   (1<<3)  /* SSE3 support (>= Prescott) */
+#define VEX_HWCAPS_X86_SSE1    (1<<1)  /* SSE1 support (Pentium III) */
+#define VEX_HWCAPS_X86_SSE2    (1<<2)  /* SSE2 support (Pentium 4) */
+#define VEX_HWCAPS_X86_SSE3    (1<<3)  /* SSE3 support (>= Prescott) */
+#define VEX_HWCAPS_X86_LZCNT   (1<<4)  /* SSE4a LZCNT insn */

 
 /* amd64: baseline capability is SSE2, with cmpxchg8b but not
    cmpxchg16b. */
 
 /* amd64: baseline capability is SSE2, with cmpxchg8b but not
    cmpxchg16b. */

-#define VEX_HWCAPS_AMD64_SSE3 (1<<4)  /* SSE3 support */
-#define VEX_HWCAPS_AMD64_CX16 (1<<5)  /* cmpxchg16b support */
+#define VEX_HWCAPS_AMD64_SSE3  (1<<5)  /* SSE3 support */
+#define VEX_HWCAPS_AMD64_CX16  (1<<6)  /* cmpxchg16b support */
+#define VEX_HWCAPS_AMD64_LZCNT (1<<7)  /* SSE4a LZCNT insn */

 
 /* ppc32: baseline capability is integer only */
 
 /* ppc32: baseline capability is integer only */

-#define VEX_HWCAPS_PPC32_F    (1<<6)  /* basic (non-optional) FP */
-#define VEX_HWCAPS_PPC32_V    (1<<7)  /* Altivec (VMX) */
-#define VEX_HWCAPS_PPC32_FX   (1<<8)  /* FP extns (fsqrt, fsqrts) */
-#define VEX_HWCAPS_PPC32_GX   (1<<9)  /* Graphics extns
-                                         (fres,frsqrte,fsel,stfiwx) */
+#define VEX_HWCAPS_PPC32_F     (1<<8)  /* basic (non-optional) FP */
+#define VEX_HWCAPS_PPC32_V     (1<<9)  /* Altivec (VMX) */
+#define VEX_HWCAPS_PPC32_FX    (1<<10) /* FP extns (fsqrt, fsqrts) */
+#define VEX_HWCAPS_PPC32_GX    (1<<11) /* Graphics extns
+                                          (fres,frsqrte,fsel,stfiwx) */

 
 /* ppc64: baseline capability is integer and basic FP insns */
 
 /* ppc64: baseline capability is integer and basic FP insns */

-#define VEX_HWCAPS_PPC64_V    (1<<10) /* Altivec (VMX) */
-#define VEX_HWCAPS_PPC64_FX   (1<<11) /* FP extns (fsqrt, fsqrts) */
-#define VEX_HWCAPS_PPC64_GX   (1<<12) /* Graphics extns
-                                         (fres,frsqrte,fsel,stfiwx) */
+#define VEX_HWCAPS_PPC64_V     (1<<12) /* Altivec (VMX) */
+#define VEX_HWCAPS_PPC64_FX    (1<<13) /* FP extns (fsqrt, fsqrts) */
+#define VEX_HWCAPS_PPC64_GX    (1<<14) /* Graphics extns
+                                          (fres,frsqrte,fsel,stfiwx) */

 
 /* arm: baseline capability is ARMv4 */
 
 /* arm: baseline capability is ARMv4 */

-/* No extra capabilities */
-
+/* Bits 5:0 - architecture level (e.g. 5 for v5, 6 for v6 etc) */
+#define VEX_HWCAPS_ARM_VFP    (1<<6)  /* VFP extension */
+#define VEX_HWCAPS_ARM_VFP2   (1<<7)  /* VFPv2 */
+#define VEX_HWCAPS_ARM_VFP3   (1<<8)  /* VFPv3 */
+/* Bits 15:10 reserved for (possible) future VFP revisions */
+#define VEX_HWCAPS_ARM_NEON   (1<<16) /* Advanced SIMD also known as NEON */
+
+/* Get an ARM architecure level from HWCAPS */
+#define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f)

 
 /* These return statically allocated strings. */
 
 
 /* These return statically allocated strings. */
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_basictypes.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_basictypes.h
index a996f2e563b058c011769990ead07c86bb5de304..a945913547065a16a2acfb3022cc81f2a0a56f17 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_basictypes.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_basictypes.h
@@ -62,7 +62,17 @@ typedef    signed long long int   Long;
 /* Always 128 bits. */
 typedef  UInt  U128[4];
 
 /* Always 128 bits. */
 typedef  UInt  U128[4];
 

+/* A union for doing 128-bit vector primitives conveniently. */
+typedef
+   union {
+      UChar  w8[16];
+      UShort w16[8];
+      UInt   w32[4];
+      ULong  w64[2];
+   }
+   V128;

 
 

+/* Floating point. */

 typedef  float   Float;    /* IEEE754 single-precision (32-bit) value */
 typedef  double  Double;   /* IEEE754 double-precision (64-bit) value */
 
 typedef  float   Float;    /* IEEE754 single-precision (32-bit) value */
 typedef  double  Double;   /* IEEE754 double-precision (64-bit) value */
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_guest_amd64.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_guest_amd64.h
index 944f27e7645fef73ef61f82dffcabbc101c2e86b..eb9e19eb1cda977c48f921853350be080ef5d29b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_guest_amd64.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_guest_amd64.h
@@ -91,7 +91,10 @@ typedef
          associated with a %fs value of zero. */
       /* 184 */ ULong guest_FS_ZERO;
 
          associated with a %fs value of zero. */
       /* 184 */ ULong guest_FS_ZERO;
 

-      /* XMM registers */
+      /* XMM registers.  Note that these must be allocated
+         consecutively in order that the SSE4.2 PCMP{E,I}STR{I,M}
+         helpers can treat them as an array.  XMM16 is a fake reg used
+         as an intermediary in handling aforementioned insns. */

       /* 192 */ULong guest_SSEROUND;
       /* 200 */U128  guest_XMM0;
       U128  guest_XMM1;
       /* 192 */ULong guest_SSEROUND;
       /* 200 */U128  guest_XMM0;
       U128  guest_XMM1;


@@ -109,6 +112,7 @@ typedef
       U128  guest_XMM13;
       U128  guest_XMM14;
       U128  guest_XMM15;
       U128  guest_XMM13;
       U128  guest_XMM14;
       U128  guest_XMM15;

+      U128  guest_XMM16;

 
       /* FPU */
       /* Note.  Setting guest_FTOP to be ULong messes up the
 
       /* FPU */
       /* Note.  Setting guest_FTOP to be ULong messes up the

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_guest_arm.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_guest_arm.h
index 664bfb786b5a4fe91a5f327b1fd8029a55082ceb..cfbf1222f209d3c2fd6bbe7dec30860bae028fb4 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_guest_arm.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_guest_arm.h
@@ -57,7 +57,15 @@ typedef
       UInt guest_R12;
       UInt guest_R13;     /* stack pointer */
       UInt guest_R14;     /* link register */
       UInt guest_R12;
       UInt guest_R13;     /* stack pointer */
       UInt guest_R14;     /* link register */

-      UInt guest_R15;     /* program counter */
+      UInt guest_R15T;
+      /* program counter[31:1] ++ [T], encoding both the current
+         instruction address and the ARM vs Thumb state of the
+         machine.  T==1 is Thumb, T==0 is ARM.  Hence values of the
+         form X--(31)--X1 denote a Thumb instruction at location
+         X--(31)--X0, values of the form X--(30)--X00 denote an ARM
+         instruction at precisely that address, and values of the form
+         X--(30)--10 are invalid since they would imply an ARM
+         instruction at a non-4-aligned address. */

 
       /* 4-word thunk used to calculate N(sign) Z(zero) C(carry,
          unsigned overflow) and V(signed overflow) flags. */
 
       /* 4-word thunk used to calculate N(sign) Z(zero) C(carry,
          unsigned overflow) and V(signed overflow) flags. */


@@ -67,6 +75,12 @@ typedef
       UInt guest_CC_DEP2;
       UInt guest_CC_NDEP;
 
       UInt guest_CC_DEP2;
       UInt guest_CC_NDEP;
 

+      /* A 32-bit value which is used to compute the APSR.Q (sticky
+         saturation) flag, when necessary.  If the value stored here
+         is zero, APSR.Q is currently zero.  If it is any other value,
+         APSR.Q is currently one. */
+      UInt guest_QFLAG32;
+

       /* Various pseudo-regs mandated by Vex or Valgrind. */
       /* Emulation warnings */
       UInt guest_EMWARN;
       /* Various pseudo-regs mandated by Vex or Valgrind. */
       /* Emulation warnings */
       UInt guest_EMWARN;


@@ -108,6 +122,22 @@ typedef
       ULong guest_D13;
       ULong guest_D14;
       ULong guest_D15;
       ULong guest_D13;
       ULong guest_D14;
       ULong guest_D15;

+      ULong guest_D16;
+      ULong guest_D17;
+      ULong guest_D18;
+      ULong guest_D19;
+      ULong guest_D20;
+      ULong guest_D21;
+      ULong guest_D22;
+      ULong guest_D23;
+      ULong guest_D24;
+      ULong guest_D25;
+      ULong guest_D26;
+      ULong guest_D27;
+      ULong guest_D28;
+      ULong guest_D29;
+      ULong guest_D30;
+      ULong guest_D31;

       UInt  guest_FPSCR;
 
       /* Not a town in Cornwall, but instead the TPIDRURO, on of the
       UInt  guest_FPSCR;
 
       /* Not a town in Cornwall, but instead the TPIDRURO, on of the


@@ -119,9 +149,45 @@ typedef
          thread-related syscalls. */
       UInt guest_TPIDRURO;
 
          thread-related syscalls. */
       UInt guest_TPIDRURO;
 

+      /* Representation of the Thumb IT state.  ITSTATE is a 32-bit
+         value with 4 8-bit lanes.  [7:0] pertain to the next insn to
+         execute, [15:8] for the one after that, etc.  The per-insn
+         update to ITSTATE is to unsignedly shift it right 8 bits,
+         hence introducing a zero byte for the furthest ahead
+         instruction.  As per the next para, a zero byte denotes the
+         condition ALWAYS.
+
+         Each byte lane has one of the two following formats:
+
+         cccc 0001  for an insn which is part of an IT block.  cccc is
+                    the guarding condition (standard ARM condition
+                    code) XORd with 0xE, so as to cause 'cccc == 0'
+                    to encode the condition ALWAYS.
+
+         0000 0000  for an insn which is not part of an IT block.
+
+         If the bottom 4 bits are zero then the top 4 must be too.
+
+         Given the byte lane for an instruction, the guarding
+         condition for the instruction is (((lane >> 4) & 0xF) ^ 0xE).
+         This is not as stupid as it sounds, because the front end
+         elides the shift.  And the am-I-in-an-IT-block check is
+         (lane != 0).
+
+         In the case where (by whatever means) we know at JIT time
+         that an instruction is not in an IT block, we can prefix its
+         IR with assignments ITSTATE = 0 and hence have iropt fold out
+         the testing code.
+
+         The condition "is outside or last in IT block" corresponds
+         to the top 24 bits of ITSTATE being zero.
+      */
+      UInt guest_ITSTATE;
+

       /* Padding to make it have an 16-aligned size */
       /* Padding to make it have an 16-aligned size */

-      /* UInt padding1; */
-      /* UInt padding2; */
+      UInt padding1;
+      UInt padding2;
+      UInt padding3;

    }
    VexGuestARMState;
 
    }
    VexGuestARMState;
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_ir.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_ir.h
index 98a980f5ef18c4acd628670fbd02b9a32ee9189e..0d8a8472b211cd74ae7fcdcb9989c7e26b8ed5b3 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_ir.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/pub/libvex_ir.h
@@ -639,6 +639,8 @@ typedef
       Iop_2xm1F64,   /* (2^arg - 1.0) */
       Iop_RoundF64toInt, /* F64 value to nearest integral value (still
                             as F64) */
       Iop_2xm1F64,   /* (2^arg - 1.0) */
       Iop_RoundF64toInt, /* F64 value to nearest integral value (still
                             as F64) */

+      Iop_RoundF32toInt, /* F32 value to nearest integral value (still
+                            as F32) */

 
       /* --- guest ppc32/64 specifics, not mandated by 754. --- */
 
 
       /* --- guest ppc32/64 specifics, not mandated by 754. --- */
 


@@ -673,6 +675,49 @@ typedef
       Iop_CalcFPRF, /* Calc 5 fpscr[FPRF] bits (Class, <, =, >, Unord)
                        from FP result */
 
       Iop_CalcFPRF, /* Calc 5 fpscr[FPRF] bits (Class, <, =, >, Unord)
                        from FP result */
 

+      /* ------------------ 64-bit SIMD FP ------------------------ */
+
+      /* Convertion to/from int */
+      Iop_I32UtoFx2,  Iop_I32StoFx2,    /* I32x4 -> F32x4 */
+      Iop_FtoI32Ux2_RZ,  Iop_FtoI32Sx2_RZ,    /* F32x4 -> I32x4 */
+      /* Fixed32 format is floating-point number with fixed number of fraction
+         bits. The number of fraction bits is passed as a second argument of
+         type I8. */
+      Iop_F32ToFixed32Ux2_RZ, Iop_F32ToFixed32Sx2_RZ, /* fp -> fixed-point */
+      Iop_Fixed32UToF32x2_RN, Iop_Fixed32SToF32x2_RN, /* fixed-point -> fp */
+
+      /* Binary operations */
+      Iop_Max32Fx2,      Iop_Min32Fx2,
+      /* Pairwise Min and Max. See integer pairwise operations for more
+         details. */
+      Iop_PwMax32Fx2,    Iop_PwMin32Fx2,
+      /* Note: For the following compares, the arm front-end assumes a
+         nan in a lane of either argument returns zero for that lane. */
+      Iop_CmpEQ32Fx2, Iop_CmpGT32Fx2, Iop_CmpGE32Fx2,
+
+      /* Vector Reciprocal Estimate finds an approximate reciprocal of each
+      element in the operand vector, and places the results in the destination
+      vector.  */
+      Iop_Recip32Fx2,
+
+      /* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
+         Note, that if one of the arguments is zero and another one is infinity
+         of arbitrary sign the result of the operation is 2.0. */
+      Iop_Recps32Fx2,
+
+      /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
+         square root of each element in the operand vector. */
+      Iop_Rsqrte32Fx2,
+
+      /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
+         Note, that of one of the arguments is zero and another one is infiinty
+         of arbitrary sign the result of the operation is 1.5. */
+      Iop_Rsqrts32Fx2,
+
+      /* Unary */
+      Iop_Neg32Fx2, Iop_Abs32Fx2,
+
+

       /* ------------------ 64-bit SIMD Integer. ------------------ */
 
       /* MISC (vector integer cmp != 0) */
       /* ------------------ 64-bit SIMD Integer. ------------------ */
 
       /* MISC (vector integer cmp != 0) */


@@ -680,54 +725,142 @@ typedef
 
       /* ADDITION (normal / unsigned sat / signed sat) */
       Iop_Add8x8,   Iop_Add16x4,   Iop_Add32x2,
 
       /* ADDITION (normal / unsigned sat / signed sat) */
       Iop_Add8x8,   Iop_Add16x4,   Iop_Add32x2,

-      Iop_QAdd8Ux8, Iop_QAdd16Ux4,
-      Iop_QAdd8Sx8, Iop_QAdd16Sx4,
+      Iop_QAdd8Ux8, Iop_QAdd16Ux4, Iop_QAdd32Ux2, Iop_QAdd64Ux1,
+      Iop_QAdd8Sx8, Iop_QAdd16Sx4, Iop_QAdd32Sx2, Iop_QAdd64Sx1,
+
+      /* PAIRWISE operations */
+      /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) =
+            [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
+      Iop_PwAdd8x8,  Iop_PwAdd16x4,  Iop_PwAdd32x2,
+      Iop_PwMax8Sx8, Iop_PwMax16Sx4, Iop_PwMax32Sx2,
+      Iop_PwMax8Ux8, Iop_PwMax16Ux4, Iop_PwMax32Ux2,
+      Iop_PwMin8Sx8, Iop_PwMin16Sx4, Iop_PwMin32Sx2,
+      Iop_PwMin8Ux8, Iop_PwMin16Ux4, Iop_PwMin32Ux2,
+      /* Longening variant is unary. The resulting vector contains two times
+         less elements than operand, but they are two times wider.
+         Example:
+            Iop_PAddL16Ux4( [a,b,c,d] ) = [a+b,c+d]
+               where a+b and c+d are unsigned 32-bit values. */
+      Iop_PwAddL8Ux8, Iop_PwAddL16Ux4, Iop_PwAddL32Ux2,
+      Iop_PwAddL8Sx8, Iop_PwAddL16Sx4, Iop_PwAddL32Sx2,

 
       /* SUBTRACTION (normal / unsigned sat / signed sat) */
       Iop_Sub8x8,   Iop_Sub16x4,   Iop_Sub32x2,
 
       /* SUBTRACTION (normal / unsigned sat / signed sat) */
       Iop_Sub8x8,   Iop_Sub16x4,   Iop_Sub32x2,

-      Iop_QSub8Ux8, Iop_QSub16Ux4,
-      Iop_QSub8Sx8, Iop_QSub16Sx4,
+      Iop_QSub8Ux8, Iop_QSub16Ux4, Iop_QSub32Ux2, Iop_QSub64Ux1,
+      Iop_QSub8Sx8, Iop_QSub16Sx4, Iop_QSub32Sx2, Iop_QSub64Sx1,

 
 

-      /* MULTIPLICATION (normal / high half of signed/unsigned) */
-      Iop_Mul16x4, Iop_Mul32x2,
+      /* ABSOLUTE VALUE */
+      Iop_Abs8x8, Iop_Abs16x4, Iop_Abs32x2,
+
+      /* MULTIPLICATION (normal / high half of signed/unsigned / plynomial ) */
+      Iop_Mul8x8, Iop_Mul16x4, Iop_Mul32x2,
+      Iop_Mul32Fx2,

       Iop_MulHi16Ux4,
       Iop_MulHi16Sx4,
       Iop_MulHi16Ux4,
       Iop_MulHi16Sx4,

+      /* Plynomial multiplication treats it's arguments as coefficients of
+         polynoms over {0, 1}. */
+      Iop_PolynomialMul8x8,
+
+      /* Vector Saturating Doubling Multiply Returning High Half and
+         Vector Saturating Rounding Doubling Multiply Returning High Half */
+      /* These IROp's multiply corresponding elements in two vectors, double
+         the results, and place the most significant half of the final results
+         in the destination vector. The results are truncated or rounded. If
+         any of the results overflow, they are saturated. */
+      Iop_QDMulHi16Sx4, Iop_QDMulHi32Sx2,
+      Iop_QRDMulHi16Sx4, Iop_QRDMulHi32Sx2,

 
       /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
       Iop_Avg8Ux8,
       Iop_Avg16Ux4,
 
       /* MIN/MAX */
 
       /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
       Iop_Avg8Ux8,
       Iop_Avg16Ux4,
 
       /* MIN/MAX */

-      Iop_Max16Sx4,
-      Iop_Max8Ux8,
-      Iop_Min16Sx4,
-      Iop_Min8Ux8,
+      Iop_Max8Sx8, Iop_Max16Sx4, Iop_Max32Sx2,
+      Iop_Max8Ux8, Iop_Max16Ux4, Iop_Max32Ux2,
+      Iop_Min8Sx8, Iop_Min16Sx4, Iop_Min32Sx2,
+      Iop_Min8Ux8, Iop_Min16Ux4, Iop_Min32Ux2,

 
       /* COMPARISON */
       Iop_CmpEQ8x8,  Iop_CmpEQ16x4,  Iop_CmpEQ32x2,
 
       /* COMPARISON */
       Iop_CmpEQ8x8,  Iop_CmpEQ16x4,  Iop_CmpEQ32x2,

+      Iop_CmpGT8Ux8, Iop_CmpGT16Ux4, Iop_CmpGT32Ux2,

       Iop_CmpGT8Sx8, Iop_CmpGT16Sx4, Iop_CmpGT32Sx2,
 
       Iop_CmpGT8Sx8, Iop_CmpGT16Sx4, Iop_CmpGT32Sx2,
 

+      /* COUNT ones / leading zeroes / leading sign bits (not including topmost
+         bit) */
+      Iop_Cnt8x8,
+      Iop_Clz8Sx8, Iop_Clz16Sx4, Iop_Clz32Sx2,
+      Iop_Cls8Sx8, Iop_Cls16Sx4, Iop_Cls32Sx2,
+
+      /* VECTOR x VECTOR SHIFT / ROTATE */
+      Iop_Shl8x8, Iop_Shl16x4, Iop_Shl32x2,
+      Iop_Shr8x8, Iop_Shr16x4, Iop_Shr32x2,
+      Iop_Sar8x8, Iop_Sar16x4, Iop_Sar32x2,
+      Iop_Sal8x8, Iop_Sal16x4, Iop_Sal32x2, Iop_Sal64x1,
+

       /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
       Iop_ShlN8x8, Iop_ShlN16x4, Iop_ShlN32x2,
       /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
       Iop_ShlN8x8, Iop_ShlN16x4, Iop_ShlN32x2,

-                   Iop_ShrN16x4, Iop_ShrN32x2,
+      Iop_ShrN8x8, Iop_ShrN16x4, Iop_ShrN32x2,

       Iop_SarN8x8, Iop_SarN16x4, Iop_SarN32x2,
 
       Iop_SarN8x8, Iop_SarN16x4, Iop_SarN32x2,
 

+      /* VECTOR x VECTOR SATURATING SHIFT */
+      Iop_QShl8x8, Iop_QShl16x4, Iop_QShl32x2, Iop_QShl64x1,
+      Iop_QSal8x8, Iop_QSal16x4, Iop_QSal32x2, Iop_QSal64x1,
+      /* VECTOR x INTEGER SATURATING SHIFT */
+      Iop_QShlN8Sx8, Iop_QShlN16Sx4, Iop_QShlN32Sx2, Iop_QShlN64Sx1,
+      Iop_QShlN8x8, Iop_QShlN16x4, Iop_QShlN32x2, Iop_QShlN64x1,
+      Iop_QSalN8x8, Iop_QSalN16x4, Iop_QSalN32x2, Iop_QSalN64x1,
+

       /* NARROWING -- narrow 2xI64 into 1xI64, hi half from left arg */
       Iop_QNarrow16Ux4,
       Iop_QNarrow16Sx4,
       Iop_QNarrow32Sx2,
 
       /* NARROWING -- narrow 2xI64 into 1xI64, hi half from left arg */
       Iop_QNarrow16Ux4,
       Iop_QNarrow16Sx4,
       Iop_QNarrow32Sx2,
 

-      /* INTERLEAVING -- interleave lanes from low or high halves of
+      /* INTERLEAVING */
+      /* Interleave lanes from low or high halves of

          operands.  Most-significant result lane is from the left
          arg. */
       Iop_InterleaveHI8x8, Iop_InterleaveHI16x4, Iop_InterleaveHI32x2,
       Iop_InterleaveLO8x8, Iop_InterleaveLO16x4, Iop_InterleaveLO32x2,
          operands.  Most-significant result lane is from the left
          arg. */
       Iop_InterleaveHI8x8, Iop_InterleaveHI16x4, Iop_InterleaveHI32x2,
       Iop_InterleaveLO8x8, Iop_InterleaveLO16x4, Iop_InterleaveLO32x2,

+      /* Interleave odd/even lanes of operands.  Most-significant result lane
+         is from the left arg.  Note that Interleave{Odd,Even}Lanes32x2 are
+         identical to Interleave{HI,LO}32x2 and so are omitted.*/
+      Iop_InterleaveOddLanes8x8, Iop_InterleaveEvenLanes8x8,
+      Iop_InterleaveOddLanes16x4, Iop_InterleaveEvenLanes16x4,
+

 
       /* CONCATENATION -- build a new value by concatenating either
          the even or odd lanes of both operands.  Note that
          Cat{Odd,Even}Lanes32x2 are identical to Interleave{HI,LO}32x2
          and so are omitted. */
 
       /* CONCATENATION -- build a new value by concatenating either
          the even or odd lanes of both operands.  Note that
          Cat{Odd,Even}Lanes32x2 are identical to Interleave{HI,LO}32x2
          and so are omitted. */

-      Iop_CatOddLanes16x4, Iop_CatEvenLanes16x4,
+      Iop_CatOddLanes8x8, Iop_CatOddLanes16x4,
+      Iop_CatEvenLanes8x8, Iop_CatEvenLanes16x4,
+
+      /* GET / SET elements of VECTOR
+         GET is binop (I64, I8) -> I<elem_size>
+         SET is triop (I64, I8, I<elem_size>) -> I64 */
+      /* Note: the arm back-end handles only constant second argument */
+      Iop_GetElem8x8, Iop_GetElem16x4, Iop_GetElem32x2,
+      Iop_SetElem8x8, Iop_SetElem16x4, Iop_SetElem32x2,
+
+      /* DUPLICATING -- copy value to all lanes */
+      Iop_Dup8x8,   Iop_Dup16x4,   Iop_Dup32x2,
+
+      /* EXTRACT -- copy 8-arg3 highest bytes from arg1 to 8-arg3 lowest bytes
+         of result and arg3 lowest bytes of arg2 to arg3 highest bytes of
+         result.
+         It is a triop: (I64, I64, I8) -> I64 */
+      /* Note: the arm back-end handles only constant third argumnet. */
+      Iop_Extract64,
+
+      /* REVERSE the order of elements in each Half-words, Words,
+         Double-words */
+      /* Examples:
+            Reverse16_8x8([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g]
+            Reverse32_8x8([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e]
+            Reverse64_8x8([a,b,c,d,e,f,g,h]) = [h,g,f,e,d,c,b,a] */
+      Iop_Reverse16_8x8,
+      Iop_Reverse32_8x8, Iop_Reverse32_16x4,
+      Iop_Reverse64_8x8, Iop_Reverse64_16x4, Iop_Reverse64_32x2,

 
       /* PERMUTING -- copy src bytes to dst,
          as indexed by control vector bytes:
 
       /* PERMUTING -- copy src bytes to dst,
          as indexed by control vector bytes:


@@ -736,6 +869,10 @@ typedef
          is undefined. */
       Iop_Perm8x8,
 
          is undefined. */
       Iop_Perm8x8,
 

+      /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate
+         See floating-point equiwalents for details. */
+      Iop_Recip32x2, Iop_Rsqrte32x2,
+

       /* ------------------ 128-bit SIMD FP. ------------------ */
 
       /* --- 32x4 vector FP --- */
       /* ------------------ 128-bit SIMD FP. ------------------ */
 
       /* --- 32x4 vector FP --- */


@@ -743,22 +880,59 @@ typedef
       /* binary */
       Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4, 
       Iop_Max32Fx4, Iop_Min32Fx4,
       /* binary */
       Iop_Add32Fx4, Iop_Sub32Fx4, Iop_Mul32Fx4, Iop_Div32Fx4, 
       Iop_Max32Fx4, Iop_Min32Fx4,

-      /* Note: For the following compares, the ppc front-end assumes a
+      Iop_Add32Fx2, Iop_Sub32Fx2,
+      /* Note: For the following compares, the ppc and arm front-ends assume a

          nan in a lane of either argument returns zero for that lane. */
          nan in a lane of either argument returns zero for that lane. */

-      Iop_CmpEQ32Fx4, Iop_CmpLT32Fx4, Iop_CmpLE32Fx4, Iop_CmpUN32Fx4, 
+      Iop_CmpEQ32Fx4, Iop_CmpLT32Fx4, Iop_CmpLE32Fx4, Iop_CmpUN32Fx4,

       Iop_CmpGT32Fx4, Iop_CmpGE32Fx4,
 
       Iop_CmpGT32Fx4, Iop_CmpGE32Fx4,
 

+      /* Vector Absolute */
+      Iop_Abs32Fx4,
+
+      /* Pairwise Max and Min. See integer pairwise operations for details. */
+      Iop_PwMax32Fx4, Iop_PwMin32Fx4,
+

       /* unary */
       /* unary */

-      Iop_Recip32Fx4, Iop_Sqrt32Fx4, Iop_RSqrt32Fx4,
+      Iop_Sqrt32Fx4, Iop_RSqrt32Fx4,
+      Iop_Neg32Fx4,
+
+      /* Vector Reciprocal Estimate finds an approximate reciprocal of each
+      element in the operand vector, and places the results in the destination
+      vector.  */
+      Iop_Recip32Fx4,
+
+      /* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
+         Note, that if one of the arguments is zero and another one is infinity
+         of arbitrary sign the result of the operation is 2.0. */
+      Iop_Recps32Fx4,
+
+      /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
+         square root of each element in the operand vector. */
+      Iop_Rsqrte32Fx4,
+
+      /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
+         Note, that of one of the arguments is zero and another one is infiinty
+         of arbitrary sign the result of the operation is 1.5. */
+      Iop_Rsqrts32Fx4,
+

 
       /* --- Int to/from FP conversion --- */
       /* Unlike the standard fp conversions, these irops take no
          rounding mode argument. Instead the irop trailers _R{M,P,N,Z}
          indicate the mode: {-inf, +inf, nearest, zero} respectively. */
 
       /* --- Int to/from FP conversion --- */
       /* Unlike the standard fp conversions, these irops take no
          rounding mode argument. Instead the irop trailers _R{M,P,N,Z}
          indicate the mode: {-inf, +inf, nearest, zero} respectively. */

-      Iop_I32UtoFx4,     Iop_I32StoFx4,       /* I32x4 -> F32x4       */
-      Iop_QFtoI32Ux4_RZ, Iop_QFtoI32Sx4_RZ,   /* F32x4 -> I32x4       */
+      Iop_I32UtoFx4,  Iop_I32StoFx4,       /* I32x4 -> F32x4       */
+      Iop_FtoI32Ux4_RZ,  Iop_FtoI32Sx4_RZ,    /* F32x4 -> I32x4       */
+      Iop_QFtoI32Ux4_RZ, Iop_QFtoI32Sx4_RZ,   /* F32x4 -> I32x4 (with saturation) */

       Iop_RoundF32x4_RM, Iop_RoundF32x4_RP,   /* round to fp integer  */
       Iop_RoundF32x4_RN, Iop_RoundF32x4_RZ,   /* round to fp integer  */
       Iop_RoundF32x4_RM, Iop_RoundF32x4_RP,   /* round to fp integer  */
       Iop_RoundF32x4_RN, Iop_RoundF32x4_RZ,   /* round to fp integer  */

+      /* Fixed32 format is floating-point number with fixed number of fraction
+         bits. The number of fraction bits is passed as a second argument of
+         type I8. */
+      Iop_F32ToFixed32Ux4_RZ, Iop_F32ToFixed32Sx4_RZ, /* fp -> fixed-point */
+      Iop_Fixed32UToF32x4_RN, Iop_Fixed32SToF32x4_RN, /* fixed-point -> fp */
+
+      /* --- Single to/from half conversion --- */
+      Iop_F32toF16x4, Iop_F16toF32x4,         /* F32x4 <-> F16x4      */

 
       /* --- 32x4 lowest-lane-only scalar FP --- */
 
 
       /* --- 32x4 lowest-lane-only scalar FP --- */
 


@@ -824,22 +998,56 @@ typedef
       Iop_CmpNEZ8x16, Iop_CmpNEZ16x8, Iop_CmpNEZ32x4, Iop_CmpNEZ64x2,
 
       /* ADDITION (normal / unsigned sat / signed sat) */
       Iop_CmpNEZ8x16, Iop_CmpNEZ16x8, Iop_CmpNEZ32x4, Iop_CmpNEZ64x2,
 
       /* ADDITION (normal / unsigned sat / signed sat) */

-      Iop_Add8x16,   Iop_Add16x8,   Iop_Add32x4,  Iop_Add64x2,
-      Iop_QAdd8Ux16, Iop_QAdd16Ux8, Iop_QAdd32Ux4,
-      Iop_QAdd8Sx16, Iop_QAdd16Sx8, Iop_QAdd32Sx4,
+      Iop_Add8x16,   Iop_Add16x8,   Iop_Add32x4,   Iop_Add64x2,
+      Iop_QAdd8Ux16, Iop_QAdd16Ux8, Iop_QAdd32Ux4, Iop_QAdd64Ux2,
+      Iop_QAdd8Sx16, Iop_QAdd16Sx8, Iop_QAdd32Sx4, Iop_QAdd64Sx2,

 
       /* SUBTRACTION (normal / unsigned sat / signed sat) */
 
       /* SUBTRACTION (normal / unsigned sat / signed sat) */

-      Iop_Sub8x16,   Iop_Sub16x8,   Iop_Sub32x4,  Iop_Sub64x2,
-      Iop_QSub8Ux16, Iop_QSub16Ux8, Iop_QSub32Ux4,
-      Iop_QSub8Sx16, Iop_QSub16Sx8, Iop_QSub32Sx4,
+      Iop_Sub8x16,   Iop_Sub16x8,   Iop_Sub32x4,   Iop_Sub64x2,
+      Iop_QSub8Ux16, Iop_QSub16Ux8, Iop_QSub32Ux4, Iop_QSub64Ux2,
+      Iop_QSub8Sx16, Iop_QSub16Sx8, Iop_QSub32Sx4, Iop_QSub64Sx2,

 
       /* MULTIPLICATION (normal / high half of signed/unsigned) */
 
       /* MULTIPLICATION (normal / high half of signed/unsigned) */

-      Iop_Mul16x8,
-      Iop_MulHi16Ux8, Iop_MulHi32Ux4,
-      Iop_MulHi16Sx8, Iop_MulHi32Sx4,
+      Iop_Mul8x16,  Iop_Mul16x8,    Iop_Mul32x4,
+                    Iop_MulHi16Ux8, Iop_MulHi32Ux4,
+                    Iop_MulHi16Sx8, Iop_MulHi32Sx4,

       /* (widening signed/unsigned of even lanes, with lowest lane=zero) */
       Iop_MullEven8Ux16, Iop_MullEven16Ux8,
       Iop_MullEven8Sx16, Iop_MullEven16Sx8,
       /* (widening signed/unsigned of even lanes, with lowest lane=zero) */
       Iop_MullEven8Ux16, Iop_MullEven16Ux8,
       Iop_MullEven8Sx16, Iop_MullEven16Sx8,

+      /* FIXME: document these */
+      Iop_Mull8Ux8, Iop_Mull8Sx8,
+      Iop_Mull16Ux4, Iop_Mull16Sx4,
+      Iop_Mull32Ux2, Iop_Mull32Sx2,
+      /* Vector Saturating Doubling Multiply Returning High Half and
+         Vector Saturating Rounding Doubling Multiply Returning High Half */
+      /* These IROp's multiply corresponding elements in two vectors, double
+         the results, and place the most significant half of the final results
+         in the destination vector. The results are truncated or rounded. If
+         any of the results overflow, they are saturated. */
+      Iop_QDMulHi16Sx8, Iop_QDMulHi32Sx4,
+      Iop_QRDMulHi16Sx8, Iop_QRDMulHi32Sx4,
+      /* Doubling saturating multiplication (long) (I64, I64) -> V128 */
+      Iop_QDMulLong16Sx4, Iop_QDMulLong32Sx2,
+      /* Plynomial multiplication treats it's arguments as coefficients of
+         polynoms over {0, 1}. */
+      Iop_PolynomialMul8x16, /* (V128, V128) -> V128 */
+      Iop_PolynomialMull8x8, /*   (I64, I64) -> V128 */
+
+      /* PAIRWISE operations */
+      /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) =
+            [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
+      Iop_PwAdd8x16, Iop_PwAdd16x8, Iop_PwAdd32x4,
+      Iop_PwAdd32Fx2,
+      /* Longening variant is unary. The resulting vector contains two times
+         less elements than operand, but they are two times wider.
+         Example:
+            Iop_PwAddL16Ux4( [a,b,c,d] ) = [a+b,c+d]
+               where a+b and c+d are unsigned 32-bit values. */
+      Iop_PwAddL8Ux16, Iop_PwAddL16Ux8, Iop_PwAddL32Ux4,
+      Iop_PwAddL8Sx16, Iop_PwAddL16Sx8, Iop_PwAddL32Sx4,
+
+      /* ABSOLUTE VALUE */
+      Iop_Abs8x16, Iop_Abs16x8, Iop_Abs32x4,

 
       /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
       Iop_Avg8Ux16, Iop_Avg16Ux8, Iop_Avg32Ux4,
 
       /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
       Iop_Avg8Ux16, Iop_Avg16Ux8, Iop_Avg32Ux4,


@@ -853,43 +1061,113 @@ typedef
 
       /* COMPARISON */
       Iop_CmpEQ8x16,  Iop_CmpEQ16x8,  Iop_CmpEQ32x4,
 
       /* COMPARISON */
       Iop_CmpEQ8x16,  Iop_CmpEQ16x8,  Iop_CmpEQ32x4,

-      Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4,
+      Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, Iop_CmpGT64Sx2,

       Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4,
 
       Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4,
 

+      /* COUNT ones / leading zeroes / leading sign bits (not including topmost
+         bit) */
+      Iop_Cnt8x16,
+      Iop_Clz8Sx16, Iop_Clz16Sx8, Iop_Clz32Sx4,
+      Iop_Cls8Sx16, Iop_Cls16Sx8, Iop_Cls32Sx4,
+

       /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
       Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2,
       Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2,
       /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
       Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2,
       Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2,

-      Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4,
+      Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2,

 
       /* VECTOR x VECTOR SHIFT / ROTATE */
 
       /* VECTOR x VECTOR SHIFT / ROTATE */

-      Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4,
-      Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4,
-      Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4,
+      Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4, Iop_Shl64x2,
+      Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4, Iop_Shr64x2,
+      Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4, Iop_Sar64x2,
+      Iop_Sal8x16, Iop_Sal16x8, Iop_Sal32x4, Iop_Sal64x2,

       Iop_Rol8x16, Iop_Rol16x8, Iop_Rol32x4,
 
       Iop_Rol8x16, Iop_Rol16x8, Iop_Rol32x4,
 

+      /* VECTOR x VECTOR SATURATING SHIFT */
+      Iop_QShl8x16, Iop_QShl16x8, Iop_QShl32x4, Iop_QShl64x2,
+      Iop_QSal8x16, Iop_QSal16x8, Iop_QSal32x4, Iop_QSal64x2,
+      /* VECTOR x INTEGER SATURATING SHIFT */
+      Iop_QShlN8Sx16, Iop_QShlN16Sx8, Iop_QShlN32Sx4, Iop_QShlN64Sx2,
+      Iop_QShlN8x16, Iop_QShlN16x8, Iop_QShlN32x4, Iop_QShlN64x2,
+      Iop_QSalN8x16, Iop_QSalN16x8, Iop_QSalN32x4, Iop_QSalN64x2,
+

       /* NARROWING -- narrow 2xV128 into 1xV128, hi half from left arg */
       /* Note: the 16{U,S} and 32{U,S} are the pre-narrow lane widths. */
       Iop_QNarrow16Ux8, Iop_QNarrow32Ux4,
       Iop_QNarrow16Sx8, Iop_QNarrow32Sx4,
       Iop_Narrow16x8, Iop_Narrow32x4,
       /* NARROWING -- narrow 2xV128 into 1xV128, hi half from left arg */
       /* Note: the 16{U,S} and 32{U,S} are the pre-narrow lane widths. */
       Iop_QNarrow16Ux8, Iop_QNarrow32Ux4,
       Iop_QNarrow16Sx8, Iop_QNarrow32Sx4,
       Iop_Narrow16x8, Iop_Narrow32x4,

-
-      /* INTERLEAVING -- interleave lanes from low or high halves of
+      /* Shortening V128->I64, lo half from each element */
+      Iop_Shorten16x8, Iop_Shorten32x4, Iop_Shorten64x2,
+      /* Saturating shortening from signed source to signed/unsigned destination */
+      Iop_QShortenS16Sx8, Iop_QShortenS32Sx4, Iop_QShortenS64Sx2,
+      Iop_QShortenU16Sx8, Iop_QShortenU32Sx4, Iop_QShortenU64Sx2,
+      /* Saturating shortening from unsigned source to unsigned destination */
+      Iop_QShortenU16Ux8, Iop_QShortenU32Ux4, Iop_QShortenU64Ux2,
+
+      /* WIDENING */
+      /* Longening --- sign or zero extends each element of the argument
+         vector to the twice original size. The resulting vector consists of
+         the same number of elements but each element and the vector itself
+         are two times wider.
+         All operations are I64->V128.
+         Example
+            Iop_Longen32Sx2( [a, b] ) = [c, d]
+               where c = Iop_32Sto64(a) and d = Iop_32Sto64(b) */
+      Iop_Longen8Ux8, Iop_Longen16Ux4, Iop_Longen32Ux2,
+      Iop_Longen8Sx8, Iop_Longen16Sx4, Iop_Longen32Sx2,
+
+      /* INTERLEAVING */
+      /* Interleave lanes from low or high halves of

          operands.  Most-significant result lane is from the left
          arg. */
       Iop_InterleaveHI8x16, Iop_InterleaveHI16x8,
       Iop_InterleaveHI32x4, Iop_InterleaveHI64x2,
          operands.  Most-significant result lane is from the left
          arg. */
       Iop_InterleaveHI8x16, Iop_InterleaveHI16x8,
       Iop_InterleaveHI32x4, Iop_InterleaveHI64x2,

-      Iop_InterleaveLO8x16, Iop_InterleaveLO16x8, 
+      Iop_InterleaveLO8x16, Iop_InterleaveLO16x8,

       Iop_InterleaveLO32x4, Iop_InterleaveLO64x2,
       Iop_InterleaveLO32x4, Iop_InterleaveLO64x2,

+      /* Interleave odd/even lanes of operands.  Most-significant result lane
+         is from the left arg. */
+      Iop_InterleaveOddLanes8x16, Iop_InterleaveEvenLanes8x16,
+      Iop_InterleaveOddLanes16x8, Iop_InterleaveEvenLanes16x8,
+      Iop_InterleaveOddLanes32x4, Iop_InterleaveEvenLanes32x4,
+
+      /* CONCATENATION -- build a new value by concatenating either
+         the even or odd lanes of both operands. */
+      Iop_CatOddLanes8x16, Iop_CatOddLanes16x8, Iop_CatOddLanes32x4,
+      Iop_CatEvenLanes8x16, Iop_CatEvenLanes16x8, Iop_CatEvenLanes32x4,
+
+      /* GET elements of VECTOR
+         GET is binop (V128, I8) -> I<elem_size> */
+      /* Note: the arm back-end handles only constant second argument. */
+      Iop_GetElem8x16, Iop_GetElem16x8, Iop_GetElem32x4, Iop_GetElem64x2,

 
       /* DUPLICATING -- copy value to all lanes */
 
       /* DUPLICATING -- copy value to all lanes */

-      Iop_Dup8x16, Iop_Dup16x8, Iop_Dup32x4,
+      Iop_Dup8x16,   Iop_Dup16x8,   Iop_Dup32x4,
+
+      /* EXTRACT -- copy 16-arg3 highest bytes from arg1 to 16-arg3 lowest bytes
+         of result and arg3 lowest bytes of arg2 to arg3 highest bytes of
+         result.
+         It is a triop: (V128, V128, I8) -> V128 */
+      /* Note: the ARM back end handles only constant arg3 in this operation. */
+      Iop_ExtractV128,
+
+      /* REVERSE the order of elements in each Half-words, Words,
+         Double-words */
+      /* Examples:
+            Reverse32_16x8([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g]
+            Reverse64_16x8([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e] */
+      Iop_Reverse16_8x16,
+      Iop_Reverse32_8x16, Iop_Reverse32_16x8,
+      Iop_Reverse64_8x16, Iop_Reverse64_16x8, Iop_Reverse64_32x4,

 
       /* PERMUTING -- copy src bytes to dst,
          as indexed by control vector bytes:
             for i in 0 .. 15 . result[i] = argL[ argR[i] ] 
          argR[i] values may only be in the range 0 .. 15, else behaviour
          is undefined. */
 
       /* PERMUTING -- copy src bytes to dst,
          as indexed by control vector bytes:
             for i in 0 .. 15 . result[i] = argL[ argR[i] ] 
          argR[i] values may only be in the range 0 .. 15, else behaviour
          is undefined. */

-      Iop_Perm8x16
+      Iop_Perm8x16,
+
+      /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate
+         See floating-point equiwalents for details. */
+      Iop_Recip32x4, Iop_Rsqrte32x4

    }
    IROp;
 
    }
    IROp;
 


@@ -1176,6 +1454,8 @@ extern IRExpr** mkIRExprVec_6 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*,
                                 IRExpr*, IRExpr* );
 extern IRExpr** mkIRExprVec_7 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*,
                                 IRExpr*, IRExpr*, IRExpr* );
                                 IRExpr*, IRExpr* );
 extern IRExpr** mkIRExprVec_7 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*,
                                 IRExpr*, IRExpr*, IRExpr* );

+extern IRExpr** mkIRExprVec_8 ( IRExpr*, IRExpr*, IRExpr*, IRExpr*,
+                                IRExpr*, IRExpr*, IRExpr*, IRExpr*);

 
 /* IRExpr copiers:
    - shallowCopy: shallow-copy (ie. create a new vector that shares the
 
 /* IRExpr copiers:
    - shallowCopy: shallow-copy (ie. create a new vector that shares the

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/test_main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/test_main.c
index dad12702b64673deaba0bf44ec3e0a84983148dc..2fc41a63546ed4696b60ebd021d1dd53d813f4d8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/test_main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/test_main.c
@@ -1647,13 +1647,21 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
          return binary16Ix8(mce, vatom1, vatom2);
 
       case Iop_Sub32x4:
          return binary16Ix8(mce, vatom1, vatom2);
 
       case Iop_Sub32x4:

+      case Iop_QSub32Sx4:
+      case Iop_QSub32Ux4:

       case Iop_CmpGT32Sx4:
       case Iop_CmpEQ32x4:
       case Iop_Add32x4:
       case Iop_CmpGT32Sx4:
       case Iop_CmpEQ32x4:
       case Iop_Add32x4:

+      case Iop_QAdd32Ux4:
+      case Iop_QAdd32Sx4:

          return binary32Ix4(mce, vatom1, vatom2);
 
       case Iop_Sub64x2:
          return binary32Ix4(mce, vatom1, vatom2);
 
       case Iop_Sub64x2:

+      case Iop_QSub64Ux2:
+      case Iop_QSub64Sx2:

       case Iop_Add64x2:
       case Iop_Add64x2:

+      case Iop_QAdd64Ux2:
+      case Iop_QAdd64Sx2:

          return binary64Ix2(mce, vatom1, vatom2);
 
       case Iop_QNarrow32Sx4:
          return binary64Ix2(mce, vatom1, vatom2);
 
       case Iop_QNarrow32Sx4:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/useful/cpuid.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/useful/cpuid.c
new file mode 100644 (file)
index 0000000..30d88f2
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/VEX/useful/cpuid.c
@@ -0,0 +1,72 @@
+
+#include <stdio.h>
+
+typedef  unsigned int            UInt;
+typedef  unsigned long long int  ULong;
+
+void cpuid ( UInt* eax, UInt* ebx, UInt* ecx, UInt* edx, 
+             UInt index, UInt ecx_in )
+{
+   UInt a,b,c,d;
+   asm volatile ("cpuid"
+                 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
+                 : "0" (index), "2"(ecx_in) );
+   *eax = a; *ebx = b; *ecx = c; *edx = d;
+   printf("%08x %08x -> %08x %08x %08x %08x\n",
+          index,ecx_in, a,b,c,d );
+}
+
+int main ( void )
+{
+  UInt eax, ebx, ecx, edx;
+  UInt maxidx, maxextidx, i,ecx_in;
+
+  printf("\n");
+  cpuid(&eax,&ebx,&ecx,&edx, 0,0);
+  maxidx = eax;
+  for (i = 1; i <= maxidx +2; i++) {
+
+    cpuid(&eax,&ebx,&ecx,&edx, i,0);
+
+    if (i == 4) {
+      printf("\n");
+      for (ecx_in = 1; ecx_in < 10; ecx_in++) {
+         cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in);
+      }
+      printf("\n");
+    }
+
+    if (i == 0xb) {
+      printf("\n");
+      for (ecx_in = 1; ecx_in < 10; ecx_in++) {
+         cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in);
+      }
+      printf("\n");
+    }
+
+    if (i == 0xd) {
+      printf("\n");
+      for (ecx_in = 1; ecx_in < 5; ecx_in++) {
+         cpuid(&eax,&ebx,&ecx,&edx, i,ecx_in);
+      }
+      printf("\n");
+    }
+
+
+  }
+
+  printf("\n");
+
+  cpuid(&eax,&ebx,&ecx,&edx, 0x80000000,0);
+  maxextidx = eax;
+  for (i = 0x80000001; i <= maxextidx +2; i++) {
+     cpuid(&eax,&ebx,&ecx,&edx, i,0);
+  }
+
+  printf("invalid\n");
+  cpuid(&eax,&ebx,&ecx,&edx, 1234,0);
+  cpuid(&eax,&ebx,&ecx,&edx, 0x800004d3,0);
+
+
+  return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/aclocal.m4 b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/aclocal.m4
index 4c13db2be33519d2f68e4735584621520eed2bf6..84ad65fb3a8b467cc8eb09d9825f0e77f550d52a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/aclocal.m4
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/aclocal.m4
@@ -13,13 +13,14 @@
 
 m4_ifndef([AC_AUTOCONF_VERSION],
   [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl
 
 m4_ifndef([AC_AUTOCONF_VERSION],
   [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl

-m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.65],,
-[m4_warning([this file was generated for autoconf 2.65.
+m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.67],,
+[m4_warning([this file was generated for autoconf 2.67.

 You have another version of autoconf.  It may work, but is not guaranteed to.
 If you have problems, you may need to regenerate the build system entirely.
 To do so, use the procedure documented by the package, typically `autoreconf'.])])
 
 # pkg.m4 - Macros to locate and utilise pkg-config.            -*- Autoconf -*-
 You have another version of autoconf.  It may work, but is not guaranteed to.
 If you have problems, you may need to regenerate the build system entirely.
 To do so, use the procedure documented by the package, typically `autoreconf'.])])
 
 # pkg.m4 - Macros to locate and utilise pkg-config.            -*- Autoconf -*-

+# serial 1 (pkg-config-0.24)

 # 
 # Copyright © 2004 Scott James Remnant <scott@netsplit.com>.
 #
 # 
 # Copyright © 2004 Scott James Remnant <scott@netsplit.com>.
 #


@@ -47,7 +48,10 @@ To do so, use the procedure documented by the package, typically `autoreconf'.])
 AC_DEFUN([PKG_PROG_PKG_CONFIG],
 [m4_pattern_forbid([^_?PKG_[A-Z_]+$])
 m4_pattern_allow([^PKG_CONFIG(_PATH)?$])
 AC_DEFUN([PKG_PROG_PKG_CONFIG],
 [m4_pattern_forbid([^_?PKG_[A-Z_]+$])
 m4_pattern_allow([^PKG_CONFIG(_PATH)?$])

-AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility])dnl
+AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility])
+AC_ARG_VAR([PKG_CONFIG_PATH], [directories to add to pkg-config's search path])
+AC_ARG_VAR([PKG_CONFIG_LIBDIR], [path overriding pkg-config's built-in search path])
+

 if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
        AC_PATH_TOOL([PKG_CONFIG], [pkg-config])
 fi
 if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
        AC_PATH_TOOL([PKG_CONFIG], [pkg-config])
 fi


@@ -60,7 +64,6 @@ if test -n "$PKG_CONFIG"; then
                AC_MSG_RESULT([no])
                PKG_CONFIG=""
        fi
                AC_MSG_RESULT([no])
                PKG_CONFIG=""
        fi

-               

 fi[]dnl
 ])# PKG_PROG_PKG_CONFIG
 
 fi[]dnl
 ])# PKG_PROG_PKG_CONFIG
 


@@ -69,34 +72,31 @@ fi[]dnl
 # Check to see whether a particular set of modules exists.  Similar
 # to PKG_CHECK_MODULES(), but does not set variables or print errors.
 #
 # Check to see whether a particular set of modules exists.  Similar
 # to PKG_CHECK_MODULES(), but does not set variables or print errors.
 #

-#
-# Similar to PKG_CHECK_MODULES, make sure that the first instance of
-# this or PKG_CHECK_MODULES is called, or make sure to call
-# PKG_CHECK_EXISTS manually
+# Please remember that m4 expands AC_REQUIRE([PKG_PROG_PKG_CONFIG])
+# only at the first occurence in configure.ac, so if the first place
+# it's called might be skipped (such as if it is within an "if", you
+# have to call PKG_CHECK_EXISTS manually

 # --------------------------------------------------------------
 AC_DEFUN([PKG_CHECK_EXISTS],
 [AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
 if test -n "$PKG_CONFIG" && \
     AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then
 # --------------------------------------------------------------
 AC_DEFUN([PKG_CHECK_EXISTS],
 [AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl
 if test -n "$PKG_CONFIG" && \
     AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then

-  m4_ifval([$2], [$2], [:])
+  m4_default([$2], [:])

 m4_ifvaln([$3], [else
   $3])dnl
 fi])
 
 m4_ifvaln([$3], [else
   $3])dnl
 fi])
 

-

 # _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES])
 # ---------------------------------------------
 m4_define([_PKG_CONFIG],
 # _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES])
 # ---------------------------------------------
 m4_define([_PKG_CONFIG],

-[if test -n "$PKG_CONFIG"; then
-    if test -n "$$1"; then
-        pkg_cv_[]$1="$$1"
-    else
-        PKG_CHECK_EXISTS([$3],
-                         [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null`],
-                        [pkg_failed=yes])
-    fi
-else
-       pkg_failed=untried
+[if test -n "$$1"; then
+    pkg_cv_[]$1="$$1"
+ elif test -n "$PKG_CONFIG"; then
+    PKG_CHECK_EXISTS([$3],
+                     [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null`],
+                    [pkg_failed=yes])
+ else
+    pkg_failed=untried

 fi[]dnl
 ])# _PKG_CONFIG
 
 fi[]dnl
 ])# _PKG_CONFIG
 


@@ -138,16 +138,17 @@ and $1[]_LIBS to avoid the need to call pkg-config.
 See the pkg-config man page for more details.])
 
 if test $pkg_failed = yes; then
 See the pkg-config man page for more details.])
 
 if test $pkg_failed = yes; then

+       AC_MSG_RESULT([no])

         _PKG_SHORT_ERRORS_SUPPORTED
         if test $_pkg_short_errors_supported = yes; then
         _PKG_SHORT_ERRORS_SUPPORTED
         if test $_pkg_short_errors_supported = yes; then

-               $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --errors-to-stdout --print-errors "$2"`
+               $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors "$2" 2>&1`

         else 
         else 

-               $1[]_PKG_ERRORS=`$PKG_CONFIG --errors-to-stdout --print-errors "$2"`
+               $1[]_PKG_ERRORS=`$PKG_CONFIG --print-errors "$2" 2>&1`

         fi
        # Put the nasty error message in config.log where it belongs
        echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD
 
         fi
        # Put the nasty error message in config.log where it belongs
        echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD
 

-       ifelse([$4], , [AC_MSG_ERROR(dnl
+       m4_default([$4], [AC_MSG_ERROR(

 [Package requirements ($2) were not met:
 
 $$1_PKG_ERRORS
 [Package requirements ($2) were not met:
 
 $$1_PKG_ERRORS


@@ -155,25 +156,24 @@ $$1_PKG_ERRORS
 Consider adjusting the PKG_CONFIG_PATH environment variable if you
 installed software in a non-standard prefix.
 
 Consider adjusting the PKG_CONFIG_PATH environment variable if you
 installed software in a non-standard prefix.
 

-_PKG_TEXT
-])],
-               [AC_MSG_RESULT([no])
-                $4])
+_PKG_TEXT])dnl
+        ])

 elif test $pkg_failed = untried; then
 elif test $pkg_failed = untried; then

-       ifelse([$4], , [AC_MSG_FAILURE(dnl
+       AC_MSG_RESULT([no])
+       m4_default([$4], [AC_MSG_FAILURE(

 [The pkg-config script could not be found or is too old.  Make sure it
 is in your PATH or set the PKG_CONFIG environment variable to the full
 path to pkg-config.
 
 _PKG_TEXT
 
 [The pkg-config script could not be found or is too old.  Make sure it
 is in your PATH or set the PKG_CONFIG environment variable to the full
 path to pkg-config.
 
 _PKG_TEXT
 

-To get pkg-config, see <http://pkg-config.freedesktop.org/>.])],
-               [$4])
+To get pkg-config, see <http://pkg-config.freedesktop.org/>.])dnl
+        ])

 else
        $1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS
        $1[]_LIBS=$pkg_cv_[]$1[]_LIBS
         AC_MSG_RESULT([yes])
 else
        $1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS
        $1[]_LIBS=$pkg_cv_[]$1[]_LIBS
         AC_MSG_RESULT([yes])

-       ifelse([$3], , :, [$3])
+       $3

 fi[]dnl
 ])# PKG_CHECK_MODULES
 
 fi[]dnl
 ])# PKG_CHECK_MODULES
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/auxprogs/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/auxprogs/Makefile.am
index 38a643e92610232bf582cd5ddfb8d21c381fd1fd..1563f4bca2d877d9e00989a63893e05f5bc10411 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/auxprogs/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/auxprogs/Makefile.am
@@ -29,4 +29,6 @@ valgrind_listener_CPPFLAGS  = $(AM_CPPFLAGS_PRI) -I$(top_srcdir)/coregrind
 valgrind_listener_CFLAGS    = $(AM_CFLAGS_PRI)
 valgrind_listener_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 valgrind_listener_LDFLAGS   = $(AM_CFLAGS_PRI)
 valgrind_listener_CFLAGS    = $(AM_CFLAGS_PRI)
 valgrind_listener_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 valgrind_listener_LDFLAGS   = $(AM_CFLAGS_PRI)

-
+if VGCONF_PLATFORMS_INCLUDE_X86_DARWIN
+valgrind_listener_LDFLAGS   += -Wl,-read_only_relocs -Wl,suppress
+endif

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/auxprogs/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/auxprogs/Makefile.in
index 05d20a99719d8f86a83700a2d5a167017688a6c7..3b2e3512f02a8b3788866118ceec5a3eda003ed3 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/auxprogs/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/auxprogs/Makefile.in
@@ -45,6 +45,7 @@ host_triplet = @host@
 DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am
 bin_PROGRAMS = valgrind-listener$(EXEEXT)
 DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am
 bin_PROGRAMS = valgrind-listener$(EXEEXT)

+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_1 = -Wl,-read_only_relocs -Wl,suppress

 subdir = auxprogs
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = auxprogs
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -113,6 +114,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -147,14 +149,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -237,7 +243,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -296,7 +304,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -311,8 +319,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -378,7 +386,7 @@ valgrind_listener_SOURCES = valgrind-listener.c
 valgrind_listener_CPPFLAGS = $(AM_CPPFLAGS_PRI) -I$(top_srcdir)/coregrind
 valgrind_listener_CFLAGS = $(AM_CFLAGS_PRI)
 valgrind_listener_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 valgrind_listener_CPPFLAGS = $(AM_CPPFLAGS_PRI) -I$(top_srcdir)/coregrind
 valgrind_listener_CFLAGS = $(AM_CFLAGS_PRI)
 valgrind_listener_CCASFLAGS = $(AM_CCASFLAGS_PRI)

-valgrind_listener_LDFLAGS = $(AM_CFLAGS_PRI)
+valgrind_listener_LDFLAGS = $(AM_CFLAGS_PRI) $(am__append_1)

 all: all-am
 
 .SUFFIXES:
 all: all-am
 
 .SUFFIXES:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/Makefile.am
index fc1c4007da4f92e31d1843148cf416d58be79d60..816808139e33ed94847652e3d38696051ab7c59f 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/Makefile.am
@@ -8,7 +8,7 @@ EXTRA_DIST = \
 # Headers, etc
 #----------------------------------------------------------------------------
 
 # Headers, etc
 #----------------------------------------------------------------------------
 

-bin_SCRIPTS = cg_annotate
+bin_SCRIPTS = cg_annotate cg_diff

 
 noinst_HEADERS = \
        cg_arch.h \
 
 noinst_HEADERS = \
        cg_arch.h \


@@ -26,6 +26,9 @@ cg_merge_CPPFLAGS  = $(AM_CPPFLAGS_PRI)
 cg_merge_CFLAGS    = $(AM_CFLAGS_PRI)
 cg_merge_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 cg_merge_LDFLAGS   = $(AM_CFLAGS_PRI)
 cg_merge_CFLAGS    = $(AM_CFLAGS_PRI)
 cg_merge_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 cg_merge_LDFLAGS   = $(AM_CFLAGS_PRI)

+if VGCONF_PLATFORMS_INCLUDE_X86_DARWIN
+cg_merge_LDFLAGS   += -Wl,-read_only_relocs -Wl,suppress
+endif

 
 #----------------------------------------------------------------------------
 # cachegrind-<platform>
 
 #----------------------------------------------------------------------------
 # cachegrind-<platform>


@@ -55,6 +58,13 @@ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
        $(CACHEGRIND_SOURCES_COMMON)
 if VGCONF_HAVE_PLATFORM_SEC
 cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
        $(CACHEGRIND_SOURCES_COMMON)


@@ -68,6 +78,12 @@ cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 
 endif
 
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/Makefile.in
index 32ac458d15785a77dc4a3e7bd3374e9f167a1db5..03686c08a3424601fb57947b4344e6448afa3a10 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/Makefile.in
@@ -45,27 +45,13 @@ build_triplet = @build@
 host_triplet = @host@
 DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(srcdir)/cg_annotate.in \
 host_triplet = @host@
 DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(srcdir)/cg_annotate.in \

-       $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds
+       $(srcdir)/cg_diff.in $(top_srcdir)/Makefile.all.am \
+       $(top_srcdir)/Makefile.tool.am

 bin_PROGRAMS = cg_merge$(EXEEXT)
 bin_PROGRAMS = cg_merge$(EXEEXT)

+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_1 = -Wl,-read_only_relocs -Wl,suppress

 noinst_PROGRAMS = cachegrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)
 noinst_PROGRAMS = cachegrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = cachegrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = cachegrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = cachegrind
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = cachegrind
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4


@@ -74,7 +60,7 @@ am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
        $(ACLOCAL_M4)
 mkinstalldirs = $(install_sh) -d
 CONFIG_HEADER = $(top_builddir)/config.h
        $(ACLOCAL_M4)
 mkinstalldirs = $(install_sh) -d
 CONFIG_HEADER = $(top_builddir)/config.h

-CONFIG_CLEAN_FILES = cg_annotate
+CONFIG_CLEAN_FILES = cg_annotate cg_diff

 CONFIG_CLEAN_VPATH_FILES =
 am__installdirs = "$(DESTDIR)$(bindir)" "$(DESTDIR)$(bindir)"
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = cachegrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)
 CONFIG_CLEAN_VPATH_FILES =
 am__installdirs = "$(DESTDIR)$(bindir)" "$(DESTDIR)$(bindir)"
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@am__EXEEXT_1 = cachegrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@$(EXEEXT)


@@ -89,10 +75,6 @@ am_cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am__objects_1)
 cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
        $(am__objects_1)
 cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) \
-       -o $@

 am__cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = cg_main.c \
        cg-x86-amd64.c cg-ppc32.c cg-ppc64.c cg-arm.c
 am__objects_2 =  \
 am__cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = cg_main.c \
        cg-x86-amd64.c cg-ppc32.c cg-ppc64.c cg-arm.c
 am__objects_2 =  \


@@ -105,10 +87,6 @@ am__objects_2 =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) \
-       -o $@

 am_cg_merge_OBJECTS = cg_merge-cg_merge.$(OBJEXT)
 cg_merge_OBJECTS = $(am_cg_merge_OBJECTS)
 cg_merge_LDADD = $(LDADD)
 am_cg_merge_OBJECTS = cg_merge-cg_merge.$(OBJEXT)
 cg_merge_OBJECTS = $(am_cg_merge_OBJECTS)
 cg_merge_LDADD = $(LDADD)


@@ -229,6 +207,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -263,14 +242,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -354,7 +337,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -413,7 +398,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -428,8 +413,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -492,37 +477,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -531,32 +516,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -641,7 +622,7 @@ EXTRA_DIST = \
 #----------------------------------------------------------------------------
 # Headers, etc
 #----------------------------------------------------------------------------
 #----------------------------------------------------------------------------
 # Headers, etc
 #----------------------------------------------------------------------------

-bin_SCRIPTS = cg_annotate
+bin_SCRIPTS = cg_annotate cg_diff

 noinst_HEADERS = \
        cg_arch.h \
        cg_branchpred.c \
 noinst_HEADERS = \
        cg_arch.h \
        cg_branchpred.c \


@@ -651,7 +632,7 @@ cg_merge_SOURCES = cg_merge.c
 cg_merge_CPPFLAGS = $(AM_CPPFLAGS_PRI)
 cg_merge_CFLAGS = $(AM_CFLAGS_PRI)
 cg_merge_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 cg_merge_CPPFLAGS = $(AM_CPPFLAGS_PRI)
 cg_merge_CFLAGS = $(AM_CFLAGS_PRI)
 cg_merge_CCASFLAGS = $(AM_CCASFLAGS_PRI)

-cg_merge_LDFLAGS = $(AM_CFLAGS_PRI)
+cg_merge_LDFLAGS = $(AM_CFLAGS_PRI) $(am__append_1)

 CACHEGRIND_SOURCES_COMMON = \
        cg_main.c \
        cg-x86-amd64.c \
 CACHEGRIND_SOURCES_COMMON = \
        cg_main.c \
        cg-x86-amd64.c \


@@ -677,6 +658,13 @@ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

+cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(CACHEGRIND_SOURCES_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(CACHEGRIND_SOURCES_COMMON)
 


@@ -695,8 +683,14 @@ cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(cachegrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -732,6 +726,8 @@ $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
 $(am__aclocal_m4_deps):
 cg_annotate: $(top_builddir)/config.status $(srcdir)/cg_annotate.in
        cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
 $(am__aclocal_m4_deps):
 cg_annotate: $(top_builddir)/config.status $(srcdir)/cg_annotate.in
        cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@

+cg_diff: $(top_builddir)/config.status $(srcdir)/cg_diff.in
+       cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@

 install-binPROGRAMS: $(bin_PROGRAMS)
        @$(NORMAL_INSTALL)
        test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)"
 install-binPROGRAMS: $(bin_PROGRAMS)
        @$(NORMAL_INSTALL)
        test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)"


@@ -1196,16 +1192,14 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) $(SCRIPTS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(bindir)" "$(DESTDIR)$(bindir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done
 all-am: Makefile $(PROGRAMS) $(SCRIPTS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(bindir)" "$(DESTDIR)$(bindir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -1222,7 +1216,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -1231,7 +1224,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-binPROGRAMS clean-generic clean-local \
 clean: clean-recursive
 
 clean-am: clean-binPROGRAMS clean-generic clean-local \


@@ -1303,9 +1295,8 @@ ps-am:
 
 uninstall-am: uninstall-binPROGRAMS uninstall-binSCRIPTS
 
 
 uninstall-am: uninstall-binPROGRAMS uninstall-binSCRIPTS
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-binPROGRAMS \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-binPROGRAMS \


@@ -1388,65 +1379,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_annotate.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_annotate.in
index 29d94264ebf66c56d11b6a24299088976385323e..9dc9565841864d5387537494ee72105a9bfa9d87 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_annotate.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_annotate.in
@@ -84,7 +84,7 @@ my %fn_totals;
 
 # Individual CCs, organised by filename and line_num for easy annotation.
 # hash(filename => hash(line_num => CC array))
 
 # Individual CCs, organised by filename and line_num for easy annotation.
 # hash(filename => hash(line_num => CC array))

-my %all_ind_CCs;
+my %allCCs;

 
 # Files chosen for annotation on the command line.  
 # key = basename (trimmed of any directory), value = full filename
 
 # Files chosen for annotation on the command line.  
 # key = basename (trimmed of any directory), value = full filename


@@ -120,7 +120,7 @@ my @sort_order;
 # handled this proportion of all the events thresholded.
 my @thresholds;
 
 # handled this proportion of all the events thresholded.
 my @thresholds;
 

-my $default_threshold = 99;
+my $default_threshold = 0.1;

 
 my $single_threshold  = $default_threshold;
 
 
 my $single_threshold  = $default_threshold;
 


@@ -149,8 +149,8 @@ usage: cg_annotate [options] cachegrind-out-file [source-files...]
     --version             show version
     --show=A,B,C          only show figures for events A,B,C [all]
     --sort=A,B,C          sort columns by events A,B,C [event column order]
     --version             show version
     --show=A,B,C          only show figures for events A,B,C [all]
     --sort=A,B,C          sort columns by events A,B,C [event column order]

-    --threshold=<0--100>  percentage of counts (of primary sort event) we
-                          are interested in [$default_threshold%]
+    --threshold=<0--20>   a function is shown if it accounts for more than x% of
+                          the counts of the primary sort event [$default_threshold]

     --auto=yes|no         annotate all source files containing functions
                           that helped reach the event count threshold [no]
     --context=N           print N lines of context before and after
     --auto=yes|no         annotate all source files containing functions
                           that helped reach the event count threshold [no]
     --context=N           print N lines of context before and after


@@ -168,6 +168,12 @@ END
 # Used in various places of output.
 my $fancy = '-' x 80 . "\n";
 
 # Used in various places of output.
 my $fancy = '-' x 80 . "\n";
 

+sub safe_div($$)
+{
+    my ($x, $y) = @_;
+    return ($y == 0 ? 0 : $x / $y);
+}
+

 #-----------------------------------------------------------------------------
 # Argument and option handling
 #-----------------------------------------------------------------------------
 #-----------------------------------------------------------------------------
 # Argument and option handling
 #-----------------------------------------------------------------------------


@@ -211,7 +217,7 @@ sub process_cmd_line()
             # --threshold=X (tolerates a trailing '%')
             } elsif ($arg =~ /^--threshold=([\d\.]+)%?$/) {
                 $single_threshold = $1;
             # --threshold=X (tolerates a trailing '%')
             } elsif ($arg =~ /^--threshold=([\d\.]+)%?$/) {
                 $single_threshold = $1;

-                ($1 >= 0 && $1 <= 100) or die($usage);
+                ($1 >= 0 && $1 <= 20) or die($usage);

 
             # --auto=yes|no
             } elsif ($arg =~ /^--auto=yes$/) {
 
             # --auto=yes|no
             } elsif ($arg =~ /^--auto=yes$/) {


@@ -371,64 +377,61 @@ sub read_input_file()
     # the primary sort event, and 0% for the rest.
     if (not @thresholds) {
         foreach my $e (@sort_order) {
     # the primary sort event, and 0% for the rest.
     if (not @thresholds) {
         foreach my $e (@sort_order) {

-            push(@thresholds, 0);
+            push(@thresholds, 100);

         }
         $thresholds[0] = $single_threshold;
     }
 
         }
         $thresholds[0] = $single_threshold;
     }
 

-    my $curr_file;
-    my $curr_fn;
-    my $curr_name;
+    my $currFileName;
+    my $currFileFuncName;

 
 

-    my $curr_fn_CC = [];
-    my $curr_file_ind_CCs = {};     # hash(line_num => CC)
+    my $currFuncCC;
+    my $currFileCCs = {};     # hash(line_num => CC)

 
     # Read body of input file.
     while (<INPUTFILE>) {
         s/#.*$//;   # remove comments
 
     # Read body of input file.
     while (<INPUTFILE>) {
         s/#.*$//;   # remove comments

-        if (s/^(\d+)\s+//) {
-            my $line_num = $1;
+        if (s/^(-?\d+)\s+//) {
+            my $lineNum = $1;

             my $CC = line_to_CC($_);
             my $CC = line_to_CC($_);

-            add_array_a_to_b($CC, $curr_fn_CC);
+            defined($currFuncCC) || die;
+            add_array_a_to_b($CC, $currFuncCC);

             
             

-            # If curr_file is selected, add CC to curr_file list.  We look for
+            # If currFileName is selected, add CC to currFileName list.  We look for

             # full filename matches;  or, if auto-annotating, we have to
             # remember everything -- we won't know until the end what's needed.
             # full filename matches;  or, if auto-annotating, we have to
             # remember everything -- we won't know until the end what's needed.

-            if ($auto_annotate || defined $user_ann_files{$curr_file}) {
-                my $tmp = $curr_file_ind_CCs->{$line_num};
-                $tmp = [] unless defined $tmp;
-                add_array_a_to_b($CC, $tmp);
-                $curr_file_ind_CCs->{$line_num} = $tmp;
+            defined($currFileCCs) || die;
+            if ($auto_annotate || defined $user_ann_files{$currFileName}) {
+                my $currLineCC = $currFileCCs->{$lineNum};
+                if (not defined $currLineCC) {
+                    $currLineCC = [];
+                    $currFileCCs->{$lineNum} = $currLineCC;
+                }
+                add_array_a_to_b($CC, $currLineCC);

             }
 
         } elsif (s/^fn=(.*)$//) {
             }
 
         } elsif (s/^fn=(.*)$//) {

-            # Commit result from previous function
-            $fn_totals{$curr_name} = $curr_fn_CC if (defined $curr_name);
-
-            # Setup new one
-            $curr_fn = $1;
-            $curr_name = "$curr_file:$curr_fn";
-            $curr_fn_CC = $fn_totals{$curr_name};
-            $curr_fn_CC = [] unless (defined $curr_fn_CC);
+            $currFileFuncName = "$currFileName:$1";
+            $currFuncCC = $fn_totals{$currFileFuncName};
+            if (not defined $currFuncCC) {
+                $currFuncCC = [];
+                $fn_totals{$currFileFuncName} = $currFuncCC;
+            }

 
         } elsif (s/^fl=(.*)$//) {
 
         } elsif (s/^fl=(.*)$//) {

-            $all_ind_CCs{$curr_file} = $curr_file_ind_CCs 
-                if (defined $curr_file);
-
-            $curr_file = $1;
-            $curr_file_ind_CCs = $all_ind_CCs{$curr_file};
-            $curr_file_ind_CCs = {} unless (defined $curr_file_ind_CCs);
+            $currFileName = $1;
+            $currFileCCs = $allCCs{$currFileName};
+            if (not defined $currFileCCs) {
+                $currFileCCs = {};
+                $allCCs{$currFileName} = $currFileCCs;
+            }
+            # Assume that a "fn=" line is followed by a "fl=" line.
+            $currFileFuncName = undef;

 
         } elsif (s/^\s*$//) {
             # blank, do nothing
         
         } elsif (s/^summary:\s+//) {
 
         } elsif (s/^\s*$//) {
             # blank, do nothing
         
         } elsif (s/^summary:\s+//) {

-            # Finish up handling final filename/fn_name counts
-            $fn_totals{"$curr_file:$curr_fn"} = $curr_fn_CC 
-                if (defined $curr_file && defined $curr_fn);
-            $all_ind_CCs{$curr_file} = 
-                $curr_file_ind_CCs if (defined $curr_file);
-

             $summary_CC = line_to_CC($_);
             (scalar(@$summary_CC) == @events) 
                 or die("Line $.: summary event and total event mismatch\n");
             $summary_CC = line_to_CC($_);
             (scalar(@$summary_CC) == @events) 
                 or die("Line $.: summary event and total event mismatch\n");


@@ -497,7 +500,7 @@ sub mycmp ($$)
         $x = -1 unless defined $x;
         $y = -1 unless defined $y;
 
         $x = -1 unless defined $x;
         $y = -1 unless defined $y;
 

-        my $cmp = $y <=> $x;        # reverse sort
+        my $cmp = abs($y) <=> abs($x);      # reverse sort of absolute size

         if (0 != $cmp) {
             return $cmp;
         }
         if (0 != $cmp) {
             return $cmp;
         }


@@ -508,7 +511,7 @@ sub mycmp ($$)
 
 sub commify ($) {
     my ($val) = @_;
 
 sub commify ($) {
     my ($val) = @_;

-    1 while ($val =~ s/^(\d+)(\d{3})/$1,$2/);
+    1 while ($val =~ s/^(-?\d+)(\d{3})/$1,$2/);

     return $val;
 }
 
     return $val;
 }
 


@@ -614,16 +617,18 @@ sub print_summary_and_fn_totals ()
     # Print functions, stopping when the threshold has been reached.
     foreach my $fn_name (@fn_fullnames) {
 
     # Print functions, stopping when the threshold has been reached.
     foreach my $fn_name (@fn_fullnames) {
 

+        my $fn_CC = $fn_totals{$fn_name};
+

         # Stop when we've reached all the thresholds
         # Stop when we've reached all the thresholds

-        my $reached_all_thresholds = 1;
+        my $any_thresholds_exceeded = 0;

         foreach my $i (0 .. scalar @thresholds - 1) {
         foreach my $i (0 .. scalar @thresholds - 1) {

-            my $prop = $curr_totals[$i] * 100 / $summary_CC->[$sort_order[$i]];
-            $reached_all_thresholds &&= ($prop >= $thresholds[$i]);
+            my $prop = safe_div(abs($fn_CC->[$sort_order[$i]] * 100),
+                                abs($summary_CC->[$sort_order[$i]]));
+            $any_thresholds_exceeded ||= ($prop >= $thresholds[$i]);

         }
         }

-        last if $reached_all_thresholds;
+        last if not $any_thresholds_exceeded;

 
         # Print function results
 
         # Print function results

-        my $fn_CC = $fn_totals{$fn_name};

         print_CC($fn_CC, $fn_CC_col_widths);
         print(" $fn_name\n");
 
         print_CC($fn_CC, $fn_CC_col_widths);
         print(" $fn_name\n");
 


@@ -761,7 +766,7 @@ sub annotate_ann_files($)
             print("$fancy");
 
             # Get file's CCs
             print("$fancy");
 
             # Get file's CCs

-            my $src_file_CCs = $all_ind_CCs{$src_file};
+            my $src_file_CCs = $allCCs{$src_file};

             if (!defined $src_file_CCs) {
                 print("  No information has been collected for $src_file\n\n");
                 next LOOP;
             if (!defined $src_file_CCs) {
                 print("  No information has been collected for $src_file\n\n");
                 next LOOP;


@@ -877,7 +882,8 @@ sub annotate_ann_files($)
         foreach (my $i = 0; $i < @$summary_CC; $i++) {
             $percent_printed_CC->[$i] = 
                 sprintf("%.0f", 
         foreach (my $i = 0; $i < @$summary_CC; $i++) {
             $percent_printed_CC->[$i] = 
                 sprintf("%.0f", 

-                        $printed_totals_CC->[$i] / $summary_CC->[$i] * 100);
+                        100 * safe_div(abs($printed_totals_CC->[$i]),
+                                       abs($summary_CC->[$i])));

         }
         my $pp_CC_col_widths = compute_CC_col_widths($percent_printed_CC);
         print($fancy);
         }
         my $pp_CC_col_widths = compute_CC_col_widths($percent_printed_CC);
         print($fancy);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_diff.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_diff.in
new file mode 100644 (file)
index 0000000..951066e
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_diff.in
@@ -0,0 +1,328 @@
+#! @PERL@
+
+##--------------------------------------------------------------------##
+##--- Cachegrind's differencer.                         cg_diff.in ---##
+##--------------------------------------------------------------------##
+
+#  This file is part of Cachegrind, a Valgrind tool for cache
+#  profiling programs.
+#
+#  Copyright (C) 2002-2010 Nicholas Nethercote
+#     njn@valgrind.org
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of the
+#  License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+#  02111-1307, USA.
+#
+#  The GNU General Public License is contained in the file COPYING.
+
+#----------------------------------------------------------------------------
+# This is a very cut-down and modified version of cg_annotate.
+#----------------------------------------------------------------------------
+
+use warnings;
+use strict;
+
+#----------------------------------------------------------------------------
+# Global variables
+#----------------------------------------------------------------------------
+
+# Version number
+my $version = "@VERSION@";
+
+# Usage message.
+my $usage = <<END
+usage: cg_diff [options] <cachegrind-out-file1> <cachegrind-out-file2>
+
+  options for the user, with defaults in [ ], are:
+    -h --help             show this message
+    -v --version          show version
+    --mod-filename=<expr> a Perl search-and-replace expression that is applied
+                          to filenames, eg. --mod-filename='s/prog[0-9]/projN/'
+
+  cg_diff is Copyright (C) 2010-2010 Nicholas Nethercote.
+  and licensed under the GNU General Public License, version 2.
+  Bug reports, feedback, admiration, abuse, etc, to: njn\@valgrind.org.
+                                                
+END
+;
+
+# --mod-filename expression
+my $mod_filename = undef;
+
+#-----------------------------------------------------------------------------
+# Argument and option handling
+#-----------------------------------------------------------------------------
+sub process_cmd_line() 
+{
+    my ($file1, $file2) = (undef, undef);
+
+    for my $arg (@ARGV) { 
+
+        if ($arg =~ /^-/) {
+            # --version
+            if ($arg =~ /^-v$|^--version$/) {
+                die("cg_diff-$version\n");
+
+            } elsif ($arg =~ /^--mod-filename=(.*)/) {
+                $mod_filename = $1;
+
+            } else {            # -h and --help fall under this case
+                die($usage);
+            }
+
+        } elsif (not defined($file1)) {
+            $file1 = $arg;
+
+        } elsif (not defined($file2)) {
+            $file2 = $arg;
+
+        } else {
+            die($usage);
+        }
+    }
+
+    # Must have specified two input files.
+    if (not defined $file1 or not defined $file2) {
+        die($usage);
+    }
+
+    return ($file1, $file2);
+}
+
+#-----------------------------------------------------------------------------
+# Reading of input file
+#-----------------------------------------------------------------------------
+sub max ($$) 
+{
+    my ($x, $y) = @_;
+    return ($x > $y ? $x : $y);
+}
+
+# Add the two arrays;  any '.' entries are ignored.  Two tricky things:
+# 1. If $a2->[$i] is undefined, it defaults to 0 which is what we want; we turn
+#    off warnings to allow this.  This makes things about 10% faster than
+#    checking for definedness ourselves.
+# 2. We don't add an undefined count or a ".", even though it's value is 0,
+#    because we don't want to make an $a2->[$i] that is undef become 0
+#    unnecessarily.
+sub add_array_a_to_b ($$) 
+{
+    my ($a, $b) = @_;
+
+    my $n = max(scalar @$a, scalar @$b);
+    $^W = 0;
+    foreach my $i (0 .. $n-1) {
+        $b->[$i] += $a->[$i] if (defined $a->[$i] && "." ne $a->[$i]);
+    }
+    $^W = 1;
+}
+
+sub sub_array_b_from_a ($$) 
+{
+    my ($a, $b) = @_;
+
+    my $n = max(scalar @$a, scalar @$b);
+    $^W = 0;
+    foreach my $i (0 .. $n-1) {
+        $a->[$i] -= $b->[$i];       # XXX: doesn't handle '.' entries
+    }
+    $^W = 1;
+}
+
+# Add each event count to the CC array.  '.' counts become undef, as do
+# missing entries (implicitly).
+sub line_to_CC ($$)
+{
+    my ($line, $numEvents) = @_;
+
+    my @CC = (split /\s+/, $line);
+    (@CC <= $numEvents) or die("Line $.: too many event counts\n");
+    return \@CC;
+}
+
+sub read_input_file($) 
+{
+    my ($input_file) = @_;
+
+    open(INPUTFILE, "< $input_file") 
+         || die "Cannot open $input_file for reading\n";
+
+    # Read "desc:" lines.
+    my $desc;
+    my $line;
+    while ($line = <INPUTFILE>) {
+        if ($line =~ s/desc:\s+//) {
+            $desc .= $line;
+        } else {
+            last;
+        }
+    }
+
+    # Read "cmd:" line (Nb: will already be in $line from "desc:" loop above).
+    ($line =~ s/^cmd:\s+//) or die("Line $.: missing command line\n");
+    my $cmd = $line;
+    chomp($cmd);    # Remove newline
+
+    # Read "events:" line.  We make a temporary hash in which the Nth event's
+    # value is N, which is useful for handling --show/--sort options below.
+    $line = <INPUTFILE>;
+    (defined $line && $line =~ s/^events:\s+//) 
+        or die("Line $.: missing events line\n");
+    my @events = split(/\s+/, $line);
+    my $numEvents = scalar @events;
+
+    my $currFileName;
+    my $currFileFuncName;
+
+    my %CCs;                    # hash("$filename#$funcname" => CC array)
+    my $currCC = undef;         # CC array
+
+    my $summaryCC;
+
+    # Read body of input file.
+    while (<INPUTFILE>) {
+        s/#.*$//;   # remove comments
+        if (s/^(\d+)\s+//) {
+            my $CC = line_to_CC($_, $numEvents);
+            defined($currCC) || die;
+            add_array_a_to_b($CC, $currCC);
+
+        } elsif (s/^fn=(.*)$//) {
+            defined($currFileName) || die;
+            $currFileFuncName = "$currFileName#$1";
+            $currCC = $CCs{$currFileFuncName};
+            if (not defined $currCC) {
+                $currCC = [];
+                $CCs{$currFileFuncName} = $currCC;
+            }
+
+        } elsif (s/^fl=(.*)$//) {
+            $currFileName = $1;
+            if (defined $mod_filename) {
+                eval "\$currFileName =~ $mod_filename";
+            }
+            # Assume that a "fn=" line is followed by a "fl=" line.
+            $currFileFuncName = undef;  
+
+        } elsif (s/^\s*$//) {
+            # blank, do nothing
+        
+        } elsif (s/^summary:\s+//) {
+            $summaryCC = line_to_CC($_, $numEvents);
+            (scalar(@$summaryCC) == @events) 
+                or die("Line $.: summary event and total event mismatch\n");
+
+        } else {
+            warn("WARNING: line $. malformed, ignoring\n");
+        }
+    }
+
+    # Check if summary line was present
+    if (not defined $summaryCC) {
+        die("missing final summary line, aborting\n");
+    }
+
+    close(INPUTFILE);
+
+    return ($cmd, \@events, \%CCs, $summaryCC);
+}
+
+#----------------------------------------------------------------------------
+# "main()"
+#----------------------------------------------------------------------------
+# Commands seen in the files.  Need not match.
+my $cmd1;
+my $cmd2;
+
+# Events seen in the files.  They must match.
+my $events1;
+my $events2;
+
+# Individual CCs, organised by filename/funcname/line_num.
+# hashref("$filename#$funcname", CC array)
+my $CCs1;
+my $CCs2;
+
+# Total counts for summary (an arrayref).
+my $summaryCC1;
+my $summaryCC2;
+
+#----------------------------------------------------------------------------
+# Read the input files
+#----------------------------------------------------------------------------
+my ($file1, $file2) = process_cmd_line();
+($cmd1, $events1, $CCs1, $summaryCC1) = read_input_file($file1);
+($cmd2, $events2, $CCs2, $summaryCC2) = read_input_file($file2);
+
+#----------------------------------------------------------------------------
+# Check the events match
+#----------------------------------------------------------------------------
+my $n = max(scalar @$events1, scalar @$events2);
+$^W = 0;    # turn off warnings, because we might hit undefs
+foreach my $i (0 .. $n-1) {
+    ($events1->[$i] eq $events2->[$i]) || die "events don't match, aborting\n";
+}
+$^W = 1;
+
+#----------------------------------------------------------------------------
+# Do the subtraction: CCs2 -= CCs1
+#----------------------------------------------------------------------------
+while (my ($filefuncname, $CC1) = each(%$CCs1)) {
+    my $CC2 = $CCs2->{$filefuncname};
+    if (not defined $CC2) {
+        $CC2 = [];
+        sub_array_b_from_a($CC2, $CC1);     # CC2 -= CC1
+        $CCs2->{$filefuncname} = $CC2;
+    } else {
+        sub_array_b_from_a($CC2, $CC1);     # CC2 -= CC1
+    }
+}
+sub_array_b_from_a($summaryCC2, $summaryCC1);
+
+#----------------------------------------------------------------------------
+# Print the result, in CCs2
+#----------------------------------------------------------------------------
+print("desc: Files compared:   $file1; $file2\n");
+print("cmd:  $cmd1; $cmd2\n");
+print("events: ");
+for my $e (@$events1) {
+    print(" $e");
+}
+print("\n");
+
+while (my ($filefuncname, $CC) = each(%$CCs2)) {
+
+    my @x = split(/#/, $filefuncname);
+    (scalar @x == 2) || die;
+
+    print("fl=$x[0]\n");
+    print("fn=$x[1]\n");
+
+    print("0");
+    foreach my $n (@$CC) {
+        print(" $n");
+    }
+    print("\n");
+}
+
+print("summary:");
+foreach my $n (@$summaryCC2) {
+    print(" $n");
+}
+print("\n");
+
+##--------------------------------------------------------------------##
+##--- end                                                          ---##
+##--------------------------------------------------------------------##

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_main.c
index e858ef5cac36a72453cc0813619d1830f2d5f914..cb0af568218a7e68a1adcc2e667a4e545d12737a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg_main.c
@@ -1191,45 +1191,40 @@ static cache_t clo_I1_cache = UNDEFINED_CACHE;
 static cache_t clo_D1_cache = UNDEFINED_CACHE;
 static cache_t clo_L2_cache = UNDEFINED_CACHE;
 
 static cache_t clo_D1_cache = UNDEFINED_CACHE;
 static cache_t clo_L2_cache = UNDEFINED_CACHE;
 

-/* Checks cache config is ok;  makes it so if not. */
-static 
-void check_cache(cache_t* cache, Char *name)
+// Checks cache config is ok.  Returns NULL if ok, or a pointer to an error
+// string otherwise.
+static Char* check_cache(cache_t* cache)

 {
 {

-   /* Simulator requires line size and set count to be powers of two */
-   if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
-       (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
-      VG_(umsg)("error: %s set count not a power of two; aborting.\n", name);
-      VG_(exit)(1);
+   // Simulator requires set count to be a power of two.
+   if ((cache->size % (cache->line_size * cache->assoc) != 0) ||
+       (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc)))
+   {
+      return "Cache set count is not a power of two.\n";

    }
 
    }
 

+   // Simulator requires line size to be a power of two.

    if (-1 == VG_(log2)(cache->line_size)) {
    if (-1 == VG_(log2)(cache->line_size)) {

-      VG_(umsg)("error: %s line size of %dB not a power of two; aborting.\n",
-                name, cache->line_size);
-      VG_(exit)(1);
+      return "Cache line size is not a power of two.\n";

    }
 
    // Then check line size >= 16 -- any smaller and a single instruction could
    // straddle three cache lines, which breaks a simulation assertion and is
    // stupid anyway.
    if (cache->line_size < MIN_LINE_SIZE) {
    }
 
    // Then check line size >= 16 -- any smaller and a single instruction could
    // straddle three cache lines, which breaks a simulation assertion and is
    // stupid anyway.
    if (cache->line_size < MIN_LINE_SIZE) {

-      VG_(umsg)("error: %s line size of %dB too small; aborting.\n", 
-                name, cache->line_size);
-      VG_(exit)(1);
+      return "Cache line size is too small.\n";

    }
 
    /* Then check cache size > line size (causes seg faults if not). */
    if (cache->size <= cache->line_size) {
    }
 
    /* Then check cache size > line size (causes seg faults if not). */
    if (cache->size <= cache->line_size) {

-      VG_(umsg)("error: %s cache size of %dB <= line size of %dB; aborting.\n",
-                name, cache->size, cache->line_size);
-      VG_(exit)(1);
+      return "Cache size <= line size.\n";

    }
 
    /* Then check assoc <= (size / line size) (seg faults otherwise). */
    if (cache->assoc > (cache->size / cache->line_size)) {
    }
 
    /* Then check assoc <= (size / line size) (seg faults otherwise). */
    if (cache->assoc > (cache->size / cache->line_size)) {

-      VG_(umsg)("warning: %s associativity > (size / line size); aborting.\n",
-                name);
-      VG_(exit)(1);
+      return "Cache associativity > (size / line size).\n";

    }
    }

+
+   return NULL;

 }
 
 static 
 }
 
 static 


@@ -1237,27 +1232,29 @@ void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c)
 {
 #define DEFINED(L)   (-1 != L.size  || -1 != L.assoc || -1 != L.line_size)
 
 {
 #define DEFINED(L)   (-1 != L.size  || -1 != L.assoc || -1 != L.line_size)
 

-   Int n_clos = 0;
+   Char* checkRes;

 
    // Count how many were defined on the command line.
 
    // Count how many were defined on the command line.

-   if (DEFINED(clo_I1_cache)) { n_clos++; }
-   if (DEFINED(clo_D1_cache)) { n_clos++; }
-   if (DEFINED(clo_L2_cache)) { n_clos++; }
+   Bool all_caches_clo_defined =
+      (DEFINED(clo_I1_cache) &&
+       DEFINED(clo_D1_cache) &&
+       DEFINED(clo_L2_cache));

 
    // Set the cache config (using auto-detection, if supported by the
 
    // Set the cache config (using auto-detection, if supported by the

-   // architecture)
-   VG_(configure_caches)( I1c, D1c, L2c, (3 == n_clos) );
+   // architecture).
+   VG_(configure_caches)( I1c, D1c, L2c, all_caches_clo_defined );

 
 

-   // Then replace with any defined on the command line.
+   // Check the default/auto-detected values.
+   checkRes = check_cache(I1c);  tl_assert(!checkRes);
+   checkRes = check_cache(D1c);  tl_assert(!checkRes);
+   checkRes = check_cache(L2c);  tl_assert(!checkRes);
+
+   // Then replace with any defined on the command line.  (Already checked in
+   // parse_cache_opt().)

    if (DEFINED(clo_I1_cache)) { *I1c = clo_I1_cache; }
    if (DEFINED(clo_D1_cache)) { *D1c = clo_D1_cache; }
    if (DEFINED(clo_L2_cache)) { *L2c = clo_L2_cache; }
 
    if (DEFINED(clo_I1_cache)) { *I1c = clo_I1_cache; }
    if (DEFINED(clo_D1_cache)) { *D1c = clo_D1_cache; }
    if (DEFINED(clo_L2_cache)) { *L2c = clo_L2_cache; }
 

-   // Then check values and fix if not acceptable.
-   check_cache(I1c, "I1");
-   check_cache(D1c, "D1");
-   check_cache(L2c, "L2");
-

    if (VG_(clo_verbosity) >= 2) {
       VG_(umsg)("Cache configuration used:\n");
       VG_(umsg)("  I1: %dB, %d-way, %dB lines\n",
    if (VG_(clo_verbosity) >= 2) {
       VG_(umsg)("Cache configuration used:\n");
       VG_(umsg)("  I1: %dB, %d-way, %dB lines\n",


@@ -1671,13 +1668,14 @@ void cg_discard_superblock_info ( Addr64 orig_addr64, VexGuestExtents vge )
 /*--- Command line processing                                      ---*/
 /*--------------------------------------------------------------------*/
 
 /*--- Command line processing                                      ---*/
 /*--------------------------------------------------------------------*/
 

-static void parse_cache_opt ( cache_t* cache, Char* opt )
+static void parse_cache_opt ( cache_t* cache, Char* opt, Char* optval )

 {
    Long i1, i2, i3;
    Char* endptr;
 {
    Long i1, i2, i3;
    Char* endptr;

+   Char* checkRes;

 
    // Option argument looks like "65536,2,64".  Extract them.
 
    // Option argument looks like "65536,2,64".  Extract them.

-   i1 = VG_(strtoll10)(opt,      &endptr); if (*endptr != ',')  goto bad;
+   i1 = VG_(strtoll10)(optval,   &endptr); if (*endptr != ',')  goto bad;

    i2 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != ',')  goto bad;
    i3 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != '\0') goto bad;
 
    i2 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != ',')  goto bad;
    i3 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != '\0') goto bad;
 


@@ -1689,14 +1687,20 @@ static void parse_cache_opt ( cache_t* cache, Char* opt )
    if (cache->assoc     != i2) goto overflow;
    if (cache->line_size != i3) goto overflow;
 
    if (cache->assoc     != i2) goto overflow;
    if (cache->line_size != i3) goto overflow;
 

+   checkRes = check_cache(cache);
+   if (checkRes) {
+      VG_(fmsg)("%s", checkRes);
+      goto bad;
+   }
+

    return;
 
    return;
 

-  overflow:
-   VG_(umsg)("one of the cache parameters was too large and overflowed\n");

   bad:
   bad:

-   // XXX: this omits the "--I1/D1/L2=" part from the message, but that's
-   // not a big deal.
-   VG_(err_bad_option)(opt);
+   VG_(fmsg_bad_option)(opt, "");
+
+  overflow:
+   VG_(fmsg_bad_option)(opt,
+      "One of the cache parameters was too large and overflowed.\n");

 }
 
 static Bool cg_process_cmd_line_option(Char* arg)
 }
 
 static Bool cg_process_cmd_line_option(Char* arg)


@@ -1705,11 +1709,11 @@ static Bool cg_process_cmd_line_option(Char* arg)
 
    // 5 is length of "--I1="
    if      VG_STR_CLO(arg, "--I1", tmp_str)
 
    // 5 is length of "--I1="
    if      VG_STR_CLO(arg, "--I1", tmp_str)

-      parse_cache_opt(&clo_I1_cache, tmp_str);
+      parse_cache_opt(&clo_I1_cache, arg, tmp_str);

    else if VG_STR_CLO(arg, "--D1", tmp_str)
    else if VG_STR_CLO(arg, "--D1", tmp_str)

-      parse_cache_opt(&clo_D1_cache, tmp_str);
+      parse_cache_opt(&clo_D1_cache, arg, tmp_str);

    else if VG_STR_CLO(arg, "--L2", tmp_str)
    else if VG_STR_CLO(arg, "--L2", tmp_str)

-      parse_cache_opt(&clo_L2_cache, tmp_str);
+      parse_cache_opt(&clo_L2_cache, arg, tmp_str);

 
    else if VG_STR_CLO( arg, "--cachegrind-out-file", clo_cachegrind_out_file) {}
    else if VG_BOOL_CLO(arg, "--cache-sim",  clo_cache_sim)  {}
 
    else if VG_STR_CLO( arg, "--cachegrind-out-file", clo_cachegrind_out_file) {}
    else if VG_BOOL_CLO(arg, "--cache-sim",  clo_cache_sim)  {}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/docs/cg-manual.xml b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/docs/cg-manual.xml
index e8ab23db512e457bd240fdf33b12069751e2e913..b312771f9bce500c906d9d0dc058467f4152e1de 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/docs/cg-manual.xml
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/docs/cg-manual.xml
@@ -98,8 +98,10 @@ be normally run.</para>
 <para>Then, you need to run Cachegrind itself to gather the profiling
 information, and then run cg_annotate to get a detailed presentation of that
 information.  As an optional intermediate step, you can use cg_merge to sum
 <para>Then, you need to run Cachegrind itself to gather the profiling
 information, and then run cg_annotate to get a detailed presentation of that
 information.  As an optional intermediate step, you can use cg_merge to sum

-together the outputs of multiple Cachegrind runs, into a single file which
-you then use as the input for cg_annotate.</para>
+together the outputs of multiple Cachegrind runs into a single file which
+you then use as the input for cg_annotate.  Alternatively, you can use
+cg_diff to difference the outputs of two Cachegrind runs into a signel file
+which you then use as the input for cg_annotate.</para>

 
 
 <sect2 id="cg-manual.running-cachegrind" xreflabel="Running Cachegrind">
 
 
 <sect2 id="cg-manual.running-cachegrind" xreflabel="Running Cachegrind">


@@ -697,6 +699,85 @@ fail these checks.</para>
 </sect2>
 
 
 </sect2>
 
 

+<sect2 id="cg-manual.cg_diff" xreflabel="cg_diff">
+<title>Differencing Profiles with cg_diff</title>
+
+<para>
+cg_diff is a simple program which
+reads two profile files, as created by Cachegrind, finds the difference
+between them, and writes the results into another file in the same format.
+You can then examine the merged results using
+<computeroutput>cg_annotate &lt;filename&gt;</computeroutput>, as
+described above.  This is very useful if you want to measure how a change to
+a program affected its performance.
+</para>
+
+<para>
+cg_diff is invoked as follows:
+</para>
+
+<programlisting><![CDATA[
+cg_diff file1 file2]]></programlisting>
+
+<para>
+It reads and checks <computeroutput>file1</computeroutput>, then read
+and checks <computeroutput>file2</computeroutput>, then computes the
+difference (effectively <computeroutput>file1</computeroutput> -
+<computeroutput>file2</computeroutput>).  The final results are written to
+standard output.</para>
+
+<para>
+Costs are summed on a per-function basis.  Per-line costs are not summed,
+because doing so is too difficult.  For example, consider differencing two
+profiles, one from a single-file program A, and one from the same program A
+where a single blank line was inserted at the top of the file.  Every single
+per-line count has changed.  In comparison, the per-function counts have not
+changed.  The per-function count differences are still very useful for
+determining differences between programs.  Note that because the result is
+the difference of two profiles, many of the counts will be negative;  this
+indicates that the counts for the relevant function are fewer in the second
+version than those in the first version.</para>
+
+<para>
+cg_diff does not attempt to check
+that the input files come from runs of the same executable.  It will
+happily merge together profile files from completely unrelated
+programs.  It does however check that the
+<computeroutput>Events:</computeroutput> lines of all the inputs are
+identical, so as to ensure that the addition of costs makes sense.
+For example, it would be nonsensical for it to add a number indicating
+D1 read references to a number from a different file indicating L2
+write misses.</para>
+
+<para>
+A number of other syntax and sanity checks are done whilst reading the
+inputs.  cg_diff will stop and
+attempt to print a helpful error message if any of the input files
+fail these checks.</para>
+
+<para>
+Sometimes you will want to compare Cachegrind profiles of two versions of a
+program that you have sitting side-by-side.  For example, you might have
+<computeroutput>version1/prog.c</computeroutput> and
+<computeroutput>version2/prog.c</computeroutput>, where the second is
+slightly different to the first.  A straight comparison of the two will not
+be useful -- because functions are qualified with filenames, a function
+<function>f</function> will be listed as
+<computeroutput>version1/prog.c:f</computeroutput> for the first version but
+<computeroutput>version2/prog.c:f</computeroutput> for the second
+version.</para>
+
+<para>
+When this happens, you can use the <option>--mod-filename</option> option.
+Its argument is a Perl search-and-replace expression that will be applied
+to all the filenames in both Cachegrind output files.  It can be used to
+remove minor differences in filenames.  For example, the option
+<option>--mod-filename='s/version[0-9]/versionN/'</option> will suffice for
+this case.</para>
+
+</sect2>
+
+

 </sect1>
 
 
 </sect1>
 
 


@@ -842,21 +923,21 @@ fail these checks.</para>
 
   <varlistentry>
     <term>
 
   <varlistentry>
     <term>

-      <option><![CDATA[--threshold=X [default: 99%] ]]></option>
+      <option><![CDATA[--threshold=X [default: 0.1%] ]]></option>

     </term>
     <listitem>
       <para>Sets the threshold for the function-by-function
     </term>
     <listitem>
       <para>Sets the threshold for the function-by-function

-      summary.  Functions are shown that account for more than X%
-      of the primary sort event.  If auto-annotating, also affects
-      which files are annotated.</para>
+      summary.  A function is shown if it accounts for more than X%
+      of the counts for the primary sort event.  If auto-annotating, also
+      affects which files are annotated.</para>

         
       <para>Note: thresholds can be set for more than one of the
       events by appending any events for the
       <option>--sort</option> option with a colon
       and a number (no spaces, though).  E.g. if you want to see
         
       <para>Note: thresholds can be set for more than one of the
       events by appending any events for the
       <option>--sort</option> option with a colon
       and a number (no spaces, though).  E.g. if you want to see

-      the functions that cover 99% of L2 read misses and 99% of L2
+      each function that covers more than 1% of L2 read misses or 1% of L2

       write misses, use this option:</para>
       write misses, use this option:</para>

-      <para><option>--sort=D2mr:99,D2mw:99</option></para>
+      <para><option>--sort=D2mr:1,D2mw:1</option></para>

     </listitem>
   </varlistentry>
 
     </listitem>
   </varlistentry>
 


@@ -900,6 +981,49 @@ fail these checks.</para>
 </sect1>
 
 
 </sect1>
 
 

+<sect1 id="cg-manual.diffopts" xreflabel="cg_diff Command-line Options">
+<title>cg_diff Command-line Options</title>
+
+<!-- start of xi:include in the manpage -->
+<variablelist id="cg_diff.opts.list">
+
+  <varlistentry>
+    <term>
+      <option><![CDATA[-h --help ]]></option>
+    </term>
+    <listitem>
+      <para>Show the help message.</para>
+    </listitem>
+  </varlistentry>
+
+  <varlistentry>
+    <term>
+      <option><![CDATA[--version ]]></option>
+    </term>
+    <listitem>
+      <para>Show the version number.</para>
+    </listitem>
+  </varlistentry>
+
+  <varlistentry>
+    <term>
+      <option><![CDATA[--mod-filename=<expr> [default: none]]]></option>
+    </term>
+    <listitem>
+      <para>Specifies a Perl search-and-replace expression that is applied
+      to all filenames.  Useful for removing minor differences in paths
+      between two different versions of a program that are sitting in
+      different directories.</para>
+    </listitem>
+  </varlistentry>
+
+</variablelist>
+<!-- end of xi:include in the manpage -->
+  
+</sect1>
+
+
+

 
 <sect1 id="cg-manual.acting-on"
        xreflabel="Acting on Cachegrind's Information">
 
 <sect1 id="cg-manual.acting-on"
        xreflabel="Acting on Cachegrind's Information">

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/tests/Makefile.in
index 14661b180b48b16d188452ea6801a7dff7c42982..ef96b1ba088c35dbb7907357ff0e5574e4edb627 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/tests/Makefile.in
@@ -160,6 +160,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -194,14 +195,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -284,7 +289,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -343,7 +350,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -358,8 +365,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/tests/x86/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/tests/x86/Makefile.in
index cb8332210da40f703fdac5ca60935dc1dc284cfb..c1bf3914275fdf63b712c18bf2388db8365bb03f 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/tests/x86/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/tests/x86/Makefile.in
@@ -112,6 +112,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -146,14 +147,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -236,7 +241,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -295,7 +302,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -310,8 +317,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/Makefile.am
index 59e4d03f4013a400da9dbe8e8a461004890f19d6..74f3597ab02aad86da4adfd6231cf04cd82b693a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/Makefile.am
@@ -65,6 +65,13 @@ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
        $(CALLGRIND_SOURCES_COMMON)
 if VGCONF_HAVE_PLATFORM_SEC
 callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
        $(CALLGRIND_SOURCES_COMMON)


@@ -78,5 +85,11 @@ callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 endif
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/Makefile.in
index 9cd288ae58b9c8c665ed6ae6845b5cdad60af52a..7a4b6a68b54017ff22847a7b3e3a7e025b9a1b9e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/Makefile.in
@@ -47,25 +47,9 @@ DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
        $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(srcdir)/callgrind_annotate.in $(srcdir)/callgrind_control.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
        $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(srcdir)/callgrind_annotate.in $(srcdir)/callgrind_control.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = callgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)
 noinst_PROGRAMS = callgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = callgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = callgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = callgrind
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = callgrind
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4


@@ -100,10 +84,6 @@ am__objects_1 = callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@-bb.$(OBJEXT) \
 am_callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
 am_callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) \
-       -o $@

 am__callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = bb.c bbcc.c \
        callstack.c clo.c command.c context.c costs.c debug.c dump.c \
        events.c fn.c jumps.c main.c sim.c threads.c \
 am__callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = bb.c bbcc.c \
        callstack.c clo.c command.c context.c costs.c debug.c dump.c \
        events.c fn.c jumps.c main.c sim.c threads.c \


@@ -132,10 +112,6 @@ am__objects_2 = callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bb.$(OBJEXT) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) \
-       -o $@

 am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
 am__vpath_adj = case $$p in \
     $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
 am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
 am__vpath_adj = case $$p in \
     $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \


@@ -250,6 +226,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -284,14 +261,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -375,7 +356,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -434,7 +417,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -449,8 +432,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -513,37 +496,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -552,32 +535,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -714,6 +693,13 @@ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

+callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(CALLGRIND_SOURCES_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(CALLGRIND_SOURCES_COMMON)
 


@@ -732,8 +718,14 @@ callgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(callgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -1620,16 +1612,14 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) $(SCRIPTS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(bindir)" "$(DESTDIR)$(pkgincludedir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done
 all-am: Makefile $(PROGRAMS) $(SCRIPTS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(bindir)" "$(DESTDIR)$(pkgincludedir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -1646,7 +1636,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -1655,7 +1644,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1726,9 +1714,8 @@ ps-am:
 
 uninstall-am: uninstall-binSCRIPTS uninstall-pkgincludeHEADERS
 
 
 uninstall-am: uninstall-binSCRIPTS uninstall-pkgincludeHEADERS
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1811,65 +1798,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/bbcc.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/bbcc.c
index ac7c21ed06adda5180dd60916660a55c682edc83..24862a80caaacbee8ba9fef40a36856f2c4ec05e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/bbcc.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/bbcc.c
@@ -580,6 +580,7 @@ void CLG_(setup_bbcc)(BB* bb)
 
   if (last_bb) {
       passed = CLG_(current_state).jmps_passed;
 
   if (last_bb) {
       passed = CLG_(current_state).jmps_passed;

+      CLG_ASSERT(passed <= last_bb->cjmp_count);

       if (passed == last_bb->cjmp_count) {
          jmpkind = last_bb->jmpkind;
 
       if (passed == last_bb->cjmp_count) {
          jmpkind = last_bb->jmpkind;
 


@@ -599,9 +600,9 @@ void CLG_(setup_bbcc)(BB* bb)
          last_bbcc->ecounter_sum++;
          last_bbcc->jmp[passed].ecounter++;
          if (!CLG_(clo).simulate_cache) {
          last_bbcc->ecounter_sum++;
          last_bbcc->jmp[passed].ecounter++;
          if (!CLG_(clo).simulate_cache) {

-             /* update Ir cost */
-             int instr_count = last_bb->jmp[passed].instr+1;
-             CLG_(current_state).cost[CLG_(sets).off_full_Ir] += instr_count;
+             /* update Ir cost */              
+              UInt instr_count = last_bb->jmp[passed].instr+1;
+              CLG_(current_state).cost[ fullOffset(EG_IR) ] += instr_count;

          }
       }
 
          }
       }
 


@@ -864,6 +865,9 @@ void CLG_(setup_bbcc)(BB* bb)
   }
   
   CLG_(current_state).bbcc = bbcc;
   }
   
   CLG_(current_state).bbcc = bbcc;

+  // needed for log_* handlers called in this BB
+  CLG_(bb_base)   = bb->obj->offset + bb->offset;
+  CLG_(cost_base) = bbcc->cost;

   
   CLG_DEBUGIF(1) {
     VG_(printf)("     ");
   
   CLG_DEBUGIF(1) {
     VG_(printf)("     ");


@@ -878,7 +882,5 @@ void CLG_(setup_bbcc)(BB* bb)
     CLG_(print_cxt)(-8, CLG_(current_state).cxt, bbcc->rec_index);
   CLG_DEBUG(3,"\n");
   
     CLG_(print_cxt)(-8, CLG_(current_state).cxt, bbcc->rec_index);
   CLG_DEBUG(3,"\n");
   

-  (*CLG_(cachesim).after_bbsetup)();
-

   CLG_(stat).bb_executions++;
 }
   CLG_(stat).bb_executions++;
 }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/clo.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/clo.c
index 6d7df37bab82aa74299acbd8555a23631dffc7e2..fc99b0df6211027c32e32b9e3f384c9cc37aa36b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/clo.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/clo.c
@@ -525,8 +525,13 @@ Bool CLG_(process_cmd_line_option)(Char* arg)
 
    else if VG_BOOL_CLO(arg, "--collect-alloc",   CLG_(clo).collect_alloc) {}
    else if VG_BOOL_CLO(arg, "--collect-systime", CLG_(clo).collect_systime) {}
 
    else if VG_BOOL_CLO(arg, "--collect-alloc",   CLG_(clo).collect_alloc) {}
    else if VG_BOOL_CLO(arg, "--collect-systime", CLG_(clo).collect_systime) {}

+   else if VG_BOOL_CLO(arg, "--collect-bus",     CLG_(clo).collect_bus) {}
+   /* for option compatibility with cachegrind */
+   else if VG_BOOL_CLO(arg, "--cache-sim",       CLG_(clo).simulate_cache) {}
+   /* compatibility alias, deprecated option */

    else if VG_BOOL_CLO(arg, "--simulate-cache",  CLG_(clo).simulate_cache) {}
    else if VG_BOOL_CLO(arg, "--simulate-cache",  CLG_(clo).simulate_cache) {}

-
+   /* for option compatibility with cachegrind */
+   else if VG_BOOL_CLO(arg, "--branch-sim",      CLG_(clo).simulate_branch) {}

    else {
        Bool isCachesimOption = (*CLG_(cachesim).parse_opt)(arg);
 
    else {
        Bool isCachesimOption = (*CLG_(cachesim).parse_opt)(arg);
 


@@ -572,6 +577,7 @@ void CLG_(print_usage)(void)
 "    --collect-atstart=no|yes  Collect at process/thread start [yes]\n"
 "    --toggle-collect=<func>   Toggle collection on enter/leave function\n"
 "    --collect-jumps=no|yes    Collect jumps? [no]\n"
 "    --collect-atstart=no|yes  Collect at process/thread start [yes]\n"
 "    --toggle-collect=<func>   Toggle collection on enter/leave function\n"
 "    --collect-jumps=no|yes    Collect jumps? [no]\n"

+"    --collect-bus=no|yes      Collect global bus events? [no]\n"

 #if CLG_EXPERIMENTAL
 "    --collect-alloc=no|yes    Collect memory allocation info? [no]\n"
 #endif
 #if CLG_EXPERIMENTAL
 "    --collect-alloc=no|yes    Collect memory allocation info? [no]\n"
 #endif


@@ -589,6 +595,9 @@ void CLG_(print_usage)(void)
 #if CLG_EXPERIMENTAL
 "    --fn-group<no>=<func>     Put function into separation group <no>\n"
 #endif
 #if CLG_EXPERIMENTAL
 "    --fn-group<no>=<func>     Put function into separation group <no>\n"
 #endif

+"\n   simulation options:\n"
+"    --branch-sim=no|yes       Do branch prediction simulation [no]\n"
+"    --cache-sim=no|yes        Do cache simulation [no]\n"

     );
 
    (*CLG_(cachesim).print_opts)();
     );
 
    (*CLG_(cachesim).print_opts)();


@@ -639,6 +648,7 @@ void CLG_(set_clo_defaults)(void)
   CLG_(clo).collect_jumps    = False;
   CLG_(clo).collect_alloc    = False;
   CLG_(clo).collect_systime  = False;
   CLG_(clo).collect_jumps    = False;
   CLG_(clo).collect_alloc    = False;
   CLG_(clo).collect_systime  = False;

+  CLG_(clo).collect_bus      = False;

 
   CLG_(clo).skip_plt         = True;
   CLG_(clo).separate_callers = 0;
 
   CLG_(clo).skip_plt         = True;
   CLG_(clo).separate_callers = 0;


@@ -648,6 +658,7 @@ void CLG_(set_clo_defaults)(void)
   /* Instrumentation */
   CLG_(clo).instrument_atstart = True;
   CLG_(clo).simulate_cache = False;
   /* Instrumentation */
   CLG_(clo).instrument_atstart = True;
   CLG_(clo).simulate_cache = False;

+  CLG_(clo).simulate_branch = False;

 
   /* Call graph */
   CLG_(clo).pop_on_jump = False;
 
   /* Call graph */
   CLG_(clo).pop_on_jump = False;

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/debug.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/debug.c
index b89b753613e06113de2ce680c06998edd68440dc..966aa747f35c16e356c6623d410ab6f49c3d1242 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/debug.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/debug.c
@@ -137,40 +137,46 @@ void CLG_(print_bbcc)(int s, BBCC* bbcc)
 
 void CLG_(print_eventset)(int s, EventSet* es)
 {
 
 void CLG_(print_eventset)(int s, EventSet* es)
 {

-  int i;
+    int i, j;
+    UInt mask;
+    EventGroup* eg;

 
 

-  if (s<0) {
-    s = -s;
-    print_indent(s);
-  }
+    if (s<0) {
+       s = -s;
+       print_indent(s);
+    }

 
 

-  if (!es) {
-    VG_(printf)("(EventSet not set)\n");
-    return;
-  }
+    if (!es) {
+       VG_(printf)("(EventSet not set)\n");
+       return;
+    }

 
 

-  VG_(printf)("%5s (Size/Cap %d/%d): ",
-             es->name, es->size, es->capacity);
-
-  if (es->size == 0)
-    VG_(printf)("-");
-  else {
-    for(i=0; i< es->size; i++) {
-      if (i>0) {
-       VG_(printf)(" ");
-       if (es->e[i-1].nextTop == i)
-         VG_(printf)("| ");
-      }
-      VG_(printf)("%s", es->e[i].type->name);
+    VG_(printf)("EventSet %d (%d groups, size %d):",
+               es->mask, es->count, es->size);
+
+    if (es->count == 0) {
+       VG_(printf)("-\n");
+       return;

     }
     }

-  }
-  VG_(printf)("\n");
+
+    for(i=0, mask=1; i<MAX_EVENTGROUP_COUNT; i++, mask=mask<<1) {
+       if ((es->mask & mask)==0) continue;
+       eg = CLG_(get_event_group)(i);
+       if (!eg) continue;
+       VG_(printf)(" (%d: %s", i, eg->name[0]);
+       for(j=1; j<eg->size; j++)
+           VG_(printf)(" %s", eg->name[j]);
+       VG_(printf)(")");
+    }
+    VG_(printf)("\n");

 }
 
 
 void CLG_(print_cost)(int s, EventSet* es, ULong* c)
 {
 }
 
 
 void CLG_(print_cost)(int s, EventSet* es, ULong* c)
 {

-  Int i, pos;
+    Int i, j, pos, off;
+    UInt mask;
+    EventGroup* eg;

 
     if (s<0) {
        s = -s;
 
     if (s<0) {
        s = -s;


@@ -182,29 +188,36 @@ void CLG_(print_cost)(int s, EventSet* es, ULong* c)
       return;
     }
     if (!c) {
       return;
     }
     if (!c) {

-      VG_(printf)("Cost (Null, EventSet %s)\n", es->name);
+      VG_(printf)("Cost (Null, EventSet %d)\n", es->mask);

       return;
     }
 
     if (es->size == 0) {
       return;
     }
 
     if (es->size == 0) {

-      VG_(printf)("Cost (Nothing, EventSet %s with len 0)\n", es->name);
+      VG_(printf)("Cost (Nothing, EventSet with len 0)\n");

       return;
     } 
 
     pos = s;
       return;
     } 
 
     pos = s;

-    pos += VG_(printf)("Cost %s [%p]: %s %llu", es->name, c, es->e[0].type->name, c[0]);
-
-    i = 1;
-    while(i<es->size) {
-      if (pos > 70) {
-       VG_(printf)(",\n");
-       print_indent(s+5);
-       pos = s+5;
-      }
-      else
-       pos += VG_(printf)(", ");
-      pos += VG_(printf)("%s %llu", es->e[i].type->name, c[i]);
-      i++;
+    pos += VG_(printf)("Cost [%p]: ", c);
+    off = 0;
+    for(i=0, mask=1; i<MAX_EVENTGROUP_COUNT; i++, mask=mask<<1) {
+       if ((es->mask & mask)==0) continue;
+       eg = CLG_(get_event_group)(i);
+       if (!eg) continue;
+       for(j=0; j<eg->size; j++) {
+
+           if (off>0) {
+               if (pos > 70) {
+                   VG_(printf)(",\n");
+                   print_indent(s+5);
+                   pos = s+5;
+               }
+               else
+                   pos += VG_(printf)(", ");
+           }
+
+           pos += VG_(printf)("%s %llu", eg->name[j], c[off++]);
+       }

     }
     VG_(printf)("\n");
 }
     }
     VG_(printf)("\n");
 }


@@ -213,13 +226,13 @@ void CLG_(print_cost)(int s, EventSet* es, ULong* c)
 void CLG_(print_short_jcc)(jCC* jcc)
 {
     if (jcc)
 void CLG_(print_short_jcc)(jCC* jcc)
 {
     if (jcc)

-       VG_(printf)("%#lx => %#lx [%llu/%llu,%llu,%llu]",
+       VG_(printf)("%#lx => %#lx [calls %llu/Ir %llu, Dr %llu, Dw %llu]",

                    bb_jmpaddr(jcc->from->bb),
                    bb_addr(jcc->to->bb),
                    jcc->call_counter,
                    bb_jmpaddr(jcc->from->bb),
                    bb_addr(jcc->to->bb),
                    jcc->call_counter,

-                   jcc->cost ? jcc->cost[CLG_(sets).off_full_Ir]:0,
-                   jcc->cost ? jcc->cost[CLG_(sets).off_full_Dr]:0,
-                   jcc->cost ? jcc->cost[CLG_(sets).off_full_Dw]:0);
+                   jcc->cost ? jcc->cost[fullOffset(EG_IR)]:0,
+                   jcc->cost ? jcc->cost[fullOffset(EG_DR)]:0,
+                   jcc->cost ? jcc->cost[fullOffset(EG_DW)]:0);

     else
        VG_(printf)("[Skipped JCC]");
 }
     else
        VG_(printf)("[Skipped JCC]");
 }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/docs/cl-manual.xml b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/docs/cl-manual.xml
index 7e43bfa44c7091c72b642baf2710245e99404748..e2289ff552523fef67c98cbee4c60e37e2544fb4 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/docs/cl-manual.xml
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/docs/cl-manual.xml
@@ -4,7 +4,7 @@
 [ <!ENTITY % vg-entities SYSTEM "../../docs/xml/vg-entities.xml"> %vg-entities; ]>
 
 <chapter id="cl-manual" xreflabel="Callgrind Manual">
 [ <!ENTITY % vg-entities SYSTEM "../../docs/xml/vg-entities.xml"> %vg-entities; ]>
 
 <chapter id="cl-manual" xreflabel="Callgrind Manual">

-<title>Callgrind: a call-graph generating cache profiler</title>
+<title>Callgrind: a call-graph generating cache and branch prediction profiler</title>

 
 
 <para>To use this tool, you must specify
 
 
 <para>To use this tool, you must specify


@@ -14,14 +14,14 @@ Valgrind command line.</para>
 <sect1 id="cl-manual.use" xreflabel="Overview">
 <title>Overview</title>
 
 <sect1 id="cl-manual.use" xreflabel="Overview">
 <title>Overview</title>
 

-<para>Callgrind is a profiling tool that can
-construct a call graph for a program's run.
+<para>Callgrind is a profiling tool that records the call history among
+functions in a program's run as a call-graph.

 By default, the collected data consists of
 the number of instructions executed, their relationship
 to source lines, the caller/callee relationship between functions,
 and the numbers of such calls.
 By default, the collected data consists of
 the number of instructions executed, their relationship
 to source lines, the caller/callee relationship between functions,
 and the numbers of such calls.

-Optionally, a cache simulator (similar to Cachegrind) can produce
-further information about the memory access behavior of the application.
+Optionally, cache simulation and/or branch prediction (similar to Cachegrind)
+can produce further information about the runtime behavior of an application.

 </para>
 
 <para>The profile data is written out to a file at program
 </para>
 
 <para>The profile data is written out to a file at program


@@ -175,10 +175,10 @@ on heuristics to detect calls and returns.</para>
   results in this case.</para>
 
   <para>If you are additionally interested in measuring the 
   results in this case.</para>
 
   <para>If you are additionally interested in measuring the 

-  cache behavior of your 
-  program, use Callgrind with the option
-  <option><xref linkend="opt.simulate-cache"/>=yes.</option>
-  However, expect a  further slow down approximately by a factor of 2.</para>
+  cache behavior of your program, use Callgrind with the option
+  <option><xref linkend="clopt.cache-sim"/>=yes</option>. For
+  branch prediction simulation, use <option><xref linkend="clopt.branch-sim"/>=yes</option>.
+  Expect a further slow down approximately by a factor of 2.</para>

 
   <para>If the program section you want to profile is somewhere in the
   middle of the run, it is beneficial to 
 
   <para>If the program section you want to profile is somewhere in the
   middle of the run, it is beneficial to 


@@ -353,10 +353,27 @@ callgrind.out.<emphasis>pid</emphasis>.<emphasis>part</emphasis>-<emphasis>threa
   start event collection a few million instructions after you have enabled
   instrumentation.</para>
 
   start event collection a few million instructions after you have enabled
   instrumentation.</para>
 

-

   </sect2>
 
   </sect2>
 

+  <sect2 id="cl-manual.busevents" xreflabel="Counting global bus events">
+  <title>Counting global bus events</title>
+
+  <para>For access to shared data among threads in a multithreaded
+  code, synchronization is required to avoid raced conditions.
+  Synchronization primitives are usually implemented via atomic instructions.
+  However, excessive use of such instructions can lead to performance
+  issues.</para>
+
+  <para>To enable analysis of this problem, Callgrind optionally can count
+  the number of atomic instructions executed. More precisely, for x86/x86_64,
+  these are instructions using a lock prefix. For architectures supporting
+  LL/SC, these are the number of SC instructions executed. For both, the term
+  "global bus events" is used.</para>

 
 

+  <para>The short name of the event type used for global bus events is "Ge".
+  To count global bus events, use <option><xref linkend="clopt.collect-bus"/>=yes</option>.
+  </para>
+  </sect2>

 
   <sect2 id="cl-manual.cycles" xreflabel="Avoiding cycles">
   <title>Avoiding cycles</title>
 
   <sect2 id="cl-manual.cycles" xreflabel="Avoiding cycles">
   <title>Avoiding cycles</title>


@@ -762,6 +779,16 @@ Also see <xref linkend="cl-manual.limits"/>.</para>
     </listitem>
   </varlistentry>
 
     </listitem>
   </varlistentry>
 

+  <varlistentry id="clopt.collect-bus" xreflabel="--collect-bus">
+    <term>
+      <option><![CDATA[--collect-bus=<no|yes> [default: no] ]]></option>
+    </term>
+    <listitem>
+      <para>This specifies whether the number of global bus events executed
+      should be collected. The event type "Ge" is used for these events.</para>
+    </listitem>
+  </varlistentry>
+

 </variablelist>
 <!-- end of xi:include in the manpage -->
 </sect2>
 </variablelist>
 <!-- end of xi:include in the manpage -->
 </sect2>


@@ -890,23 +917,55 @@ Also see <xref linkend="cl-manual.cycles"/>.</para>
 <!-- end of xi:include in the manpage -->
 </sect2>
 
 <!-- end of xi:include in the manpage -->
 </sect2>
 

+

 <sect2 id="cl-manual.options.simulation"
 <sect2 id="cl-manual.options.simulation"

-       xreflabel="Cache simulation options">
-<title>Cache simulation options</title>
+       xreflabel="Simulation options">
+<title>Simulation options</title>

 
 <!-- start of xi:include in the manpage -->
 <variablelist id="cl.opts.list.simulation">
 
 <!-- start of xi:include in the manpage -->
 <variablelist id="cl.opts.list.simulation">

-  
-  <varlistentry id="opt.simulate-cache" xreflabel="--simulate-cache">
+
+  <varlistentry id="clopt.cache-sim" xreflabel="--cache-sim">

     <term>
     <term>

-      <option><![CDATA[--simulate-cache=<yes|no> [default: no] ]]></option>
+      <option><![CDATA[--cache-sim=<yes|no> [default: no] ]]></option>

     </term>
     <listitem>
       <para>Specify if you want to do full cache simulation.  By default,
     </term>
     <listitem>
       <para>Specify if you want to do full cache simulation.  By default,

-      only instruction read accesses will be profiled.</para>
+      only instruction read accesses will be counted ("Ir").
+      With cache simulation, further event counters are enabled:
+      Cache misses on instruction reads ("I1mr"/"I2mr"),
+      data read accesses ("Dr") and related cache misses ("D1mr"/"D2mr"),
+      data write accesses ("Dw") and related cache misses ("D1mw"/"D2mw").
+      For more information, see <xref linkend="cg-manual"/>.
+      </para>

     </listitem>
   </varlistentry>
 
     </listitem>
   </varlistentry>
 

+  <varlistentry id="clopt.branch-sim" xreflabel="--branch-sim">
+    <term>
+      <option><![CDATA[--branch-sim=<yes|no> [default: no] ]]></option>
+    </term>
+    <listitem>
+      <para>Specify if you want to do branch prediction simulation.
+      Further event counters are enabled: Number of executed conditional
+      branches and related predictor misses ("Bc"/"Bcm"), executed indirect
+      jumps and related misses of the jump address predictor ("Bi"/"Bim").
+      </para>
+    </listitem>
+  </varlistentry>
+
+</variablelist>
+<!-- end of xi:include in the manpage -->
+</sect2>
+
+
+<sect2 id="cl-manual.options.cachesimulation"
+       xreflabel="Cache simulation options">
+<title>Cache simulation options</title>
+
+<!-- start of xi:include in the manpage -->
+<variablelist id="cl.opts.list.cachesimulation">
+

   <varlistentry id="opt.simulate-wb" xreflabel="--simulate-wb">
     <term>
       <option><![CDATA[--simulate-wb=<yes|no> [default: no] ]]></option>
   <varlistentry id="opt.simulate-wb" xreflabel="--simulate-wb">
     <term>
       <option><![CDATA[--simulate-wb=<yes|no> [default: no] ]]></option>

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/events.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/events.c
index c0654143e08d999474371d015ad938cf3f3045ea..fb5a77a380ab84a74ea69f290592fc3220d8ba0f 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/events.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/events.c
@@ -28,550 +28,534 @@
 
 #include "global.h"
 
 
 #include "global.h"
 

-#define MAX_EVENTTYPE 20
+/* This should be 2**MAX_EVENTGROUP_COUNT */
+#define MAX_EVENTSET_COUNT 1024

 
 

-static EventType eventtype[MAX_EVENTTYPE];
-static Int eventtype_count = 0;
+static EventGroup* eventGroup[MAX_EVENTGROUP_COUNT];
+static EventSet* eventSetTable[MAX_EVENTSET_COUNT];
+static Bool eventSets_initialized = 0;

 
 

-EventType* CLG_(register_eventtype)(Char* name)
+static
+void initialize_event_sets(void)

 {
 {

-  EventType* et;
+    Int i;

 
 

-  if (eventtype_count == MAX_EVENTTYPE) {
-    VG_(printf)("\nMore than %d event types used!\n"
-               "Increase MAX_EVENTTYPE in ct_events.c and recomile this tool!\n",
-               MAX_EVENTTYPE);
-    VG_(tool_panic)("Too many event types requested.");
-  }
+    if (eventSets_initialized) return;

 
 

-  et = &(eventtype[eventtype_count]);
-  et->id = eventtype_count; 
-  et->name = (UChar*) VG_(strdup)("cl.events.re.1", name);
-  et->description = 0;
+    for(i=0; i< MAX_EVENTGROUP_COUNT; i++)
+       eventGroup[i] = 0;

 
 

-  eventtype_count++;
-
-  return et;
-}
+    for(i=0; i< MAX_EVENTSET_COUNT; i++)
+       eventSetTable[i] = 0;

 
 

+    eventSets_initialized = 1;
+ }

 
 

-EventType* CLG_(get_eventtype)(Char* name)
+static
+EventGroup* new_event_group(int id, int n)

 {
 {

-  Int i;
+    EventGroup* eg;
+
+    initialize_event_sets();

 
 

-  for(i=0;i<eventtype_count;i++)
-    if (VG_(strcmp)(eventtype[i].name, name) == 0)
-      return eventtype+i;
-  return 0;
+    CLG_ASSERT(id>=0 && id<MAX_EVENTGROUP_COUNT);
+    CLG_ASSERT(eventGroup[id]==0);
+
+    eg = (EventGroup*) CLG_MALLOC("cl.events.group.1",
+                                 sizeof(EventGroup) + n * sizeof(Char*));
+    eg->size = n;
+    eventGroup[id] = eg;
+    return eg;

 }
 
 }
 

-EventType* CLG_(get_eventtype_byindex)(Int id)
+EventGroup* CLG_(register_event_group) (int id, Char* n1)

 {
 {

-  if ((id >= 0) && (id < eventtype_count))
-    return eventtype+id;
-  return 0;
+    EventGroup* eg = new_event_group(id, 1);
+    eg->name[0] = n1;
+
+    return eg;

 }
 
 }
 

-/* Allocate space for an event set */
-EventSet* CLG_(get_eventset)(Char* n, Int capacity)
+EventGroup* CLG_(register_event_group2)(int id, Char* n1, Char* n2)

 {
 {

-  EventSet* es;
+    EventGroup* eg = new_event_group(id, 2);
+    eg->name[0] = n1;
+    eg->name[1] = n2;

 
 

-  es = (EventSet*) CLG_MALLOC("cl.events.geSet.1",
-                               sizeof(EventSet) +
-                              capacity * sizeof(EventSetEntry));
-  es->capacity = capacity;
-  es->size = 0;
-  es->name = n;
-
-  return es;
+    return eg;

 }
 
 }
 

-/* Incorporate a event type into a set, get start offset */
-Int CLG_(add_eventtype)(EventSet* es, EventType* t)
+EventGroup* CLG_(register_event_group3)(int id, Char* n1, Char* n2, Char* n3)

 {
 {

-  Int offset = es->size;
-  if (es->capacity - offset < 1) return -1;
-
-  es->size++;
-  es->e[offset].type = t;
-  es->e[offset].nextTop = es->size;
+    EventGroup* eg = new_event_group(id, 3);
+    eg->name[0] = n1;
+    eg->name[1] = n2;
+    eg->name[2] = n3;

 
 

-  return offset;
+    return eg;

 }
 
 }
 

-/* Incorporate one event set into another, get start offset */
-Int CLG_(add_eventset)(EventSet* dst, EventSet* src)
+EventGroup* CLG_(register_event_group4)(int id,
+                                       Char* n1, Char* n2, Char* n3, Char* n4)

 {
 {

-  Int offset = dst->size, i;
-  if (!src || (src->size == 0)) return offset;
+    EventGroup* eg = new_event_group(id, 4);
+    eg->name[0] = n1;
+    eg->name[1] = n2;
+    eg->name[2] = n3;
+    eg->name[3] = n4;

 
 

-  if (dst->capacity - offset < src->size) return -1;
-  
-  for(i=0;i<src->size;i++) {
-    dst->e[offset+i].type = src->e[i].type;
-    dst->e[offset+i].nextTop = src->e[i].nextTop + offset;
-  }
-  dst->size += src->size;
+    return eg;
+}

 
 

-  return offset;
+EventGroup* CLG_(get_event_group)(int id)
+{
+    CLG_ASSERT(id>=0 && id<MAX_EVENTGROUP_COUNT);
+
+    return eventGroup[id];

 }
 
 }
 

-/* Incorporate two event types into a set, with second < first */
-Int CLG_(add_dep_event2)(EventSet* es, EventType* e1, EventType* e2)
+
+static
+EventSet* eventset_from_mask(UInt mask)

 {
 {

-  Int offset = es->size;
+    EventSet* es;
+    Int i, count, offset;

 
 

-  if (es->capacity - offset < 2) return -1;
+    if (mask >= MAX_EVENTSET_COUNT) return 0;

 
 

-  es->size += 2;
-  es->e[offset].type = e1;
-  es->e[offset].nextTop = es->size;
-  es->e[offset+1].type = e2;
-  es->e[offset+1].nextTop = es->size;
-  
-  return offset;
+    initialize_event_sets();
+    if (eventSetTable[mask]) return eventSetTable[mask];
+
+    es = (EventSet*) CLG_MALLOC("cl.events.eventset.1", sizeof(EventSet));
+    es->mask = mask;
+
+    offset = 0;
+    count = 0;
+    for(i=0;i<MAX_EVENTGROUP_COUNT;i++) {
+       es->offset[i] = offset;
+       if ( ((mask & (1u<<i))==0) || (eventGroup[i]==0))
+           continue;
+
+       offset += eventGroup[i]->size;
+       count++;
+    }
+    es->size = offset;
+    es->count = count;
+
+    eventSetTable[mask] = es;
+    return es;

 }
 
 }
 

-/* Incorporate 3 event types into a set, with third < second < first */
-Int CLG_(add_dep_event3)(EventSet* es,
-                       EventType* e1, EventType* e2, EventType* e3)
+EventSet* CLG_(get_event_set)(Int id)

 {
 {

-  Int offset = es->size;
+    CLG_ASSERT(id>=0 && id<MAX_EVENTGROUP_COUNT);
+    return eventset_from_mask(1u << id);
+}

 
 

-  if (es->capacity - offset < 3) return -1;
+EventSet* CLG_(get_event_set2)(Int id1, Int id2)
+{
+    CLG_ASSERT(id1>=0 && id1<MAX_EVENTGROUP_COUNT);
+    CLG_ASSERT(id2>=0 && id2<MAX_EVENTGROUP_COUNT);
+    return eventset_from_mask((1u << id1) | (1u << id2));
+}

 
 

-  es->size += 3;
-  es->e[offset].type = e1;
-  es->e[offset].nextTop = es->size;
-  es->e[offset+1].type = e2;
-  es->e[offset+1].nextTop = es->size;
-  es->e[offset+2].type = e3;
-  es->e[offset+2].nextTop = es->size;
-  
-  return offset;
+EventSet* CLG_(get_event_set3)(Int id1, Int id2, Int id3)
+{
+    CLG_ASSERT(id1>=0 && id1<MAX_EVENTGROUP_COUNT);
+    CLG_ASSERT(id2>=0 && id2<MAX_EVENTGROUP_COUNT);
+    CLG_ASSERT(id3>=0 && id3<MAX_EVENTGROUP_COUNT);
+    return eventset_from_mask((1u << id1) | (1u << id2) | (1u << id3));

 }
 
 }
 

-Int CLG_(add_dep_event4)(EventSet* es,
-                       EventType* e1, EventType* e2,
-                       EventType* e3, EventType* e4)
+EventSet* CLG_(add_event_group)(EventSet* es, Int id)

 {
 {

-  Int offset = es->size;
+    CLG_ASSERT(id>=0 && id<MAX_EVENTGROUP_COUNT);
+    if (!es) es = eventset_from_mask(0);
+    return eventset_from_mask(es->mask | (1u << id));
+}

 
 

-  if (es->capacity - offset < 4) return -1;
+EventSet* CLG_(add_event_group2)(EventSet* es, Int id1, Int id2)
+{
+    CLG_ASSERT(id1>=0 && id1<MAX_EVENTGROUP_COUNT);
+    CLG_ASSERT(id2>=0 && id2<MAX_EVENTGROUP_COUNT);
+    if (!es) es = eventset_from_mask(0);
+    return eventset_from_mask(es->mask | (1u << id1) | (1u << id2));
+}

 
 

-  es->size += 4;
-  es->e[offset].type = e1;
-  es->e[offset].nextTop = es->size;
-  es->e[offset+1].type = e2;
-  es->e[offset+1].nextTop = es->size;
-  es->e[offset+2].type = e3;
-  es->e[offset+2].nextTop = es->size;
-  es->e[offset+3].type = e4;
-  es->e[offset+3].nextTop = es->size;
-  
-  return offset;
+EventSet* CLG_(add_event_set)(EventSet* es1, EventSet* es2)
+{
+    if (!es1) es1 = eventset_from_mask(0);
+    if (!es2) es2 = eventset_from_mask(0);
+    return eventset_from_mask(es1->mask | es2->mask);

 }
 
 }
 

-/* Returns number of characters written */

 Int CLG_(sprint_eventset)(Char* buf, EventSet* es)
 {
 Int CLG_(sprint_eventset)(Char* buf, EventSet* es)
 {

-  Int i, pos = 0;
-
-  for(i=0; i< es->size; i++) {
-    if (pos>0) buf[pos++] = ' ';
-    pos += VG_(sprintf)(buf + pos, "%s", es->e[i].type->name);
-  }
-  buf[pos] = 0;
+    Int i, j, pos;
+    UInt mask;
+    EventGroup* eg;
+
+
+    CLG_ASSERT(es->size >0);
+    pos = 0;
+    for(i=0, mask=1; i<MAX_EVENTGROUP_COUNT; i++, mask=mask<<1) {
+       if ((es->mask & mask)==0) continue;
+       if (eventGroup[i] ==0) continue;
+
+       eg = eventGroup[i];
+       for(j=0; j<eg->size; j++) {
+           if (pos>0) buf[pos++] = ' ';
+           pos += VG_(sprintf)(buf + pos, "%s", eg->name[j]);
+       }
+    }
+    buf[pos] = 0;

 
 

-  return pos;
+    return pos;

 }
 
 }
 

+

 /* Get cost array for an event set */
 ULong* CLG_(get_eventset_cost)(EventSet* es)
 {
 /* Get cost array for an event set */
 ULong* CLG_(get_eventset_cost)(EventSet* es)
 {

-  return CLG_(get_costarray)(es->capacity);
+    return CLG_(get_costarray)(es->size);

 }
 
 /* Set all costs of an event set to zero */
 void CLG_(init_cost)(EventSet* es, ULong* cost)
 {
 }
 
 /* Set all costs of an event set to zero */
 void CLG_(init_cost)(EventSet* es, ULong* cost)
 {

-  Int i;
+    Int i;

 
 

-  if (!cost) return;
+    if (!cost) return;

 
 

-  for(i=0;i<es->capacity;i++)
-    cost[i] = 0;
+    for(i=0; i<es->size; i++)
+       cost[i] = 0;

 }
 
 /* Set all costs of an event set to zero */
 void CLG_(init_cost_lz)(EventSet* es, ULong** cost)
 {
 }
 
 /* Set all costs of an event set to zero */
 void CLG_(init_cost_lz)(EventSet* es, ULong** cost)
 {

-  Int i;
+    Int i;

 
 

-  CLG_ASSERT(cost != 0);
-  if (!(*cost))
-    *cost = CLG_(get_eventset_cost)(es);
+    CLG_ASSERT(cost != 0);
+    if (!(*cost))
+       *cost = CLG_(get_eventset_cost)(es);

 
 

-  for(i=0;i<es->capacity;i++)
-    (*cost)[i] = 0;
+    for(i=0; i<es->size; i++)
+       (*cost)[i] = 0;

 }
 
 void CLG_(zero_cost)(EventSet* es, ULong* cost)
 {
 }
 
 void CLG_(zero_cost)(EventSet* es, ULong* cost)
 {

-  Int i;
+    Int i;

 
 

-  if (!cost) return;
+    if (!cost) return;

 
 

-  for(i=0;i<es->size;i++)
-    cost[i] = 0;
+    for(i=0;i<es->size;i++)
+       cost[i] = 0;

 }
   
 Bool CLG_(is_zero_cost)(EventSet* es, ULong* cost)
 {
 }
   
 Bool CLG_(is_zero_cost)(EventSet* es, ULong* cost)
 {

-  Int i = 0;
+    Int i;

 
 

-  if (!cost) return True;
+    if (!cost) return True;

 
 

-  while(i<es->size) {
-    if (cost[i] != 0) return False;
-    i = es->e[i].nextTop;
-  }
-  return True;
+    for(i=0; i<es->size; i++)
+       if (cost[i] != 0) return False;
+
+    return True;

 }
 
 Bool CLG_(is_equal_cost)(EventSet* es, ULong* c1, ULong* c2)
 {
 }
 
 Bool CLG_(is_equal_cost)(EventSet* es, ULong* c1, ULong* c2)
 {

-  Int i = 0;
+    Int i;

 
 

-  if (!c1) return CLG_(is_zero_cost)(es,c2);
-  if (!c2) return CLG_(is_zero_cost)(es,c1);
+    if (!c1) return CLG_(is_zero_cost)(es, c2);
+    if (!c2) return CLG_(is_zero_cost)(es, c1);

 
 

-  while(i<es->size) {
-    if (c1[i] != c2[i]) return False;
-    if (c1[i] == 0)
-      i = es->e[i].nextTop;
-    else
-      i++;
-  }
-  return True;
+    for(i=0; i<es->size; i++)
+       if (c1[i] != c2[i]) return False;
+
+    return True;

 }
 
 void CLG_(copy_cost)(EventSet* es, ULong* dst, ULong* src)
 {
 }
 
 void CLG_(copy_cost)(EventSet* es, ULong* dst, ULong* src)
 {

-  Int i;
+    Int i;

 
 

-  if (!src) {
-    CLG_(zero_cost)(es, dst);
-    return;
-  }
-  CLG_ASSERT(dst != 0);
+    if (!src) {
+       CLG_(zero_cost)(es, dst);
+       return;
+    }
+    CLG_ASSERT(dst != 0);

   
   

-  for(i=0;i<es->size;i++)
-    dst[i] = src[i];
+    for(i=0;i<es->size;i++)
+       dst[i] = src[i];

 }
 
 void CLG_(copy_cost_lz)(EventSet* es, ULong** pdst, ULong* src)
 {
 }
 
 void CLG_(copy_cost_lz)(EventSet* es, ULong** pdst, ULong* src)
 {

-  Int i;
-  ULong* dst;
+    Int i;
+    ULong* dst;

 
 

-  CLG_ASSERT(pdst != 0);
+    CLG_ASSERT(pdst != 0);

 
 

-  if (!src) {
-    CLG_(zero_cost)(es, *pdst);
-    return;
-  }
-  dst = *pdst;
-  if (!dst)
-    dst = *pdst = CLG_(get_eventset_cost)(es);
+    if (!src) {
+       CLG_(zero_cost)(es, *pdst);
+       return;
+    }
+    dst = *pdst;
+    if (!dst)
+       dst = *pdst = CLG_(get_eventset_cost)(es);

   
   

-  for(i=0;i<es->size;i++)
-    dst[i] = src[i];
+    for(i=0;i<es->size;i++)
+       dst[i] = src[i];

 }
 
 void CLG_(add_cost)(EventSet* es, ULong* dst, ULong* src)
 {
 }
 
 void CLG_(add_cost)(EventSet* es, ULong* dst, ULong* src)
 {

-  Int i = 0;
+    Int i;

 
 

-  if (!src) return;
-  CLG_ASSERT(dst != 0);
+    if (!src) return;
+    CLG_ASSERT(dst != 0);

 
 

-  while(i<es->size) {
-    if (src[i] == 0)
-      i = es->e[i].nextTop;
-    else {
-      dst[i] += src[i];
-      i++;
-    }
-  }
+    for(i=0; i<es->size; i++)
+       dst[i] += src[i];

 }
 
 void CLG_(add_cost_lz)(EventSet* es, ULong** pdst, ULong* src)
 {
 }
 
 void CLG_(add_cost_lz)(EventSet* es, ULong** pdst, ULong* src)
 {

-  Int i;
-  ULong* dst;
-
-  if (!src) return;
-  CLG_ASSERT(pdst != 0);
-
-  dst = *pdst;
-  if (!dst) {
-    dst = *pdst = CLG_(get_eventset_cost)(es);
-    CLG_(copy_cost)(es,dst,src);
-    return;
-  }
-
-  i = 0;
-  while(i<es->size) {
-    if (src[i] == 0)
-      i = es->e[i].nextTop;
-    else {
-      dst[i] += src[i];
-      i++;
+    Int i;
+    ULong* dst;
+
+    if (!src) return;
+    CLG_ASSERT(pdst != 0);
+
+    dst = *pdst;
+    if (!dst) {
+       dst = *pdst = CLG_(get_eventset_cost)(es);
+       CLG_(copy_cost)(es, dst, src);
+       return;

     }
     }

-  }
+
+    for(i=0; i<es->size; i++)
+       dst[i] += src[i];

 }
 
 /* Adds src to dst and zeros src. Returns false if nothing changed */
 Bool CLG_(add_and_zero_cost)(EventSet* es, ULong* dst, ULong* src)
 {
 }
 
 /* Adds src to dst and zeros src. Returns false if nothing changed */
 Bool CLG_(add_and_zero_cost)(EventSet* es, ULong* dst, ULong* src)
 {

-  Int i = 0, j = 0;
-
-  CLG_DEBUGIF(6) {
-    CLG_DEBUG(6, "   add_and_zero_cost(%s, dst %p, src %p)\n", es->name, dst, src);
-    CLG_(print_cost)(-5, es, src);
-  }
+    Int i;
+    Bool is_nonzero = False;

 
 

-  if (!es || !src) return False;
+    CLG_ASSERT((es != 0) && (dst != 0));
+    if (!src) return False;

 
 

-  while(i<es->size) {
-    if (src[i] == 0)
-      i = es->e[i].nextTop;
-    else {
-      dst[i] += src[i];
-      src[i] = 0;
-      i++;
-      j++;
+    for(i=0; i<es->size; i++) {
+       if (src[i]==0) continue;
+       dst[i] += src[i];
+       src[i] = 0;
+       is_nonzero = True;

     }
     }

-  }

 
 

-  return (j>0);
+    return is_nonzero;

 }
 
 /* Adds src to dst and zeros src. Returns false if nothing changed */
 }
 
 /* Adds src to dst and zeros src. Returns false if nothing changed */

-Bool CLG_(add_and_zero_cost_lz)(EventSet* es, ULong** pdst, ULong* src)
-{
-  Int i;
-  ULong* dst;
-
-  if (!src) return False;
-
-  i = 0;
-  while(1) {
-    if (i >= es->size) return False;
-    if (src[i] != 0) break;
-    i = es->e[i].nextTop;
-  }
-
-  CLG_ASSERT(pdst != 0);
-  dst = *pdst;
-  if (!dst) {
-    dst = *pdst = CLG_(get_eventset_cost)(es);
-    CLG_(copy_cost)(es,dst,src);
-    CLG_(zero_cost)(es,src);
-    return True;
-  }
-
-  dst[i] += src[i];
-  src[i] = 0;
-  i++;
-
-  while(i<es->size) {
-    if (src[i] == 0)
-      i = es->e[i].nextTop;
-    else {
-      dst[i] += src[i];
-      src[i] = 0;
+Bool CLG_(add_and_zero_cost2)(EventSet* esDst, ULong* dst,
+                             EventSet* esSrc, ULong* src)
+{
+    Int i,j;
+    Bool is_nonzero = False;
+    UInt mask;
+    EventGroup *eg;
+    ULong *egDst, *egSrc;
+
+    CLG_ASSERT((esDst != 0) && (dst != 0) && (esSrc != 0));
+    if (!src) return False;
+
+    for(i=0, mask=1; i<MAX_EVENTGROUP_COUNT; i++, mask=mask<<1) {
+       if ((esSrc->mask & mask)==0) continue;
+       if (eventGroup[i] ==0) continue;
+
+       /* if src has a subset, dst must have, too */
+       CLG_ASSERT((esDst->mask & mask)>0);
+       eg = eventGroup[i];
+       egSrc = src + esSrc->offset[i];
+       egDst = dst + esDst->offset[i];
+       for(j=0; j<eg->size; j++) {
+           if (egSrc[j]==0) continue;
+           egDst[j] += egSrc[j];
+           egSrc[j] = 0;
+           is_nonzero = True;
+       }

     }
     }

-  }

 
 

-  return True;
+    return is_nonzero;

 }
 
 }
 

+
+

 /* Adds difference of new and old to dst, and set old to new.
  * Returns false if nothing changed */
 Bool CLG_(add_diff_cost)(EventSet* es, ULong* dst, ULong* old, ULong* new_cost)
 {
 /* Adds difference of new and old to dst, and set old to new.
  * Returns false if nothing changed */
 Bool CLG_(add_diff_cost)(EventSet* es, ULong* dst, ULong* old, ULong* new_cost)
 {

-  Int i = 0, j = 0;
+    Int i;
+    Bool is_nonzero = False;

 
 

-  while(i<es->size) {
-    if (new_cost[i] == old[i])
-      i = es->e[i].nextTop;
-    else {
-      dst[i] += new_cost[i] - old[i];
-      old[i] = new_cost[i];
-      i++;
-      j++;
+    CLG_ASSERT((es != 0) && (dst != 0));
+    CLG_ASSERT(old && new_cost);
+
+    for(i=0; i<es->size; i++) {
+       if (new_cost[i] == old[i]) continue;
+       dst[i] += new_cost[i] - old[i];
+       old[i] = new_cost[i];
+       is_nonzero = True;

     }
     }

-  }

 
 

-  return (j>0);
+    return is_nonzero;

 }
 
 }
 

-/* Adds difference of new and old to dst, and set old to new.
- * Returns false if nothing changed */
-Bool CLG_(add_diff_cost_lz)(EventSet* es, ULong** pdst, 
-                           ULong* old, ULong* new_cost)
-{
-  Int i;
-  ULong* dst;
-
-  if (!old && !new_cost) return False;
-  CLG_ASSERT(old && new_cost);
-
-  i = 0;
-  while(1) {
-    if (i >= es->size) return False;
-    if (old[i] != new_cost[i]) break;
-    i = es->e[i].nextTop;
-  }
-
-  CLG_ASSERT(pdst != 0);
-  dst = *pdst;
-  if (!dst) {
-    dst = *pdst = CLG_(get_eventset_cost)(es);
-    CLG_(zero_cost)(es,dst);
-  }
-
-  dst[i] += new_cost[i] - old[i];
-  old[i] = new_cost[i];
-  i++;
-
-  while(i<es->size) {
-    if (new_cost[i] == old[i])
-      i = es->e[i].nextTop;
-    else {
-      dst[i] += new_cost[i] - old[i];
-      old[i] = new_cost[i];
-      i++;
+Bool CLG_(add_diff_cost_lz)(EventSet* es, ULong** pdst, ULong* old, ULong* new_cost)
+{
+    Int i;
+    ULong* dst;
+    Bool is_nonzero = False;
+
+    CLG_ASSERT((es != 0) && (pdst != 0));
+    CLG_ASSERT(old && new_cost);
+
+    dst = *pdst;
+    if (!dst) {
+       dst = *pdst = CLG_(get_eventset_cost)(es);
+       CLG_(zero_cost)(es, dst);

     }
     }

-  }

 
 

-  return True;
+    for(i=0; i<es->size; i++) {
+       if (new_cost[i] == old[i]) continue;
+       dst[i] += new_cost[i] - old[i];
+       old[i] = new_cost[i];
+       is_nonzero = True;
+    }
+
+    return is_nonzero;

 }
 
 }
 

+

 /* Returns number of characters written */
 Int CLG_(sprint_cost)(Char* buf, EventSet* es, ULong* c)
 {
 /* Returns number of characters written */
 Int CLG_(sprint_cost)(Char* buf, EventSet* es, ULong* c)
 {

-  Int i, pos, skipped = 0;
+    Int i, pos, skipped = 0;

 
 

-  if (!c || es->size==0) return 0;
+    if (!c || es->size==0) return 0;

 
 

-  /* At least one entry */
-  pos = VG_(sprintf)(buf, "%llu", c[0]);
-  i = 1;
-
-  while(i<es->size) {
-    if (c[i] == 0) {
-      skipped  += es->e[i].nextTop - i;
-      i = es->e[i].nextTop;
-    }
-    else {
-      while(skipped>0) {
+    /* At least one entry */
+    pos = VG_(sprintf)(buf, "%llu", c[0]);
+    for(i=1; i<es->size; i++) {
+       if (c[i] == 0) {
+           skipped++;
+           continue;
+       }
+       while(skipped>0) {
+           buf[pos++] = ' ';
+           buf[pos++] = '0';
+           skipped--;
+       }

        buf[pos++] = ' ';
        buf[pos++] = ' ';

-       buf[pos++] = '0';
-       skipped--;
-      }
-      buf[pos++] = ' ';
-      pos += VG_(sprintf)(buf+pos, "%llu", c[i]);
-      i++;
+       pos += VG_(sprintf)(buf+pos, "%llu", c[i]);

     }
     }

-  }

 
 

-  return pos;
+    return pos;

 }
 
 
 /* Allocate space for an event mapping */
 EventMapping* CLG_(get_eventmapping)(EventSet* es)
 {
 }
 
 
 /* Allocate space for an event mapping */
 EventMapping* CLG_(get_eventmapping)(EventSet* es)
 {

-  EventMapping* em;
+    EventMapping* em;

 
 

-  CLG_ASSERT(es != 0);
+    CLG_ASSERT(es != 0);

 
 

-  em = (EventMapping*) CLG_MALLOC("cl.events.geMapping.1",
-                                   sizeof(EventMapping) +
-                                  es->capacity * sizeof(Int));
-  em->capacity = es->capacity;
-  em->size = 0;
-  em->set = es;
+    em = (EventMapping*) CLG_MALLOC("cl.events.geMapping.1",
+                                   sizeof(EventMapping) +
+                                   sizeof(struct EventMappingEntry) *
+                                   es->size);
+    em->capacity = es->size;
+    em->size = 0;
+    em->es = es;

 
 

-  return em;
+    return em;

 }
 
 void CLG_(append_event)(EventMapping* em, Char* n)
 {
 }
 
 void CLG_(append_event)(EventMapping* em, Char* n)
 {

-  Int i;
-
-  CLG_ASSERT(em != 0);
-
-  for(i=0; i<em->set->size; i++)
-    if (VG_(strcmp)(n, em->set->e[i].type->name)==0)
-      break;
-  
-  if (i == em->set->size) return;
-
-  CLG_ASSERT(em->capacity > em->size);
-
-  em->index[em->size] = i;
-  em->size++;
+    Int i, j, offset = 0;
+    UInt mask;
+    EventGroup* eg;
+
+    CLG_ASSERT(em != 0);
+    for(i=0, mask=1; i<MAX_EVENTGROUP_COUNT; i++, mask=mask<<1) {
+       if ((em->es->mask & mask)==0) continue;
+       if (eventGroup[i] ==0) continue;
+
+       eg = eventGroup[i];
+       for(j=0; j<eg->size; j++, offset++) {
+           if (VG_(strcmp)(n, eg->name[j])!=0)
+                   continue;
+
+           CLG_ASSERT(em->capacity > em->size);
+           em->entry[em->size].group = i;
+           em->entry[em->size].index = j;
+           em->entry[em->size].offset = offset;
+           em->size++;
+           return;
+       }
+    }

 }
 
 
 /* Returns number of characters written */
 Int CLG_(sprint_eventmapping)(Char* buf, EventMapping* em)
 {
 }
 
 
 /* Returns number of characters written */
 Int CLG_(sprint_eventmapping)(Char* buf, EventMapping* em)
 {

-  Int i, pos = 0;
+    Int i, pos = 0;
+    EventGroup* eg;

 
 

-  CLG_ASSERT(em != 0);
+    CLG_ASSERT(em != 0);

 
 

-  for(i=0; i< em->size; i++) {
-    if (pos>0) buf[pos++] = ' ';
-    pos += VG_(sprintf)(buf + pos, "%s", em->set->e[em->index[i]].type->name);
-  }
-  buf[pos] = 0;
+    for(i=0; i< em->size; i++) {
+       if (pos>0) buf[pos++] = ' ';
+       eg = eventGroup[em->entry[i].group];
+       CLG_ASSERT(eg != 0);
+       pos += VG_(sprintf)(buf + pos, "%s", eg->name[em->entry[i].index]);
+    }
+    buf[pos] = 0;

 
 

-  return pos;
+    return pos;

 }
 
 /* Returns number of characters written */
 Int CLG_(sprint_mappingcost)(Char* buf, EventMapping* em, ULong* c)
 {
 }
 
 /* Returns number of characters written */
 Int CLG_(sprint_mappingcost)(Char* buf, EventMapping* em, ULong* c)
 {

-  Int i, pos, skipped = 0;
+    Int i, pos, skipped = 0;

 
 

-  if (!c || em->size==0) return 0;
+    if (!c || em->size==0) return 0;

 
     /* At least one entry */
 
     /* At least one entry */

-  pos = VG_(sprintf)(buf, "%llu", c[em->index[0]]);
-  i = 1;
-
-  while(i<em->size) {
-    if (c[em->index[i]] == 0) {
-      skipped++;
-      i++;
-    }
-    else {
-      while(skipped>0) {
+    pos = VG_(sprintf)(buf, "%llu", c[em->entry[0].offset]);
+
+    for(i=1; i<em->size; i++) {
+       if (c[em->entry[i].offset] == 0) {
+           skipped++;
+           continue;
+       }
+       while(skipped>0) {
+           buf[pos++] = ' ';
+           buf[pos++] = '0';
+           skipped--;
+       }

        buf[pos++] = ' ';
        buf[pos++] = ' ';

-       buf[pos++] = '0';
-       skipped--;
-      }
-      buf[pos++] = ' ';
-      pos += VG_(sprintf)(buf+pos, "%llu", c[em->index[i]]);
-      i++;
+       pos += VG_(sprintf)(buf+pos, "%llu", c[em->entry[i].offset]);

     }
     }

-  }

 
 

-  return pos;
+    return pos;

 }
 }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/events.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/events.h
index c3ddbe36c5400ac47bb24dded1cd74f1fa379192..d892ccb050643ae03055b878d85a29c045ff2944 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/events.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/events.h
@@ -1,86 +1,90 @@
 /*--------------------------------------------------------------------*/
 /*--- Callgrind                                                    ---*/
 /*---                                                     events.h ---*/
 /*--------------------------------------------------------------------*/
 /*--- Callgrind                                                    ---*/
 /*---                                                     events.h ---*/

-/*--- (C) 2004-2005, Josef Weidendorfer                            ---*/

 /*--------------------------------------------------------------------*/
 
 /*--------------------------------------------------------------------*/
 

+/*
+   This file is part of Callgrind, a Valgrind tool for call tracing.
+
+   Copyright (C) 2002-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+*/

 
 /* Abstractions for 64-bit cost lists (events.h) */
 
 
 /* Abstractions for 64-bit cost lists (events.h) */
 

-#ifndef CG_EVENTS
-#define CG_EVENTS
+#ifndef CLG_EVENTS
+#define CLG_EVENTS

 
 #include "pub_tool_basics.h"
 
 #define CLG_(str) VGAPPEND(vgCallgrind_,str)
 
 
 #include "pub_tool_basics.h"
 
 #define CLG_(str) VGAPPEND(vgCallgrind_,str)
 

-/* An event type */
-typedef struct _EventType EventType;
-struct _EventType {
-  Char* name;
-  Char* description;
-  Int id;
-};
+/* Event groups consist of one or more named event types.
+ * Event sets are constructed from such event groups.
+ *
+ * Event groups have to be registered globally with a unique ID
+ * before they can be used in an event set.
+ * A group can appear at most once in a event set.
+ */

 
 

-EventType* CLG_(register_eventtype)(Char*);
-EventType* CLG_(get_eventtype)(Char*);
-EventType* CLG_(get_eventtype_byindex)(Int id);
+#define MAX_EVENTGROUP_COUNT 10

 
 

-/* An event set is a ordered list of event types, which comes down
- * to some description for ordered lists of costs.
- * Often, costs of 2 event types are related, e.g. one is always smaller
- * than the other. This is useful to speed up arithmetics on cost lists:
- * Each event type in the set has a <nextTop>. All indexes before are
- * promised to hold smaller values than the current.
- */
-typedef struct _EventSetEntry EventSetEntry;
-struct _EventSetEntry {
-  EventType* type;
-  Int nextTop;
-};
-typedef struct _EventSet EventSet;
-struct _EventSet {
-  Char* name;
-  Int size;
-  Int capacity;
-  EventSetEntry e[0];
+typedef struct _EventGroup EventGroup;
+struct _EventGroup {
+    Int size;
+    Char* name[0];

 };
 
 };
 

+/* return 0 if event group can not be registered */
+EventGroup* CLG_(register_event_group) (int id, Char*);
+EventGroup* CLG_(register_event_group2)(int id, Char*, Char*);
+EventGroup* CLG_(register_event_group3)(int id, Char*, Char*, Char*);
+EventGroup* CLG_(register_event_group4)(int id, Char*, Char*, Char*, Char*);
+EventGroup* CLG_(get_event_group)(int id);

 
 

-/* Some events out of an event set.
- * Used to print out part of an EventSet, or in another order.
- */
-typedef struct _EventMapping EventMapping;
-struct _EventMapping {
-  EventSet* set;
-  Int size;
-  Int capacity;
-  Int index[0];
-};
+/* Event sets are defined by event groups they consist of. */

 
 

-  
-/* Allocate space for an event set */
-EventSet* CLG_(get_eventset)(Char* n, Int capacity);
-/* Incorporate a event type into a set, get start offset */
-Int CLG_(add_eventtype)(EventSet* dst, EventType*);
-/* Incorporate event types into a set, with ... < second < first */
-Int CLG_(add_dep_event2)(EventSet* dst, EventType* e1, EventType* e2);
-Int CLG_(add_dep_event3)(EventSet* dst,
-                       EventType* e1, EventType* e2, EventType* e3);
-Int CLG_(add_dep_event4)(EventSet* dst,
-                       EventType* e1, EventType* e2, EventType* e3,
-                       EventType* e4);
-/* Incorporate one event set into another, get start offset */
-Int CLG_(add_eventset)(EventSet* dst, EventSet* src);
-/* Returns number of characters written */
+typedef struct _EventSet EventSet;
+struct _EventSet {
+    /* if subset with ID x is in the set, then bit x is set */
+    UInt mask;
+    Int count;
+    Int size;
+    Int offset[MAX_EVENTGROUP_COUNT];
+ };
+
+/* Same event set is returned when requesting same event groups */
+EventSet* CLG_(get_event_set)(Int id);
+EventSet* CLG_(get_event_set2)(Int id1, Int id2);
+EventSet* CLG_(get_event_set3)(Int id1, Int id2, Int id3);
+EventSet* CLG_(add_event_group)(EventSet*, Int id);
+EventSet* CLG_(add_event_group2)(EventSet*, Int id1, Int id2);
+EventSet* CLG_(add_event_set)(EventSet*, EventSet*);
+/* Writes event names into buf. Returns number of characters written */

 Int CLG_(sprint_eventset)(Char* buf, EventSet*);
 Int CLG_(sprint_eventset)(Char* buf, EventSet*);

-/* Allocate cost array for an event set */
-ULong* CLG_(get_eventset_cost)(EventSet*);
+

 
 /* Operations on costs. A cost pointer of 0 means zero cost.
 
 /* Operations on costs. A cost pointer of 0 means zero cost.

- * Functions ending in _lz allocate costs lazy if needed
+ * Functions ending in _lz allocate cost arrays only when needed

  */
  */

-/* Set costs according full capacity of event set to 0 */
+ULong* CLG_(get_eventset_cost)(EventSet*);
+/* Set costs of event set to 0 */

 void CLG_(init_cost)(EventSet*,ULong*);
 /* This always allocates counter and sets them to 0 */
 void CLG_(init_cost_lz)(EventSet*,ULong**);
 void CLG_(init_cost)(EventSet*,ULong*);
 /* This always allocates counter and sets them to 0 */
 void CLG_(init_cost_lz)(EventSet*,ULong**);


@@ -94,7 +98,7 @@ void CLG_(add_cost)(EventSet*,ULong* dst, ULong* src);
 void CLG_(add_cost_lz)(EventSet*,ULong** pdst, ULong* src);
 /* Adds src to dst and zeros src. Returns false if nothing changed */
 Bool CLG_(add_and_zero_cost)(EventSet*,ULong* dst, ULong* src);
 void CLG_(add_cost_lz)(EventSet*,ULong** pdst, ULong* src);
 /* Adds src to dst and zeros src. Returns false if nothing changed */
 Bool CLG_(add_and_zero_cost)(EventSet*,ULong* dst, ULong* src);

-Bool CLG_(add_and_zero_cost_lz)(EventSet*,ULong** pdst, ULong* src);
+Bool CLG_(add_and_zero_cost2)(EventSet*,ULong* dst,EventSet*,ULong* src);

 /* Adds difference of new and old to to dst, and set old to new.
  * Returns false if nothing changed */
 Bool CLG_(add_diff_cost)(EventSet*,ULong* dst, ULong* old, ULong* new_cost);
 /* Adds difference of new and old to to dst, and set old to new.
  * Returns false if nothing changed */
 Bool CLG_(add_diff_cost)(EventSet*,ULong* dst, ULong* old, ULong* new_cost);


@@ -102,6 +106,22 @@ Bool CLG_(add_diff_cost_lz)(EventSet*,ULong** pdst, ULong* old, ULong* new_cost)
 /* Returns number of characters written */
 Int CLG_(sprint_cost)(Char* buf, EventSet*, ULong*);
 
 /* Returns number of characters written */
 Int CLG_(sprint_cost)(Char* buf, EventSet*, ULong*);
 

+/* EventMapping: An ordered subset of events from an event set.
+ * This is used to print out part of an EventSet, or in another order.
+ */
+struct EventMappingEntry {
+    Int group;
+    Int index;
+    Int offset;
+};
+typedef struct _EventMapping EventMapping;
+struct _EventMapping {
+  EventSet* es;
+  Int size;
+  Int capacity;
+  struct EventMappingEntry entry[0];
+};
+

 /* Allocate space for an event mapping */
 EventMapping* CLG_(get_eventmapping)(EventSet*);
 void CLG_(append_event)(EventMapping*, Char*);
 /* Allocate space for an event mapping */
 EventMapping* CLG_(get_eventmapping)(EventSet*);
 void CLG_(append_event)(EventMapping*, Char*);


@@ -110,4 +130,4 @@ Int CLG_(sprint_eventmapping)(Char* buf, EventMapping*);
 /* Returns number of characters written */
 Int CLG_(sprint_mappingcost)(Char* buf, EventMapping*, ULong*);
 
 /* Returns number of characters written */
 Int CLG_(sprint_mappingcost)(Char* buf, EventMapping*, ULong*);
 

-#endif /* CG_EVENTS */
+#endif /* CLG_EVENTS */

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/global.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/global.h
index 367f2d7d34684cbc529772b38dd6a11c86e810e4..706edec988d383b28a96ff8c775fd1be85985da0 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/global.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/global.h
@@ -87,9 +87,12 @@ struct _CommandLineOptions {
   Bool collect_alloc;    /* Collect size of allocated memory */
   Bool collect_systime;  /* Collect time for system calls */
 
   Bool collect_alloc;    /* Collect size of allocated memory */
   Bool collect_systime;  /* Collect time for system calls */
 

+  Bool collect_bus;      /* Collect global bus events */
+

   /* Instrument options */
   Bool instrument_atstart;  /* Instrument at start? */
   Bool simulate_cache;      /* Call into cache simulator ? */
   /* Instrument options */
   Bool instrument_atstart;  /* Instrument at start? */
   Bool simulate_cache;      /* Call into cache simulator ? */

+  Bool simulate_branch;     /* Call into branch prediction simulator ? */

 
   /* Call graph generation */
   Bool pop_on_jump;       /* Handle a jump between functions as ret+call */
 
   /* Call graph generation */
   Bool pop_on_jump;       /* Handle a jump between functions as ret+call */


@@ -650,9 +653,8 @@ struct cachesim_if
     void (*post_clo_init)(void);
     void (*clear)(void);
     void (*getdesc)(Char* buf);
     void (*post_clo_init)(void);
     void (*clear)(void);
     void (*getdesc)(Char* buf);

-    void (*printstat)(void);  
+    void (*printstat)(Int,Int,Int);

     void (*add_icost)(SimCost, BBCC*, InstrInfo*, ULong);
     void (*add_icost)(SimCost, BBCC*, InstrInfo*, ULong);

-    void (*after_bbsetup)(void);

     void (*finish)(void);
     
     void (*log_1I0D)(InstrInfo*) VG_REGPARM(1);
     void (*finish)(void);
     
     void (*log_1I0D)(InstrInfo*) VG_REGPARM(1);


@@ -671,6 +673,28 @@ struct cachesim_if
     Char *log_0I1Dr_name, *log_0I1Dw_name;
 };
 
     Char *log_0I1Dr_name, *log_0I1Dw_name;
 };
 

+// set by setup_bbcc at start of every BB, and needed by log_* helpers
+extern Addr   CLG_(bb_base);
+extern ULong* CLG_(cost_base);
+
+// Event groups
+#define EG_USE   0
+#define EG_IR    1
+#define EG_DR    2
+#define EG_DW    3
+#define EG_BC    4
+#define EG_BI    5
+#define EG_BUS   6
+#define EG_ALLOC 7
+#define EG_SYS   8
+
+struct event_sets {
+    EventSet *base, *full;
+};
+extern struct event_sets CLG_(sets);
+
+#define fullOffset(group) (CLG_(sets).full->offset[group])
+

 
 /*------------------------------------------------------------*/
 /*--- Functions                                            ---*/
 
 /*------------------------------------------------------------*/
 /*--- Functions                                            ---*/


@@ -685,20 +709,8 @@ void CLG_(print_usage)(void);
 void CLG_(print_debug_usage)(void);
 
 /* from sim.c */
 void CLG_(print_debug_usage)(void);
 
 /* from sim.c */

-struct event_sets {
-  EventSet *Use, *Ir, *Dr, *Dw;
-  EventSet *UIr, *UIrDr, *UIrDrDw, *UIrDw, *UIrDwDr;
-  EventSet *full;
-
-  /* offsets into eventsets */  
-  Int off_full_Ir, off_full_Dr, off_full_Dw;
-  Int off_full_alloc, off_full_systime;
-};
-
-extern struct event_sets CLG_(sets);

 extern struct cachesim_if CLG_(cachesim);
 extern struct cachesim_if CLG_(cachesim);

-
-void CLG_(init_eventsets)(Int user);
+void CLG_(init_eventsets)(void);

 
 /* from main.c */
 Bool CLG_(get_debug_info)(Addr, Char filename[FILENAME_LEN],
 
 /* from main.c */
 Bool CLG_(get_debug_info)(Addr, Char filename[FILENAME_LEN],

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/main.c
index 3f02517b0927f5f7f39a6ddbd53090f29e46651c..2dd7e18a99b85d79405912fc4b4a8eb5a052088b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/main.c
@@ -37,6 +37,8 @@
 
 #include <pub_tool_threadstate.h>
 
 
 #include <pub_tool_threadstate.h>
 

+#include "cg_branchpred.c"
+

 /*------------------------------------------------------------*/
 /*--- Global variables                                     ---*/
 /*------------------------------------------------------------*/
 /*------------------------------------------------------------*/
 /*--- Global variables                                     ---*/
 /*------------------------------------------------------------*/


@@ -94,6 +96,97 @@ static void CLG_(init_statistics)(Statistics* s)
 }
 
 
 }
 
 

+/*------------------------------------------------------------*/
+/*--- Simple callbacks (not cache similator)               ---*/
+/*------------------------------------------------------------*/
+
+VG_REGPARM(1)
+static void log_global_event(InstrInfo* ii)
+{
+    ULong* cost_Bus;
+
+    CLG_DEBUG(6, "log_global_event:  Ir  %#lx/%u\n",
+              CLG_(bb_base) + ii->instr_offset, ii->instr_size);
+
+    if (!CLG_(current_state).collect) return;
+
+    CLG_ASSERT( (ii->eventset->mask & (1u<<EG_BUS))>0 );
+
+    CLG_(current_state).cost[ fullOffset(EG_BUS) ]++;
+
+    if (CLG_(current_state).nonskipped)
+        cost_Bus = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BUS);
+    else
+        cost_Bus = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BUS];
+    cost_Bus[0]++;
+}
+
+
+/* For branches, we consult two different predictors, one which
+   predicts taken/untaken for conditional branches, and the other
+   which predicts the branch target address for indirect branches
+   (jump-to-register style ones). */
+
+static VG_REGPARM(2)
+void log_cond_branch(InstrInfo* ii, Word taken)
+{
+    Bool miss;
+    Int fullOffset_Bc;
+    ULong* cost_Bc;
+
+    CLG_DEBUG(6, "log_cond_branch:  Ir %#lx, taken %lu\n",
+              CLG_(bb_base) + ii->instr_offset, taken);
+
+    miss = 1 & do_cond_branch_predict(CLG_(bb_base) + ii->instr_offset, taken);
+
+    if (!CLG_(current_state).collect) return;
+
+    CLG_ASSERT( (ii->eventset->mask & (1u<<EG_BC))>0 );
+
+    if (CLG_(current_state).nonskipped)
+        cost_Bc = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BC);
+    else
+        cost_Bc = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BC];
+
+    fullOffset_Bc = fullOffset(EG_BC);
+    CLG_(current_state).cost[ fullOffset_Bc ]++;
+    cost_Bc[0]++;
+    if (miss) {
+        CLG_(current_state).cost[ fullOffset_Bc+1 ]++;
+        cost_Bc[1]++;
+    }
+}
+
+static VG_REGPARM(2)
+void log_ind_branch(InstrInfo* ii, UWord actual_dst)
+{
+    Bool miss;
+    Int fullOffset_Bi;
+    ULong* cost_Bi;
+
+    CLG_DEBUG(6, "log_ind_branch:  Ir  %#lx, dst %#lx\n",
+              CLG_(bb_base) + ii->instr_offset, actual_dst);
+
+    miss = 1 & do_ind_branch_predict(CLG_(bb_base) + ii->instr_offset, actual_dst);
+
+    if (!CLG_(current_state).collect) return;
+
+    CLG_ASSERT( (ii->eventset->mask & (1u<<EG_BI))>0 );
+
+    if (CLG_(current_state).nonskipped)
+        cost_Bi = CLG_(current_state).nonskipped->skipped + fullOffset(EG_BI);
+    else
+        cost_Bi = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_BI];
+
+    fullOffset_Bi = fullOffset(EG_BI);
+    CLG_(current_state).cost[ fullOffset_Bi ]++;
+    cost_Bi[0]++;
+    if (miss) {
+        CLG_(current_state).cost[ fullOffset_Bi+1 ]++;
+        cost_Bi[1]++;
+    }
+}
+

 /*------------------------------------------------------------*/
 /*--- Instrumentation structures and event queue handling  ---*/
 /*------------------------------------------------------------*/
 /*------------------------------------------------------------*/
 /*--- Instrumentation structures and event queue handling  ---*/
 /*------------------------------------------------------------*/


@@ -137,6 +230,9 @@ typedef
       Ev_Dr,  // Data read
       Ev_Dw,  // Data write
       Ev_Dm,  // Data modify (read then write)
       Ev_Dr,  // Data read
       Ev_Dw,  // Data write
       Ev_Dm,  // Data modify (read then write)

+      Ev_Bc,  // branch conditional
+      Ev_Bi,  // branch indirect (to unknown destination)
+      Ev_G    // Global bus event

    }
    EventTag;
 
    }
    EventTag;
 


@@ -159,6 +255,14 @@ typedef
            IRAtom* ea;
            Int     szB;
         } Dm;
            IRAtom* ea;
            Int     szB;
         } Dm;

+         struct {
+            IRAtom* taken; /* :: Ity_I1 */
+         } Bc;
+         struct {
+            IRAtom* dst;
+         } Bi;
+        struct {
+        } G;

       } Ev;
    }
    Event;
       } Ev;
    }
    Event;


@@ -242,6 +346,19 @@ static void showEvent ( Event* ev )
         ppIRExpr(ev->Ev.Dm.ea);
         VG_(printf)("\n");
         break;
         ppIRExpr(ev->Ev.Dm.ea);
         VG_(printf)("\n");
         break;

+      case Ev_Bc:
+         VG_(printf)("Bc %p   GA=", ev->inode);
+         ppIRExpr(ev->Ev.Bc.taken);
+         VG_(printf)("\n");
+         break;
+      case Ev_Bi:
+         VG_(printf)("Bi %p  DST=", ev->inode);
+         ppIRExpr(ev->Ev.Bi.dst);
+         VG_(printf)("\n");
+         break;
+      case Ev_G:
+         VG_(printf)("G  %p\n", ev->inode);
+         break;

       default:
         tl_assert(0);
         break;
       default:
         tl_assert(0);
         break;


@@ -273,34 +390,33 @@ static void flushEvents ( ClgState* clgs )
           case Ev_Ir:
               // Ir event always is first for a guest instruction
               CLG_ASSERT(ev->inode->eventset == 0);
           case Ev_Ir:
               // Ir event always is first for a guest instruction
               CLG_ASSERT(ev->inode->eventset == 0);

-              ev->inode->eventset = CLG_(sets).UIr;
+              ev->inode->eventset = CLG_(sets).base;

               break;
           case Ev_Dr:
               break;
           case Ev_Dr:

-              // extend event set by Dr counter
-              if ((ev->inode->eventset == CLG_(sets).UIrDr)   ||
-                  (ev->inode->eventset == CLG_(sets).UIrDrDw) ||
-                  (ev->inode->eventset == CLG_(sets).UIrDwDr))
-                  break;
-              if (ev->inode->eventset == CLG_(sets).UIrDw) {
-                  ev->inode->eventset = CLG_(sets).UIrDwDr;
-                  break;
-              }
-              CLG_ASSERT(ev->inode->eventset == CLG_(sets).UIr);
-              ev->inode->eventset = CLG_(sets).UIrDr;
+               // extend event set by Dr counters
+              ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
+                                                          EG_DR);

               break;
           case Ev_Dw:
           case Ev_Dm:
               break;
           case Ev_Dw:
           case Ev_Dm:

-              // extend event set by Dw counter
-              if ((ev->inode->eventset == CLG_(sets).UIrDw)   ||
-                  (ev->inode->eventset == CLG_(sets).UIrDwDr) ||
-                  (ev->inode->eventset == CLG_(sets).UIrDrDw))
-                  break;
-              if (ev->inode->eventset == CLG_(sets).UIrDr) {
-                  ev->inode->eventset = CLG_(sets).UIrDrDw;
-                  break;
-              }
-              CLG_ASSERT(ev->inode->eventset == CLG_(sets).UIr);
-              ev->inode->eventset = CLG_(sets).UIrDw;
+               // extend event set by Dw counters
+              ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
+                                                          EG_DW);
+              break;
+           case Ev_Bc:
+               // extend event set by Bc counters
+               ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
+                                                           EG_BC);
+               break;
+           case Ev_Bi:
+               // extend event set by Bi counters
+               ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
+                                                           EG_BI);
+               break;
+          case Ev_G:
+               // extend event set by Bus counter
+              ev->inode->eventset = CLG_(add_event_group)(ev->inode->eventset,
+                                                          EG_BUS);

               break;
           default:
               tl_assert(0);
               break;
           default:
               tl_assert(0);


@@ -417,6 +533,30 @@ static void flushEvents ( ClgState* clgs )
            regparms = 3;
            inew = i+1;
            break;
            regparms = 3;
            inew = i+1;
            break;

+         case Ev_Bc:
+            /* Conditional branch */
+            helperName = "log_cond_branch";
+            helperAddr = &log_cond_branch;
+            argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bc.taken );
+            regparms = 2;
+            inew = i+1;
+            break;
+         case Ev_Bi:
+            /* Branch to an unknown destination */
+            helperName = "log_ind_branch";
+            helperAddr = &log_ind_branch;
+            argv = mkIRExprVec_2( i_node_expr, ev->Ev.Bi.dst );
+            regparms = 2;
+            inew = i+1;
+            break;
+         case Ev_G:
+            /* Global bus event (CAS, LOCK-prefix, LL-SC, etc) */
+            helperName = "log_global_event";
+            helperAddr = &log_global_event;
+            argv = mkIRExprVec_1( i_node_expr );
+            regparms = 1;
+            inew = i+1;
+            break;

         default:
            tl_assert(0);
       }
         default:
            tl_assert(0);
       }


@@ -521,6 +661,62 @@ void addEvent_Dw ( ClgState* clgs, InstrInfo* inode, Int datasize, IRAtom* ea )
    clgs->events_used++;
 }
 
    clgs->events_used++;
 }
 

+static
+void addEvent_Bc ( ClgState* clgs, InstrInfo* inode, IRAtom* guard )
+{
+   Event* evt;
+   tl_assert(isIRAtom(guard));
+   tl_assert(typeOfIRExpr(clgs->sbOut->tyenv, guard)
+             == (sizeof(HWord)==4 ? Ity_I32 : Ity_I64));
+   if (!CLG_(clo).simulate_branch) return;
+
+   if (clgs->events_used == N_EVENTS)
+      flushEvents(clgs);
+   tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
+   evt = &clgs->events[clgs->events_used];
+   init_Event(evt);
+   evt->tag         = Ev_Bc;
+   evt->inode       = inode;
+   evt->Ev.Bc.taken = guard;
+   clgs->events_used++;
+}
+
+static
+void addEvent_Bi ( ClgState* clgs, InstrInfo* inode, IRAtom* whereTo )
+{
+   Event* evt;
+   tl_assert(isIRAtom(whereTo));
+   tl_assert(typeOfIRExpr(clgs->sbOut->tyenv, whereTo)
+             == (sizeof(HWord)==4 ? Ity_I32 : Ity_I64));
+   if (!CLG_(clo).simulate_branch) return;
+
+   if (clgs->events_used == N_EVENTS)
+      flushEvents(clgs);
+   tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
+   evt = &clgs->events[clgs->events_used];
+   init_Event(evt);
+   evt->tag       = Ev_Bi;
+   evt->inode     = inode;
+   evt->Ev.Bi.dst = whereTo;
+   clgs->events_used++;
+}
+
+static
+void addEvent_G ( ClgState* clgs, InstrInfo* inode )
+{
+   Event* evt;
+   if (!CLG_(clo).collect_bus) return;
+
+   if (clgs->events_used == N_EVENTS)
+      flushEvents(clgs);
+   tl_assert(clgs->events_used >= 0 && clgs->events_used < N_EVENTS);
+   evt = &clgs->events[clgs->events_used];
+   init_Event(evt);
+   evt->tag       = Ev_G;
+   evt->inode     = inode;
+   clgs->events_used++;
+}
+

 /* Initialise or check (if already seen before) an InstrInfo for next insn.
    We only can set instr_offset/instr_size here. The required event set and
    resulting cost offset depend on events (Ir/Dr/Dw/Dm) in guest
 /* Initialise or check (if already seen before) an InstrInfo for next insn.
    We only can set instr_offset/instr_size here. The required event set and
    resulting cost offset depend on events (Ir/Dr/Dw/Dm) in guest


@@ -711,6 +907,7 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure,
    Int      i, isize;
    IRStmt*  st;
    Addr     origAddr;
    Int      i, isize;
    IRStmt*  st;
    Addr     origAddr;

+   Addr64   cia; /* address of current insn */

    InstrInfo* curr_inode = NULL;
    ClgState clgs;
    UInt     cJumps = 0;
    InstrInfo* curr_inode = NULL;
    ClgState clgs;
    UInt     cJumps = 0;


@@ -747,6 +944,8 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure,
    CLG_ASSERT(Ist_IMark == st->tag);
 
    origAddr = (Addr)st->Ist.IMark.addr;
    CLG_ASSERT(Ist_IMark == st->tag);
 
    origAddr = (Addr)st->Ist.IMark.addr;

+   cia   = st->Ist.IMark.addr;
+   isize = st->Ist.IMark.len;

    CLG_ASSERT(origAddr == st->Ist.IMark.addr);  // XXX: check no overflow
 
    /* Get BB struct (creating if necessary).
    CLG_ASSERT(origAddr == st->Ist.IMark.addr);  // XXX: check no overflow
 
    /* Get BB struct (creating if necessary).


@@ -777,8 +976,9 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure,
            break;
 
         case Ist_IMark: {
            break;
 
         case Ist_IMark: {

-           CLG_ASSERT(clgs.instr_offset == (Addr)st->Ist.IMark.addr - origAddr);
-           isize = st->Ist.IMark.len;
+            cia   = st->Ist.IMark.addr;
+            isize = st->Ist.IMark.len;
+            CLG_ASSERT(clgs.instr_offset == (Addr)cia - origAddr);

            // If Vex fails to decode an instruction, the size will be zero.
            // Pretend otherwise.
            if (isize == 0) isize = VG_MIN_INSTR_SZB;
            // If Vex fails to decode an instruction, the size will be zero.
            // Pretend otherwise.
            if (isize == 0) isize = VG_MIN_INSTR_SZB;


@@ -856,6 +1056,7 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure,
                dataSize *= 2; /* since this is a doubleword-cas */
             addEvent_Dr( &clgs, curr_inode, dataSize, cas->addr );
             addEvent_Dw( &clgs, curr_inode, dataSize, cas->addr );
                dataSize *= 2; /* since this is a doubleword-cas */
             addEvent_Dr( &clgs, curr_inode, dataSize, cas->addr );
             addEvent_Dw( &clgs, curr_inode, dataSize, cas->addr );

+            addEvent_G(  &clgs, curr_inode );

             break;
          }
 
             break;
          }
 


@@ -871,12 +1072,74 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure,
                dataTy = typeOfIRExpr(sbIn->tyenv, st->Ist.LLSC.storedata);
                addEvent_Dw( &clgs, curr_inode,
                             sizeofIRType(dataTy), st->Ist.LLSC.addr );
                dataTy = typeOfIRExpr(sbIn->tyenv, st->Ist.LLSC.storedata);
                addEvent_Dw( &clgs, curr_inode,
                             sizeofIRType(dataTy), st->Ist.LLSC.addr );

+               /* I don't know whether the global-bus-lock cost should
+                  be attributed to the LL or the SC, but it doesn't
+                  really matter since they always have to be used in
+                  pairs anyway.  Hence put it (quite arbitrarily) on
+                  the SC. */
+               addEvent_G(  &clgs, curr_inode );

             }
             break;
          }
 
         case Ist_Exit: {
             }
             break;
          }
 
         case Ist_Exit: {

-           UInt jmps_passed;
+            Bool guest_exit, inverted;
+
+            /* VEX code generation sometimes inverts conditional branches.
+             * As Callgrind counts (conditional) jumps, it has to correct
+             * inversions. The heuristic is the following:
+             * (1) Callgrind switches off SB chasing and unrolling, and
+             *     therefore it assumes that a candidate for inversion only is
+             *     the last conditional branch in an SB.
+             * (2) inversion is assumed if the branch jumps to the address of
+             *     the next guest instruction in memory.
+             * This heuristic is precalculated in CLG_(collectBlockInfo)().
+             *
+             * Branching behavior is also used for branch prediction. Note that
+             * above heuristic is different from what Cachegrind does.
+             * Cachegrind uses (2) for all branches.
+             */
+            if (cJumps+1 == clgs.bb->cjmp_count)
+                inverted = clgs.bb->cjmp_inverted;
+            else
+                inverted = False;
+
+            // call branch predictor only if this is a branch in guest code
+            guest_exit = (st->Ist.Exit.jk == Ijk_Boring) ||
+                         (st->Ist.Exit.jk == Ijk_Call) ||
+                         (st->Ist.Exit.jk == Ijk_Ret);
+
+            if (guest_exit) {
+                /* Stuff to widen the guard expression to a host word, so
+                   we can pass it to the branch predictor simulation
+                   functions easily. */
+                IRType   tyW    = hWordTy;
+                IROp     widen  = tyW==Ity_I32  ? Iop_1Uto32  : Iop_1Uto64;
+                IROp     opXOR  = tyW==Ity_I32  ? Iop_Xor32   : Iop_Xor64;
+                IRTemp   guard1 = newIRTemp(clgs.sbOut->tyenv, Ity_I1);
+                IRTemp   guardW = newIRTemp(clgs.sbOut->tyenv, tyW);
+                IRTemp   guard  = newIRTemp(clgs.sbOut->tyenv, tyW);
+                IRExpr*  one    = tyW==Ity_I32 ? IRExpr_Const(IRConst_U32(1))
+                                               : IRExpr_Const(IRConst_U64(1));
+
+                /* Widen the guard expression. */
+                addStmtToIRSB( clgs.sbOut,
+                               IRStmt_WrTmp( guard1, st->Ist.Exit.guard ));
+                addStmtToIRSB( clgs.sbOut,
+                               IRStmt_WrTmp( guardW,
+                                             IRExpr_Unop(widen,
+                                                         IRExpr_RdTmp(guard1))) );
+                /* If the exit is inverted, invert the sense of the guard. */
+                addStmtToIRSB(
+                        clgs.sbOut,
+                        IRStmt_WrTmp(
+                                guard,
+                                inverted ? IRExpr_Binop(opXOR, IRExpr_RdTmp(guardW), one)
+                                    : IRExpr_RdTmp(guardW)
+                                    ));
+                /* And post the event. */
+                addEvent_Bc( &clgs, curr_inode, IRExpr_RdTmp(guard) );
+            }

 
            /* We may never reach the next statement, so need to flush
               all outstanding transactions now. */
 
            /* We may never reach the next statement, so need to flush
               all outstanding transactions now. */


@@ -891,12 +1154,9 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure,
            /* Update global variable jmps_passed before the jump
             * A correction is needed if VEX inverted the last jump condition
            */
            /* Update global variable jmps_passed before the jump
             * A correction is needed if VEX inverted the last jump condition
            */

-           jmps_passed = cJumps;
-           if ((cJumps+1 == clgs.bb->cjmp_count) && clgs.bb->cjmp_inverted)
-               jmps_passed++;

            addConstMemStoreStmt( clgs.sbOut,
                                  (UWord) &CLG_(current_state).jmps_passed,
            addConstMemStoreStmt( clgs.sbOut,
                                  (UWord) &CLG_(current_state).jmps_passed,

-                                 jmps_passed, hWordTy);
+                                  inverted ? cJumps+1 : cJumps, hWordTy);

            cJumps++;
 
            break;
            cJumps++;
 
            break;


@@ -917,6 +1177,26 @@ IRSB* CLG_(instrument)( VgCallbackClosure* closure,
       }
    }
 
       }
    }
 

+   /* Deal with branches to unknown destinations.  Except ignore ones
+      which are function returns as we assume the return stack
+      predictor never mispredicts. */
+   if ((sbIn->jumpkind == Ijk_Boring) || (sbIn->jumpkind == Ijk_Call)) {
+      if (0) { ppIRExpr( sbIn->next ); VG_(printf)("\n"); }
+      switch (sbIn->next->tag) {
+         case Iex_Const:
+            break; /* boring - branch to known address */
+         case Iex_RdTmp:
+            /* looks like an indirect branch (branch to unknown) */
+            addEvent_Bi( &clgs, curr_inode, sbIn->next );
+            break;
+         default:
+            /* shouldn't happen - if the incoming IR is properly
+               flattened, should only have tmp and const cases to
+               consider. */
+            tl_assert(0);
+      }
+   }
+

    /* At the end of the bb.  Flush outstandings. */
    flushEvents( &clgs );
 
    /* At the end of the bb.  Flush outstandings. */
    flushEvents( &clgs );
 


@@ -1161,7 +1441,7 @@ void CLG_(post_syscalltime)(ThreadId tid, UInt syscallno,
 {
   if (CLG_(clo).collect_systime &&
       CLG_(current_state).bbcc) {
 {
   if (CLG_(clo).collect_systime &&
       CLG_(current_state).bbcc) {

-    Int o = CLG_(sets).off_full_systime;
+      Int o;

 #if CLG_MICROSYSTIME
     struct vki_timeval tv_now;
     ULong diff;
 #if CLG_MICROSYSTIME
     struct vki_timeval tv_now;
     ULong diff;


@@ -1171,11 +1451,12 @@ void CLG_(post_syscalltime)(ThreadId tid, UInt syscallno,
 #else
     UInt diff = VG_(read_millisecond_timer)() - syscalltime[tid];
 #endif  
 #else
     UInt diff = VG_(read_millisecond_timer)() - syscalltime[tid];
 #endif  

-    
+
+    /* offset o is for "SysCount", o+1 for "SysTime" */
+    o = fullOffset(EG_SYS);
+    CLG_ASSERT(o>=0);

     CLG_DEBUG(0,"   Time (Off %d) for Syscall %d: %ull\n", o, syscallno, diff);
     
     CLG_DEBUG(0,"   Time (Off %d) for Syscall %d: %ull\n", o, syscallno, diff);
     

-    if (o<0) return;
-

     CLG_(current_state).cost[o] ++;
     CLG_(current_state).cost[o+1] += diff;
     if (!CLG_(current_state).bbcc->skipped)
     CLG_(current_state).cost[o] ++;
     CLG_(current_state).cost[o+1] += diff;
     if (!CLG_(current_state).bbcc->skipped)


@@ -1186,10 +1467,61 @@ void CLG_(post_syscalltime)(ThreadId tid, UInt syscallno,
   }
 }
 
   }
 }
 

+static UInt ULong_width(ULong n)
+{
+   UInt w = 0;
+   while (n > 0) {
+      n = n / 10;
+      w++;
+   }
+   if (w == 0) w = 1;
+   return w + (w-1)/3;   // add space for commas
+}
+
+static
+void branchsim_printstat(int l1, int l2, int l3)
+{
+    static Char buf1[128], buf2[128], buf3[128], fmt[128];
+    FullCost total;
+    ULong Bc_total_b, Bc_total_mp, Bi_total_b, Bi_total_mp;
+    ULong B_total_b, B_total_mp;
+
+    total = CLG_(total_cost);
+    Bc_total_b  = total[ fullOffset(EG_BC)   ];
+    Bc_total_mp = total[ fullOffset(EG_BC)+1 ];
+    Bi_total_b  = total[ fullOffset(EG_BI)   ];
+    Bi_total_mp = total[ fullOffset(EG_BI)+1 ];
+
+    /* Make format string, getting width right for numbers */
+    VG_(sprintf)(fmt, "%%s %%,%dllu  (%%,%dllu cond + %%,%dllu ind)\n",
+                 l1, l2, l3);
+
+    if (0 == Bc_total_b)  Bc_total_b = 1;
+    if (0 == Bi_total_b)  Bi_total_b = 1;
+    B_total_b  = Bc_total_b  + Bi_total_b;
+    B_total_mp = Bc_total_mp + Bi_total_mp;
+
+    VG_(umsg)("\n");
+    VG_(umsg)(fmt, "Branches:     ",
+              B_total_b, Bc_total_b, Bi_total_b);
+
+    VG_(umsg)(fmt, "Mispredicts:  ",
+              B_total_mp, Bc_total_mp, Bi_total_mp);
+
+    VG_(percentify)(B_total_mp,  B_total_b,  1, l1+1, buf1);
+    VG_(percentify)(Bc_total_mp, Bc_total_b, 1, l2+1, buf2);
+    VG_(percentify)(Bi_total_mp, Bi_total_b, 1, l3+1, buf3);
+
+    VG_(umsg)("Mispred rate:  %s (%s     + %s   )\n", buf1, buf2,buf3);
+}
+
+

 static
 void finish(void)
 {
 static
 void finish(void)
 {

-  char buf[RESULTS_BUF_LEN];
+  Char buf[RESULTS_BUF_LEN], fmt[128];
+  Int l1, l2, l3;
+  FullCost total;

 
   CLG_DEBUG(0, "finish()\n");
 
 
   CLG_DEBUG(0, "finish()\n");
 


@@ -1284,8 +1616,33 @@ void finish(void)
   VG_(message)(Vg_UserMsg, "Collected : %s\n", buf);
   VG_(message)(Vg_UserMsg, "\n");
 
   VG_(message)(Vg_UserMsg, "Collected : %s\n", buf);
   VG_(message)(Vg_UserMsg, "\n");
 

-  //  if (CLG_(clo).simulate_cache)
-  (*CLG_(cachesim).printstat)();
+  /* determine value widths for statistics */
+  total = CLG_(total_cost);
+  l1 = ULong_width( total[fullOffset(EG_IR)] );
+  l2 = l3 = 0;
+  if (CLG_(clo).simulate_cache) {
+      l2 = ULong_width( total[fullOffset(EG_DR)] );
+      l3 = ULong_width( total[fullOffset(EG_DW)] );
+  }
+  if (CLG_(clo).simulate_branch) {
+      int l2b = ULong_width( total[fullOffset(EG_BC)] );
+      int l3b = ULong_width( total[fullOffset(EG_BI)] );
+      if (l2b > l2) l2 = l2b;
+      if (l3b > l3) l3 = l3b;
+  }
+
+  /* Make format string, getting width right for numbers */
+  VG_(sprintf)(fmt, "%%s %%,%dllu\n", l1);
+
+  /* Always print this */
+  VG_(umsg)(fmt, "I   refs:     ", total[fullOffset(EG_IR)] );
+
+  if (CLG_(clo).simulate_cache)
+      (*CLG_(cachesim).printstat)(l1, l2, l3);
+
+  if (CLG_(clo).simulate_branch)
+      branchsim_printstat(l1, l2, l3);
+

 }
 
 
 }
 
 


@@ -1333,7 +1690,7 @@ void CLG_(post_clo_init)(void)
 
    (*CLG_(cachesim).post_clo_init)();
 
 
    (*CLG_(cachesim).post_clo_init)();
 

-   CLG_(init_eventsets)(0);
+   CLG_(init_eventsets)();

    CLG_(init_statistics)(& CLG_(stat));
    CLG_(init_cost_lz)( CLG_(sets).full, &CLG_(total_cost) );
 
    CLG_(init_statistics)(& CLG_(stat));
    CLG_(init_cost_lz)( CLG_(sets).full, &CLG_(total_cost) );
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/sim.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/sim.c
index e79d9e2ad66daeb488afe2dec95ed8b3a5867330..cb41d57d1e4d8d386d4180b9f4b12c902fb0c8f5 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/sim.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/sim.c
@@ -1,4 +1,3 @@
-

 /*--------------------------------------------------------------------*/
 /*--- Cache simulation.                                            ---*/
 /*---                                                        sim.c ---*/
 /*--------------------------------------------------------------------*/
 /*--- Cache simulation.                                            ---*/
 /*---                                                        sim.c ---*/


@@ -8,7 +7,7 @@
    This file is part of Callgrind, a Valgrind tool for call graph
    profiling programs.
 
    This file is part of Callgrind, a Valgrind tool for call graph
    profiling programs.
 

-   Copyright (C) 2003-2005, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)
+   Copyright (C) 2003-2010, Josef Weidendorfer (Josef.Weidendorfer@gmx.de)

 
    This tool is derived from and contains code from Cachegrind
    Copyright (C) 2002-2010 Nicholas Nethercote (njn@valgrind.org)
 
    This tool is derived from and contains code from Cachegrind
    Copyright (C) 2002-2010 Nicholas Nethercote (njn@valgrind.org)


@@ -105,25 +104,15 @@ static Bool clo_simulate_hwpref = False;
 static Bool clo_simulate_sectors = False;
 static Bool clo_collect_cacheuse = False;
 
 static Bool clo_simulate_sectors = False;
 static Bool clo_collect_cacheuse = False;
 

-/* Following global vars are setup before by
- *  setup_bbcc()/cachesim_after_bbsetup():
+/* Following global vars are setup before by setup_bbcc():

  *
  *

- * - Addr   bb_base     (instruction start address of original BB)
- * - ULong* cost_base   (start of cost array for BB)
- * - BBCC*  nonskipped  (only != 0 when in a function not skipped)
+ * - Addr   CLG_(bb_base)     (instruction start address of original BB)
+ * - ULong* CLG_(cost_base)   (start of cost array for BB)

  */
 
  */
 

-/* Offset to events in event set, used in log_* functions
- * <off_EventSet_BasicEventSet>: offset where basic set is found
- */
-static Int off_UIr_Ir;
-static Int off_UIrDr_Ir,   off_UIrDr_Dr;
-static Int off_UIrDrDw_Ir, off_UIrDrDw_Dr, off_UIrDrDw_Dw;
-static Int off_UIrDw_Ir,   off_UIrDw_Dw;
-static Int off_UIrDwDr_Ir, off_UIrDwDr_Dr, off_UIrDwDr_Dw;
-
-static Addr   bb_base;
-static ULong* cost_base;
+Addr   CLG_(bb_base);
+ULong* CLG_(cost_base);
+

 static InstrInfo* current_ii;
 
 /* Cache use offsets */
 static InstrInfo* current_ii;
 
 /* Cache use offsets */


@@ -855,7 +844,7 @@ static void update_L2_use(int idx, Addr memline)
   int i = ((32 - countBits(use->mask)) * L2.line_size)>>5;
   
   CLG_DEBUG(2, " L2.miss [%d]: at %#lx accessing memline %#lx\n",
   int i = ((32 - countBits(use->mask)) * L2.line_size)>>5;
   
   CLG_DEBUG(2, " L2.miss [%d]: at %#lx accessing memline %#lx\n",

-          idx, bb_base + current_ii->instr_offset, memline);
+           idx, CLG_(bb_base) + current_ii->instr_offset, memline);

   if (use->count>0) {
     CLG_DEBUG(2, "   old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",
             use->count, i, use->mask, loaded->memline, loaded->iaddr);
   if (use->count>0) {
     CLG_DEBUG(2, "   old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",
             use->count, i, use->mask, loaded->memline, loaded->iaddr);


@@ -872,10 +861,10 @@ static void update_L2_use(int idx, Addr memline)
    use->mask  = 0;
 
   loaded->memline = memline;
    use->mask  = 0;
 
   loaded->memline = memline;

-  loaded->iaddr   = bb_base + current_ii->instr_offset;
+  loaded->iaddr   = CLG_(bb_base) + current_ii->instr_offset;

   loaded->use_base = (CLG_(current_state).nonskipped) ?
     CLG_(current_state).nonskipped->skipped :
   loaded->use_base = (CLG_(current_state).nonskipped) ?
     CLG_(current_state).nonskipped->skipped :

-    cost_base + current_ii->cost_offset;
+    CLG_(cost_base) + current_ii->cost_offset;

 }
 
 static
 }
 
 static


@@ -943,14 +932,14 @@ static CacheModelResult update##_##L##_use(cache_t2* cache, int idx, \
   int c = ((32 - countBits(use->mask)) * cache->line_size)>>5;       \
                                                                      \
   CLG_DEBUG(2, " %s.miss [%d]: at %#lx accessing memline %#lx (mask %08x)\n", \
   int c = ((32 - countBits(use->mask)) * cache->line_size)>>5;       \
                                                                      \
   CLG_DEBUG(2, " %s.miss [%d]: at %#lx accessing memline %#lx (mask %08x)\n", \

-          cache->name, idx, bb_base + current_ii->instr_offset, memline, mask); \
+           cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \

   if (use->count>0) {                                                \
     CLG_DEBUG(2, "   old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",\
             use->count, c, use->mask, loaded->memline, loaded->iaddr); \
     CLG_DEBUG(2, "   collect: %d, use_base %p\n", \
             CLG_(current_state).collect, loaded->use_base);         \
                                                                      \
   if (use->count>0) {                                                \
     CLG_DEBUG(2, "   old: used %d, loss bits %d (%08x) [line %#lx from %#lx]\n",\
             use->count, c, use->mask, loaded->memline, loaded->iaddr); \
     CLG_DEBUG(2, "   collect: %d, use_base %p\n", \
             CLG_(current_state).collect, loaded->use_base);         \
                                                                      \

-    if (CLG_(current_state).collect && loaded->use_base) {            \
+    if (CLG_(current_state).collect && loaded->use_base) {           \

       (loaded->use_base)[off_##L##_AcCost] += 1000 / use->count;     \
       (loaded->use_base)[off_##L##_SpLoss] += c;                     \
                                                                      \
       (loaded->use_base)[off_##L##_AcCost] += 1000 / use->count;     \
       (loaded->use_base)[off_##L##_SpLoss] += c;                     \
                                                                      \


@@ -963,10 +952,10 @@ static CacheModelResult update##_##L##_use(cache_t2* cache, int idx, \
   use->count = 1;                                                    \
   use->mask  = mask;                                                 \
   loaded->memline = memline;                                         \
   use->count = 1;                                                    \
   use->mask  = mask;                                                 \
   loaded->memline = memline;                                         \

-  loaded->iaddr   = bb_base + current_ii->instr_offset;              \
-  loaded->use_base = (CLG_(current_state).nonskipped) ?               \
-    CLG_(current_state).nonskipped->skipped :                         \
-    cost_base + current_ii->cost_offset;                            \
+  loaded->iaddr   = CLG_(bb_base) + current_ii->instr_offset;        \
+  loaded->use_base = (CLG_(current_state).nonskipped) ?              \
+    CLG_(current_state).nonskipped->skipped :                        \
+    CLG_(cost_base) + current_ii->cost_offset;                       \

                                                                      \
   if (memline == 0) return L2_Hit;                                   \
   return cacheuse_L2_access(memline, loaded);                        \
                                                                      \
   if (memline == 0) return L2_Hit;                                   \
   return cacheuse_L2_access(memline, loaded);                        \


@@ -987,9 +976,9 @@ void cacheuse_finish(void)
 
   if (!CLG_(current_state).collect) return;
 
 
   if (!CLG_(current_state).collect) return;
 

-  bb_base = 0;
+  CLG_(bb_base) = 0;

   current_ii = &ii;
   current_ii = &ii;

-  cost_base = 0;
+  CLG_(cost_base) = 0;

 
   /* update usage counters */
   if (I1.use)
 
   /* update usage counters */
   if (I1.use)


@@ -1062,21 +1051,21 @@ static void log_1I0D(InstrInfo* ii)
     CacheModelResult IrRes;
 
     current_ii = ii;
     CacheModelResult IrRes;
 
     current_ii = ii;

-    IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size);
+    IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);

 
     CLG_DEBUG(6, "log_1I0D:  Ir  %#lx/%u => %s\n",
 
     CLG_DEBUG(6, "log_1I0D:  Ir  %#lx/%u => %s\n",

-             bb_base + ii->instr_offset, ii->instr_size, cacheRes(IrRes));
+              CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes));

 
     if (CLG_(current_state).collect) {
        ULong* cost_Ir;
 
        if (CLG_(current_state).nonskipped)
 
     if (CLG_(current_state).collect) {
        ULong* cost_Ir;
 
        if (CLG_(current_state).nonskipped)

-           cost_Ir = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Ir;
+           cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);

        else
        else

-           cost_Ir = cost_base + ii->cost_offset + off_UIr_Ir;
+            cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR];

 
        inc_costs(IrRes, cost_Ir, 
 
        inc_costs(IrRes, cost_Ir, 

-                 CLG_(current_state).cost + CLG_(sets).off_full_Ir );
+                 CLG_(current_state).cost + fullOffset(EG_IR) );

     }
 }
 
     }
 }
 


@@ -1087,27 +1076,30 @@ static void log_2I0D(InstrInfo* ii1, InstrInfo* ii2)
     ULong *global_cost_Ir;
 
     current_ii = ii1;
     ULong *global_cost_Ir;
 
     current_ii = ii1;

-    Ir1Res = (*simulator.I1_Read)(bb_base + ii1->instr_offset, ii1->instr_size);
+    Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);

     current_ii = ii2;
     current_ii = ii2;

-    Ir2Res = (*simulator.I1_Read)(bb_base + ii2->instr_offset, ii2->instr_size);
+    Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);

 
     CLG_DEBUG(6, "log_2I0D:  Ir1 %#lx/%u => %s, Ir2 %#lx/%u => %s\n",
 
     CLG_DEBUG(6, "log_2I0D:  Ir1 %#lx/%u => %s, Ir2 %#lx/%u => %s\n",

-             bb_base + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),
-             bb_base + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) );
+              CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),
+              CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res) );

 
     if (!CLG_(current_state).collect) return;
 
 
     if (!CLG_(current_state).collect) return;
 

-    global_cost_Ir = CLG_(current_state).cost + CLG_(sets).off_full_Ir;
+    global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR);

     if (CLG_(current_state).nonskipped) {
     if (CLG_(current_state).nonskipped) {

-       ULong* skipped_cost_Ir = CLG_(current_state).nonskipped->skipped +
-                                CLG_(sets).off_full_Ir;
+       ULong* skipped_cost_Ir =
+           CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);
+

        inc_costs(Ir1Res, global_cost_Ir, skipped_cost_Ir);
        inc_costs(Ir2Res, global_cost_Ir, skipped_cost_Ir);
        return;
     }
 
        inc_costs(Ir1Res, global_cost_Ir, skipped_cost_Ir);
        inc_costs(Ir2Res, global_cost_Ir, skipped_cost_Ir);
        return;
     }
 

-    inc_costs(Ir1Res, global_cost_Ir, cost_base + ii1->cost_offset + off_UIr_Ir);
-    inc_costs(Ir2Res, global_cost_Ir, cost_base + ii2->cost_offset + off_UIr_Ir);
+    inc_costs(Ir1Res, global_cost_Ir,
+              CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]);
+    inc_costs(Ir2Res, global_cost_Ir,
+              CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]);

 }
 
 VG_REGPARM(3)
 }
 
 VG_REGPARM(3)


@@ -1117,32 +1109,35 @@ static void log_3I0D(InstrInfo* ii1, InstrInfo* ii2, InstrInfo* ii3)
     ULong *global_cost_Ir;
 
     current_ii = ii1;
     ULong *global_cost_Ir;
 
     current_ii = ii1;

-    Ir1Res = (*simulator.I1_Read)(bb_base + ii1->instr_offset, ii1->instr_size);
+    Ir1Res = (*simulator.I1_Read)(CLG_(bb_base) + ii1->instr_offset, ii1->instr_size);

     current_ii = ii2;
     current_ii = ii2;

-    Ir2Res = (*simulator.I1_Read)(bb_base + ii2->instr_offset, ii2->instr_size);
+    Ir2Res = (*simulator.I1_Read)(CLG_(bb_base) + ii2->instr_offset, ii2->instr_size);

     current_ii = ii3;
     current_ii = ii3;

-    Ir3Res = (*simulator.I1_Read)(bb_base + ii3->instr_offset, ii3->instr_size);
+    Ir3Res = (*simulator.I1_Read)(CLG_(bb_base) + ii3->instr_offset, ii3->instr_size);

 
     CLG_DEBUG(6, "log_3I0D:  Ir1 %#lx/%u => %s, Ir2 %#lx/%u => %s, Ir3 %#lx/%u => %s\n",
 
     CLG_DEBUG(6, "log_3I0D:  Ir1 %#lx/%u => %s, Ir2 %#lx/%u => %s, Ir3 %#lx/%u => %s\n",

-             bb_base + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),
-             bb_base + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res),
-             bb_base + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) );
+              CLG_(bb_base) + ii1->instr_offset, ii1->instr_size, cacheRes(Ir1Res),
+              CLG_(bb_base) + ii2->instr_offset, ii2->instr_size, cacheRes(Ir2Res),
+              CLG_(bb_base) + ii3->instr_offset, ii3->instr_size, cacheRes(Ir3Res) );

 
     if (!CLG_(current_state).collect) return;
 
 
     if (!CLG_(current_state).collect) return;
 

-    global_cost_Ir = CLG_(current_state).cost + CLG_(sets).off_full_Ir;
+    global_cost_Ir = CLG_(current_state).cost + fullOffset(EG_IR);

     if (CLG_(current_state).nonskipped) {
     if (CLG_(current_state).nonskipped) {

-       ULong* skipped_cost_Ir = CLG_(current_state).nonskipped->skipped +
-                                CLG_(sets).off_full_Ir;
+       ULong* skipped_cost_Ir =
+           CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);

        inc_costs(Ir1Res, global_cost_Ir, skipped_cost_Ir);
        inc_costs(Ir2Res, global_cost_Ir, skipped_cost_Ir);
        inc_costs(Ir3Res, global_cost_Ir, skipped_cost_Ir);
        return;
     }
 
        inc_costs(Ir1Res, global_cost_Ir, skipped_cost_Ir);
        inc_costs(Ir2Res, global_cost_Ir, skipped_cost_Ir);
        inc_costs(Ir3Res, global_cost_Ir, skipped_cost_Ir);
        return;
     }
 

-    inc_costs(Ir1Res, global_cost_Ir, cost_base + ii1->cost_offset + off_UIr_Ir);
-    inc_costs(Ir2Res, global_cost_Ir, cost_base + ii2->cost_offset + off_UIr_Ir);
-    inc_costs(Ir3Res, global_cost_Ir, cost_base + ii3->cost_offset + off_UIr_Ir);
+    inc_costs(Ir1Res, global_cost_Ir,
+              CLG_(cost_base) + ii1->cost_offset + ii1->eventset->offset[EG_IR]);
+    inc_costs(Ir2Res, global_cost_Ir,
+              CLG_(cost_base) + ii2->cost_offset + ii2->eventset->offset[EG_IR]);
+    inc_costs(Ir3Res, global_cost_Ir,
+              CLG_(cost_base) + ii3->cost_offset + ii3->eventset->offset[EG_IR]);

 }
 
 /* Instruction doing a read access */
 }
 
 /* Instruction doing a read access */


@@ -1153,32 +1148,29 @@ static void log_1I1Dr(InstrInfo* ii, Addr data_addr, Word data_size)
     CacheModelResult IrRes, DrRes;
 
     current_ii = ii;
     CacheModelResult IrRes, DrRes;
 
     current_ii = ii;

-    IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size);
+    IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);

     DrRes = (*simulator.D1_Read)(data_addr, data_size);
 
     CLG_DEBUG(6, "log_1I1Dr: Ir  %#lx/%u => %s, Dr  %#lx/%lu => %s\n",
     DrRes = (*simulator.D1_Read)(data_addr, data_size);
 
     CLG_DEBUG(6, "log_1I1Dr: Ir  %#lx/%u => %s, Dr  %#lx/%lu => %s\n",

-             bb_base + ii->instr_offset, ii->instr_size, cacheRes(IrRes),
+              CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes),

              data_addr, data_size, cacheRes(DrRes));
 
     if (CLG_(current_state).collect) {
        ULong *cost_Ir, *cost_Dr;
        
        if (CLG_(current_state).nonskipped) {
              data_addr, data_size, cacheRes(DrRes));
 
     if (CLG_(current_state).collect) {
        ULong *cost_Ir, *cost_Dr;
        
        if (CLG_(current_state).nonskipped) {

-           cost_Ir = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Ir;
-           cost_Dr = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Dr;
+           cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);
+           cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR);

        }
        else {
        }
        else {

-           // event set must be UIrDr or extension
-           CLG_ASSERT((ii->eventset == CLG_(sets).UIrDr) ||
-                      (ii->eventset == CLG_(sets).UIrDrDw));
-           cost_Ir = cost_base + ii->cost_offset + off_UIrDr_Ir;
-           cost_Dr = cost_base + ii->cost_offset + off_UIrDr_Dr;
+            cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR];
+            cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR];

        }
        
        inc_costs(IrRes, cost_Ir, 
        }
        
        inc_costs(IrRes, cost_Ir, 

-                 CLG_(current_state).cost + CLG_(sets).off_full_Ir );
+                 CLG_(current_state).cost + fullOffset(EG_IR) );

        inc_costs(DrRes, cost_Dr,
        inc_costs(DrRes, cost_Dr,

-                 CLG_(current_state).cost + CLG_(sets).off_full_Dr );
+                 CLG_(current_state).cost + fullOffset(EG_DR) );

     }
 }
 
     }
 }
 


@@ -1197,21 +1189,13 @@ static void log_0I1Dr(InstrInfo* ii, Addr data_addr, Word data_size)
     if (CLG_(current_state).collect) {
        ULong *cost_Dr;
        
     if (CLG_(current_state).collect) {
        ULong *cost_Dr;
        

-       if (CLG_(current_state).nonskipped) {
-           cost_Dr = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Dr;
-       }
-       else {
-           Int off_Dr;
-           if      (ii->eventset == CLG_(sets).UIrDr)   off_Dr = off_UIrDr_Dr;
-           else if (ii->eventset == CLG_(sets).UIrDrDw) off_Dr = off_UIrDrDw_Dr;
-           else if (ii->eventset == CLG_(sets).UIrDwDr) off_Dr = off_UIrDwDr_Dr;
-           else CLG_ASSERT(0);
-
-           cost_Dr = cost_base + ii->cost_offset + off_Dr;
-       }
+       if (CLG_(current_state).nonskipped)
+           cost_Dr = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DR);
+       else
+            cost_Dr = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DR];

 
        inc_costs(DrRes, cost_Dr,
 
        inc_costs(DrRes, cost_Dr,

-                 CLG_(current_state).cost + CLG_(sets).off_full_Dr );
+                 CLG_(current_state).cost + fullOffset(EG_DR) );

     }
 }
 
     }
 }
 


@@ -1224,33 +1208,29 @@ static void log_1I1Dw(InstrInfo* ii, Addr data_addr, Word data_size)
     CacheModelResult IrRes, DwRes;
 
     current_ii = ii;
     CacheModelResult IrRes, DwRes;
 
     current_ii = ii;

-    IrRes = (*simulator.I1_Read)(bb_base + ii->instr_offset, ii->instr_size);
+    IrRes = (*simulator.I1_Read)(CLG_(bb_base) + ii->instr_offset, ii->instr_size);

     DwRes = (*simulator.D1_Write)(data_addr, data_size);
 
     CLG_DEBUG(6, "log_1I1Dw: Ir  %#lx/%u => %s, Dw  %#lx/%lu => %s\n",
     DwRes = (*simulator.D1_Write)(data_addr, data_size);
 
     CLG_DEBUG(6, "log_1I1Dw: Ir  %#lx/%u => %s, Dw  %#lx/%lu => %s\n",

-             bb_base + ii->instr_offset, ii->instr_size, cacheRes(IrRes),
+              CLG_(bb_base) + ii->instr_offset, ii->instr_size, cacheRes(IrRes),

              data_addr, data_size, cacheRes(DwRes));
 
     if (CLG_(current_state).collect) {
        ULong *cost_Ir, *cost_Dw;
        
        if (CLG_(current_state).nonskipped) {
              data_addr, data_size, cacheRes(DwRes));
 
     if (CLG_(current_state).collect) {
        ULong *cost_Ir, *cost_Dw;
        
        if (CLG_(current_state).nonskipped) {

-           cost_Ir = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Ir;
-           cost_Dw = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Dw;
+           cost_Ir = CLG_(current_state).nonskipped->skipped + fullOffset(EG_IR);
+           cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW);

        }
        else {
        }
        else {

-           // This helper is called when a Dr event follows Ir;
-           // Event set must be UIrDw or extension
-           CLG_ASSERT((ii->eventset == CLG_(sets).UIrDw) ||
-                      (ii->eventset == CLG_(sets).UIrDwDr));
-           cost_Ir = cost_base + ii->cost_offset + off_UIrDw_Ir;
-           cost_Dw = cost_base + ii->cost_offset + off_UIrDw_Dw;
+            cost_Ir = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_IR];
+            cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW];

        }
        
        inc_costs(IrRes, cost_Ir,
        }
        
        inc_costs(IrRes, cost_Ir,

-                 CLG_(current_state).cost + CLG_(sets).off_full_Ir );
+                 CLG_(current_state).cost + fullOffset(EG_IR) );

        inc_costs(DwRes, cost_Dw,
        inc_costs(DwRes, cost_Dw,

-                 CLG_(current_state).cost + CLG_(sets).off_full_Dw );
+                 CLG_(current_state).cost + fullOffset(EG_DW) );

     }
 }
 
     }
 }
 


@@ -1268,21 +1248,13 @@ static void log_0I1Dw(InstrInfo* ii, Addr data_addr, Word data_size)
     if (CLG_(current_state).collect) {
        ULong *cost_Dw;
        
     if (CLG_(current_state).collect) {
        ULong *cost_Dw;
        

-       if (CLG_(current_state).nonskipped) {
-           cost_Dw = CLG_(current_state).nonskipped->skipped + CLG_(sets).off_full_Dw;
-       }
-       else {
-           Int off_Dw;
-           if      (ii->eventset == CLG_(sets).UIrDw)   off_Dw = off_UIrDw_Dw;
-           else if (ii->eventset == CLG_(sets).UIrDwDr) off_Dw = off_UIrDwDr_Dw;
-           else if (ii->eventset == CLG_(sets).UIrDrDw) off_Dw = off_UIrDrDw_Dw;
-           else CLG_ASSERT(0);
-
-           cost_Dw = cost_base + ii->cost_offset + off_Dw;
-       }
+       if (CLG_(current_state).nonskipped)
+           cost_Dw = CLG_(current_state).nonskipped->skipped + fullOffset(EG_DW);
+       else
+            cost_Dw = CLG_(cost_base) + ii->cost_offset + ii->eventset->offset[EG_DW];

        
        inc_costs(DwRes, cost_Dw,
        
        inc_costs(DwRes, cost_Dw,

-                 CLG_(current_state).cost + CLG_(sets).off_full_Dw );
+                 CLG_(current_state).cost + fullOffset(EG_DW) );

     }
 }
 
     }
 }
 


@@ -1299,49 +1271,40 @@ static cache_t clo_D1_cache = UNDEFINED_CACHE;
 static cache_t clo_L2_cache = UNDEFINED_CACHE;
 
 
 static cache_t clo_L2_cache = UNDEFINED_CACHE;
 
 

-/* Checks cache config is ok;  makes it so if not. */
-static
-void check_cache(cache_t* cache, Char *name)
+// Checks cache config is ok.  Returns NULL if ok, or a pointer to an error
+// string otherwise.
+static Char* check_cache(cache_t* cache)

 {
 {

-   /* Simulator requires line size and set count to be powers of two */
+   // Simulator requires line size and set count to be powers of two.

    if (( cache->size % (cache->line_size * cache->assoc) != 0) ||
    if (( cache->size % (cache->line_size * cache->assoc) != 0) ||

-       (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc))) {
-      VG_(message)(Vg_UserMsg,
-         "error: %s set count not a power of two; aborting.\n",
-         name);
+       (-1 == VG_(log2)(cache->size/cache->line_size/cache->assoc)))
+   {
+      return "Cache set count is not a power of two.\n";

    }
 
    }
 

+   // Simulator requires line size to be a power of two.

    if (-1 == VG_(log2)(cache->line_size)) {
    if (-1 == VG_(log2)(cache->line_size)) {

-      VG_(message)(Vg_UserMsg,
-         "error: %s line size of %dB not a power of two; aborting.\n",
-         name, cache->line_size);
-      VG_(exit)(1);
+      return "Cache line size is not a power of two.\n";

    }
 
    // Then check line size >= 16 -- any smaller and a single instruction could
    // straddle three cache lines, which breaks a simulation assertion and is
    // stupid anyway.
    if (cache->line_size < MIN_LINE_SIZE) {
    }
 
    // Then check line size >= 16 -- any smaller and a single instruction could
    // straddle three cache lines, which breaks a simulation assertion and is
    // stupid anyway.
    if (cache->line_size < MIN_LINE_SIZE) {

-      VG_(message)(Vg_UserMsg,
-         "error: %s line size of %dB too small; aborting.\n",
-         name, cache->line_size);
-      VG_(exit)(1);
+      return "Cache line size is too small.\n";

    }
 
    /* Then check cache size > line size (causes seg faults if not). */
    if (cache->size <= cache->line_size) {
    }
 
    /* Then check cache size > line size (causes seg faults if not). */
    if (cache->size <= cache->line_size) {

-      VG_(message)(Vg_UserMsg,
-         "error: %s cache size of %dB <= line size of %dB; aborting.\n",
-         name, cache->size, cache->line_size);
-      VG_(exit)(1);
+      return "Cache size <= line size.\n";

    }
 
    /* Then check assoc <= (size / line size) (seg faults otherwise). */
    if (cache->assoc > (cache->size / cache->line_size)) {
    }
 
    /* Then check assoc <= (size / line size) (seg faults otherwise). */
    if (cache->assoc > (cache->size / cache->line_size)) {

-      VG_(message)(Vg_UserMsg,
-         "warning: %s associativity > (size / line size); aborting.\n", name);
-      VG_(exit)(1);
+      return "Cache associativity > (size / line size).\n";

    }
    }

+
+   return NULL;

 }
 
 static
 }
 
 static


@@ -1349,27 +1312,27 @@ void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* L2c)
 {
 #define DEFINED(L)   (-1 != L.size  || -1 != L.assoc || -1 != L.line_size)
 
 {
 #define DEFINED(L)   (-1 != L.size  || -1 != L.assoc || -1 != L.line_size)
 

-   Int n_clos = 0;
+   Char* checkRes;

 
 

-   // Count how many were defined on the command line.
-   if (DEFINED(clo_I1_cache)) { n_clos++; }
-   if (DEFINED(clo_D1_cache)) { n_clos++; }
-   if (DEFINED(clo_L2_cache)) { n_clos++; }
+   Bool all_caches_clo_defined =
+      (DEFINED(clo_I1_cache) &&
+       DEFINED(clo_D1_cache) &&
+       DEFINED(clo_L2_cache));

 
    // Set the cache config (using auto-detection, if supported by the
 
    // Set the cache config (using auto-detection, if supported by the

-   // architecture)
-   VG_(configure_caches)( I1c, D1c, L2c, (3 == n_clos) );
+   // architecture).
+   VG_(configure_caches)( I1c, D1c, L2c, all_caches_clo_defined );
+
+   // Check the default/auto-detected values.
+   checkRes = check_cache(I1c);  tl_assert(!checkRes);
+   checkRes = check_cache(D1c);  tl_assert(!checkRes);
+   checkRes = check_cache(L2c);  tl_assert(!checkRes);

 
    // Then replace with any defined on the command line.
    if (DEFINED(clo_I1_cache)) { *I1c = clo_I1_cache; }
    if (DEFINED(clo_D1_cache)) { *D1c = clo_D1_cache; }
    if (DEFINED(clo_L2_cache)) { *L2c = clo_L2_cache; }
 
 
    // Then replace with any defined on the command line.
    if (DEFINED(clo_I1_cache)) { *I1c = clo_I1_cache; }
    if (DEFINED(clo_D1_cache)) { *D1c = clo_D1_cache; }
    if (DEFINED(clo_L2_cache)) { *L2c = clo_L2_cache; }
 

-   // Then check values and fix if not acceptable.
-   check_cache(I1c, "I1");
-   check_cache(D1c, "D1");
-   check_cache(L2c, "L2");
-

    if (VG_(clo_verbosity) > 1) {
       VG_(message)(Vg_UserMsg, "Cache configuration used:\n");
       VG_(message)(Vg_UserMsg, "  I1: %dB, %d-way, %dB lines\n",
    if (VG_(clo_verbosity) > 1) {
       VG_(message)(Vg_UserMsg, "Cache configuration used:\n");
       VG_(message)(Vg_UserMsg, "  I1: %dB, %d-way, %dB lines\n",


@@ -1518,8 +1481,7 @@ static
 void cachesim_print_opts(void)
 {
   VG_(printf)(
 void cachesim_print_opts(void)
 {
   VG_(printf)(

-"\n   cache simulator options:\n"
-"    --simulate-cache=no|yes   Do cache simulation [no]\n"
+"\n   cache simulator options (does cache simulation if used):\n"

 "    --simulate-wb=no|yes      Count write-back events [no]\n"
 "    --simulate-hwpref=no|yes  Simulate hardware prefetch [no]\n"
 #if CLG_EXPERIMENTAL
 "    --simulate-wb=no|yes      Count write-back events [no]\n"
 "    --simulate-hwpref=no|yes  Simulate hardware prefetch [no]\n"
 #if CLG_EXPERIMENTAL


@@ -1532,13 +1494,14 @@ void cachesim_print_opts(void)
              );
 }
 
              );
 }
 

-static void parse_opt ( cache_t* cache, char* opt )
+static void parse_opt ( cache_t* cache, char* opt, Char* optval )

 {
    Long i1, i2, i3;
    Char* endptr;
 {
    Long i1, i2, i3;
    Char* endptr;

+   Char* checkRes;

 
    // Option argument looks like "65536,2,64".  Extract them.
 
    // Option argument looks like "65536,2,64".  Extract them.

-   i1 = VG_(strtoll10)(opt,      &endptr); if (*endptr != ',')  goto bad;
+   i1 = VG_(strtoll10)(optval,   &endptr); if (*endptr != ',')  goto bad;

    i2 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != ',')  goto bad;
    i3 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != '\0') goto bad;
 
    i2 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != ',')  goto bad;
    i3 = VG_(strtoll10)(endptr+1, &endptr); if (*endptr != '\0') goto bad;
 


@@ -1550,15 +1513,20 @@ static void parse_opt ( cache_t* cache, char* opt )
    if (cache->assoc     != i2) goto overflow;
    if (cache->line_size != i3) goto overflow;
 
    if (cache->assoc     != i2) goto overflow;
    if (cache->line_size != i3) goto overflow;
 

+   checkRes = check_cache(cache);
+   if (checkRes) {
+      VG_(fmsg)("%s", checkRes);
+      goto bad;
+   }
+

    return;
 
    return;
 

-  overflow:
-   VG_(message)(Vg_UserMsg,
-                "one of the cache parameters was too large and overflowed\n");

   bad:
   bad:

-   // XXX: this omits the "--I1/D1/L2=" part from the message, but that's
-   // not a big deal.
-   VG_(err_bad_option)(opt);
+   VG_(fmsg_bad_option)(opt, "");
+
+  overflow:
+   VG_(fmsg_bad_option)(opt,
+      "One of the cache parameters was too large and overflowed.\n");

 }
 
 /* Check for command line option for cache configuration.
 }
 
 /* Check for command line option for cache configuration.


@@ -1582,11 +1550,11 @@ static Bool cachesim_parse_opt(Char* arg)
    }
 
    else if VG_STR_CLO(arg, "--I1", tmp_str)
    }
 
    else if VG_STR_CLO(arg, "--I1", tmp_str)

-      parse_opt(&clo_I1_cache, tmp_str);
+      parse_opt(&clo_I1_cache, arg, tmp_str);

    else if VG_STR_CLO(arg, "--D1", tmp_str)
    else if VG_STR_CLO(arg, "--D1", tmp_str)

-      parse_opt(&clo_D1_cache, tmp_str);
+      parse_opt(&clo_D1_cache, arg, tmp_str);

    else if VG_STR_CLO(arg, "--L2", tmp_str)
    else if VG_STR_CLO(arg, "--L2", tmp_str)

-      parse_opt(&clo_L2_cache, tmp_str);
+      parse_opt(&clo_L2_cache, arg, tmp_str);

   else
     return False;
 
   else
     return False;
 


@@ -1642,7 +1610,7 @@ void percentify(Int n, Int ex, Int field_width, char buf[])
 }
 
 static
 }
 
 static

-void cachesim_printstat(void)
+void cachesim_printstat(Int l1, Int l2, Int l3)

 {
   FullCost total = CLG_(total_cost), D_total = 0;
   ULong L2_total_m, L2_total_mr, L2_total_mw,
 {
   FullCost total = CLG_(total_cost), D_total = 0;
   ULong L2_total_m, L2_total_mr, L2_total_mw,


@@ -1650,7 +1618,6 @@ void cachesim_printstat(void)
   char buf1[RESULTS_BUF_LEN], 
     buf2[RESULTS_BUF_LEN], 
     buf3[RESULTS_BUF_LEN];
   char buf1[RESULTS_BUF_LEN], 
     buf2[RESULTS_BUF_LEN], 
     buf3[RESULTS_BUF_LEN];

-  Int l1, l2, l3;

   Int p;
 
   if ((VG_(clo_verbosity) >1) && clo_simulate_hwpref) {
   Int p;
 
   if ((VG_(clo_verbosity) >1) && clo_simulate_hwpref) {


@@ -1661,30 +1628,23 @@ void cachesim_printstat(void)
     VG_(message)(Vg_DebugMsg, "\n");
   }
 
     VG_(message)(Vg_DebugMsg, "\n");
   }
 

-  /* I cache results.  Use the I_refs value to determine the first column
-   * width. */
-  l1 = commify(total[CLG_(sets).off_full_Ir], 0, buf1);
-  VG_(message)(Vg_UserMsg, "I   refs:      %s\n", buf1);
-
-  if (!CLG_(clo).simulate_cache) return;
-
-  commify(total[CLG_(sets).off_full_Ir +1], l1, buf1);
+  commify(total[fullOffset(EG_IR) +1], l1, buf1);

   VG_(message)(Vg_UserMsg, "I1  misses:    %s\n", buf1);
 
   VG_(message)(Vg_UserMsg, "I1  misses:    %s\n", buf1);
 

-  commify(total[CLG_(sets).off_full_Ir +2], l1, buf1);
+  commify(total[fullOffset(EG_IR) +2], l1, buf1);

   VG_(message)(Vg_UserMsg, "L2i misses:    %s\n", buf1);
 
   p = 100;
 
   VG_(message)(Vg_UserMsg, "L2i misses:    %s\n", buf1);
 
   p = 100;
 

-  if (0 == total[CLG_(sets).off_full_Ir]) 
-    total[CLG_(sets).off_full_Ir] = 1;
+  if (0 == total[fullOffset(EG_IR)])
+    total[fullOffset(EG_IR)] = 1;

 
 

-  percentify(total[CLG_(sets).off_full_Ir+1] * 100 * p /
-            total[CLG_(sets).off_full_Ir], p, l1+1, buf1);
+  percentify(total[fullOffset(EG_IR)+1] * 100 * p /
+            total[fullOffset(EG_IR)], p, l1+1, buf1);

   VG_(message)(Vg_UserMsg, "I1  miss rate: %s\n", buf1);
        
   VG_(message)(Vg_UserMsg, "I1  miss rate: %s\n", buf1);
        

-  percentify(total[CLG_(sets).off_full_Ir+2] * 100 * p /
-            total[CLG_(sets).off_full_Ir], p, l1+1, buf1);
+  percentify(total[fullOffset(EG_IR)+2] * 100 * p /
+            total[fullOffset(EG_IR)], p, l1+1, buf1);

   VG_(message)(Vg_UserMsg, "L2i miss rate: %s\n", buf1);
   VG_(message)(Vg_UserMsg, "\n");
    
   VG_(message)(Vg_UserMsg, "L2i miss rate: %s\n", buf1);
   VG_(message)(Vg_UserMsg, "\n");
    


@@ -1694,46 +1654,47 @@ void cachesim_printstat(void)
 
   D_total = CLG_(get_eventset_cost)( CLG_(sets).full );
   CLG_(init_cost)( CLG_(sets).full, D_total);
 
   D_total = CLG_(get_eventset_cost)( CLG_(sets).full );
   CLG_(init_cost)( CLG_(sets).full, D_total);

-  CLG_(copy_cost)( CLG_(sets).Dr, D_total, total + CLG_(sets).off_full_Dr );
-  CLG_(add_cost) ( CLG_(sets).Dw, D_total, total + CLG_(sets).off_full_Dw );
+  // we only use the first 3 values of D_total, adding up Dr and Dw costs
+  CLG_(copy_cost)( CLG_(get_event_set)(EG_DR), D_total, total + fullOffset(EG_DR) );
+  CLG_(add_cost) ( CLG_(get_event_set)(EG_DW), D_total, total + fullOffset(EG_DW) );

 
   commify( D_total[0], l1, buf1);
 
   commify( D_total[0], l1, buf1);

-  l2 = commify(total[CLG_(sets).off_full_Dr], 0,  buf2);
-  l3 = commify(total[CLG_(sets).off_full_Dw], 0,  buf3);
+  commify(total[fullOffset(EG_DR)], l2,  buf2);
+  commify(total[fullOffset(EG_DW)], l3,  buf3);

   VG_(message)(Vg_UserMsg, "D   refs:      %s  (%s rd + %s wr)\n",
               buf1,  buf2,  buf3);
 
   commify( D_total[1], l1, buf1);
   VG_(message)(Vg_UserMsg, "D   refs:      %s  (%s rd + %s wr)\n",
               buf1,  buf2,  buf3);
 
   commify( D_total[1], l1, buf1);

-  commify(total[CLG_(sets).off_full_Dr+1], l2, buf2);
-  commify(total[CLG_(sets).off_full_Dw+1], l3, buf3);
+  commify(total[fullOffset(EG_DR)+1], l2, buf2);
+  commify(total[fullOffset(EG_DW)+1], l3, buf3);

   VG_(message)(Vg_UserMsg, "D1  misses:    %s  (%s rd + %s wr)\n",
               buf1, buf2, buf3);
 
   commify( D_total[2], l1, buf1);
   VG_(message)(Vg_UserMsg, "D1  misses:    %s  (%s rd + %s wr)\n",
               buf1, buf2, buf3);
 
   commify( D_total[2], l1, buf1);

-  commify(total[CLG_(sets).off_full_Dr+2], l2, buf2);
-  commify(total[CLG_(sets).off_full_Dw+2], l3, buf3);
+  commify(total[fullOffset(EG_DR)+2], l2, buf2);
+  commify(total[fullOffset(EG_DW)+2], l3, buf3);

   VG_(message)(Vg_UserMsg, "L2d misses:    %s  (%s rd + %s wr)\n",
               buf1, buf2, buf3);
 
   p = 10;
   
   if (0 == D_total[0])   D_total[0] = 1;
   VG_(message)(Vg_UserMsg, "L2d misses:    %s  (%s rd + %s wr)\n",
               buf1, buf2, buf3);
 
   p = 10;
   
   if (0 == D_total[0])   D_total[0] = 1;

-  if (0 == total[CLG_(sets).off_full_Dr]) total[CLG_(sets).off_full_Dr] = 1;
-  if (0 == total[CLG_(sets).off_full_Dw]) total[CLG_(sets).off_full_Dw] = 1;
+  if (0 == total[fullOffset(EG_DR)]) total[fullOffset(EG_DR)] = 1;
+  if (0 == total[fullOffset(EG_DW)]) total[fullOffset(EG_DW)] = 1;

   
   percentify( D_total[1] * 100 * p / D_total[0],  p, l1+1, buf1);
   
   percentify( D_total[1] * 100 * p / D_total[0],  p, l1+1, buf1);

-  percentify(total[CLG_(sets).off_full_Dr+1] * 100 * p /
-            total[CLG_(sets).off_full_Dr], p, l2+1, buf2);
-  percentify(total[CLG_(sets).off_full_Dw+1] * 100 * p /
-            total[CLG_(sets).off_full_Dw], p, l3+1, buf3);
+  percentify(total[fullOffset(EG_DR)+1] * 100 * p /
+            total[fullOffset(EG_DR)], p, l2+1, buf2);
+  percentify(total[fullOffset(EG_DW)+1] * 100 * p /
+            total[fullOffset(EG_DW)], p, l3+1, buf3);

   VG_(message)(Vg_UserMsg, "D1  miss rate: %s (%s   + %s  )\n", 
                buf1, buf2,buf3);
   
   percentify( D_total[2] * 100 * p / D_total[0],  p, l1+1, buf1);
   VG_(message)(Vg_UserMsg, "D1  miss rate: %s (%s   + %s  )\n", 
                buf1, buf2,buf3);
   
   percentify( D_total[2] * 100 * p / D_total[0],  p, l1+1, buf1);

-  percentify(total[CLG_(sets).off_full_Dr+2] * 100 * p /
-            total[CLG_(sets).off_full_Dr], p, l2+1, buf2);
-  percentify(total[CLG_(sets).off_full_Dw+2] * 100 * p /
-            total[CLG_(sets).off_full_Dw], p, l3+1, buf3);
+  percentify(total[fullOffset(EG_DR)+2] * 100 * p /
+            total[fullOffset(EG_DR)], p, l2+1, buf2);
+  percentify(total[fullOffset(EG_DW)+2] * 100 * p /
+            total[fullOffset(EG_DW)], p, l3+1, buf3);

   VG_(message)(Vg_UserMsg, "L2d miss rate: %s (%s   + %s  )\n", 
                buf1, buf2,buf3);
   VG_(message)(Vg_UserMsg, "\n");
   VG_(message)(Vg_UserMsg, "L2d miss rate: %s (%s   + %s  )\n", 
                buf1, buf2,buf3);
   VG_(message)(Vg_UserMsg, "\n");


@@ -1743,13 +1704,13 @@ void cachesim_printstat(void)
   /* L2 overall results */
   
   L2_total   =
   /* L2 overall results */
   
   L2_total   =

-    total[CLG_(sets).off_full_Dr +1] +
-    total[CLG_(sets).off_full_Dw +1] +
-    total[CLG_(sets).off_full_Ir +1];
+    total[fullOffset(EG_DR) +1] +
+    total[fullOffset(EG_DW) +1] +
+    total[fullOffset(EG_IR) +1];

   L2_total_r =
   L2_total_r =

-    total[CLG_(sets).off_full_Dr +1] +
-    total[CLG_(sets).off_full_Ir +1];
-  L2_total_w = total[CLG_(sets).off_full_Dw +1];
+    total[fullOffset(EG_DR) +1] +
+    total[fullOffset(EG_IR) +1];
+  L2_total_w = total[fullOffset(EG_DW) +1];

   commify(L2_total,   l1, buf1);
   commify(L2_total_r, l2, buf2);
   commify(L2_total_w, l3, buf3);
   commify(L2_total,   l1, buf1);
   commify(L2_total_r, l2, buf2);
   commify(L2_total_w, l3, buf3);


@@ -1757,13 +1718,13 @@ void cachesim_printstat(void)
               buf1, buf2, buf3);
   
   L2_total_m  =
               buf1, buf2, buf3);
   
   L2_total_m  =

-    total[CLG_(sets).off_full_Dr +2] +
-    total[CLG_(sets).off_full_Dw +2] +
-    total[CLG_(sets).off_full_Ir +2];
+    total[fullOffset(EG_DR) +2] +
+    total[fullOffset(EG_DW) +2] +
+    total[fullOffset(EG_IR) +2];

   L2_total_mr =
   L2_total_mr =

-    total[CLG_(sets).off_full_Dr +2] +
-    total[CLG_(sets).off_full_Ir +2];
-  L2_total_mw = total[CLG_(sets).off_full_Dw +2];
+    total[fullOffset(EG_DR) +2] +
+    total[fullOffset(EG_IR) +2];
+  L2_total_mw = total[fullOffset(EG_DW) +2];

   commify(L2_total_m,  l1, buf1);
   commify(L2_total_mr, l2, buf2);
   commify(L2_total_mw, l3, buf3);
   commify(L2_total_m,  l1, buf1);
   commify(L2_total_mr, l2, buf2);
   commify(L2_total_mw, l3, buf3);


@@ -1771,12 +1732,12 @@ void cachesim_printstat(void)
               buf1, buf2, buf3);
   
   percentify(L2_total_m  * 100 * p /
               buf1, buf2, buf3);
   
   percentify(L2_total_m  * 100 * p /

-            (total[CLG_(sets).off_full_Ir] + D_total[0]),  p, l1+1, buf1);
+            (total[fullOffset(EG_IR)] + D_total[0]),  p, l1+1, buf1);

   percentify(L2_total_mr * 100 * p /
   percentify(L2_total_mr * 100 * p /

-            (total[CLG_(sets).off_full_Ir] + total[CLG_(sets).off_full_Dr]),
+            (total[fullOffset(EG_IR)] + total[fullOffset(EG_DR)]),

             p, l2+1, buf2);
   percentify(L2_total_mw * 100 * p /
             p, l2+1, buf2);
   percentify(L2_total_mw * 100 * p /

-            total[CLG_(sets).off_full_Dw], p, l3+1, buf3);
+            total[fullOffset(EG_DW)], p, l3+1, buf3);

   VG_(message)(Vg_UserMsg, "L2 miss rate:  %s (%s   + %s  )\n",
               buf1, buf2,buf3);
 }
   VG_(message)(Vg_UserMsg, "L2 miss rate:  %s (%s   + %s  )\n",
               buf1, buf2,buf3);
 }


@@ -1788,251 +1749,96 @@ void cachesim_printstat(void)
 
 struct event_sets CLG_(sets);
 
 
 struct event_sets CLG_(sets);
 

-void CLG_(init_eventsets)(Int max_user)
+void CLG_(init_eventsets)()

 {
 {

-  EventType * e1, *e2, *e3, *e4;
-  // Basic event sets from which others are composed
-  EventSet *Use, *Ir, *Dr, *Dw;
-  // Compositions of basic sets used for per-instruction counters
-  EventSet *UIr, *UIrDr, *UIrDrDw, *UIrDw, *UIrDwDr;
-  // Composition used for global counters and aggregation
-  EventSet *full;
-  int sizeOfUseIr;
-
-  // the "Use" events types only are used with "cacheuse" simulation
-  Use = CLG_(get_eventset)("Use", 4);
-  if (clo_collect_cacheuse) {
-    /* if TUse is 0, there was never a load, and no loss, too */
-    e1 = CLG_(register_eventtype)("AcCost1");
-    CLG_(add_eventtype)(Use, e1);
-    e1 = CLG_(register_eventtype)("SpLoss1");
-    CLG_(add_eventtype)(Use, e1);
-    e1 = CLG_(register_eventtype)("AcCost2");
-    CLG_(add_eventtype)(Use, e1);
-    e1 = CLG_(register_eventtype)("SpLoss2");
-    CLG_(add_eventtype)(Use, e1);
-  }
-
-  Ir = CLG_(get_eventset)("Ir", 4);
-  Dr = CLG_(get_eventset)("Dr", 4);
-  Dw = CLG_(get_eventset)("Dw", 4);
-  if (CLG_(clo).simulate_cache) {
-    e1 = CLG_(register_eventtype)("Ir");
-    e2 = CLG_(register_eventtype)("I1mr");
-    e3 = CLG_(register_eventtype)("I2mr");
-    if (clo_simulate_writeback) {
-      e4 = CLG_(register_eventtype)("I2dmr");
-      CLG_(add_dep_event4)(Ir, e1,e2,e3,e4);
-    }
-    else
-      CLG_(add_dep_event3)(Ir, e1,e2,e3);
-
-    e1 = CLG_(register_eventtype)("Dr");
-    e2 = CLG_(register_eventtype)("D1mr");
-    e3 = CLG_(register_eventtype)("D2mr");
-    if (clo_simulate_writeback) {
-      e4 = CLG_(register_eventtype)("D2dmr");
-      CLG_(add_dep_event4)(Dr, e1,e2,e3,e4);
+    // Event groups from which the event sets are composed
+    // the "Use" group only is used with "cacheuse" simulation
+    if (clo_collect_cacheuse)
+       CLG_(register_event_group4)(EG_USE,
+                                   "AcCost1", "SpLoss1", "AcCost2", "SpLoss2");
+
+    if (!CLG_(clo).simulate_cache)
+       CLG_(register_event_group)(EG_IR, "Ir");
+    else if (!clo_simulate_writeback) {
+       CLG_(register_event_group3)(EG_IR, "Ir", "I1mr", "I2mr");
+       CLG_(register_event_group3)(EG_DR, "Dr", "D1mr", "D2mr");
+       CLG_(register_event_group3)(EG_DW, "Dw", "D1mw", "D2mw");

     }
     }

-    else
-      CLG_(add_dep_event3)(Dr, e1,e2,e3);
-    
-    e1 = CLG_(register_eventtype)("Dw");
-    e2 = CLG_(register_eventtype)("D1mw");
-    e3 = CLG_(register_eventtype)("D2mw");
-    if (clo_simulate_writeback) {
-      e4 = CLG_(register_eventtype)("D2dmw");
-      CLG_(add_dep_event4)(Dw, e1,e2,e3,e4);
+    else { // clo_simulate_writeback
+       CLG_(register_event_group4)(EG_IR, "Ir", "I1mr", "I2mr", "I2dmr");
+        CLG_(register_event_group4)(EG_DR, "Dr", "D1mr", "D2mr", "D2dmr");
+        CLG_(register_event_group4)(EG_DW, "Dw", "D1mw", "D2mw", "D2dmw");

     }
     }

-    else
-      CLG_(add_dep_event3)(Dw, e1,e2,e3);

 
 

-  }
-  else {
-    e1 = CLG_(register_eventtype)("Ir");
-    CLG_(add_eventtype)(Ir, e1);
-  }
-
-  // Self cost event sets per guest instruction (U used only for cacheUse).
-  // Each basic event set only appears once, as eg. multiple different Dr's
-  // in one guest instruction are counted in the same counter.
-
-  sizeOfUseIr =  Use->size + Ir->size;
-  UIr = CLG_(get_eventset)("UIr", sizeOfUseIr);
-  CLG_(add_eventset)(UIr, Use);
-  off_UIr_Ir  = CLG_(add_eventset)(UIr, Ir);
-
-  UIrDr = CLG_(get_eventset)("UIrDr", sizeOfUseIr + Dr->size);
-  CLG_(add_eventset)(UIrDr, Use);
-  off_UIrDr_Ir = CLG_(add_eventset)(UIrDr, Ir);
-  off_UIrDr_Dr = CLG_(add_eventset)(UIrDr, Dr);
-
-  UIrDrDw  = CLG_(get_eventset)("IrDrDw", sizeOfUseIr + Dr->size + Dw->size);
-  CLG_(add_eventset)(UIrDrDw, Use);
-  off_UIrDrDw_Ir    = CLG_(add_eventset)(UIrDrDw, Ir);
-  off_UIrDrDw_Dr    = CLG_(add_eventset)(UIrDrDw, Dr);
-  off_UIrDrDw_Dw    = CLG_(add_eventset)(UIrDrDw, Dw);
-
-  UIrDw = CLG_(get_eventset)("UIrDw", sizeOfUseIr + Dw->size);
-  CLG_(add_eventset)(UIrDw, Use);
-  off_UIrDw_Ir   = CLG_(add_eventset)(UIrDw, Ir);
-  off_UIrDw_Dw   = CLG_(add_eventset)(UIrDw, Dw);
-
-  UIrDwDr  = CLG_(get_eventset)("IrDwDr", sizeOfUseIr + Dw->size + Dr->size);
-  CLG_(add_eventset)(UIrDwDr, Use);
-  off_UIrDwDr_Ir    = CLG_(add_eventset)(UIrDrDw, Ir);
-  off_UIrDwDr_Dw    = CLG_(add_eventset)(UIrDrDw, Dw);
-  off_UIrDwDr_Dr    = CLG_(add_eventset)(UIrDrDw, Dr);
-
-
-  // the "full" event set is used as global counter and for aggregation
-  if (CLG_(clo).collect_alloc)   max_user += 2;
-  if (CLG_(clo).collect_systime) max_user += 2;
-  full = CLG_(get_eventset)("full",
-                           sizeOfUseIr + Dr->size + Dw->size + max_user);
-  CLG_(add_eventset)(full, Use);
-  CLG_(sets).off_full_Ir   = CLG_(add_eventset)(full, Ir);
-  CLG_(sets).off_full_Dr   = CLG_(add_eventset)(full, Dr);
-  CLG_(sets).off_full_Dw   = CLG_(add_eventset)(full, Dw);
-  if (CLG_(clo).collect_alloc) {
-      e1 = CLG_(register_eventtype)("allocCount");
-      e2 = CLG_(register_eventtype)("allocSize");
-      CLG_(sets).off_full_alloc =  CLG_(add_dep_event2)(full, e1,e2);
-  }
-  if (CLG_(clo).collect_systime) {
-      e1 = CLG_(register_eventtype)("sysCount");
-      e2 = CLG_(register_eventtype)("sysTime");
-      CLG_(sets).off_full_systime =  CLG_(add_dep_event2)(full, e1,e2);
-  }
+    if (CLG_(clo).simulate_branch) {
+        CLG_(register_event_group2)(EG_BC, "Bc", "Bcm");
+        CLG_(register_event_group2)(EG_BI, "Bi", "Bim");
+    }

 
 

-  CLG_(sets).Use = Use;
-  CLG_(sets).Ir  = Ir;
-  CLG_(sets).Dr  = Dr;
-  CLG_(sets).Dw  = Dw;
-  CLG_(sets).UIr  = UIr;
-  CLG_(sets).UIrDr = UIrDr;
-  CLG_(sets).UIrDrDw  = UIrDrDw;
-  CLG_(sets).UIrDw = UIrDw;
-  CLG_(sets).UIrDwDr  = UIrDwDr;
-  CLG_(sets).full = full;
-
-
-  CLG_DEBUGIF(1) {
-    CLG_DEBUG(1, "EventSets:\n");
-    CLG_(print_eventset)(-2, Use);
-    CLG_(print_eventset)(-2, Ir);
-    CLG_(print_eventset)(-2, Dr);
-    CLG_(print_eventset)(-2, Dw);
-    CLG_(print_eventset)(-2, full);
-  }
+    if (CLG_(clo).collect_bus)
+       CLG_(register_event_group)(EG_BUS, "Ge");

 
 

-  /* Not-existing events are silently ignored */
-  CLG_(dumpmap) = CLG_(get_eventmapping)(full);
-  CLG_(append_event)(CLG_(dumpmap), "Ir");
-  CLG_(append_event)(CLG_(dumpmap), "Dr");
-  CLG_(append_event)(CLG_(dumpmap), "Dw");
-  CLG_(append_event)(CLG_(dumpmap), "I1mr");
-  CLG_(append_event)(CLG_(dumpmap), "D1mr");
-  CLG_(append_event)(CLG_(dumpmap), "D1mw");
-  CLG_(append_event)(CLG_(dumpmap), "I2mr");
-  CLG_(append_event)(CLG_(dumpmap), "D2mr");
-  CLG_(append_event)(CLG_(dumpmap), "D2mw");
-  CLG_(append_event)(CLG_(dumpmap), "I2dmr");
-  CLG_(append_event)(CLG_(dumpmap), "D2dmr");
-  CLG_(append_event)(CLG_(dumpmap), "D2dmw");
-  CLG_(append_event)(CLG_(dumpmap), "AcCost1");
-  CLG_(append_event)(CLG_(dumpmap), "SpLoss1");
-  CLG_(append_event)(CLG_(dumpmap), "AcCost2");
-  CLG_(append_event)(CLG_(dumpmap), "SpLoss2");
-  CLG_(append_event)(CLG_(dumpmap), "allocCount");
-  CLG_(append_event)(CLG_(dumpmap), "allocSize");
-  CLG_(append_event)(CLG_(dumpmap), "sysCount");
-  CLG_(append_event)(CLG_(dumpmap), "sysTime");
+    if (CLG_(clo).collect_alloc)
+       CLG_(register_event_group2)(EG_ALLOC, "allocCount", "allocSize");

 
 

-}
+    if (CLG_(clo).collect_systime)
+       CLG_(register_event_group2)(EG_SYS, "sysCount", "sysTime");

 
 

+    // event set used as base for instruction self cost
+    CLG_(sets).base = CLG_(get_event_set2)(EG_USE, EG_IR);

 
 

+    // event set comprising all event groups, used for inclusive cost
+    CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).base, EG_DR, EG_DW);
+    CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_BC, EG_BI);
+    CLG_(sets).full = CLG_(add_event_group) (CLG_(sets).full, EG_BUS);
+    CLG_(sets).full = CLG_(add_event_group2)(CLG_(sets).full, EG_ALLOC, EG_SYS);

 
 

-static
-void add_and_zero_Dx(EventSet* es, SimCost dst, ULong* cost)
-{
-  /* if eventset use is defined, it is always first (hardcoded!) */
-  CLG_(add_and_zero_cost)( CLG_(sets).Use, dst, cost);
+    CLG_DEBUGIF(1) {
+       CLG_DEBUG(1, "EventSets:\n");
+       CLG_(print_eventset)(-2, CLG_(sets).base);
+       CLG_(print_eventset)(-2, CLG_(sets).full);
+    }

 
 

-  if (es == CLG_(sets).UIr) {
-    CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir,
-                           cost + off_UIr_Ir);
-  }
-  else if (es == CLG_(sets).UIrDr) {
-    CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir,
-                           cost + off_UIrDr_Ir);
-    CLG_(add_and_zero_cost)( CLG_(sets).Dr, dst + CLG_(sets).off_full_Dr,
-                           cost + off_UIrDr_Dr);
-  }
-  else if (es == CLG_(sets).UIrDrDw) {
-    CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir,
-                           cost + off_UIrDrDw_Ir);
-    CLG_(add_and_zero_cost)( CLG_(sets).Dr, dst + CLG_(sets).off_full_Dr,
-                           cost + off_UIrDrDw_Dr);
-    CLG_(add_and_zero_cost)( CLG_(sets).Dw, dst + CLG_(sets).off_full_Dw,
-                           cost + off_UIrDrDw_Dw);
-  }
-  else if (es == CLG_(sets).UIrDw) {
-      CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir,
-                              cost + off_UIrDw_Ir);
-      CLG_(add_and_zero_cost)( CLG_(sets).Dw, dst + CLG_(sets).off_full_Dw,
-                              cost + off_UIrDw_Dw);
-  }
-  else if (es == CLG_(sets).UIrDwDr) {
-    CLG_(add_and_zero_cost)( CLG_(sets).Ir, dst + CLG_(sets).off_full_Ir,
-                           cost + off_UIrDwDr_Ir);
-    CLG_(add_and_zero_cost)( CLG_(sets).Dw, dst + CLG_(sets).off_full_Dw,
-                           cost + off_UIrDwDr_Dw);
-    CLG_(add_and_zero_cost)( CLG_(sets).Dr, dst + CLG_(sets).off_full_Dr,
-                            cost + off_UIrDwDr_Dr);
-  }
-  else CLG_ASSERT(0);
+    /* Not-existing events are silently ignored */
+    CLG_(dumpmap) = CLG_(get_eventmapping)(CLG_(sets).full);
+    CLG_(append_event)(CLG_(dumpmap), "Ir");
+    CLG_(append_event)(CLG_(dumpmap), "Dr");
+    CLG_(append_event)(CLG_(dumpmap), "Dw");
+    CLG_(append_event)(CLG_(dumpmap), "I1mr");
+    CLG_(append_event)(CLG_(dumpmap), "D1mr");
+    CLG_(append_event)(CLG_(dumpmap), "D1mw");
+    CLG_(append_event)(CLG_(dumpmap), "I2mr");
+    CLG_(append_event)(CLG_(dumpmap), "D2mr");
+    CLG_(append_event)(CLG_(dumpmap), "D2mw");
+    CLG_(append_event)(CLG_(dumpmap), "I2dmr");
+    CLG_(append_event)(CLG_(dumpmap), "D2dmr");
+    CLG_(append_event)(CLG_(dumpmap), "D2dmw");
+    CLG_(append_event)(CLG_(dumpmap), "Bc");
+    CLG_(append_event)(CLG_(dumpmap), "Bcm");
+    CLG_(append_event)(CLG_(dumpmap), "Bi");
+    CLG_(append_event)(CLG_(dumpmap), "Bim");
+    CLG_(append_event)(CLG_(dumpmap), "AcCost1");
+    CLG_(append_event)(CLG_(dumpmap), "SpLoss1");
+    CLG_(append_event)(CLG_(dumpmap), "AcCost2");
+    CLG_(append_event)(CLG_(dumpmap), "SpLoss2");
+    CLG_(append_event)(CLG_(dumpmap), "Ge");
+    CLG_(append_event)(CLG_(dumpmap), "allocCount");
+    CLG_(append_event)(CLG_(dumpmap), "allocSize");
+    CLG_(append_event)(CLG_(dumpmap), "sysCount");
+    CLG_(append_event)(CLG_(dumpmap), "sysTime");

 }
 
 }
 

+

 /* this is called at dump time for every instruction executed */
 static void cachesim_add_icost(SimCost cost, BBCC* bbcc,
                               InstrInfo* ii, ULong exe_count)
 {
 /* this is called at dump time for every instruction executed */
 static void cachesim_add_icost(SimCost cost, BBCC* bbcc,
                               InstrInfo* ii, ULong exe_count)
 {

-  if (!CLG_(clo).simulate_cache)
-      cost[CLG_(sets).off_full_Ir] += exe_count;
-  else {
-
-#if 0
-/* There is always a trivial case where exe_count and Ir can be
- * slightly different because ecounter is updated when executing
- * the next BB. E.g. for last BB executed, or when toggling collection
- */
-      /* FIXME: Hardcoded that each eventset has Ir as first */
-      if ((bbcc->cost + ii->cost_offset)[0] != exe_count) {
-         VG_(printf)("==> Ir %llu, exe %llu\n",
-                     (bbcc->cost + ii->cost_offset)[0], exe_count);
-         CLG_(print_bbcc_cost)(-2, bbcc);
-         //CLG_ASSERT((bbcc->cost + ii->cost_offset)[0] == exe_count);
-      }
-#endif
+    if (!CLG_(clo).simulate_cache)
+       cost[ fullOffset(EG_IR) ] += exe_count;

 
 

-      add_and_zero_Dx(ii->eventset, cost,
-                     bbcc->cost + ii->cost_offset);
-  }
-}
-
-static
-void cachesim_after_bbsetup(void)
-{
-  BBCC* bbcc = CLG_(current_state).bbcc;
-
-  if (CLG_(clo).simulate_cache) {
-    BB* bb = bbcc->bb;
-
-    /* only needed if log_* functions are called */
-    bb_base   = bb->obj->offset + bb->offset;
-    cost_base = bbcc->cost;
-  }
+    if (ii->eventset)
+       CLG_(add_and_zero_cost2)( CLG_(sets).full, cost,
+                                 ii->eventset, bbcc->cost + ii->cost_offset);

 }
 
 static
 }
 
 static


@@ -2054,7 +1860,6 @@ struct cachesim_if CLG_(cachesim) = {
   .getdesc       = cachesim_getdesc,
   .printstat     = cachesim_printstat,
   .add_icost     = cachesim_add_icost,
   .getdesc       = cachesim_getdesc,
   .printstat     = cachesim_printstat,
   .add_icost     = cachesim_add_icost,

-  .after_bbsetup = cachesim_after_bbsetup,

   .finish        = cachesim_finish,
 
   /* these will be set by cachesim_post_clo_init */
   .finish        = cachesim_finish,
 
   /* these will be set by cachesim_post_clo_init */

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/Makefile.am
index 03e0f9f764f081beee3bed9f90ad848a00b3ea57..2fb9fe2655c211672ade8224d4863d0199a0e974 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/Makefile.am
@@ -15,7 +15,8 @@ EXTRA_DIST = \
        notpower2-wb.vgtest notpower2-wb.stderr.exp \
        notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
        notpower2-use.vgtest notpower2-use.stderr.exp \
        notpower2-wb.vgtest notpower2-wb.stderr.exp \
        notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
        notpower2-use.vgtest notpower2-use.stderr.exp \

-       threads.vgtest threads.stderr.exp
+       threads.vgtest threads.stderr.exp \
+       threads-use.vgtest threads-use.stderr.exp

 
 check_PROGRAMS = clreq simwork threads
 
 
 check_PROGRAMS = clreq simwork threads
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/Makefile.in
index 7b4e938b9fe680be5d02663d0b3d11e024959a9b..d7d283b0eb89cd2c0e1116aac6de4d6d297a8864 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/Makefile.in
@@ -153,6 +153,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -187,14 +188,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -277,7 +282,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -336,7 +343,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -351,8 +358,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -423,7 +430,8 @@ EXTRA_DIST = \
        notpower2-wb.vgtest notpower2-wb.stderr.exp \
        notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
        notpower2-use.vgtest notpower2-use.stderr.exp \
        notpower2-wb.vgtest notpower2-wb.stderr.exp \
        notpower2-hwpref.vgtest notpower2-hwpref.stderr.exp \
        notpower2-use.vgtest notpower2-use.stderr.exp \

-       threads.vgtest threads.stderr.exp
+       threads.vgtest threads.stderr.exp \
+       threads-use.vgtest threads-use.stderr.exp

 
 threads_LDADD = -lpthread
 all: all-recursive
 
 threads_LDADD = -lpthread
 all: all-recursive

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/filter_stderr b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/filter_stderr
index 1a58540d4546cd882a2cea13aeb0d7d4058ff984..d2d754456b5cb188ddcfda2a21a19241f20d866c 100755 (executable)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/filter_stderr
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/filter_stderr
@@ -19,6 +19,9 @@ perl -p -e 's/((I|D|L2) *refs:)[ 0-9,()+rdw]*$/\1/'  |
 # Remove numbers from I1/D1/L2/L2i/L2d "misses:" and "miss rates:" lines
 perl -p -e 's/((I1|D1|L2|L2i|L2d) *(misses|miss rate):)[ 0-9,()+rdw%\.]*$/\1/' |
 
 # Remove numbers from I1/D1/L2/L2i/L2d "misses:" and "miss rates:" lines
 perl -p -e 's/((I1|D1|L2|L2i|L2d) *(misses|miss rate):)[ 0-9,()+rdw%\.]*$/\1/' |
 

+# Remove numbers from "Branches:", "Mispredicts:, and "Mispred rate:" lines
+perl -p -e 's/((Branches|Mispredicts|Mispred rate):)[ 0-9,()+condi%\.]*$/\1/' |
+

 # Remove CPUID warnings lines for P4s and other machines
 sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
 sed "/Simulating a 16 KB I-cache with 32 B lines/d"   |
 # Remove CPUID warnings lines for P4s and other machines
 sed "/warning: Pentium 4 with 12 KB micro-op instruction trace cache/d" |
 sed "/Simulating a 16 KB I-cache with 32 B lines/d"   |

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.stderr.exp
new file mode 100644 (file)
index 0000000..b742c21
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.stderr.exp
@@ -0,0 +1,24 @@
+
+
+Events    : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw Bc Bcm Bi Bim
+Collected :
+
+I   refs:
+I1  misses:
+L2i misses:
+I1  miss rate:
+L2i miss rate:
+
+D   refs:
+D1  misses:
+L2d misses:
+D1  miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:
+
+Branches:
+Mispredicts:
+Mispred rate:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.stdout.exp
new file mode 100644 (file)
index 0000000..d4c867c
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.stdout.exp
@@ -0,0 +1 @@
+Sum: 1000000

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.vgtest
new file mode 100644 (file)
index 0000000..19c3ff8
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-both.vgtest
@@ -0,0 +1,3 @@
+prog: simwork
+vgopts: --cache-sim=yes --branch-sim=yes
+cleanup: rm callgrind.out.*

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.stderr.exp
new file mode 100644 (file)
index 0000000..7cda62e
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.stderr.exp
@@ -0,0 +1,10 @@
+
+
+Events    : Ir Bc Bcm Bi Bim
+Collected :
+
+I   refs:
+
+Branches:
+Mispredicts:
+Mispred rate:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.stdout.exp
new file mode 100644 (file)
index 0000000..d4c867c
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.stdout.exp
@@ -0,0 +1 @@
+Sum: 1000000

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.vgtest
new file mode 100644 (file)
index 0000000..a866e1e
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-branch.vgtest
@@ -0,0 +1,3 @@
+prog: simwork
+vgopts: --branch-sim=yes
+cleanup: rm callgrind.out.*

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.stderr.exp
new file mode 100644 (file)
index 0000000..0705c1c
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.stderr.exp
@@ -0,0 +1,20 @@
+
+
+Events    : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw
+Collected :
+
+I   refs:
+I1  misses:
+L2i misses:
+I1  miss rate:
+L2i miss rate:
+
+D   refs:
+D1  misses:
+L2d misses:
+D1  miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.stdout.exp
new file mode 100644 (file)
index 0000000..d4c867c
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.stdout.exp
@@ -0,0 +1 @@
+Sum: 1000000

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.vgtest
new file mode 100644 (file)
index 0000000..ce222c0
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/simwork-cache.vgtest
@@ -0,0 +1,3 @@
+prog: simwork
+vgopts: --cache-sim=yes
+cleanup: rm callgrind.out.*

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads-use.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads-use.stderr.exp
new file mode 100644 (file)
index 0000000..4f0bb99
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads-use.stderr.exp
@@ -0,0 +1,20 @@
+
+
+Events    : Ir Dr Dw I1mr D1mr D1mw I2mr D2mr D2mw AcCost1 SpLoss1 AcCost2 SpLoss2 Ge sysCount sysTime
+Collected :
+
+I   refs:
+I1  misses:
+L2i misses:
+I1  miss rate:
+L2i miss rate:
+
+D   refs:
+D1  misses:
+L2d misses:
+D1  miss rate:
+L2d miss rate:
+
+L2 refs:
+L2 misses:
+L2 miss rate:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads-use.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads-use.vgtest
new file mode 100644 (file)
index 0000000..6299b1f
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads-use.vgtest
@@ -0,0 +1,3 @@
+prog: threads
+vgopts: --separate-threads=yes --cacheuse=yes --collect-bus=yes --collect-systime=yes
+cleanup: rm callgrind.out.*

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads.stderr.exp
index d0b7820ae3a6bb73ff444c43c5e7985e130a8b02..da443cf50e2a88e29ecbf1d16e536fc0eda6c6c7 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads.stderr.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads.stderr.exp
@@ -1,6 +1,6 @@
 
 
 
 

-Events    : Ir
+Events    : Ir Ge

 Collected :
 
 I   refs:
 Collected :
 
 I   refs:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads.vgtest
index d015eebb5ed690ed130361ea964286b94eae505e..4ff103aabe1090c4272ee14b1b10b2ef113cbb13 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads.vgtest
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/callgrind/tests/threads.vgtest
@@ -1,3 +1,3 @@
 prog: threads
 prog: threads

-vgopts: --separate-threads=yes
+vgopts: --separate-threads=yes --collect-bus=yes

 cleanup: rm callgrind.out.*
 cleanup: rm callgrind.out.*

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/config.h.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/config.h.in
index c34447526e75b74137d0a31edd7106381fcd67c7..42bbc73dad9854d959fd6bf76eb97ffdd289960d 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/config.h.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/config.h.in
@@ -3,9 +3,21 @@
 /* Define to 1 if you're using AIX 5.1 or 5.2 or 5.3 */
 #undef AIX5_LIBC
 
 /* Define to 1 if you're using AIX 5.1 or 5.2 or 5.3 */
 #undef AIX5_LIBC
 

+/* DARWIN_VERS value for Mac OS X 10.5 */
+#undef DARWIN_10_5
+
+/* DARWIN_VERS value for Mac OS X 10.6 */
+#undef DARWIN_10_6
+
+/* DARWIN_VERS value for Mac OS X 10.7 */
+#undef DARWIN_10_7
+

 /* Define to 1 if you're using Darwin */
 #undef DARWIN_LIBC
 
 /* Define to 1 if you're using Darwin */
 #undef DARWIN_LIBC
 

+/* Darwin / Mac OS X version */
+#undef DARWIN_VERS
+

 /* configured to run as an inner Valgrind */
 #undef ENABLE_INNER
 
 /* configured to run as an inner Valgrind */
 #undef ENABLE_INNER
 


@@ -18,6 +30,9 @@
 /* Define to 1 if you're using glibc 2.11.x */
 #undef GLIBC_2_11
 
 /* Define to 1 if you're using glibc 2.11.x */
 #undef GLIBC_2_11
 

+/* Define to 1 if you're using glibc 2.12.x */
+#undef GLIBC_2_12
+

 /* Define to 1 if you're using glibc 2.2.x */
 #undef GLIBC_2_2
 
 /* Define to 1 if you're using glibc 2.2.x */
 #undef GLIBC_2_2
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/configure b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/configure
index 987becd4984ff4ddea5044df3c4d4ca48e633acb..b0548851f4348d373a34db86edafac6489a7e861 100755 (executable)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/configure
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/configure
@@ -1,13 +1,13 @@
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.
 #! /bin/sh
 # Guess values for system-dependent variables and create Makefiles.

-# Generated by GNU Autoconf 2.65 for Valgrind 3.6.0.SVN.
+# Generated by GNU Autoconf 2.67 for Valgrind 3.6.0.SVN.

 #
 # Report bugs to <valgrind-users@lists.sourceforge.net>.
 #
 #
 # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
 #
 # Report bugs to <valgrind-users@lists.sourceforge.net>.
 #
 #
 # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,

-# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation,
-# Inc.
+# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software
+# Foundation, Inc.

 #
 #
 # This configure script is free software; the Free Software Foundation
 #
 #
 # This configure script is free software; the Free Software Foundation


@@ -319,7 +319,7 @@ $as_echo X"$as_dir" |
       test -d "$as_dir" && break
     done
     test -z "$as_dirs" || eval "mkdir $as_dirs"
       test -d "$as_dir" && break
     done
     test -z "$as_dirs" || eval "mkdir $as_dirs"

-  } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir"
+  } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"

 
 
 } # as_fn_mkdir_p
 
 
 } # as_fn_mkdir_p


@@ -359,19 +359,19 @@ else
 fi # as_fn_arith
 
 
 fi # as_fn_arith
 
 

-# as_fn_error ERROR [LINENO LOG_FD]
-# ---------------------------------
+# as_fn_error STATUS ERROR [LINENO LOG_FD]
+# ----------------------------------------

 # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
 # provided, also output the error to LOG_FD, referencing LINENO. Then exit the
 # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
 # provided, also output the error to LOG_FD, referencing LINENO. Then exit the

-# script with status $?, using 1 if that was 0.
+# script with STATUS, using 1 if that was 0.

 as_fn_error ()
 {
 as_fn_error ()
 {

-  as_status=$?; test $as_status -eq 0 && as_status=1
-  if test "$3"; then
-    as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
-    $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3
+  as_status=$1; test $as_status -eq 0 && as_status=1
+  if test "$4"; then
+    as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+    $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4

   fi
   fi

-  $as_echo "$as_me: error: $1" >&2
+  $as_echo "$as_me: error: $2" >&2

   as_fn_exit $as_status
 } # as_fn_error
 
   as_fn_exit $as_status
 } # as_fn_error
 


@@ -533,7 +533,7 @@ test -n "$DJDIR" || exec 7<&0 </dev/null
 exec 6>&1
 
 # Name of the host.
 exec 6>&1
 
 # Name of the host.

-# hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
+# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status,

 # so uname gets run too.
 ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
 
 # so uname gets run too.
 ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
 


@@ -612,6 +612,8 @@ HAVE_QTCORE_FALSE
 HAVE_QTCORE_TRUE
 QTCORE_LIBS
 QTCORE_CFLAGS
 HAVE_QTCORE_TRUE
 QTCORE_LIBS
 QTCORE_CFLAGS

+PKG_CONFIG_LIBDIR
+PKG_CONFIG_PATH

 PKG_CONFIG
 BUILD_MPIWRAP_SEC_FALSE
 BUILD_MPIWRAP_SEC_TRUE
 PKG_CONFIG
 BUILD_MPIWRAP_SEC_FALSE
 BUILD_MPIWRAP_SEC_TRUE


@@ -629,6 +631,7 @@ BUILD_SSSE3_TESTS_FALSE
 BUILD_SSSE3_TESTS_TRUE
 BUILD_SSE3_TESTS_FALSE
 BUILD_SSE3_TESTS_TRUE
 BUILD_SSSE3_TESTS_TRUE
 BUILD_SSE3_TESTS_FALSE
 BUILD_SSE3_TESTS_TRUE

+FLAG_NO_BUILD_ID

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH
 FLAG_FNO_STACK_PROTECTOR
 FLAG_W_EXTRA
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH
 FLAG_FNO_STACK_PROTECTOR
 FLAG_W_EXTRA


@@ -653,7 +656,8 @@ EGREP
 GREP
 GENERATED_SUPP
 DEFAULT_SUPP
 GREP
 GENERATED_SUPP
 DEFAULT_SUPP

-VALT_LOAD_ADDRESS
+VALT_LOAD_ADDRESS_SEC
+VALT_LOAD_ADDRESS_PRI

 VGCONF_HAVE_PLATFORM_SEC_FALSE
 VGCONF_HAVE_PLATFORM_SEC_TRUE
 VGCONF_OS_IS_L4RE_FALSE
 VGCONF_HAVE_PLATFORM_SEC_FALSE
 VGCONF_HAVE_PLATFORM_SEC_TRUE
 VGCONF_OS_IS_L4RE_FALSE


@@ -716,6 +720,7 @@ CCAS
 GDB
 PERL
 AR
 GDB
 PERL
 AR

+SED

 RANLIB
 am__fastdepCXX_FALSE
 am__fastdepCXX_TRUE
 RANLIB
 am__fastdepCXX_FALSE
 am__fastdepCXX_TRUE


@@ -832,6 +837,8 @@ AR
 CCAS
 CCASFLAGS
 PKG_CONFIG
 CCAS
 CCASFLAGS
 PKG_CONFIG

+PKG_CONFIG_PATH
+PKG_CONFIG_LIBDIR

 QTCORE_CFLAGS
 QTCORE_LIBS'
 
 QTCORE_CFLAGS
 QTCORE_LIBS'
 


@@ -896,8 +903,9 @@ do
   fi
 
   case $ac_option in
   fi
 
   case $ac_option in

-  *=*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;;
-  *)   ac_optarg=yes ;;
+  *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;;
+  *=)   ac_optarg= ;;
+  *)    ac_optarg=yes ;;

   esac
 
   # Accept the important Cygnus configure options, so we can diagnose typos.
   esac
 
   # Accept the important Cygnus configure options, so we can diagnose typos.


@@ -942,7 +950,7 @@ do
     ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
     # Reject names that are not valid shell variable names.
     expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
     ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
     # Reject names that are not valid shell variable names.
     expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&

-      as_fn_error "invalid feature name: $ac_useropt"
+      as_fn_error $? "invalid feature name: $ac_useropt"

     ac_useropt_orig=$ac_useropt
     ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
     case $ac_user_opts in
     ac_useropt_orig=$ac_useropt
     ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
     case $ac_user_opts in


@@ -968,7 +976,7 @@ do
     ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
     # Reject names that are not valid shell variable names.
     expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
     ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
     # Reject names that are not valid shell variable names.
     expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&

-      as_fn_error "invalid feature name: $ac_useropt"
+      as_fn_error $? "invalid feature name: $ac_useropt"

     ac_useropt_orig=$ac_useropt
     ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
     case $ac_user_opts in
     ac_useropt_orig=$ac_useropt
     ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
     case $ac_user_opts in


@@ -1172,7 +1180,7 @@ do
     ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
     # Reject names that are not valid shell variable names.
     expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
     ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
     # Reject names that are not valid shell variable names.
     expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&

-      as_fn_error "invalid package name: $ac_useropt"
+      as_fn_error $? "invalid package name: $ac_useropt"

     ac_useropt_orig=$ac_useropt
     ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
     case $ac_user_opts in
     ac_useropt_orig=$ac_useropt
     ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
     case $ac_user_opts in


@@ -1188,7 +1196,7 @@ do
     ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'`
     # Reject names that are not valid shell variable names.
     expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
     ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'`
     # Reject names that are not valid shell variable names.
     expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&

-      as_fn_error "invalid package name: $ac_useropt"
+      as_fn_error $? "invalid package name: $ac_useropt"

     ac_useropt_orig=$ac_useropt
     ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
     case $ac_user_opts in
     ac_useropt_orig=$ac_useropt
     ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
     case $ac_user_opts in


@@ -1218,8 +1226,8 @@ do
   | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
     x_libraries=$ac_optarg ;;
 
   | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
     x_libraries=$ac_optarg ;;
 

-  -*) as_fn_error "unrecognized option: \`$ac_option'
-Try \`$0 --help' for more information."
+  -*) as_fn_error $? "unrecognized option: \`$ac_option'
+Try \`$0 --help' for more information"

     ;;
 
   *=*)
     ;;
 
   *=*)


@@ -1227,7 +1235,7 @@ Try \`$0 --help' for more information."
     # Reject names that are not valid shell variable names.
     case $ac_envvar in #(
       '' | [0-9]* | *[!_$as_cr_alnum]* )
     # Reject names that are not valid shell variable names.
     case $ac_envvar in #(
       '' | [0-9]* | *[!_$as_cr_alnum]* )

-      as_fn_error "invalid variable name: \`$ac_envvar'" ;;
+      as_fn_error $? "invalid variable name: \`$ac_envvar'" ;;

     esac
     eval $ac_envvar=\$ac_optarg
     export $ac_envvar ;;
     esac
     eval $ac_envvar=\$ac_optarg
     export $ac_envvar ;;


@@ -1245,13 +1253,13 @@ done
 
 if test -n "$ac_prev"; then
   ac_option=--`echo $ac_prev | sed 's/_/-/g'`
 
 if test -n "$ac_prev"; then
   ac_option=--`echo $ac_prev | sed 's/_/-/g'`

-  as_fn_error "missing argument to $ac_option"
+  as_fn_error $? "missing argument to $ac_option"

 fi
 
 if test -n "$ac_unrecognized_opts"; then
   case $enable_option_checking in
     no) ;;
 fi
 
 if test -n "$ac_unrecognized_opts"; then
   case $enable_option_checking in
     no) ;;

-    fatal) as_fn_error "unrecognized options: $ac_unrecognized_opts" ;;
+    fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;;

     *)     $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;;
   esac
 fi
     *)     $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;;
   esac
 fi


@@ -1274,7 +1282,7 @@ do
     [\\/$]* | ?:[\\/]* )  continue;;
     NONE | '' ) case $ac_var in *prefix ) continue;; esac;;
   esac
     [\\/$]* | ?:[\\/]* )  continue;;
     NONE | '' ) case $ac_var in *prefix ) continue;; esac;;
   esac

-  as_fn_error "expected an absolute directory name for --$ac_var: $ac_val"
+  as_fn_error $? "expected an absolute directory name for --$ac_var: $ac_val"

 done
 
 # There might be people who depend on the old broken behavior: `$host'
 done
 
 # There might be people who depend on the old broken behavior: `$host'


@@ -1288,8 +1296,8 @@ target=$target_alias
 if test "x$host_alias" != x; then
   if test "x$build_alias" = x; then
     cross_compiling=maybe
 if test "x$host_alias" != x; then
   if test "x$build_alias" = x; then
     cross_compiling=maybe

-    $as_echo "$as_me: WARNING: If you wanted to set the --build type, don't use --host.
-    If a cross compiler is detected then cross compile mode will be used." >&2
+    $as_echo "$as_me: WARNING: if you wanted to set the --build type, don't use --host.
+    If a cross compiler is detected then cross compile mode will be used" >&2

   elif test "x$build_alias" != "x$host_alias"; then
     cross_compiling=yes
   fi
   elif test "x$build_alias" != "x$host_alias"; then
     cross_compiling=yes
   fi


@@ -1304,9 +1312,9 @@ test "$silent" = yes && exec 6>/dev/null
 ac_pwd=`pwd` && test -n "$ac_pwd" &&
 ac_ls_di=`ls -di .` &&
 ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` ||
 ac_pwd=`pwd` && test -n "$ac_pwd" &&
 ac_ls_di=`ls -di .` &&
 ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` ||

-  as_fn_error "working directory cannot be determined"
+  as_fn_error $? "working directory cannot be determined"

 test "X$ac_ls_di" = "X$ac_pwd_ls_di" ||
 test "X$ac_ls_di" = "X$ac_pwd_ls_di" ||

-  as_fn_error "pwd does not report name of working directory"
+  as_fn_error $? "pwd does not report name of working directory"

 
 
 # Find the source files, if location was not specified.
 
 
 # Find the source files, if location was not specified.


@@ -1345,11 +1353,11 @@ else
 fi
 if test ! -r "$srcdir/$ac_unique_file"; then
   test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .."
 fi
 if test ! -r "$srcdir/$ac_unique_file"; then
   test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .."

-  as_fn_error "cannot find sources ($ac_unique_file) in $srcdir"
+  as_fn_error $? "cannot find sources ($ac_unique_file) in $srcdir"

 fi
 ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work"
 ac_abs_confdir=`(
 fi
 ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work"
 ac_abs_confdir=`(

-       cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error "$ac_msg"
+       cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error $? "$ac_msg"

        pwd)`
 # When building in place, set srcdir=.
 if test "$ac_abs_confdir" = "$ac_pwd"; then
        pwd)`
 # When building in place, set srcdir=.
 if test "$ac_abs_confdir" = "$ac_pwd"; then


@@ -1389,7 +1397,7 @@ Configuration:
       --help=short        display options specific to this package
       --help=recursive    display the short help of all the included packages
   -V, --version           display version information and exit
       --help=short        display options specific to this package
       --help=recursive    display the short help of all the included packages
   -V, --version           display version information and exit

-  -q, --quiet, --silent   do not print \`checking...' messages
+  -q, --quiet, --silent   do not print \`checking ...' messages

       --cache-file=FILE   cache test results in FILE [disabled]
   -C, --config-cache      alias for \`--cache-file=config.cache'
   -n, --no-create         do not create output files
       --cache-file=FILE   cache test results in FILE [disabled]
   -C, --config-cache      alias for \`--cache-file=config.cache'
   -n, --no-create         do not create output files


@@ -1482,6 +1490,10 @@ Some influential environment variables:
   CCAS        assembler compiler command (defaults to CC)
   CCASFLAGS   assembler compiler flags (defaults to CFLAGS)
   PKG_CONFIG  path to pkg-config utility
   CCAS        assembler compiler command (defaults to CC)
   CCASFLAGS   assembler compiler flags (defaults to CFLAGS)
   PKG_CONFIG  path to pkg-config utility

+  PKG_CONFIG_PATH
+              directories to add to pkg-config's search path
+  PKG_CONFIG_LIBDIR
+              path overriding pkg-config's built-in search path

   QTCORE_CFLAGS
               C compiler flags for QTCORE, overriding pkg-config
   QTCORE_LIBS linker flags for QTCORE, overriding pkg-config
   QTCORE_CFLAGS
               C compiler flags for QTCORE, overriding pkg-config
   QTCORE_LIBS linker flags for QTCORE, overriding pkg-config


@@ -1553,9 +1565,9 @@ test -n "$ac_init_help" && exit $ac_status
 if $ac_init_version; then
   cat <<\_ACEOF
 Valgrind configure 3.6.0.SVN
 if $ac_init_version; then
   cat <<\_ACEOF
 Valgrind configure 3.6.0.SVN

-generated by GNU Autoconf 2.65
+generated by GNU Autoconf 2.67

 
 

-Copyright (C) 2009 Free Software Foundation, Inc.
+Copyright (C) 2010 Free Software Foundation, Inc.

 This configure script is free software; the Free Software Foundation
 gives unlimited permission to copy, distribute and modify it.
 _ACEOF
 This configure script is free software; the Free Software Foundation
 gives unlimited permission to copy, distribute and modify it.
 _ACEOF


@@ -1625,7 +1637,7 @@ $as_echo "$ac_try_echo"; } >&5
     mv -f conftest.er1 conftest.err
   fi
   $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
     mv -f conftest.er1 conftest.err
   fi
   $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5

-  test $ac_status = 0; } >/dev/null && {
+  test $ac_status = 0; } > conftest.i && {

         test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
         test ! -s conftest.err
        }; then :
         test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" ||
         test ! -s conftest.err
        }; then :


@@ -1725,48 +1737,6 @@ fi
 
 } # ac_fn_c_try_link
 
 
 } # ac_fn_c_try_link
 

-# ac_fn_c_try_run LINENO
-# ----------------------
-# Try to link conftest.$ac_ext, and return whether this succeeded. Assumes
-# that executables *can* be run.
-ac_fn_c_try_run ()
-{
-  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
-  if { { ac_try="$ac_link"
-case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
-$as_echo "$ac_try_echo"; } >&5
-  (eval "$ac_link") 2>&5
-  ac_status=$?
-  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-  test $ac_status = 0; } && { ac_try='./conftest$ac_exeext'
-  { { case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
-$as_echo "$ac_try_echo"; } >&5
-  (eval "$ac_try") 2>&5
-  ac_status=$?
-  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
-  test $ac_status = 0; }; }; then :
-  ac_retval=0
-else
-  $as_echo "$as_me: program exited with status $ac_status" >&5
-       $as_echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-       ac_retval=$ac_status
-fi
-  rm -rf conftest.dSYM conftest_ipa8_conftest.oo
-  eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
-  as_fn_set_status $ac_retval
-
-} # ac_fn_c_try_run
-

 # ac_fn_c_check_header_mongrel LINENO HEADER VAR INCLUDES
 # -------------------------------------------------------
 # Tests whether HEADER exists, giving a warning if it cannot be compiled using
 # ac_fn_c_check_header_mongrel LINENO HEADER VAR INCLUDES
 # -------------------------------------------------------
 # Tests whether HEADER exists, giving a warning if it cannot be compiled using


@@ -1775,10 +1745,10 @@ fi
 ac_fn_c_check_header_mongrel ()
 {
   as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
 ac_fn_c_check_header_mongrel ()
 {
   as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack

-  if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+  if eval "test \"\${$3+set}\"" = set; then :

   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }

-if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+if eval "test \"\${$3+set}\"" = set; then :

   $as_echo_n "(cached) " >&6
 fi
 eval ac_res=\$$3
   $as_echo_n "(cached) " >&6
 fi
 eval ac_res=\$$3


@@ -1814,7 +1784,7 @@ if ac_fn_c_try_cpp "$LINENO"; then :
 else
   ac_header_preproc=no
 fi
 else
   ac_header_preproc=no
 fi

-rm -f conftest.err conftest.$ac_ext
+rm -f conftest.err conftest.i conftest.$ac_ext

 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_preproc" >&5
 $as_echo "$ac_header_preproc" >&6; }
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_preproc" >&5
 $as_echo "$ac_header_preproc" >&6; }
 


@@ -1837,17 +1807,15 @@ $as_echo "$as_me: WARNING: $2: see the Autoconf documentation" >&2;}
 $as_echo "$as_me: WARNING: $2:     section \"Present But Cannot Be Compiled\"" >&2;}
     { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: proceeding with the compiler's result" >&5
 $as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;}
 $as_echo "$as_me: WARNING: $2:     section \"Present But Cannot Be Compiled\"" >&2;}
     { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $2: proceeding with the compiler's result" >&5
 $as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;}

-( cat <<\_ASBOX
-## --------------------------------------------------- ##
+( $as_echo "## --------------------------------------------------- ##

 ## Report this to valgrind-users@lists.sourceforge.net ##
 ## Report this to valgrind-users@lists.sourceforge.net ##

-## --------------------------------------------------- ##
-_ASBOX
+## --------------------------------------------------- ##"

      ) | sed "s/^/$as_me: WARNING:     /" >&2
     ;;
 esac
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }
      ) | sed "s/^/$as_me: WARNING:     /" >&2
     ;;
 esac
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }

-if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+if eval "test \"\${$3+set}\"" = set; then :

   $as_echo_n "(cached) " >&6
 else
   eval "$3=\$ac_header_compiler"
   $as_echo_n "(cached) " >&6
 else
   eval "$3=\$ac_header_compiler"


@@ -1860,6 +1828,48 @@ fi
 
 } # ac_fn_c_check_header_mongrel
 
 
 } # ac_fn_c_check_header_mongrel
 

+# ac_fn_c_try_run LINENO
+# ----------------------
+# Try to link conftest.$ac_ext, and return whether this succeeded. Assumes
+# that executables *can* be run.
+ac_fn_c_try_run ()
+{
+  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+  if { { ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; } && { ac_try='./conftest$ac_exeext'
+  { { case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_try") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }; then :
+  ac_retval=0
+else
+  $as_echo "$as_me: program exited with status $ac_status" >&5
+       $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+       ac_retval=$ac_status
+fi
+  rm -rf conftest.dSYM conftest_ipa8_conftest.oo
+  eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;}
+  as_fn_set_status $ac_retval
+
+} # ac_fn_c_try_run
+

 # ac_fn_c_check_header_compile LINENO HEADER VAR INCLUDES
 # -------------------------------------------------------
 # Tests whether HEADER exists and can be compiled using the include files in
 # ac_fn_c_check_header_compile LINENO HEADER VAR INCLUDES
 # -------------------------------------------------------
 # Tests whether HEADER exists and can be compiled using the include files in


@@ -1869,7 +1879,7 @@ ac_fn_c_check_header_compile ()
   as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }
   as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }

-if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+if eval "test \"\${$3+set}\"" = set; then :

   $as_echo_n "(cached) " >&6
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
   $as_echo_n "(cached) " >&6
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext


@@ -1900,7 +1910,7 @@ ac_fn_c_check_type ()
   as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }
   as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }

-if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+if eval "test \"\${$3+set}\"" = set; then :

   $as_echo_n "(cached) " >&6
 else
   eval "$3=no"
   $as_echo_n "(cached) " >&6
 else
   eval "$3=no"


@@ -1953,7 +1963,7 @@ ac_fn_c_check_func ()
   as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }
   as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
   { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5
 $as_echo_n "checking for $2... " >&6; }

-if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then :
+if eval "test \"\${$3+set}\"" = set; then :

   $as_echo_n "(cached) " >&6
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
   $as_echo_n "(cached) " >&6
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext


@@ -2062,7 +2072,7 @@ This file contains any messages produced by compilers while
 running configure, to aid debugging if configure makes a mistake.
 
 It was created by Valgrind $as_me 3.6.0.SVN, which was
 running configure, to aid debugging if configure makes a mistake.
 
 It was created by Valgrind $as_me 3.6.0.SVN, which was

-generated by GNU Autoconf 2.65.  Invocation command line was
+generated by GNU Autoconf 2.67.  Invocation command line was

 
   $ $0 $@
 
 
   $ $0 $@
 


@@ -2172,11 +2182,9 @@ trap 'exit_status=$?
   {
     echo
 
   {
     echo
 

-    cat <<\_ASBOX
-## ---------------- ##
+    $as_echo "## ---------------- ##

 ## Cache variables. ##
 ## Cache variables. ##

-## ---------------- ##
-_ASBOX
+## ---------------- ##"

     echo
     # The following way of writing the cache mishandles newlines in values,
 (
     echo
     # The following way of writing the cache mishandles newlines in values,
 (


@@ -2210,11 +2218,9 @@ $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
 )
     echo
 
 )
     echo
 

-    cat <<\_ASBOX
-## ----------------- ##
+    $as_echo "## ----------------- ##

 ## Output variables. ##
 ## Output variables. ##

-## ----------------- ##
-_ASBOX
+## ----------------- ##"

     echo
     for ac_var in $ac_subst_vars
     do
     echo
     for ac_var in $ac_subst_vars
     do


@@ -2227,11 +2233,9 @@ _ASBOX
     echo
 
     if test -n "$ac_subst_files"; then
     echo
 
     if test -n "$ac_subst_files"; then

-      cat <<\_ASBOX
-## ------------------- ##
+      $as_echo "## ------------------- ##

 ## File substitutions. ##
 ## File substitutions. ##

-## ------------------- ##
-_ASBOX
+## ------------------- ##"

       echo
       for ac_var in $ac_subst_files
       do
       echo
       for ac_var in $ac_subst_files
       do


@@ -2245,11 +2249,9 @@ _ASBOX
     fi
 
     if test -s confdefs.h; then
     fi
 
     if test -s confdefs.h; then

-      cat <<\_ASBOX
-## ----------- ##
+      $as_echo "## ----------- ##

 ## confdefs.h. ##
 ## confdefs.h. ##

-## ----------- ##
-_ASBOX
+## ----------- ##"

       echo
       cat confdefs.h
       echo
       echo
       cat confdefs.h
       echo


@@ -2304,7 +2306,12 @@ _ACEOF
 ac_site_file1=NONE
 ac_site_file2=NONE
 if test -n "$CONFIG_SITE"; then
 ac_site_file1=NONE
 ac_site_file2=NONE
 if test -n "$CONFIG_SITE"; then

-  ac_site_file1=$CONFIG_SITE
+  # We do not want a PATH search for config.site.
+  case $CONFIG_SITE in #((
+    -*)  ac_site_file1=./$CONFIG_SITE;;
+    */*) ac_site_file1=$CONFIG_SITE;;
+    *)   ac_site_file1=./$CONFIG_SITE;;
+  esac

 elif test "x$prefix" != xNONE; then
   ac_site_file1=$prefix/share/config.site
   ac_site_file2=$prefix/etc/config.site
 elif test "x$prefix" != xNONE; then
   ac_site_file1=$prefix/share/config.site
   ac_site_file2=$prefix/etc/config.site


@@ -2319,7 +2326,11 @@ do
     { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5
 $as_echo "$as_me: loading site script $ac_site_file" >&6;}
     sed 's/^/| /' "$ac_site_file" >&5
     { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5
 $as_echo "$as_me: loading site script $ac_site_file" >&6;}
     sed 's/^/| /' "$ac_site_file" >&5

-    . "$ac_site_file"
+    . "$ac_site_file" \
+      || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "failed to load site script $ac_site_file
+See \`config.log' for more details" "$LINENO" 5 ; }

   fi
 done
 
   fi
 done
 


@@ -2398,7 +2409,7 @@ if $ac_cache_corrupted; then
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
   { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5
 $as_echo "$as_me: error: changes in the environment can compromise the build" >&2;}
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
   { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5
 $as_echo "$as_me: error: changes in the environment can compromise the build" >&2;}

-  as_fn_error "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5
+  as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5

 fi
 ## -------------------- ##
 ## Main body of script. ##
 fi
 ## -------------------- ##
 ## Main body of script. ##


@@ -2418,16 +2429,22 @@ am__api_version='1.11'
 
 ac_aux_dir=
 for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do
 
 ac_aux_dir=
 for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do

-  for ac_t in install-sh install.sh shtool; do
-    if test -f "$ac_dir/$ac_t"; then
-      ac_aux_dir=$ac_dir
-      ac_install_sh="$ac_aux_dir/$ac_t -c"
-      break 2
-    fi
-  done
+  if test -f "$ac_dir/install-sh"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install-sh -c"
+    break
+  elif test -f "$ac_dir/install.sh"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/install.sh -c"
+    break
+  elif test -f "$ac_dir/shtool"; then
+    ac_aux_dir=$ac_dir
+    ac_install_sh="$ac_aux_dir/shtool install -c"
+    break
+  fi

 done
 if test -z "$ac_aux_dir"; then
 done
 if test -z "$ac_aux_dir"; then

-  as_fn_error "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5
+  as_fn_error $? "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5

 fi
 
 # These three variables are undocumented and unsupported,
 fi
 
 # These three variables are undocumented and unsupported,


@@ -2543,11 +2560,11 @@ am_lf='
 '
 case `pwd` in
   *[\\\"\#\$\&\'\`$am_lf]*)
 '
 case `pwd` in
   *[\\\"\#\$\&\'\`$am_lf]*)

-    as_fn_error "unsafe absolute working directory name" "$LINENO" 5;;
+    as_fn_error $? "unsafe absolute working directory name" "$LINENO" 5 ;;

 esac
 case $srcdir in
   *[\\\"\#\$\&\'\`$am_lf\ \    ]*)
 esac
 case $srcdir in
   *[\\\"\#\$\&\'\`$am_lf\ \    ]*)

-    as_fn_error "unsafe srcdir value: \`$srcdir'" "$LINENO" 5;;
+    as_fn_error $? "unsafe srcdir value: \`$srcdir'" "$LINENO" 5 ;;

 esac
 
 # Do `set' in a subshell so we don't clobber the current shell's
 esac
 
 # Do `set' in a subshell so we don't clobber the current shell's


@@ -2569,7 +2586,7 @@ if (
       # if, for instance, CONFIG_SHELL is bash and it inherits a
       # broken ls alias from the environment.  This has actually
       # happened.  Such a system could not be considered "sane".
       # if, for instance, CONFIG_SHELL is bash and it inherits a
       # broken ls alias from the environment.  This has actually
       # happened.  Such a system could not be considered "sane".

-      as_fn_error "ls -t appears to fail.  Make sure there is not a broken
+      as_fn_error $? "ls -t appears to fail.  Make sure there is not a broken

 alias in your environment" "$LINENO" 5
    fi
 
 alias in your environment" "$LINENO" 5
    fi
 


@@ -2579,7 +2596,7 @@ then
    # Ok.
    :
 else
    # Ok.
    :
 else

-   as_fn_error "newly created file is older than distributed files!
+   as_fn_error $? "newly created file is older than distributed files!

 Check your system clock" "$LINENO" 5
 fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
 Check your system clock" "$LINENO" 5
 fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5


@@ -2817,7 +2834,7 @@ done
 $as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; }
 set x ${MAKE-make}
 ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'`
 $as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; }
 set x ${MAKE-make}
 ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'`

-if { as_var=ac_cv_prog_make_${ac_make}_set; eval "test \"\${$as_var+set}\" = set"; }; then :
+if eval "test \"\${ac_cv_prog_make_${ac_make}_set+set}\"" = set; then :

   $as_echo_n "(cached) " >&6
 else
   cat >conftest.make <<\_ACEOF
   $as_echo_n "(cached) " >&6
 else
   cat >conftest.make <<\_ACEOF


@@ -2825,7 +2842,7 @@ SHELL = /bin/sh
 all:
        @echo '@@@%%%=$(MAKE)=@@@%%%'
 _ACEOF
 all:
        @echo '@@@%%%=$(MAKE)=@@@%%%'
 _ACEOF

-# GNU make sometimes prints "make[1]: Entering...", which would confuse us.
+# GNU make sometimes prints "make[1]: Entering ...", which would confuse us.

 case `${MAKE-make} -f conftest.make 2>/dev/null` in
   *@@@%%%=?*=@@@%%%*)
     eval ac_cv_prog_make_${ac_make}_set=yes;;
 case `${MAKE-make} -f conftest.make 2>/dev/null` in
   *@@@%%%=?*=@@@%%%*)
     eval ac_cv_prog_make_${ac_make}_set=yes;;


@@ -2859,7 +2876,7 @@ if test "`cd $srcdir && pwd`" != "`pwd`"; then
   am__isrc=' -I$(srcdir)'
   # test to see if srcdir already configured
   if test -f $srcdir/config.status; then
   am__isrc=' -I$(srcdir)'
   # test to see if srcdir already configured
   if test -f $srcdir/config.status; then

-    as_fn_error "source directory already configured; run \"make distclean\" there first" "$LINENO" 5
+    as_fn_error $? "source directory already configured; run \"make distclean\" there first" "$LINENO" 5

   fi
 fi
 
   fi
 fi
 


@@ -2943,7 +2960,7 @@ fi
 #----------------------------------------------------------------------------
 # Checks for various programs.
 #----------------------------------------------------------------------------
 #----------------------------------------------------------------------------
 # Checks for various programs.
 #----------------------------------------------------------------------------

-CFLAGS="-Wno-long-long"
+CFLAGS="-Wno-long-long $CFLAGS"

 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ln -s works" >&5
 $as_echo_n "checking whether ln -s works... " >&6; }
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ln -s works" >&5
 $as_echo_n "checking whether ln -s works... " >&6; }


@@ -3256,8 +3273,8 @@ fi
 
 test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
 
 test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}

-as_fn_error "no acceptable C compiler found in \$PATH
-See \`config.log' for more details." "$LINENO" 5; }
+as_fn_error $? "no acceptable C compiler found in \$PATH
+See \`config.log' for more details" "$LINENO" 5 ; }

 
 # Provide some information about the compiler.
 $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5
 
 # Provide some information about the compiler.
 $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5


@@ -3371,9 +3388,8 @@ sed 's/^/| /' conftest.$ac_ext >&5
 
 { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
 
 { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}

-{ as_fn_set_status 77
-as_fn_error "C compiler cannot create executables
-See \`config.log' for more details." "$LINENO" 5; }; }
+as_fn_error 77 "C compiler cannot create executables
+See \`config.log' for more details" "$LINENO" 5 ; }

 else
   { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
 $as_echo "yes" >&6; }
 else
   { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
 $as_echo "yes" >&6; }


@@ -3415,8 +3431,8 @@ done
 else
   { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
 else
   { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}

-as_fn_error "cannot compute suffix of executables: cannot compile and link
-See \`config.log' for more details." "$LINENO" 5; }
+as_fn_error $? "cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details" "$LINENO" 5 ; }

 fi
 rm -f conftest conftest$ac_cv_exeext
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5
 fi
 rm -f conftest conftest$ac_cv_exeext
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5


@@ -3473,9 +3489,9 @@ $as_echo "$ac_try_echo"; } >&5
     else
        { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
     else
        { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}

-as_fn_error "cannot run C compiled programs.
+as_fn_error $? "cannot run C compiled programs.

 If you meant to cross compile, use \`--host'.
 If you meant to cross compile, use \`--host'.

-See \`config.log' for more details." "$LINENO" 5; }
+See \`config.log' for more details" "$LINENO" 5 ; }

     fi
   fi
 fi
     fi
   fi
 fi


@@ -3526,8 +3542,8 @@ sed 's/^/| /' conftest.$ac_ext >&5
 
 { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
 
 { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}

-as_fn_error "cannot compute suffix of object files: cannot compile
-See \`config.log' for more details." "$LINENO" 5; }
+as_fn_error $? "cannot compute suffix of object files: cannot compile
+See \`config.log' for more details" "$LINENO" 5 ; }

 fi
 rm -f conftest.$ac_cv_objext conftest.$ac_ext
 fi
 fi
 rm -f conftest.$ac_cv_objext conftest.$ac_ext
 fi


@@ -3945,7 +3961,7 @@ $as_echo_n "checking whether cc understands -c and -o together... " >&6; }
 fi
 set dummy $CC; ac_cc=`$as_echo "$2" |
                      sed 's/[^a-zA-Z0-9_]/_/g;s/^[0-9]/_/'`
 fi
 set dummy $CC; ac_cc=`$as_echo "$2" |
                      sed 's/[^a-zA-Z0-9_]/_/g;s/^[0-9]/_/'`

-if { as_var=ac_cv_prog_cc_${ac_cc}_c_o; eval "test \"\${$as_var+set}\" = set"; }; then :
+if eval "test \"\${ac_cv_prog_cc_${ac_cc}_c_o+set}\"" = set; then :

   $as_echo_n "(cached) " >&6
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
   $as_echo_n "(cached) " >&6
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext


@@ -4104,7 +4120,7 @@ else
   # Broken: fails on valid input.
 continue
 fi
   # Broken: fails on valid input.
 continue
 fi

-rm -f conftest.err conftest.$ac_ext
+rm -f conftest.err conftest.i conftest.$ac_ext

 
   # OK, works on sane cases.  Now check whether nonexistent headers
   # can be detected and how.
 
   # OK, works on sane cases.  Now check whether nonexistent headers
   # can be detected and how.


@@ -4120,11 +4136,11 @@ else
 ac_preproc_ok=:
 break
 fi
 ac_preproc_ok=:
 break
 fi

-rm -f conftest.err conftest.$ac_ext
+rm -f conftest.err conftest.i conftest.$ac_ext

 
 done
 # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
 
 done
 # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.

-rm -f conftest.err conftest.$ac_ext
+rm -f conftest.i conftest.err conftest.$ac_ext

 if $ac_preproc_ok; then :
   break
 fi
 if $ac_preproc_ok; then :
   break
 fi


@@ -4163,7 +4179,7 @@ else
   # Broken: fails on valid input.
 continue
 fi
   # Broken: fails on valid input.
 continue
 fi

-rm -f conftest.err conftest.$ac_ext
+rm -f conftest.err conftest.i conftest.$ac_ext

 
   # OK, works on sane cases.  Now check whether nonexistent headers
   # can be detected and how.
 
   # OK, works on sane cases.  Now check whether nonexistent headers
   # can be detected and how.


@@ -4179,18 +4195,18 @@ else
 ac_preproc_ok=:
 break
 fi
 ac_preproc_ok=:
 break
 fi

-rm -f conftest.err conftest.$ac_ext
+rm -f conftest.err conftest.i conftest.$ac_ext

 
 done
 # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
 
 done
 # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.

-rm -f conftest.err conftest.$ac_ext
+rm -f conftest.i conftest.err conftest.$ac_ext

 if $ac_preproc_ok; then :
 
 else
   { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
 if $ac_preproc_ok; then :
 
 else
   { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}

-as_fn_error "C preprocessor \"$CPP\" fails sanity check
-See \`config.log' for more details." "$LINENO" 5; }
+as_fn_error $? "C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details" "$LINENO" 5 ; }

 fi
 
 ac_ext=c
 fi
 
 ac_ext=c


@@ -4688,11 +4704,83 @@ else
   RANLIB="$ac_cv_prog_RANLIB"
 fi
 
   RANLIB="$ac_cv_prog_RANLIB"
 fi
 

+# provide a very basic definition for AC_PROG_SED if it's not provided by
+# autoconf (as e.g. in autoconf 2.59).
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for a sed that does not truncate output" >&5
+$as_echo_n "checking for a sed that does not truncate output... " >&6; }
+if test "${ac_cv_path_SED+set}" = set; then :
+  $as_echo_n "(cached) " >&6
+else
+            ac_script=s/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/
+     for ac_i in 1 2 3 4 5 6 7; do
+       ac_script="$ac_script$as_nl$ac_script"
+     done
+     echo "$ac_script" 2>/dev/null | sed 99q >conftest.sed
+     { ac_script=; unset ac_script;}
+     if test -z "$SED"; then
+  ac_path_SED_found=false
+  # Loop through the user's path and test for each of PROGNAME-LIST
+  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_prog in sed gsed; do
+    for ac_exec_ext in '' $ac_executable_extensions; do
+      ac_path_SED="$as_dir/$ac_prog$ac_exec_ext"
+      { test -f "$ac_path_SED" && $as_test_x "$ac_path_SED"; } || continue
+# Check for GNU ac_path_SED and select it if it is found.
+  # Check for GNU $ac_path_SED
+case `"$ac_path_SED" --version 2>&1` in
+*GNU*)
+  ac_cv_path_SED="$ac_path_SED" ac_path_SED_found=:;;
+*)
+  ac_count=0
+  $as_echo_n 0123456789 >"conftest.in"
+  while :
+  do
+    cat "conftest.in" "conftest.in" >"conftest.tmp"
+    mv "conftest.tmp" "conftest.in"
+    cp "conftest.in" "conftest.nl"
+    $as_echo '' >> "conftest.nl"
+    "$ac_path_SED" -f conftest.sed < "conftest.nl" >"conftest.out" 2>/dev/null || break
+    diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break
+    as_fn_arith $ac_count + 1 && ac_count=$as_val
+    if test $ac_count -gt ${ac_path_SED_max-0}; then
+      # Best one so far, save it but keep looking for a better one
+      ac_cv_path_SED="$ac_path_SED"
+      ac_path_SED_max=$ac_count
+    fi
+    # 10*(2^10) chars as input seems more than enough
+    test $ac_count -gt 10 && break
+  done
+  rm -f conftest.in conftest.tmp conftest.nl conftest.out;;
+esac
+
+      $ac_path_SED_found && break 3
+    done
+  done
+  done
+IFS=$as_save_IFS
+  if test -z "$ac_cv_path_SED"; then
+    as_fn_error $? "no acceptable sed could be found in \$PATH" "$LINENO" 5
+  fi
+else
+  ac_cv_path_SED=$SED
+fi
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_SED" >&5
+$as_echo "$ac_cv_path_SED" >&6; }
+ SED="$ac_cv_path_SED"
+  rm -f conftest.sed
+

 
 # If no AR variable was specified, look up the name of the archiver. Otherwise
 # do not touch the AR variable.
 if test "x$AR" = "x"; then
 
 # If no AR variable was specified, look up the name of the archiver. Otherwise
 # do not touch the AR variable.
 if test "x$AR" = "x"; then

-  for ac_prog in `echo $LD | sed 's/ld$/ar/'` "ar"
+  for ac_prog in `echo $LD | $SED 's/ld$/ar/'` "ar"

 do
   # Extract the first word of "$ac_prog", so it can be a program name with args.
 set dummy $ac_prog; ac_word=$2
 do
   # Extract the first word of "$ac_prog", so it can be a program name with args.
 set dummy $ac_prog; ac_word=$2


@@ -4743,7 +4831,7 @@ fi
 
 # Check for the compiler support
 if test "${GCC}" != "yes" ; then
 
 # Check for the compiler support
 if test "${GCC}" != "yes" ; then

-   as_fn_error "Valgrind relies on GCC to be compiled" "$LINENO" 5
+   as_fn_error $? "Valgrind relies on GCC to be compiled" "$LINENO" 5

 fi
 
 # figure out where perl lives
 fi
 
 # figure out where perl lives


@@ -4997,13 +5085,13 @@ rm $tmpfile
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a supported version of gcc" >&5
 $as_echo_n "checking for a supported version of gcc... " >&6; }
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a supported version of gcc" >&5
 $as_echo_n "checking for a supported version of gcc... " >&6; }
 

-gcc_version=`${CC} --version | head -n 1 | sed 's/^[^0-9]*\([0-9.]*\).*$/\1/'`
+gcc_version=`${CC} --version | head -n 1 | $SED 's/^[^0-9]*\([0-9.]*\).*$/\1/'`

 
 case "${gcc_version}" in
      2.*)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${gcc_version})" >&5
 $as_echo "no (${gcc_version})" >&6; }
 
 case "${gcc_version}" in
      2.*)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${gcc_version})" >&5
 $as_echo "no (${gcc_version})" >&6; }

-       as_fn_error "please use a recent (>= gcc-3.0) version of gcc" "$LINENO" 5
+       as_fn_error $? "please use a recent (>= gcc-3.0) version of gcc" "$LINENO" 5

        ;;
      *)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${gcc_version})" >&5
        ;;
      *)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${gcc_version})" >&5


@@ -5021,7 +5109,7 @@ esac
 
 # Make sure we can run config.sub.
 $SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 ||
 
 # Make sure we can run config.sub.
 $SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 ||

-  as_fn_error "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5
+  as_fn_error $? "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5

 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5
 $as_echo_n "checking build system type... " >&6; }
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5
 $as_echo_n "checking build system type... " >&6; }


@@ -5032,16 +5120,16 @@ else
 test "x$ac_build_alias" = x &&
   ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"`
 test "x$ac_build_alias" = x &&
 test "x$ac_build_alias" = x &&
   ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"`
 test "x$ac_build_alias" = x &&

-  as_fn_error "cannot guess build type; you must specify one" "$LINENO" 5
+  as_fn_error $? "cannot guess build type; you must specify one" "$LINENO" 5

 ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` ||
 ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` ||

-  as_fn_error "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5
+  as_fn_error $? "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5

 
 fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5
 $as_echo "$ac_cv_build" >&6; }
 case $ac_cv_build in
 *-*-*) ;;
 
 fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5
 $as_echo "$ac_cv_build" >&6; }
 case $ac_cv_build in
 *-*-*) ;;

-*) as_fn_error "invalid value of canonical build" "$LINENO" 5;;
+*) as_fn_error $? "invalid value of canonical build" "$LINENO" 5 ;;

 esac
 build=$ac_cv_build
 ac_save_IFS=$IFS; IFS='-'
 esac
 build=$ac_cv_build
 ac_save_IFS=$IFS; IFS='-'


@@ -5066,7 +5154,7 @@ else
   ac_cv_host=$ac_cv_build
 else
   ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` ||
   ac_cv_host=$ac_cv_build
 else
   ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` ||

-    as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5
+    as_fn_error $? "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5

 fi
 
 fi
 fi
 
 fi


@@ -5074,7 +5162,7 @@ fi
 $as_echo "$ac_cv_host" >&6; }
 case $ac_cv_host in
 *-*-*) ;;
 $as_echo "$ac_cv_host" >&6; }
 case $ac_cv_host in
 *-*-*) ;;

-*) as_fn_error "invalid value of canonical host" "$LINENO" 5;;
+*) as_fn_error $? "invalid value of canonical host" "$LINENO" 5 ;;

 esac
 host=$ac_cv_host
 ac_save_IFS=$IFS; IFS='-'
 esac
 host=$ac_cv_host
 ac_save_IFS=$IFS; IFS='-'


@@ -5142,7 +5230,7 @@ $as_echo "ok (${host_cpu})" >&6; }
      *)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${host_cpu})" >&5
 $as_echo "no (${host_cpu})" >&6; }
      *)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${host_cpu})" >&5
 $as_echo "no (${host_cpu})" >&6; }

-       as_fn_error "Unsupported host architecture. Sorry" "$LINENO" 5
+       as_fn_error $? "Unsupported host architecture. Sorry" "$LINENO" 5

        ;;
 esac
 
        ;;
 esac
 


@@ -5192,7 +5280,7 @@ $as_echo "$vg_cv_only32bit" >&6; }
 
 # Stay sane
 if test x$vg_cv_only64bit = xyes -a x$vg_cv_only32bit = xyes; then
 
 # Stay sane
 if test x$vg_cv_only64bit = xyes -a x$vg_cv_only32bit = xyes; then

-   as_fn_error "Nonsensical: both --enable-only64bit and --enable-only32bit." "$LINENO" 5
+   as_fn_error $? "Nonsensical: both --enable-only64bit and --enable-only32bit." "$LINENO" 5

 fi
 
 #----------------------------------------------------------------------------
 fi
 
 #----------------------------------------------------------------------------


@@ -5239,7 +5327,7 @@ $as_echo "#define KERNEL_2_4 1" >>confdefs.h
              *)
                    { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported (${kernel})" >&5
 $as_echo "unsupported (${kernel})" >&6; }
              *)
                    { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported (${kernel})" >&5
 $as_echo "unsupported (${kernel})" >&6; }

-                   as_fn_error "Valgrind works on kernels 2.4, 2.6" "$LINENO" 5
+                   as_fn_error $? "Valgrind works on kernels 2.4, 2.6" "$LINENO" 5

                    ;;
         esac
 
                    ;;
         esac
 


@@ -5261,12 +5349,6 @@ $as_echo "ok (${host_os})" >&6; }
         VGCONF_OS="aix5"
         ;;
 
         VGCONF_OS="aix5"
         ;;
 

-     *freebsd*)
-        { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${host_os})" >&5
-$as_echo "ok (${host_os})" >&6; }
-        VGCONF_OS="freebsd"
-        ;;
-

      *l4re*)
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${host_os})" >&5
 $as_echo "ok (${host_os})" >&6; }
      *l4re*)
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${host_os})" >&5
 $as_echo "ok (${host_os})" >&6; }


@@ -5278,6 +5360,15 @@ $as_echo "ok (${host_os})" >&6; }
 $as_echo "ok (${host_os})" >&6; }
         VGCONF_OS="darwin"
 
 $as_echo "ok (${host_os})" >&6; }
         VGCONF_OS="darwin"
 

+$as_echo "#define DARWIN_10_5 100500" >>confdefs.h
+
+
+$as_echo "#define DARWIN_10_6 100600" >>confdefs.h
+
+
+$as_echo "#define DARWIN_10_7 100700" >>confdefs.h
+
+

        { $as_echo "$as_me:${as_lineno-$LINENO}: checking for the kernel version" >&5
 $as_echo_n "checking for the kernel version... " >&6; }
        kernel=`uname -r`
        { $as_echo "$as_me:${as_lineno-$LINENO}: checking for the kernel version" >&5
 $as_echo_n "checking for the kernel version... " >&6; }
        kernel=`uname -r`


@@ -5285,9 +5376,8 @@ $as_echo_n "checking for the kernel version... " >&6; }
         # Nb: for Darwin we set DEFAULT_SUPP here.  That's because Darwin
         # has only one relevant version, the OS version. The `uname` check
         # is a good way to get that version (i.e. "Darwin 9.6.0" is Mac OS
         # Nb: for Darwin we set DEFAULT_SUPP here.  That's because Darwin
         # has only one relevant version, the OS version. The `uname` check
         # is a good way to get that version (i.e. "Darwin 9.6.0" is Mac OS

-        # X 10.5.6, and "Darwin 10.x" would presumably be Mac OS X 10.6.x
-        # Snow Leopard and darwin10.supp), and we don't know of an macros
-        # similar to __GLIBC__ to get that info.
+        # X 10.5.6, and "Darwin 10.x" is Mac OS X 10.6.x Snow Leopard),
+        # and we don't know of an macros similar to __GLIBC__ to get that info.

         #
         # XXX: `uname -r` won't do the right thing for cross-compiles, but
         # that's not a problem yet.
         #
         # XXX: `uname -r` won't do the right thing for cross-compiles, but
         # that's not a problem yet.


@@ -5295,13 +5385,25 @@ $as_echo_n "checking for the kernel version... " >&6; }
             9.*)
                  { $as_echo "$as_me:${as_lineno-$LINENO}: result: Darwin 9.x (${kernel}) / Mac OS X 10.5 Leopard" >&5
 $as_echo "Darwin 9.x (${kernel}) / Mac OS X 10.5 Leopard" >&6; }
             9.*)
                  { $as_echo "$as_me:${as_lineno-$LINENO}: result: Darwin 9.x (${kernel}) / Mac OS X 10.5 Leopard" >&5
 $as_echo "Darwin 9.x (${kernel}) / Mac OS X 10.5 Leopard" >&6; }

+
+$as_echo "#define DARWIN_VERS DARWIN_10_5" >>confdefs.h
+

                  DEFAULT_SUPP="darwin9.supp ${DEFAULT_SUPP}"
                  DEFAULT_SUPP="darwin9-drd.supp ${DEFAULT_SUPP}"
                  ;;
                  DEFAULT_SUPP="darwin9.supp ${DEFAULT_SUPP}"
                  DEFAULT_SUPP="darwin9-drd.supp ${DEFAULT_SUPP}"
                  ;;

+            10.*)
+                 { $as_echo "$as_me:${as_lineno-$LINENO}: result: Darwin 10.x (${kernel}) / Mac OS X 10.6 Snow Leopard" >&5
+$as_echo "Darwin 10.x (${kernel}) / Mac OS X 10.6 Snow Leopard" >&6; }
+
+$as_echo "#define DARWIN_VERS DARWIN_10_6" >>confdefs.h
+
+                 DEFAULT_SUPP="darwin10.supp ${DEFAULT_SUPP}"
+                 DEFAULT_SUPP="darwin10-drd.supp ${DEFAULT_SUPP}"
+                 ;;

      *)
                  { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported (${kernel})" >&5
 $as_echo "unsupported (${kernel})" >&6; }
      *)
                  { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported (${kernel})" >&5
 $as_echo "unsupported (${kernel})" >&6; }

-                 as_fn_error "Valgrind works on Darwin 9.x (Mac OS X 10.5)" "$LINENO" 5
+                 as_fn_error $? "Valgrind works on Darwin 9.x and 10.x (Mac OS X 10.5 and 10.6)" "$LINENO" 5

                  ;;
        esac
         ;;
                  ;;
        esac
         ;;


@@ -5309,7 +5411,7 @@ $as_echo "unsupported (${kernel})" >&6; }
      *)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${host_os})" >&5
 $as_echo "no (${host_os})" >&6; }
      *)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${host_os})" >&5
 $as_echo "no (${host_os})" >&6; }

-       as_fn_error "Valgrind is operating system specific. Sorry. Please consider doing a port." "$LINENO" 5
+       as_fn_error $? "Valgrind is operating system specific. Sorry." "$LINENO" 5

        ;;
 esac
 
        ;;
 esac
 


@@ -5357,7 +5459,7 @@ rm -f core conftest.err conftest.$ac_objext \
 esac
 
 if test x$vg_cv_only64bit = xyes -a x$vg_cv_only32bit = xyes; then
 esac
 
 if test x$vg_cv_only64bit = xyes -a x$vg_cv_only32bit = xyes; then

-   as_fn_error "--enable-only32bit was specified but system does not support 32 bit builds" "$LINENO" 5
+   as_fn_error $? "--enable-only32bit was specified but system does not support 32 bit builds" "$LINENO" 5

 fi
 
 #----------------------------------------------------------------------------
 fi
 
 #----------------------------------------------------------------------------


@@ -5400,36 +5502,53 @@ fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a supported CPU/OS combination" >&5
 $as_echo_n "checking for a supported CPU/OS combination... " >&6; }
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a supported CPU/OS combination" >&5
 $as_echo_n "checking for a supported CPU/OS combination... " >&6; }
 

+# NB.  The load address for a given platform may be specified in more
+# than one place, in some cases, depending on whether we're doing a biarch,
+# 32-bit only or 64-bit only build.  eg see case for amd64-linux below.
+# Be careful to give consistent values in all subcases.  Also, all four
+# valt_load_addres_{pri,sec}_{norml,inner} values must always be set,
+# even if it is to "0xUNSET".
+#

 case "$ARCH_MAX-$VGCONF_OS" in
      x86-linux)
 case "$ARCH_MAX-$VGCONF_OS" in
      x86-linux)

-               VGCONF_ARCH_PRI="x86"
-               VGCONF_ARCH_SEC=""
-       VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
-       VGCONF_PLATFORM_SEC_CAPS=""
-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"
+        VGCONF_ARCH_PRI="x86"
+        VGCONF_ARCH_SEC=""
+        VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
+        VGCONF_PLATFORM_SEC_CAPS=""
+        valt_load_address_pri_norml="0x38000000"
+        valt_load_address_pri_inner="0x28000000"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
      amd64-linux)
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
      amd64-linux)

+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""
        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        elif test x$vg_cv_only32bit = xyes; then
           VGCONF_ARCH_PRI="x86"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""
        elif test x$vg_cv_only32bit = xyes; then
           VGCONF_ARCH_PRI="x86"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        else
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC="x86"
           VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS="X86_LINUX"
        else
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC="x86"
           VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS="X86_LINUX"

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"
+           valt_load_address_sec_norml="0x38000000"
+           valt_load_address_sec_inner="0x28000000"

        fi
        fi

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"

         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;


@@ -5438,12 +5557,18 @@ $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
         VGCONF_ARCH_SEC=""
        VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
        VGCONF_PLATFORM_SEC_CAPS=""
         VGCONF_ARCH_SEC=""
        VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
        VGCONF_PLATFORM_SEC_CAPS=""

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"
+        valt_load_address_pri_norml="0x38000000"
+        valt_load_address_pri_inner="0x28000000"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
      ppc64-aix5)
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
      ppc64-aix5)

+        valt_load_address_pri_norml="0xUNSET"
+        valt_load_address_pri_inner="0xUNSET"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC=""
        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC=""


@@ -5460,30 +5585,36 @@ $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
           VGCONF_PLATFORM_PRI_CAPS="PPC64_AIX5"
           VGCONF_PLATFORM_SEC_CAPS="PPC32_AIX5"
        fi
           VGCONF_PLATFORM_PRI_CAPS="PPC64_AIX5"
           VGCONF_PLATFORM_SEC_CAPS="PPC32_AIX5"
        fi

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"

         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
      ppc64-linux)
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
      ppc64-linux)

+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        if test x$vg_cv_only64bit = xyes; then
           VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""
        if test x$vg_cv_only64bit = xyes; then
           VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        elif test x$vg_cv_only32bit = xyes; then
           VGCONF_ARCH_PRI="ppc32"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""
        elif test x$vg_cv_only32bit = xyes; then
           VGCONF_ARCH_PRI="ppc32"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        else
           VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC="ppc32"
           VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"
        else
           VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC="ppc32"
           VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"
+           valt_load_address_sec_norml="0x38000000"
+           valt_load_address_sec_inner="0x28000000"

        fi
        fi

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"

         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;


@@ -5492,41 +5623,47 @@ $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
                VGCONF_ARCH_SEC=""
                VGCONF_PLATFORM_PRI_CAPS="X86_L4RE"
                VGCONF_PLATFORM_SEC_CAPS=""
                VGCONF_ARCH_SEC=""
                VGCONF_PLATFORM_PRI_CAPS="X86_L4RE"
                VGCONF_PLATFORM_SEC_CAPS=""

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"
+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"
+           valt_load_address_sec_norml="0x38000000"
+           valt_load_address_sec_inner="0x28000000"

         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
         ;;
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
         ;;

-     x86-darwin)
-        VGCONF_ARCH_PRI="x86"
-        VGCONF_ARCH_SEC=""
-       VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
-       VGCONF_PLATFORM_SEC_CAPS=""
-        valt_load_address_normal="0x0"
-        valt_load_address_inner="0x0"
-        { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
-$as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
-       ;;
-     amd64-darwin)
+     # Darwin gets identified as 32-bit even when it supports 64-bit.
+     # (Not sure why, possibly because 'uname' returns "i386"?)  Just about
+     # all Macs support both 32-bit and 64-bit, so we just build both.  If
+     # someone has a really old 32-bit only machine they can (hopefully?)
+     # build with --enable-only32bit.  See bug 243362.
+     x86-darwin|amd64-darwin)
+        ARCH_MAX="amd64"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS=""
        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x138000000"
+           valt_load_address_pri_inner="0x128000000"

        elif test x$vg_cv_only32bit = xyes; then
            VGCONF_ARCH_PRI="x86"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS=""
           VGCONF_ARCH_PRI_CAPS="x86"
        elif test x$vg_cv_only32bit = xyes; then
            VGCONF_ARCH_PRI="x86"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS=""
           VGCONF_ARCH_PRI_CAPS="x86"

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        else
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC="x86"
           VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS="X86_DARWIN"
        else
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC="x86"
           VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS="X86_DARWIN"

+           valt_load_address_pri_norml="0x138000000"
+           valt_load_address_pri_inner="0x128000000"
+           valt_load_address_sec_norml="0x38000000"
+           valt_load_address_sec_inner="0x28000000"

        fi
        fi

-        valt_load_address_normal="0x0"
-        valt_load_address_inner="0x0"

         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        ;;


@@ -5534,8 +5671,10 @@ $as_echo "ok (${ARCH_MAX}-${VGCONF_OS})" >&6; }
        VGCONF_ARCH_PRI="arm"
        VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
        VGCONF_PLATFORM_SEC_CAPS=""
        VGCONF_ARCH_PRI="arm"
        VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
        VGCONF_PLATFORM_SEC_CAPS=""

-       valt_load_address_normal="0x38000000"
-       valt_load_address_inner="0x28000000"
+       valt_load_address_pri_norml="0x38000000"
+       valt_load_address_pri_inner="0x28000000"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${host_cpu}-${host_os})" >&5
 $as_echo "ok (${host_cpu}-${host_os})" >&6; }
        ;;
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok (${host_cpu}-${host_os})" >&5
 $as_echo "ok (${host_cpu}-${host_os})" >&6; }
        ;;


@@ -5544,9 +5683,13 @@ $as_echo "ok (${host_cpu}-${host_os})" >&6; }
         VGCONF_ARCH_SEC="unknown"
        VGCONF_PLATFORM_PRI_CAPS="UNKNOWN"
        VGCONF_PLATFORM_SEC_CAPS="UNKNOWN"
         VGCONF_ARCH_SEC="unknown"
        VGCONF_PLATFORM_PRI_CAPS="UNKNOWN"
        VGCONF_PLATFORM_SEC_CAPS="UNKNOWN"

+        valt_load_address_pri_norml="0xUNSET"
+        valt_load_address_pri_inner="0xUNSET"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

         { $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "no (${ARCH_MAX}-${VGCONF_OS})" >&6; }
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: no (${ARCH_MAX}-${VGCONF_OS})" >&5
 $as_echo "no (${ARCH_MAX}-${VGCONF_OS})" >&6; }

-        as_fn_error "Valgrind is platform specific. Sorry. Please consider doing a port." "$LINENO" 5
+        as_fn_error $? "Valgrind is platform specific. Sorry. Please consider doing a port." "$LINENO" 5

         ;;
 esac
 
         ;;
 esac
 


@@ -5693,7 +5836,7 @@ fi
 
 
 
 
 
 

-# Similarly, set up VGCONF_OF_IS_<os>.  Exactly one of these becomes defined.
+# Similarly, set up VGCONF_OS_IS_<os>.  Exactly one of these becomes defined.

 # Relies on the assumption that the primary and secondary targets are
 # for the same OS, so therefore only necessary to test the primary.
  if test x$VGCONF_PLATFORM_PRI_CAPS = xX86_LINUX \
 # Relies on the assumption that the primary and secondary targets are
 # for the same OS, so therefore only necessary to test the primary.
  if test x$VGCONF_PLATFORM_PRI_CAPS = xX86_LINUX \


@@ -5755,6 +5898,7 @@ fi
 # Check if this should be built as an inner Valgrind, to be run within
 # another Valgrind.  Choose the load address accordingly.
 
 # Check if this should be built as an inner Valgrind, to be run within
 # another Valgrind.  Choose the load address accordingly.
 

+

 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for use as an inner Valgrind" >&5
 $as_echo_n "checking for use as an inner Valgrind... " >&6; }
 if test "${vg_cv_inner+set}" = set; then :
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for use as an inner Valgrind" >&5
 $as_echo_n "checking for use as an inner Valgrind... " >&6; }
 if test "${vg_cv_inner+set}" = set; then :


@@ -5774,9 +5918,11 @@ if test "$vg_cv_inner" = yes; then
 
 $as_echo "#define ENABLE_INNER 1" >>confdefs.h
 
 
 $as_echo "#define ENABLE_INNER 1" >>confdefs.h
 

-    VALT_LOAD_ADDRESS=$valt_load_address_inner
+    VALT_LOAD_ADDRESS_PRI=$valt_load_address_pri_inner
+    VALT_LOAD_ADDRESS_SEC=$valt_load_address_sec_inner

 else
 else

-    VALT_LOAD_ADDRESS=$valt_load_address_normal
+    VALT_LOAD_ADDRESS_PRI=$valt_load_address_pri_norml
+    VALT_LOAD_ADDRESS_SEC=$valt_load_address_sec_norml

 fi
 
 
 fi
 
 


@@ -5789,8 +5935,6 @@ fi
 # glibcs >= 2.7)
 
 
 # glibcs >= 2.7)
 
 

-GLIBC_VERSION=""
-

 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5
 $as_echo_n "checking for grep that handles long lines and -e... " >&6; }
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5
 $as_echo_n "checking for grep that handles long lines and -e... " >&6; }


@@ -5843,7 +5987,7 @@ esac
   done
 IFS=$as_save_IFS
   if test -z "$ac_cv_path_GREP"; then
   done
 IFS=$as_save_IFS
   if test -z "$ac_cv_path_GREP"; then

-    as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5
+    as_fn_error $? "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5

   fi
 else
   ac_cv_path_GREP=$GREP
   fi
 else
   ac_cv_path_GREP=$GREP


@@ -5909,7 +6053,7 @@ esac
   done
 IFS=$as_save_IFS
   if test -z "$ac_cv_path_EGREP"; then
   done
 IFS=$as_save_IFS
   if test -z "$ac_cv_path_EGREP"; then

-    as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5
+    as_fn_error $? "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5

   fi
 else
   ac_cv_path_EGREP=$EGREP
   fi
 else
   ac_cv_path_EGREP=$EGREP


@@ -5922,185 +6066,152 @@ $as_echo "$ac_cv_path_EGREP" >&6; }
  EGREP="$ac_cv_path_EGREP"
 
 
  EGREP="$ac_cv_path_EGREP"
 
 

-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5
+$as_echo_n "checking for ANSI C header files... " >&6; }
+if test "${ac_cv_header_stdc+set}" = set; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext

 /* end confdefs.h.  */
 /* end confdefs.h.  */

+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>

 
 

-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 2)
-  GLIBC_22
- #endif
-#endif
+int
+main ()
+{

 
 

+  ;
+  return 0;
+}

 _ACEOF
 _ACEOF

-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "GLIBC_22" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.2"
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_cv_header_stdc=yes
+else
+  ac_cv_header_stdc=no

 fi
 fi

-rm -f conftest*
-
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext

 
 

-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+if test $ac_cv_header_stdc = yes; then
+  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext

 /* end confdefs.h.  */
 /* end confdefs.h.  */

-
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 3)
-  GLIBC_23
- #endif
-#endif
+#include <string.h>

 
 _ACEOF
 if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
 
 _ACEOF
 if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |

-  $EGREP "GLIBC_23" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.3"
-fi
-rm -f conftest*
-
-
-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */
-
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 4)
-  GLIBC_24
- #endif
-#endif
+  $EGREP "memchr" >/dev/null 2>&1; then :

 
 

-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "GLIBC_24" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.4"
+else
+  ac_cv_header_stdc=no

 fi
 rm -f conftest*
 
 fi
 rm -f conftest*
 

-
-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */
-
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 5)
-  GLIBC_25
- #endif
-#endif
-
-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "GLIBC_25" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.5"

 fi
 fi

-rm -f conftest*

 
 

-
-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+if test $ac_cv_header_stdc = yes; then
+  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext

 /* end confdefs.h.  */
 /* end confdefs.h.  */

-
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 6)
-  GLIBC_26
- #endif
-#endif
+#include <stdlib.h>

 
 _ACEOF
 if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
 
 _ACEOF
 if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |

-  $EGREP "GLIBC_26" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.6"
-fi
-rm -f conftest*
-
-
-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */
-
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 7)
-  GLIBC_27
- #endif
-#endif
+  $EGREP "free" >/dev/null 2>&1; then :

 
 

-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "GLIBC_27" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.7"
+else
+  ac_cv_header_stdc=no

 fi
 rm -f conftest*
 
 fi
 rm -f conftest*
 

+fi

 
 

-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+if test $ac_cv_header_stdc = yes; then
+  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+  if test "$cross_compiling" = yes; then :
+  :
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext

 /* end confdefs.h.  */
 /* end confdefs.h.  */

-
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 8)
-  GLIBC_28
- #endif
+#include <ctype.h>
+#include <stdlib.h>
+#if ((' ' & 0x0FF) == 0x020)
+# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#else
+# define ISLOWER(c) \
+                  (('a' <= (c) && (c) <= 'i') \
+                    || ('j' <= (c) && (c) <= 'r') \
+                    || ('s' <= (c) && (c) <= 'z'))
+# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))

 #endif
 
 #endif
 

+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int
+main ()
+{
+  int i;
+  for (i = 0; i < 256; i++)
+    if (XOR (islower (i), ISLOWER (i))
+       || toupper (i) != TOUPPER (i))
+      return 2;
+  return 0;
+}

 _ACEOF
 _ACEOF

-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "GLIBC_28" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.8"
+if ac_fn_c_try_run "$LINENO"; then :
+
+else
+  ac_cv_header_stdc=no
+fi
+rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \
+  conftest.$ac_objext conftest.beam conftest.$ac_ext

 fi
 fi

-rm -f conftest*

 
 

+fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5
+$as_echo "$ac_cv_header_stdc" >&6; }
+if test $ac_cv_header_stdc = yes; then

 
 

-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */
+$as_echo "#define STDC_HEADERS 1" >>confdefs.h

 
 

-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 9)
-  GLIBC_29
- #endif
-#endif
+fi

 
 

+# On IRIX 5.3, sys/types and inttypes.h are conflicting.
+for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
+                 inttypes.h stdint.h unistd.h
+do :
+  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
+ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default
+"
+if eval test \"x\$"$as_ac_Header"\" = x"yes"; then :
+  cat >>confdefs.h <<_ACEOF
+#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1

 _ACEOF
 _ACEOF

-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "GLIBC_29" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.9"
+

 fi
 fi

-rm -f conftest*

 
 

+done

 
 

-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */

 
 

-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 10)
-  GLIBC_210
- #endif
-#endif
+ac_fn_c_check_header_mongrel "$LINENO" "features.h" "ac_cv_header_features_h" "$ac_includes_default"
+if test "x$ac_cv_header_features_h" = x""yes; then :

 
 

-_ACEOF
-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "GLIBC_210" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.10"

 fi
 fi

-rm -f conftest*

 
 
 
 

-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */

 
 

+if test x$ac_cv_header_features_h = xyes; then
+  rm -f conftest.$ac_ext
+  cat <<_ACEOF >conftest.$ac_ext

 #include <features.h>
 #include <features.h>

-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 11)
-  GLIBC_211
- #endif
+#if defined(__GNU_LIBRARY__) && defined(__GLIBC__) && defined(__GLIBC_MINOR__)
+glibc version is: __GLIBC__ __GLIBC_MINOR__

 #endif
 #endif

-

 _ACEOF
 _ACEOF

-if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
-  $EGREP "GLIBC_211" >/dev/null 2>&1; then :
-  GLIBC_VERSION="2.11"
+  GLIBC_VERSION="`$CPP conftest.$ac_ext | $SED -n 's/^glibc version is: //p' | $SED 's/ /./g'`"

 fi
 fi

-rm -f conftest*
-

 
 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 
 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */


@@ -6241,6 +6352,16 @@ $as_echo "#define GLIBC_2_11 1" >>confdefs.h
        GENERATED_SUPP="glibc-2.X.supp ${GENERATED_SUPP}"
        DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}"
        DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}"
        GENERATED_SUPP="glibc-2.X.supp ${GENERATED_SUPP}"
        DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}"
        DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}"

+        ;;
+     2.12)
+       { $as_echo "$as_me:${as_lineno-$LINENO}: result: 2.12 family" >&5
+$as_echo "2.12 family" >&6; }
+
+$as_echo "#define GLIBC_2_12 1" >>confdefs.h
+
+       DEFAULT_SUPP="glibc-2.X.supp ${DEFAULT_SUPP}"
+       DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}"
+       DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}"

        ;;
      aix5)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: AIX 5.1 or 5.2 or 5.3" >&5
        ;;
      aix5)
        { $as_echo "$as_me:${as_lineno-$LINENO}: result: AIX 5.1 or 5.2 or 5.3" >&5


@@ -6260,11 +6381,11 @@ $as_echo "#define DARWIN_LIBC 1" >>confdefs.h
        ;;
 
      *)
        ;;
 
      *)

-       { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported version" >&5
-$as_echo "unsupported version" >&6; }
-       as_fn_error "Valgrind requires glibc version 2.2 - 2.11" "$LINENO" 5
-       as_fn_error "or AIX 5.1 or 5.2 or 5.3 GLIBC_VERSION" "$LINENO" 5
-       as_fn_error "or Darwin libc" "$LINENO" 5
+       { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported version ${GLIBC_VERSION}" >&5
+$as_echo "unsupported version ${GLIBC_VERSION}" >&6; }
+       as_fn_error $? "Valgrind requires glibc version 2.2 - 2.12" "$LINENO" 5
+       as_fn_error $? "or AIX 5.1 or 5.2 or 5.3 GLIBC_VERSION" "$LINENO" 5
+       as_fn_error $? "or Darwin libc" "$LINENO" 5

        ;;
 esac
 
        ;;
 esac
 


@@ -7304,6 +7425,48 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
 CFLAGS=$safe_CFLAGS
 
 
 CFLAGS=$safe_CFLAGS
 
 

+# does the linker support -Wl,--build-id=none ?  Note, it's
+# important that we test indirectly via whichever C compiler
+# is selected, rather than testing /usr/bin/ld or whatever
+# directly.
+
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker accepts -Wl,--build-id=none" >&5
+$as_echo_n "checking if the linker accepts -Wl,--build-id=none... " >&6; }
+
+safe_CFLAGS=$CFLAGS
+CFLAGS="-Wl,--build-id=none"
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+return 0;
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"; then :
+
+  FLAG_NO_BUILD_ID="-Wl,--build-id=none"
+
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+
+else
+
+  FLAG_NO_BUILD_ID=""
+
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+
+fi
+rm -f core conftest.err conftest.$ac_objext \
+    conftest$ac_exeext conftest.$ac_ext
+CFLAGS=$safe_CFLAGS
+
+

 # does the ppc assembler support "mtocrf" et al?
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ppc32/64 as supports mtocrf/mfocrf" >&5
 $as_echo_n "checking if ppc32/64 as supports mtocrf/mfocrf... " >&6; }
 # does the ppc assembler support "mtocrf" et al?
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking if ppc32/64 as supports mtocrf/mfocrf" >&5
 $as_echo_n "checking if ppc32/64 as supports mtocrf/mfocrf... " >&6; }


@@ -7453,8 +7616,8 @@ else
   if test "$cross_compiling" = yes; then :
   { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
   if test "$cross_compiling" = yes; then :
   { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}

-as_fn_error "cannot run test program while cross compiling
-See \`config.log' for more details." "$LINENO" 5; }
+as_fn_error $? "cannot run test program while cross compiling
+See \`config.log' for more details" "$LINENO" 5 ; }

 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */
 else
   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
 /* end confdefs.h.  */


@@ -7640,24 +7803,6 @@ $as_echo "#define STDC_HEADERS 1" >>confdefs.h
 
 fi
 
 
 fi
 

-# On IRIX 5.3, sys/types and inttypes.h are conflicting.
-for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
-                 inttypes.h stdint.h unistd.h
-do :
-  as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
-ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default
-"
-eval as_val=\$$as_ac_Header
-   if test "x$as_val" = x""yes; then :
-  cat >>confdefs.h <<_ACEOF
-#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
-_ACEOF
-
-fi
-
-done
-
-

 for ac_header in        \
         asm/unistd.h     \
         endian.h         \
 for ac_header in        \
         asm/unistd.h     \
         endian.h         \


@@ -7676,8 +7821,7 @@ for ac_header in        \
 do :
   as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
 ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"
 do :
   as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
 ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default"

-eval as_val=\$$as_ac_Header
-   if test "x$as_val" = x""yes; then :
+if eval test \"x\$"$as_ac_Header"\" = x"yes"; then :

   cat >>confdefs.h <<_ACEOF
 #define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
 _ACEOF
   cat >>confdefs.h <<_ACEOF
 #define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
 _ACEOF


@@ -7852,8 +7996,7 @@ do :
   as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
 ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default
 "
   as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh`
 ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default
 "

-eval as_val=\$$as_ac_Header
-   if test "x$as_val" = x""yes; then :
+if eval test \"x\$"$as_ac_Header"\" = x"yes"; then :

   cat >>confdefs.h <<_ACEOF
 #define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
 _ACEOF
   cat >>confdefs.h <<_ACEOF
 #define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1
 _ACEOF


@@ -8160,8 +8303,7 @@ for ac_func in      \
 do :
   as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
 ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"
 do :
   as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh`
 ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var"

-eval as_val=\$$as_ac_var
-   if test "x$as_val" = x""yes; then :
+if eval test \"x\$"$as_ac_var"\" = x"yes"; then :

   cat >>confdefs.h <<_ACEOF
 #define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
 _ACEOF
   cat >>confdefs.h <<_ACEOF
 #define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1
 _ACEOF


@@ -8397,6 +8539,10 @@ fi
 
 
 
 
 
 

+
+
+
+

 if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
        if test -n "$ac_tool_prefix"; then
   # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args.
 if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then
        if test -n "$ac_tool_prefix"; then
   # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args.


@@ -8509,7 +8655,6 @@ $as_echo "yes" >&6; }
 $as_echo "no" >&6; }
                PKG_CONFIG=""
        fi
 $as_echo "no" >&6; }
                PKG_CONFIG=""
        fi

-

 fi
 
 if test -n "$PKG_CONFIG" && \
 fi
 
 if test -n "$PKG_CONFIG" && \


@@ -8524,11 +8669,10 @@ pkg_failed=no
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for QTCORE" >&5
 $as_echo_n "checking for QTCORE... " >&6; }
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for QTCORE" >&5
 $as_echo_n "checking for QTCORE... " >&6; }
 

-if test -n "$PKG_CONFIG"; then
-    if test -n "$QTCORE_CFLAGS"; then
-        pkg_cv_QTCORE_CFLAGS="$QTCORE_CFLAGS"
-    else
-        if test -n "$PKG_CONFIG" && \
+if test -n "$QTCORE_CFLAGS"; then
+    pkg_cv_QTCORE_CFLAGS="$QTCORE_CFLAGS"
+ elif test -n "$PKG_CONFIG"; then
+    if test -n "$PKG_CONFIG" && \

     { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"QtCore\""; } >&5
   ($PKG_CONFIG --exists --print-errors "QtCore") 2>&5
   ac_status=$?
     { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"QtCore\""; } >&5
   ($PKG_CONFIG --exists --print-errors "QtCore") 2>&5
   ac_status=$?


@@ -8538,15 +8682,13 @@ if test -n "$PKG_CONFIG"; then
 else
   pkg_failed=yes
 fi
 else
   pkg_failed=yes
 fi

-    fi
-else
-       pkg_failed=untried
+ else
+    pkg_failed=untried

 fi
 fi

-if test -n "$PKG_CONFIG"; then
-    if test -n "$QTCORE_LIBS"; then
-        pkg_cv_QTCORE_LIBS="$QTCORE_LIBS"
-    else
-        if test -n "$PKG_CONFIG" && \
+if test -n "$QTCORE_LIBS"; then
+    pkg_cv_QTCORE_LIBS="$QTCORE_LIBS"
+ elif test -n "$PKG_CONFIG"; then
+    if test -n "$PKG_CONFIG" && \

     { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"QtCore\""; } >&5
   ($PKG_CONFIG --exists --print-errors "QtCore") 2>&5
   ac_status=$?
     { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"QtCore\""; } >&5
   ($PKG_CONFIG --exists --print-errors "QtCore") 2>&5
   ac_status=$?


@@ -8556,14 +8698,15 @@ if test -n "$PKG_CONFIG"; then
 else
   pkg_failed=yes
 fi
 else
   pkg_failed=yes
 fi

-    fi
-else
-       pkg_failed=untried
+ else
+    pkg_failed=untried

 fi
 
 
 
 if test $pkg_failed = yes; then
 fi
 
 
 
 if test $pkg_failed = yes; then

+       { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }

 
 if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then
         _pkg_short_errors_supported=yes
 
 if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then
         _pkg_short_errors_supported=yes


@@ -8571,14 +8714,14 @@ else
         _pkg_short_errors_supported=no
 fi
         if test $_pkg_short_errors_supported = yes; then
         _pkg_short_errors_supported=no
 fi
         if test $_pkg_short_errors_supported = yes; then

-               QTCORE_PKG_ERRORS=`$PKG_CONFIG --short-errors --errors-to-stdout --print-errors "QtCore"`
+               QTCORE_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors "QtCore" 2>&1`

         else
         else

-               QTCORE_PKG_ERRORS=`$PKG_CONFIG --errors-to-stdout --print-errors "QtCore"`
+               QTCORE_PKG_ERRORS=`$PKG_CONFIG --print-errors "QtCore" 2>&1`

         fi
        # Put the nasty error message in config.log where it belongs
        echo "$QTCORE_PKG_ERRORS" >&5
 
         fi
        # Put the nasty error message in config.log where it belongs
        echo "$QTCORE_PKG_ERRORS" >&5
 

-       as_fn_error "Package requirements (QtCore) were not met:
+       as_fn_error $? "Package requirements (QtCore) were not met:

 
 $QTCORE_PKG_ERRORS
 
 
 $QTCORE_PKG_ERRORS
 


@@ -8587,12 +8730,13 @@ installed software in a non-standard prefix.
 
 Alternatively, you may set the environment variables QTCORE_CFLAGS
 and QTCORE_LIBS to avoid the need to call pkg-config.
 
 Alternatively, you may set the environment variables QTCORE_CFLAGS
 and QTCORE_LIBS to avoid the need to call pkg-config.

-See the pkg-config man page for more details.
-" "$LINENO" 5
+See the pkg-config man page for more details." "$LINENO" 5

 elif test $pkg_failed = untried; then
 elif test $pkg_failed = untried; then

+       { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }

        { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
        { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;}

-as_fn_error "The pkg-config script could not be found or is too old.  Make sure it
+as_fn_error $? "The pkg-config script could not be found or is too old.  Make sure it

 is in your PATH or set the PKG_CONFIG environment variable to the full
 path to pkg-config.
 
 is in your PATH or set the PKG_CONFIG environment variable to the full
 path to pkg-config.
 


@@ -8601,13 +8745,13 @@ and QTCORE_LIBS to avoid the need to call pkg-config.
 See the pkg-config man page for more details.
 
 To get pkg-config, see <http://pkg-config.freedesktop.org/>.
 See the pkg-config man page for more details.
 
 To get pkg-config, see <http://pkg-config.freedesktop.org/>.

-See \`config.log' for more details." "$LINENO" 5; }
+See \`config.log' for more details" "$LINENO" 5 ; }

 else
        QTCORE_CFLAGS=$pkg_cv_QTCORE_CFLAGS
        QTCORE_LIBS=$pkg_cv_QTCORE_LIBS
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
 $as_echo "yes" >&6; }
 else
        QTCORE_CFLAGS=$pkg_cv_QTCORE_CFLAGS
        QTCORE_LIBS=$pkg_cv_QTCORE_LIBS
         { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
 $as_echo "yes" >&6; }

-       :
+

 fi
       # Paranoia: don't trust the result reported by pkg-config, but when
       # pkg-config reports that QtCore has been found, verify whether linking
 fi
       # Paranoia: don't trust the result reported by pkg-config, but when
       # pkg-config reports that QtCore has been found, verify whether linking


@@ -8956,7 +9100,15 @@ fi
 #----------------------------------------------------------------------------
 
 # Nb: VEX/Makefile is generated from Makefile.vex.in.
 #----------------------------------------------------------------------------
 
 # Nb: VEX/Makefile is generated from Makefile.vex.in.

-ac_config_files="$ac_config_files Makefile VEX/Makefile:Makefile.vex.in valgrind.spec valgrind.pc glibc-2.X.supp docs/Makefile tests/Makefile tests/vg_regtest perf/Makefile perf/vg_perf include/Makefile auxprogs/Makefile mpi/Makefile coregrind/Makefile memcheck/Makefile memcheck/tests/Makefile memcheck/tests/amd64/Makefile memcheck/tests/x86/Makefile memcheck/tests/linux/Makefile memcheck/tests/darwin/Makefile memcheck/tests/x86-linux/Makefile memcheck/perf/Makefile cachegrind/Makefile cachegrind/tests/Makefile cachegrind/tests/x86/Makefile cachegrind/cg_annotate callgrind/Makefile callgrind/callgrind_annotate callgrind/callgrind_control callgrind/tests/Makefile helgrind/Makefile helgrind/tests/Makefile massif/Makefile massif/tests/Makefile massif/perf/Makefile massif/ms_print lackey/Makefile lackey/tests/Makefile none/Makefile none/tests/Makefile none/tests/amd64/Makefile none/tests/ppc32/Makefile none/tests/ppc64/Makefile none/tests/x86/Makefile none/tests/arm/Makefile none/tests/linux/Makefile none/tests/darwin/Makefile none/tests/x86-linux/Makefile exp-ptrcheck/Makefile exp-ptrcheck/tests/Makefile drd/Makefile drd/scripts/download-and-build-splash2 drd/tests/Makefile exp-bbv/Makefile exp-bbv/tests/Makefile exp-bbv/tests/x86/Makefile exp-bbv/tests/x86-linux/Makefile exp-bbv/tests/amd64-linux/Makefile exp-bbv/tests/ppc32-linux/Makefile"
+ac_config_files="$ac_config_files Makefile VEX/Makefile:Makefile.vex.in valgrind.spec valgrind.pc glibc-2.X.supp docs/Makefile tests/Makefile tests/vg_regtest perf/Makefile perf/vg_perf include/Makefile auxprogs/Makefile mpi/Makefile coregrind/Makefile memcheck/Makefile memcheck/tests/Makefile memcheck/tests/amd64/Makefile memcheck/tests/x86/Makefile memcheck/tests/linux/Makefile memcheck/tests/darwin/Makefile memcheck/tests/amd64-linux/Makefile memcheck/tests/x86-linux/Makefile memcheck/perf/Makefile cachegrind/Makefile cachegrind/tests/Makefile cachegrind/tests/x86/Makefile cachegrind/cg_annotate cachegrind/cg_diff callgrind/Makefile callgrind/callgrind_annotate callgrind/callgrind_control callgrind/tests/Makefile helgrind/Makefile helgrind/tests/Makefile massif/Makefile massif/tests/Makefile massif/perf/Makefile massif/ms_print lackey/Makefile lackey/tests/Makefile none/Makefile none/tests/Makefile none/tests/amd64/Makefile none/tests/ppc32/Makefile none/tests/ppc64/Makefile none/tests/x86/Makefile none/tests/arm/Makefile none/tests/linux/Makefile none/tests/darwin/Makefile none/tests/x86-linux/Makefile exp-ptrcheck/Makefile exp-ptrcheck/tests/Makefile drd/Makefile drd/scripts/download-and-build-splash2 drd/tests/Makefile exp-bbv/Makefile exp-bbv/tests/Makefile exp-bbv/tests/x86/Makefile exp-bbv/tests/x86-linux/Makefile exp-bbv/tests/amd64-linux/Makefile exp-bbv/tests/ppc32-linux/Makefile"
+
+ac_config_files="$ac_config_files coregrind/link_tool_exe_linux"
+
+ac_config_files="$ac_config_files coregrind/link_tool_exe_darwin"
+
+ac_config_files="$ac_config_files coregrind/link_tool_exe_aix5"
+
+ac_config_files="$ac_config_files coregrind/link_tool_exe_l4re"

 
 cat >confcache <<\_ACEOF
 # This file is a shell script that caches the results of configure
 
 cat >confcache <<\_ACEOF
 # This file is a shell script that caches the results of configure


@@ -9041,6 +9193,7 @@ DEFS=-DHAVE_CONFIG_H
 
 ac_libobjs=
 ac_ltlibobjs=
 
 ac_libobjs=
 ac_ltlibobjs=

+U=

 for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
   # 1. Remove the extension, and $U if already installed.
   ac_script='s/\$U\././;s/\.o$//;s/\.obj$//'
 for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
   # 1. Remove the extension, and $U if already installed.
   ac_script='s/\$U\././;s/\.o$//;s/\.obj$//'


@@ -9064,163 +9217,163 @@ else
 fi
 
 if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then
 fi
 
 if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then

-  as_fn_error "conditional \"MAINTAINER_MODE\" was never defined.
+  as_fn_error $? "conditional \"MAINTAINER_MODE\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then

-  as_fn_error "conditional \"AMDEP\" was never defined.
+  as_fn_error $? "conditional \"AMDEP\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then

-  as_fn_error "conditional \"am__fastdepCC\" was never defined.
+  as_fn_error $? "conditional \"am__fastdepCC\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${am__fastdepCXX_TRUE}" && test -z "${am__fastdepCXX_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${am__fastdepCXX_TRUE}" && test -z "${am__fastdepCXX_FALSE}"; then

-  as_fn_error "conditional \"am__fastdepCXX\" was never defined.
+  as_fn_error $? "conditional \"am__fastdepCXX\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${am__fastdepCCAS_TRUE}" && test -z "${am__fastdepCCAS_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${am__fastdepCCAS_TRUE}" && test -z "${am__fastdepCCAS_FALSE}"; then

-  as_fn_error "conditional \"am__fastdepCCAS\" was never defined.
+  as_fn_error $? "conditional \"am__fastdepCCAS\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_X86_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_X86_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_X86_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_X86_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_ARCHS_INCLUDE_X86\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_X86\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_AMD64_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_AMD64_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_AMD64_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_AMD64_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_ARCHS_INCLUDE_AMD64\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_AMD64\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_PPC32_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_PPC32_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_PPC32_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_PPC32_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_ARCHS_INCLUDE_PPC32\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_PPC32\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_PPC64_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_PPC64_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_PPC64_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_PPC64_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_ARCHS_INCLUDE_PPC64\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_PPC64\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_ARM_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_ARM_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_ARCHS_INCLUDE_ARM_TRUE}" && test -z "${VGCONF_ARCHS_INCLUDE_ARM_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_ARCHS_INCLUDE_ARM\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_ARCHS_INCLUDE_ARM\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_LINUX_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_LINUX_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_LINUX\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_LINUX\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_ARM_LINUX\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_ARM_LINUX\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_PPC32_AIX5_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_PPC32_AIX5_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_PPC32_AIX5_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_PPC32_AIX5_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_PPC32_AIX5\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_PPC32_AIX5\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_PPC64_AIX5_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_PPC64_AIX5_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_PPC64_AIX5_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_PPC64_AIX5_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_PPC64_AIX5\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_PPC64_AIX5\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_DARWIN\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_DARWIN\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_AMD64_DARWIN\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_L4RE_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE}" && test -z "${VGCONF_PLATFORMS_INCLUDE_X86_L4RE_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_L4RE\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_PLATFORMS_INCLUDE_X86_L4RE\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_OS_IS_LINUX_TRUE}" && test -z "${VGCONF_OS_IS_LINUX_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_OS_IS_LINUX_TRUE}" && test -z "${VGCONF_OS_IS_LINUX_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_OS_IS_LINUX\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_OS_IS_LINUX\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_OS_IS_AIX5_TRUE}" && test -z "${VGCONF_OS_IS_AIX5_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_OS_IS_AIX5_TRUE}" && test -z "${VGCONF_OS_IS_AIX5_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_OS_IS_AIX5\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_OS_IS_AIX5\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_OS_IS_DARWIN_TRUE}" && test -z "${VGCONF_OS_IS_DARWIN_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_OS_IS_DARWIN_TRUE}" && test -z "${VGCONF_OS_IS_DARWIN_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_OS_IS_DARWIN\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_OS_IS_DARWIN\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_OS_IS_L4RE_TRUE}" && test -z "${VGCONF_OS_IS_L4RE_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_OS_IS_L4RE_TRUE}" && test -z "${VGCONF_OS_IS_L4RE_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_OS_IS_L4RE\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_OS_IS_L4RE\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_HAVE_PLATFORM_SEC_TRUE}" && test -z "${VGCONF_HAVE_PLATFORM_SEC_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${VGCONF_HAVE_PLATFORM_SEC_TRUE}" && test -z "${VGCONF_HAVE_PLATFORM_SEC_FALSE}"; then

-  as_fn_error "conditional \"VGCONF_HAVE_PLATFORM_SEC\" was never defined.
+  as_fn_error $? "conditional \"VGCONF_HAVE_PLATFORM_SEC\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAS_ALTIVEC_TRUE}" && test -z "${HAS_ALTIVEC_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAS_ALTIVEC_TRUE}" && test -z "${HAS_ALTIVEC_FALSE}"; then

-  as_fn_error "conditional \"HAS_ALTIVEC\" was never defined.
+  as_fn_error $? "conditional \"HAS_ALTIVEC\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_ALTIVEC_H_TRUE}" && test -z "${HAVE_ALTIVEC_H_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_ALTIVEC_H_TRUE}" && test -z "${HAVE_ALTIVEC_H_FALSE}"; then

-  as_fn_error "conditional \"HAVE_ALTIVEC_H\" was never defined.
+  as_fn_error $? "conditional \"HAVE_ALTIVEC_H\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_PTHREAD_CREATE_GLIBC_2_0_TRUE}" && test -z "${HAVE_PTHREAD_CREATE_GLIBC_2_0_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_PTHREAD_CREATE_GLIBC_2_0_TRUE}" && test -z "${HAVE_PTHREAD_CREATE_GLIBC_2_0_FALSE}"; then

-  as_fn_error "conditional \"HAVE_PTHREAD_CREATE_GLIBC_2_0\" was never defined.
+  as_fn_error $? "conditional \"HAVE_PTHREAD_CREATE_GLIBC_2_0\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${BUILD_SSE3_TESTS_TRUE}" && test -z "${BUILD_SSE3_TESTS_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${BUILD_SSE3_TESTS_TRUE}" && test -z "${BUILD_SSE3_TESTS_FALSE}"; then

-  as_fn_error "conditional \"BUILD_SSE3_TESTS\" was never defined.
+  as_fn_error $? "conditional \"BUILD_SSE3_TESTS\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${BUILD_SSSE3_TESTS_TRUE}" && test -z "${BUILD_SSSE3_TESTS_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${BUILD_SSSE3_TESTS_TRUE}" && test -z "${BUILD_SSSE3_TESTS_FALSE}"; then

-  as_fn_error "conditional \"BUILD_SSSE3_TESTS\" was never defined.
+  as_fn_error $? "conditional \"BUILD_SSSE3_TESTS\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_PTHREAD_BARRIER_TRUE}" && test -z "${HAVE_PTHREAD_BARRIER_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_PTHREAD_BARRIER_TRUE}" && test -z "${HAVE_PTHREAD_BARRIER_FALSE}"; then

-  as_fn_error "conditional \"HAVE_PTHREAD_BARRIER\" was never defined.
+  as_fn_error $? "conditional \"HAVE_PTHREAD_BARRIER\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_PTHREAD_MUTEX_TIMEDLOCK_TRUE}" && test -z "${HAVE_PTHREAD_MUTEX_TIMEDLOCK_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_PTHREAD_MUTEX_TIMEDLOCK_TRUE}" && test -z "${HAVE_PTHREAD_MUTEX_TIMEDLOCK_FALSE}"; then

-  as_fn_error "conditional \"HAVE_PTHREAD_MUTEX_TIMEDLOCK\" was never defined.
+  as_fn_error $? "conditional \"HAVE_PTHREAD_MUTEX_TIMEDLOCK\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_PTHREAD_SPINLOCK_TRUE}" && test -z "${HAVE_PTHREAD_SPINLOCK_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_PTHREAD_SPINLOCK_TRUE}" && test -z "${HAVE_PTHREAD_SPINLOCK_FALSE}"; then

-  as_fn_error "conditional \"HAVE_PTHREAD_SPINLOCK\" was never defined.
+  as_fn_error $? "conditional \"HAVE_PTHREAD_SPINLOCK\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${BUILD_MPIWRAP_PRI_TRUE}" && test -z "${BUILD_MPIWRAP_PRI_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${BUILD_MPIWRAP_PRI_TRUE}" && test -z "${BUILD_MPIWRAP_PRI_FALSE}"; then

-  as_fn_error "conditional \"BUILD_MPIWRAP_PRI\" was never defined.
+  as_fn_error $? "conditional \"BUILD_MPIWRAP_PRI\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${BUILD_MPIWRAP_SEC_TRUE}" && test -z "${BUILD_MPIWRAP_SEC_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${BUILD_MPIWRAP_SEC_TRUE}" && test -z "${BUILD_MPIWRAP_SEC_FALSE}"; then

-  as_fn_error "conditional \"BUILD_MPIWRAP_SEC\" was never defined.
+  as_fn_error $? "conditional \"BUILD_MPIWRAP_SEC\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_QTCORE_TRUE}" && test -z "${HAVE_QTCORE_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_QTCORE_TRUE}" && test -z "${HAVE_QTCORE_FALSE}"; then

-  as_fn_error "conditional \"HAVE_QTCORE\" was never defined.
+  as_fn_error $? "conditional \"HAVE_QTCORE\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_QTCORE_QATOMICINT_TRUE}" && test -z "${HAVE_QTCORE_QATOMICINT_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_QTCORE_QATOMICINT_TRUE}" && test -z "${HAVE_QTCORE_QATOMICINT_FALSE}"; then

-  as_fn_error "conditional \"HAVE_QTCORE_QATOMICINT\" was never defined.
+  as_fn_error $? "conditional \"HAVE_QTCORE_QATOMICINT\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_BOOST_1_35_TRUE}" && test -z "${HAVE_BOOST_1_35_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_BOOST_1_35_TRUE}" && test -z "${HAVE_BOOST_1_35_FALSE}"; then

-  as_fn_error "conditional \"HAVE_BOOST_1_35\" was never defined.
+  as_fn_error $? "conditional \"HAVE_BOOST_1_35\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_OPENMP_TRUE}" && test -z "${HAVE_OPENMP_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_OPENMP_TRUE}" && test -z "${HAVE_OPENMP_FALSE}"; then

-  as_fn_error "conditional \"HAVE_OPENMP\" was never defined.
+  as_fn_error $? "conditional \"HAVE_OPENMP\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_BUILTIN_ATOMIC_TRUE}" && test -z "${HAVE_BUILTIN_ATOMIC_FALSE}"; then
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 if test -z "${HAVE_BUILTIN_ATOMIC_TRUE}" && test -z "${HAVE_BUILTIN_ATOMIC_FALSE}"; then

-  as_fn_error "conditional \"HAVE_BUILTIN_ATOMIC\" was never defined.
+  as_fn_error $? "conditional \"HAVE_BUILTIN_ATOMIC\" was never defined.

 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 
 Usually this means the macro was only invoked conditionally." "$LINENO" 5
 fi
 


@@ -9370,19 +9523,19 @@ export LANGUAGE
 (unset CDPATH) >/dev/null 2>&1 && unset CDPATH
 
 
 (unset CDPATH) >/dev/null 2>&1 && unset CDPATH
 
 

-# as_fn_error ERROR [LINENO LOG_FD]
-# ---------------------------------
+# as_fn_error STATUS ERROR [LINENO LOG_FD]
+# ----------------------------------------

 # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
 # provided, also output the error to LOG_FD, referencing LINENO. Then exit the
 # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
 # provided, also output the error to LOG_FD, referencing LINENO. Then exit the

-# script with status $?, using 1 if that was 0.
+# script with STATUS, using 1 if that was 0.

 as_fn_error ()
 {
 as_fn_error ()
 {

-  as_status=$?; test $as_status -eq 0 && as_status=1
-  if test "$3"; then
-    as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
-    $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3
+  as_status=$1; test $as_status -eq 0 && as_status=1
+  if test "$4"; then
+    as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+    $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4

   fi
   fi

-  $as_echo "$as_me: error: $1" >&2
+  $as_echo "$as_me: error: $2" >&2

   as_fn_exit $as_status
 } # as_fn_error
 
   as_fn_exit $as_status
 } # as_fn_error
 


@@ -9578,7 +9731,7 @@ $as_echo X"$as_dir" |
       test -d "$as_dir" && break
     done
     test -z "$as_dirs" || eval "mkdir $as_dirs"
       test -d "$as_dir" && break
     done
     test -z "$as_dirs" || eval "mkdir $as_dirs"

-  } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir"
+  } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"

 
 
 } # as_fn_mkdir_p
 
 
 } # as_fn_mkdir_p


@@ -9632,7 +9785,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
 # values after options handling.
 ac_log="
 This file was extended by Valgrind $as_me 3.6.0.SVN, which was
 # values after options handling.
 ac_log="
 This file was extended by Valgrind $as_me 3.6.0.SVN, which was

-generated by GNU Autoconf 2.65.  Invocation command line was
+generated by GNU Autoconf 2.67.  Invocation command line was

 
   CONFIG_FILES    = $CONFIG_FILES
   CONFIG_HEADERS  = $CONFIG_HEADERS
 
   CONFIG_FILES    = $CONFIG_FILES
   CONFIG_HEADERS  = $CONFIG_HEADERS


@@ -9698,10 +9851,10 @@ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
 ac_cs_version="\\
 Valgrind config.status 3.6.0.SVN
 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
 ac_cs_version="\\
 Valgrind config.status 3.6.0.SVN

-configured by $0, generated by GNU Autoconf 2.65,
+configured by $0, generated by GNU Autoconf 2.67,

   with options \\"\$ac_cs_config\\"
 
   with options \\"\$ac_cs_config\\"
 

-Copyright (C) 2009 Free Software Foundation, Inc.
+Copyright (C) 2010 Free Software Foundation, Inc.

 This config.status script is free software; the Free Software Foundation
 gives unlimited permission to copy, distribute and modify it."
 
 This config.status script is free software; the Free Software Foundation
 gives unlimited permission to copy, distribute and modify it."
 


@@ -9719,11 +9872,16 @@ ac_need_defaults=:
 while test $# != 0
 do
   case $1 in
 while test $# != 0
 do
   case $1 in

-  --*=*)
+  --*=?*)

     ac_option=`expr "X$1" : 'X\([^=]*\)='`
     ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
     ac_shift=:
     ;;
     ac_option=`expr "X$1" : 'X\([^=]*\)='`
     ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
     ac_shift=:
     ;;

+  --*=)
+    ac_option=`expr "X$1" : 'X\([^=]*\)='`
+    ac_optarg=
+    ac_shift=:
+    ;;

   *)
     ac_option=$1
     ac_optarg=$2
   *)
     ac_option=$1
     ac_optarg=$2


@@ -9745,6 +9903,7 @@ do
     $ac_shift
     case $ac_optarg in
     *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
     $ac_shift
     case $ac_optarg in
     *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;

+    '') as_fn_error $? "missing file argument" ;;

     esac
     as_fn_append CONFIG_FILES " '$ac_optarg'"
     ac_need_defaults=false;;
     esac
     as_fn_append CONFIG_FILES " '$ac_optarg'"
     ac_need_defaults=false;;


@@ -9757,7 +9916,7 @@ do
     ac_need_defaults=false;;
   --he | --h)
     # Conflict between --help and --header
     ac_need_defaults=false;;
   --he | --h)
     # Conflict between --help and --header

-    as_fn_error "ambiguous option: \`$1'
+    as_fn_error $? "ambiguous option: \`$1'

 Try \`$0 --help' for more information.";;
   --help | --hel | -h )
     $as_echo "$ac_cs_usage"; exit ;;
 Try \`$0 --help' for more information.";;
   --help | --hel | -h )
     $as_echo "$ac_cs_usage"; exit ;;


@@ -9766,7 +9925,7 @@ Try \`$0 --help' for more information.";;
     ac_cs_silent=: ;;
 
   # This is an error.
     ac_cs_silent=: ;;
 
   # This is an error.

-  -*) as_fn_error "unrecognized option: \`$1'
+  -*) as_fn_error $? "unrecognized option: \`$1'

 Try \`$0 --help' for more information." ;;
 
   *) as_fn_append ac_config_targets " $1"
 Try \`$0 --help' for more information." ;;
 
   *) as_fn_append ac_config_targets " $1"


@@ -9842,12 +10001,14 @@ do
     "memcheck/tests/x86/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/x86/Makefile" ;;
     "memcheck/tests/linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/linux/Makefile" ;;
     "memcheck/tests/darwin/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/darwin/Makefile" ;;
     "memcheck/tests/x86/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/x86/Makefile" ;;
     "memcheck/tests/linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/linux/Makefile" ;;
     "memcheck/tests/darwin/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/darwin/Makefile" ;;

+    "memcheck/tests/amd64-linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/amd64-linux/Makefile" ;;

     "memcheck/tests/x86-linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/x86-linux/Makefile" ;;
     "memcheck/perf/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/perf/Makefile" ;;
     "cachegrind/Makefile") CONFIG_FILES="$CONFIG_FILES cachegrind/Makefile" ;;
     "cachegrind/tests/Makefile") CONFIG_FILES="$CONFIG_FILES cachegrind/tests/Makefile" ;;
     "cachegrind/tests/x86/Makefile") CONFIG_FILES="$CONFIG_FILES cachegrind/tests/x86/Makefile" ;;
     "cachegrind/cg_annotate") CONFIG_FILES="$CONFIG_FILES cachegrind/cg_annotate" ;;
     "memcheck/tests/x86-linux/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/tests/x86-linux/Makefile" ;;
     "memcheck/perf/Makefile") CONFIG_FILES="$CONFIG_FILES memcheck/perf/Makefile" ;;
     "cachegrind/Makefile") CONFIG_FILES="$CONFIG_FILES cachegrind/Makefile" ;;
     "cachegrind/tests/Makefile") CONFIG_FILES="$CONFIG_FILES cachegrind/tests/Makefile" ;;
     "cachegrind/tests/x86/Makefile") CONFIG_FILES="$CONFIG_FILES cachegrind/tests/x86/Makefile" ;;
     "cachegrind/cg_annotate") CONFIG_FILES="$CONFIG_FILES cachegrind/cg_annotate" ;;

+    "cachegrind/cg_diff") CONFIG_FILES="$CONFIG_FILES cachegrind/cg_diff" ;;

     "callgrind/Makefile") CONFIG_FILES="$CONFIG_FILES callgrind/Makefile" ;;
     "callgrind/callgrind_annotate") CONFIG_FILES="$CONFIG_FILES callgrind/callgrind_annotate" ;;
     "callgrind/callgrind_control") CONFIG_FILES="$CONFIG_FILES callgrind/callgrind_control" ;;
     "callgrind/Makefile") CONFIG_FILES="$CONFIG_FILES callgrind/Makefile" ;;
     "callgrind/callgrind_annotate") CONFIG_FILES="$CONFIG_FILES callgrind/callgrind_annotate" ;;
     "callgrind/callgrind_control") CONFIG_FILES="$CONFIG_FILES callgrind/callgrind_control" ;;


@@ -9881,8 +10042,12 @@ do
     "exp-bbv/tests/x86-linux/Makefile") CONFIG_FILES="$CONFIG_FILES exp-bbv/tests/x86-linux/Makefile" ;;
     "exp-bbv/tests/amd64-linux/Makefile") CONFIG_FILES="$CONFIG_FILES exp-bbv/tests/amd64-linux/Makefile" ;;
     "exp-bbv/tests/ppc32-linux/Makefile") CONFIG_FILES="$CONFIG_FILES exp-bbv/tests/ppc32-linux/Makefile" ;;
     "exp-bbv/tests/x86-linux/Makefile") CONFIG_FILES="$CONFIG_FILES exp-bbv/tests/x86-linux/Makefile" ;;
     "exp-bbv/tests/amd64-linux/Makefile") CONFIG_FILES="$CONFIG_FILES exp-bbv/tests/amd64-linux/Makefile" ;;
     "exp-bbv/tests/ppc32-linux/Makefile") CONFIG_FILES="$CONFIG_FILES exp-bbv/tests/ppc32-linux/Makefile" ;;

+    "coregrind/link_tool_exe_linux") CONFIG_FILES="$CONFIG_FILES coregrind/link_tool_exe_linux" ;;
+    "coregrind/link_tool_exe_darwin") CONFIG_FILES="$CONFIG_FILES coregrind/link_tool_exe_darwin" ;;
+    "coregrind/link_tool_exe_aix5") CONFIG_FILES="$CONFIG_FILES coregrind/link_tool_exe_aix5" ;;
+    "coregrind/link_tool_exe_l4re") CONFIG_FILES="$CONFIG_FILES coregrind/link_tool_exe_l4re" ;;

 
 

-  *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
+  *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5 ;;

   esac
 done
 
   esac
 done
 


@@ -9920,7 +10085,7 @@ $debug ||
 {
   tmp=./conf$$-$RANDOM
   (umask 077 && mkdir "$tmp")
 {
   tmp=./conf$$-$RANDOM
   (umask 077 && mkdir "$tmp")

-} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5
+} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5

 
 # Set up the scripts for CONFIG_FILES section.
 # No need to generate them if there are no CONFIG_FILES.
 
 # Set up the scripts for CONFIG_FILES section.
 # No need to generate them if there are no CONFIG_FILES.


@@ -9937,7 +10102,7 @@ if test "x$ac_cr" = x; then
 fi
 ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
 if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
 fi
 ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
 if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then

-  ac_cs_awk_cr='\r'
+  ac_cs_awk_cr='\\r'

 else
   ac_cs_awk_cr=$ac_cr
 fi
 else
   ac_cs_awk_cr=$ac_cr
 fi


@@ -9951,18 +10116,18 @@ _ACEOF
   echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' &&
   echo "_ACEOF"
 } >conf$$subs.sh ||
   echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' &&
   echo "_ACEOF"
 } >conf$$subs.sh ||

-  as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
-ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'`
+  as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
+ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'`

 ac_delim='%!_!# '
 for ac_last_try in false false false false false :; do
   . ./conf$$subs.sh ||
 ac_delim='%!_!# '
 for ac_last_try in false false false false false :; do
   . ./conf$$subs.sh ||

-    as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
+    as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5

 
   ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X`
   if test $ac_delim_n = $ac_delim_num; then
     break
   elif $ac_last_try; then
 
   ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X`
   if test $ac_delim_n = $ac_delim_num; then
     break
   elif $ac_last_try; then

-    as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5
+    as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5

   else
     ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
   fi
   else
     ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
   fi


@@ -10051,20 +10216,28 @@ if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
 else
   cat
 fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \
 else
   cat
 fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \

-  || as_fn_error "could not setup config files machinery" "$LINENO" 5
+  || as_fn_error $? "could not setup config files machinery" "$LINENO" 5

 _ACEOF
 
 _ACEOF
 

-# VPATH may cause trouble with some makes, so we remove $(srcdir),
-# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
+# VPATH may cause trouble with some makes, so we remove sole $(srcdir),
+# ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and

 # trailing colons and then remove the whole line if VPATH becomes empty
 # (actually we leave an empty line to preserve line numbers).
 if test "x$srcdir" = x.; then
 # trailing colons and then remove the whole line if VPATH becomes empty
 # (actually we leave an empty line to preserve line numbers).
 if test "x$srcdir" = x.; then

-  ac_vpsub='/^[         ]*VPATH[        ]*=/{
-s/:*\$(srcdir):*/:/
-s/:*\${srcdir}:*/:/
-s/:*@srcdir@:*/:/
-s/^\([^=]*=[    ]*\):*/\1/
+  ac_vpsub='/^[         ]*VPATH[        ]*=[    ]*/{
+h
+s///
+s/^/:/
+s/[     ]*$/:/
+s/:\$(srcdir):/:/g
+s/:\${srcdir}:/:/g
+s/:@srcdir@:/:/g
+s/^:*//

 s/:*$//
 s/:*$//

+x
+s/\(=[  ]*\).*/\1/
+G
+s/\n//

 s/^[^=]*=[      ]*$//
 }'
 fi
 s/^[^=]*=[      ]*$//
 }'
 fi


@@ -10092,7 +10265,7 @@ for ac_last_try in false false :; do
   if test -z "$ac_t"; then
     break
   elif $ac_last_try; then
   if test -z "$ac_t"; then
     break
   elif $ac_last_try; then

-    as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5
+    as_fn_error $? "could not make $CONFIG_HEADERS" "$LINENO" 5

   else
     ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
   fi
   else
     ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
   fi


@@ -10177,7 +10350,7 @@ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
 _ACAWK
 _ACEOF
 cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
 _ACAWK
 _ACEOF
 cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1

-  as_fn_error "could not setup config headers machinery" "$LINENO" 5
+  as_fn_error $? "could not setup config headers machinery" "$LINENO" 5

 fi # test -n "$CONFIG_HEADERS"
 
 
 fi # test -n "$CONFIG_HEADERS"
 
 


@@ -10190,7 +10363,7 @@ do
   esac
   case $ac_mode$ac_tag in
   :[FHL]*:*);;
   esac
   case $ac_mode$ac_tag in
   :[FHL]*:*);;

-  :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;;
+  :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5 ;;

   :[FH]-) ac_tag=-:-;;
   :[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
   esac
   :[FH]-) ac_tag=-:-;;
   :[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
   esac


@@ -10218,7 +10391,7 @@ do
           [\\/$]*) false;;
           *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
           esac ||
           [\\/$]*) false;;
           *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
           esac ||

-          as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;;
+          as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5 ;;

       esac
       case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
       as_fn_append ac_file_inputs " '$ac_f'"
       esac
       case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
       as_fn_append ac_file_inputs " '$ac_f'"


@@ -10245,7 +10418,7 @@ $as_echo "$as_me: creating $ac_file" >&6;}
 
     case $ac_tag in
     *:-:* | *:-) cat >"$tmp/stdin" \
 
     case $ac_tag in
     *:-:* | *:-) cat >"$tmp/stdin" \

-      || as_fn_error "could not create $ac_file" "$LINENO" 5 ;;
+      || as_fn_error $? "could not create $ac_file" "$LINENO" 5  ;;

     esac
     ;;
   esac
     esac
     ;;
   esac


@@ -10382,22 +10555,22 @@ s&@MKDIR_P@&$ac_MKDIR_P&;t t
 $ac_datarootdir_hack
 "
 eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$tmp/subs.awk" >$tmp/out \
 $ac_datarootdir_hack
 "
 eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$tmp/subs.awk" >$tmp/out \

-  || as_fn_error "could not create $ac_file" "$LINENO" 5
+  || as_fn_error $? "could not create $ac_file" "$LINENO" 5

 
 test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
   { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } &&
   { ac_out=`sed -n '/^[         ]*datarootdir[  ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } &&
   { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
 
 test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
   { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } &&
   { ac_out=`sed -n '/^[         ]*datarootdir[  ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } &&
   { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'

-which seems to be undefined.  Please make sure it is defined." >&5
+which seems to be undefined.  Please make sure it is defined" >&5

 $as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
 $as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'

-which seems to be undefined.  Please make sure it is defined." >&2;}
+which seems to be undefined.  Please make sure it is defined" >&2;}

 
   rm -f "$tmp/stdin"
   case $ac_file in
   -) cat "$tmp/out" && rm -f "$tmp/out";;
   *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";;
   esac \
 
   rm -f "$tmp/stdin"
   case $ac_file in
   -) cat "$tmp/out" && rm -f "$tmp/out";;
   *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";;
   esac \

-  || as_fn_error "could not create $ac_file" "$LINENO" 5
+  || as_fn_error $? "could not create $ac_file" "$LINENO" 5

  ;;
   :H)
   #
  ;;
   :H)
   #


@@ -10408,19 +10581,19 @@ which seems to be undefined.  Please make sure it is defined." >&2;}
       $as_echo "/* $configure_input  */" \
       && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs"
     } >"$tmp/config.h" \
       $as_echo "/* $configure_input  */" \
       && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs"
     } >"$tmp/config.h" \

-      || as_fn_error "could not create $ac_file" "$LINENO" 5
+      || as_fn_error $? "could not create $ac_file" "$LINENO" 5

     if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then
       { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5
 $as_echo "$as_me: $ac_file is unchanged" >&6;}
     else
       rm -f "$ac_file"
       mv "$tmp/config.h" "$ac_file" \
     if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then
       { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5
 $as_echo "$as_me: $ac_file is unchanged" >&6;}
     else
       rm -f "$ac_file"
       mv "$tmp/config.h" "$ac_file" \

-       || as_fn_error "could not create $ac_file" "$LINENO" 5
+       || as_fn_error $? "could not create $ac_file" "$LINENO" 5

     fi
   else
     $as_echo "/* $configure_input  */" \
       && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \
     fi
   else
     $as_echo "/* $configure_input  */" \
       && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \

-      || as_fn_error "could not create -" "$LINENO" 5
+      || as_fn_error $? "could not create -" "$LINENO" 5

   fi
 # Compute "$ac_file"'s index in $config_headers.
 _am_arg="$ac_file"
   fi
 # Compute "$ac_file"'s index in $config_headers.
 _am_arg="$ac_file"


@@ -10560,6 +10733,10 @@ $as_echo X"$file" |
   done
 }
  ;;
   done
 }
  ;;

+    "coregrind/link_tool_exe_linux":F) chmod +x coregrind/link_tool_exe_linux ;;
+    "coregrind/link_tool_exe_darwin":F) chmod +x coregrind/link_tool_exe_darwin ;;
+    "coregrind/link_tool_exe_aix5":F) chmod +x coregrind/link_tool_exe_aix5 ;;
+    "coregrind/link_tool_exe_l4re":F) chmod +x coregrind/link_tool_exe_l4re ;;

 
   esac
 done # for ac_tag
 
   esac
 done # for ac_tag


@@ -10570,7 +10747,7 @@ _ACEOF
 ac_clean_files=$ac_clean_files_save
 
 test $ac_write_fail = 0 ||
 ac_clean_files=$ac_clean_files_save
 
 test $ac_write_fail = 0 ||

-  as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5
+  as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5

 
 
 # configure is writing to config.log, and then calls config.status.
 
 
 # configure is writing to config.log, and then calls config.status.


@@ -10591,7 +10768,7 @@ if test "$no_create" != yes; then
   exec 5>>config.log
   # Use ||, not &&, to avoid exiting from the if with $? = 1, which
   # would make configure fail if this is the last instruction.
   exec 5>>config.log
   # Use ||, not &&, to avoid exiting from the if with $? = 1, which
   # would make configure fail if this is the last instruction.

-  $ac_cs_success || as_fn_exit $?
+  $ac_cs_success || as_fn_exit 1

 fi
 if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then
   { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5
 fi
 if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then
   { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/configure.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/configure.in
index 3649b659d11628720a65e9d5e5902509c7914297..378ea13c46fe9e235fe131d834e638ff83a3b126 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/configure.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/configure.in
@@ -18,7 +18,7 @@ AM_MAINTAINER_MODE
 #----------------------------------------------------------------------------
 # Checks for various programs.
 #----------------------------------------------------------------------------
 #----------------------------------------------------------------------------
 # Checks for various programs.
 #----------------------------------------------------------------------------

-CFLAGS="-Wno-long-long"
+CFLAGS="-Wno-long-long $CFLAGS"

 
 AC_PROG_LN_S
 AC_PROG_CC
 
 AC_PROG_LN_S
 AC_PROG_CC


@@ -39,11 +39,18 @@ AC_PROG_CXX
 #         AC_SUBST([OBJCFLAGS])
 #        ])
 AC_PROG_RANLIB
 #         AC_SUBST([OBJCFLAGS])
 #        ])
 AC_PROG_RANLIB

+# provide a very basic definition for AC_PROG_SED if it's not provided by
+# autoconf (as e.g. in autoconf 2.59).
+m4_ifndef([AC_PROG_SED],
+          [AC_DEFUN([AC_PROG_SED],
+                    [AC_ARG_VAR([SED])
+                     AC_CHECK_PROGS([SED],[gsed sed])])])
+AC_PROG_SED

 
 # If no AR variable was specified, look up the name of the archiver. Otherwise
 # do not touch the AR variable.
 if test "x$AR" = "x"; then
 
 # If no AR variable was specified, look up the name of the archiver. Otherwise
 # do not touch the AR variable.
 if test "x$AR" = "x"; then

-  AC_PATH_PROGS([AR], [`echo $LD | sed 's/ld$/ar/'` "ar"], [ar])
+  AC_PATH_PROGS([AR], [`echo $LD | $SED 's/ld$/ar/'` "ar"], [ar])

 fi
 AC_ARG_VAR([AR],[Archiver command])
 
 fi
 AC_ARG_VAR([AR],[Archiver command])
 


@@ -92,7 +99,7 @@ rm $tmpfile
 # We don't want gcc < 3.0
 AC_MSG_CHECKING([for a supported version of gcc])
 
 # We don't want gcc < 3.0
 AC_MSG_CHECKING([for a supported version of gcc])
 

-[gcc_version=`${CC} --version | head -n 1 | sed 's/^[^0-9]*\([0-9.]*\).*$/\1/'`]
+[gcc_version=`${CC} --version | head -n 1 | $SED 's/^[^0-9]*\([0-9.]*\).*$/\1/'`]

 
 case "${gcc_version}" in
      2.*)
 
 case "${gcc_version}" in
      2.*)


@@ -245,11 +252,6 @@ case "${host_os}" in
         VGCONF_OS="aix5"
         ;;       
 
         VGCONF_OS="aix5"
         ;;       
 

-     *freebsd*)
-        AC_MSG_RESULT([ok (${host_os})])
-        VGCONF_OS="freebsd"
-        ;;
-

      *l4re*)
         AC_MSG_RESULT([ok (${host_os})])
         VGCONF_OS="l4re"
      *l4re*)
         AC_MSG_RESULT([ok (${host_os})])
         VGCONF_OS="l4re"


@@ -258,6 +260,9 @@ case "${host_os}" in
      *darwin*)
         AC_MSG_RESULT([ok (${host_os})])
         VGCONF_OS="darwin"
      *darwin*)
         AC_MSG_RESULT([ok (${host_os})])
         VGCONF_OS="darwin"

+        AC_DEFINE([DARWIN_10_5], 100500, [DARWIN_VERS value for Mac OS X 10.5])
+        AC_DEFINE([DARWIN_10_6], 100600, [DARWIN_VERS value for Mac OS X 10.6])
+        AC_DEFINE([DARWIN_10_7], 100700, [DARWIN_VERS value for Mac OS X 10.7])

 
        AC_MSG_CHECKING([for the kernel version])
        kernel=`uname -r`
 
        AC_MSG_CHECKING([for the kernel version])
        kernel=`uname -r`


@@ -265,28 +270,34 @@ case "${host_os}" in
         # Nb: for Darwin we set DEFAULT_SUPP here.  That's because Darwin
         # has only one relevant version, the OS version. The `uname` check
         # is a good way to get that version (i.e. "Darwin 9.6.0" is Mac OS
         # Nb: for Darwin we set DEFAULT_SUPP here.  That's because Darwin
         # has only one relevant version, the OS version. The `uname` check
         # is a good way to get that version (i.e. "Darwin 9.6.0" is Mac OS

-        # X 10.5.6, and "Darwin 10.x" would presumably be Mac OS X 10.6.x
-        # Snow Leopard and darwin10.supp), and we don't know of an macros
-        # similar to __GLIBC__ to get that info.
+        # X 10.5.6, and "Darwin 10.x" is Mac OS X 10.6.x Snow Leopard), 
+        # and we don't know of an macros similar to __GLIBC__ to get that info.

         #
         # XXX: `uname -r` won't do the right thing for cross-compiles, but
         # that's not a problem yet.
        case "${kernel}" in
             9.*)
                  AC_MSG_RESULT([Darwin 9.x (${kernel}) / Mac OS X 10.5 Leopard])
         #
         # XXX: `uname -r` won't do the right thing for cross-compiles, but
         # that's not a problem yet.
        case "${kernel}" in
             9.*)
                  AC_MSG_RESULT([Darwin 9.x (${kernel}) / Mac OS X 10.5 Leopard])

+                 AC_DEFINE([DARWIN_VERS], DARWIN_10_5, [Darwin / Mac OS X version])

                  DEFAULT_SUPP="darwin9.supp ${DEFAULT_SUPP}"
                  DEFAULT_SUPP="darwin9-drd.supp ${DEFAULT_SUPP}"
                  ;;
                  DEFAULT_SUPP="darwin9.supp ${DEFAULT_SUPP}"
                  DEFAULT_SUPP="darwin9-drd.supp ${DEFAULT_SUPP}"
                  ;;

+            10.*)
+                 AC_MSG_RESULT([Darwin 10.x (${kernel}) / Mac OS X 10.6 Snow Leopard])
+                 AC_DEFINE([DARWIN_VERS], DARWIN_10_6, [Darwin / Mac OS X version])
+                 DEFAULT_SUPP="darwin10.supp ${DEFAULT_SUPP}"
+                 DEFAULT_SUPP="darwin10-drd.supp ${DEFAULT_SUPP}"
+                 ;;

      *) 
                  AC_MSG_RESULT([unsupported (${kernel})])
      *) 
                  AC_MSG_RESULT([unsupported (${kernel})])

-                 AC_MSG_ERROR([Valgrind works on Darwin 9.x (Mac OS X 10.5)])
+                 AC_MSG_ERROR([Valgrind works on Darwin 9.x and 10.x (Mac OS X 10.5 and 10.6)])

                  ;;
        esac
         ;;
 
      *) 
        AC_MSG_RESULT([no (${host_os})])
                  ;;
        esac
         ;;
 
      *) 
        AC_MSG_RESULT([no (${host_os})])

-       AC_MSG_ERROR([Valgrind is operating system specific. Sorry. Please consider doing a port.])
+       AC_MSG_ERROR([Valgrind is operating system specific. Sorry.])

        ;;
 esac
 
        ;;
 esac
 


@@ -357,35 +368,52 @@ AC_SUBST(VGCONF_PLATFORM_SEC_CAPS)
 
 AC_MSG_CHECKING([for a supported CPU/OS combination])
 
 
 AC_MSG_CHECKING([for a supported CPU/OS combination])
 

+# NB.  The load address for a given platform may be specified in more 
+# than one place, in some cases, depending on whether we're doing a biarch,
+# 32-bit only or 64-bit only build.  eg see case for amd64-linux below.
+# Be careful to give consistent values in all subcases.  Also, all four
+# valt_load_addres_{pri,sec}_{norml,inner} values must always be set,
+# even if it is to "0xUNSET".
+#

 case "$ARCH_MAX-$VGCONF_OS" in
      x86-linux)
 case "$ARCH_MAX-$VGCONF_OS" in
      x86-linux)

-               VGCONF_ARCH_PRI="x86"
-               VGCONF_ARCH_SEC=""
-       VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
-       VGCONF_PLATFORM_SEC_CAPS=""
-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"
+        VGCONF_ARCH_PRI="x86"
+        VGCONF_ARCH_SEC=""
+        VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
+        VGCONF_PLATFORM_SEC_CAPS=""
+        valt_load_address_pri_norml="0x38000000"
+        valt_load_address_pri_inner="0x28000000"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      amd64-linux)
         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      amd64-linux)

+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""
        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        elif test x$vg_cv_only32bit = xyes; then
           VGCONF_ARCH_PRI="x86"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""
        elif test x$vg_cv_only32bit = xyes; then
           VGCONF_ARCH_PRI="x86"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="X86_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        else
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC="x86"
           VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS="X86_LINUX"
        else
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC="x86"
           VGCONF_PLATFORM_PRI_CAPS="AMD64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS="X86_LINUX"

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"
+           valt_load_address_sec_norml="0x38000000"
+           valt_load_address_sec_inner="0x28000000"

        fi
        fi

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"

         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      ppc32-linux)
         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      ppc32-linux)


@@ -393,11 +421,17 @@ case "$ARCH_MAX-$VGCONF_OS" in
         VGCONF_ARCH_SEC=""
        VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
        VGCONF_PLATFORM_SEC_CAPS=""
         VGCONF_ARCH_SEC=""
        VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
        VGCONF_PLATFORM_SEC_CAPS=""

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"
+        valt_load_address_pri_norml="0x38000000"
+        valt_load_address_pri_inner="0x28000000"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      ppc64-aix5)
         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      ppc64-aix5)

+        valt_load_address_pri_norml="0xUNSET"
+        valt_load_address_pri_inner="0xUNSET"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC=""
        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC=""


@@ -414,29 +448,35 @@ case "$ARCH_MAX-$VGCONF_OS" in
           VGCONF_PLATFORM_PRI_CAPS="PPC64_AIX5"
           VGCONF_PLATFORM_SEC_CAPS="PPC32_AIX5"
        fi
           VGCONF_PLATFORM_PRI_CAPS="PPC64_AIX5"
           VGCONF_PLATFORM_SEC_CAPS="PPC32_AIX5"
        fi

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"

         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      ppc64-linux)
         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      ppc64-linux)

+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        if test x$vg_cv_only64bit = xyes; then
           VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""
        if test x$vg_cv_only64bit = xyes; then
           VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        elif test x$vg_cv_only32bit = xyes; then
           VGCONF_ARCH_PRI="ppc32"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""
        elif test x$vg_cv_only32bit = xyes; then
           VGCONF_ARCH_PRI="ppc32"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="PPC32_LINUX"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        else
           VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC="ppc32"
           VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"
        else
           VGCONF_ARCH_PRI="ppc64"
            VGCONF_ARCH_SEC="ppc32"
           VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
           VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"
+           valt_load_address_sec_norml="0x38000000"
+           valt_load_address_sec_inner="0x28000000"

        fi
        fi

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"

         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      x86-l4re)
         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      x86-l4re)


@@ -444,47 +484,56 @@ case "$ARCH_MAX-$VGCONF_OS" in
                VGCONF_ARCH_SEC=""
                VGCONF_PLATFORM_PRI_CAPS="X86_L4RE"
                VGCONF_PLATFORM_SEC_CAPS=""
                VGCONF_ARCH_SEC=""
                VGCONF_PLATFORM_PRI_CAPS="X86_L4RE"
                VGCONF_PLATFORM_SEC_CAPS=""

-        valt_load_address_normal="0x38000000"
-        valt_load_address_inner="0x28000000"
+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"
+           valt_load_address_sec_norml="0x38000000"
+           valt_load_address_sec_inner="0x28000000"

         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
         ;;
         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
         ;;

-     x86-darwin)
-        VGCONF_ARCH_PRI="x86"
-        VGCONF_ARCH_SEC=""
-       VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
-       VGCONF_PLATFORM_SEC_CAPS=""
-        valt_load_address_normal="0x0"
-        valt_load_address_inner="0x0"
-        AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
-       ;;
-     amd64-darwin)
+     # Darwin gets identified as 32-bit even when it supports 64-bit.
+     # (Not sure why, possibly because 'uname' returns "i386"?)  Just about
+     # all Macs support both 32-bit and 64-bit, so we just build both.  If
+     # someone has a really old 32-bit only machine they can (hopefully?)
+     # build with --enable-only32bit.  See bug 243362.
+     x86-darwin|amd64-darwin)
+        ARCH_MAX="amd64"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS=""
        if test x$vg_cv_only64bit = xyes; then
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS=""

+           valt_load_address_pri_norml="0x138000000"
+           valt_load_address_pri_inner="0x128000000"

        elif test x$vg_cv_only32bit = xyes; then
            VGCONF_ARCH_PRI="x86"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS=""
           VGCONF_ARCH_PRI_CAPS="x86"
        elif test x$vg_cv_only32bit = xyes; then
            VGCONF_ARCH_PRI="x86"
            VGCONF_ARCH_SEC=""
           VGCONF_PLATFORM_PRI_CAPS="X86_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS=""
           VGCONF_ARCH_PRI_CAPS="x86"

+           valt_load_address_pri_norml="0x38000000"
+           valt_load_address_pri_inner="0x28000000"

        else
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC="x86"
           VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS="X86_DARWIN"
        else
            VGCONF_ARCH_PRI="amd64"
            VGCONF_ARCH_SEC="x86"
           VGCONF_PLATFORM_PRI_CAPS="AMD64_DARWIN"
           VGCONF_PLATFORM_SEC_CAPS="X86_DARWIN"

+           valt_load_address_pri_norml="0x138000000"
+           valt_load_address_pri_inner="0x128000000"
+           valt_load_address_sec_norml="0x38000000"
+           valt_load_address_sec_inner="0x28000000"

        fi
        fi

-        valt_load_address_normal="0x0"
-        valt_load_address_inner="0x0"

         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      arm-linux) 
        VGCONF_ARCH_PRI="arm"
        VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
        VGCONF_PLATFORM_SEC_CAPS=""
         AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
        ;;
      arm-linux) 
        VGCONF_ARCH_PRI="arm"
        VGCONF_PLATFORM_PRI_CAPS="ARM_LINUX"
        VGCONF_PLATFORM_SEC_CAPS=""

-       valt_load_address_normal="0x38000000"
-       valt_load_address_inner="0x28000000"
+       valt_load_address_pri_norml="0x38000000"
+       valt_load_address_pri_inner="0x28000000"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

        AC_MSG_RESULT([ok (${host_cpu}-${host_os})])
        ;;
     *)
        AC_MSG_RESULT([ok (${host_cpu}-${host_os})])
        ;;
     *)


@@ -492,6 +541,10 @@ case "$ARCH_MAX-$VGCONF_OS" in
         VGCONF_ARCH_SEC="unknown"
        VGCONF_PLATFORM_PRI_CAPS="UNKNOWN"
        VGCONF_PLATFORM_SEC_CAPS="UNKNOWN"
         VGCONF_ARCH_SEC="unknown"
        VGCONF_PLATFORM_PRI_CAPS="UNKNOWN"
        VGCONF_PLATFORM_SEC_CAPS="UNKNOWN"

+        valt_load_address_pri_norml="0xUNSET"
+        valt_load_address_pri_inner="0xUNSET"
+        valt_load_address_sec_norml="0xUNSET"
+        valt_load_address_sec_inner="0xUNSET"

         AC_MSG_RESULT([no (${ARCH_MAX}-${VGCONF_OS})])
         AC_MSG_ERROR([Valgrind is platform specific. Sorry. Please consider doing a port.])
         ;;
         AC_MSG_RESULT([no (${ARCH_MAX}-${VGCONF_OS})])
         AC_MSG_ERROR([Valgrind is platform specific. Sorry. Please consider doing a port.])
         ;;


@@ -550,7 +603,7 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_X86_L4RE,
                           test x$VGCONF_PLATFORM_PRI_CAPS = xX86_L4RE)
 
 
                           test x$VGCONF_PLATFORM_PRI_CAPS = xX86_L4RE)
 
 

-# Similarly, set up VGCONF_OF_IS_<os>.  Exactly one of these becomes defined.
+# Similarly, set up VGCONF_OS_IS_<os>.  Exactly one of these becomes defined.

 # Relies on the assumption that the primary and secondary targets are 
 # for the same OS, so therefore only necessary to test the primary.
 AM_CONDITIONAL(VGCONF_OS_IS_LINUX,
 # Relies on the assumption that the primary and secondary targets are 
 # for the same OS, so therefore only necessary to test the primary.
 AM_CONDITIONAL(VGCONF_OS_IS_LINUX,


@@ -581,7 +634,8 @@ AM_CONDITIONAL(VGCONF_HAVE_PLATFORM_SEC,
 
 # Check if this should be built as an inner Valgrind, to be run within
 # another Valgrind.  Choose the load address accordingly.
 
 # Check if this should be built as an inner Valgrind, to be run within
 # another Valgrind.  Choose the load address accordingly.

-AC_SUBST(VALT_LOAD_ADDRESS)
+AC_SUBST(VALT_LOAD_ADDRESS_PRI)
+AC_SUBST(VALT_LOAD_ADDRESS_SEC)

 AC_CACHE_CHECK([for use as an inner Valgrind], vg_cv_inner,
    [AC_ARG_ENABLE(inner, 
       [  --enable-inner          enables self-hosting],
 AC_CACHE_CHECK([for use as an inner Valgrind], vg_cv_inner,
    [AC_ARG_ENABLE(inner, 
       [  --enable-inner          enables self-hosting],


@@ -589,9 +643,11 @@ AC_CACHE_CHECK([for use as an inner Valgrind], vg_cv_inner,
       [vg_cv_inner=no])])
 if test "$vg_cv_inner" = yes; then
     AC_DEFINE([ENABLE_INNER], 1, [configured to run as an inner Valgrind])
       [vg_cv_inner=no])])
 if test "$vg_cv_inner" = yes; then
     AC_DEFINE([ENABLE_INNER], 1, [configured to run as an inner Valgrind])

-    VALT_LOAD_ADDRESS=$valt_load_address_inner
+    VALT_LOAD_ADDRESS_PRI=$valt_load_address_pri_inner
+    VALT_LOAD_ADDRESS_SEC=$valt_load_address_sec_inner

 else
 else

-    VALT_LOAD_ADDRESS=$valt_load_address_normal
+    VALT_LOAD_ADDRESS_PRI=$valt_load_address_pri_norml
+    VALT_LOAD_ADDRESS_SEC=$valt_load_address_sec_norml

 fi
 
 
 fi
 
 


@@ -604,107 +660,18 @@ AC_SUBST(DEFAULT_SUPP)
 # glibcs >= 2.7)
 AC_SUBST(GENERATED_SUPP)
 
 # glibcs >= 2.7)
 AC_SUBST(GENERATED_SUPP)
 

-GLIBC_VERSION=""
-
-AC_EGREP_CPP([GLIBC_22], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 2)
-  GLIBC_22
- #endif
-#endif
-],
-GLIBC_VERSION="2.2")
-
-AC_EGREP_CPP([GLIBC_23], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 3)
-  GLIBC_23
- #endif
-#endif
-],
-GLIBC_VERSION="2.3")
-
-AC_EGREP_CPP([GLIBC_24], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 4)
-  GLIBC_24
- #endif
-#endif
-],
-GLIBC_VERSION="2.4")
-
-AC_EGREP_CPP([GLIBC_25], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 5)
-  GLIBC_25
- #endif
-#endif
-],
-GLIBC_VERSION="2.5")
-
-AC_EGREP_CPP([GLIBC_26], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 6)
-  GLIBC_26
- #endif
-#endif
-],
-GLIBC_VERSION="2.6")
-
-AC_EGREP_CPP([GLIBC_27], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 7)
-  GLIBC_27
- #endif
-#endif
-],
-GLIBC_VERSION="2.7")
-
-AC_EGREP_CPP([GLIBC_28], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 8)
-  GLIBC_28
- #endif
-#endif
-],
-GLIBC_VERSION="2.8")
-
-AC_EGREP_CPP([GLIBC_29], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 9)
-  GLIBC_29
- #endif
-#endif
-],
-GLIBC_VERSION="2.9")
+AC_CHECK_HEADER([features.h])

 
 

-AC_EGREP_CPP([GLIBC_210], [
+if test x$ac_cv_header_features_h = xyes; then
+  rm -f conftest.$ac_ext
+  cat <<_ACEOF >conftest.$ac_ext

 #include <features.h>
 #include <features.h>

-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 10)
-  GLIBC_210
- #endif
+#if defined(__GNU_LIBRARY__) && defined(__GLIBC__) && defined(__GLIBC_MINOR__)
+glibc version is: __GLIBC__ __GLIBC_MINOR__

 #endif
 #endif

-],
-GLIBC_VERSION="2.10")
-
-AC_EGREP_CPP([GLIBC_211], [
-#include <features.h>
-#ifdef __GNU_LIBRARY__
- #if (__GLIBC__ == 2 && __GLIBC_MINOR__ == 11)
-  GLIBC_211
- #endif
-#endif
-],
-GLIBC_VERSION="2.11")
+_ACEOF
+  GLIBC_VERSION="`$CPP conftest.$ac_ext | $SED -n 's/^glibc version is: //p' | $SED 's/ /./g'`"
+fi

 
 AC_EGREP_CPP([AIX5_LIBC], [
 #include <standards.h>
 
 AC_EGREP_CPP([AIX5_LIBC], [
 #include <standards.h>


@@ -798,6 +765,13 @@ case "${GLIBC_VERSION}" in
        GENERATED_SUPP="glibc-2.X.supp ${GENERATED_SUPP}"
        DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}"
        DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}"
        GENERATED_SUPP="glibc-2.X.supp ${GENERATED_SUPP}"
        DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}"
        DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}"

+        ;;
+     2.12)
+       AC_MSG_RESULT(2.12 family)
+       AC_DEFINE([GLIBC_2_12], 1, [Define to 1 if you're using glibc 2.12.x])
+       DEFAULT_SUPP="glibc-2.X.supp ${DEFAULT_SUPP}"
+       DEFAULT_SUPP="glibc-2.34567-NPTL-helgrind.supp ${DEFAULT_SUPP}"
+       DEFAULT_SUPP="glibc-2.X-drd.supp ${DEFAULT_SUPP}"

        ;;
      aix5)
        AC_MSG_RESULT(AIX 5.1 or 5.2 or 5.3)
        ;;
      aix5)
        AC_MSG_RESULT(AIX 5.1 or 5.2 or 5.3)


@@ -811,8 +785,8 @@ case "${GLIBC_VERSION}" in
        ;;
 
      *)
        ;;
 
      *)

-       AC_MSG_RESULT(unsupported version)
-       AC_MSG_ERROR([Valgrind requires glibc version 2.2 - 2.11])
+       AC_MSG_RESULT([unsupported version ${GLIBC_VERSION}])
+       AC_MSG_ERROR([Valgrind requires glibc version 2.2 - 2.12])

        AC_MSG_ERROR([or AIX 5.1 or 5.2 or 5.3 GLIBC_VERSION])
        AC_MSG_ERROR([or Darwin libc])
        ;;
        AC_MSG_ERROR([or AIX 5.1 or 5.2 or 5.3 GLIBC_VERSION])
        AC_MSG_ERROR([or Darwin libc])
        ;;


@@ -1391,6 +1365,28 @@ AC_MSG_RESULT([no])
 CFLAGS=$safe_CFLAGS
 
 
 CFLAGS=$safe_CFLAGS
 
 

+# does the linker support -Wl,--build-id=none ?  Note, it's
+# important that we test indirectly via whichever C compiler
+# is selected, rather than testing /usr/bin/ld or whatever
+# directly.
+
+AC_MSG_CHECKING([if the linker accepts -Wl,--build-id=none])
+
+safe_CFLAGS=$CFLAGS
+CFLAGS="-Wl,--build-id=none"
+
+AC_LINK_IFELSE(
+[AC_LANG_PROGRAM([ ], [return 0;])],
+[
+  AC_SUBST([FLAG_NO_BUILD_ID], ["-Wl,--build-id=none"])
+  AC_MSG_RESULT([yes])
+], [
+  AC_SUBST([FLAG_NO_BUILD_ID], [""])
+  AC_MSG_RESULT([no])
+])
+CFLAGS=$safe_CFLAGS
+
+

 # does the ppc assembler support "mtocrf" et al?
 AC_MSG_CHECKING([if ppc32/64 as supports mtocrf/mfocrf])
 
 # does the ppc assembler support "mtocrf" et al?
 AC_MSG_CHECKING([if ppc32/64 as supports mtocrf/mfocrf])
 


@@ -1916,12 +1912,14 @@ AC_CONFIG_FILES([
    memcheck/tests/x86/Makefile
    memcheck/tests/linux/Makefile
    memcheck/tests/darwin/Makefile
    memcheck/tests/x86/Makefile
    memcheck/tests/linux/Makefile
    memcheck/tests/darwin/Makefile

+   memcheck/tests/amd64-linux/Makefile

    memcheck/tests/x86-linux/Makefile
    memcheck/perf/Makefile
    cachegrind/Makefile
    cachegrind/tests/Makefile
    cachegrind/tests/x86/Makefile
    cachegrind/cg_annotate
    memcheck/tests/x86-linux/Makefile
    memcheck/perf/Makefile
    cachegrind/Makefile
    cachegrind/tests/Makefile
    cachegrind/tests/x86/Makefile
    cachegrind/cg_annotate

+   cachegrind/cg_diff

    callgrind/Makefile
    callgrind/callgrind_annotate
    callgrind/callgrind_control
    callgrind/Makefile
    callgrind/callgrind_annotate
    callgrind/callgrind_control


@@ -1956,6 +1954,14 @@ AC_CONFIG_FILES([
    exp-bbv/tests/amd64-linux/Makefile
    exp-bbv/tests/ppc32-linux/Makefile
 ])
    exp-bbv/tests/amd64-linux/Makefile
    exp-bbv/tests/ppc32-linux/Makefile
 ])

+AC_CONFIG_FILES([coregrind/link_tool_exe_linux],
+                [chmod +x coregrind/link_tool_exe_linux])
+AC_CONFIG_FILES([coregrind/link_tool_exe_darwin],
+                [chmod +x coregrind/link_tool_exe_darwin])
+AC_CONFIG_FILES([coregrind/link_tool_exe_aix5],
+                [chmod +x coregrind/link_tool_exe_aix5])
+AC_CONFIG_FILES([coregrind/link_tool_exe_l4re],
+                [chmod +x coregrind/link_tool_exe_l4re])

 AC_OUTPUT
 
 cat<<EOF
 AC_OUTPUT
 
 cat<<EOF

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/Makefile.am
index 1195c9894729ebbd70dafe66e4f7ddcd69eb3e12..c5a876c61271e1cae597d3b46be3f6fc201ca369 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/Makefile.am
@@ -59,12 +59,18 @@ valgrind_CFLAGS    = $(AM_CFLAGS_PRI)
 valgrind_CXXFLAGS  = $(AM_CXXFLAGS_PRI)
 valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 valgrind_LDFLAGS   = $(AM_CFLAGS_PRI)
 valgrind_CXXFLAGS  = $(AM_CXXFLAGS_PRI)
 valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 valgrind_LDFLAGS   = $(AM_CFLAGS_PRI)

+if VGCONF_PLATFORMS_INCLUDE_X86_DARWIN
+valgrind_LDFLAGS   += -Wl,-read_only_relocs -Wl,suppress
+endif

 
 no_op_client_for_valgrind_SOURCES = no_op_client_for_valgrind.c
 no_op_client_for_valgrind_CPPFLAGS  = $(AM_CPPFLAGS_PRI)
 no_op_client_for_valgrind_CFLAGS    = $(AM_CFLAGS_PRI)
 no_op_client_for_valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 no_op_client_for_valgrind_LDFLAGS   = $(AM_CFLAGS_PRI)
 
 no_op_client_for_valgrind_SOURCES = no_op_client_for_valgrind.c
 no_op_client_for_valgrind_CPPFLAGS  = $(AM_CPPFLAGS_PRI)
 no_op_client_for_valgrind_CFLAGS    = $(AM_CFLAGS_PRI)
 no_op_client_for_valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 no_op_client_for_valgrind_LDFLAGS   = $(AM_CFLAGS_PRI)

+if VGCONF_PLATFORMS_INCLUDE_X86_DARWIN
+no_op_client_for_valgrind_LDFLAGS   += -Wl,-read_only_relocs -Wl,suppress
+endif

 
 #----------------------------------------------------------------------------
 # Darwin Mach stuff
 
 #----------------------------------------------------------------------------
 # Darwin Mach stuff


@@ -114,11 +120,13 @@ mach_defs += \
         /usr/include/mach/vm_map.defs
 endif
 
         /usr/include/mach/vm_map.defs
 endif
 

-# Be careful w.r.t. parellel builds.  See section 27.9 of the automake info
+# Be careful w.r.t. parallel builds.  See section 27.9 of the automake info

 # page, "Handling Tools that Produce many Outputs".
 # page, "Handling Tools that Produce many Outputs".

-$(mach_user_srcs): $(mach_defs)
+$(abs_builddir)/m_mach: 
+       mkdir -p $@
+$(mach_user_srcs): $(mach_defs) $(abs_builddir)/m_mach

        (cd m_mach && mig $(mach_defs))
        (cd m_mach && mig $(mach_defs))

-$(mach_hdrs): $(mach_defs) $(mach_user_srcs)
+$(mach_hdrs): $(mach_defs) $(mach_user_srcs) $(abs_builddir)/m_mach

        (cd m_mach && mig $(mach_defs))
 
 #----------------------------------------------------------------------------
        (cd m_mach && mig $(mach_defs))
 
 #----------------------------------------------------------------------------


@@ -311,8 +319,6 @@ COREGRIND_SOURCES_COMMON = \
        m_sigframe/sigframe-ppc64-aix5.c \
        m_sigframe/sigframe-x86-darwin.c \
        m_sigframe/sigframe-amd64-darwin.c \
        m_sigframe/sigframe-ppc64-aix5.c \
        m_sigframe/sigframe-x86-darwin.c \
        m_sigframe/sigframe-amd64-darwin.c \

-       m_start-x86-darwin.S \
-       m_start-amd64-darwin.S \

        m_syswrap/syscall-x86-linux.S \
        m_syswrap/syscall-amd64-linux.S \
        m_syswrap/syscall-ppc32-linux.S \
        m_syswrap/syscall-x86-linux.S \
        m_syswrap/syscall-amd64-linux.S \
        m_syswrap/syscall-ppc32-linux.S \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/Makefile.in
index e465639be6ea93bc8b3bb00c35bdc75ab8163f91..8d3ef7b3537557e3324993205c0d90fbc6e268d1 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/Makefile.in
@@ -48,35 +48,40 @@ POST_UNINSTALL = :
 build_triplet = @build@
 host_triplet = @host@
 DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \
 build_triplet = @build@
 host_triplet = @host@
 DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \

-       $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am
+       $(srcdir)/Makefile.in $(srcdir)/link_tool_exe_aix5.in \
+       $(srcdir)/link_tool_exe_darwin.in \
+       $(srcdir)/link_tool_exe_l4re.in \
+       $(srcdir)/link_tool_exe_linux.in $(top_srcdir)/Makefile.all.am

 @VGCONF_OS_IS_L4RE_FALSE@bin_PROGRAMS = valgrind$(EXEEXT) \
 @VGCONF_OS_IS_L4RE_FALSE@      no_op_client_for_valgrind$(EXEEXT)
 @VGCONF_OS_IS_L4RE_FALSE@bin_PROGRAMS = valgrind$(EXEEXT) \
 @VGCONF_OS_IS_L4RE_FALSE@      no_op_client_for_valgrind$(EXEEXT)

-@VGCONF_OS_IS_DARWIN_TRUE@am__append_1 = \
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_1 = -Wl,-read_only_relocs -Wl,suppress
+@VGCONF_PLATFORMS_INCLUDE_X86_DARWIN_TRUE@am__append_2 = -Wl,-read_only_relocs -Wl,suppress
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_3 = \

 @VGCONF_OS_IS_DARWIN_TRUE@     m_mach/mach_vmUser.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/taskUser.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/thread_actUser.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/vm_mapUser.c
 
 @VGCONF_OS_IS_DARWIN_TRUE@     m_mach/mach_vmUser.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/taskUser.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/thread_actUser.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/vm_mapUser.c
 

-@VGCONF_OS_IS_DARWIN_TRUE@am__append_2 = \
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_4 = \

 @VGCONF_OS_IS_DARWIN_TRUE@     m_mach/mach_vmServer.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/taskServer.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/thread_actServer.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/vm_mapServer.c
 
 @VGCONF_OS_IS_DARWIN_TRUE@     m_mach/mach_vmServer.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/taskServer.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/thread_actServer.c \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/vm_mapServer.c
 

-@VGCONF_OS_IS_DARWIN_TRUE@am__append_3 = \
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_5 = \

 @VGCONF_OS_IS_DARWIN_TRUE@     m_mach/mach_vm.h \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/task.h \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/thread_act.h \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/vm_map.h
 
 @VGCONF_OS_IS_DARWIN_TRUE@     m_mach/mach_vm.h \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/task.h \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/thread_act.h \
 @VGCONF_OS_IS_DARWIN_TRUE@        m_mach/vm_map.h
 

-@VGCONF_OS_IS_DARWIN_TRUE@am__append_4 = \
+@VGCONF_OS_IS_DARWIN_TRUE@am__append_6 = \

 @VGCONF_OS_IS_DARWIN_TRUE@     /usr/include/mach/mach_vm.defs \
 @VGCONF_OS_IS_DARWIN_TRUE@        /usr/include/mach/task.defs \
 @VGCONF_OS_IS_DARWIN_TRUE@        /usr/include/mach/thread_act.defs \
 @VGCONF_OS_IS_DARWIN_TRUE@        /usr/include/mach/vm_map.defs
 
 @VGCONF_OS_IS_DARWIN_TRUE@     /usr/include/mach/mach_vm.defs \
 @VGCONF_OS_IS_DARWIN_TRUE@        /usr/include/mach/task.defs \
 @VGCONF_OS_IS_DARWIN_TRUE@        /usr/include/mach/thread_act.defs \
 @VGCONF_OS_IS_DARWIN_TRUE@        /usr/include/mach/vm_map.defs
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_5 = libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
-@VGCONF_OS_IS_L4RE_TRUE@am__append_6 = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_7 = libcoregrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+@VGCONF_OS_IS_L4RE_TRUE@am__append_8 = \

 @VGCONF_OS_IS_L4RE_TRUE@       l4re_helper.c \
 @VGCONF_OS_IS_L4RE_TRUE@       l4re_trampoline.c \
 @VGCONF_OS_IS_L4RE_TRUE@       l4re/vcap.cpp \
 @VGCONF_OS_IS_L4RE_TRUE@       l4re_helper.c \
 @VGCONF_OS_IS_L4RE_TRUE@       l4re_trampoline.c \
 @VGCONF_OS_IS_L4RE_TRUE@       l4re/vcap.cpp \


@@ -91,11 +96,11 @@ DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \
 @VGCONF_OS_IS_L4RE_TRUE@       m_initimg/initimg-l4re.c \
 @VGCONF_OS_IS_L4RE_TRUE@       m_dispatch/dispatch-x86-l4re.S
 
 @VGCONF_OS_IS_L4RE_TRUE@       m_initimg/initimg-l4re.c \
 @VGCONF_OS_IS_L4RE_TRUE@       m_dispatch/dispatch-x86-l4re.S
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_7 = libreplacemalloc_toolpreload-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_9 = libreplacemalloc_toolpreload-@VGCONF_ARCH_SEC@-@VGCONF_OS@.a

 noinst_PROGRAMS =  \
        vgpreload_core-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_1)
 noinst_PROGRAMS =  \
        vgpreload_core-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_1)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_8 = vgpreload_core-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_10 = vgpreload_core-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so

 subdir = coregrind
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = coregrind
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -103,7 +108,8 @@ am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
        $(ACLOCAL_M4)
 mkinstalldirs = $(install_sh) -d
 CONFIG_HEADER = $(top_builddir)/config.h
        $(ACLOCAL_M4)
 mkinstalldirs = $(install_sh) -d
 CONFIG_HEADER = $(top_builddir)/config.h

-CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_FILES = link_tool_exe_linux link_tool_exe_darwin \
+       link_tool_exe_aix5 link_tool_exe_l4re

 CONFIG_CLEAN_VPATH_FILES =
 am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
 am__vpath_adj = case $$p in \
 CONFIG_CLEAN_VPATH_FILES =
 am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
 am__vpath_adj = case $$p in \


@@ -174,9 +180,8 @@ am__libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES_DIST =  \
        m_sigframe/sigframe-ppc32-aix5.c \
        m_sigframe/sigframe-ppc64-aix5.c \
        m_sigframe/sigframe-x86-darwin.c \
        m_sigframe/sigframe-ppc32-aix5.c \
        m_sigframe/sigframe-ppc64-aix5.c \
        m_sigframe/sigframe-x86-darwin.c \

-       m_sigframe/sigframe-amd64-darwin.c m_start-x86-darwin.S \
-       m_start-amd64-darwin.S m_syswrap/syscall-x86-linux.S \
-       m_syswrap/syscall-amd64-linux.S \
+       m_sigframe/sigframe-amd64-darwin.c \
+       m_syswrap/syscall-x86-linux.S m_syswrap/syscall-amd64-linux.S \

        m_syswrap/syscall-ppc32-linux.S \
        m_syswrap/syscall-ppc64-linux.S m_syswrap/syscall-arm-linux.S \
        m_syswrap/syscall-ppc32-aix5.S m_syswrap/syscall-ppc64-aix5.S \
        m_syswrap/syscall-ppc32-linux.S \
        m_syswrap/syscall-ppc64-linux.S m_syswrap/syscall-arm-linux.S \
        m_syswrap/syscall-ppc32-aix5.S m_syswrap/syscall-ppc64-aix5.S \


@@ -297,8 +302,6 @@ am__objects_2 = libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_commandline.$(OBJ
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-aix5.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-ppc64-aix5.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \

-       libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.$(OBJEXT) \
-       libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-amd64-darwin.$(OBJEXT) \

        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-amd64-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-ppc32-linux.$(OBJEXT) \


@@ -386,9 +389,8 @@ am__libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_SOURCES_DIST =  \
        m_sigframe/sigframe-ppc32-aix5.c \
        m_sigframe/sigframe-ppc64-aix5.c \
        m_sigframe/sigframe-x86-darwin.c \
        m_sigframe/sigframe-ppc32-aix5.c \
        m_sigframe/sigframe-ppc64-aix5.c \
        m_sigframe/sigframe-x86-darwin.c \

-       m_sigframe/sigframe-amd64-darwin.c m_start-x86-darwin.S \
-       m_start-amd64-darwin.S m_syswrap/syscall-x86-linux.S \
-       m_syswrap/syscall-amd64-linux.S \
+       m_sigframe/sigframe-amd64-darwin.c \
+       m_syswrap/syscall-x86-linux.S m_syswrap/syscall-amd64-linux.S \

        m_syswrap/syscall-ppc32-linux.S \
        m_syswrap/syscall-ppc64-linux.S m_syswrap/syscall-arm-linux.S \
        m_syswrap/syscall-ppc32-aix5.S m_syswrap/syscall-ppc64-aix5.S \
        m_syswrap/syscall-ppc32-linux.S \
        m_syswrap/syscall-ppc64-linux.S m_syswrap/syscall-arm-linux.S \
        m_syswrap/syscall-ppc32-aix5.S m_syswrap/syscall-ppc64-aix5.S \


@@ -509,8 +511,6 @@ am__objects_7 = libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_commandline.$(OBJ
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-aix5.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-ppc64-aix5.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-x86-darwin.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-sigframe-amd64-darwin.$(OBJEXT) \

-       libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.$(OBJEXT) \
-       libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.$(OBJEXT) \

        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-amd64-linux.$(OBJEXT) \
        libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-ppc32-linux.$(OBJEXT) \


@@ -682,6 +682,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -716,14 +717,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -806,7 +811,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 
 #----------------------------------------------------------------------------
 # Basics, flags
 
 #----------------------------------------------------------------------------
 # Basics, flags


@@ -879,7 +886,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -894,8 +901,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -960,12 +967,12 @@ valgrind_CPPFLAGS = $(AM_CPPFLAGS_PRI)
 valgrind_CFLAGS = $(AM_CFLAGS_PRI)
 valgrind_CXXFLAGS = $(AM_CXXFLAGS_PRI)
 valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 valgrind_CFLAGS = $(AM_CFLAGS_PRI)
 valgrind_CXXFLAGS = $(AM_CXXFLAGS_PRI)
 valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)

-valgrind_LDFLAGS = $(AM_CFLAGS_PRI)
+valgrind_LDFLAGS = $(AM_CFLAGS_PRI) $(am__append_1)

 no_op_client_for_valgrind_SOURCES = no_op_client_for_valgrind.c
 no_op_client_for_valgrind_CPPFLAGS = $(AM_CPPFLAGS_PRI)
 no_op_client_for_valgrind_CFLAGS = $(AM_CFLAGS_PRI)
 no_op_client_for_valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)
 no_op_client_for_valgrind_SOURCES = no_op_client_for_valgrind.c
 no_op_client_for_valgrind_CPPFLAGS = $(AM_CPPFLAGS_PRI)
 no_op_client_for_valgrind_CFLAGS = $(AM_CFLAGS_PRI)
 no_op_client_for_valgrind_CCASFLAGS = $(AM_CCASFLAGS_PRI)

-no_op_client_for_valgrind_LDFLAGS = $(AM_CFLAGS_PRI)
+no_op_client_for_valgrind_LDFLAGS = $(AM_CFLAGS_PRI) $(am__append_2)

 
 #----------------------------------------------------------------------------
 # Darwin Mach stuff
 
 #----------------------------------------------------------------------------
 # Darwin Mach stuff


@@ -988,10 +995,10 @@ no_op_client_for_valgrind_LDFLAGS = $(AM_CFLAGS_PRI)
 #      processor.defs \
 #      processor_set.defs \
 #
 #      processor.defs \
 #      processor_set.defs \
 #

-mach_user_srcs = $(am__append_1)
-mach_server_srcs = $(am__append_2)
-mach_hdrs = $(am__append_3)
-mach_defs = $(am__append_4)
+mach_user_srcs = $(am__append_3)
+mach_server_srcs = $(am__append_4)
+mach_hdrs = $(am__append_5)
+mach_defs = $(am__append_6)

 
 #----------------------------------------------------------------------------
 # Headers
 
 #----------------------------------------------------------------------------
 # Headers


@@ -1092,9 +1099,9 @@ CLEANFILES = $(mach_user_srcs) $(mach_server_srcs) $(mach_hdrs)
 # libreplacemalloc_toolpreload-<platform>.a
 #----------------------------------------------------------------------------
 pkglib_LIBRARIES = libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
 # libreplacemalloc_toolpreload-<platform>.a
 #----------------------------------------------------------------------------
 pkglib_LIBRARIES = libcoregrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \

-       $(am__append_5) \
+       $(am__append_7) \

        libreplacemalloc_toolpreload-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \
        libreplacemalloc_toolpreload-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a \

-       $(am__append_7)
+       $(am__append_9)

 COREGRIND_SOURCES_COMMON = m_commandline.c m_clientstate.c m_cpuid.S \
        m_debugger.c m_debuglog.c m_errormgr.c m_execontext.c \
        m_hashtable.c m_libcbase.c m_libcassert.c m_libcfile.c \
 COREGRIND_SOURCES_COMMON = m_commandline.c m_clientstate.c m_cpuid.S \
        m_debugger.c m_debuglog.c m_errormgr.c m_execontext.c \
        m_hashtable.c m_libcbase.c m_libcassert.c m_libcfile.c \


@@ -1137,9 +1144,8 @@ COREGRIND_SOURCES_COMMON = m_commandline.c m_clientstate.c m_cpuid.S \
        m_sigframe/sigframe-ppc32-aix5.c \
        m_sigframe/sigframe-ppc64-aix5.c \
        m_sigframe/sigframe-x86-darwin.c \
        m_sigframe/sigframe-ppc32-aix5.c \
        m_sigframe/sigframe-ppc64-aix5.c \
        m_sigframe/sigframe-x86-darwin.c \

-       m_sigframe/sigframe-amd64-darwin.c m_start-x86-darwin.S \
-       m_start-amd64-darwin.S m_syswrap/syscall-x86-linux.S \
-       m_syswrap/syscall-amd64-linux.S \
+       m_sigframe/sigframe-amd64-darwin.c \
+       m_syswrap/syscall-x86-linux.S m_syswrap/syscall-amd64-linux.S \

        m_syswrap/syscall-ppc32-linux.S \
        m_syswrap/syscall-ppc64-linux.S m_syswrap/syscall-arm-linux.S \
        m_syswrap/syscall-ppc32-aix5.S m_syswrap/syscall-ppc64-aix5.S \
        m_syswrap/syscall-ppc32-linux.S \
        m_syswrap/syscall-ppc64-linux.S m_syswrap/syscall-arm-linux.S \
        m_syswrap/syscall-ppc32-aix5.S m_syswrap/syscall-ppc64-aix5.S \


@@ -1154,7 +1160,7 @@ COREGRIND_SOURCES_COMMON = m_commandline.c m_clientstate.c m_cpuid.S \
        m_syswrap/syswrap-ppc32-aix5.c m_syswrap/syswrap-ppc64-aix5.c \
        m_syswrap/syswrap-x86-darwin.c \
        m_syswrap/syswrap-amd64-darwin.c m_ume/elf.c m_ume/macho.c \
        m_syswrap/syswrap-ppc32-aix5.c m_syswrap/syswrap-ppc64-aix5.c \
        m_syswrap/syswrap-x86-darwin.c \
        m_syswrap/syswrap-amd64-darwin.c m_ume/elf.c m_ume/macho.c \

-       m_ume/main.c m_ume/script.c $(am__append_6)
+       m_ume/main.c m_ume/script.c $(am__append_8)

 libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_DEPENDENCIES = blub.o
 libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES = \
     $(COREGRIND_SOURCES_COMMON)
 libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_DEPENDENCIES = blub.o
 libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_SOURCES = \
     $(COREGRIND_SOURCES_COMMON)


@@ -1269,6 +1275,14 @@ $(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
 $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
        cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
 $(am__aclocal_m4_deps):
 $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
        cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
 $(am__aclocal_m4_deps):

+link_tool_exe_linux: $(top_builddir)/config.status $(srcdir)/link_tool_exe_linux.in
+       cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+link_tool_exe_darwin: $(top_builddir)/config.status $(srcdir)/link_tool_exe_darwin.in
+       cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+link_tool_exe_aix5: $(top_builddir)/config.status $(srcdir)/link_tool_exe_aix5.in
+       cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@
+link_tool_exe_l4re: $(top_builddir)/config.status $(srcdir)/link_tool_exe_l4re.in
+       cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@

 install-pkglibLIBRARIES: $(pkglib_LIBRARIES)
        @$(NORMAL_INSTALL)
        test -z "$(pkglibdir)" || $(MKDIR_P) "$(DESTDIR)$(pkglibdir)"
 install-pkglibLIBRARIES: $(pkglib_LIBRARIES)
        @$(NORMAL_INSTALL)
        test -z "$(pkglibdir)" || $(MKDIR_P) "$(DESTDIR)$(pkglibdir)"


@@ -1436,8 +1450,6 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_sparsewa.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacks.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_stacktrace.Po@am__quote@

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-amd64-darwin.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_syscall.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_threadstate.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_tooliface.Po@am__quote@


@@ -1571,8 +1583,6 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_sparsewa.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacks.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_stacktrace.Po@am__quote@

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_syscall.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_threadstate.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_tooliface.Po@am__quote@


@@ -1853,34 +1863,6 @@ libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj: m_mach
 @AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCCAS_FALSE@        $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj `if test -f 'm_mach/mach_traps-amd64-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-amd64-darwin.S'; fi`
 
 @AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCCAS_FALSE@        $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj `if test -f 'm_mach/mach_traps-amd64-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-amd64-darwin.S'; fi`
 

-libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.o: m_start-x86-darwin.S
-@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.o `test -f 'm_start-x86-darwin.S' || echo '$(srcdir)/'`m_start-x86-darwin.S
-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.Po
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='m_start-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-@am__fastdepCCAS_FALSE@        $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.o `test -f 'm_start-x86-darwin.S' || echo '$(srcdir)/'`m_start-x86-darwin.S
-
-libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.obj: m_start-x86-darwin.S
-@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.obj `if test -f 'm_start-x86-darwin.S'; then $(CYGPATH_W) 'm_start-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_start-x86-darwin.S'; fi`
-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.Po
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='m_start-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-x86-darwin.obj' libtool=no @AMDEPBACKSLASH@
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-
-libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-amd64-darwin.o: m_start-amd64-darwin.S
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-
-libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-amd64-darwin.obj: m_start-amd64-darwin.S
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-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-amd64-darwin.Po
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='m_start-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-m_start-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
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-

 libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o: m_syswrap/syscall-x86-linux.S
 @am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o `test -f 'm_syswrap/syscall-x86-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-linux.S
 @am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Po
 libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o: m_syswrap/syscall-x86-linux.S
 @am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.o `test -f 'm_syswrap/syscall-x86-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-linux.S
 @am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a-syscall-x86-linux.Po


@@ -2217,34 +2199,6 @@ libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj: m_mach
 @AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCCAS_FALSE@        $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj `if test -f 'm_mach/mach_traps-amd64-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-amd64-darwin.S'; fi`
 
 @AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCCAS_FALSE@        $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-mach_traps-amd64-darwin.obj `if test -f 'm_mach/mach_traps-amd64-darwin.S'; then $(CYGPATH_W) 'm_mach/mach_traps-amd64-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_mach/mach_traps-amd64-darwin.S'; fi`
 

-libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.o: m_start-x86-darwin.S
-@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.o `test -f 'm_start-x86-darwin.S' || echo '$(srcdir)/'`m_start-x86-darwin.S
-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.Po
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='m_start-x86-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.o' libtool=no @AMDEPBACKSLASH@
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-
-libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.obj: m_start-x86-darwin.S
-@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.obj -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.obj `if test -f 'm_start-x86-darwin.S'; then $(CYGPATH_W) 'm_start-x86-darwin.S'; else $(CYGPATH_W) '$(srcdir)/m_start-x86-darwin.S'; fi`
-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-x86-darwin.Po
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-
-libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.o: m_start-amd64-darwin.S
-@am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.o `test -f 'm_start-amd64-darwin.S' || echo '$(srcdir)/'`m_start-amd64-darwin.S
-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.Po
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='m_start-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.o' libtool=no @AMDEPBACKSLASH@
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-
-libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.obj: m_start-amd64-darwin.S
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-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.Po
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='m_start-amd64-darwin.S' object='libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-m_start-amd64-darwin.obj' libtool=no @AMDEPBACKSLASH@
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-

 libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o: m_syswrap/syscall-x86-linux.S
 @am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o `test -f 'm_syswrap/syscall-x86-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-linux.S
 @am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Po
 libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o: m_syswrap/syscall-x86-linux.S
 @am__fastdepCCAS_TRUE@ $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CPPFLAGS) $(CPPFLAGS) $(libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a_CCASFLAGS) $(CCASFLAGS) -MT libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o -MD -MP -MF $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Tpo -c -o libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.o `test -f 'm_syswrap/syscall-x86-linux.S' || echo '$(srcdir)/'`m_syswrap/syscall-x86-linux.S
 @am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Tpo $(DEPDIR)/libcoregrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_a-syscall-x86-linux.Po


@@ -5891,11 +5845,13 @@ clean-noinst_DSYMS:
          rm -rf $$f.dSYM; \
        done
 
          rm -rf $$f.dSYM; \
        done
 

-# Be careful w.r.t. parellel builds.  See section 27.9 of the automake info
+# Be careful w.r.t. parallel builds.  See section 27.9 of the automake info

 # page, "Handling Tools that Produce many Outputs".
 # page, "Handling Tools that Produce many Outputs".

-$(mach_user_srcs): $(mach_defs)
+$(abs_builddir)/m_mach: 
+       mkdir -p $@
+$(mach_user_srcs): $(mach_defs) $(abs_builddir)/m_mach

        (cd m_mach && mig $(mach_defs))
        (cd m_mach && mig $(mach_defs))

-$(mach_hdrs): $(mach_defs) $(mach_user_srcs)
+$(mach_hdrs): $(mach_defs) $(mach_user_srcs) $(abs_builddir)/m_mach

        (cd m_mach && mig $(mach_defs))
 #libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_LIBADD = blub.o
 
        (cd m_mach && mig $(mach_defs))
 #libcoregrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_a_LIBADD = blub.o
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/l4re/vcap.cpp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/l4re/vcap.cpp
index 1e7f5d24815030b53408fa93229b87b067c40db3..9497c3cd21d6a357d885539aa93f15ae9e85486b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/l4re/vcap.cpp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/l4re/vcap.cpp
@@ -131,10 +131,9 @@ class Region_ops
             real_rm->reserve_area(&the_map_area, L4_PAGESIZE,
                                   L4Re::Rm::Reserved | L4Re::Rm::Search_addr);
             the_map_area_end = the_map_area + L4_PAGESIZE -1;
             real_rm->reserve_area(&the_map_area, L4_PAGESIZE,
                                   L4Re::Rm::Reserved | L4Re::Rm::Search_addr);
             the_map_area_end = the_map_area + L4_PAGESIZE -1;

-            unsigned prot;
-            prot |= VKI_PROT_READ;
-            prot |= VKI_PROT_WRITE;
-            prot |= VKI_PROT_EXEC;
+            unsigned prot =   VKI_PROT_READ
+                            | VKI_PROT_WRITE
+                            | VKI_PROT_EXEC;

 
             unsigned flags = VKI_MAP_ANONYMOUS;
 
 
             unsigned flags = VKI_MAP_ANONYMOUS;
 


@@ -194,18 +193,21 @@ class Region_ops
         static void unmap(MyRegion_handler const *h, l4_addr_t vaddr,
                         l4_addr_t offs, unsigned long size)
         {
         static void unmap(MyRegion_handler const *h, l4_addr_t vaddr,
                         l4_addr_t offs, unsigned long size)
         {

+            (void)h; (void)vaddr; (void)offs; (void)size;

             VG_(debugLog)(0, "vcap", "\n");
             enter_kdebug("Region_ops::unmap()");
         }
 
         static void take(MyRegion_handler const *h)
         {
             VG_(debugLog)(0, "vcap", "\n");
             enter_kdebug("Region_ops::unmap()");
         }
 
         static void take(MyRegion_handler const *h)
         {

+            (void)h;

             VG_(debugLog)(0, "vcap", "\n");
             enter_kdebug("Region_ops::take()");
         }
 
         static void release(MyRegion_handler const *h)
         {
             VG_(debugLog)(0, "vcap", "\n");
             enter_kdebug("Region_ops::take()");
         }
 
         static void release(MyRegion_handler const *h)
         {

+            (void)h;

             VG_(debugLog)(0, "vcap", "\n");
             enter_kdebug("Region_ops::release()");
         }
             VG_(debugLog)(0, "vcap", "\n");
             enter_kdebug("Region_ops::release()");
         }


@@ -458,8 +460,18 @@ class rm
         void *__find_free_segment(void *start, unsigned size)
         {
             Bool ok;
         void *__find_free_segment(void *start, unsigned size)
         {
             Bool ok;

-            void *ret = (void*)VG_(am_get_advisory_client_simple)((Addr)start,
-                                                                  size, &ok);
+            void *ret;
+
+            if (_id == VRMcap_client)
+                ret = (void*)VG_(am_get_advisory_client_simple)((Addr)start, size, &ok);
+            else if (_id == VRMcap_valgrind)
+                ret = (void*)VG_(am_get_advisory_valgrind_simple)((Addr)start, size, &ok);
+            else {
+                // should not happen!
+                VG_(printf)("Cannot determine the type of mapping here: %lx\n", _id);
+                enter_kdebug();
+            }
+

             if (!ok) {
                 VG_(debugLog)(0, "vcap", "Advisor has no free area for us!\n");
                 RM_ERROR;
             if (!ok) {
                 VG_(debugLog)(0, "vcap", "Advisor has no free area for us!\n");
                 RM_ERROR;


@@ -712,7 +724,7 @@ class rm
              * If there's no node ptr, something went wrong
              */
             if (!vg_seg->dsNodePtr) {
              * If there's no node ptr, something went wrong
              */
             if (!vg_seg->dsNodePtr) {

-                VG_(debugLog)(0, "vcap", "ERROR: no node ptr found for region %p - %p\n",
+                VG_(debugLog)(0, "vcap", "ERROR: no node ptr found for region %lx - %lx\n",

                               reg.start(), reg.end());
                 RM_ERROR;
             }
                               reg.start(), reg.end());
                 RM_ERROR;
             }


@@ -725,13 +737,13 @@ class rm
         }
 
 
         }
 
 

-        Node area_find(Region const &r) const throw()
+        Node area_find(Region const &) const throw()

         {
             enter_kdebug("area_find");
             return NULL;
         }
 
         {
             enter_kdebug("area_find");
             return NULL;
         }
 

-        void get_lists( l4_addr_t addr ) const throw()
+        void get_lists( l4_addr_t) const throw()

         {
             enter_kdebug("get_lists");
         }
         {
             enter_kdebug("get_lists");
         }


@@ -767,7 +779,6 @@ class Vcap_object : public L4::Server_object
         {
             if (dbg_vcap) VG_(debugLog)(4, "vcap", "dispatch\n");
 
         {
             if (dbg_vcap) VG_(debugLog)(4, "vcap", "dispatch\n");
 

-            int r;

             l4_msgtag_t t;
             ios >> t;
 
             l4_msgtag_t t;
             ios >> t;
 


@@ -792,12 +803,11 @@ class Vcap_object : public L4::Server_object
                 case L4Re::Protocol::Parent:
                     if (dbg_vcap) VG_(debugLog)(2, "vcap", "parent protocol\n");
                     enter_kdebug("parent");
                 case L4Re::Protocol::Parent:
                     if (dbg_vcap) VG_(debugLog)(2, "vcap", "parent protocol\n");
                     enter_kdebug("parent");

-                    break;
+                    return -L4_ENOSYS;

 
                 case L4_PROTO_IRQ:
                     if (dbg_vcap) VG_(debugLog)(2, "vcap", "irq protocol\n");
                     return _rm.dispatch(t, obj, ios);
 
                 case L4_PROTO_IRQ:
                     if (dbg_vcap) VG_(debugLog)(2, "vcap", "irq protocol\n");
                     return _rm.dispatch(t, obj, ios);

-                    break;

 
                 case L4_PROTO_EXCEPTION:
                     return handle_exception();
 
                 case L4_PROTO_EXCEPTION:
                     return handle_exception();


@@ -807,7 +817,7 @@ class Vcap_object : public L4::Server_object
                                   t.label(), t.label());
                     VG_(show_sched_status)();
                     enter_kdebug("Unknown protocol");
                                   t.label(), t.label());
                     VG_(show_sched_status)();
                     enter_kdebug("Unknown protocol");

-                    break;
+                    return -L4_ENOSYS;

             }
         }
 };
             }
         }
 };


@@ -831,7 +841,7 @@ L4::Cap<void> Vcap::Loop_hooks::rcv_cap;
 /*
  * Main VRM function
  */
 /*
  * Main VRM function
  */

-static void vcap_thread_fn(void *arg) L4_NOTHROW
+static void vcap_thread_fn(void *) L4_NOTHROW

 {
     VG_(debugLog)(1, "vcap", "%s: Here, vcap_running @ %p (%d)\n", __func__,
                   &vcap_running, vcap_running);
 {
     VG_(debugLog)(1, "vcap", "%s: Here, vcap_running @ %p (%d)\n", __func__,
                   &vcap_running, vcap_running);


@@ -982,7 +992,7 @@ void vrm_track_utcb_area()
     l4_fpage_t fp = L4Re::Env::env()->utcb_area();
     Addr start = l4_fpage_page(fp) << L4_PAGESHIFT;
     Addr end = start + (l4_fpage_size(fp) << L4_PAGESHIFT);
     l4_fpage_t fp = L4Re::Env::env()->utcb_area();
     Addr start = l4_fpage_page(fp) << L4_PAGESHIFT;
     Addr end = start + (l4_fpage_size(fp) << L4_PAGESHIFT);

-    VG_(debugLog)(4, "vcap", "TRACK(%p, %lx, 1, 1, 0, 0)\n", start, end-start);
+    VG_(debugLog)(4, "vcap", "TRACK(%lx, %lx, 1, 1, 0, 0)\n", start, end-start);

     VG_TRACK(new_mem_startup, start, end-start, True, True, False, 0);
 }
 
     VG_TRACK(new_mem_startup, start, end-start, True, True, False, 0);
 }
 


@@ -1006,6 +1016,15 @@ EXTERN_C void l4re_vcap_start_thread(void)
     main_thread_modify_rm(valgrind_obj.obj_cap());
 }
 
     main_thread_modify_rm(valgrind_obj.obj_cap());
 }
 

+/* The size of an L4Re::Env object is needed in setup_client_stack() which is
+   part of a C source code file and thus cannot determine the size of a C++ class
+   itself.
+ */
+EXTERN_C size_t l4re_env_env_size()
+{
+    return sizeof(L4Re::Env);
+}
+

 
 /*
  * Currently, the client sees all init caps Valgrind sees. In future versions we might
 
 /*
  * Currently, the client sees all init caps Valgrind sees. In future versions we might


@@ -1013,14 +1032,16 @@ EXTERN_C void l4re_vcap_start_thread(void)
  * pass the client this copy for usage. This is the place to filter out or modify these
  * caps before starting the client.
  */
  * pass the client this copy for usage. This is the place to filter out or modify these
  * caps before starting the client.
  */

-static L4Re::Env::Cap_entry* __copy_init_caps(L4Re::Env::Env const * const e)
+static L4Re::Env::Cap_entry* __copy_init_caps(L4Re::Env const * const e)

 {
     if (dbg_vcap) VG_(debugLog)(4, "vcap", "counting caps\n");
     L4Re::Env::Cap_entry const *c = e->initial_caps();
 {
     if (dbg_vcap) VG_(debugLog)(4, "vcap", "counting caps\n");
     L4Re::Env::Cap_entry const *c = e->initial_caps();

+

     unsigned cnt = 0;
     for ( ; c->flags != ~0UL; ++c, ++cnt)
         ;
     unsigned cnt = 0;
     for ( ; c->flags != ~0UL; ++c, ++cnt)
         ;

-    if (dbg_vcap) VG_(debugLog)(4, "vcap", "count: %lx\n", cnt+1);
+
+    if (dbg_vcap) VG_(debugLog)(4, "vcap", "count: %x\n", cnt+1);

 
     SysRes res = VG_(am_mmap_anon_float_client)((cnt+1) * sizeof(L4Re::Env::Cap_entry),
                                                 VKI_PROT_READ | VKI_PROT_WRITE);
 
     SysRes res = VG_(am_mmap_anon_float_client)((cnt+1) * sizeof(L4Re::Env::Cap_entry),
                                                 VKI_PROT_READ | VKI_PROT_WRITE);


@@ -1038,9 +1059,9 @@ static L4Re::Env::Cap_entry* __copy_init_caps(L4Re::Env::Env const * const e)
  * Modify client environment and make VRM be the handler for all
  * interesting events.
  */
  * Modify client environment and make VRM be the handler for all
  * interesting events.
  */

-EXTERN_C void *l4re_vcap_modify_env(struct ume_auxv *envp)
+EXTERN_C void *l4re_vcap_modify_env(struct ume_auxv *envp, Addr client_l4re_env_addr)

 {
 {

-    L4Re::Env::Env *e = new L4Re::Env::Env(*L4Re::Env::env());
+    L4Re::Env *e = new ((void*)client_l4re_env_addr) L4Re::Env(*L4Re::Env::env());

     VG_(debugLog)(0, "vcap", "  New env @ %p\n", e);
     VG_(debugLog)(0, "vcap", "  Orig env @ %p\n", L4Re::Env::env());
 
     VG_(debugLog)(0, "vcap", "  New env @ %p\n", e);
     VG_(debugLog)(0, "vcap", "  Orig env @ %p\n", L4Re::Env::env());
 


@@ -1054,7 +1075,7 @@ EXTERN_C void *l4re_vcap_modify_env(struct ume_auxv *envp)
     e->initial_caps(__copy_init_caps(e));
 
     client_env = (void *) e;
     e->initial_caps(__copy_init_caps(e));
 
     client_env = (void *) e;

-    client_env_size = sizeof(L4Re::Env::Env);
+    client_env_size = l4re_env_env_size();

 
     return e;
 }
 
     return e;
 }


@@ -1106,13 +1127,14 @@ void vrm_segment_fixup(NSegment *seg)
     unsigned flags     = 0;
     L4::Cap<L4Re::Dataspace> ds;
     int i = _rm->find(&addr, &size, &offset, &flags, &ds);
     unsigned flags     = 0;
     L4::Cap<L4Re::Dataspace> ds;
     int i = _rm->find(&addr, &size, &offset, &flags, &ds);

+    if (i && dbg_rm) VG_(debugLog)(2, "vcap", "vailed rm-find\n");

 
 

-    if (dbg_rm) VG_(debugLog)(2, "vcap", "%s: addr %p size %lx, cap %lx, offs %lx\n",
+    if (dbg_rm) VG_(debugLog)(2, "vcap", "%s: addr %lx size %lx, cap %lx, offs %lx\n",

                   __func__, addr, size, ds.cap(), offset);
 
     if (ds.is_valid())
         vrm_update_segptr(seg, ds.cap(), offset, flags);
                   __func__, addr, size, ds.cap(), offset);
 
     if (ds.is_valid())
         vrm_update_segptr(seg, ds.cap(), offset, flags);

-    if (dbg_rm) VG_(debugLog)(2, "vcap", "ds %lx node ptr @ %p\n", ds.cap(), seg->dsNodePtr);
+    if (dbg_rm) VG_(debugLog)(2, "vcap", "ds %lx node ptr @ %lx\n", ds.cap(), seg->dsNodePtr);

 }
 
 
 }
 
 


@@ -1151,7 +1173,7 @@ void vrm_update_segptr(NSegment *seg, l4_cap_idx_t dscap, unsigned offset, unsig
 
     VG_(am_set_nodeptr)(seg, (Addr)n);
     if (dbg_rm) {
 
     VG_(am_set_nodeptr)(seg, (Addr)n);
     if (dbg_rm) {

-        VG_(debugLog)(4, "vcap", "\033[32mupdate_segment %p (%p): node %p\033[0m\n",
+        VG_(debugLog)(4, "vcap", "\033[32mupdate_segment %lx (%lx): node %p\033[0m\n",

                       seg->start, seg, seg->dsNodePtr);
     }
 }
                       seg->start, seg, seg->dsNodePtr);
     }
 }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_aix5.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_aix5.in
new file mode 100644 (file)
index 0000000..b909db1
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_aix5.in
@@ -0,0 +1,6 @@
+#! @PERL@
+
+use warnings;
+use strict;
+
+die "link_tool_exe_@VGCONF_OS@ requires implementation";

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_darwin.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_darwin.in
new file mode 100644 (file)
index 0000000..be1a1d9
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_darwin.in
@@ -0,0 +1,173 @@
+#! @PERL@
+
+# This script handles linking the tool executables on Linux,
+# statically and at an alternative load address.
+#
+# Linking statically sidesteps all sorts of complications to do with
+# having two copies of the dynamic linker (valgrind's and the
+# client's) coexisting in the same process.  The alternative load
+# address is needed because Valgrind itself will load the client at
+# whatever address it specifies, which is almost invariably the
+# default load address.  Hence we can't allow Valgrind itself (viz,
+# the tool executable) to be loaded at that address.
+#
+# Unfortunately there's no standard way to do 'static link at
+# alternative address', so these link_tool_exe_*.in scripts handle
+# the per-platform hoop-jumping.
+#
+# What we get passed here is:
+#   first arg
+#      the alternative load address
+#   all the rest of the args
+#      the gcc invokation to do the final link, that
+#      the build system would have done, left to itself
+#
+# We just let the script 'die' if something is wrong, rather than do
+# proper error reporting.  We don't expect the users to run this 
+# directly.  It is only run as part of the build process, with 
+# carefully constrained inputs.
+#
+#
+# So: what we actually do is:
+#
+# Look at the specified gcc invokation.  Ignore all parts of it except
+# the *.a, *.o and -o outfile parts.  Wrap them up in a new command
+# which looks (eg) as follows:
+#
+#   (64-bit):
+#
+#   /usr/bin/ld -static -arch x86_64 -macosx_version_min 10.5 \
+#      -o memcheck-amd64-darwin -u __start -e __start \
+#      -image_base 0x138000000 -stack_addr 0x13c000000 \
+#      -stack_size 0x800000 \
+#      memcheck_amd*.o \
+#      ../coregrind/libcoregrind-amd64-darwin.a \
+#      ../VEX/libvex-amd64-darwin.a
+#
+#   (32-bit)
+#
+#   /usr/bin/ld -static -arch i386 -macosx_version_min 10.5 \
+#      -o memcheck-x86-darwin -u __start -e __start \
+#      -image_base 0x38000000 -stack_addr 0x3c000000 \
+#      -stack_size 0x800000 \
+#      memcheck_x86*.o \
+#      ../coregrind/libcoregrind-x86-darwin.a \
+#      ../VEX/libvex-x86-darwin.a
+#
+# The addresses shown above will actually work, although "for real" we
+# of course need to take it from argv[1].  In these examples the stack
+# is placed 64M after the executable start.  It is probably safer to
+# place it 64M before the executable's start point, so the executable
+# + data + bss can grow arbitrarily in future without colliding with
+# the stack.
+#
+# There's one more twist: we need to know the word size of the
+# executable for which we are linking.  We need to know this because
+# we must tell the linker that, by handing it either "-arch x86_64" or
+# "-arch i386".  Fortunately we can figure this out by scanning the
+# gcc invokation, which itself must contain either "-arch x86_64" or
+# "-arch i386".
+
+use warnings;
+use strict;
+# we need to be able to do 64-bit arithmetic:
+use Math::BigInt;
+
+
+# User configurable constants: how far before the exe should we
+# place the stack?
+my $TX_STACK_OFFSET_BEFORE_TEXT = 64 * 1024 * 1024;
+
+# and how big should the stack be?
+my $TX_STACK_SIZE = 8 * 1024 * 1024;
+
+
+# string -> bool
+sub is_dota_or_doto($)
+{
+   my ($str) = @_;
+   if ($str =~ /.\.a$/ || $str =~ /.\.o$/) {
+      return 1;
+   } else {
+      return 0;
+   }
+}
+
+
+# expect at least: alt-load-address gcc -o foo bar.o
+die "Not enough arguments"
+    if (($#ARGV + 1) < 5);
+
+my $ala = $ARGV[0];
+
+# check for plausible-ish alt load address
+die "Bogus alt-load address (1)"
+    if (length($ala) < 3 || index($ala, "0x") != 0);
+
+die "Bogus alt-load address (2)"
+    if ($ala !~ /^0x[0-9a-fA-F]+$/);
+
+
+# get hold of the outfile name (following "-o")
+my $outname = "";
+
+foreach my $n (2 .. $#ARGV - 1) {
+    my $str = $ARGV[$n];
+    if ($str eq "-o" && $outname eq "") {
+        $outname = $ARGV[$n + 1];
+    }
+}
+
+die "Can't find '-o outfilename' in command line"
+    if ($outname eq "");
+
+
+# get hold of the string following "-arch"
+my $archstr = "";
+
+foreach my $n (2 .. $#ARGV - 1) {
+    my $str = $ARGV[$n];
+    if ($str eq "-arch" && $archstr eq "") {
+        $archstr = $ARGV[$n + 1];
+    }
+}
+
+die "Can't find '-arch archstr' in command line"
+    if ($archstr eq "");
+
+
+# build the command line
+my $cmd = "/usr/bin/ld";
+
+$cmd = "$cmd -static";
+$cmd = "$cmd -arch $archstr";
+$cmd = "$cmd -macosx_version_min 10.5";
+$cmd = "$cmd -o $outname";
+$cmd = "$cmd -u __start -e __start";
+
+my $stack_addr = Math::BigInt->new( $ala ) - $TX_STACK_OFFSET_BEFORE_TEXT;
+my $stack_addr_str = $stack_addr->as_hex();
+my $stack_size_str = Math::BigInt::as_hex($TX_STACK_SIZE);
+
+$cmd = "$cmd -image_base $ala";
+$cmd = "$cmd -stack_addr $stack_addr_str";
+$cmd = "$cmd -stack_size $stack_size_str";
+
+foreach my $n (2 .. $#ARGV) {
+    my $str = $ARGV[$n];
+    if (is_dota_or_doto($str)) {
+        $cmd = "$cmd $str";
+    }
+}
+
+#print "link_tool_exe_darwin: $cmd\n";
+
+
+# Execute the command:
+my $r = system("$cmd");
+
+if ($r == 0) {
+    exit 0;
+} else {
+    exit 1;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_l4re.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_l4re.in
new file mode 100644 (file)
index 0000000..94d36a4
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_l4re.in
@@ -0,0 +1,88 @@
+#! @PERL@
+
+# This script handles linking the tool executables on Linux for L4Re,
+# statically and at an alternative load address.
+#
+# Linking statically sidesteps all sorts of complications to do with
+# having two copies of the dynamic linker (valgrind's and the
+# client's) coexisting in the same process.  The alternative load
+# address is needed because Valgrind itself will load the client at
+# whatever address it specifies, which is almost invariably the
+# default load address.  Hence we can't allow Valgrind itself (viz,
+# the tool executable) to be loaded at that address.
+#
+# Unfortunately there's no standard way to do 'static link at
+# alternative address', so these link_tool_exe_*.in scripts handle
+# the per-platform hoop-jumping.
+#
+# What we get passed here is:
+#   first arg
+#      the alternative load address
+#   all the rest of the args
+#      the gcc invokation to do the final link, that
+#      the build system would have done, left to itself
+#
+# We just let the script 'die' if something is wrong, rather than do
+# proper error reporting.  We don't expect the users to run this 
+# directly.  It is only run as part of the build process, with 
+# carefully constrained inputs.
+#
+# Linux/L4Re specific complications:
+#
+# - need to support both old GNU ld and gold: use -Ttext= to
+#   set the text segment address.
+#
+# - need to pass --build-id=none (that is, -Wl,--build-id=none to
+#   gcc) if it accepts it, to ensure the linker doesn't add a
+#   notes section which ends up at the default load address and
+#   so defeats our attempts to keep that address clear for the
+#   client.  However, older linkers don't support this flag, so it
+#   is tested for by configure.in and is shipped to us as part of
+#   argv[2 ..].
+#
+# - need to specify a custom L4Re linker script: this is passed
+#   by the L4Re build system through an environment variable and
+#   we just need to read this out
+#
+#
+# So: what we actually do:
+# 
+#   pass the specified command to the linker as-is, except, add
+#   "-static" and "-Ttext=<argv[1]>" and "-T$ENV["L4_LDS_stat_bin"]" to it.
+#
+
+use warnings;
+use strict;
+
+# expect at least: alt-load-address gcc -o foo bar.o
+die "Not enough arguments"
+    if (($#ARGV + 1) < 5);
+
+my $ala = $ARGV[0];
+
+# check for plausible-ish alt load address
+die "Bogus alt-load address"
+    if (length($ala) < 3 || index($ala, "0x") != 0);
+
+my $linkscript = $ENV{"L4_LDS_stat_bin"};
+my $cmdline = "";
+my $cmdadd  = " -static -Wl,-Ttext=$ala -Wl,-T$linkscript";
+
+# Add the rest of the parameters
+foreach my $n (1 .. $#ARGV) {
+   $cmdline = "$cmdline $ARGV[$n]";
+}
+
+$cmdline .= $cmdadd;
+
+print "link_tool_exe_l4re: $cmdline\n";
+
+
+# Execute the command:
+my $r = system("$cmdline");
+
+if ($r == 0) {
+    exit 0;
+} else {
+    exit 1;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_linux.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_linux.in
new file mode 100644 (file)
index 0000000..6de2562
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/link_tool_exe_linux.in
@@ -0,0 +1,88 @@
+#! @PERL@
+
+# This script handles linking the tool executables on Linux,
+# statically and at an alternative load address.
+#
+# Linking statically sidesteps all sorts of complications to do with
+# having two copies of the dynamic linker (valgrind's and the
+# client's) coexisting in the same process.  The alternative load
+# address is needed because Valgrind itself will load the client at
+# whatever address it specifies, which is almost invariably the
+# default load address.  Hence we can't allow Valgrind itself (viz,
+# the tool executable) to be loaded at that address.
+#
+# Unfortunately there's no standard way to do 'static link at
+# alternative address', so these link_tool_exe_*.in scripts handle
+# the per-platform hoop-jumping.
+#
+# What we get passed here is:
+#   first arg
+#      the alternative load address
+#   all the rest of the args
+#      the gcc invokation to do the final link, that
+#      the build system would have done, left to itself
+#
+# We just let the script 'die' if something is wrong, rather than do
+# proper error reporting.  We don't expect the users to run this 
+# directly.  It is only run as part of the build process, with 
+# carefully constrained inputs.
+#
+# Linux specific complications:
+#
+# - need to support both old GNU ld and gold: use -Ttext= to
+#   set the text segment address.
+#
+# - need to pass --build-id=none (that is, -Wl,--build-id=none to
+#   gcc) if it accepts it, to ensure the linker doesn't add a
+#   notes section which ends up at the default load address and
+#   so defeats our attempts to keep that address clear for the
+#   client.  However, older linkers don't support this flag, so it
+#   is tested for by configure.in and is shipped to us as part of
+#   argv[2 ..].
+#
+#
+# So: what we actually do:
+# 
+#   pass the specified command to the linker as-is, except, add
+#   "-static" and "-Ttext=<argv[1]>" to it.
+#
+
+use warnings;
+use strict;
+
+# expect at least: alt-load-address gcc -o foo bar.o
+die "Not enough arguments"
+    if (($#ARGV + 1) < 5);
+
+my $ala = $ARGV[0];
+
+# check for plausible-ish alt load address
+die "Bogus alt-load address"
+    if (length($ala) < 3 || index($ala, "0x") != 0);
+
+# The cc invokation to do the final link
+my $cc = $ARGV[1];
+
+# and the 'restargs' are argv[2 ..]
+
+# so, build up the complete command here:
+# 'cc' -static -Ttext='ala' 'restargs'
+
+my $cmd="$cc -static -Wl,-Ttext=$ala";
+
+# Add the rest of the parameters
+foreach my $n (2 .. $#ARGV) {
+   $cmd = "$cmd $ARGV[$n]";
+}
+
+#print "link_tool_exe_linux: $cmd\n";
+
+
+# Execute the command:
+my $r = system("$cmd");
+
+if ($r == 0) {
+    exit 0;
+} else {
+    exit 1;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_aspacemgr/aspacemgr-l4re.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_aspacemgr/aspacemgr-l4re.c
index c561568f21d8d9457b02c96c9027fe71a80466c2..8fc2ab2181476b4ccb7a9bcb893957fd67511206 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_aspacemgr/aspacemgr-l4re.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_aspacemgr/aspacemgr-l4re.c
@@ -1989,6 +1989,22 @@ Addr VG_(am_get_advisory_client_simple) ( Addr start, SizeT len,
 }
 
 
 }
 
 

+/* Convenience wrapper for VG_(am_get_advisory) for Valgrind floating or
+   fixed requests.  If start is zero, a floating request is issued; if
+   nonzero, a fixed request at that address is issued.  Same comments
+   about return values apply. */
+
+Addr VG_(am_get_advisory_valgrind_simple) ( Addr start, SizeT len, 
+                                                                                       /*OUT*/Bool* ok )
+{
+       MapRequest mreq;
+       mreq.rkind = start==0 ? MAny : MFixed;
+       mreq.start = start;
+       mreq.len   = len;
+       return VG_(am_get_advisory)( &mreq, False/*Valgrind*/, ok );
+}
+
+

 /* Notifies aspacem that the client completed an mmap successfully.
    The segment array is updated accordingly.  If the returned Bool is
    True, the caller should immediately discard translations from the
 /* Notifies aspacem that the client completed an mmap successfully.
    The segment array is updated accordingly.  If the returned Bool is
    True, the caller should immediately discard translations from the

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_aspacemgr/aspacemgr-linux.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_aspacemgr/aspacemgr-linux.c
index ae955a88915fe57209a8069c1ba19fc884d55b03..b911345e85fe276d6b6a2aca3544e71cfb2fcb76 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_aspacemgr/aspacemgr-linux.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_aspacemgr/aspacemgr-linux.c
@@ -3478,8 +3478,8 @@ static void add_mapping_callback(Addr addr, SizeT len, UInt prot,
 #        endif
          if (seg_prot != prot) {
              if (VG_(clo_trace_syscalls)) 
 #        endif
          if (seg_prot != prot) {
              if (VG_(clo_trace_syscalls)) 

-                 VG_(debugLog)(0,"aspacem","\nregion %p..%p permission "
-                                 "mismatch (kernel %x, V %x)", 
+                 VG_(debugLog)(0,"aspacem","region %p..%p permission "
+                                 "mismatch (kernel %x, V %x)\n", 

                                  (void*)nsegments[i].start,
                                  (void*)(nsegments[i].end+1), prot, seg_prot);
          }
                                  (void*)nsegments[i].start,
                                  (void*)(nsegments[i].end+1), prot, seg_prot);
          }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_clientstate.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_clientstate.c
index 7a27f44cae030fa2d6a084f3c37f483d4d186609..d6dc7b2a58d8212e4cd73026ba0c0edf169042de 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_clientstate.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_clientstate.c
@@ -75,7 +75,7 @@ Int VG_(args_for_valgrind_noexecpass) = 0;
 
 /* The name of the client executable, as specified on the command
    line. */
 
 /* The name of the client executable, as specified on the command
    line. */

-HChar* VG_(args_the_exename) = NULL;
+const HChar* VG_(args_the_exename) = NULL;

 
 // Client's original rlimit data and rlimit stack
 struct vki_rlimit VG_(client_rlimit_data);
 
 // Client's original rlimit data and rlimit stack
 struct vki_rlimit VG_(client_rlimit_data);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_coredump/coredump-elf.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_coredump/coredump-elf.c
index b9ca8d2a94a0321bd0caf2b492d28b367002205d..c47562ed71be76a9b89a5a48bc9d5bcb5e4ca920 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_coredump/coredump-elf.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_coredump/coredump-elf.c
@@ -340,7 +340,7 @@ static void fill_prstatus(const ThreadState *tst,
    regs->ARM_ip   = arch->vex.guest_R12;
    regs->ARM_sp   = arch->vex.guest_R13;
    regs->ARM_lr   = arch->vex.guest_R14;
    regs->ARM_ip   = arch->vex.guest_R12;
    regs->ARM_sp   = arch->vex.guest_R13;
    regs->ARM_lr   = arch->vex.guest_R14;

-   regs->ARM_pc   = arch->vex.guest_R15;
+   regs->ARM_pc   = arch->vex.guest_R15T;

    regs->ARM_cpsr = LibVEX_GuestARM_get_cpsr( &((ThreadArchState*)arch)->vex );
 
 #else
    regs->ARM_cpsr = LibVEX_GuestARM_get_cpsr( &((ThreadArchState*)arch)->vex );
 
 #else

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debugger.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debugger.c
index 6bf9128aad0babee9d6b05d602682f8d61be5cc5..8f3f9df69e24911eaf7a8aea1bf298504faf5f66 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debugger.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debugger.c
@@ -223,7 +223,7 @@ static Int ptrace_setregs(Int pid, VexGuestArchState* vex)
    uregs.ARM_ip   = vex->guest_R12; 
    uregs.ARM_sp   = vex->guest_R13; 
    uregs.ARM_lr   = vex->guest_R14; 
    uregs.ARM_ip   = vex->guest_R12; 
    uregs.ARM_sp   = vex->guest_R13; 
    uregs.ARM_lr   = vex->guest_R14; 

-   uregs.ARM_pc   = vex->guest_R15; 
+   uregs.ARM_pc   = vex->guest_R15T;

    uregs.ARM_cpsr = LibVEX_GuestARM_get_cpsr(vex);
    return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs);
 
    uregs.ARM_cpsr = LibVEX_GuestARM_get_cpsr(vex);
    return VG_(ptrace)(VKI_PTRACE_SETREGS, pid, NULL, &uregs);
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuginfo/readmacho.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuginfo/readmacho.c
index b6b746e4180f47681401ebd9adbe0733ce8531fb..68ba359f2121a2befb50ca6102e108e1cab22170 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuginfo/readmacho.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuginfo/readmacho.c
@@ -948,10 +948,12 @@ Bool ML_(read_macho_debug_info)( struct _DebugInfo* di )
      HChar* cmd = ML_(dinfo_zalloc)( "di.readmacho.tmp1", 
                                      VG_(strlen)(dsymutil)
                                      + VG_(strlen)(di->filename)
      HChar* cmd = ML_(dinfo_zalloc)( "di.readmacho.tmp1", 
                                      VG_(strlen)(dsymutil)
                                      + VG_(strlen)(di->filename)

-                                     + 30 /* misc */ );
+                                     + 32 /* misc */ );

      VG_(strcpy)(cmd, dsymutil);
      if (0) VG_(strcat)(cmd, "--verbose ");
      VG_(strcpy)(cmd, dsymutil);
      if (0) VG_(strcat)(cmd, "--verbose ");

+     VG_(strcat)(cmd, "\"");

      VG_(strcat)(cmd, di->filename);
      VG_(strcat)(cmd, di->filename);

+     VG_(strcat)(cmd, "\"");

      VG_(message)(Vg_DebugMsg, "run: %s\n", cmd);
      r = VG_(system)( cmd );
      if (r)
      VG_(message)(Vg_DebugMsg, "run: %s\n", cmd);
      r = VG_(system)( cmd );
      if (r)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuginfo/readpdb.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuginfo/readpdb.c
index d309593bf66e6ef708c50602361dc04ac9d7fb23..3920b0a019a20553173932fc07ce5924f6be4405 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuginfo/readpdb.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuginfo/readpdb.c
@@ -997,6 +997,11 @@ static void* pdb_ds_read( struct pdb_reader* pdb,
    UInt i;
 
    if (!size) return NULL;
    UInt i;
 
    if (!size) return NULL;

+   if (size > 512 * 1024 * 1024) {
+      VG_(umsg)("Warning: pdb_ds_read: implausible size "
+                "(%u); skipping -- possible invalid .pdb file?\n", size);
+      return NULL;
+   }

 
    blocksize = pdb->u.ds.header->block_size;
    nBlocks   = (size + blocksize - 1) / blocksize;
 
    blocksize = pdb->u.ds.header->block_size;
    nBlocks   = (size + blocksize - 1) / blocksize;

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuglog.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuglog.c
index cc07b1803809e14c81b52c64dba1f3fd59c50684..c018b60c03d1541d44e8482d271c365d22925f4a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuglog.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_debuglog.c
@@ -245,9 +245,9 @@ static UInt local_sys_write_stderr ( HChar* buf, Int n )
    block[0] = (Int)buf;
    block[1] = n;
    __asm__ volatile (
    block[0] = (Int)buf;
    block[1] = n;
    __asm__ volatile (

-      "mov  r0, #1\n\t"
-      "ldr  r1, [%0]\n\t"
-      "ldr  r2, [%0, #4]\n\t"
+      "mov  r0, #2\n\t"        /* stderr */
+      "ldr  r1, [%0]\n\t"      /* buf */
+      "ldr  r2, [%0, #4]\n\t"  /* n */

       "mov  r7, #"VG_STRINGIFY(__NR_write)"\n\t"
       "svc  0x0\n"          /* write() */
       "str  r0, [%0]\n\t"
       "mov  r7, #"VG_STRINGIFY(__NR_write)"\n\t"
       "svc  0x0\n"          /* write() */
       "str  r0, [%0]\n\t"

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_dispatch/dispatch-arm-linux.S b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_dispatch/dispatch-arm-linux.S
index f81ac2ac312992fcdd37ee81a8a825bf4c37c391..8c9281415306db010c80675a2bf0fc94aa8cdc47 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_dispatch/dispatch-arm-linux.S
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_dispatch/dispatch-arm-linux.S
@@ -1,4 +1,3 @@
-

 /*--------------------------------------------------------------------*/
 /*--- The core dispatch loop, for jumping to a code address.       ---*/
 /*---                                         dispatch-arm-linux.S ---*/
 /*--------------------------------------------------------------------*/
 /*--- The core dispatch loop, for jumping to a code address.       ---*/
 /*---                                         dispatch-arm-linux.S ---*/


@@ -30,6 +29,7 @@
 */
 
 #if defined(VGP_arm_linux)
 */
 
 #if defined(VGP_arm_linux)

+       .fpu vfp

 
 #include "pub_core_basics_asm.h"
 #include "pub_core_dispatch_asm.h"
 
 #include "pub_core_basics_asm.h"
 #include "pub_core_dispatch_asm.h"


@@ -63,7 +63,7 @@ VG_(run_innerloop):
         /* r0 (hence also [sp,#0]) holds guest_state */
         /* r1 holds do_profiling */
        mov r8, r0
         /* r0 (hence also [sp,#0]) holds guest_state */
         /* r1 holds do_profiling */
        mov r8, r0

-       ldr r0, [r8, #OFFSET_arm_R15]
+       ldr r0, [r8, #OFFSET_arm_R15T]

         
                /* fall into main loop (the right one) */
        cmp r1, #0      /* do_profiling */
         
                /* fall into main loop (the right one) */
        cmp r1, #0      /* do_profiling */


@@ -87,7 +87,7 @@ VG_(run_innerloop__dispatch_unprofiled):
        bne  gsp_changed
 
        /* save the jump address in the guest state */
        bne  gsp_changed
 
        /* save the jump address in the guest state */

-        str  r0, [r8, #OFFSET_arm_R15]
+        str  r0, [r8, #OFFSET_arm_R15T]

 
         /* Are we out of timeslice?  If yes, defer to scheduler. */
         ldr  r1, =VG_(dispatch_ctr)
 
         /* Are we out of timeslice?  If yes, defer to scheduler. */
         ldr  r1, =VG_(dispatch_ctr)


@@ -132,7 +132,7 @@ VG_(run_innerloop__dispatch_profiled):
        bne  gsp_changed
 
        /* save the jump address in the guest state */
        bne  gsp_changed
 
        /* save the jump address in the guest state */

-        str  r0, [r8, #OFFSET_arm_R15]
+        str  r0, [r8, #OFFSET_arm_R15T]

 
         /* Are we out of timeslice?  If yes, defer to scheduler. */
         ldr  r1, =VG_(dispatch_ctr)
 
         /* Are we out of timeslice?  If yes, defer to scheduler. */
         ldr  r1, =VG_(dispatch_ctr)


@@ -172,22 +172,22 @@ VG_(run_innerloop__dispatch_profiled):
 /*----------------------------------------------------*/
 
 gsp_changed:
 /*----------------------------------------------------*/
 
 gsp_changed:

-        // r0 = next guest addr (R15), r8 = modified gsp
+        // r0 = next guest addr (R15T), r8 = modified gsp

         /* Someone messed with the gsp.  Have to
            defer to scheduler to resolve this.  dispatch ctr
            is not yet decremented, so no need to increment. */
         /* Someone messed with the gsp.  Have to
            defer to scheduler to resolve this.  dispatch ctr
            is not yet decremented, so no need to increment. */

-        /* R15 is NOT up to date here.  First, need to write
-           r0 back to R15, but without trashing r8 since
+        /* R15T is NOT up to date here.  First, need to write
+           r0 back to R15T, but without trashing r8 since

            that holds the value we want to return to the scheduler.
            Hence use r1 transiently for the guest state pointer. */
        ldr r1, [sp, #0]
            that holds the value we want to return to the scheduler.
            Hence use r1 transiently for the guest state pointer. */
        ldr r1, [sp, #0]

-       str r0, [r1, #OFFSET_arm_R15]
+       str r0, [r1, #OFFSET_arm_R15T]

        mov r0, r8      // "return modified gsp"
        b run_innerloop_exit
         /*NOTREACHED*/
 
 counter_is_zero:
        mov r0, r8      // "return modified gsp"
        b run_innerloop_exit
         /*NOTREACHED*/
 
 counter_is_zero:

-        /* R15 is up to date here */
+        /* R15T is up to date here */

         /* Back out increment of the dispatch ctr */
         ldr  r1, =VG_(dispatch_ctr)
         ldr  r2, [r1]
         /* Back out increment of the dispatch ctr */
         ldr  r1, =VG_(dispatch_ctr)
         ldr  r2, [r1]


@@ -198,7 +198,7 @@ counter_is_zero:
         /*NOTREACHED*/
         
 fast_lookup_failed:
         /*NOTREACHED*/
         
 fast_lookup_failed:

-        /* R15 is up to date here */
+        /* R15T is up to date here */

         /* Back out increment of the dispatch ctr */
         ldr  r1, =VG_(dispatch_ctr)
         ldr  r2, [r1]
         /* Back out increment of the dispatch ctr */
         ldr  r1, =VG_(dispatch_ctr)
         ldr  r2, [r1]


@@ -215,8 +215,8 @@ run_innerloop_exit:
         /* We're leaving.  Check that nobody messed with
            FPSCR in ways we don't expect. */
         fmrx r4, fpscr
         /* We're leaving.  Check that nobody messed with
            FPSCR in ways we don't expect. */
         fmrx r4, fpscr

-        bic  r4, #0xF0000000 /* mask out NZCV */
-        bic  r4, #0x0000001F /* mask out IXC,UFC,OFC,DZC,IOC */
+        bic  r4, #0xF8000000 /* mask out NZCV and QC */
+        bic  r4, #0x0000009F /* mask out IDC,IXC,UFC,OFC,DZC,IOC */

         cmp  r4, #0
         bne  invariant_violation
         b    run_innerloop_exit_REALLY
         cmp  r4, #0
         bne  invariant_violation
         b    run_innerloop_exit_REALLY

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_dispatch/dispatch-ppc32-linux.S b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_dispatch/dispatch-ppc32-linux.S
index bb1bfdc0047834f97bfe860afe8d7d56948c4da3..c8ba4e8e8e74eada3370fc975fbb84babfb8aa78 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_dispatch/dispatch-ppc32-linux.S
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_dispatch/dispatch-ppc32-linux.S
@@ -30,6 +30,7 @@
 
 #if defined(VGP_ppc32_linux)
 
 
 #if defined(VGP_ppc32_linux)
 

+#include "config.h"

 #include "pub_core_basics_asm.h"
 #include "pub_core_dispatch_asm.h"
 #include "pub_core_transtab_asm.h"
 #include "pub_core_basics_asm.h"
 #include "pub_core_dispatch_asm.h"
 #include "pub_core_transtab_asm.h"


@@ -131,6 +132,7 @@ LafterFP1:
         cmplwi  5,0
         beq     LafterVMX1
 
         cmplwi  5,0
         beq     LafterVMX1
 

+#ifdef HAS_ALTIVEC

         /* VRSAVE save word : 32 bytes */
         mfspr   5,256         /* vrsave reg is spr number 256 */
         stw     5,244(1)
         /* VRSAVE save word : 32 bytes */
         mfspr   5,256         /* vrsave reg is spr number 256 */
         stw     5,244(1)


@@ -162,6 +164,8 @@ LafterFP1:
         stvx    21,5,1
         li      5,48
         stvx    20,5,1
         stvx    21,5,1
         li      5,48
         stvx    20,5,1

+#endif
+        

 LafterVMX1:
 
         /* Save cr */
 LafterVMX1:
 
         /* Save cr */


@@ -218,8 +222,11 @@ LafterFP2:
         cmplwi  5,0
         beq     LafterVMX2
 
         cmplwi  5,0
         beq     LafterVMX2
 

+#ifdef HAS_ALTIVEC

         vspltisw 3,0x0  /* generate zero */
         mtvscr  3
         vspltisw 3,0x0  /* generate zero */
         mtvscr  3

+#endif
+        

 LafterVMX2:
 
         /* make a stack frame for the code we are calling */
 LafterVMX2:
 
         /* make a stack frame for the code we are calling */


@@ -415,6 +422,7 @@ LafterFP8:
         cmplwi  11,0
         beq     LafterVMX8
 
         cmplwi  11,0
         beq     LafterVMX8
 

+#ifdef HAS_ALTIVEC

         /* Check VSCR[NJ] == 1 */
         /* first generate 4x 0x00010000 */
         vspltisw  4,0x1                   /* 4x 0x00000001 */
         /* Check VSCR[NJ] == 1 */
         /* first generate 4x 0x00010000 */
         vspltisw  4,0x1                   /* 4x 0x00000001 */


@@ -426,6 +434,7 @@ LafterFP8:
         vspltw    7,7,0x3                 /* flags-word to all lanes */
         vcmpequw. 8,6,7                   /* CR[24] = 1 if v6 == v7 */
         bt        24,invariant_violation  /* branch if all_equal */
         vspltw    7,7,0x3                 /* flags-word to all lanes */
         vcmpequw. 8,6,7                   /* CR[24] = 1 if v6 == v7 */
         bt        24,invariant_violation  /* branch if all_equal */

+#endif

 LafterVMX8:
 
        /* otherwise we're OK */
 LafterVMX8:
 
        /* otherwise we're OK */


@@ -502,6 +511,7 @@ LafterFP9:
         cmplwi  11,0
         beq     LafterVMX9
 
         cmplwi  11,0
         beq     LafterVMX9
 

+#ifdef HAS_ALTIVEC

         /* VRSAVE */
         lwz     4,244(1)
         mfspr   4,256         /* VRSAVE reg is spr number 256 */
         /* VRSAVE */
         lwz     4,244(1)
         mfspr   4,256         /* VRSAVE reg is spr number 256 */


@@ -531,6 +541,7 @@ LafterFP9:
         lvx     21,4,1
         li      4,48
         lvx     20,4,1
         lvx     21,4,1
         li      4,48
         lvx     20,4,1

+#endif

 LafterVMX9:
 
         /* reset lr & sp */
 LafterVMX9:
 
         /* reset lr & sp */

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-l4re.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-l4re.c
index 3fbf02899416d53bfba0456ee00e1fd1a6952176..06df8cb331ca1ce7940736786b47999abaddf584 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-l4re.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-l4re.c
@@ -415,6 +415,9 @@ Addr setup_client_stack( void*  init_sp,
    Addr clstack_start;
    Int i;
    Bool have_exename;
    Addr clstack_start;
    Int i;
    Bool have_exename;

+#if defined(VGO_l4re)
+   Addr client_l4re_env_addr;
+#endif

 
    VG_(debugLog)(2, "initimg", "%s sp %p env %p info %p stack_end %p size %lx\n",
                  __func__, init_sp, orig_envp, info, clstack_end, clstack_max_size);
 
    VG_(debugLog)(2, "initimg", "%s sp %p env %p info %p stack_end %p size %lx\n",
                  __func__, init_sp, orig_envp, info, clstack_end, clstack_max_size);


@@ -489,6 +492,9 @@ Addr setup_client_stack( void*  init_sp,
       sizeof(char **)*envc +                  /* envp */
       sizeof(char **) +                          /* terminal NULL */
       auxsize +                               /* auxv */
       sizeof(char **)*envc +                  /* envp */
       sizeof(char **) +                          /* terminal NULL */
       auxsize +                               /* auxv */

+#if defined(VGO_l4re)
+         l4re_env_env_size() +                   /* L4Re Env object */
+#endif

       VG_ROUNDUP(stringsize, sizeof(Word));   /* strings (aligned) */
 
    if (0) VG_(printf)("stacksize = %d\n", stacksize);
       VG_ROUNDUP(stringsize, sizeof(Word));   /* strings (aligned) */
 
    if (0) VG_(printf)("stacksize = %d\n", stacksize);


@@ -501,6 +507,8 @@ Addr setup_client_stack( void*  init_sp,
    stringbase = strtab = (char *)clstack_end 
                          - VG_ROUNDUP(stringsize, sizeof(int));
 
    stringbase = strtab = (char *)clstack_end 
                          - VG_ROUNDUP(stringsize, sizeof(int));
 

+   client_l4re_env_addr = stringbase - l4re_env_env_size();
+

    clstack_start = VG_PGROUNDDN(client_SP);
 
    /* The max stack size */
    clstack_start = VG_PGROUNDDN(client_SP);
 
    /* The max stack size */


@@ -815,7 +823,7 @@ Addr setup_client_stack( void*  init_sp,
                 // install modifications to
                 // global environment
                 *auxv = *orig_auxv;
                 // install modifications to
                 // global environment
                 *auxv = *orig_auxv;

-                auxv->u.a_val = (Word) l4re_vcap_modify_env(orig_auxv);
+                auxv->u.a_val = (Word) l4re_vcap_modify_env(orig_auxv, client_l4re_env_addr);

             }
             break;
 
             }
             break;
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-linux.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-linux.c
index 115d4a40ab4947f71f5c875357400125d76ed4d4..19535039d8e8b53859ba68dd22013e23b303d1f8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-linux.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-linux.c
@@ -1025,8 +1025,8 @@ void VG_(ii_finalise_image)( IIFinaliseImageInfo iifii )
    VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestARMState));
    VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestARMState));
 
    VG_(memset)(&arch->vex_shadow1, 0, sizeof(VexGuestARMState));
    VG_(memset)(&arch->vex_shadow2, 0, sizeof(VexGuestARMState));
 

-   arch->vex.guest_R13 = iifii.initial_client_SP;
-   arch->vex.guest_R15 = iifii.initial_client_IP;
+   arch->vex.guest_R13  = iifii.initial_client_SP;
+   arch->vex.guest_R15T = iifii.initial_client_IP;

 
    /* This is just EABI stuff. */
    // FIXME jrs: what's this for?
 
    /* This is just EABI stuff. */
    // FIXME jrs: what's this for?

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-pathscan.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-pathscan.c
index acde9c96b8adb86f6f7d162cba880463b50ac824..df47316bdf167e88ce9109fee8b23fb0c13ad03a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-pathscan.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/initimg-pathscan.c
@@ -130,7 +130,7 @@ static Bool match_executable(const char *entry)
 }
 
 // Returns NULL if it wasn't found.
 }
 
 // Returns NULL if it wasn't found.

-HChar* ML_(find_executable) ( HChar* exec )
+HChar* ML_(find_executable) ( const HChar* exec )

 {
    vg_assert(NULL != exec);
    if (VG_(strchr)(exec, '/')) {
 {
    vg_assert(NULL != exec);
    if (VG_(strchr)(exec, '/')) {

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/priv_initimg_pathscan.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/priv_initimg_pathscan.h
index 8245ce13b1d588007b36eeee42805957dea1aff5..f3169b171f7e7cde7b7901488cc78f522fe46e7c 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/priv_initimg_pathscan.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_initimg/priv_initimg_pathscan.h
@@ -32,6 +32,6 @@
 #ifndef __PRIV_INITIMG_PATHSCAN_H
 #define __PRIV_INITIMG_PATHSCAN_
 
 #ifndef __PRIV_INITIMG_PATHSCAN_H
 #define __PRIV_INITIMG_PATHSCAN_
 

-extern HChar* ML_(find_executable) ( HChar* exec );
+extern HChar* ML_(find_executable) ( const HChar* exec );

 
 #endif
 
 #endif

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_libcprint.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_libcprint.c
index 3a545049ab7e84211568426da76978b501ebba5b..389fd4c18c81a86b5036436377ce9d2b321604b0 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_libcprint.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_libcprint.c
@@ -400,14 +400,6 @@ static void add_to__vmessage_buf ( HChar c, void *p )
       HChar ch;
       Int   i, depth;
 
       HChar ch;
       Int   i, depth;
 

-      switch (b->kind) {
-         case Vg_UserMsg:       ch = '='; break;
-         case Vg_DebugMsg:      ch = '-'; break;
-         case Vg_DebugExtraMsg: ch = '+'; break;
-         case Vg_ClientMsg:     ch = '*'; break;
-         default:               ch = '?'; break;
-      }
-

       // Print one '>' in front of the messages for each level of
       // self-hosting being performed.
       depth = RUNNING_ON_VALGRIND;
       // Print one '>' in front of the messages for each level of
       // self-hosting being performed.
       depth = RUNNING_ON_VALGRIND;


@@ -417,25 +409,46 @@ static void add_to__vmessage_buf ( HChar c, void *p )
          b->buf[b->buf_used++] = '>';
       }
 
          b->buf[b->buf_used++] = '>';
       }
 

-      b->buf[b->buf_used++] = ch;
-      b->buf[b->buf_used++] = ch;
-
-      if (VG_(clo_time_stamp)) {
-         VG_(memset)(tmp, 0, sizeof(tmp));
-         VG_(elapsed_wallclock_time)(tmp);
+      if (Vg_FailMsg == b->kind) {
+         // "valgrind: " prefix.
+         b->buf[b->buf_used++] = 'v';
+         b->buf[b->buf_used++] = 'a';
+         b->buf[b->buf_used++] = 'l';
+         b->buf[b->buf_used++] = 'g';
+         b->buf[b->buf_used++] = 'r';
+         b->buf[b->buf_used++] = 'i';
+         b->buf[b->buf_used++] = 'n';
+         b->buf[b->buf_used++] = 'd';
+         b->buf[b->buf_used++] = ':';
+         b->buf[b->buf_used++] = ' ';
+      } else {
+         switch (b->kind) {
+            case Vg_UserMsg:       ch = '='; break;
+            case Vg_DebugMsg:      ch = '-'; break;
+            case Vg_ClientMsg:     ch = '*'; break;
+            default:               ch = '?'; break;
+         }
+
+         b->buf[b->buf_used++] = ch;
+         b->buf[b->buf_used++] = ch;
+
+         if (VG_(clo_time_stamp)) {
+            VG_(memset)(tmp, 0, sizeof(tmp));
+            VG_(elapsed_wallclock_time)(tmp);
+            tmp[sizeof(tmp)-1] = 0;
+            for (i = 0; tmp[i]; i++)
+               b->buf[b->buf_used++] = tmp[i];
+         }
+
+         VG_(sprintf)(tmp, "%d", VG_(getpid)());

          tmp[sizeof(tmp)-1] = 0;
          for (i = 0; tmp[i]; i++)
             b->buf[b->buf_used++] = tmp[i];
          tmp[sizeof(tmp)-1] = 0;
          for (i = 0; tmp[i]; i++)
             b->buf[b->buf_used++] = tmp[i];

-      }

 
 

-      VG_(sprintf)(tmp, "%d", VG_(getpid)());
-      tmp[sizeof(tmp)-1] = 0;
-      for (i = 0; tmp[i]; i++)
-         b->buf[b->buf_used++] = tmp[i];
-
-      b->buf[b->buf_used++] = ch;
-      b->buf[b->buf_used++] = ch;
-      b->buf[b->buf_used++] = ' ';
+         b->buf[b->buf_used++] = ch;
+         b->buf[b->buf_used++] = ch;
+         b->buf[b->buf_used++] = ' ';
+      }

 
       /* We can't possibly have stuffed 96 chars in merely as a result
          of making the preamble (can we?) */
 
       /* We can't possibly have stuffed 96 chars in merely as a result
          of making the preamble (can we?) */


@@ -503,33 +516,52 @@ UInt VG_(message) ( VgMsgKind kind, const HChar* format, ... )
    return count;
 }
 
    return count;
 }
 

+static void revert_to_stderr ( void )
+{
+   VG_(log_output_sink).fd = 2; /* stderr */
+   VG_(log_output_sink).is_socket = False;
+}
+

 /* VG_(message) variants with hardwired first argument. */
 /* VG_(message) variants with hardwired first argument. */

-UInt VG_(umsg) ( const HChar* format, ... )
+
+UInt VG_(fmsg) ( const HChar* format, ... )

 {
    UInt count;
    va_list vargs;
    va_start(vargs,format);
 {
    UInt count;
    va_list vargs;
    va_start(vargs,format);

-   count = VG_(vmessage) ( Vg_UserMsg, format, vargs );
+   count = VG_(vmessage) ( Vg_FailMsg, format, vargs );

    va_end(vargs);
    return count;
 }
 
    va_end(vargs);
    return count;
 }
 

-UInt VG_(dmsg) ( const HChar* format, ... )
+void VG_(fmsg_bad_option) ( HChar* opt, const HChar* format, ... )
+{
+   va_list vargs;
+   va_start(vargs,format);
+   revert_to_stderr();
+   VG_(message) (Vg_FailMsg, "Bad option: %s\n", opt);
+   VG_(vmessage)(Vg_FailMsg, format, vargs );
+   VG_(message) (Vg_FailMsg, "Use --help for more information or consult the user manual.\n");
+   VG_(exit)(1);
+   va_end(vargs);
+}
+
+UInt VG_(umsg) ( const HChar* format, ... )

 {
    UInt count;
    va_list vargs;
    va_start(vargs,format);
 {
    UInt count;
    va_list vargs;
    va_start(vargs,format);

-   count = VG_(vmessage) ( Vg_DebugMsg, format, vargs );
+   count = VG_(vmessage) ( Vg_UserMsg, format, vargs );

    va_end(vargs);
    return count;
 }
 
    va_end(vargs);
    return count;
 }
 

-UInt VG_(emsg) ( const HChar* format, ... )
+UInt VG_(dmsg) ( const HChar* format, ... )

 {
    UInt count;
    va_list vargs;
    va_start(vargs,format);
 {
    UInt count;
    va_list vargs;
    va_start(vargs,format);

-   count = VG_(vmessage) ( Vg_DebugExtraMsg, format, vargs );
+   count = VG_(vmessage) ( Vg_DebugMsg, format, vargs );

    va_end(vargs);
    return count;
 }
    va_end(vargs);
    return count;
 }


@@ -543,6 +575,24 @@ void VG_(message_flush) ( void )
    b->buf_used = 0;
 }
 
    b->buf_used = 0;
 }
 

+__attribute__((noreturn))
+void VG_(err_missing_prog) ( void  )
+{
+   revert_to_stderr();
+   VG_(fmsg)("no program specified\n");
+   VG_(fmsg)("Use --help for more information.\n");
+   VG_(exit)(1);
+}
+
+__attribute__((noreturn))
+void VG_(err_config_error) ( Char* msg )
+{
+   revert_to_stderr();
+   VG_(fmsg)("Startup or configuration error:\n   %s\n", msg);
+   VG_(fmsg)("Unable to start up properly.  Giving up.\n");
+   VG_(exit)(1);
+}
+

 
 /*--------------------------------------------------------------------*/
 /*--- end                                                          ---*/
 
 /*--------------------------------------------------------------------*/
 /*--- end                                                          ---*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_libcproc.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_libcproc.c
index 5b3a33ba8d47a5c6dc897528d2e84c47f1506d11..1ac94ec2dba7ac3c751487cae4d1ad683dc0c4ba 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_libcproc.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_libcproc.c
@@ -69,6 +69,15 @@ Char** VG_(client_envp) = NULL;
 /* Path to library directory */
 const Char *VG_(libdir) = VG_LIBDIR;
 
 /* Path to library directory */
 const Char *VG_(libdir) = VG_LIBDIR;
 

+const Char *VG_(LD_PRELOAD_var_name) =
+#if defined(VGO_linux) || defined(VGO_aix5) || defined(VGO_l4re)
+   "LD_PRELOAD";
+#elif defined(VGO_darwin)
+   "DYLD_INSERT_LIBRARIES";
+#else
+#  error Unknown OS
+#endif
+

 /* We do getenv without libc's help by snooping around in
    VG_(client_envp) as determined at startup time. */
 Char *VG_(getenv)(Char *varname)
 /* We do getenv without libc's help by snooping around in
    VG_(client_envp) as determined at startup time. */
 Char *VG_(getenv)(Char *varname)


@@ -187,9 +196,13 @@ static void mash_colon_env(Char *varp, const Char *remove_pattern)
            entry_start = output+1;     /* entry starts after ':' */
       }
 
            entry_start = output+1;     /* entry starts after ':' */
       }
 

-      *output++ = *varp++;
+      if (*varp)
+         *output++ = *varp++;

    }
 
    }
 

+   /* make sure last entry is nul terminated */
+   *output = '\0';
+

    /* match against the last entry */
    if (VG_(string_match)(remove_pattern, entry_start)) {
       output = entry_start;
    /* match against the last entry */
    if (VG_(string_match)(remove_pattern, entry_start)) {
       output = entry_start;

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_machine.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_machine.c
index 00a5e7be6611dcbbc819cae724f056a50bc986a0..76e62290db1fa11108f1bd7c921d563efe34dfa3 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_machine.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_machine.c
@@ -43,45 +43,23 @@
 #define STACK_PTR(regs)    ((regs).vex.VG_STACK_PTR)
 #define FRAME_PTR(regs)    ((regs).vex.VG_FRAME_PTR)
 
 #define STACK_PTR(regs)    ((regs).vex.VG_STACK_PTR)
 #define FRAME_PTR(regs)    ((regs).vex.VG_FRAME_PTR)
 

-Addr VG_(get_SP) ( ThreadId tid )
-{
-   return STACK_PTR( VG_(threads)[tid].arch );
-}
-
-Addr VG_(get_IP) ( ThreadId tid )
-{
+Addr VG_(get_IP) ( ThreadId tid ) {

    return INSTR_PTR( VG_(threads)[tid].arch );
 }
    return INSTR_PTR( VG_(threads)[tid].arch );
 }

-
-Addr VG_(get_FP) ( ThreadId tid )
-{
+Addr VG_(get_SP) ( ThreadId tid ) {
+   return STACK_PTR( VG_(threads)[tid].arch );
+}
+Addr VG_(get_FP) ( ThreadId tid ) {

    return FRAME_PTR( VG_(threads)[tid].arch );
 }
 
    return FRAME_PTR( VG_(threads)[tid].arch );
 }
 

-Addr VG_(get_LR) ( ThreadId tid )
-{
-#  if defined(VGA_ppc32) || defined(VGA_ppc64)
-   return VG_(threads)[tid].arch.vex.guest_LR;
-#  elif defined(VGA_x86) || defined(VGA_amd64)
-   return 0;
-#  elif defined(VGA_arm)
-   return VG_(threads)[tid].arch.vex.guest_R14;
-#  else
-#    error "Unknown arch"
-#  endif
+void VG_(set_IP) ( ThreadId tid, Addr ip ) {
+   INSTR_PTR( VG_(threads)[tid].arch ) = ip;

 }
 }

-
-void VG_(set_SP) ( ThreadId tid, Addr sp )
-{
+void VG_(set_SP) ( ThreadId tid, Addr sp ) {

    STACK_PTR( VG_(threads)[tid].arch ) = sp;
 }
 
    STACK_PTR( VG_(threads)[tid].arch ) = sp;
 }
 

-void VG_(set_IP) ( ThreadId tid, Addr ip )
-{
-   INSTR_PTR( VG_(threads)[tid].arch ) = ip;
-}
-
-

 void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs,
                                 ThreadId tid )
 {
 void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs,
                                 ThreadId tid )
 {


@@ -106,7 +84,7 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs,
    regs->misc.PPC64.r_lr
       = VG_(threads)[tid].arch.vex.guest_LR;
 #  elif defined(VGA_arm)
    regs->misc.PPC64.r_lr
       = VG_(threads)[tid].arch.vex.guest_LR;
 #  elif defined(VGA_arm)

-   regs->r_pc = (ULong)VG_(threads)[tid].arch.vex.guest_R15;
+   regs->r_pc = (ULong)VG_(threads)[tid].arch.vex.guest_R15T;

    regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_R13;
    regs->misc.ARM.r14
       = VG_(threads)[tid].arch.vex.guest_R14;
    regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_R13;
    regs->misc.ARM.r14
       = VG_(threads)[tid].arch.vex.guest_R14;


@@ -385,13 +363,16 @@ UInt VG_(machine_ppc32_has_VMX) = 0;
 #if defined(VGA_ppc64)
 ULong VG_(machine_ppc64_has_VMX) = 0;
 #endif
 #if defined(VGA_ppc64)
 ULong VG_(machine_ppc64_has_VMX) = 0;
 #endif

+#if defined(VGA_arm)
+Int VG_(machine_arm_archlevel) = 4;
+#endif

 
 
 /* Determine what insn set and insn set variant the host has, and
    record it.  To be called once at system startup.  Returns False if
    this a CPU incapable of running Valgrind. */
 
 
 
 /* Determine what insn set and insn set variant the host has, and
    record it.  To be called once at system startup.  Returns False if
    this a CPU incapable of running Valgrind. */
 

-#if defined(VGA_ppc32) || defined(VGA_ppc64)
+#if defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm)

 #include <setjmp.h> // For jmp_buf
 static jmp_buf env_unsup_insn;
 static void handler_unsup_insn ( Int x ) { __builtin_longjmp(env_unsup_insn,1); }
 #include <setjmp.h> // For jmp_buf
 static jmp_buf env_unsup_insn;
 static void handler_unsup_insn ( Int x ) { __builtin_longjmp(env_unsup_insn,1); }


@@ -407,8 +388,10 @@ Bool VG_(machine_get_hwcaps)( void )
    LibVEX_default_VexArchInfo(&vai);
 
 #if defined(VGA_x86)
    LibVEX_default_VexArchInfo(&vai);
 
 #if defined(VGA_x86)

-   { Bool have_sse1, have_sse2, have_cx8;
-     UInt eax, ebx, ecx, edx;
+   { Bool have_sse1, have_sse2, have_cx8, have_lzcnt;
+     UInt eax, ebx, ecx, edx, max_basic, max_extended;
+     UChar vstr[13];
+     vstr[0] = 0;

 
      if (!VG_(has_cpuid)())
         /* we can't do cpuid at all.  Give up. */
 
      if (!VG_(has_cpuid)())
         /* we can't do cpuid at all.  Give up. */


@@ -419,6 +402,17 @@ Bool VG_(machine_get_hwcaps)( void )
         /* we can't ask for cpuid(x) for x > 0.  Give up. */
         return False;
 
         /* we can't ask for cpuid(x) for x > 0.  Give up. */
         return False;
 

+     /* Get processor ID string, and max basic/extended index
+        values. */
+     max_basic = eax;
+     VG_(memcpy)(&vstr[0], &ebx, 4);
+     VG_(memcpy)(&vstr[4], &edx, 4);
+     VG_(memcpy)(&vstr[8], &ecx, 4);
+     vstr[12] = 0;
+
+     VG_(cpuid)(0x80000000, &eax, &ebx, &ecx, &edx);
+     max_extended = eax;
+

      /* get capabilities bits into edx */
      VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
 
      /* get capabilities bits into edx */
      VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
 


@@ -432,10 +426,20 @@ Bool VG_(machine_get_hwcaps)( void )
      if (!have_cx8)
         return False;
 
      if (!have_cx8)
         return False;
 

+     /* Figure out if this is an AMD that can do LZCNT. */
+     have_lzcnt = False;
+     if (0 == VG_(strcmp)(vstr, "AuthenticAMD")
+         && max_extended >= 0x80000001) {
+        VG_(cpuid)(0x80000001, &eax, &ebx, &ecx, &edx);
+        have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */
+     }
+

      if (have_sse2 && have_sse1) {
         va          = VexArchX86;
         vai.hwcaps  = VEX_HWCAPS_X86_SSE1;
         vai.hwcaps |= VEX_HWCAPS_X86_SSE2;
      if (have_sse2 && have_sse1) {
         va          = VexArchX86;
         vai.hwcaps  = VEX_HWCAPS_X86_SSE1;
         vai.hwcaps |= VEX_HWCAPS_X86_SSE2;

+        if (have_lzcnt)
+           vai.hwcaps |= VEX_HWCAPS_X86_LZCNT;

         VG_(machine_x86_have_mxcsr) = 1;
         return True;
      }
         VG_(machine_x86_have_mxcsr) = 1;
         return True;
      }


@@ -455,7 +459,10 @@ Bool VG_(machine_get_hwcaps)( void )
 
 #elif defined(VGA_amd64)
    { Bool have_sse1, have_sse2, have_sse3, have_cx8, have_cx16;
 
 #elif defined(VGA_amd64)
    { Bool have_sse1, have_sse2, have_sse3, have_cx8, have_cx16;

-     UInt eax, ebx, ecx, edx;
+     Bool have_lzcnt;
+     UInt eax, ebx, ecx, edx, max_basic, max_extended;
+     UChar vstr[13];
+     vstr[0] = 0;

 
      if (!VG_(has_cpuid)())
         /* we can't do cpuid at all.  Give up. */
 
      if (!VG_(has_cpuid)())
         /* we can't do cpuid at all.  Give up. */


@@ -466,12 +473,26 @@ Bool VG_(machine_get_hwcaps)( void )
         /* we can't ask for cpuid(x) for x > 0.  Give up. */
         return False;
 
         /* we can't ask for cpuid(x) for x > 0.  Give up. */
         return False;
 

+     /* Get processor ID string, and max basic/extended index
+        values. */
+      max_basic = eax;
+     VG_(memcpy)(&vstr[0], &ebx, 4);
+     VG_(memcpy)(&vstr[4], &edx, 4);
+     VG_(memcpy)(&vstr[8], &ecx, 4);
+     vstr[12] = 0;
+
+     VG_(cpuid)(0x80000000, &eax, &ebx, &ecx, &edx);
+     max_extended = eax;
+

      /* get capabilities bits into edx */
      VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
 
      have_sse1 = (edx & (1<<25)) != 0; /* True => have sse insns */
      have_sse2 = (edx & (1<<26)) != 0; /* True => have sse2 insns */
      have_sse3 = (ecx & (1<<0)) != 0;  /* True => have sse3 insns */
      /* get capabilities bits into edx */
      VG_(cpuid)(1, &eax, &ebx, &ecx, &edx);
 
      have_sse1 = (edx & (1<<25)) != 0; /* True => have sse insns */
      have_sse2 = (edx & (1<<26)) != 0; /* True => have sse2 insns */
      have_sse3 = (ecx & (1<<0)) != 0;  /* True => have sse3 insns */

+     // ssse3  is ecx:9
+     // sse41  is ecx:19
+     // sse42  is ecx:20

 
      /* cmpxchg8b is a minimum requirement now; if we don't have it we
         must simply give up.  But all CPUs since Pentium-I have it, so
 
      /* cmpxchg8b is a minimum requirement now; if we don't have it we
         must simply give up.  But all CPUs since Pentium-I have it, so


@@ -483,9 +504,18 @@ Bool VG_(machine_get_hwcaps)( void )
      /* on amd64 we tolerate older cpus, which don't have cmpxchg16b */
      have_cx16 = (ecx & (1<<13)) != 0; /* True => have cmpxchg16b */
 
      /* on amd64 we tolerate older cpus, which don't have cmpxchg16b */
      have_cx16 = (ecx & (1<<13)) != 0; /* True => have cmpxchg16b */
 

+     /* Figure out if this is an AMD that can do LZCNT. */
+     have_lzcnt = False;
+     if (0 == VG_(strcmp)(vstr, "AuthenticAMD")
+         && max_extended >= 0x80000001) {
+        VG_(cpuid)(0x80000001, &eax, &ebx, &ecx, &edx);
+        have_lzcnt = (ecx & (1<<5)) != 0; /* True => have LZCNT */
+     }
+

      va         = VexArchAMD64;
      vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)
      va         = VexArchAMD64;
      vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)

-                  | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0);
+                  | (have_cx16 ? VEX_HWCAPS_AMD64_CX16 : 0)
+                  | (have_lzcnt ? VEX_HWCAPS_AMD64_LZCNT : 0);

      return True;
    }
 
      return True;
    }
 


@@ -715,8 +745,110 @@ Bool VG_(machine_get_hwcaps)( void )
 
 #elif defined(VGA_arm)
    {
 
 #elif defined(VGA_arm)
    {

+     /* Same instruction set detection algorithm as for ppc32. */
+     vki_sigset_t          saved_set, tmp_set;
+     vki_sigaction_fromK_t saved_sigill_act, saved_sigfpe_act;
+     vki_sigaction_toK_t     tmp_sigill_act,   tmp_sigfpe_act;
+
+     volatile Bool have_VFP, have_VFP2, have_VFP3, have_NEON;
+     volatile Int archlevel;
+     Int r;
+
+     /* This is a kludge.  Really we ought to back-convert saved_act
+        into a toK_t using VG_(convert_sigaction_fromK_to_toK), but
+        since that's a no-op on all ppc64 platforms so far supported,
+        it's not worth the typing effort.  At least include most basic
+        sanity check: */
+     vg_assert(sizeof(vki_sigaction_fromK_t) == sizeof(vki_sigaction_toK_t));
+
+     VG_(sigemptyset)(&tmp_set);
+     VG_(sigaddset)(&tmp_set, VKI_SIGILL);
+     VG_(sigaddset)(&tmp_set, VKI_SIGFPE);
+
+     r = VG_(sigprocmask)(VKI_SIG_UNBLOCK, &tmp_set, &saved_set);
+     vg_assert(r == 0);
+
+     r = VG_(sigaction)(VKI_SIGILL, NULL, &saved_sigill_act);
+     vg_assert(r == 0);
+     tmp_sigill_act = saved_sigill_act;
+
+     VG_(sigaction)(VKI_SIGFPE, NULL, &saved_sigfpe_act);
+     tmp_sigfpe_act = saved_sigfpe_act;
+
+     /* NODEFER: signal handler does not return (from the kernel's point of
+        view), hence if it is to successfully catch a signal more than once,
+        we need the NODEFER flag. */
+     tmp_sigill_act.sa_flags &= ~VKI_SA_RESETHAND;
+     tmp_sigill_act.sa_flags &= ~VKI_SA_SIGINFO;
+     tmp_sigill_act.sa_flags |=  VKI_SA_NODEFER;
+     tmp_sigill_act.ksa_handler = handler_unsup_insn;
+     VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
+
+     tmp_sigfpe_act.sa_flags &= ~VKI_SA_RESETHAND;
+     tmp_sigfpe_act.sa_flags &= ~VKI_SA_SIGINFO;
+     tmp_sigfpe_act.sa_flags |=  VKI_SA_NODEFER;
+     tmp_sigfpe_act.ksa_handler = handler_unsup_insn;
+     VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL);
+
+     /* VFP insns */
+     have_VFP = True;
+     if (__builtin_setjmp(env_unsup_insn)) {
+        have_VFP = False;
+     } else {
+        __asm__ __volatile__(".word 0xEEB02B42"); /* VMOV.F64 d2, d2 */
+     }
+     /* There are several generation of VFP extension but they differs very
+        little so for now we will not distinguish them. */
+     have_VFP2 = have_VFP;
+     have_VFP3 = have_VFP;
+
+     /* NEON insns */
+     have_NEON = True;
+     if (__builtin_setjmp(env_unsup_insn)) {
+        have_NEON = False;
+     } else {
+        __asm__ __volatile__(".word 0xF2244154"); /* VMOV q2, q2 */
+     }
+
+     /* ARM architecture level */
+     archlevel = 5; /* v5 will be base level */
+     if (archlevel < 7) {
+        archlevel = 7;
+        if (__builtin_setjmp(env_unsup_insn)) {
+           archlevel = 5;
+        } else {
+           __asm__ __volatile__(".word 0xF45FF000"); /* PLI [PC,#-0] */
+        }
+     }
+     if (archlevel < 6) {
+        archlevel = 6;
+        if (__builtin_setjmp(env_unsup_insn)) {
+           archlevel = 5;
+        } else {
+           __asm__ __volatile__(".word 0xE6822012"); /* PKHBT r2, r2, r2 */
+        }
+     }
+
+     VG_(convert_sigaction_fromK_to_toK)(&saved_sigill_act, &tmp_sigill_act);
+     VG_(convert_sigaction_fromK_to_toK)(&saved_sigfpe_act, &tmp_sigfpe_act);
+     VG_(sigaction)(VKI_SIGILL, &tmp_sigill_act, NULL);
+     VG_(sigaction)(VKI_SIGFPE, &tmp_sigfpe_act, NULL);
+     VG_(sigprocmask)(VKI_SIG_SETMASK, &saved_set, NULL);
+
+     VG_(debugLog)(1, "machine", "ARMv%d VFP %d VFP2 %d VFP3 %d NEON %d\n",
+           archlevel, (Int)have_VFP, (Int)have_VFP2, (Int)have_VFP3,
+           (Int)have_NEON);
+
+     VG_(machine_arm_archlevel) = archlevel;
+

      va = VexArchARM;
      va = VexArchARM;

-     vai.hwcaps = 0;
+
+     vai.hwcaps = VEX_ARM_ARCHLEVEL(archlevel);
+     if (have_VFP3) vai.hwcaps |= VEX_HWCAPS_ARM_VFP3;
+     if (have_VFP2) vai.hwcaps |= VEX_HWCAPS_ARM_VFP2;
+     if (have_VFP)  vai.hwcaps |= VEX_HWCAPS_ARM_VFP;
+     if (have_NEON) vai.hwcaps |= VEX_HWCAPS_ARM_NEON;
+

      return True;
    }
 
      return True;
    }
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_main.c
index 784569695533f5429124d2fd0b07d157dc726954..89683d8d1a593646d323ba222198c6beae74a112 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_main.c
@@ -187,8 +187,8 @@ static void usage_NORETURN ( Bool debug_help )
    Char* usage2 = 
 "\n"
 "  debugging options for all Valgrind tools:\n"
    Char* usage2 = 
 "\n"
 "  debugging options for all Valgrind tools:\n"

-"    --stats=no|yes            show tool and core statistics [no]\n"

 "    -d                        show verbose debugging output\n"
 "    -d                        show verbose debugging output\n"

+"    --stats=no|yes            show tool and core statistics [no]\n"

 "    --sanity-level=<number>   level of sanity checking to do [1]\n"
 "    --trace-flags=<XXXXXXXX>   show generated code? (X = 0|1) [00000000]\n"
 "    --profile-flags=<XXXXXXXX> ditto, but for profiling (X = 0|1) [00000000]\n"
 "    --sanity-level=<number>   level of sanity checking to do [1]\n"
 "    --trace-flags=<XXXXXXXX>   show generated code? (X = 0|1) [00000000]\n"
 "    --profile-flags=<XXXXXXXX> ditto, but for profiling (X = 0|1) [00000000]\n"


@@ -312,10 +312,10 @@ static void early_process_cmd_line_options ( /*OUT*/Int* need_help,
          VG_(printf)("valgrind-" VERSION "\n");
          VG_(exit)(0);
       }
          VG_(printf)("valgrind-" VERSION "\n");
          VG_(exit)(0);
       }

-      else if VG_XACT_CLO(str, "--help", *need_help, 1) {}
-      else if VG_XACT_CLO(str, "-h",     *need_help, 1) {}
+      else if VG_XACT_CLO(str, "--help", *need_help, *need_help+1) {}
+      else if VG_XACT_CLO(str, "-h",     *need_help, *need_help+1) {}

 
 

-      else if VG_XACT_CLO(str, "--help-debug", *need_help, 2) {}
+      else if VG_XACT_CLO(str, "--help-debug", *need_help, *need_help+2) {}

 
       // The tool has already been determined, but we need to know the name
       // here.
 
       // The tool has already been determined, but we need to know the name
       // here.


@@ -551,11 +551,9 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
 
       else if VG_STR_CLO(arg, "--suppressions", tmp_str) {
          if (VG_(clo_n_suppressions) >= VG_CLO_MAX_SFILES) {
 
       else if VG_STR_CLO(arg, "--suppressions", tmp_str) {
          if (VG_(clo_n_suppressions) >= VG_CLO_MAX_SFILES) {

-            VG_(message)(Vg_UserMsg,
-                         "Too many suppression files specified.\n");
-            VG_(message)(Vg_UserMsg, 
-                         "Increase VG_CLO_MAX_SFILES and recompile.\n");
-            VG_(err_bad_option)(arg);
+            VG_(fmsg_bad_option)(arg,
+               "Too many suppression files specified.\n"
+               "Increase VG_CLO_MAX_SFILES and recompile.\n");

          }
          VG_(clo_suppressions)[VG_(clo_n_suppressions)] = tmp_str;
          VG_(clo_n_suppressions)++;
          }
          VG_(clo_suppressions)[VG_(clo_n_suppressions)] = tmp_str;
          VG_(clo_n_suppressions)++;


@@ -563,11 +561,9 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
 
       else if VG_STR_CLO(arg, "--require-text-symbol", tmp_str) {
          if (VG_(clo_n_req_tsyms) >= VG_CLO_MAX_REQ_TSYMS) {
 
       else if VG_STR_CLO(arg, "--require-text-symbol", tmp_str) {
          if (VG_(clo_n_req_tsyms) >= VG_CLO_MAX_REQ_TSYMS) {

-            VG_(message)(Vg_UserMsg,
-                         "Too many --require-text-symbol= specifications.\n");
-            VG_(message)(Vg_UserMsg, 
-                         "Increase VG_CLO_MAX_REQ_TSYMS and recompile.\n");
-            VG_(err_bad_option)(arg);
+            VG_(fmsg_bad_option)(arg,
+               "Too many --require-text-symbol= specifications.\n"
+               "Increase VG_CLO_MAX_REQ_TSYMS and recompile.\n");

          }
          /* String needs to be of the form C?*C?*, where C is any
             character, but is the same both times.  Having it in this
          }
          /* String needs to be of the form C?*C?*, where C is any
             character, but is the same both times.  Having it in this


@@ -586,9 +582,8 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
            ok = VG_(string_match)(patt, tmp_str);
          }
          if (!ok) {
            ok = VG_(string_match)(patt, tmp_str);
          }
          if (!ok) {

-            VG_(message)(Vg_UserMsg,
-                         "Invalid --require-text-symbol= specification.\n");
-            VG_(err_bad_option)(arg);
+            VG_(fmsg_bad_option)(arg,
+               "Invalid --require-text-symbol= specification.\n");

          }
          VG_(clo_req_tsyms)[VG_(clo_n_req_tsyms)] = tmp_str;
          VG_(clo_n_req_tsyms)++;
          }
          VG_(clo_req_tsyms)[VG_(clo_n_req_tsyms)] = tmp_str;
          VG_(clo_n_req_tsyms)++;


@@ -599,17 +594,15 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
          Int j;
    
          if (8 != VG_(strlen)(tmp_str)) {
          Int j;
    
          if (8 != VG_(strlen)(tmp_str)) {

-            VG_(message)(Vg_UserMsg, 
-                         "--trace-flags argument must have 8 digits\n");
-            VG_(err_bad_option)(arg);
+            VG_(fmsg_bad_option)(arg,
+               "--trace-flags argument must have 8 digits\n");

          }
          for (j = 0; j < 8; j++) {
             if      ('0' == tmp_str[j]) { /* do nothing */ }
             else if ('1' == tmp_str[j]) VG_(clo_trace_flags) |= (1 << (7-j));
             else {
          }
          for (j = 0; j < 8; j++) {
             if      ('0' == tmp_str[j]) { /* do nothing */ }
             else if ('1' == tmp_str[j]) VG_(clo_trace_flags) |= (1 << (7-j));
             else {

-               VG_(message)(Vg_UserMsg, "--trace-flags argument can only "
-                                        "contain 0s and 1s\n");
-               VG_(err_bad_option)(arg);
+               VG_(fmsg_bad_option)(arg,
+                  "--trace-flags argument can only contain 0s and 1s\n");

             }
          }
       }
             }
          }
       }


@@ -619,17 +612,15 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
          Int j;
    
          if (8 != VG_(strlen)(tmp_str)) {
          Int j;
    
          if (8 != VG_(strlen)(tmp_str)) {

-            VG_(message)(Vg_UserMsg, 
-                         "--profile-flags argument must have 8 digits\n");
-            VG_(err_bad_option)(arg);
+            VG_(fmsg_bad_option)(arg, 
+               "--profile-flags argument must have 8 digits\n");

          }
          for (j = 0; j < 8; j++) {
             if      ('0' == tmp_str[j]) { /* do nothing */ }
             else if ('1' == tmp_str[j]) VG_(clo_profile_flags) |= (1 << (7-j));
             else {
          }
          for (j = 0; j < 8; j++) {
             if      ('0' == tmp_str[j]) { /* do nothing */ }
             else if ('1' == tmp_str[j]) VG_(clo_profile_flags) |= (1 << (7-j));
             else {

-               VG_(message)(Vg_UserMsg, "--profile-flags argument can only "
-                                        "contain 0s and 1s\n");
-               VG_(err_bad_option)(arg);
+               VG_(fmsg_bad_option)(arg,
+                  "--profile-flags argument can only contain 0s and 1s\n");

             }
          }
       }
             }
          }
       }


@@ -645,7 +636,7 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
 
       else if ( ! VG_(needs).command_line_options
              || ! VG_TDICT_CALL(tool_process_cmd_line_option, arg) ) {
 
       else if ( ! VG_(needs).command_line_options
              || ! VG_TDICT_CALL(tool_process_cmd_line_option, arg) ) {

-         VG_(err_bad_option)(arg);
+         VG_(fmsg_bad_option)(arg, "");

       }
    }
 
       }
    }
 


@@ -668,20 +659,17 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
 
    if (VG_(clo_gen_suppressions) > 0 && 
        !VG_(needs).core_errors && !VG_(needs).tool_errors) {
 
    if (VG_(clo_gen_suppressions) > 0 && 
        !VG_(needs).core_errors && !VG_(needs).tool_errors) {

-      VG_(message)(Vg_UserMsg, 
-                   "Can't use --gen-suppressions= with this tool,\n");
-      VG_(message)(Vg_UserMsg, 
-                   "as it doesn't generate errors.\n");
-      VG_(err_bad_option)("--gen-suppressions=");
+      VG_(fmsg_bad_option)("--gen-suppressions=yes",
+         "Can't use --gen-suppressions= with %s\n"
+         "because it doesn't generate errors.\n", VG_(details).name);

    }
 
    /* If XML output is requested, check that the tool actually
       supports it. */
    if (VG_(clo_xml) && !VG_(needs).xml_output) {
       VG_(clo_xml) = False;
    }
 
    /* If XML output is requested, check that the tool actually
       supports it. */
    if (VG_(clo_xml) && !VG_(needs).xml_output) {
       VG_(clo_xml) = False;

-      VG_(message)(Vg_UserMsg, 
+      VG_(fmsg_bad_option)("--xml=yes",

          "%s does not support XML output.\n", VG_(details).name); 
          "%s does not support XML output.\n", VG_(details).name); 

-      VG_(err_bad_option)("--xml=yes");

       /*NOTREACHED*/
    }
 
       /*NOTREACHED*/
    }
 


@@ -702,33 +690,28 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
          (--gen-suppressions=all is still OK since we don't need any
          user interaction in this case.) */
       if (VG_(clo_gen_suppressions) == 1) {
          (--gen-suppressions=all is still OK since we don't need any
          user interaction in this case.) */
       if (VG_(clo_gen_suppressions) == 1) {

-         VG_(umsg)(
-            "When --xml=yes is specified, only --gen-suppressions=no\n"
-            "or --gen-suppressions=all are allowed, but not "
+         VG_(fmsg_bad_option)(
+            "--xml=yes together with --gen-suppressions=yes",
+            "When --xml=yes is specified, --gen-suppressions=no\n"
+            "or --gen-suppressions=all is allowed, but not "

             "--gen-suppressions=yes.\n");
             "--gen-suppressions=yes.\n");

-         /* FIXME: this is really a misuse of VG_(err_bad_option). */
-         VG_(err_bad_option)(
-            "--xml=yes together with --gen-suppressions=yes");

       }
 
       /* We can't allow DB attaching (or we maybe could, but results
          could be chaotic ..) since it requires user input.  Hence
          disallow. */
       if (VG_(clo_db_attach)) {
       }
 
       /* We can't allow DB attaching (or we maybe could, but results
          could be chaotic ..) since it requires user input.  Hence
          disallow. */
       if (VG_(clo_db_attach)) {

-         VG_(umsg)("--db-attach=yes is not allowed in XML mode,\n"
-                  "as it would require user input.\n");
-         /* FIXME: this is really a misuse of VG_(err_bad_option). */
-         VG_(err_bad_option)(
-            "--xml=yes together with --db-attach=yes");
+         VG_(fmsg_bad_option)(
+            "--xml=yes together with --db-attach=yes",
+            "--db-attach=yes is not allowed with --xml=yes\n"
+            "because it would require user input.\n");

       }
 
       /* Disallow dump_error in XML mode; sounds like a recipe for
          chaos.  No big deal; dump_error is a flag for debugging V
          itself. */
       if (VG_(clo_dump_error) > 0) {
       }
 
       /* Disallow dump_error in XML mode; sounds like a recipe for
          chaos.  No big deal; dump_error is a flag for debugging V
          itself. */
       if (VG_(clo_dump_error) > 0) {

-         /* FIXME: this is really a misuse of VG_(err_bad_option). */
-         VG_(err_bad_option)(
-            "--xml=yes together with --dump-error=");
+         VG_(fmsg_bad_option)("--xml=yes together with --dump-error", "");

       }
 
       /* Disable error limits (this might be a bad idea!) */
       }
 
       /* Disable error limits (this might be a bad idea!) */


@@ -786,11 +769,9 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
             tmp_log_fd = sr_Res(sres);
             VG_(clo_log_fname_expanded) = logfilename;
          } else {
             tmp_log_fd = sr_Res(sres);
             VG_(clo_log_fname_expanded) = logfilename;
          } else {

-            VG_(message)(Vg_UserMsg, 
-                         "Can't create log file '%s' (%s); giving up!\n", 
-                         logfilename, VG_(strerror)(sr_Err(sres)));
-            VG_(err_bad_option)(
-               "--log-file=<file> (didn't work out for some reason.)");
+            VG_(fmsg)("can't create log file '%s': %s\n", 
+                      logfilename, VG_(strerror)(sr_Err(sres)));
+            VG_(exit)(1);

             /*NOTREACHED*/
          }
          break;
             /*NOTREACHED*/
          }
          break;


@@ -801,23 +782,16 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
          vg_assert(VG_(strlen)(log_fsname_unexpanded) <= 900); /* paranoia */
          tmp_log_fd = VG_(connect_via_socket)( log_fsname_unexpanded );
          if (tmp_log_fd == -1) {
          vg_assert(VG_(strlen)(log_fsname_unexpanded) <= 900); /* paranoia */
          tmp_log_fd = VG_(connect_via_socket)( log_fsname_unexpanded );
          if (tmp_log_fd == -1) {

-            VG_(message)(Vg_UserMsg, 
-               "Invalid --log-socket=ipaddr or "
-               "--log-socket=ipaddr:port spec\n"); 
-            VG_(message)(Vg_UserMsg, 
-               "of '%s'; giving up!\n", log_fsname_unexpanded );
-            VG_(err_bad_option)(
-               "--log-socket=");
+            VG_(fmsg)("Invalid --log-socket spec of '%s'\n",
+                      log_fsname_unexpanded);
+            VG_(exit)(1);

             /*NOTREACHED*/
         }
          if (tmp_log_fd == -2) {
             /*NOTREACHED*/
         }
          if (tmp_log_fd == -2) {

-            VG_(message)(Vg_UserMsg, 
-               "valgrind: failed to connect to logging server '%s'.\n",
-               log_fsname_unexpanded ); 
-            VG_(message)(Vg_UserMsg, 
-                "Log messages will sent to stderr instead.\n" );
-            VG_(message)(Vg_UserMsg, 
-                "\n" );
+            VG_(umsg)("failed to connect to logging server '%s'.\n"
+                      "Log messages will sent to stderr instead.\n",
+                      log_fsname_unexpanded ); 
+

             /* We don't change anything here. */
             vg_assert(VG_(log_output_sink).fd == 2);
             tmp_log_fd = 2;
             /* We don't change anything here. */
             vg_assert(VG_(log_output_sink).fd == 2);
             tmp_log_fd = 2;


@@ -857,11 +831,9 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
             *xml_fname_unexpanded = VG_(strdup)( "main.mpclo.2",
                                                  xml_fsname_unexpanded );
          } else {
             *xml_fname_unexpanded = VG_(strdup)( "main.mpclo.2",
                                                  xml_fsname_unexpanded );
          } else {

-            VG_(message)(Vg_UserMsg, 
-                         "Can't create XML file '%s' (%s); giving up!\n", 
-                         xmlfilename, VG_(strerror)(sr_Err(sres)));
-            VG_(err_bad_option)(
-               "--xml-file=<file> (didn't work out for some reason.)");
+            VG_(fmsg)("can't create XML file '%s': %s\n", 
+                      xmlfilename, VG_(strerror)(sr_Err(sres)));
+            VG_(exit)(1);

             /*NOTREACHED*/
          }
          break;
             /*NOTREACHED*/
          }
          break;


@@ -872,23 +844,15 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
          vg_assert(VG_(strlen)(xml_fsname_unexpanded) <= 900); /* paranoia */
          tmp_xml_fd = VG_(connect_via_socket)( xml_fsname_unexpanded );
          if (tmp_xml_fd == -1) {
          vg_assert(VG_(strlen)(xml_fsname_unexpanded) <= 900); /* paranoia */
          tmp_xml_fd = VG_(connect_via_socket)( xml_fsname_unexpanded );
          if (tmp_xml_fd == -1) {

-            VG_(message)(Vg_UserMsg, 
-               "Invalid --xml-socket=ipaddr or "
-               "--xml-socket=ipaddr:port spec\n"); 
-            VG_(message)(Vg_UserMsg, 
-               "of '%s'; giving up!\n", xml_fsname_unexpanded );
-            VG_(err_bad_option)(
-               "--xml-socket=");
+            VG_(fmsg)("Invalid --xml-socket spec of '%s'\n",
+                      xml_fsname_unexpanded );
+            VG_(exit)(1);

             /*NOTREACHED*/
         }
          if (tmp_xml_fd == -2) {
             /*NOTREACHED*/
         }
          if (tmp_xml_fd == -2) {

-            VG_(message)(Vg_UserMsg, 
-               "valgrind: failed to connect to XML logging server '%s'.\n",
-               xml_fsname_unexpanded ); 
-            VG_(message)(Vg_UserMsg, 
-                "XML output will sent to stderr instead.\n" );
-            VG_(message)(Vg_UserMsg, 
-                "\n" );
+            VG_(umsg)("failed to connect to XML logging server '%s'.\n"
+                      "XML output will sent to stderr instead.\n",
+                      xml_fsname_unexpanded); 

             /* We don't change anything here. */
             vg_assert(VG_(xml_output_sink).fd == 2);
             tmp_xml_fd = 2;
             /* We don't change anything here. */
             vg_assert(VG_(xml_output_sink).fd == 2);
             tmp_xml_fd = 2;


@@ -906,13 +870,12 @@ void main_process_cmd_line_options ( /*OUT*/Bool* logging_to_fd,
       but that is likely to confuse the hell out of users, which is
       distinctly Ungood. */
    if (VG_(clo_xml) && tmp_xml_fd == -1) {
       but that is likely to confuse the hell out of users, which is
       distinctly Ungood. */
    if (VG_(clo_xml) && tmp_xml_fd == -1) {

-      VG_(umsg)(
+      VG_(fmsg_bad_option)(
+          "--xml=yes, but no XML destination specified",

           "--xml=yes has been specified, but there is no XML output\n"
           "destination.  You must specify an XML output destination\n"
           "--xml=yes has been specified, but there is no XML output\n"
           "destination.  You must specify an XML output destination\n"

-          "using --xml-fd=, --xml-file= or --xml=socket=.\n" );
-      /* FIXME: this is really a misuse of VG_(err_bad_option). */
-      VG_(err_bad_option)(
-         "--xml=yes, but no XML destination specified");
+          "using --xml-fd, --xml-file or --xml-socket.\n"
+      );

    }
 
    // Finalise the output fds: the log fd ..
    }
 
    // Finalise the output fds: the log fd ..


@@ -1025,7 +988,7 @@ static void print_file_vars(Char* format)
 /*====================================================================*/
 
 // Print the command, escaping any chars that require it.
 /*====================================================================*/
 
 // Print the command, escaping any chars that require it.

-static void umsg_or_xml_arg(Char* arg,
+static void umsg_or_xml_arg(const Char* arg,

                             UInt (*umsg_or_xml)( const HChar*, ... ) )
 {
    SizeT len = VG_(strlen)(arg);
                             UInt (*umsg_or_xml)( const HChar*, ... ) )
 {
    SizeT len = VG_(strlen)(arg);


@@ -1073,7 +1036,7 @@ static void print_preamble ( Bool logging_to_fd,
          VG_(printf_xml)("<preamble>\n");
 
       /* Tool details */
          VG_(printf_xml)("<preamble>\n");
 
       /* Tool details */

-      umsg_or_xml( "%s%s%s%s, %s%s\n",
+      umsg_or_xml( VG_(clo_xml) ? "%s%t%t%t, %t%s\n" : "%s%s%s%s, %s%s\n",

                    xpre,
                    VG_(details).name, 
                    NULL == VG_(details).version ? "" : "-",
                    xpre,
                    VG_(details).name, 
                    NULL == VG_(details).version ? "" : "-",


@@ -1089,7 +1052,8 @@ static void print_preamble ( Bool logging_to_fd,
          );
       }
 
          );
       }
 

-      umsg_or_xml("%s%s%s\n", xpre, VG_(details).copyright_author, xpost);
+      umsg_or_xml( VG_(clo_xml) ? "%s%t%s\n" : "%s%s%s\n",
+                   xpre, VG_(details).copyright_author, xpost );

 
       /* Core details */
       umsg_or_xml(
 
       /* Core details */
       umsg_or_xml(


@@ -1142,8 +1106,8 @@ static void print_preamble ( Bool logging_to_fd,
          VG_(printf_xml_no_f_c)("    <exe>%t</exe>\n",
                                 VG_(name_of_launcher));
       else
          VG_(printf_xml_no_f_c)("    <exe>%t</exe>\n",
                                 VG_(name_of_launcher));
       else

-         VG_(printf_xml_no_f_c)(Vg_UserMsg, "    <exe>%t</exe>\n",
-                                            "(launcher name unknown)");
+         VG_(printf_xml_no_f_c)("    <exe>%t</exe>\n",
+                                "(launcher name unknown)");

       for (i = 0; i < VG_(sizeXA)( VG_(args_for_valgrind) ); i++) {
          VG_(printf_xml_no_f_c)(
             "    <arg>%t</arg>\n",
       for (i = 0; i < VG_(sizeXA)( VG_(args_for_valgrind) ); i++) {
          VG_(printf_xml_no_f_c)(
             "    <arg>%t</arg>\n",


@@ -1598,52 +1562,10 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp )
    }
 #  endif
 
    }
 #  endif
 

-   //--------------------------------------------------------------
-   // Darwin only: munmap address-space-filling segments
-   // (oversized pagezero or stack)
-   //   p: none
-   //--------------------------------------------------------------
-   // DDD:  comments from Greg Parker why these address-space-filling segments
-   // are necessary:
-   //
-   //   The memory maps are there to make sure that Valgrind's copies of libc
-   //   and dyld load in a non-default location, so that the inferior's own
-   //   libc and dyld do load in the default locations. (The kernel performs
-   //   the work of loading several things as described by the executable's
-   //   load commands, including the executable itself, dyld, the main
-   //   thread's stack, and the page-zero segment.) There might be a way to
-   //   fine-tune it so the maps are smaller but still do the job.
-   //
-   //   The post-launch mmap behavior can be cleaned up - looks like we don't
-   //   unmap as much as we should - which would improve post-launch
-   //   performance.
-   //
-   //   Hmm, there might be an extra-clever way to give Valgrind a custom
-   //   MH_DYLINKER that performs the "bootloader" work of loading dyld in an
-   //   acceptable place and then unloading itself. Then no mmaps would be
-   //   needed. I'll have to think about that one.
-   //
-   // [I can't work out where the address-space-filling segments are
-   // created in the first place. --njn]
-   //
-#if defined(VGO_darwin)
-# if VG_WORDSIZE == 4
-   VG_(do_syscall2)(__NR_munmap, 0x00000000, 0xf0000000);
-# else
-   // open up client space
-   VG_(do_syscall2)(__NR_munmap, 0x100000000, 0x700000000000-0x100000000);
-   // open up client stack and dyld
-   VG_(do_syscall2)(__NR_munmap, 0x7fff5c000000, 0x4000000);
-# endif
-#endif
-

    //--------------------------------------------------------------
    // Ensure we're on a plausible stack.
    //   p: logging
    //--------------------------------------------------------------
    //--------------------------------------------------------------
    // Ensure we're on a plausible stack.
    //   p: logging
    //--------------------------------------------------------------

-#if defined(VGO_darwin)
-   // Darwin doesn't use the interim stack.
-#else

    VG_(debugLog)(1, "main", "Checking current stack is plausible\n");
    { HChar* limLo  = (HChar*)(&VG_(interim_stack).bytes[0]);
      HChar* limHi  = limLo + sizeof(VG_(interim_stack));
    VG_(debugLog)(1, "main", "Checking current stack is plausible\n");
    { HChar* limLo  = (HChar*)(&VG_(interim_stack).bytes[0]);
      HChar* limHi  = limLo + sizeof(VG_(interim_stack));


@@ -1671,12 +1593,11 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp )
       VG_(debugLog)(0, "main", "   Cannot continue.  Sorry.\n");
       VG_(exit)(1);
    }
       VG_(debugLog)(0, "main", "   Cannot continue.  Sorry.\n");
       VG_(exit)(1);
    }

-#endif

 
    //--------------------------------------------------------------
    // Start up the address space manager, and determine the
    // approximate location of the client's stack
 
    //--------------------------------------------------------------
    // Start up the address space manager, and determine the
    // approximate location of the client's stack

-   //   p: logging, plausible-stack, darwin-munmap
+   //   p: logging, plausible-stack

    //--------------------------------------------------------------
    VG_(debugLog)(1, "main", "Starting the address space manager\n");
    vg_assert(VKI_PAGE_SIZE     == 4096 || VKI_PAGE_SIZE     == 65536);
    //--------------------------------------------------------------
    VG_(debugLog)(1, "main", "Starting the address space manager\n");
    vg_assert(VKI_PAGE_SIZE     == 4096 || VKI_PAGE_SIZE     == 65536);


@@ -1969,7 +1890,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp )
       HChar  buf[50], buf2[50+64];
       HChar  nul[1];
       Int    fd, r;
       HChar  buf[50], buf2[50+64];
       HChar  nul[1];
       Int    fd, r;

-      HChar* exename;
+      const HChar* exename;

 
       VG_(debugLog)(1, "main", "Create fake /proc/<pid>/cmdline\n");
 
 
       VG_(debugLog)(1, "main", "Create fake /proc/<pid>/cmdline\n");
 


@@ -2020,7 +1941,7 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp )
    //--------------------------------------------------------------
    VG_(debugLog)(1, "main", "Print help and quit, if requested\n");
    if (need_help) {
    //--------------------------------------------------------------
    VG_(debugLog)(1, "main", "Print help and quit, if requested\n");
    if (need_help) {

-      usage_NORETURN(/*--help-debug?*/2 == need_help);
+      usage_NORETURN(/*--help-debug?*/need_help >= 2);

    }
 
    //--------------------------------------------------------------
    }
 
    //--------------------------------------------------------------


@@ -2804,6 +2725,13 @@ void* memset(void *s, int c, SizeT n) {
   return VG_(memset)(s,c,n);
 }
 
   return VG_(memset)(s,c,n);
 }
 

+/* BVA: abort() for those platforms that need it (PPC and ARM). */
+void abort(void);
+void abort(void){
+   VG_(printf)("Something called raise().\n");
+   vg_assert(0);
+}
+

 /* EAZG: ARM's EABI will call floating point exception handlers in
    libgcc which boil down to an abort or raise, that's usually defined
    in libc. Instead, define them here. */
 /* EAZG: ARM's EABI will call floating point exception handlers in
    libgcc which boil down to an abort or raise, that's usually defined
    in libc. Instead, define them here. */


@@ -2814,17 +2742,17 @@ void raise(void){
    vg_assert(0);
 }
 
    vg_assert(0);
 }
 

-void abort(void);
-void abort(void){
-   VG_(printf)("Something called raise().\n");
-   vg_assert(0);
-}
-

 void __aeabi_unwind_cpp_pr0(void);
 void __aeabi_unwind_cpp_pr0(void){
    VG_(printf)("Something called __aeabi_unwind_cpp_pr0()\n");
    vg_assert(0);
 }
 void __aeabi_unwind_cpp_pr0(void);
 void __aeabi_unwind_cpp_pr0(void){
    VG_(printf)("Something called __aeabi_unwind_cpp_pr0()\n");
    vg_assert(0);
 }

+
+void __aeabi_unwind_cpp_pr1(void);
+void __aeabi_unwind_cpp_pr1(void){
+   VG_(printf)("Something called __aeabi_unwind_cpp_pr1()\n");
+   vg_assert(0);
+}

 #endif
 
 /* ---------------- Requirement 2 ---------------- */
 #endif
 
 /* ---------------- Requirement 2 ---------------- */


@@ -3152,6 +3080,68 @@ void max_pw_passlen       ( void ) { vg_assert(0); }
 
 #elif defined(VGO_darwin)
 
 
 #elif defined(VGO_darwin)
 

+/*
+   Memory layout established by kernel:
+
+   0(%esp)   argc
+   4(%esp)   argv[0]
+             ...
+             argv[argc-1]
+             NULL
+             envp[0]
+             ...
+             envp[n]
+             NULL
+             executable name (presumably, a pointer to it)
+             NULL
+
+   Ditto in the 64-bit case, except all offsets from SP are obviously
+   twice as large.
+*/
+
+/* The kernel hands control to _start, which extracts the initial
+   stack pointer and calls onwards to _start_in_C_darwin.  This also
+   switches to the new stack.  */
+#if defined(VGP_x86_darwin)
+asm("\n"
+    ".text\n"
+    ".align 2,0x90\n"
+    "\t.globl __start\n"
+    "__start:\n"
+    /* set up the new stack in %eax */
+    "\tmovl  $_vgPlain_interim_stack, %eax\n"
+    "\taddl  $"VG_STRINGIFY(VG_STACK_GUARD_SZB)", %eax\n"
+    "\taddl  $"VG_STRINGIFY(VG_STACK_ACTIVE_SZB)", %eax\n"
+    "\tsubl  $16, %eax\n"
+    "\tandl  $~15, %eax\n"
+    /* install it, and collect the original one */
+    "\txchgl %eax, %esp\n"
+    /* call _start_in_C_darwin, passing it the startup %esp */
+    "\tpushl %eax\n"
+    "\tcall  __start_in_C_darwin\n"
+    "\tint $3\n"
+    "\tint $3\n"
+);
+#elif defined(VGP_amd64_darwin)
+asm("\n"
+    ".text\n"
+    "\t.globl __start\n"
+    ".align 3,0x90\n"
+    "__start:\n"
+    /* set up the new stack in %rdi */
+    "\tmovabsq $_vgPlain_interim_stack, %rdi\n"
+    "\taddq    $"VG_STRINGIFY(VG_STACK_GUARD_SZB)", %rdi\n"
+    "\taddq    $"VG_STRINGIFY(VG_STACK_ACTIVE_SZB)", %rdi\n"
+    "\tandq    $~15, %rdi\n"
+    /* install it, and collect the original one */
+    "\txchgq %rdi, %rsp\n"
+    /* call _start_in_C_darwin, passing it the startup %rsp */
+    "\tcall  __start_in_C_darwin\n"
+    "\tint $3\n"
+    "\tint $3\n"
+);
+#endif
+

 void* __memcpy_chk(void *dest, const void *src, SizeT n, SizeT n2);
 void* __memcpy_chk(void *dest, const void *src, SizeT n, SizeT n2) {
     // skip check
 void* __memcpy_chk(void *dest, const void *src, SizeT n, SizeT n2);
 void* __memcpy_chk(void *dest, const void *src, SizeT n, SizeT n2) {
     // skip check


@@ -3176,15 +3166,13 @@ void* memset(void *s, int c, SizeT n) {
   return VG_(memset)(s,c,n);
 }
 
   return VG_(memset)(s,c,n);
 }
 

-/* _start in m_start-<arch>-darwin.S calls _start_in_C_darwin(). */
-

 /* Avoid compiler warnings: this fn _is_ used, but labelling it
    'static' causes gcc to complain it isn't. */
 void _start_in_C_darwin ( UWord* pArgc );
 void _start_in_C_darwin ( UWord* pArgc )
 {
    Int     r;
 /* Avoid compiler warnings: this fn _is_ used, but labelling it
    'static' causes gcc to complain it isn't. */
 void _start_in_C_darwin ( UWord* pArgc );
 void _start_in_C_darwin ( UWord* pArgc )
 {
    Int     r;

-   Int    argc = *(Int *)pArgc;  // not pArgc[0] on LP64
+   Int     argc = *(Int *)pArgc;  // not pArgc[0] on LP64

    HChar** argv = (HChar**)&pArgc[1];
    HChar** envp = (HChar**)&pArgc[1+argc+1];
 
    HChar** argv = (HChar**)&pArgc[1];
    HChar** envp = (HChar**)&pArgc[1+argc+1];
 


@@ -3273,6 +3261,330 @@ void _start_in_C_l4re ( int argc, char **argv, char **envp ,int esp)
 #endif
 
 
 #endif
 
 

+/*====================================================================*/
+/*=== {u,}{div,mod}di3 replacements                                ===*/
+/*====================================================================*/
+
+/* For static linking on x86-darwin, we need to supply our own 64-bit
+   integer division code, else the link dies thusly:
+
+   ld_classic: Undefined symbols:
+     ___udivdi3
+     ___umoddi3
+*/
+#if defined(VGP_x86_darwin)
+
+/* Routines for doing signed/unsigned 64 x 64 ==> 64 div and mod
+   (udivdi3, umoddi3, divdi3, moddi3) using only 32 x 32 ==> 32
+   division.  Cobbled together from
+
+   http://www.hackersdelight.org/HDcode/divlu.c
+   http://www.hackersdelight.org/HDcode/divls.c
+   http://www.hackersdelight.org/HDcode/newCode/divDouble.c
+
+   The code from those three files is covered by the following license,
+   as it appears at:
+
+   http://www.hackersdelight.org/permissions.htm
+
+      You are free to use, copy, and distribute any of the code on
+      this web site, whether modified by you or not. You need not give
+      attribution. This includes the algorithms (some of which appear
+      in Hacker's Delight), the Hacker's Assistant, and any code
+      submitted by readers. Submitters implicitly agree to this.
+*/
+
+/* Long division, unsigned (64/32 ==> 32).
+   This procedure performs unsigned "long division" i.e., division of a
+64-bit unsigned dividend by a 32-bit unsigned divisor, producing a
+32-bit quotient.  In the overflow cases (divide by 0, or quotient
+exceeds 32 bits), it returns a remainder of 0xFFFFFFFF (an impossible
+value).
+   The dividend is u1 and u0, with u1 being the most significant word.
+The divisor is parameter v. The value returned is the quotient.
+   Max line length is 57, to fit in hacker.book. */
+
+static Int nlz32(UInt x) 
+{
+   Int n;
+   if (x == 0) return(32);
+   n = 0;
+   if (x <= 0x0000FFFF) {n = n +16; x = x <<16;}
+   if (x <= 0x00FFFFFF) {n = n + 8; x = x << 8;}
+   if (x <= 0x0FFFFFFF) {n = n + 4; x = x << 4;}
+   if (x <= 0x3FFFFFFF) {n = n + 2; x = x << 2;}
+   if (x <= 0x7FFFFFFF) {n = n + 1;}
+   return n;
+}
+
+/* 64 x 32 ==> 32 unsigned division, using only 32 x 32 ==> 32
+   division as a primitive. */
+static UInt divlu2(UInt u1, UInt u0, UInt v, UInt *r)
+{
+   const UInt b = 65536;     // Number base (16 bits).
+   UInt un1, un0,            // Norm. dividend LSD's.
+        vn1, vn0,            // Norm. divisor digits.
+        q1, q0,              // Quotient digits.
+        un32, un21, un10,    // Dividend digit pairs.
+        rhat;                // A remainder.
+   Int s;                    // Shift amount for norm.
+
+   if (u1 >= v) {            // If overflow, set rem.
+      if (r != NULL)         // to an impossible value,
+         *r = 0xFFFFFFFF;    // and return the largest
+      return 0xFFFFFFFF;}    // possible quotient.
+
+   s = nlz32(v);             // 0 <= s <= 31.
+   v = v << s;               // Normalize divisor.
+   vn1 = v >> 16;            // Break divisor up into
+   vn0 = v & 0xFFFF;         // two 16-bit digits.
+
+   un32 = (u1 << s) | ((u0 >> (32 - s)) & (-s >> 31));
+   un10 = u0 << s;           // Shift dividend left.
+
+   un1 = un10 >> 16;         // Break right half of
+   un0 = un10 & 0xFFFF;      // dividend into two digits.
+
+   q1 = un32/vn1;            // Compute the first
+   rhat = un32 - q1*vn1;     // quotient digit, q1.
+ again1:
+   if (q1 >= b || q1*vn0 > b*rhat + un1) {
+     q1 = q1 - 1;
+     rhat = rhat + vn1;
+     if (rhat < b) goto again1;}
+
+   un21 = un32*b + un1 - q1*v;  // Multiply and subtract.
+
+   q0 = un21/vn1;            // Compute the second
+   rhat = un21 - q0*vn1;     // quotient digit, q0.
+ again2:
+   if (q0 >= b || q0*vn0 > b*rhat + un0) {
+     q0 = q0 - 1;
+     rhat = rhat + vn1;
+     if (rhat < b) goto again2;}
+
+   if (r != NULL)            // If remainder is wanted,
+      *r = (un21*b + un0 - q0*v) >> s;     // return it.
+   return q1*b + q0;
+}
+
+
+/* 64 x 32 ==> 32 signed division, using only 32 x 32 ==> 32 division
+   as a primitive. */
+static Int divls(Int u1, UInt u0, Int v, Int *r)
+{
+   Int q, uneg, vneg, diff, borrow;
+
+   uneg = u1 >> 31;          // -1 if u < 0.
+   if (uneg) {               // Compute the absolute
+      u0 = -u0;              // value of the dividend u.
+      borrow = (u0 != 0);
+      u1 = -u1 - borrow;}
+
+   vneg = v >> 31;           // -1 if v < 0.
+   v = (v ^ vneg) - vneg;    // Absolute value of v.
+
+   if ((UInt)u1 >= (UInt)v) goto overflow;
+
+   q = divlu2(u1, u0, v, (UInt *)r);
+
+   diff = uneg ^ vneg;       // Negate q if signs of
+   q = (q ^ diff) - diff;    // u and v differed.
+   if (uneg && r != NULL)
+      *r = -*r;
+
+   if ((diff ^ q) < 0 && q != 0) {  // If overflow,
+ overflow:                    // set remainder
+      if (r != NULL)         // to an impossible value,
+         *r = 0x80000000;    // and return the largest
+      q = 0x80000000;}       // possible neg. quotient.
+   return q;
+}
+
+
+
+/* This file contains a program for doing 64/64 ==> 64 division, on a
+machine that does not have that instruction but that does have
+instructions for "long division" (64/32 ==> 32). Code for unsigned
+division is given first, followed by a simple program for doing the
+signed version by using the unsigned version.
+   These programs are useful in implementing "long long" (64-bit)
+arithmetic on a machine that has the long division instruction. It will
+work on 64- and 32-bit machines, provided the compiler implements long
+long's (64-bit integers). It is desirable that the machine have the
+Count Leading Zeros instruction.
+   In the GNU world, these programs are known as __divdi3 and __udivdi3,
+and similar names are used here.
+   This material is not in HD, but may be in a future edition.
+Max line length is 57, to fit in hacker.book. */
+
+
+static Int nlz64(ULong x) 
+{
+   Int n;
+   if (x == 0) return(64);
+   n = 0;
+   if (x <= 0x00000000FFFFFFFFULL) {n = n + 32; x = x << 32;}
+   if (x <= 0x0000FFFFFFFFFFFFULL) {n = n + 16; x = x << 16;}
+   if (x <= 0x00FFFFFFFFFFFFFFULL) {n = n +  8; x = x <<  8;}
+   if (x <= 0x0FFFFFFFFFFFFFFFULL) {n = n +  4; x = x <<  4;}
+   if (x <= 0x3FFFFFFFFFFFFFFFULL) {n = n +  2; x = x <<  2;}
+   if (x <= 0x7FFFFFFFFFFFFFFFULL) {n = n +  1;}
+   return n;
+}
+
+// ---------------------------- udivdi3 --------------------------------
+
+   /* The variables u0, u1, etc. take on only 32-bit values, but they
+   are declared long long to avoid some compiler warning messages and to
+   avoid some unnecessary EXTRs that the compiler would put in, to
+   convert long longs to ints.
+
+   First the procedure takes care of the case in which the divisor is a
+   32-bit quantity. There are two subcases: (1) If the left half of the
+   dividend is less than the divisor, one execution of DIVU is all that
+   is required (overflow is not possible). (2) Otherwise it does two
+   divisions, using the grade school method, with variables used as
+   suggested below.
+
+       q1 q0
+    ________
+   v)  u1 u0
+     q1*v
+     ____
+        k u0   */
+
+/* These macros must be used with arguments of the appropriate type
+(unsigned long long for DIVU and long long for DIVS. They are
+simulations of the presumed machines ops. I.e., they look at only the
+low-order 32 bits of the divisor, they return garbage if the division
+overflows, and they return garbage in the high-order half of the
+quotient doubleword.
+   In practice, these would be replaced with uses of the machine's DIVU
+and DIVS instructions (e.g., by using the GNU "asm" facility). */
+
+static UInt DIVU ( ULong u, UInt v )
+{
+  UInt uHi = (UInt)(u >> 32);
+  UInt uLo = (UInt)u;
+  return divlu2(uHi, uLo, v, NULL);
+}
+
+static Int DIVS ( Long u, Int v )
+{
+  Int  uHi = (Int)(u >> 32);
+  UInt uLo = (UInt)u;
+  return divls(uHi, uLo, v, NULL);
+}
+
+/* 64 x 64 ==> 64 unsigned division, using only 32 x 32 ==> 32
+   division as a primitive. */
+static ULong udivdi3(ULong u, ULong v)
+{
+   ULong u0, u1, v1, q0, q1, k, n;
+
+   if (v >> 32 == 0) {          // If v < 2**32:
+      if (u >> 32 < v)          // If u/v cannot overflow,
+         return DIVU(u, v)      // just do one division.
+            & 0xFFFFFFFF;
+      else {                    // If u/v would overflow:
+         u1 = u >> 32;          // Break u up into two
+         u0 = u & 0xFFFFFFFF;   // halves.
+         q1 = DIVU(u1, v)       // First quotient digit.
+            & 0xFFFFFFFF;
+         k = u1 - q1*v;         // First remainder, < v.
+         q0 = DIVU((k << 32) + u0, v) // 2nd quot. digit.
+            & 0xFFFFFFFF;
+         return (q1 << 32) + q0;
+      }
+   }
+                                // Here v >= 2**32.
+   n = nlz64(v);                // 0 <= n <= 31.
+   v1 = (v << n) >> 32;         // Normalize the divisor
+                                // so its MSB is 1.
+   u1 = u >> 1;                 // To ensure no overflow.
+   q1 = DIVU(u1, v1)            // Get quotient from
+       & 0xFFFFFFFF;            // divide unsigned insn.
+   q0 = (q1 << n) >> 31;        // Undo normalization and
+                                // division of u by 2.
+   if (q0 != 0)                 // Make q0 correct or
+      q0 = q0 - 1;              // too small by 1.
+   if ((u - q0*v) >= v)
+      q0 = q0 + 1;              // Now q0 is correct.
+   return q0;
+}
+
+
+// ----------------------------- divdi3 --------------------------------
+
+/* This routine presumes that smallish cases (those which can be done in
+one execution of DIVS) are common. If this is not the case, the test for
+this case should be deleted.
+   Note that the test for when DIVS can be used is not entirely
+accurate. For example, DIVS is not used if v = 0xFFFFFFFF8000000,
+whereas if could be (if u is sufficiently small in magnitude). */
+
+// ------------------------------ cut ----------------------------------
+
+static ULong my_llabs ( Long x )
+{
+   ULong t = x >> 63;
+   return (x ^ t) - t;
+}
+
+/* 64 x 64 ==> 64 signed division, using only 32 x 32 ==> 32 division
+   as a primitive. */
+static Long divdi3(Long u, Long v)
+{
+   ULong au, av;
+   Long q, t;
+   au = my_llabs(u);
+   av = my_llabs(v);
+   if (av >> 31 == 0) {         // If |v| < 2**31 and
+   // if (v << 32 >> 32 == v) { // If v is in range and
+      if (au < av << 31) {      // |u|/|v| cannot
+         q = DIVS(u, v);        // overflow, use DIVS.
+         return (q << 32) >> 32;
+      }
+   }
+   q = udivdi3(au,av);          // Invoke udivdi3.
+   t = (u ^ v) >> 63;           // If u, v have different
+   return (q ^ t) - t;          // signs, negate q.
+}
+
+// ---------------------------- end cut --------------------------------
+
+ULong __udivdi3 (ULong u, ULong v);
+ULong __udivdi3 (ULong u, ULong v)
+{
+  return udivdi3(u,v);
+}
+
+Long __divdi3 (Long u, Long v);
+Long __divdi3 (Long u, Long v)
+{
+  return divdi3(u,v);
+}
+
+ULong __umoddi3 (ULong u, ULong v);
+ULong __umoddi3 (ULong u, ULong v)
+{
+  ULong q = __udivdi3(u, v);
+  ULong r = u - q * v;
+  return r;
+}
+
+Long __moddi3 (Long u, Long v);
+Long __moddi3 (Long u, Long v)
+{
+  Long q = __divdi3(u, v);
+  Long r = u - q * v;
+  return r;
+}
+
+#endif
+
+

 /*--------------------------------------------------------------------*/
 /*--- end                                                          ---*/
 /*--------------------------------------------------------------------*/
 /*--------------------------------------------------------------------*/
 /*--- end                                                          ---*/
 /*--------------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_options.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_options.c
index d6aea74f0952b3280f0f397b2ebac7827cf7c4da..90672c1c33e1a8d723e20274dd656506e30c5f72 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_options.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_options.c
@@ -1,7 +1,6 @@
 
 /*--------------------------------------------------------------------*/
 
 /*--------------------------------------------------------------------*/

-/*--- Command line options.                                        ---*/
-/*---                                                  m_options.c ---*/
+/*--- Command line options.                            m_options.c ---*/

 /*--------------------------------------------------------------------*/
 
 /*
 /*--------------------------------------------------------------------*/
 
 /*


@@ -100,42 +99,9 @@ Bool   VG_(clo_dsymutil)       = False;
 
 
 /*====================================================================*/
 
 
 /*====================================================================*/

-/*=== Command line errors                                          ===*/
+/*=== File expansion                                               ===*/

 /*====================================================================*/
 
 /*====================================================================*/
 

-static void revert_to_stderr ( void )
-{
-   VG_(log_output_sink).fd = 2; /* stderr */
-   VG_(log_output_sink).is_socket = False;
-}
-
-__attribute__((noreturn))
-void VG_(err_bad_option) ( Char* opt )
-{
-   revert_to_stderr();
-   VG_(printf)("valgrind: Bad option '%s'; aborting.\n", opt);
-   VG_(printf)("valgrind: Use --help for more information.\n");
-   VG_(exit)(1);
-}
-
-__attribute__((noreturn))
-void VG_(err_missing_prog) ( void  )
-{
-   revert_to_stderr();
-   VG_(printf)("valgrind: no program specified\n");
-   VG_(printf)("valgrind: Use --help for more information.\n");
-   VG_(exit)(1);
-}
-
-__attribute__((noreturn))
-void VG_(err_config_error) ( Char* msg )
-{
-   revert_to_stderr();
-   VG_(printf)("valgrind: Startup or configuration error:\n   %s\n", msg);
-   VG_(printf)("valgrind: Unable to start up properly.  Giving up.\n");
-   VG_(exit)(1);
-}
-

 // Copies the string, prepending it with the startup working directory, and
 // expanding %p and %q entries.  Returns a new, malloc'd string.
 Char* VG_(expand_file_name)(Char* option_name, Char* format)
 // Copies the string, prepending it with the startup working directory, and
 // expanding %p and %q entries.  Returns a new, malloc'd string.
 Char* VG_(expand_file_name)(Char* option_name, Char* format)


@@ -149,7 +115,7 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format)
 
    if (VG_STREQ(format, "")) {
       // Empty name, bad.
 
    if (VG_STREQ(format, "")) {
       // Empty name, bad.

-      VG_(umsg)("%s: filename is empty", option_name);
+      VG_(fmsg)("%s: filename is empty", option_name);

       goto bad;
    }
    
       goto bad;
    }
    


@@ -158,11 +124,13 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format)
    // that we don't allow a legitimate filename beginning with '~' but that
    // seems very unlikely.
    if (format[0] == '~') {
    // that we don't allow a legitimate filename beginning with '~' but that
    // seems very unlikely.
    if (format[0] == '~') {

-      VG_(umsg)("%s: filename begins with '~'\n", option_name);
-      VG_(umsg)("You probably expected the shell to expand the '~', but it\n");
-      VG_(umsg)("didn't.  The rules for '~'-expansion "
-                "vary from shell to shell.\n");
-      VG_(umsg)("You might have more luck using $HOME instead.\n");
+      VG_(fmsg)(
+         "%s: filename begins with '~'\n"
+         "You probably expected the shell to expand the '~', but it\n"
+         "didn't.  The rules for '~'-expansion vary from shell to shell.\n"
+         "You might have more luck using $HOME instead.\n",
+         option_name
+      );

       goto bad;
    }
 
       goto bad;
    }
 


@@ -216,8 +184,7 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format)
                qualname = &format[i];
                while (True) {
                   if (0 == format[i]) {
                qualname = &format[i];
                while (True) {
                   if (0 == format[i]) {

-                     VG_(message)(Vg_UserMsg, "%s: malformed %%q specifier\n",
-                        option_name);
+                     VG_(fmsg)("%s: malformed %%q specifier\n", option_name);

                      goto bad;
                   } else if ('}' == format[i]) {
                      // Temporarily replace the '}' with NUL to extract var
                      goto bad;
                   } else if ('}' == format[i]) {
                      // Temporarily replace the '}' with NUL to extract var


@@ -225,9 +192,8 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format)
                      format[i] = 0;
                      qual = VG_(getenv)(qualname);
                      if (NULL == qual) {
                      format[i] = 0;
                      qual = VG_(getenv)(qualname);
                      if (NULL == qual) {

-                        VG_(message)(Vg_UserMsg,
-                           "%s: environment variable %s is not set\n",
-                           option_name, qualname);
+                        VG_(fmsg)("%s: environment variable %s is not set\n",
+                                  option_name, qualname);

                         format[i] = '}';  // Put the '}' back.
                         goto bad;
                      }
                         format[i] = '}';  // Put the '}' back.
                         goto bad;
                      }


@@ -240,15 +206,14 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format)
                ENSURE_THIS_MUCH_SPACE(VG_(strlen)(qual));
                j += VG_(sprintf)(&out[j], "%s", qual);
             } else {
                ENSURE_THIS_MUCH_SPACE(VG_(strlen)(qual));
                j += VG_(sprintf)(&out[j], "%s", qual);
             } else {

-               VG_(message)(Vg_UserMsg,
-                  "%s: expected '{' after '%%q'\n", option_name);
+               VG_(fmsg)("%s: expected '{' after '%%q'\n", option_name);

                goto bad;
             }
          } 
          else {
             // Something else, abort.
                goto bad;
             }
          } 
          else {
             // Something else, abort.

-            VG_(message)(Vg_UserMsg,
-               "%s: expected 'p' or 'q' or '%%' after '%%'\n", option_name);
+            VG_(fmsg)("%s: expected 'p' or 'q' or '%%' after '%%'\n",
+                      option_name);

             goto bad;
          }
       }
             goto bad;
          }
       }


@@ -265,7 +230,7 @@ Char* VG_(expand_file_name)(Char* option_name, Char* format)
    VG_(strcpy)(opt, option_name);
    VG_(strcat)(opt, "=");
    VG_(strcat)(opt, format);
    VG_(strcpy)(opt, option_name);
    VG_(strcat)(opt, "=");
    VG_(strcat)(opt, format);

-   VG_(err_bad_option)(opt);
+   VG_(fmsg_bad_option)(opt, "");

   }
 }
 
   }
 }
 


@@ -335,5 +300,5 @@ Bool VG_(should_we_trace_this_child) ( HChar* child_exe_name )
 
 
 /*--------------------------------------------------------------------*/
 
 
 /*--------------------------------------------------------------------*/

-/*--- end                                              m_options.c ---*/
+/*--- end                                                          ---*/

 /*--------------------------------------------------------------------*/
 /*--------------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_redir.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_redir.c
index 22ee4aafa6c33023d51f86b5601e4cb78828e0ed..d6a8274020ace41b054b3d9cb3dcbab260e0d840 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_redir.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_redir.c
@@ -1048,7 +1048,7 @@ void VG_(redir_initialise) ( void )
       add_hardwired_spec(
          "ld-linux.so.3", "strlen",
          (Addr)&VG_(arm_linux_REDIR_FOR_strlen),
       add_hardwired_spec(
          "ld-linux.so.3", "strlen",
          (Addr)&VG_(arm_linux_REDIR_FOR_strlen),

-         NULL
+         complain_about_stripped_glibc_ldso

       );
       //add_hardwired_spec(
       //   "ld-linux.so.3", "index",
       );
       //add_hardwired_spec(
       //   "ld-linux.so.3", "index",


@@ -1058,7 +1058,7 @@ void VG_(redir_initialise) ( void )
       add_hardwired_spec(
          "ld-linux.so.3", "memcpy",
          (Addr)&VG_(arm_linux_REDIR_FOR_memcpy),
       add_hardwired_spec(
          "ld-linux.so.3", "memcpy",
          (Addr)&VG_(arm_linux_REDIR_FOR_memcpy),

-         NULL 
+         complain_about_stripped_glibc_ldso

       );
    }
    /* nothing so far */
       );
    }
    /* nothing so far */


@@ -1069,25 +1069,39 @@ void VG_(redir_initialise) ( void )
 #  elif defined(VGP_ppc64_aix5)
    /* nothing so far */
 
 #  elif defined(VGP_ppc64_aix5)
    /* nothing so far */
 

-#  elif defined(VGO_darwin)
+#  elif defined(VGP_x86_darwin)
+   /* If we're using memcheck, use these intercepts right from
+      the start, otherwise dyld makes a lot of noise. */
+   if (0==VG_(strcmp)("Memcheck", VG_(details).name)) {
+      add_hardwired_spec("dyld", "strcmp",
+                         (Addr)&VG_(x86_darwin_REDIR_FOR_strcmp), NULL);
+      add_hardwired_spec("dyld", "strlen",
+                         (Addr)&VG_(x86_darwin_REDIR_FOR_strlen), NULL);
+      add_hardwired_spec("dyld", "strcat",
+                         (Addr)&VG_(x86_darwin_REDIR_FOR_strcat), NULL);
+      add_hardwired_spec("dyld", "strcpy",
+                         (Addr)&VG_(x86_darwin_REDIR_FOR_strcpy), NULL);
+      add_hardwired_spec("dyld", "strlcat",
+                         (Addr)&VG_(x86_darwin_REDIR_FOR_strlcat), NULL);
+   }
+
+#  elif defined(VGP_amd64_darwin)

    /* If we're using memcheck, use these intercepts right from
       the start, otherwise dyld makes a lot of noise. */
    if (0==VG_(strcmp)("Memcheck", VG_(details).name)) {
       add_hardwired_spec("dyld", "strcmp",
    /* If we're using memcheck, use these intercepts right from
       the start, otherwise dyld makes a lot of noise. */
    if (0==VG_(strcmp)("Memcheck", VG_(details).name)) {
       add_hardwired_spec("dyld", "strcmp",

-                         (Addr)&VG_(darwin_REDIR_FOR_strcmp), NULL);
+                         (Addr)&VG_(amd64_darwin_REDIR_FOR_strcmp), NULL);

       add_hardwired_spec("dyld", "strlen",
       add_hardwired_spec("dyld", "strlen",

-                         (Addr)&VG_(darwin_REDIR_FOR_strlen), NULL);
+                         (Addr)&VG_(amd64_darwin_REDIR_FOR_strlen), NULL);

       add_hardwired_spec("dyld", "strcat",
       add_hardwired_spec("dyld", "strcat",

-                         (Addr)&VG_(darwin_REDIR_FOR_strcat), NULL);
+                         (Addr)&VG_(amd64_darwin_REDIR_FOR_strcat), NULL);

       add_hardwired_spec("dyld", "strcpy",
       add_hardwired_spec("dyld", "strcpy",

-                         (Addr)&VG_(darwin_REDIR_FOR_strcpy), NULL);
+                         (Addr)&VG_(amd64_darwin_REDIR_FOR_strcpy), NULL);

       add_hardwired_spec("dyld", "strlcat",
       add_hardwired_spec("dyld", "strlcat",

-                         (Addr)&VG_(darwin_REDIR_FOR_strlcat), NULL);
-#     if defined(VGP_amd64_darwin)
+                         (Addr)&VG_(amd64_darwin_REDIR_FOR_strlcat), NULL);

       // DDD: #warning fixme rdar://6166275
       add_hardwired_spec("dyld", "arc4random",
       // DDD: #warning fixme rdar://6166275
       add_hardwired_spec("dyld", "arc4random",

-                         (Addr)&VG_(darwin_REDIR_FOR_arc4random), NULL);
-#     endif
+                         (Addr)&VG_(amd64_darwin_REDIR_FOR_arc4random), NULL);

    }
 
 #  elif defined(VGO_l4re)
    }
 
 #  elif defined(VGO_l4re)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_replacemalloc/replacemalloc_core.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_replacemalloc/replacemalloc_core.c
index 7bcbaaefdb0d49046356514a883c53e79b6c689f..c861fde4df4986845fce6325c5aff24afde63f54 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_replacemalloc/replacemalloc_core.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_replacemalloc/replacemalloc_core.c
@@ -58,12 +58,9 @@ Bool VG_(replacement_malloc_process_cmd_line_option)(Char* arg)
           VG_(clo_alignment) > 4096 ||
           VG_(log2)( VG_(clo_alignment) ) == -1 /* not a power of 2 */)
       {
           VG_(clo_alignment) > 4096 ||
           VG_(log2)( VG_(clo_alignment) ) == -1 /* not a power of 2 */)
       {

-         VG_(message)(Vg_UserMsg, 
-            "Invalid --alignment= setting.  "
-            "Should be a power of 2, >= %d, <= 4096.\n",
-            VG_MIN_MALLOC_SZB
-         );
-         VG_(err_bad_option)("--alignment");
+         VG_(fmsg_bad_option)(arg,
+            "Alignment must be a power of 2 in the range %d..4096.\n",
+            VG_MIN_MALLOC_SZB);

       }
    }
 
       }
    }
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_replacemalloc/vg_replace_malloc.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_replacemalloc/vg_replace_malloc.c
index 42e4731cae38a6841154aefcd9ab4be3fd165aad..b861e06dd9619d6fc899374b3f581b231f6d6864 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_replacemalloc/vg_replace_malloc.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_replacemalloc/vg_replace_malloc.c
@@ -219,7 +219,7 @@ static void init(void);
       v = (void*)VALGRIND_NON_SIMD_CALL1( info.tl_##vg_replacement, n ); \
       MALLOC_TRACE(" = %p\n", v ); \
       if (NULL == v) { \
       v = (void*)VALGRIND_NON_SIMD_CALL1( info.tl_##vg_replacement, n ); \
       MALLOC_TRACE(" = %p\n", v ); \
       if (NULL == v) { \

-         VALGRIND_PRINTF_BACKTRACE( \
+         VALGRIND_PRINTF( \

             "new/new[] failed and should throw an exception, but Valgrind\n"); \
          VALGRIND_PRINTF_BACKTRACE( \
             "   cannot throw exceptions and so is aborting instead.  Sorry.\n"); \
             "new/new[] failed and should throw an exception, but Valgrind\n"); \
          VALGRIND_PRINTF_BACKTRACE( \
             "   cannot throw exceptions and so is aborting instead.  Sorry.\n"); \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_scheduler/scheduler.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_scheduler/scheduler.c
index e3d1f91bd60d1af9ac28634a898bd942e9f3a06b..fc21dfe787e6e7449015b75b64024ff567292d6d 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_scheduler/scheduler.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_scheduler/scheduler.c
@@ -204,9 +204,11 @@ ThreadId VG_(alloc_ThreadState) ( void )
 
          VG_(threads)[i].os_state.utcb = (l4_utcb_t *)ts_utcb_copy(&VG_(threads)[i]);
 
 
          VG_(threads)[i].os_state.utcb = (l4_utcb_t *)ts_utcb_copy(&VG_(threads)[i]);
 

+#if 0

          // copy current utcb as initial utcb into thread state
          l4_utcb_t *utcb = l4_utcb_wrap();
          VG_(memcpy)(ts_utcb(&VG_(threads)[i]), utcb, L4RE_UTCB_SIZE);
          // copy current utcb as initial utcb into thread state
          l4_utcb_t *utcb = l4_utcb_wrap();
          VG_(memcpy)(ts_utcb(&VG_(threads)[i]), utcb, L4RE_UTCB_SIZE);

+#endif

 #endif
          return i;
       }
 #endif
          return i;
       }


@@ -686,6 +688,16 @@ static void do_pre_run_checks ( ThreadState* tst )
    vg_assert(sz_spill == LibVEX_N_SPILL_BYTES);
    vg_assert(a_vex + 3 * sz_vex == a_spill);
 
    vg_assert(sz_spill == LibVEX_N_SPILL_BYTES);
    vg_assert(a_vex + 3 * sz_vex == a_spill);
 

+#  if defined(VGA_amd64)
+   /* x86/amd64 XMM regs must form an array, ie, have no
+      holes in between. */
+   vg_assert(
+      (offsetof(VexGuestAMD64State,guest_XMM16)
+       - offsetof(VexGuestAMD64State,guest_XMM0))
+      == (17/*#regs*/-1) * 16/*bytes per reg*/
+   );
+#  endif
+

 #  if defined(VGA_ppc32) || defined(VGA_ppc64)
    /* ppc guest_state vector regs must be 16 byte aligned for
       loads/stores.  This is important! */
 #  if defined(VGA_ppc32) || defined(VGA_ppc64)
    /* ppc guest_state vector regs must be 16 byte aligned for
       loads/stores.  This is important! */


@@ -696,7 +708,7 @@ static void do_pre_run_checks ( ThreadState* tst )
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_VR1));

-#  endif   
+#  endif

 
 #  if defined(VGA_arm)
    /* arm guest_state VFP regs must be 8 byte aligned for
 
 #  if defined(VGA_arm)
    /* arm guest_state VFP regs must be 8 byte aligned for


@@ -1671,6 +1683,35 @@ void do_client_request ( ThreadId tid )
          SET_CLREQ_RETVAL( tid, 0 );     /* return value is meaningless */
          break;
 
          SET_CLREQ_RETVAL( tid, 0 );     /* return value is meaningless */
          break;
 

+      case VG_USERREQ__MAP_IP_TO_SRCLOC: {
+         Addr   ip    = arg[1];
+         UChar* buf64 = (UChar*)arg[2];
+
+         VG_(memset)(buf64, 0, 64);
+         UInt linenum = 0;
+         Bool ok = VG_(get_filename_linenum)(
+                      ip, &buf64[0], 50, NULL, 0, NULL, &linenum
+                   );
+         if (ok) {
+            /* Find the terminating zero in the first 50 bytes. */
+            UInt i;
+            for (i = 0; i < 50; i++) {
+               if (buf64[i] == 0)
+                  break;
+            }
+            /* We must find a zero somewhere in 0 .. 49.  Else
+               VG_(get_filename_linenum) is not properly zero
+               terminating. */
+            vg_assert(i < 50);
+            VG_(sprintf)(&buf64[i], ":%u", linenum);
+         } else {
+            buf64[0] = 0;
+         }
+
+         SET_CLREQ_RETVAL( tid, 0 ); /* return value is meaningless */
+         break;
+      }
+

       case VG_USERREQ__MALLOCLIKE_BLOCK:
       case VG_USERREQ__FREELIKE_BLOCK:
          // Ignore them if the addr is NULL;  otherwise pass onto the tool.
       case VG_USERREQ__MALLOCLIKE_BLOCK:
       case VG_USERREQ__FREELIKE_BLOCK:
          // Ignore them if the addr is NULL;  otherwise pass onto the tool.

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-amd64-darwin.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-amd64-darwin.c
index 6be95757b5dad1545cc2ccc5f12e3e809708409e..273dea53b7af73b16bb343bce46c6bc891433d1e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-amd64-darwin.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-amd64-darwin.c
@@ -47,6 +47,64 @@
 #include "pub_core_sigframe.h"      /* self */
 
 
 #include "pub_core_sigframe.h"      /* self */
 
 

+/* Cheap-ass hack copied from ppc32-aix5 code, just to get started.
+   Produce a frame with layout entirely of our own choosing. */
+
+/* This module creates and removes signal frames for signal deliveries
+   on amd64-darwin.  Kludgey; the machine state ought to be saved in a
+   ucontext and retrieved from it later, so the handler can modify it
+   and return.  However .. for now .. just stick the vex guest state
+   in the frame and snarf it again later.
+
+   Also, don't bother with creating siginfo and ucontext in the
+   handler, although do point them somewhere non-faulting.
+
+   Frame should have a 16-aligned size, just in case that turns out to
+   be important for Darwin.  (be conservative)
+*/
+struct hacky_sigframe {
+   /* first word looks like a call to a 3-arg amd64-ELF function */
+   ULong               returnAddr;
+   UChar               lower_guardzone[512];  // put nothing here
+   VexGuestAMD64State  gst;
+   VexGuestAMD64State  gshadow1;
+   VexGuestAMD64State  gshadow2;
+   vki_siginfo_t       fake_siginfo;
+   struct vki_ucontext fake_ucontext;
+   UInt                magicPI;
+   UInt                sigNo_private;
+   vki_sigset_t        mask; // saved sigmask; restore when hdlr returns
+   UInt                __pad[2];
+   UChar               upper_guardzone[512]; // put nothing here
+   // and don't zero it, since that might overwrite the client's
+   // stack redzone, at least on archs which have one
+};
+
+
+/* Extend the stack segment downwards if needed so as to ensure the
+   new signal frames are mapped to something.  Return a Bool
+   indicating whether or not the operation was successful.
+*/
+static Bool extend ( ThreadState *tst, Addr addr, SizeT size )
+{
+   ThreadId tid = tst->tid;
+   /* For tracking memory events, indicate the entire frame has been
+      allocated.  Except, don't mess with the area which
+      overlaps the previous frame's redzone. */
+   /* XXX is the following call really right?  compared with the
+      amd64-linux version, this doesn't appear to handle the redzone
+      in the same way. */
+   VG_TRACK( new_mem_stack_signal,
+             addr - VG_STACK_REDZONE_SZB, size, tid );
+   return True;
+}
+
+
+/* Create a signal frame for thread 'tid'.  Make a 3-arg frame
+   regardless of whether the client originally requested a 1-arg
+   version (no SA_SIGINFO) or a 3-arg one (SA_SIGINFO) since in the
+   former case, the amd64 calling conventions will simply cause the
+   extra 2 args to be ignored (inside the handler).  (We hope!) */

 void VG_(sigframe_create) ( ThreadId tid,
                             Addr sp_top_of_frame,
                             const vki_siginfo_t *siginfo,
 void VG_(sigframe_create) ( ThreadId tid,
                             Addr sp_top_of_frame,
                             const vki_siginfo_t *siginfo,


@@ -56,13 +114,121 @@ void VG_(sigframe_create) ( ThreadId tid,
                             const vki_sigset_t *mask,
                             void *restorer )
 {
                             const vki_sigset_t *mask,
                             void *restorer )
 {

-   I_die_here;
+   ThreadState* tst;
+   Addr rsp;
+   struct hacky_sigframe* frame;
+   Int sigNo = siginfo->si_signo;
+
+   vg_assert(VG_IS_16_ALIGNED(sizeof(struct hacky_sigframe)));
+
+   sp_top_of_frame &= ~0xfUL;
+   rsp = sp_top_of_frame - sizeof(struct hacky_sigframe);
+
+   tst = VG_(get_ThreadState)(tid);
+   if (!extend(tst, rsp, sp_top_of_frame - rsp))
+      return;
+
+   vg_assert(VG_IS_16_ALIGNED(rsp));
+
+   frame = (struct hacky_sigframe *) rsp;
+
+   /* clear it (very conservatively) (why so conservatively??) */
+   VG_(memset)(&frame->lower_guardzone, 0, 512);
+   VG_(memset)(&frame->gst,      0, sizeof(VexGuestAMD64State));
+   VG_(memset)(&frame->gshadow1, 0, sizeof(VexGuestAMD64State));
+   VG_(memset)(&frame->gshadow2, 0, sizeof(VexGuestAMD64State));
+   VG_(memset)(&frame->fake_siginfo,  0, sizeof(frame->fake_siginfo));
+   VG_(memset)(&frame->fake_ucontext, 0, sizeof(frame->fake_ucontext));
+
+   /* save stuff in frame */
+   frame->gst           = tst->arch.vex;
+   frame->gshadow1      = tst->arch.vex_shadow1;
+   frame->gshadow2      = tst->arch.vex_shadow2;
+   frame->sigNo_private = sigNo;
+   frame->mask          = tst->sig_mask;
+   frame->magicPI       = 0x31415927;
+
+   /* Minimally fill in the siginfo and ucontext.  Note, utter
+      lameness prevails.  Be underwhelmed, be very underwhelmed. */
+   frame->fake_siginfo.si_signo = sigNo;
+   frame->fake_siginfo.si_code  = siginfo->si_code;
+
+   /* Set up stack pointer */
+   vg_assert(rsp == (Addr)&frame->returnAddr);
+   VG_(set_SP)(tid, rsp);
+   VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR, sizeof(ULong));
+
+   /* Set up program counter */
+   VG_(set_IP)(tid, (ULong)handler);
+   VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_INSTR_PTR, sizeof(ULong));
+
+   /* Set up RA and args for the frame */
+   VG_TRACK( pre_mem_write, Vg_CoreSignal, tid, "signal handler frame",
+             (Addr)frame, 1*sizeof(ULong) );
+   frame->returnAddr  = (ULong)&VG_(amd64_darwin_SUBST_FOR_sigreturn);
+
+   /* XXX should tell the tool that these regs got written */
+   tst->arch.vex.guest_RDI = (ULong) sigNo;
+   tst->arch.vex.guest_RSI = (Addr)  &frame->fake_siginfo;/* oh well */
+   tst->arch.vex.guest_RDX = (Addr)  &frame->fake_ucontext; /* oh well */
+
+   VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
+             (Addr)frame, 1*sizeof(ULong) );
+   VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
+             (Addr)&frame->fake_siginfo, sizeof(frame->fake_siginfo));
+   VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
+             (Addr)&frame->fake_ucontext, sizeof(frame->fake_ucontext));
+
+   if (VG_(clo_trace_signals))
+      VG_(message)(Vg_DebugMsg,
+                   "sigframe_create (thread %d): next EIP=%#lx, next ESP=%#lx",
+                   tid, (Addr)handler, (Addr)frame );

 }
 
 
 }
 
 

+/* Remove a signal frame from thread 'tid's stack, and restore the CPU
+   state from it.  Note, isRT is irrelevant here. */

 void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
 {
 void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
 {

-   I_die_here;
+   ThreadState *tst;
+   Addr rsp;
+   Int sigNo;
+   struct hacky_sigframe* frame;
+ 
+   vg_assert(VG_(is_valid_tid)(tid));
+   tst = VG_(get_ThreadState)(tid);
+
+   /* Check that the stack frame looks valid */
+   rsp = VG_(get_SP)(tid);
+
+   /* why -8 ? because the signal handler's return will have popped
+      the return address of the stack; and the return address is the
+      lowest-addressed element of hacky_sigframe. */
+   frame = (struct hacky_sigframe*)(rsp - 8);
+   vg_assert(frame->magicPI == 0x31415927);
+   vg_assert(VG_IS_16_ALIGNED(frame));
+
+   /* restore the entire guest state, and shadows, from the
+      frame.  Note, as per comments above, this is a kludge - should
+      restore it from saved ucontext.  Oh well. */
+   tst->arch.vex = frame->gst;
+   tst->arch.vex_shadow1 = frame->gshadow1;
+   tst->arch.vex_shadow2 = frame->gshadow2;
+   tst->sig_mask = frame->mask;
+   tst->tmp_sig_mask = frame->mask;
+   sigNo = frame->sigNo_private;
+
+   if (VG_(clo_trace_signals))
+      VG_(message)(Vg_DebugMsg,
+                   "sigframe_destroy (thread %d): valid magic; next RIP=%#llx",
+                   tid, tst->arch.vex.guest_RIP);
+
+   VG_TRACK( die_mem_stack_signal, 
+             (Addr)frame - VG_STACK_REDZONE_SZB, 
+             sizeof(struct hacky_sigframe) );
+
+   /* tell the tools */
+   VG_TRACK( post_deliver_signal, tid, sigNo );

 }
 
 #endif // defined(VGP_amd64_darwin)
 }
 
 #endif // defined(VGP_amd64_darwin)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-arm-linux.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-arm-linux.c
index 11e01451d3753629206192aee0bba25b1a69fe17..01c1c058c48b913313ef86ae02020fde899d0668 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-arm-linux.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-arm-linux.c
@@ -139,7 +139,7 @@ static void synth_ucontext( ThreadId tid, const vki_siginfo_t *si,
    SC2(ip,R12);
    SC2(sp,R13);
    SC2(lr,R14);
    SC2(ip,R12);
    SC2(sp,R13);
    SC2(lr,R14);

-   SC2(pc,R15);
+   SC2(pc,R15T);

 #  undef SC2
 
    sc->trap_no = trapno;
 #  undef SC2
 
    sc->trap_no = trapno;


@@ -236,20 +236,20 @@ void VG_(sigframe_create)( ThreadId tid,
       tst->arch.vex.guest_R1 = (Addr)&rsf->info;
       tst->arch.vex.guest_R2 = (Addr)&rsf->sig.uc;
    }
       tst->arch.vex.guest_R1 = (Addr)&rsf->info;
       tst->arch.vex.guest_R2 = (Addr)&rsf->sig.uc;
    }

-   else{
+   else {

       build_sigframe(tst, (struct sigframe *)sp, siginfo, siguc,
                              handler, flags, mask, restorer);
       build_sigframe(tst, (struct sigframe *)sp, siginfo, siguc,
                              handler, flags, mask, restorer);

-    }
+   }

 
    VG_(set_SP)(tid, sp);
    VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR,
          sizeof(Addr));
 
    VG_(set_SP)(tid, sp);
    VG_TRACK( post_reg_write, Vg_CoreSignal, tid, VG_O_STACK_PTR,
          sizeof(Addr));

-    tst->arch.vex.guest_R0  = sigNo; 
+   tst->arch.vex.guest_R0  = sigNo; 

 
 

-    if(flags & VKI_SA_RESTORER)
-        tst->arch.vex.guest_R14 = (Addr) restorer; 
+   if (flags & VKI_SA_RESTORER)
+       tst->arch.vex.guest_R14 = (Addr) restorer; 

 
 

-   tst->arch.vex.guest_R15 = (Addr) handler; /* R15 == PC */
+   tst->arch.vex.guest_R15T = (Addr) handler; /* R15 == PC */

 }
 
 
 }
 
 


@@ -312,7 +312,7 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
    REST(ip,R12);
    REST(sp,R13);
    REST(lr,R14);
    REST(ip,R12);
    REST(sp,R13);
    REST(lr,R14);

-   REST(pc,R15);
+   REST(pc,R15T);

 #  undef REST
 
    tst->arch.vex_shadow1 = priv->vex_shadow1;
 #  undef REST
 
    tst->arch.vex_shadow1 = priv->vex_shadow1;


@@ -323,8 +323,9 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
              
    if (VG_(clo_trace_signals))
       VG_(message)(Vg_DebugMsg,
              
    if (VG_(clo_trace_signals))
       VG_(message)(Vg_DebugMsg,

-                   "vg_pop_signal_frame (thread %d): isRT=%d valid magic; PC=%#x",
-                   tid, has_siginfo, tst->arch.vex.guest_R15);
+                   "vg_pop_signal_frame (thread %d): "
+                   "isRT=%d valid magic; PC=%#x",
+                   tid, has_siginfo, tst->arch.vex.guest_R15T);

 
    /* tell the tools */
    VG_TRACK( post_deliver_signal, tid, sigNo );
 
    /* tell the tools */
    VG_TRACK( post_deliver_signal, tid, sigNo );

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-x86-darwin.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-x86-darwin.c
index f36f987031a9efff574f027ace3047366942a57a..383a8d3dcfd397a4bbacb4f4579e1e4cd78041d2 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-x86-darwin.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_sigframe/sigframe-x86-darwin.c
@@ -79,6 +79,8 @@ struct hacky_sigframe {
    vki_sigset_t     mask; // saved sigmask; restore when hdlr returns
    UInt             __pad[1];
    UChar            upper_guardzone[512]; // put nothing here
    vki_sigset_t     mask; // saved sigmask; restore when hdlr returns
    UInt             __pad[1];
    UChar            upper_guardzone[512]; // put nothing here

+   // and don't zero it, since that might overwrite the client's
+   // stack redzone, at least on archs which have one

 };
 
 
 };
 
 


@@ -96,7 +98,7 @@ static Bool extend ( ThreadState *tst, Addr addr, SizeT size )
       amd64-linux version, this doesn't appear to handle the redzone
       in the same way. */
    VG_TRACK( new_mem_stack_signal,
       amd64-linux version, this doesn't appear to handle the redzone
       in the same way. */
    VG_TRACK( new_mem_stack_signal,

-             addr, size - VG_STACK_REDZONE_SZB, tid );
+             addr - VG_STACK_REDZONE_SZB, size, tid );

    return True;
 }
 
    return True;
 }
 


@@ -222,8 +224,8 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
                    tid, tst->arch.vex.guest_EIP);
 
    VG_TRACK( die_mem_stack_signal, 
                    tid, tst->arch.vex.guest_EIP);
 
    VG_TRACK( die_mem_stack_signal, 

-             (Addr)frame, 
-             sizeof(struct hacky_sigframe) - VG_STACK_REDZONE_SZB );
+             (Addr)frame - VG_STACK_REDZONE_SZB, 
+             sizeof(struct hacky_sigframe) );

 
    /* tell the tools */
    VG_TRACK( post_deliver_signal, tid, sigNo );
 
    /* tell the tools */
    VG_TRACK( post_deliver_signal, tid, sigNo );

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_signals.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_signals.c
index bcc9a01ef3c69414b097784501c011466d991858..dd29fc43ba69115ed9535ce07ffab1b78edb7bdd 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_signals.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_signals.c
@@ -516,10 +516,9 @@ typedef struct SigQueue {
                                                     UWord scclass ) {
       I_die_here;
    }
                                                     UWord scclass ) {
       I_die_here;
    }

-   static inline Addr VG_UCONTEXT_LINK_REG( void* ucV ) {
-      return 0; /* No, really.  We have no LRs today. */
-   }
-   static inline Addr VG_UCONTEXT_FRAME_PTR( void* ucV ) {
+   static inline
+   void VG_UCONTEXT_TO_UnwindStartRegs( UnwindStartRegs* srP,
+                                        void* ucV ) {

       I_die_here;
    }
 
       I_die_here;
    }
 


@@ -994,7 +993,7 @@ SysRes VG_(do_sys_sigaltstack) ( ThreadId tid, vki_stack_t* ss, vki_stack_t* oss
    m_SP  = VG_(get_SP)(tid);
 
    if (VG_(clo_trace_signals))
    m_SP  = VG_(get_SP)(tid);
 
    if (VG_(clo_trace_signals))

-      VG_(emsg)("sys_sigaltstack: tid %d, "
+      VG_(dmsg)("sys_sigaltstack: tid %d, "

                 "ss %p{%p,sz=%llu,flags=0x%llx}, oss %p (current SP %p)\n",
                 tid, (void*)ss, 
                 ss ? ss->ss_sp : 0,
                 "ss %p{%p,sz=%llu,flags=0x%llx}, oss %p (current SP %p)\n",
                 tid, (void*)ss, 
                 ss ? ss->ss_sp : 0,


@@ -1039,7 +1038,7 @@ SysRes VG_(do_sys_sigaction) ( Int signo,
                                vki_sigaction_fromK_t* old_act )
 {
    if (VG_(clo_trace_signals))
                                vki_sigaction_fromK_t* old_act )
 {
    if (VG_(clo_trace_signals))

-      VG_(emsg)("sys_sigaction: sigNo %d, "
+      VG_(dmsg)("sys_sigaction: sigNo %d, "

                 "new %#lx, old %#lx, new flags 0x%llx\n",
                 signo, (UWord)new_act, (UWord)old_act,
                 (ULong)(new_act ? new_act->sa_flags : 0));
                 "new %#lx, old %#lx, new flags 0x%llx\n",
                 signo, (UWord)new_act, (UWord)old_act,
                 (ULong)(new_act ? new_act->sa_flags : 0));


@@ -1188,7 +1187,7 @@ void do_setmask ( ThreadId tid,
                  vki_sigset_t* oldset )
 {
    if (VG_(clo_trace_signals))
                  vki_sigset_t* oldset )
 {
    if (VG_(clo_trace_signals))

-      VG_(emsg)("do_setmask: tid = %d how = %d (%s), newset = %p (%s)\n", 
+      VG_(dmsg)("do_setmask: tid = %d how = %d (%s), newset = %p (%s)\n", 

                 tid, how,
                 how==VKI_SIG_BLOCK ? "SIG_BLOCK" : (
                    how==VKI_SIG_UNBLOCK ? "SIG_UNBLOCK" : (
                 tid, how,
                 how==VKI_SIG_BLOCK ? "SIG_BLOCK" : (
                    how==VKI_SIG_UNBLOCK ? "SIG_UNBLOCK" : (


@@ -1200,7 +1199,7 @@ void do_setmask ( ThreadId tid,
    if (oldset) {
       *oldset = VG_(threads)[tid].sig_mask;
       if (VG_(clo_trace_signals))
    if (oldset) {
       *oldset = VG_(threads)[tid].sig_mask;
       if (VG_(clo_trace_signals))

-         VG_(emsg)("\toldset=%p %s\n", oldset, format_sigset(oldset));
+         VG_(dmsg)("\toldset=%p %s\n", oldset, format_sigset(oldset));

    }
    if (newset) {
       do_sigprocmask_bitops (how, &VG_(threads)[tid].sig_mask, newset );
    }
    if (newset) {
       do_sigprocmask_bitops (how, &VG_(threads)[tid].sig_mask, newset );


@@ -2599,7 +2598,7 @@ void VG_(sigstartup_actions) ( void )
       /* Get the old host action */
       ret = VG_(sigaction)(i, NULL, &sa);
 
       /* Get the old host action */
       ret = VG_(sigaction)(i, NULL, &sa);
 

-#     if defined(VGP_x86_darwin)
+#     if defined(VGP_x86_darwin) || defined(VGP_amd64_darwin)

       /* apparently we may not even ask about the disposition of these
          signals, let alone change them */
       if (ret != 0 && (i == VKI_SIGKILL || i == VKI_SIGSTOP))
       /* apparently we may not even ask about the disposition of these
          signals, let alone change them */
       if (ret != 0 && (i == VKI_SIGKILL || i == VKI_SIGSTOP))

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_start-amd64-darwin.S b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_start-amd64-darwin.S
index edd96130bc4e84da27fb22d3899d3bb8a6c31ba0..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_start-amd64-darwin.S
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_start-amd64-darwin.S
@@ -1,88 +0,0 @@
-
-/*--------------------------------------------------------------------*/
-/*--- Darwin amd64 bootstrap.               m_start-amd64-darwin.S ---*/
-/*--------------------------------------------------------------------*/
-
-/*
-   This file is part of Valgrind, a dynamic binary instrumentation
-   framework.
-
-   Copyright (C) 2007 Apple Inc.
-      Greg Parker  gparker@apple.com
-
-   This program is free software; you can redistribute it and/or
-   modify it under the terms of the GNU General Public License as
-   published by the Free Software Foundation; either version 2 of the
-   License, or (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful, but
-   WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-   02111-1307, USA.
-
-   The GNU General Public License is contained in the file COPYING.
-*/
-
-#if defined(VGP_amd64_darwin)
-
-#include "pub_core_basics_asm.h"
-
-       .text
-       .align  3,0x90
-Ldyld_stub_binding_helper:
-        pushq   %r11
-        leaq    ___dso_handle(%rip), %r11
-        pushq   %r11
-       jmpq    *Ldyld_lazy_symbol_binding_entry_point(%rip)
-
-       .dyld
-       .align  3
-Ldyld_lazy_symbol_binding_entry_point:
-       .quad   0
-       .quad   0
-       .quad   0
-       .quad   0
-       .quad   0
-       .quad   Ldyld_stub_binding_helper
-       .quad   0
-
-               
-       // Memory layout established by kernel:
-       //
-       //        0
-       //        executable_name
-       //        0
-       //        envp[n]
-       //        ...
-       //        envp[0]
-       //        0
-       //        argv[argc-1]
-       //        ...
-       // sp+8-> argv[0]
-       // sp  -> argc
-       
-       .text
-       .align 3,0x90
-       .globl __start
-__start:
-       movq    %rsp, %rdi      // save &argc
-       andq    $-16, %rsp      // align stack
-       pushq   $0              // push NULL "return address" for backtraces
-       pushq   $0              // push fake saved ebp and align stack
-       movq    %rsp, %rbp      // save frame pointer
-       call    __start_in_C_darwin  // __start_in_C_darwin(&argc)
-       
-       // should not reach here
-       int $3
-       int $3
-
-#endif // defined(VGP_amd64_darwin)
-
-/*--------------------------------------------------------------------*/
-/*--- end                                                          ---*/
-/*--------------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_start-x86-darwin.S b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_start-x86-darwin.S
index 10e7e13ae2d6198a72f56f8342fd80b412d81f04..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_start-x86-darwin.S
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_start-x86-darwin.S
@@ -1,88 +0,0 @@
-
-/*--------------------------------------------------------------------*/
-/*--- Darwin x86 bootstrap.                   m_start-x86-darwin.S ---*/
-/*--------------------------------------------------------------------*/
-
-/*
-   This file is part of Valgrind, a dynamic binary instrumentation
-   framework.
-
-   Copyright (C) 2007 Apple Inc.
-      Greg Parker  gparker@apple.com
-
-   This program is free software; you can redistribute it and/or
-   modify it under the terms of the GNU General Public License as
-   published by the Free Software Foundation; either version 2 of the
-   License, or (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful, but
-   WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-   02111-1307, USA.
-
-   The GNU General Public License is contained in the file COPYING.
-*/
-
-#if defined(VGP_x86_darwin)
-
-#include "pub_core_basics_asm.h"
-
-       .text
-       .align  2,0x90
-Ldyld_stub_binding_helper:
-       pushl   $__mh_execute_header
-       jmpl    *Ldyld_lazy_symbol_binding_entry_point
-
-       .dyld
-       .align  2
-Ldyld_lazy_symbol_binding_entry_point:
-       .long   0
-       .long   0
-       .long   0
-       .long   0
-       .long   0
-       .long   Ldyld_stub_binding_helper
-       .long   0
-
-               
-       // Memory layout established by kernel:
-       //
-       //        0
-       //        executable_name
-       //        0
-       //        envp[n]
-       //        ...
-       //        envp[0]
-       //        0
-       //        argv[argc-1]
-       //        ...
-       // sp+4-> argv[0]
-       // sp  -> argc
-       
-       .text
-       .align 2,0x90
-       .globl __start
-__start:
-       movl    %esp, %eax      // save &argc
-       andl    $-16, %esp      // align stack
-       pushl   $0              // push NULL "return address" for backtraces
-       pushl   $0              // push fake saved ebp
-       movl    %esp, %ebp      // save frame pointer
-       pushl   $0              // align stack
-       pushl   %eax            // start_in_C_darwin(&argc)
-       call    __start_in_C_darwin
-       
-       // should not reach here
-       int $3
-       int $3
-
-#endif // defined(VGP_x86_darwin)
-
-/*--------------------------------------------------------------------*/
-/*--- end                                                          ---*/
-/*--------------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/priv_syswrap-darwin.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/priv_syswrap-darwin.h
index 3fb16564c1cae5dc4cf1f01baa90e4e0ae9b446e..17ffcc6897161d62fdabbebde5d8e307e7a3410d 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/priv_syswrap-darwin.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/priv_syswrap-darwin.h
@@ -393,7 +393,9 @@ DECL_TEMPLATE(darwin, __pthread_markcancel);    // 332
 DECL_TEMPLATE(darwin, __pthread_canceled);      // 333
 DECL_TEMPLATE(darwin, __semwait_signal);        // 334
 // old utrace
 DECL_TEMPLATE(darwin, __pthread_canceled);      // 333
 DECL_TEMPLATE(darwin, __semwait_signal);        // 334
 // old utrace

-// NYI proc_info 336
+#if DARWIN_VERS >= DARWIN_10_6
+DECL_TEMPLATE(darwin, proc_info);               // 336
+#endif

 DECL_TEMPLATE(darwin, sendfile);                // 337
 DECL_TEMPLATE(darwin, stat64);                  // 338
 DECL_TEMPLATE(darwin, fstat64);                 // 339
 DECL_TEMPLATE(darwin, sendfile);                // 337
 DECL_TEMPLATE(darwin, stat64);                  // 338
 DECL_TEMPLATE(darwin, fstat64);                 // 339


@@ -429,7 +431,7 @@ DECL_TEMPLATE(darwin, workq_ops);               // 368
 // 369
 // 370
 // 371
 // 369
 // 370
 // 371

-// 372
+DECL_TEMPLATE(darwin, __thread_selfid);         // 372

 // 373
 // 374
 // 375
 // 373
 // 374
 // 375


@@ -484,6 +486,9 @@ DECL_TEMPLATE(darwin, __mac_syscall);           // 381
 // NYI __mac_mount 424
 // NYI __mac_get_mount 425
 // NYI __mac_getfsstat 426
 // NYI __mac_mount 424
 // NYI __mac_get_mount 425
 // NYI __mac_getfsstat 426

+DECL_TEMPLATE(darwin, fsgetpath);                // 427
+DECL_TEMPLATE(darwin, audit_session_self);       // 428
+// NYI audit_session_join 429

 
 // Mach message helpers
 DECL_TEMPLATE(darwin, host_info);
 
 // Mach message helpers
 DECL_TEMPLATE(darwin, host_info);


@@ -498,9 +503,11 @@ DECL_TEMPLATE(darwin, mach_port_deallocate);
 DECL_TEMPLATE(darwin, mach_port_get_refs);
 DECL_TEMPLATE(darwin, mach_port_mod_refs);
 DECL_TEMPLATE(darwin, mach_port_get_set_status);
 DECL_TEMPLATE(darwin, mach_port_get_refs);
 DECL_TEMPLATE(darwin, mach_port_mod_refs);
 DECL_TEMPLATE(darwin, mach_port_get_set_status);

+DECL_TEMPLATE(darwin, mach_port_move_member);

 DECL_TEMPLATE(darwin, mach_port_destroy);
 DECL_TEMPLATE(darwin, mach_port_request_notification);
 DECL_TEMPLATE(darwin, mach_port_insert_right);
 DECL_TEMPLATE(darwin, mach_port_destroy);
 DECL_TEMPLATE(darwin, mach_port_request_notification);
 DECL_TEMPLATE(darwin, mach_port_insert_right);

+DECL_TEMPLATE(darwin, mach_port_extract_right);

 DECL_TEMPLATE(darwin, mach_port_get_attributes);
 DECL_TEMPLATE(darwin, mach_port_set_attributes);
 DECL_TEMPLATE(darwin, mach_port_insert_member);
 DECL_TEMPLATE(darwin, mach_port_get_attributes);
 DECL_TEMPLATE(darwin, mach_port_set_attributes);
 DECL_TEMPLATE(darwin, mach_port_insert_member);


@@ -537,6 +544,7 @@ DECL_TEMPLATE(darwin, thread_create_running);
 DECL_TEMPLATE(darwin, thread_suspend);
 DECL_TEMPLATE(darwin, thread_get_state);
 DECL_TEMPLATE(darwin, thread_policy);
 DECL_TEMPLATE(darwin, thread_suspend);
 DECL_TEMPLATE(darwin, thread_get_state);
 DECL_TEMPLATE(darwin, thread_policy);

+DECL_TEMPLATE(darwin, thread_policy_set);

 DECL_TEMPLATE(darwin, thread_info);
 DECL_TEMPLATE(darwin, bootstrap_register);
 DECL_TEMPLATE(darwin, bootstrap_look_up);
 DECL_TEMPLATE(darwin, thread_info);
 DECL_TEMPLATE(darwin, bootstrap_register);
 DECL_TEMPLATE(darwin, bootstrap_look_up);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-amd64-darwin.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-amd64-darwin.c
index 70c5a9087623954f576a01fd5db586597942c084..1057bb108456cb58ac03e8f2347113a28176c6d7 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-amd64-darwin.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-amd64-darwin.c
@@ -288,6 +288,7 @@ asm(
 void pthread_hijack(Addr self, Addr kport, Addr func, Addr func_arg, 
                     Addr stacksize, Addr flags, Addr sp)
 {
 void pthread_hijack(Addr self, Addr kport, Addr func, Addr func_arg, 
                     Addr stacksize, Addr flags, Addr sp)
 {

+   vki_sigset_t blockall;

    ThreadState *tst = (ThreadState *)func_arg;
    VexGuestAMD64State *vex = &tst->arch.vex;
 
    ThreadState *tst = (ThreadState *)func_arg;
    VexGuestAMD64State *vex = &tst->arch.vex;
 


@@ -297,6 +298,11 @@ void pthread_hijack(Addr self, Addr kport, Addr func, Addr func_arg,
    // The parent thread holds V's lock on our behalf.
    semaphore_wait(tst->os_state.child_go);
 
    // The parent thread holds V's lock on our behalf.
    semaphore_wait(tst->os_state.child_go);
 

+   /* Start the thread with all signals blocked.  VG_(scheduler) will
+      set the mask correctly when we finally get there. */
+   VG_(sigfillset)(&blockall);
+   VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, NULL);
+

    // Set thread's registers
    // Do this FIRST because some code below tries to collect a backtrace, 
    // which requires valid register data.
    // Set thread's registers
    // Do this FIRST because some code below tries to collect a backtrace, 
    // which requires valid register data.


@@ -331,12 +337,17 @@ void pthread_hijack(Addr self, Addr kport, Addr func, Addr func_arg,
             VKI_PROT_READ|VKI_PROT_WRITE, VKI_MAP_PRIVATE, -1, 0);
       // guard page
       ML_(notify_core_and_tool_of_mmap)(
             VKI_PROT_READ|VKI_PROT_WRITE, VKI_MAP_PRIVATE, -1, 0);
       // guard page
       ML_(notify_core_and_tool_of_mmap)(

-            stack-VKI_PAGE_SIZE, VKI_PAGE_SIZE, 0, VKI_MAP_PRIVATE, -1, 0);
+            stack-VKI_PAGE_SIZE, VKI_PAGE_SIZE,
+            0, VKI_MAP_PRIVATE, -1, 0);

    } else {
       // client allocated stack
       find_stack_segment(tst->tid, sp);
    }
    } else {
       // client allocated stack
       find_stack_segment(tst->tid, sp);
    }

-   VG_(am_do_sync_check)("after", "pthread_hijack", 0);
+   ML_(sync_mappings)("after", "pthread_hijack", 0);
+
+   // DDD: should this be here rather than in POST(sys_bsdthread_create)?
+   // But we don't have ptid here...
+   //VG_TRACK ( pre_thread_ll_create, ptid, tst->tid );

 
    // Tell parent thread's POST(sys_bsdthread_create) that we're done 
    // initializing registers and mapping memory.
 
    // Tell parent thread's POST(sys_bsdthread_create) that we're done 
    // initializing registers and mapping memory.


@@ -363,8 +374,7 @@ asm(
     );
 
 
     );
 
 

-/*
-  wqthread note: The kernel may create or destroy pthreads in the 
+/*  wqthread note: The kernel may create or destroy pthreads in the 

     wqthread pool at any time with no userspace interaction, 
     and wqthread_start may be entered at any time with no userspace 
     interaction.
     wqthread pool at any time with no userspace interaction, 
     and wqthread_start may be entered at any time with no userspace 
     interaction.


@@ -378,6 +388,22 @@ void wqthread_hijack(Addr self, Addr kport, Addr stackaddr, Addr workitem,
    VexGuestAMD64State *vex;
    Addr stack;
    SizeT stacksize;
    VexGuestAMD64State *vex;
    Addr stack;
    SizeT stacksize;

+   vki_sigset_t blockall;
+
+   /* When we enter here we hold no lock (!), so we better acquire it
+      pronto.  Why do we hold no lock?  Because (presumably) the only
+      way to get here is as a result of a SfMayBlock syscall
+      "workq_ops(WQOPS_THREAD_RETURN)", which will have dropped the
+      lock.  At least that's clear for the 'reuse' case.  The
+      non-reuse case?  Dunno, perhaps it's a new thread the kernel
+      pulled out of a hat.  In any case we still need to take a
+      lock. */
+   VG_(acquire_BigLock_LL)("wqthread_hijack");
+
+   /* Start the thread with all signals blocked.  VG_(scheduler) will
+      set the mask correctly when we finally get there. */
+   VG_(sigfillset)(&blockall);
+   VG_(sigprocmask)(VKI_SIG_SETMASK, &blockall, NULL);

 
    if (reuse) {
        // This thread already exists; we're merely re-entering 
 
    if (reuse) {
        // This thread already exists; we're merely re-entering 


@@ -418,10 +444,18 @@ void wqthread_hijack(Addr self, Addr kport, Addr stackaddr, Addr workitem,
    if (reuse) {
       // Continue V's thread back in the scheduler. 
       // The client thread is of course in another location entirely.
    if (reuse) {
       // Continue V's thread back in the scheduler. 
       // The client thread is of course in another location entirely.

+
+      /* Drop the lock before going into
+         ML_(wqthread_continue_NORETURN).  The latter will immediately
+         attempt to reacquire it in non-LL mode, which is a bit
+         wasteful but I don't think is harmful.  A better solution
+         would be to not drop the lock but instead "upgrade" it from a
+         LL lock to a full lock, but that's too much like hard work
+         right now. */
+      VG_(release_BigLock_LL)("wqthread_hijack(1)");

       ML_(wqthread_continue_NORETURN)(tst->tid);
    } 
    else {
       ML_(wqthread_continue_NORETURN)(tst->tid);
    } 
    else {

-

       // Record thread's stack and Mach port and pthread struct
       tst->os_state.pthread = self;
       tst->os_state.lwpid = kport;
       // Record thread's stack and Mach port and pthread struct
       tst->os_state.pthread = self;
       tst->os_state.lwpid = kport;


@@ -445,11 +479,22 @@ void wqthread_hijack(Addr self, Addr kport, Addr stackaddr, Addr workitem,
       // guard page
       // GrP fixme ban_mem_stack!
       ML_(notify_core_and_tool_of_mmap)(
       // guard page
       // GrP fixme ban_mem_stack!
       ML_(notify_core_and_tool_of_mmap)(

-            stack-VKI_PAGE_SIZE, VKI_PAGE_SIZE, 0, VKI_MAP_PRIVATE, -1, 0);
+            stack-VKI_PAGE_SIZE, VKI_PAGE_SIZE,
+            0, VKI_MAP_PRIVATE, -1, 0);

 
 

-      VG_(am_do_sync_check)("after", "wqthread_hijack", 0);
+      ML_(sync_mappings)("after", "wqthread_hijack", 0);

 
       // Go!
 
       // Go!

+      /* Same comments as the 'release' in the then-clause.
+         start_thread_NORETURN calls run_thread_NORETURN calls
+         thread_wrapper which acquires the lock before continuing.
+         Let's hope nothing non-thread-local happens until that point.
+
+         DDD: I think this is plain wrong .. if we get to
+         thread_wrapper not holding the lock, and someone has recycled
+         this thread slot in the meantime, we're hosed.  Is that
+         possible, though? */
+      VG_(release_BigLock_LL)("wqthread_hijack(2)");

       call_on_new_stack_0_1(tst->os_state.valgrind_stack_init_SP, 0, 
                             start_thread_NORETURN, (Word)tst);
    }
       call_on_new_stack_0_1(tst->os_state.valgrind_stack_init_SP, 0, 
                             start_thread_NORETURN, (Word)tst);
    }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-amd64-linux.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-amd64-linux.c
index cf0170150b940f6532f7b5a5c830761bd74696c1..466fe1fb5d8e85ac3a6756d64563b02ea7e477a0 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-amd64-linux.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-amd64-linux.c
@@ -1343,7 +1343,7 @@ static SyscallTableEntry syscall_table[] = {
    LINXY(__NR_mq_open,           sys_mq_open),        // 240 
    LINX_(__NR_mq_unlink,         sys_mq_unlink),      // 241 
    LINX_(__NR_mq_timedsend,      sys_mq_timedsend),   // 242 
    LINXY(__NR_mq_open,           sys_mq_open),        // 240 
    LINX_(__NR_mq_unlink,         sys_mq_unlink),      // 241 
    LINX_(__NR_mq_timedsend,      sys_mq_timedsend),   // 242 

-   LINX_(__NR_mq_timedreceive,   sys_mq_timedreceive),// 243 
+   LINXY(__NR_mq_timedreceive,   sys_mq_timedreceive),// 243 

    LINX_(__NR_mq_notify,         sys_mq_notify),      // 244
 
    LINXY(__NR_mq_getsetattr,     sys_mq_getsetattr),  // 245 
    LINX_(__NR_mq_notify,         sys_mq_notify),      // 244
 
    LINXY(__NR_mq_getsetattr,     sys_mq_getsetattr),  // 245 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-arm-linux.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-arm-linux.c
index d550469c04f1f0ae6072b883d1919a5a9385dbdc..875f9680be6519b7593151566e994fb2c6218e2b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-arm-linux.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-arm-linux.c
@@ -1657,10 +1657,13 @@ static SyscallTableEntry syscall_main_table[] = {
    // correspond to what's in include/vki/vki-scnums-arm-linux.h.
    // From here onwards, please ensure the numbers are correct.
 
    // correspond to what's in include/vki/vki-scnums-arm-linux.h.
    // From here onwards, please ensure the numbers are correct.
 

+   LINX_(__NR_pselect6,                 sys_pselect6),         // 335
+

    LINXY(__NR_signalfd4,         sys_signalfd4),        // 355
    LINX_(__NR_eventfd2,          sys_eventfd2),         // 356
 
    LINXY(__NR_signalfd4,         sys_signalfd4),        // 355
    LINX_(__NR_eventfd2,          sys_eventfd2),         // 356
 

-   LINXY(__NR_pipe2,             sys_pipe2)             // 359
+   LINXY(__NR_pipe2,             sys_pipe2),            // 359
+   LINXY(__NR_inotify_init1,     sys_inotify_init1)     // 360

 };
 
 
 };
 
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-darwin.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-darwin.c
index edb4c881337f7b50a91379176ba85916ca497bfc..d2c46d83c81201da8d5bef57cbe55446d92bc8fc 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-darwin.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-darwin.c
@@ -66,7 +66,6 @@
 #include <mach/mach.h>
 #include <mach/mach_vm.h>
 #include <semaphore.h>
 #include <mach/mach.h>
 #include <mach/mach_vm.h>
 #include <semaphore.h>

-#include <sys/acl.h>   /* struct kauth_filesec */

 /* --- !!! --- EXTERNAL HEADERS end --- !!! --- */
 
 #define msgh_request_port      msgh_remote_port
 /* --- !!! --- EXTERNAL HEADERS end --- !!! --- */
 
 #define msgh_request_port      msgh_remote_port


@@ -1240,7 +1239,9 @@ PRE(futimes)
 {
    PRINT("futimes ( %ld, %#lx )", ARG1,ARG2);
    PRE_REG_READ2(long, "futimes", int, fd, struct timeval *, tvp);
 {
    PRINT("futimes ( %ld, %#lx )", ARG1,ARG2);
    PRE_REG_READ2(long, "futimes", int, fd, struct timeval *, tvp);

-   if (ARG2 != 0) {
+   if (!ML_(fd_allowed)(ARG1, "futimes", tid, False)) {
+      SET_STATUS_Failure( VKI_EBADF );
+   } else if (ARG2 != 0) {

       PRE_timeval_READ( "futimes(tvp[0])", ARG2 );
       PRE_timeval_READ( "futimes(tvp[1])", ARG2+sizeof(struct vki_timeval) );
    }
       PRE_timeval_READ( "futimes(tvp[0])", ARG2 );
       PRE_timeval_READ( "futimes(tvp[1])", ARG2+sizeof(struct vki_timeval) );
    }


@@ -1635,10 +1636,12 @@ PRE(kdebug_trace)
 {
    PRINT("kdebug_trace(%ld, %ld, %ld, %ld, %ld, %ld)", 
          ARG1, ARG2, ARG3, ARG4, ARG5, ARG6);
 {
    PRINT("kdebug_trace(%ld, %ld, %ld, %ld, %ld, %ld)", 
          ARG1, ARG2, ARG3, ARG4, ARG5, ARG6);

+   /*
+     Don't check anything - some clients pass fewer arguments.

    PRE_REG_READ6(long, "kdebug_trace", 
                  int,"code", int,"arg1", int,"arg2", 
                  int,"arg3", int,"arg4", int,"arg5");
    PRE_REG_READ6(long, "kdebug_trace", 
                  int,"code", int,"arg1", int,"arg2", 
                  int,"arg3", int,"arg4", int,"arg5");

-   // GrP fixme anything else?
+   */

 }
 
 
 }
 
 


@@ -2018,7 +2021,7 @@ PRE(fchmod_extended)
       is just way wrong.  [The trouble is with the size, which depends on a
       non-trival kernel computation] */
    PRE_MEM_READ( "fchmod_extended(xsecurity)", ARG5, 
       is just way wrong.  [The trouble is with the size, which depends on a
       non-trival kernel computation] */
    PRE_MEM_READ( "fchmod_extended(xsecurity)", ARG5, 

-                 sizeof(struct kauth_filesec) );
+                 sizeof(struct vki_kauth_filesec) );

 }
 
 PRE(chmod_extended)
 }
 
 PRE(chmod_extended)


@@ -2038,7 +2041,7 @@ PRE(chmod_extended)
       is just way wrong.  [The trouble is with the size, which depends on a
       non-trival kernel computation] */
    PRE_MEM_READ( "chmod_extended(xsecurity)", ARG5, 
       is just way wrong.  [The trouble is with the size, which depends on a
       non-trival kernel computation] */
    PRE_MEM_READ( "chmod_extended(xsecurity)", ARG5, 

-                 sizeof(struct kauth_filesec) );
+                 sizeof(struct vki_kauth_filesec) );

 }
 
 
 }
 
 


@@ -2241,6 +2244,9 @@ static void scan_attrlist(ThreadId tid, struct vki_attrlist *attrList,
    } attrspec;
    static const attrspec commonattr[] = {
       // This order is important.
    } attrspec;
    static const attrspec commonattr[] = {
       // This order is important.

+#if DARWIN_VERS >= DARWIN_10_6
+      { ATTR_CMN_RETURNED_ATTRS,  sizeof(attribute_set_t) }, 
+#endif

       { ATTR_CMN_NAME,            -1 }, 
       { ATTR_CMN_DEVID,           sizeof(dev_t) }, 
       { ATTR_CMN_FSID,            sizeof(fsid_t) }, 
       { ATTR_CMN_NAME,            -1 }, 
       { ATTR_CMN_DEVID,           sizeof(dev_t) }, 
       { ATTR_CMN_FSID,            sizeof(fsid_t) }, 


@@ -2263,8 +2269,14 @@ static void scan_attrlist(ThreadId tid, struct vki_attrlist *attrList,
       { ATTR_CMN_NAMEDATTRLIST,   -1 }, 
       { ATTR_CMN_FLAGS,           sizeof(uint32_t) }, 
       { ATTR_CMN_USERACCESS,      sizeof(uint32_t) }, 
       { ATTR_CMN_NAMEDATTRLIST,   -1 }, 
       { ATTR_CMN_FLAGS,           sizeof(uint32_t) }, 
       { ATTR_CMN_USERACCESS,      sizeof(uint32_t) }, 

+      { ATTR_CMN_EXTENDED_SECURITY, -1 }, 
+      { ATTR_CMN_UUID,            sizeof(guid_t) }, 
+      { ATTR_CMN_GRPUUID,         sizeof(guid_t) }, 

       { ATTR_CMN_FILEID,          sizeof(uint64_t) }, 
       { ATTR_CMN_PARENTID,        sizeof(uint64_t) }, 
       { ATTR_CMN_FILEID,          sizeof(uint64_t) }, 
       { ATTR_CMN_PARENTID,        sizeof(uint64_t) }, 

+#if DARWIN_VERS >= DARWIN_10_6
+      { ATTR_CMN_FULLPATH,        -1 }, 
+#endif

       { 0,                        0 }
    };
    static const attrspec volattr[] = {
       { 0,                        0 }
    };
    static const attrspec volattr[] = {


@@ -2288,6 +2300,9 @@ static void scan_attrlist(ThreadId tid, struct vki_attrlist *attrList,
       { ATTR_VOL_MOUNTEDDEVICE,   -1 }, 
       { ATTR_VOL_ENCODINGSUSED,   sizeof(uint64_t) }, 
       { ATTR_VOL_CAPABILITIES,    sizeof(vol_capabilities_attr_t) }, 
       { ATTR_VOL_MOUNTEDDEVICE,   -1 }, 
       { ATTR_VOL_ENCODINGSUSED,   sizeof(uint64_t) }, 
       { ATTR_VOL_CAPABILITIES,    sizeof(vol_capabilities_attr_t) }, 

+#if DARWIN_VERS >= DARWIN_10_6
+      { ATTR_VOL_UUID,            sizeof(uuid_t) }, 
+#endif

       { ATTR_VOL_ATTRIBUTES,      sizeof(vol_attributes_attr_t) }, 
       { 0,                        0 }
    };
       { ATTR_VOL_ATTRIBUTES,      sizeof(vol_attributes_attr_t) }, 
       { 0,                        0 }
    };


@@ -2336,6 +2351,16 @@ static void scan_attrlist(ThreadId tid, struct vki_attrlist *attrList,
    d = attrBuf;
    dend = d + attrBufSize;
 
    d = attrBuf;
    dend = d + attrBufSize;
 

+#if DARWIN_VERS >= DARWIN_10_6
+   // ATTR_CMN_RETURNED_ATTRS tells us what's really here, if set
+   if (a[0] & ATTR_CMN_RETURNED_ATTRS) {
+       // fixme range check this?
+       a[0] &= ~ATTR_CMN_RETURNED_ATTRS;
+       fn(tid, d, sizeof(attribute_set_t));
+       VG_(memcpy)(a, d, sizeof(a));
+   }
+#endif
+

    for (g = 0; g < 5; g++) {
       for (i = 0; attrdefs[g][i].attrBit; i++) {
          uint32_t bit = attrdefs[g][i].attrBit;
    for (g = 0; g < 5; g++) {
       for (i = 0; attrdefs[g][i].attrBit; i++) {
          uint32_t bit = attrdefs[g][i].attrBit;


@@ -2398,10 +2423,15 @@ PRE(getattrlist)
 POST(getattrlist) 
 {
    if (ARG4 > sizeof(vki_uint32_t)) {
 POST(getattrlist) 
 {
    if (ARG4 > sizeof(vki_uint32_t)) {

-      // attrBuf is uint32_t bytes written followed by attr data
+      // attrBuf is uint32_t size followed by attr data

       vki_uint32_t *sizep = (vki_uint32_t *)ARG3;
       POST_MEM_WRITE(ARG3, sizeof(vki_uint32_t));
       vki_uint32_t *sizep = (vki_uint32_t *)ARG3;
       POST_MEM_WRITE(ARG3, sizeof(vki_uint32_t));

-      scan_attrlist(tid, (struct vki_attrlist *)ARG2, sizep+1, *sizep, &get1attr);
+      if (ARG5 & FSOPT_REPORT_FULLSIZE) {
+         // *sizep is bytes required for return value, including *sizep
+      } else {
+         // *sizep is actual bytes returned, including *sizep
+      }
+      scan_attrlist(tid, (struct vki_attrlist *)ARG2, sizep+1, MIN(*sizep, ARG4), &get1attr);

    }
 }
 
    }
 }
 


@@ -2457,9 +2487,50 @@ POST(getdirentriesattr)
 
    POST_MEM_WRITE(ARG3, p - (char *)ARG3);
 
 
    POST_MEM_WRITE(ARG3, p - (char *)ARG3);
 

-   PRINT("got %d records, %d/%lu bytes\n", count, p-(char *)ARG3, ARG4);
+   PRINT("got %d records, %ld/%lu bytes\n",
+         count, (Addr)p-(Addr)ARG3, ARG4);
+}
+
+
+PRE(fsgetpath)
+{
+#if VG_WORDSIZE == 4
+   PRINT("fsgetpath(%#lx, %ld, %#lx {%u,%u}, %llu)", 
+         ARG1, ARG2, ARG3,
+         ((unsigned int *)ARG3)[0], ((unsigned int *)ARG3)[1],
+         LOHI64(ARG4, ARG5));
+   PRE_REG_READ5(ssize_t, "fsgetpath", 
+                 void*,"buf", size_t,"bufsize", 
+                 fsid_t *,"fsid",
+                 vki_uint32_t, "objid_low32", vki_uint32_t, "objid_high32");
+#else
+   PRINT("fsgetpath(%#lx, %ld, %#lx {%u,%u}, %lu)", 
+         ARG1, ARG2, ARG3,
+         ((unsigned int *)ARG3)[0],
+         ((unsigned int *)ARG3)[1], ARG4);
+   PRE_REG_READ4(ssize_t, "fsgetpath", 
+                 void*,"buf", size_t,"bufsize", 
+                 fsid_t *,"fsid", uint64_t,"objid");
+#endif
+   PRE_MEM_READ("fsgetpath(fsid)", ARG3, sizeof(fsid_t));
+   PRE_MEM_WRITE("fsgetpath(buf)", ARG1, ARG2);
+}
+
+POST(fsgetpath)
+{
+   POST_MEM_WRITE(ARG1, RES);

 }
 
 }
 

+PRE(audit_session_self)
+{
+  PRINT("audit_session_self()");
+}
+
+POST(audit_session_self)
+{
+  record_named_port(tid, RES, MACH_PORT_RIGHT_SEND, "audit-session-%p");
+  PRINT("audit-session %#lx", RES);
+}

 
 PRE(exchangedata)
 {
 
 PRE(exchangedata)
 {


@@ -3248,6 +3319,9 @@ PRE(auditon)
    case VKI_A_SETCLASS:
    case VKI_A_SETPMASK:
    case VKI_A_SETFSIZE:
    case VKI_A_SETCLASS:
    case VKI_A_SETPMASK:
    case VKI_A_SETFSIZE:

+#if DARWIN_VERS >= DARWIN_10_6
+   case VKI_A_SENDTRIGGER:
+#endif

       // kernel reads data..data+length
       PRE_MEM_READ("auditon(data)", ARG2, ARG3);
       break;
       // kernel reads data..data+length
       PRE_MEM_READ("auditon(data)", ARG2, ARG3);
       break;


@@ -3266,6 +3340,9 @@ PRE(auditon)
    case VKI_A_GETCLASS:
    case VKI_A_GETPINFO:
    case VKI_A_GETPINFO_ADDR:
    case VKI_A_GETCLASS:
    case VKI_A_GETPINFO:
    case VKI_A_GETPINFO_ADDR:

+#if DARWIN_VERS >= DARWIN_10_6
+   case VKI_A_GETSINFO_ADDR:
+#endif

       // kernel reads and writes data..data+length
       // GrP fixme be precise about what gets read and written
       PRE_MEM_READ("auditon(data)", ARG2, ARG3);
       // kernel reads and writes data..data+length
       // GrP fixme be precise about what gets read and written
       PRE_MEM_READ("auditon(data)", ARG2, ARG3);


@@ -3299,6 +3376,9 @@ POST(auditon)
    case VKI_A_SETCLASS:
    case VKI_A_SETPMASK:
    case VKI_A_SETFSIZE:
    case VKI_A_SETCLASS:
    case VKI_A_SETPMASK:
    case VKI_A_SETFSIZE:

+#if DARWIN_VERS >= DARWIN_10_6
+   case VKI_A_SENDTRIGGER:
+#endif

       // kernel reads data..data+length
       break;
 
       // kernel reads data..data+length
       break;
 


@@ -3316,6 +3396,9 @@ POST(auditon)
    case VKI_A_GETCLASS:
    case VKI_A_GETPINFO:
    case VKI_A_GETPINFO_ADDR:
    case VKI_A_GETCLASS:
    case VKI_A_GETPINFO:
    case VKI_A_GETPINFO_ADDR:

+#if DARWIN_VERS >= DARWIN_10_6
+   case VKI_A_GETSINFO_ADDR:
+#endif

       // kernel reads and writes data..data+length
       // GrP fixme be precise about what gets read and written
       POST_MEM_WRITE(ARG2, ARG3);
       // kernel reads and writes data..data+length
       // GrP fixme be precise about what gets read and written
       POST_MEM_WRITE(ARG2, ARG3);


@@ -3538,6 +3621,57 @@ PRE(sigsuspend)
    PRE_REG_READ1(int, "sigsuspend", int, sigmask);
 }
 
    PRE_REG_READ1(int, "sigsuspend", int, sigmask);
 }
 

+
+/* Be careful about the 4th arg, since that is a uint64_t.  Hence 64-
+   and 32-bit wrappers are different.
+
+   ARG5 and ARG6 (buffer, buffersize) specify a buffer start and
+   length in the usual way.  I have seen values NULL, 0 passed in some
+   cases.  I left the calls to PRE_MEM_WRITE/READ unconditional on the
+   basis that they don't do anything if the length is zero, so it's OK
+   for the buffer pointer to be NULL in that case (meaning they don't
+   complain).
+
+   int proc_info(int32_t callnum, int32_t pid,
+                 uint32_t flavor, uint64_t arg,
+                 user_addr_t buffer, int32_t buffersize)
+*/
+#if DARWIN_VERS >= DARWIN_10_6
+PRE(proc_info)
+{
+#if VG_WORDSIZE == 4
+   PRINT("proc_info(%d, %d, %u, %llu, %#lx, %d)",
+         (Int)ARG1, (Int)ARG2, (UInt)ARG3, LOHI64(ARG4,ARG5), ARG6, (Int)ARG7);
+   PRE_REG_READ7(int, "proc_info",
+                 int, callnum, int, pid, unsigned int, flavor,
+                 vki_uint32_t, arg_low32,
+                 vki_uint32_t, arg_high32,
+                 void*, buffer, int, buffersize);
+   PRE_MEM_WRITE("proc_info(buffer)", ARG6, ARG7);
+#else
+   PRINT("proc_info(%d, %d, %u, %llu, %#lx, %d)",
+         (Int)ARG1, (Int)ARG2, (UInt)ARG3, (ULong)ARG4, ARG5, (Int)ARG6);
+   PRE_REG_READ6(int, "proc_info",
+                 int, callnum, int, pid, unsigned int, flavor,
+                 unsigned long long int, arg,
+                 void*, buffer, int, buffersize);
+   PRE_MEM_WRITE("proc_info(buffer)", ARG5, ARG6);
+#endif
+}
+
+POST(proc_info)
+{
+#if VG_WORDSIZE == 4
+   vg_assert(SUCCESS);
+   POST_MEM_WRITE(ARG6, ARG7);
+#else
+   vg_assert(SUCCESS);
+   POST_MEM_WRITE(ARG5, ARG6);
+#endif
+}
+
+#endif /* DARWIN_VERS >= DARWIN_10_6 */
+

 /* ---------------------------------------------------------------------
    aio_*
    ------------------------------------------------------------------ */
 /* ---------------------------------------------------------------------
    aio_*
    ------------------------------------------------------------------ */


@@ -3959,7 +4093,7 @@ POST(host_page_size)
    Reply *reply = (Reply *)ARG1;
 
    if (!reply->RetCode) {
    Reply *reply = (Reply *)ARG1;
 
    if (!reply->RetCode) {

-      PRINT("page size %u", reply->out_page_size);
+     PRINT("page size %llu", (ULong)reply->out_page_size);

    } else {
       PRINT("mig return %d", reply->RetCode);
    }
    } else {
       PRINT("mig return %d", reply->RetCode);
    }


@@ -4384,6 +4518,51 @@ POST(mach_port_get_set_status)
 }
 
 
 }
 
 

+PRE(mach_port_move_member)
+{
+#pragma pack(4)
+    typedef struct {
+        mach_msg_header_t Head;
+        NDR_record_t NDR;
+        mach_port_name_t member;
+        mach_port_name_t after;
+    } Request;
+#pragma pack()
+
+    Request *req = (Request *)ARG1;
+
+    PRINT("mach_port_move_member(%s, %s, %s)", 
+          name_for_port(MACH_REMOTE), 
+          name_for_port(req->member), 
+          name_for_port(req->after));
+    /*
+    MACH_ARG(mach_port_move_member.member) = req->member;
+    MACH_ARG(mach_port_move_member.after) = req->after;
+    */
+    AFTER = POST_FN(mach_port_move_member);
+}
+
+POST(mach_port_move_member)
+{
+#pragma pack(4)
+   typedef struct {
+      mach_msg_header_t Head;
+      NDR_record_t NDR;
+      kern_return_t RetCode;
+      mach_msg_trailer_t trailer;
+   } Reply;
+#pragma pack()
+
+   Reply *reply = (Reply *)ARG1;
+
+   if (!reply->RetCode) {
+      // fixme port set tracker?
+   } else {
+      PRINT("mig return %d", reply->RetCode);
+   }
+}
+
+

 PRE(mach_port_destroy)
 {
 #pragma pack(4)
 PRE(mach_port_destroy)
 {
 #pragma pack(4)


@@ -4504,6 +4683,34 @@ POST(mach_port_insert_right)
 }
 
 
 }
 
 

+PRE(mach_port_extract_right)
+{
+#pragma pack(4)
+   typedef struct {
+      mach_msg_header_t Head;
+      NDR_record_t NDR;
+      mach_port_name_t name;
+      mach_msg_type_name_t msgt_name;
+   } Request;
+#pragma pack()
+
+   Request *req = (Request *)ARG1;
+   
+   PRINT("mach_port_extract_right(%s, %s, %d)", 
+         name_for_port(MACH_REMOTE), 
+         name_for_port(req->name), req->msgt_name);
+   
+   AFTER = POST_FN(mach_port_extract_right);
+   
+   // fixme port tracker?
+}
+
+POST(mach_port_extract_right)
+{
+   // fixme import_complex_message handles the returned result, right?
+}
+
+

 PRE(mach_port_get_attributes)
 {
 #pragma pack(4)
 PRE(mach_port_get_attributes)
 {
 #pragma pack(4)


@@ -4875,9 +5082,9 @@ PRE(vm_allocate)
 
    Request *req = (Request *)ARG1;
 
 
    Request *req = (Request *)ARG1;
 

-   PRINT("vm_allocate (%s, at %#x, size %d, flags %#x)", 
+   PRINT("vm_allocate (%s, at %#llx, size %lld, flags %#x)", 

          name_for_port(MACH_REMOTE), 
          name_for_port(MACH_REMOTE), 

-         req->address, req->size, req->flags);
+         (ULong)req->address, (ULong)req->size, req->flags);

 
    MACH_ARG(vm_allocate.size) = req->size;
    MACH_ARG(vm_allocate.flags) = req->flags;
 
    MACH_ARG(vm_allocate.size) = req->size;
    MACH_ARG(vm_allocate.flags) = req->flags;


@@ -4901,7 +5108,7 @@ POST(vm_allocate)
    
    if (!reply->RetCode) {
       if (MACH_REMOTE == vg_task_port) {
    
    if (!reply->RetCode) {
       if (MACH_REMOTE == vg_task_port) {

-         PRINT("allocated at %#x", reply->address);
+        PRINT("allocated at %#llx", (ULong)reply->address);

          // requesting 0 bytes returns address 0 with no error
          if (MACH_ARG(vm_allocate.size)) {
             ML_(notify_core_and_tool_of_mmap)(
          // requesting 0 bytes returns address 0 with no error
          if (MACH_ARG(vm_allocate.size)) {
             ML_(notify_core_and_tool_of_mmap)(


@@ -4909,7 +5116,8 @@ POST(vm_allocate)
                   VKI_PROT_READ|VKI_PROT_WRITE, VKI_MAP_ANON, -1, 0);
          }
       } else {
                   VKI_PROT_READ|VKI_PROT_WRITE, VKI_MAP_ANON, -1, 0);
          }
       } else {

-         PRINT("allocated at %#x in remote task %s", reply->address, 
+         PRINT("allocated at %#llx in remote task %s",
+               (ULong)reply->address, 

                name_for_port(MACH_REMOTE));
       }
    } else {
                name_for_port(MACH_REMOTE));
       }
    } else {


@@ -4931,9 +5139,9 @@ PRE(vm_deallocate)
    
    Request *req = (Request *)ARG1;
    
    
    Request *req = (Request *)ARG1;
    

-   PRINT("vm_deallocate(%s, at %#x, size %d)", 
+   PRINT("vm_deallocate(%s, at %#llx, size %lld)", 

          name_for_port(MACH_REMOTE), 
          name_for_port(MACH_REMOTE), 

-         req->address, req->size);
+         (ULong)req->address, (ULong)req->size);

    
    MACH_ARG(vm_deallocate.address) = req->address;
    MACH_ARG(vm_deallocate.size) = req->size;
    
    MACH_ARG(vm_deallocate.address) = req->address;
    MACH_ARG(vm_deallocate.size) = req->size;


@@ -4989,8 +5197,9 @@ PRE(vm_protect)
    
    Request *req = (Request *)ARG1;
    
    
    Request *req = (Request *)ARG1;
    

-   PRINT("vm_protect(%s, at %#x, size %d, set_max %d, prot %d)", 
-         name_for_port(MACH_REMOTE), req->address, req->size, 
+   PRINT("vm_protect(%s, at %#llx, size %lld, set_max %d, prot %d)", 
+         name_for_port(MACH_REMOTE),
+         (ULong)req->address, (ULong)req->size, 

          req->set_maximum, req->new_protection);
    
    MACH_ARG(vm_protect.address) = req->address;
          req->set_maximum, req->new_protection);
    
    MACH_ARG(vm_protect.address) = req->address;


@@ -5048,9 +5257,9 @@ PRE(vm_inherit)
    
    Request *req = (Request *)ARG1;
    
    
    Request *req = (Request *)ARG1;
    

-   PRINT("vm_inherit(%s, at %#x, size %d, value %d)", 
+   PRINT("vm_inherit(%s, at %#llx, size %lld, value %d)", 

          name_for_port(MACH_REMOTE), 
          name_for_port(MACH_REMOTE), 

-         req->address, req->size, 
+         (ULong)req->address, (ULong)req->size, 

          req->new_inheritance);
    
    AFTER = POST_FN(vm_inherit);
          req->new_inheritance);
    
    AFTER = POST_FN(vm_inherit);


@@ -5092,8 +5301,9 @@ PRE(vm_read)
 
    Request *req = (Request *)ARG1;
 
 
    Request *req = (Request *)ARG1;
 

-   PRINT("vm_read(from %s at %#x size %u)", 
-         name_for_port(MACH_REMOTE), req->address, req->size);
+   PRINT("vm_read(from %s at %#llx size %llu)", 
+         name_for_port(MACH_REMOTE),
+         (ULong)req->address, (ULong)req->size);

    
    MACH_ARG(vm_read.addr) = req->address;
    MACH_ARG(vm_read.size) = req->size;
    
    MACH_ARG(vm_read.addr) = req->address;
    MACH_ARG(vm_read.size) = req->size;


@@ -5184,8 +5394,9 @@ PRE(vm_read_overwrite)
 
    Request *req = (Request *)ARG1;
 
 
    Request *req = (Request *)ARG1;
 

-   PRINT("vm_read_overwrite(from %s at %#x size %u to %#x)", 
-         name_for_port(MACH_REMOTE), req->address, req->size, req->data);
+   PRINT("vm_read_overwrite(from %s at %#llx size %llu to %#llx)", 
+         name_for_port(MACH_REMOTE),
+         (ULong)req->address, (ULong)req->size, (ULong)req->data);

    
    MACH_ARG(vm_read_overwrite.addr) = req->address;
    MACH_ARG(vm_read_overwrite.size) = req->size;
    
    MACH_ARG(vm_read_overwrite.addr) = req->address;
    MACH_ARG(vm_read_overwrite.size) = req->size;


@@ -5239,9 +5450,10 @@ PRE(vm_copy)
    
    Request *req = (Request *)ARG1;
    
    
    Request *req = (Request *)ARG1;
    

-   PRINT("vm_copy(%s, %#x, %d, %#x)", 
+   PRINT("vm_copy(%s, %#llx, %lld, %#llx)", 

          name_for_port(MACH_REMOTE), 
          name_for_port(MACH_REMOTE), 

-         req->source_address, req->size, req->dest_address);
+         (ULong)req->source_address,
+         (ULong)req->size, (ULong)req->dest_address);

 
    MACH_ARG(vm_copy.src) = req->source_address;
    MACH_ARG(vm_copy.dst) = req->dest_address;
 
    MACH_ARG(vm_copy.src) = req->source_address;
    MACH_ARG(vm_copy.dst) = req->dest_address;


@@ -5299,9 +5511,9 @@ PRE(vm_map)
    Request *req = (Request *)ARG1;
 
    // GrP fixme check these
    Request *req = (Request *)ARG1;
 
    // GrP fixme check these

-   PRINT("vm_map(in %s, at %#x, size %d, from %s ...)", 
+   PRINT("vm_map(in %s, at %#llx, size %lld, from %s ...)", 

          name_for_port(MACH_REMOTE), 
          name_for_port(MACH_REMOTE), 

-         req->address, req->size, 
+         (ULong)req->address, (ULong)req->size, 

          name_for_port(req->object.name));
 
    MACH_ARG(vm_map.size) = req->size;
          name_for_port(req->object.name));
 
    MACH_ARG(vm_map.size) = req->size;


@@ -5327,7 +5539,7 @@ POST(vm_map)
 
    if (!reply->RetCode) {
       // GrP fixme check src and dest tasks
 
    if (!reply->RetCode) {
       // GrP fixme check src and dest tasks

-      PRINT("mapped at %#x", reply->address);
+     PRINT("mapped at %#llx", (ULong)reply->address);

       // GrP fixme max prot
       ML_(notify_core_and_tool_of_mmap)(
             reply->address, VG_PGROUNDUP(MACH_ARG(vm_map.size)), 
       // GrP fixme max prot
       ML_(notify_core_and_tool_of_mmap)(
             reply->address, VG_PGROUNDUP(MACH_ARG(vm_map.size)), 


@@ -5367,13 +5579,14 @@ PRE(vm_remap)
       mach_port_name_t source_task = req->src_task.name;
       if (source_task == mach_task_self()) {
          PRINT("vm_remap(mach_task_self(), "
       mach_port_name_t source_task = req->src_task.name;
       if (source_task == mach_task_self()) {
          PRINT("vm_remap(mach_task_self(), "

-               "to %#x size %d, from mach_task_self() at %#x, ...)",
-               req->target_address, req->size, req->src_address);
+               "to %#llx size %lld, from mach_task_self() at %#llx, ...)",
+               (ULong)req->target_address,
+               (ULong)req->size, (ULong)req->src_address);

       } else {
       } else {

-          PRINT("vm_remap(mach_task_self(), "
-                "to %#x size %d, from task %u at %#x, ...)",
-                req->target_address, req->size, 
-                source_task,  req->src_address);
+         PRINT("vm_remap(mach_task_self(), "
+               "to %#llx size %lld, from task %u at %#llx, ...)",
+               (ULong)req->target_address, (ULong)req->size, 
+               source_task, (ULong)req->src_address);

       }
    }
 
       }
    }
 


@@ -5405,7 +5618,7 @@ POST(vm_remap)
       // GrP fixme check src and dest tasks
       UInt prot = reply->cur_protection & reply->max_protection;
       // GrP fixme max prot
       // GrP fixme check src and dest tasks
       UInt prot = reply->cur_protection & reply->max_protection;
       // GrP fixme max prot

-      PRINT("mapped at %#x", reply->target_address);
+      PRINT("mapped at %#llx", (ULong)reply->target_address);

       ML_(notify_core_and_tool_of_mmap)(
             reply->target_address, VG_PGROUNDUP(MACH_ARG(vm_remap.size)), 
             prot, VKI_MAP_SHARED, -1, 0);
       ML_(notify_core_and_tool_of_mmap)(
             reply->target_address, VG_PGROUNDUP(MACH_ARG(vm_remap.size)), 
             prot, VKI_MAP_SHARED, -1, 0);


@@ -5477,9 +5690,9 @@ PRE(vm_purgable_control)
 
    Request *req = (Request *)ARG1;
 
 
    Request *req = (Request *)ARG1;
 

-   PRINT("vm_purgable_control(%s, %#x, %d, %d)", 
+   PRINT("vm_purgable_control(%s, %#llx, %d, %d)", 

          name_for_port(MACH_REMOTE), 
          name_for_port(MACH_REMOTE), 

-         req->address, req->control, req->state);
+         (ULong)req->address, req->control, req->state);

 
    // GrP fixme verify address?
 
 
    // GrP fixme verify address?
 


@@ -6092,6 +6305,7 @@ POST(bsdthread_create)
 
    // GrP fixme semaphore destroy needed when thread creation fails
    // GrP fixme probably other cleanup too
 
    // GrP fixme semaphore destroy needed when thread creation fails
    // GrP fixme probably other cleanup too

+   // GrP fixme spinlocks might be good enough?

 
    // DDD: I'm not at all sure this is the right spot for this.  It probably
    // should be in pthread_hijack instead, just before the call to
 
    // DDD: I'm not at all sure this is the right spot for this.  It probably
    // should be in pthread_hijack instead, just before the call to


@@ -6210,10 +6424,6 @@ PRE(thread_get_state)
 }
 
 
 }
 
 

-POST(thread_policy)
-{
-}
-

 PRE(thread_policy)
 {
    mach_msg_header_t *mh = (mach_msg_header_t *)ARG1;
 PRE(thread_policy)
 {
    mach_msg_header_t *mh = (mach_msg_header_t *)ARG1;


@@ -6228,6 +6438,24 @@ PRE(thread_policy)
    AFTER = POST_FN(thread_policy);
 }
 
    AFTER = POST_FN(thread_policy);
 }
 

+POST(thread_policy)
+{
+}
+
+
+PRE(thread_policy_set)
+{
+   mach_msg_header_t *mh = (mach_msg_header_t *)ARG1;
+
+   PRINT("thread_policy_set(%s, ...)", name_for_port(mh->msgh_request_port));
+
+   AFTER = POST_FN(thread_policy_set);
+}
+
+POST(thread_policy_set)
+{
+}
+

 
 PRE(thread_info)
 {
 
 PRE(thread_info)
 {


@@ -6455,12 +6683,18 @@ PRE(mach_msg_task)
    case 3211:
       CALL_PRE(mach_port_get_set_status);
       return;
    case 3211:
       CALL_PRE(mach_port_get_set_status);
       return;

+   case 3212:
+      CALL_PRE(mach_port_move_member);
+      return;

    case 3213:
       CALL_PRE(mach_port_request_notification);
       return;
    case 3214:
       CALL_PRE(mach_port_insert_right);
       return;
    case 3213:
       CALL_PRE(mach_port_request_notification);
       return;
    case 3214:
       CALL_PRE(mach_port_insert_right);
       return;

+   case 3215:
+      CALL_PRE(mach_port_extract_right);
+      return;

    case 3217:
       CALL_PRE(mach_port_get_attributes);
       return;
    case 3217:
       CALL_PRE(mach_port_get_attributes);
       return;


@@ -6602,6 +6836,9 @@ PRE(mach_msg_thread)
    case 3616: 
       CALL_PRE(thread_policy);
       return;
    case 3616: 
       CALL_PRE(thread_policy);
       return;

+   case 3617: 
+      CALL_PRE(thread_policy_set);
+      return;

    default:
       // unknown message to a thread
       VG_(printf)("UNKNOWN thread message [id %d, to %s, reply 0x%x]\n", 
    default:
       // unknown message to a thread
       VG_(printf)("UNKNOWN thread message [id %d, to %s, reply 0x%x]\n", 


@@ -6766,7 +7003,7 @@ POST(mach_msg)
 
 POST(mach_msg_unhandled)
 {
 
 POST(mach_msg_unhandled)
 {

-   ML_(sync_mappings)("after", "mach_msg_unhandled", 0);
+   ML_(sync_mappings)("after", "mach_msg_receive (unhandled)", 0);

 }
 
 
 }
 
 


@@ -6908,9 +7145,9 @@ PRE(semaphore_timedwait_signal)
 
 PRE(__semwait_signal)
 {
 
 PRE(__semwait_signal)
 {

-   /* args: int cond_sem, int mutex_sem,
-            int timeout, int relative,
-            time_t tv_sec, time_t tv_nsec */
+   /* 10.5 args: int cond_sem, int mutex_sem,
+                 int timeout, int relative,
+                 time_t tv_sec, time_t tv_nsec */

    PRINT("__semwait_signal(wait %s, signal %s, %ld, %ld, %lds:%ldns)", 
          name_for_port(ARG1), name_for_port(ARG2), ARG3, ARG4, ARG5, ARG6);
    PRE_REG_READ6(long, "__semwait_signal", 
    PRINT("__semwait_signal(wait %s, signal %s, %ld, %ld, %lds:%ldns)", 
          name_for_port(ARG1), name_for_port(ARG2), ARG3, ARG4, ARG5, ARG6);
    PRE_REG_READ6(long, "__semwait_signal", 


@@ -6920,7 +7157,33 @@ PRE(__semwait_signal)
 
    *flags |= SfMayBlock;
 }
 
    *flags |= SfMayBlock;
 }

-
+// GrP provided this alternative version for 10.6, but NjN
+// reckons the 10.5 is is still correct for 10.6.  So, retaining
+// Greg's version as a comment just in case we need it later.
+//PRE(__semwait_signal)
+//{
+//   /* 10.5 args: int cond_sem, int mutex_sem,
+//                 int timeout, int relative,
+//                 const timespec *ts */
+//   PRINT("__semwait_signal(wait %s, signal %s, %ld, %ld, %#lx)", 
+//         name_for_port(ARG1), name_for_port(ARG2), ARG3, ARG4, ARG5);
+//   PRE_REG_READ5(int, "__semwait_signal", 
+//                 int,cond_sem, int,mutex_sem,
+//                 int,timeout, int,relative, 
+//                 const struct vki_timespec *,ts);
+//   
+//   if (ARG5) PRE_MEM_READ ("__semwait_signal(ts)", 
+//                           ARG5, sizeof(struct vki_timespec));
+//   
+//   *flags |= SfMayBlock;
+//}
+
+
+PRE(__thread_selfid)
+{
+   PRINT("__thread_selfid ()");
+   PRE_REG_READ0(vki_uint64_t, "__thread_selfid");
+}

 
 PRE(task_for_pid)
 {
 
 PRE(task_for_pid)
 {


@@ -6977,10 +7240,10 @@ POST(mach_timebase_info)
 PRE(mach_wait_until)
 {
 #if VG_WORDSIZE == 8
 PRE(mach_wait_until)
 {
 #if VG_WORDSIZE == 8

-   PRINT("mach_wait_until(%llu)", ARG1);
+   PRINT("mach_wait_until(%lu)", ARG1);

    PRE_REG_READ1(long, "mach_wait_until", 
                  unsigned long long,"deadline");
    PRE_REG_READ1(long, "mach_wait_until", 
                  unsigned long long,"deadline");

-#else   
+#else

    PRINT("mach_wait_until(%llu)", LOHI64(ARG1, ARG2));
    PRE_REG_READ2(long, "mach_wait_until", 
                  int,"deadline_hi", int,"deadline_lo");
    PRINT("mach_wait_until(%llu)", LOHI64(ARG1, ARG2));
    PRE_REG_READ2(long, "mach_wait_until", 
                  int,"deadline_hi", int,"deadline_lo");


@@ -7021,7 +7284,7 @@ POST(mk_timer_destroy)
 PRE(mk_timer_arm)
 {
 #if VG_WORDSIZE == 8
 PRE(mk_timer_arm)
 {
 #if VG_WORDSIZE == 8

-   PRINT("mk_timer_arm(%s, %llu)", name_for_port(ARG1), ARG2);
+   PRINT("mk_timer_arm(%s, %lu)", name_for_port(ARG1), ARG2);

    PRE_REG_READ2(long, "mk_timer_arm", mach_port_t,"name", 
                  unsigned long,"expire_time");
 #else
    PRE_REG_READ2(long, "mk_timer_arm", mach_port_t,"name", 
                  unsigned long,"expire_time");
 #else


@@ -7344,7 +7607,7 @@ const SyscallTableEntry ML_(syscall_table)[] = {
    MACXY(__NR_ioctl,       ioctl), 
 // _____(__NR_reboot), 
 // _____(__NR_revoke), 
    MACXY(__NR_ioctl,       ioctl), 
 // _____(__NR_reboot), 
 // _____(__NR_revoke), 

-// _____(__NR_symlink), 
+   GENX_(__NR_symlink,     sys_symlink),   // 57

    GENX_(__NR_readlink,    sys_readlink), 
    GENX_(__NR_execve,      sys_execve), 
    GENX_(__NR_umask,       sys_umask),     // 60
    GENX_(__NR_readlink,    sys_readlink), 
    GENX_(__NR_execve,      sys_execve), 
    GENX_(__NR_umask,       sys_umask),     // 60


@@ -7474,7 +7737,11 @@ const SyscallTableEntry ML_(syscall_table)[] = {
    MACX_(__NR_sigreturn,   sigreturn), 
 // _____(__NR_chud), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(186)),   // ??? 
    MACX_(__NR_sigreturn,   sigreturn), 
 // _____(__NR_chud), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(186)),   // ??? 

+#if DARWIN_VERS >= DARWIN_10_6
+// _____(__NR_fdatasync), 
+#else

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(187)),   // ??? 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(187)),   // ??? 

+#endif

    GENXY(__NR_stat,        sys_newstat), 
    GENXY(__NR_fstat,       sys_newfstat), 
    GENXY(__NR_lstat,       sys_newlstat), 
    GENXY(__NR_stat,        sys_newstat), 
    GENXY(__NR_fstat,       sys_newfstat), 
    GENXY(__NR_lstat,       sys_newlstat), 


@@ -7501,8 +7768,13 @@ const SyscallTableEntry ML_(syscall_table)[] = {
 // _____(__NR_ATPgetreq), 
 // _____(__NR_ATPgetrsp), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(213)),   // Reserved for AppleTalk
 // _____(__NR_ATPgetreq), 
 // _____(__NR_ATPgetrsp), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(213)),   // Reserved for AppleTalk

+#if DARWIN_VERS >= DARWIN_10_6
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(214)),   // old kqueue_from_portset_np
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(215)),   // old kqueue_portset_np
+#else

 // _____(__NR_kqueue_from_portset_np), 
 // _____(__NR_kqueue_portset_np), 
 // _____(__NR_kqueue_from_portset_np), 
 // _____(__NR_kqueue_portset_np), 

+#endif

 // _____(__NR_mkcomplex), 
 // _____(__NR_statv), 
 // _____(__NR_lstatv), 
 // _____(__NR_mkcomplex), 
 // _____(__NR_statv), 
 // _____(__NR_lstatv), 


@@ -7515,8 +7787,13 @@ const SyscallTableEntry ML_(syscall_table)[] = {
 // _____(__NR_searchfs), 
    GENX_(__NR_delete,      sys_unlink), 
 // _____(__NR_copyfile), 
 // _____(__NR_searchfs), 
    GENX_(__NR_delete,      sys_unlink), 
 // _____(__NR_copyfile), 

+#if DARWIN_VERS >= DARWIN_10_6
+// _____(__NR_fgetattrlist), 
+// _____(__NR_fsetattrlist), 
+#else

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(228)),   // ?? 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(229)),   // ?? 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(228)),   // ?? 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(229)),   // ?? 

+#endif

    GENXY(__NR_poll,        sys_poll), 
    MACX_(__NR_watchevent,  watchevent), 
    MACXY(__NR_waitevent,   waitevent), 
    GENXY(__NR_poll,        sys_poll), 
    MACX_(__NR_watchevent,  watchevent), 
    MACXY(__NR_waitevent,   waitevent), 


@@ -7532,7 +7809,11 @@ const SyscallTableEntry ML_(syscall_table)[] = {
    MACXY(__NR_fsctl,       fsctl), 
    MACX_(__NR_initgroups,  initgroups), 
    MACXY(__NR_posix_spawn, posix_spawn), 
    MACXY(__NR_fsctl,       fsctl), 
    MACX_(__NR_initgroups,  initgroups), 
    MACXY(__NR_posix_spawn, posix_spawn), 

+#if DARWIN_VERS >= DARWIN_10_6
+// _____(__NR_ffsctl), 
+#else

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(245)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(245)),   // ???

+#endif

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(246)),   // ???
 // _____(__NR_nfsclnt), 
 // _____(__NR_fhopen), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(246)),   // ???
 // _____(__NR_nfsclnt), 
 // _____(__NR_fhopen), 


@@ -7583,23 +7864,27 @@ const SyscallTableEntry ML_(syscall_table)[] = {
 // _____(__NR_identitysvc), 
 // _____(__NR_shared_region_check_np), 
 // _____(__NR_shared_region_map_np), 
 // _____(__NR_identitysvc), 
 // _____(__NR_shared_region_check_np), 
 // _____(__NR_shared_region_map_np), 

+#if DARWIN_VERS >= DARWIN_10_6
+// _____(__NR_vm_pressure_monitor), 
+#else

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(296)),   // old load_shared_file 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(296)),   // old load_shared_file 

+#endif

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(297)),   // old reset_shared_file 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(298)),   // old new_system_shared_regions 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(299)),   // old shared_region_map_file_np 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(300)),   // old shared_region_make_private_np
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(297)),   // old reset_shared_file 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(298)),   // old new_system_shared_regions 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(299)),   // old shared_region_map_file_np 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(300)),   // old shared_region_make_private_np

-// _____(__NR___pthread_mutex_destroy), 
-// _____(__NR___pthread_mutex_init), 
-// _____(__NR___pthread_mutex_lock), 
-// _____(__NR___pthread_mutex_trylock), 
-// _____(__NR___pthread_mutex_unlock), 
-// _____(__NR___pthread_cond_init), 
-// _____(__NR___pthread_cond_destroy), 
-// _____(__NR___pthread_cond_broadcast), 
-// _____(__NR___pthread_cond_signal), 
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(301)),   // ???
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(302)),   // ???
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(303)),   // ???
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(304)),   // ???
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(305)),   // ???
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(306)),   // ???
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(307)),   // ???
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(308)),   // ???
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(309)),   // ???

 // _____(__NR_getsid), 
 // _____(__NR_settid_with_pid), 
 // _____(__NR_getsid), 
 // _____(__NR_settid_with_pid), 

-// _____(__NR___pthread_cond_timedwait), 
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(312)),   // ???

 // _____(__NR_aio_fsync), 
    MACXY(__NR_aio_return,     aio_return), 
    MACX_(__NR_aio_suspend,    aio_suspend), 
 // _____(__NR_aio_fsync), 
    MACXY(__NR_aio_return,     aio_return), 
    MACX_(__NR_aio_suspend,    aio_suspend), 


@@ -7608,7 +7893,7 @@ const SyscallTableEntry ML_(syscall_table)[] = {
    MACXY(__NR_aio_read,       aio_read), 
    MACX_(__NR_aio_write,      aio_write), 
 // _____(__NR_lio_listio),   // 320
    MACXY(__NR_aio_read,       aio_read), 
    MACX_(__NR_aio_write,      aio_write), 
 // _____(__NR_lio_listio),   // 320

-// _____(__NR___pthread_cond_wait), 
+   _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(321)),   // ???

 // _____(__NR_iopolicysys), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(323)),   // ???
 // _____(__NR_mlockall), 
 // _____(__NR_iopolicysys), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(323)),   // ???
 // _____(__NR_mlockall), 


@@ -7623,7 +7908,9 @@ const SyscallTableEntry ML_(syscall_table)[] = {
    MACX_(__NR___pthread_canceled,      __pthread_canceled),
    MACX_(__NR___semwait_signal,        __semwait_signal), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(335)),   // old utrace
    MACX_(__NR___pthread_canceled,      __pthread_canceled),
    MACX_(__NR___semwait_signal,        __semwait_signal), 
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(335)),   // old utrace

-// _____(__NR_proc_info), 
+#if DARWIN_VERS >= DARWIN_10_6
+   MACXY(__NR_proc_info,               proc_info),  // 336
+#endif

    MACXY(__NR_sendfile,    sendfile), 
    MACXY(__NR_stat64,      stat64), 
    MACXY(__NR_fstat64,     fstat64), 
    MACXY(__NR_sendfile,    sendfile), 
    MACXY(__NR_stat64,      stat64), 
    MACXY(__NR_fstat64,     fstat64), 


@@ -7651,15 +7938,23 @@ const SyscallTableEntry ML_(syscall_table)[] = {
    MACX_(__NR_bsdthread_terminate,  bsdthread_terminate), 
    MACXY(__NR_kqueue,      kqueue), 
    MACXY(__NR_kevent,      kevent), 
    MACX_(__NR_bsdthread_terminate,  bsdthread_terminate), 
    MACXY(__NR_kqueue,      kqueue), 
    MACXY(__NR_kevent,      kevent), 

-// _____(__NR_lchown), 
+   GENX_(__NR_lchown,      sys_lchown), 

 // _____(__NR_stack_snapshot), 
    MACX_(__NR_bsdthread_register, bsdthread_register), 
    MACX_(__NR_workq_open,  workq_open), 
    MACXY(__NR_workq_ops,   workq_ops), 
 // _____(__NR_stack_snapshot), 
    MACX_(__NR_bsdthread_register, bsdthread_register), 
    MACX_(__NR_workq_open,  workq_open), 
    MACXY(__NR_workq_ops,   workq_ops), 

+#if DARWIN_VERS >= DARWIN_10_6
+// _____(__NR_kevent64), 
+#else

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(369)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(369)),   // ???

+#endif

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(370)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(371)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(370)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(371)),   // ???

+#if DARWIN_VERS >= DARWIN_10_6
+   MACX_(__NR___thread_selfid, __thread_selfid), 
+#else

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(372)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(372)),   // ???

+#endif

    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(373)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(374)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(375)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(373)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(374)),   // ???
    _____(VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(375)),   // ???


@@ -7715,6 +8010,12 @@ const SyscallTableEntry ML_(syscall_table)[] = {
 // _____(__NR___mac_mount),
 // _____(__NR___mac_get_mount),
 // _____(__NR___mac_getfsstat),
 // _____(__NR___mac_mount),
 // _____(__NR___mac_get_mount),
 // _____(__NR___mac_getfsstat),

+#if DARWIN_VERS >= DARWIN_10_6
+   MACXY(__NR_fsgetpath, fsgetpath), 
+   MACXY(__NR_audit_session_self, audit_session_self),
+// _____(__NR_audit_session_join),
+#endif
+

 // _____(__NR_MAXSYSCALL)
    MACX_(__NR_DARWIN_FAKE_SIGRETURN, FAKE_SIGRETURN)
 };
 // _____(__NR_MAXSYSCALL)
    MACX_(__NR_DARWIN_FAKE_SIGRETURN, FAKE_SIGRETURN)
 };

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-linux.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-linux.c
index d2cfbbda70cb4c80c45dc465f6b258be781f8072..c5fc108f216d4b7ba6279c90029c6442f81bc4f5 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-linux.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-linux.c
@@ -420,7 +420,8 @@ PRE(sys_mount)
    PRE_REG_READ5(long, "mount",
                  char *, source, char *, target, char *, type,
                  unsigned long, flags, void *, data);
    PRE_REG_READ5(long, "mount",
                  char *, source, char *, target, char *, type,
                  unsigned long, flags, void *, data);

-   PRE_MEM_RASCIIZ( "mount(source)", ARG1);
+   if (ARG1)
+      PRE_MEM_RASCIIZ( "mount(source)", ARG1);

    PRE_MEM_RASCIIZ( "mount(target)", ARG2);
    PRE_MEM_RASCIIZ( "mount(type)", ARG3);
 }
    PRE_MEM_RASCIIZ( "mount(target)", ARG2);
    PRE_MEM_RASCIIZ( "mount(type)", ARG3);
 }


@@ -1726,7 +1727,7 @@ PRE(sys_mq_timedreceive)
 }
 POST(sys_mq_timedreceive)
 {
 }
 POST(sys_mq_timedreceive)
 {

-   POST_MEM_WRITE( ARG2, ARG3 );
+   POST_MEM_WRITE( ARG2, RES );

    if (ARG4 != 0)
       POST_MEM_WRITE( ARG4, sizeof(unsigned int) );
 }
    if (ARG4 != 0)
       POST_MEM_WRITE( ARG4, sizeof(unsigned int) );
 }


@@ -4280,7 +4281,7 @@ PRE(sys_ioctl)
       PRE_MEM_WRITE( "ioctl(FIGETBSZ)", ARG3, sizeof(unsigned long));
       break;
    case VKI_FIBMAP:
       PRE_MEM_WRITE( "ioctl(FIGETBSZ)", ARG3, sizeof(unsigned long));
       break;
    case VKI_FIBMAP:

-      PRE_MEM_READ( "ioctl(FIBMAP)", ARG3, sizeof(unsigned long));
+      PRE_MEM_READ( "ioctl(FIBMAP)", ARG3, sizeof(int));

       break;
 
    case VKI_FBIOGET_VSCREENINFO: /* 0x4600 */
       break;
 
    case VKI_FBIOGET_VSCREENINFO: /* 0x4600 */


@@ -4842,8 +4843,7 @@ PRE(sys_ioctl)
       case VKI_EVIOCGBIT(VKI_EV_FF,0):
       case VKI_EVIOCGBIT(VKI_EV_PWR,0):
       case VKI_EVIOCGBIT(VKI_EV_FF_STATUS,0):
       case VKI_EVIOCGBIT(VKI_EV_FF,0):
       case VKI_EVIOCGBIT(VKI_EV_PWR,0):
       case VKI_EVIOCGBIT(VKI_EV_FF_STATUS,0):

-         if (RES > 0)
-            PRE_MEM_WRITE("ioctl(EVIO*)", ARG3, _VKI_IOC_SIZE(ARG2));
+         PRE_MEM_WRITE("ioctl(EVIO*)", ARG3, _VKI_IOC_SIZE(ARG2));

          break;
       default:
          ML_(PRE_unknown_ioctl)(tid, ARG2, ARG3);
          break;
       default:
          ML_(PRE_unknown_ioctl)(tid, ARG2, ARG3);


@@ -5244,7 +5244,7 @@ POST(sys_ioctl)
       POST_MEM_WRITE(ARG3, sizeof(unsigned long));
       break;
    case VKI_FIBMAP:
       POST_MEM_WRITE(ARG3, sizeof(unsigned long));
       break;
    case VKI_FIBMAP:

-      POST_MEM_WRITE(ARG3, sizeof(unsigned long));
+      POST_MEM_WRITE(ARG3, sizeof(int));

       break;
 
    case VKI_FBIOGET_VSCREENINFO: //0x4600
       break;
 
    case VKI_FBIOGET_VSCREENINFO: //0x4600

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-main.c
index e867ec6c78ad84fe39663e1c2b970021234997f1..922389a1a08e0cb5131edf643ac2de31d021bbfa 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-main.c
@@ -66,6 +66,7 @@
    amd64  rax rdi  rsi  rdx  r10  r8   r9   n/a  n/a  rax       (== NUM)
    ppc32  r0  r3   r4   r5   r6   r7   r8   n/a  n/a  r3+CR0.SO (== ARG1)
    ppc64  r0  r3   r4   r5   r6   r7   r8   n/a  n/a  r3+CR0.SO (== ARG1)
    amd64  rax rdi  rsi  rdx  r10  r8   r9   n/a  n/a  rax       (== NUM)
    ppc32  r0  r3   r4   r5   r6   r7   r8   n/a  n/a  r3+CR0.SO (== ARG1)
    ppc64  r0  r3   r4   r5   r6   r7   r8   n/a  n/a  r3+CR0.SO (== ARG1)

+   arm    r7  r0   r1   r2   r3   r4   r5   n/a  n/a  r0        (== ARG1)

 
    AIX:
    ppc32  r2  r3   r4   r5   r6   r7   r8   r9   r10  r3(res),r4(err)
 
    AIX:
    ppc32  r2  r3   r4   r5   r6   r7   r8   r9   r10  r3(res),r4(err)


@@ -1999,16 +2000,42 @@ void ML_(fixup_guest_state_to_restart_syscall) ( ThreadArchState* arch )
    }
 
 #elif defined(VGP_arm_linux)
    }
 
 #elif defined(VGP_arm_linux)

-   arch->vex.guest_R15 -= 4;   // sizeof(arm instr)
-   {
-      UChar *p = (UChar*)arch->vex.guest_R15;
-
-      if ((p[3] & 0xF) != 0xF)
+   if (arch->vex.guest_R15T & 1) {
+      // Thumb mode.  SVC is a encoded as
+      //   1101 1111 imm8
+      // where imm8 is the SVC number, and we only accept 0.
+      arch->vex.guest_R15T -= 2;   // sizeof(thumb 16 bit insn)
+      UChar* p     = (UChar*)(arch->vex.guest_R15T - 1);
+      Bool   valid = p[0] == 0 && p[1] == 0xDF;
+      if (!valid) {

          VG_(message)(Vg_DebugMsg,
          VG_(message)(Vg_DebugMsg,

-                      "?! restarting over syscall that is not syscall at %#llx %02x %02x %02x %02x\n",
-                      arch->vex.guest_R15 + 0ULL, p[0], p[1], p[2], p[3]);
-
-      vg_assert((p[3] & 0xF) == 0xF);
+                      "?! restarting over (Thumb) syscall that is not syscall "
+                      "at %#llx %02x %02x\n",
+                      arch->vex.guest_R15T - 1ULL, p[0], p[1]);
+      }
+      vg_assert(valid);
+      // FIXME: NOTE, this really isn't right.  We need to back up
+      // ITSTATE to what it was before the SVC instruction, but we
+      // don't know what it was.  At least assert that it is now
+      // zero, because if it is nonzero then it must also have
+      // been nonzero for the SVC itself, which means it was
+      // conditional.  Urk.
+      vg_assert(arch->vex.guest_ITSTATE == 0);
+   } else {
+      // ARM mode.  SVC is encoded as 
+      //   cond 1111 imm24
+      // where imm24 is the SVC number, and we only accept 0.
+      arch->vex.guest_R15T -= 4;   // sizeof(arm instr)
+      UChar* p     = (UChar*)arch->vex.guest_R15T;
+      Bool   valid = p[0] == 0 && p[1] == 0 && p[2] == 0
+                     && (p[3] & 0xF) == 0xF;
+      if (!valid) {
+         VG_(message)(Vg_DebugMsg,
+                      "?! restarting over (ARM) syscall that is not syscall "
+                      "at %#llx %02x %02x %02x %02x\n",
+                      arch->vex.guest_R15T + 0ULL, p[0], p[1], p[2], p[3]);
+      }
+      vg_assert(valid);

    }
 
 #elif defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5)
    }
 
 #elif defined(VGP_ppc32_aix5) || defined(VGP_ppc64_aix5)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-ppc64-linux.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-ppc64-linux.c
index fa4b8637bd374b55e38899cc19ea480666b02bcd..4f1bf29b9e148e10e6f75e9ac1d5fb49ed80eb71 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-ppc64-linux.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_syswrap/syswrap-ppc64-linux.c
@@ -1479,7 +1479,7 @@ static SyscallTableEntry syscall_table[] = {
    LINX_(__NR_mq_unlink,         sys_mq_unlink),          // 263
    LINX_(__NR_mq_timedsend,      sys_mq_timedsend),       // 264
 
    LINX_(__NR_mq_unlink,         sys_mq_unlink),          // 263
    LINX_(__NR_mq_timedsend,      sys_mq_timedsend),       // 264
 

-   LINX_(__NR_mq_timedreceive,   sys_mq_timedreceive),    // 265
+   LINXY(__NR_mq_timedreceive,   sys_mq_timedreceive),    // 265

    LINX_(__NR_mq_notify,         sys_mq_notify),          // 266
    LINXY(__NR_mq_getsetattr,     sys_mq_getsetattr),      // 267
 // _____(__NR_kexec_load,        sys_kexec_load),         // 268
    LINX_(__NR_mq_notify,         sys_mq_notify),          // 266
    LINXY(__NR_mq_getsetattr,     sys_mq_getsetattr),      // 267
 // _____(__NR_kexec_load,        sys_kexec_load),         // 268

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_trampoline.S b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_trampoline.S
index 5913098dc1945d06607ba3fe2a01f28907efb8c9..e225efed50c45a42198b595741c8bae5028b78be 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_trampoline.S
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_trampoline.S
@@ -924,8 +924,8 @@ VG_(x86_darwin_SUBST_FOR_sigreturn):
         int     $0x80
         ud2
 
         int     $0x80
         ud2
 

-.globl VG_(darwin_REDIR_FOR_strlen)
-VG_(darwin_REDIR_FOR_strlen):
+.globl VG_(x86_darwin_REDIR_FOR_strlen)
+VG_(x86_darwin_REDIR_FOR_strlen):

         movl    4(%esp), %edx
         movl    %edx, %eax
         jmp     1f
         movl    4(%esp), %edx
         movl    %edx, %eax
         jmp     1f


@@ -937,8 +937,8 @@ VG_(darwin_REDIR_FOR_strlen):
         subl    %edx, %eax
         ret
 
         subl    %edx, %eax
         ret
 

-.globl VG_(darwin_REDIR_FOR_strcat)
-VG_(darwin_REDIR_FOR_strcat):
+.globl VG_(x86_darwin_REDIR_FOR_strcat)
+VG_(x86_darwin_REDIR_FOR_strcat):

         pushl   %esi
         movl    8(%esp), %esi
         movl    12(%esp), %ecx
         pushl   %esi
         movl    8(%esp), %esi
         movl    12(%esp), %ecx


@@ -961,8 +961,8 @@ VG_(darwin_REDIR_FOR_strcat):
         ret
 
 
         ret
 
 

-.globl VG_(darwin_REDIR_FOR_strcmp)
-VG_(darwin_REDIR_FOR_strcmp):
+.globl VG_(x86_darwin_REDIR_FOR_strcmp)
+VG_(x86_darwin_REDIR_FOR_strcmp):

         movl    4(%esp), %edx
         movl    8(%esp), %ecx
         jmp     1f
         movl    4(%esp), %edx
         movl    8(%esp), %ecx
         jmp     1f


@@ -982,8 +982,8 @@ VG_(darwin_REDIR_FOR_strcmp):
         ret
 
 
         ret
 
 

-.globl VG_(darwin_REDIR_FOR_strcpy)
-VG_(darwin_REDIR_FOR_strcpy):
+.globl VG_(x86_darwin_REDIR_FOR_strcpy)
+VG_(x86_darwin_REDIR_FOR_strcpy):

        pushl   %ebp
        movl    %esp, %ebp
        pushl   %esi
        pushl   %ebp
        movl    %esp, %ebp
        pushl   %esi


@@ -1004,8 +1004,8 @@ VG_(darwin_REDIR_FOR_strcpy):
        leave
        ret
 
        leave
        ret
 

-.globl VG_(darwin_REDIR_FOR_strlcat)
-VG_(darwin_REDIR_FOR_strlcat):
+.globl VG_(x86_darwin_REDIR_FOR_strlcat)
+VG_(x86_darwin_REDIR_FOR_strlcat):

        pushl   %ebp
        movl    %esp, %ebp
        pushl   %edi
        pushl   %ebp
        movl    %esp, %ebp
        pushl   %edi


@@ -1034,7 +1034,7 @@ VG_(darwin_REDIR_FOR_strlcat):
 3:
        movl    12(%ebp), %eax
        movl    %eax, (%esp)
 3:
        movl    12(%ebp), %eax
        movl    %eax, (%esp)

-       call    VG_(darwin_REDIR_FOR_strlen)
+       call    VG_(x86_darwin_REDIR_FOR_strlen)

        jmp     7f
 4:
        cmpl    $1, %esi
        jmp     7f
 4:
        cmpl    $1, %esi


@@ -1076,8 +1076,16 @@ VG_(trampoline_stuff_end):
 .globl VG_(trampoline_stuff_start)
 VG_(trampoline_stuff_start):
 
 .globl VG_(trampoline_stuff_start)
 VG_(trampoline_stuff_start):
 

-.globl VG_(darwin_REDIR_FOR_strlen)
-VG_(darwin_REDIR_FOR_strlen):
+.globl VG_(amd64_darwin_SUBST_FOR_sigreturn)
+VG_(amd64_darwin_SUBST_FOR_sigreturn):
+        /* XXX does this need to have any special form? (cf x86-linux
+       version) */
+        movq    $ __NR_DARWIN_FAKE_SIGRETURN, %rax
+        syscall
+        ud2
+
+.globl VG_(amd64_darwin_REDIR_FOR_strlen)
+VG_(amd64_darwin_REDIR_FOR_strlen):

         movq    %rdi, %rax
         jmp     1f
 0:
         movq    %rdi, %rax
         jmp     1f
 0:


@@ -1088,8 +1096,8 @@ VG_(darwin_REDIR_FOR_strlen):
         subq    %rdi, %rax
         ret
 
         subq    %rdi, %rax
         ret
 

-.globl VG_(darwin_REDIR_FOR_strcat)
-VG_(darwin_REDIR_FOR_strcat):
+.globl VG_(amd64_darwin_REDIR_FOR_strcat)
+VG_(amd64_darwin_REDIR_FOR_strcat):

        movq    %rdi, %rdx
        jmp     1f
 0:
        movq    %rdi, %rdx
        jmp     1f
 0:


@@ -1108,8 +1116,8 @@ VG_(darwin_REDIR_FOR_strcat):
        ret
 
 
        ret
 
 

-.globl VG_(darwin_REDIR_FOR_strcmp)
-VG_(darwin_REDIR_FOR_strcmp):
+.globl VG_(amd64_darwin_REDIR_FOR_strcmp)
+VG_(amd64_darwin_REDIR_FOR_strcmp):

        jmp     1f
 0:
        incq    %rdi
        jmp     1f
 0:
        incq    %rdi


@@ -1126,8 +1134,8 @@ VG_(darwin_REDIR_FOR_strcmp):
        subl    %edx, %eax
        ret
 
        subl    %edx, %eax
        ret
 

-.globl VG_(darwin_REDIR_FOR_strcpy)
-VG_(darwin_REDIR_FOR_strcpy):
+.globl VG_(amd64_darwin_REDIR_FOR_strcpy)
+VG_(amd64_darwin_REDIR_FOR_strcpy):

        pushq   %rbp
        movq    %rdi, %rdx
        movq    %rsp, %rbp
        pushq   %rbp
        movq    %rdi, %rdx
        movq    %rsp, %rbp


@@ -1144,8 +1152,8 @@ VG_(darwin_REDIR_FOR_strcpy):
        movq    %rdi, %rax
        ret
        
        movq    %rdi, %rax
        ret
        

-.globl VG_(darwin_REDIR_FOR_strlcat)
-VG_(darwin_REDIR_FOR_strlcat):
+.globl VG_(amd64_darwin_REDIR_FOR_strlcat)
+VG_(amd64_darwin_REDIR_FOR_strlcat):

        pushq   %rbp
        leaq    (%rdx,%rdi), %rax
        movq    %rdi, %rcx
        pushq   %rbp
        leaq    (%rdx,%rdi), %rax
        movq    %rdi, %rcx


@@ -1170,7 +1178,7 @@ VG_(darwin_REDIR_FOR_strlcat):
        jmp     6f
 3:
        movq    %rsi, %rdi
        jmp     6f
 3:
        movq    %rsi, %rdi

-       call    VG_(darwin_REDIR_FOR_strlen)
+       call    VG_(amd64_darwin_REDIR_FOR_strlen)

        jmp     7f
 4:
        cmpq    $1, %rdi
        jmp     7f
 4:
        cmpq    $1, %rdi


@@ -1193,8 +1201,8 @@ VG_(darwin_REDIR_FOR_strlcat):
        leave
        ret
 
        leave
        ret
 

-.globl VG_(darwin_REDIR_FOR_arc4random)
-VG_(darwin_REDIR_FOR_arc4random):
+.globl VG_(amd64_darwin_REDIR_FOR_arc4random)
+VG_(amd64_darwin_REDIR_FOR_arc4random):

        /* not very random, hope dyld won't mind */
        movq    $0x76616c6772696e64, %rax
        ret
        /* not very random, hope dyld won't mind */
        movq    $0x76616c6772696e64, %rax
        ret

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/macho.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/macho.c
index 03547936c77364363edcbdd4a0a75e4cef5fd729..72f26b36f9844583da589de742fd07b093580772 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/macho.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/macho.c
@@ -73,11 +73,11 @@ static void print(const char *str)
    VG_(printf)("%s", str);
 }
 
    VG_(printf)("%s", str);
 }
 

-static void check_mmap(SysRes res, Addr base, SizeT len)
+static void check_mmap(SysRes res, Addr base, SizeT len, HChar* who)

 {
    if (sr_isError(res)) {
 {
    if (sr_isError(res)) {

-      VG_(printf)("valgrind: mmap(0x%llx, %lld) failed in UME.\n", 
-                  (ULong)base, (Long)len);
+      VG_(printf)("valgrind: mmap(0x%llx, %lld) failed in UME (%s).\n", 
+                  (ULong)base, (Long)len, who);

       VG_(exit)(1);
    }
 }
       VG_(exit)(1);
    }
 }


@@ -173,6 +173,19 @@ load_segment(int fd, vki_off_t offset, vki_off_t size,
 
    // GrP fixme mark __UNIXSTACK as SF_STACK
     
 
    // GrP fixme mark __UNIXSTACK as SF_STACK
     

+   // Don't honour the client's request to map PAGEZERO.  Why not?
+   // Because when the kernel loaded the valgrind tool executable,
+   // it will have mapped pagezero itself.  So further attempts
+   // to map it when loading the client are guaranteed to fail.
+#if VG_WORDSIZE == 4
+   if (segcmd->vmaddr == 0 && 0 == VG_(strcmp)(segcmd->segname, SEG_PAGEZERO)) {
+      if (segcmd->vmsize != 0x1000) {
+         print("bad executable (__PAGEZERO is not 4 KB)\n");
+         return -1;
+      }
+      return 0;
+   }
+#endif

 #if VG_WORDSIZE == 8
    if (segcmd->vmaddr == 0 && 0 == VG_(strcmp)(segcmd->segname, SEG_PAGEZERO)) {
       if (segcmd->vmsize != 0x100000000) {
 #if VG_WORDSIZE == 8
    if (segcmd->vmaddr == 0 && 0 == VG_(strcmp)(segcmd->segname, SEG_PAGEZERO)) {
       if (segcmd->vmsize != 0x100000000) {


@@ -213,10 +226,11 @@ load_segment(int fd, vki_off_t offset, vki_off_t size,
    vmsize = VG_PGROUNDUP(segcmd->vmsize);
    if (filesize > 0) {
       addr = (Addr)segcmd->vmaddr;
    vmsize = VG_PGROUNDUP(segcmd->vmsize);
    if (filesize > 0) {
       addr = (Addr)segcmd->vmaddr;

+      VG_(debugLog)(2, "ume", "mmap fixed (file) (%#lx, %lu)\n", addr, filesize);

       res = VG_(am_mmap_named_file_fixed_client)(addr, filesize, prot, fd, 
                                                  offset + segcmd->fileoff, 
                                                  filename);
       res = VG_(am_mmap_named_file_fixed_client)(addr, filesize, prot, fd, 
                                                  offset + segcmd->fileoff, 
                                                  filename);

-      check_mmap(res, addr, filesize);
+      check_mmap(res, addr, filesize, "load_segment1");

    }
 
    // Zero-fill the remainder of the segment, if any
    }
 
    // Zero-fill the remainder of the segment, if any


@@ -229,8 +243,9 @@ load_segment(int fd, vki_off_t offset, vki_off_t size,
       // page-aligned part
       SizeT length = vmsize - filesize;
       addr = (Addr)(filesize + segcmd->vmaddr);
       // page-aligned part
       SizeT length = vmsize - filesize;
       addr = (Addr)(filesize + segcmd->vmaddr);

+      VG_(debugLog)(2, "ume", "mmap fixed (anon) (%#lx, %lu)\n", addr, length);

       res = VG_(am_mmap_anon_fixed_client)(addr, length, prot);
       res = VG_(am_mmap_anon_fixed_client)(addr, length, prot);

-      check_mmap(res, addr, length);
+      check_mmap(res, addr, length, "load_segment2");

    }
 
    return 0;
    }
 
    return 0;


@@ -343,7 +358,7 @@ load_unixthread(vki_uint8_t **out_stack_start, vki_uint8_t **out_stack_end,
       SysRes res;
         
       res = VG_(am_mmap_anon_fixed_client)(stackbase, stacksize, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC);
       SysRes res;
         
       res = VG_(am_mmap_anon_fixed_client)(stackbase, stacksize, VKI_PROT_READ|VKI_PROT_WRITE|VKI_PROT_EXEC);

-      check_mmap(res, stackbase, stacksize);
+      check_mmap(res, stackbase, stacksize, "load_unixthread1");

       if (out_stack_start) *out_stack_start = (vki_uint8_t *)stackbase;
    } else {
       // custom stack - mapped via __UNIXTHREAD segment
       if (out_stack_start) *out_stack_start = (vki_uint8_t *)stackbase;
    } else {
       // custom stack - mapped via __UNIXTHREAD segment

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/main.c
index a99ee5e08d074787039601c5a23e58c26a2dd90b..45887eb10f01723ae4d941d5e3b52d4643ff0753 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/main.c
@@ -197,7 +197,7 @@ static Bool is_binary_file(Char* f)
       // Something went wrong.  This will only happen if we earlier
       // succeeded in opening the file but fail here (eg. the file was
       // deleted between then and now).
       // Something went wrong.  This will only happen if we earlier
       // succeeded in opening the file but fail here (eg. the file was
       // deleted between then and now).

-      VG_(printf)("valgrind: %s: unknown error\n", f);
+      VG_(fmsg)("%s: unknown error\n", f);

       VG_(exit)(126);      // 126 == NOEXEC
    }
 }
       VG_(exit)(126);      // 126 == NOEXEC
    }
 }


@@ -218,7 +218,7 @@ static Int do_exec_shell_followup(Int ret, HChar* exe_name, ExeInfo* info)
 
       // Is it a binary file?  
       if (is_binary_file(exe_name)) {
 
       // Is it a binary file?  
       if (is_binary_file(exe_name)) {

-         VG_(printf)("valgrind: %s: cannot execute binary file\n", exe_name);
+         VG_(fmsg)("%s: cannot execute binary file\n", exe_name);

          VG_(exit)(126);      // 126 == NOEXEC
       }
 
          VG_(exit)(126);      // 126 == NOEXEC
       }
 


@@ -234,7 +234,7 @@ static Int do_exec_shell_followup(Int ret, HChar* exe_name, ExeInfo* info)
 
       if (0 != ret) {
          // Something went wrong with executing the default interpreter
 
       if (0 != ret) {
          // Something went wrong with executing the default interpreter

-         VG_(printf)("valgrind: %s: bad interpreter (%s): %s\n",
+         VG_(fmsg)("%s: bad interpreter (%s): %s\n",

                      exe_name, info->interp_name, VG_(strerror)(ret));
          VG_(exit)(126);      // 126 == NOEXEC
       }
                      exe_name, info->interp_name, VG_(strerror)(ret));
          VG_(exit)(126);      // 126 == NOEXEC
       }


@@ -246,21 +246,20 @@ static Int do_exec_shell_followup(Int ret, HChar* exe_name, ExeInfo* info)
       // Was it a directory?
       res = VG_(stat)(exe_name, &st);
       if (!sr_isError(res) && VKI_S_ISDIR(st.mode)) {
       // Was it a directory?
       res = VG_(stat)(exe_name, &st);
       if (!sr_isError(res) && VKI_S_ISDIR(st.mode)) {

-         VG_(printf)("valgrind: %s: is a directory\n", exe_name);
+         VG_(fmsg)("%s: is a directory\n", exe_name);

       
       // Was it not executable?
       } else if (0 != VG_(check_executable)(NULL, exe_name, 
                                             False/*allow_setuid*/)) {
       
       // Was it not executable?
       } else if (0 != VG_(check_executable)(NULL, exe_name, 
                                             False/*allow_setuid*/)) {

-         VG_(printf)("valgrind: %s: %s\n", exe_name, VG_(strerror)(ret));
+         VG_(fmsg)("%s: %s\n", exe_name, VG_(strerror)(ret));

 
       // Did it start with "#!"?  If so, it must have been a bad interpreter.
       } else if (is_hash_bang_file(exe_name)) {
 
       // Did it start with "#!"?  If so, it must have been a bad interpreter.
       } else if (is_hash_bang_file(exe_name)) {

-         VG_(printf)("valgrind: %s: bad interpreter: %s\n",
-                     exe_name, VG_(strerror)(ret));
+         VG_(fmsg)("%s: bad interpreter: %s\n", exe_name, VG_(strerror)(ret));

 
       // Otherwise it was something else.
       } else {
 
       // Otherwise it was something else.
       } else {

-         VG_(printf)("valgrind: %s: %s\n", exe_name, VG_(strerror)(ret));
+         VG_(fmsg)("%s: %s\n", exe_name, VG_(strerror)(ret));

       }
       // 126 means NOEXEC;  I think this is Posix, and that in some cases we
       // should be returning 127, meaning NOTFOUND.  Oh well.
       }
       // 126 means NOEXEC;  I think this is Posix, and that in some cases we
       // should be returning 127, meaning NOTFOUND.  Oh well.

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/script.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/script.c
index 44359f417fac17b9c509a7cc018761504a15181e..13ca99192defe1675f0a406d4d5a4ae48d8c7a2c 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/script.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_ume/script.c
@@ -35,6 +35,8 @@
 #include "pub_core_libcassert.h"    // VG_(exit), vg_assert
 #include "pub_core_libcfile.h"      // VG_(close) et al
 #include "pub_core_libcprint.h"
 #include "pub_core_libcassert.h"    // VG_(exit), vg_assert
 #include "pub_core_libcfile.h"      // VG_(close) et al
 #include "pub_core_libcprint.h"

+#include "pub_core_xarray.h"
+#include "pub_core_clientstate.h"

 #include "pub_core_mallocfree.h"    // VG_(strdup)
 #include "pub_core_ume.h"           // self
 
 #include "pub_core_mallocfree.h"    // VG_(strdup)
 #include "pub_core_ume.h"           // self
 


@@ -133,6 +135,8 @@ Int VG_(load_script)(Int fd, const HChar* name, ExeInfo* info)
    if (info->argv && info->argv[0] != NULL)
       info->argv[0] = (char *)name;
 
    if (info->argv && info->argv[0] != NULL)
       info->argv[0] = (char *)name;
 

+   VG_(args_the_exename) = name;
+

    if (0)
       VG_(printf)("#! script: interp_name=\"%s\" interp_args=\"%s\"\n",
                   info->interp_name, info->interp_args);
    if (0)
       VG_(printf)("#! script: interp_name=\"%s\" interp_args=\"%s\"\n",
                   info->interp_name, info->interp_args);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_vkiscnums.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_vkiscnums.c
index 9813ae2f7e015217685de759c72f70f1825f2163..740d919a7d37763f9890774686fb29490bdb2598 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_vkiscnums.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/m_vkiscnums.c
@@ -1163,12 +1163,11 @@ Char* VG_(sysnum_string)(Word sysnum, SizeT n_buf, Char* buf)
 {
    Char* classname = NULL;
    switch (VG_DARWIN_SYSNO_CLASS(sysnum)) {
 {
    Char* classname = NULL;
    switch (VG_DARWIN_SYSNO_CLASS(sysnum)) {

-    case VG_DARWIN_SYSCALL_CLASS_MACH: classname = "mach"; break;
-    case VG_DARWIN_SYSCALL_CLASS_UNIX: classname = "unix"; break;
-    case VG_DARWIN_SYSCALL_CLASS_MDEP: classname = "mdep"; break;
-    case VG_DARWIN_SYSCALL_CLASS_DIAG: classname = "diag"; break;
-    default:
-      VG_(core_panic)("unknown Darwin sysnum class");
+      case VG_DARWIN_SYSCALL_CLASS_MACH: classname = "mach"; break;
+      case VG_DARWIN_SYSCALL_CLASS_UNIX: classname = "unix"; break;
+      case VG_DARWIN_SYSCALL_CLASS_MDEP: classname = "mdep"; break;
+      case VG_DARWIN_SYSCALL_CLASS_DIAG: classname = "diag"; break;
+      default: classname = "UNKNOWN"; break;

    }
    VG_(snprintf)(buf, n_buf, "%s:%3ld",
                              classname, VG_DARWIN_SYSNO_INDEX(sysnum));
    }
    VG_(snprintf)(buf, n_buf, "%s:%3ld",
                              classname, VG_DARWIN_SYSNO_INDEX(sysnum));

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_aspacemgr.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_aspacemgr.h
index 44bb6c477a5b416627de6f4aae4427fadf0500dc..581cb335620b39bd5bc83d644fa09ce6c7edab18 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_aspacemgr.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_aspacemgr.h
@@ -148,9 +148,19 @@ extern Addr VG_(am_get_advisory)
    fixed requests.  If start is zero, a floating request is issued; if
    nonzero, a fixed request at that address is issued.  Same comments
    about return values apply. */
    fixed requests.  If start is zero, a floating request is issued; if
    nonzero, a fixed request at that address is issued.  Same comments
    about return values apply. */

-extern Addr VG_(am_get_advisory_client_simple) 
+extern Addr VG_(am_get_advisory_client_simple)

    ( Addr start, SizeT len, /*OUT*/Bool* ok );
 
    ( Addr start, SizeT len, /*OUT*/Bool* ok );
 

+#if defined(VGO_l4re)
+/* Convenience wrapper for VG_(am_get_advisory) for Valgrind floating or
+    fixed requests.  If start is zero, a floating request is issued; if
+    nonzero, a fixed request at that address is issued.  Same comments
+    about return values apply. */
+extern Addr VG_(am_get_advisory_valgrind_simple)
+    ( Addr start, SizeT len, /*OUT*/Bool* ok );
+#endif
+
+

 /* Notifies aspacem that the client completed an mmap successfully.
    The segment array is updated accordingly.  If the returned Bool is
    True, the caller should immediately discard translations from the
 /* Notifies aspacem that the client completed an mmap successfully.
    The segment array is updated accordingly.  If the returned Bool is
    True, the caller should immediately discard translations from the


@@ -375,10 +385,10 @@ extern Bool VG_(am_relocate_nooverlap_client)( /*OUT*/Bool* need_discard,
 
 #if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
 # define VG_STACK_GUARD_SZB  65536  // 1 or 16 pages
 
 #if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
 # define VG_STACK_GUARD_SZB  65536  // 1 or 16 pages

-# define VG_STACK_ACTIVE_SZB 131072 // 2 or 32 pages
+# define VG_STACK_ACTIVE_SZB (4096 * 256) // 1Mb

 #else
 # define VG_STACK_GUARD_SZB  8192   // 2 pages
 #else
 # define VG_STACK_GUARD_SZB  8192   // 2 pages

-# define VG_STACK_ACTIVE_SZB 65536  // 16 pages
+# define VG_STACK_ACTIVE_SZB (4096 * 256) // 1Mb

 #endif
 
 typedef
 #endif
 
 typedef

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_dispatch.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_dispatch.h
index 6fa04addaece6f3baacd931ffe25cd5984faa106..8deaeca63f4057b0dcf214c061ce0f807fa7d0c5 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_dispatch.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_dispatch.h
@@ -68,8 +68,8 @@ UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
    following somewhat bogus decls.  At least on x86 and amd64.  ppc32
    and ppc64 use straightforward bl-blr to get from dispatcher to
    translation and back and so do not need these labels. */
    following somewhat bogus decls.  At least on x86 and amd64.  ppc32
    and ppc64 use straightforward bl-blr to get from dispatcher to
    translation and back and so do not need these labels. */

-extern void VG_(run_innerloop__dispatch_unprofiled);
-extern void VG_(run_innerloop__dispatch_profiled);
+extern Addr VG_(run_innerloop__dispatch_unprofiled);
+extern Addr VG_(run_innerloop__dispatch_profiled);

 #endif
 
 
 #endif
 
 


@@ -86,7 +86,7 @@ extern void VG_(run_a_noredir_translation) ( volatile UWord* argblock );
 /* We need to a label inside VG_(run_a_noredir_translation), so that
    Vex can add branches to them from generated code.  Hence the
    following somewhat bogus decl. */
 /* We need to a label inside VG_(run_a_noredir_translation), so that
    Vex can add branches to them from generated code.  Hence the
    following somewhat bogus decl. */

-extern void VG_(run_a_noredir_translation__return_point);
+extern Addr VG_(run_a_noredir_translation__return_point);

 #endif
 
 
 #endif
 
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_libcprint.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_libcprint.h
index 9148235c25196ec39cec765f32712bc7abb9d73e..5692972c1b46403bd0c8d5e0cde3ac6c5574f895 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_libcprint.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_libcprint.h
@@ -54,6 +54,16 @@ extern OutputSink VG_(xml_output_sink);
    m_main during startup. */
 void VG_(elapsed_wallclock_time) ( /*OUT*/HChar* buf );
 
    m_main during startup. */
 void VG_(elapsed_wallclock_time) ( /*OUT*/HChar* buf );
 

+/* Call this if the executable is missing.  This function prints an
+   error message, then shuts down the entire system. */
+__attribute__((noreturn))
+extern void VG_(err_missing_prog) ( void );
+
+/* Similarly - complain and stop if there is some kind of config
+   error. */
+__attribute__((noreturn))
+extern void VG_(err_config_error) ( Char* msg );
+

 #endif   // __PUB_CORE_LIBCPRINT_H
 
 /*--------------------------------------------------------------------*/
 #endif   // __PUB_CORE_LIBCPRINT_H
 
 /*--------------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_machine.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_machine.h
index a6ef97c3fc11dad80604cade7b6bb0f47c9a7755..979bdf7015577edba1c491fe5778bd8b6d448710 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_machine.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_machine.h
@@ -101,7 +101,7 @@
 #  define VG_STACK_PTR        guest_GPR1
 #  define VG_FRAME_PTR        guest_GPR1   // No frame ptr for PPC
 #elif defined(VGA_arm)
 #  define VG_STACK_PTR        guest_GPR1
 #  define VG_FRAME_PTR        guest_GPR1   // No frame ptr for PPC
 #elif defined(VGA_arm)

-#  define VG_INSTR_PTR        guest_R15
+#  define VG_INSTR_PTR        guest_R15T

 #  define VG_STACK_PTR        guest_R13
 #  define VG_FRAME_PTR        guest_R11
 #else
 #  define VG_STACK_PTR        guest_R13
 #  define VG_FRAME_PTR        guest_R11
 #else


@@ -114,6 +114,18 @@
 #define VG_O_INSTR_PTR        (offsetof(VexGuestArchState, VG_INSTR_PTR))
 
 
 #define VG_O_INSTR_PTR        (offsetof(VexGuestArchState, VG_INSTR_PTR))
 
 

+//-------------------------------------------------------------
+// Guest state accessors that are not visible to tools.  The only
+// ones that are visible are get_IP and get_SP.
+
+//Addr VG_(get_IP) ( ThreadId tid );  // in pub_tool_machine.h
+//Addr VG_(get_SP) ( ThreadId tid );  // in pub_tool_machine.h
+Addr VG_(get_FP) ( ThreadId tid );
+
+void VG_(set_IP) ( ThreadId tid, Addr encip );
+void VG_(set_SP) ( ThreadId tid, Addr sp );
+
+

 //-------------------------------------------------------------
 // Get hold of the values needed for a stack unwind, for the specified
 // (client) thread.
 //-------------------------------------------------------------
 // Get hold of the values needed for a stack unwind, for the specified
 // (client) thread.


@@ -203,6 +215,10 @@ extern UInt VG_(machine_ppc32_has_VMX);
 extern ULong VG_(machine_ppc64_has_VMX);
 #endif
 
 extern ULong VG_(machine_ppc64_has_VMX);
 #endif
 

+#if defined(VGA_arm)
+extern Int VG_(machine_arm_archlevel);
+#endif
+

 #endif   // __PUB_CORE_MACHINE_H
 
 /*--------------------------------------------------------------------*/
 #endif   // __PUB_CORE_MACHINE_H
 
 /*--------------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_options.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_options.h
index 716a124c06fe1e7bf33a240f98711cea17e371f8..24125bc89c705a3e525ac6f494a107a8b6b6e0ab 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_options.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_options.h
@@ -210,18 +210,6 @@ extern HChar* VG_(clo_kernel_variant);
    .dSYM directories as necessary? */
 extern Bool VG_(clo_dsymutil);
 
    .dSYM directories as necessary? */
 extern Bool VG_(clo_dsymutil);
 

-/* --------- Functions --------- */
-
-/* Call this if the executable is missing.  This function prints an
-   error message, then shuts down the entire system. */
-__attribute__((noreturn))
-extern void VG_(err_missing_prog) ( void );
-
-/* Similarly - complain and stop if there is some kind of config
-   error. */
-__attribute__((noreturn))
-extern void VG_(err_config_error) ( Char* msg );
-

 /* Should we trace into this child executable (across execve etc) ?
    This involves considering --trace-children=, --trace-children-skip=
    and the name of the executable. */
 /* Should we trace into this child executable (across execve etc) ?
    This involves considering --trace-children=, --trace-children-skip=
    and the name of the executable. */

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_trampoline.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_trampoline.h
index d72e900a22f84648638007033f3208ba728fd894..56025ad7d98946ef51513e1b1da59d5885fc733c 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_trampoline.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/pub_core_trampoline.h
@@ -53,32 +53,32 @@
    readable, at least.  Otherwise Memcheck complains we're jumping to
    invalid addresses. */
 
    readable, at least.  Otherwise Memcheck complains we're jumping to
    invalid addresses. */
 

-extern void VG_(trampoline_stuff_start);
-extern void VG_(trampoline_stuff_end);
+extern Addr VG_(trampoline_stuff_start);
+extern Addr VG_(trampoline_stuff_end);

 
 #if defined(VGP_x86_linux)
 
 #if defined(VGP_x86_linux)

-extern void VG_(x86_linux_SUBST_FOR_sigreturn);
-extern void VG_(x86_linux_SUBST_FOR_rt_sigreturn);
+extern Addr VG_(x86_linux_SUBST_FOR_sigreturn);
+extern Addr VG_(x86_linux_SUBST_FOR_rt_sigreturn);

 extern Char* VG_(x86_linux_REDIR_FOR_index) ( const Char*, Int );
 #endif
 
 #if defined(VGP_amd64_linux)
 extern Char* VG_(x86_linux_REDIR_FOR_index) ( const Char*, Int );
 #endif
 
 #if defined(VGP_amd64_linux)

-extern void VG_(amd64_linux_SUBST_FOR_rt_sigreturn);
-extern void VG_(amd64_linux_REDIR_FOR_vgettimeofday);
-extern void VG_(amd64_linux_REDIR_FOR_vtime);
+extern Addr VG_(amd64_linux_SUBST_FOR_rt_sigreturn);
+extern Addr VG_(amd64_linux_REDIR_FOR_vgettimeofday);
+extern Addr VG_(amd64_linux_REDIR_FOR_vtime);

 extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* );
 #endif
 
 #if defined(VGP_ppc32_linux)
 extern UInt VG_(amd64_linux_REDIR_FOR_strlen)( void* );
 #endif
 
 #if defined(VGP_ppc32_linux)

-extern void  VG_(ppc32_linux_SUBST_FOR_sigreturn);
-extern void  VG_(ppc32_linux_SUBST_FOR_rt_sigreturn);
+extern Addr  VG_(ppc32_linux_SUBST_FOR_sigreturn);
+extern Addr  VG_(ppc32_linux_SUBST_FOR_rt_sigreturn);

 extern UInt  VG_(ppc32_linux_REDIR_FOR_strlen)( void* );
 extern UInt  VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* );
 extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int );
 #endif
 
 #if defined(VGP_ppc64_linux)
 extern UInt  VG_(ppc32_linux_REDIR_FOR_strlen)( void* );
 extern UInt  VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* );
 extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int );
 #endif
 
 #if defined(VGP_ppc64_linux)

-extern void  VG_(ppc64_linux_SUBST_FOR_rt_sigreturn);
+extern Addr  VG_(ppc64_linux_SUBST_FOR_rt_sigreturn);

 extern UInt  VG_(ppc64_linux_REDIR_FOR_strlen)( void* );
 extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int );
 /* A label (sans dot) marking the ultra-magical return stub via which
 extern UInt  VG_(ppc64_linux_REDIR_FOR_strlen)( void* );
 extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int );
 /* A label (sans dot) marking the ultra-magical return stub via which


@@ -88,7 +88,7 @@ extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int );
    restore the thread's LR and R2 registers from a small stack in the
    ppc64 guest state structure, and then branch to LR.  Convoluted?
    Confusing?  You betcha.  Could I think of anything simpler?  No. */
    restore the thread's LR and R2 registers from a small stack in the
    ppc64 guest state structure, and then branch to LR.  Convoluted?
    Confusing?  You betcha.  Could I think of anything simpler?  No. */

-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern Addr VG_(ppctoc_magic_redirect_return_stub);

 #endif
 
 #if defined(VGP_arm_linux)
 #endif
 
 #if defined(VGP_arm_linux)


@@ -105,28 +105,39 @@ extern void* VG_(arm_linux_REDIR_FOR_memcpy)( void*, void*, Int );
    then it cleans up the register state to be more what it really
    should be at client startup, and finally it jumps to the client's
    real entry point. */
    then it cleans up the register state to be more what it really
    should be at client startup, and finally it jumps to the client's
    real entry point. */

-extern void VG_(ppc32_aix5_do_preloads_then_start_client);
+extern Addr VG_(ppc32_aix5_do_preloads_then_start_client);

 
 /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */
 
 /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */

-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern Addr VG_(ppctoc_magic_redirect_return_stub);

 #endif
 
 #if defined(VGP_ppc64_aix5)
 /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */
 #endif
 
 #if defined(VGP_ppc64_aix5)
 /* See comment for VG_(ppctoc_magic_redirect_return_stub) above. */

-extern void VG_(ppctoc_magic_redirect_return_stub);
+extern Addr VG_(ppctoc_magic_redirect_return_stub);

 
 /* See comment for ppc32_aix5 equivalent above. */
 
 /* See comment for ppc32_aix5 equivalent above. */

-extern void VG_(ppc64_aix5_do_preloads_then_start_client);
+extern Addr VG_(ppc64_aix5_do_preloads_then_start_client);

 #endif
 
 #endif
 

-#if defined(VGO_darwin)
-extern void  VG_(x86_darwin_SUBST_FOR_sigreturn);
-extern SizeT VG_(darwin_REDIR_FOR_strlen)( void* );
-extern SizeT VG_(darwin_REDIR_FOR_strcmp)( void*, void* );
-extern void* VG_(darwin_REDIR_FOR_strcat)( void*, void * );
-extern char* VG_(darwin_REDIR_FOR_strcpy)( char *s1, char *s2 );
-extern SizeT VG_(darwin_REDIR_FOR_strlcat)( char *s1, const char *s2, SizeT size );
-extern UInt VG_(darwin_REDIR_FOR_arc4random)( void );
+#if defined(VGP_x86_darwin)
+extern Addr  VG_(x86_darwin_SUBST_FOR_sigreturn);
+extern SizeT VG_(x86_darwin_REDIR_FOR_strlen)( void* );
+extern SizeT VG_(x86_darwin_REDIR_FOR_strcmp)( void*, void* );
+extern void* VG_(x86_darwin_REDIR_FOR_strcat)( void*, void * );
+extern char* VG_(x86_darwin_REDIR_FOR_strcpy)( char *s1, char *s2 );
+extern SizeT VG_(x86_darwin_REDIR_FOR_strlcat)( char *s1, const char *s2,
+                                                SizeT size );
+#endif
+
+#if defined(VGP_amd64_darwin)
+extern Addr  VG_(amd64_darwin_SUBST_FOR_sigreturn);
+extern SizeT VG_(amd64_darwin_REDIR_FOR_strlen)( void* );
+extern SizeT VG_(amd64_darwin_REDIR_FOR_strcmp)( void*, void* );
+extern void* VG_(amd64_darwin_REDIR_FOR_strcat)( void*, void * );
+extern char* VG_(amd64_darwin_REDIR_FOR_strcpy)( char *s1, char *s2 );
+extern SizeT VG_(amd64_darwin_REDIR_FOR_strlcat)( char *s1, const char *s2,
+                                                  SizeT size );
+extern UInt VG_(amd64_darwin_REDIR_FOR_arc4random)( void );

 #endif
 
 #if defined(VGO_l4re)
 #endif
 
 #if defined(VGO_l4re)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/vg_preloaded.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/vg_preloaded.c
index 750eead4c19703d929314f1062e1fc305ae50c2b..8d69b16dd64bffc8618191f877d927e251ffdaac 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/vg_preloaded.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/coregrind/vg_preloaded.c
@@ -151,17 +151,18 @@ static void vg_cleanup_env(void)
    Darwin arc4random (rdar://6166275)
    ------------------------------------------------------------------ */
 
    Darwin arc4random (rdar://6166275)
    ------------------------------------------------------------------ */
 

-#include <stdio.h>
+#include <fcntl.h>
+#include <unistd.h>

 
 int VG_REPLACE_FUNCTION_ZU(libSystemZdZaZddylib, arc4random)(void);
 int VG_REPLACE_FUNCTION_ZU(libSystemZdZaZddylib, arc4random)(void)
 {
 
 int VG_REPLACE_FUNCTION_ZU(libSystemZdZaZddylib, arc4random)(void);
 int VG_REPLACE_FUNCTION_ZU(libSystemZdZaZddylib, arc4random)(void)
 {

-    static FILE *rnd = 0;
+    static int rnd = -1;

     int result;
 
     int result;
 

-    if (!rnd) rnd = fopen("/dev/random", "r");
-    
-    fread(&result, sizeof(result), 1, rnd);
+    if (rnd < 0) rnd = open("/dev/random", O_RDONLY);
+
+    read(rnd, &result, sizeof(result));

     return result;
 }
 
     return result;
 }
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin10-drd.supp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin10-drd.supp
new file mode 100644 (file)
index 0000000..385d6c9
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin10-drd.supp
@@ -0,0 +1,2 @@
+
+# DRD suppressions for Darwin 10.x / Mac OS X 10.6 Snow Leopard

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin10.supp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin10.supp
new file mode 100644 (file)
index 0000000..f9515a5
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin10.supp
@@ -0,0 +1,22 @@
+
+# Suppressions for Darwin 10.x / Mac OS X 10.6 Snow Leopard
+
+##----------------------------------------------------------------------##
+# Memcheck
+##----------------------------------------------------------------------##
+
+# From Jesse Ruderman.
+{
+   Mac OS X 10.6.4. rdar://8145289. "new[]" paired with "delete" in the DesktopServicesPriv framework.
+   Memcheck:Free
+   fun:_ZdlPv
+   fun:_ZN5TChar18RemovePtrReferenceEv
+ }
+
+# From Jesse Ruderman.
+{
+   Mac OS X 10.6.4. rdar://8145318. Uninitialized memory from HIMenuBarView::MeasureAppMenus is used in HIMenuBarView::SetAdjustTextTitleBoundsAtIndex.
+   Memcheck:Cond
+   fun:_ZN13HIMenuBarView31SetAdjustTextTitleBoundsAtIndexEih
+   fun:_ZN13HIMenuBarView15MeasureAppMenusEv
+ }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin9-drd.supp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin9-drd.supp
index f9425e768da31d9bd9566215d46afeacc87e6c6c..ea301431b0624438a50f65fda0c636a6edf9b98b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin9-drd.supp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin9-drd.supp
@@ -1,3 +1,6 @@
+
+# DRD suppressions for Darwin 9.x / Mac OS X 10.5 Leopard
+

 #
 # Suppression patterns for dyld, the dynamic loader.
 #
 #
 # Suppression patterns for dyld, the dynamic loader.
 #

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin9.supp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin9.supp
index 17228671043921be1e1e04ef27a08d3944b430e3..d49fcdd5b56b1a13df85abd4a92c7dc3ef723e93 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin9.supp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/darwin9.supp
@@ -180,6 +180,13 @@
    fun:vsnprintf
 }
 
    fun:vsnprintf
 }
 

+{
+   macos-TFontFeatures::TFontFeatures(unsigned long)-uninitialised-stack-val
+   Memcheck:Cond
+   fun:_ZN13TFontFeaturesC2Em
+   fun:_ZNK9TBaseFont12CopyFeaturesEv
+}
+

 ##----------------------------------------------------------------------##
 # Helgrind
 ##----------------------------------------------------------------------##
 ##----------------------------------------------------------------------##
 # Helgrind
 ##----------------------------------------------------------------------##

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/Makefile.in
index fcec024be2ca4335cd629c551d2f46a9da1a78cb..087a43c969b20b4b841affb9c9721f752d0ea753 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/Makefile.in
@@ -83,6 +83,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -117,14 +118,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/FAQ.xml b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/FAQ.xml
index 9ee8ea3d0876ef7efa668f4c80f84adecbd4bf33..983e02adde4228cde678ac65ff031014086247fe 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/FAQ.xml
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/FAQ.xml
@@ -528,7 +528,10 @@ int main(void)
       </listitem>
       <listitem>
         <para>"possibly lost" means your program is leaking
       </listitem>
       <listitem>
         <para>"possibly lost" means your program is leaking

-        memory, unless you're doing funny things with pointers.</para>
+        memory, unless you're doing funny things with pointers.
+        This is sometimes reasonable.  Use
+        <option>--show-possibly-lost=no</option> if you don't want to see
+        these reports.</para>

       </listitem>
       <listitem>
         <para>"still reachable" means your program is probably ok -- it
       </listitem>
       <listitem>
         <para>"still reachable" means your program is probably ok -- it

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/manual-core-adv.xml b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/manual-core-adv.xml
index 03d86e1e3b54d910dc3ad6c07d5cefbdb4232370..10929b7ffbe8a42bc4baeccb6fd79bbeb0595691 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/manual-core-adv.xml
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/manual-core-adv.xml
@@ -196,7 +196,7 @@ tool-specific macros).</para>
     message is prefixed with the PID between a pair of
     <computeroutput>**</computeroutput> markers.  (Like all client requests,
     nothing is output if the client program is not running under Valgrind.)
     message is prefixed with the PID between a pair of
     <computeroutput>**</computeroutput> markers.  (Like all client requests,
     nothing is output if the client program is not running under Valgrind.)

-    Output is not produced until a newline is encountered, or subequent
+    Output is not produced until a newline is encountered, or subsequent

     Valgrind output is printed; this allows you to build up a single line of
     output over multiple calls.  Returns the number of characters output,
     excluding the PID prefix.</para>
     Valgrind output is printed; this allows you to build up a single line of
     output over multiple calls.  Returns the number of characters output,
     excluding the PID prefix.</para>

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/manual-core.xml b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/manual-core.xml
index 724dac99e5d534b074283c06a10a48604abcf5e0..8a75292d369d00b730b522ae3d3e03b0dc2bcee7 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/manual-core.xml
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/docs/xml/manual-core.xml
@@ -596,7 +596,8 @@ in most cases.  We group the available options by rough categories.</para>
     <term><option>-h --help</option></term>
     <listitem>
       <para>Show help for all options, both for the core and for the
     <term><option>-h --help</option></term>
     <listitem>
       <para>Show help for all options, both for the core and for the

-      selected tool.</para>
+      selected tool.  If the option is repeated it is equivalent to giving
+      <option>--help-debug</option>.</para>

     </listitem>
   </varlistentry>
 
     </listitem>
   </varlistentry>
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/Makefile.am
index c54d665ecaa645bd64d784b28ca03840070a4840..f28c7524dac032687ddcbcd90f2e56e4b42a1246 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/Makefile.am
@@ -56,6 +56,7 @@ DRD_SOURCES_COMMON =    \
   drd_clientobj.c       \
   drd_clientreq.c       \
   drd_cond.c            \
   drd_clientobj.c       \
   drd_clientreq.c       \
   drd_cond.c            \

+  drd_cond_initializer.c \

   drd_error.c           \
   drd_hb.c              \
   drd_load_store.c      \
   drd_error.c           \
   drd_hb.c              \
   drd_load_store.c      \


@@ -66,7 +67,8 @@ DRD_SOURCES_COMMON =    \
   drd_semaphore.c       \
   drd_suppression.c
 
   drd_semaphore.c       \
   drd_suppression.c
 

-drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = $(DRD_SOURCES_COMMON)
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = \
+       $(DRD_SOURCES_COMMON)

 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \


@@ -77,8 +79,16 @@ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 if VGCONF_HAVE_PLATFORM_SEC

-drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = $(DRD_SOURCES_COMMON)
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
+       $(DRD_SOURCES_COMMON)

 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \
 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \


@@ -89,6 +99,12 @@ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 #----------------------------------------------------------------------------
 endif
 
 #----------------------------------------------------------------------------


@@ -120,6 +136,7 @@ vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
 vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+

 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = \
        $(VGPRELOAD_DRD_SOURCES_COMMON)
 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = \
        $(VGPRELOAD_DRD_SOURCES_COMMON)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/Makefile.in
index b54d88233d1844b2c0df0293d653cb57027fd7bd..740a3857866984a4934e8ec8372e613b2e738616 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/Makefile.in
@@ -45,29 +45,13 @@ host_triplet = @host@
 DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
        $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
 DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
        $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)
 noinst_PROGRAMS = drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_drd-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_14 = vgpreload_drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = vgpreload_drd-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so

 subdir = drd
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = drd
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -86,6 +70,7 @@ am__objects_1 =  \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.$(OBJEXT) \

+       drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.$(OBJEXT) \

        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.$(OBJEXT) \
        drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.$(OBJEXT) \


@@ -98,20 +83,18 @@ am__objects_1 =  \
 am_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
 am_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o $@

 am__drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = drd_barrier.c \
        drd_bitmap2_node.c drd_clientobj.c drd_clientreq.c drd_cond.c \
 am__drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = drd_barrier.c \
        drd_bitmap2_node.c drd_clientobj.c drd_clientreq.c drd_cond.c \

-       drd_error.c drd_hb.c drd_load_store.c drd_main.c \
-       drd_malloc_wrappers.c drd_mutex.c drd_rwlock.c drd_semaphore.c \
-       drd_suppression.c
+       drd_cond_initializer.c drd_error.c drd_hb.c drd_load_store.c \
+       drd_main.c drd_malloc_wrappers.c drd_mutex.c drd_rwlock.c \
+       drd_semaphore.c drd_suppression.c

 am__objects_2 =  \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_bitmap2_node.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.$(OBJEXT) \
 am__objects_2 =  \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_barrier.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_bitmap2_node.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.$(OBJEXT) \

+       drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.$(OBJEXT) \

        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.$(OBJEXT) \
        drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.$(OBJEXT) \


@@ -125,9 +108,6 @@ am__objects_2 =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o $@

 am__objects_3 = vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.$(OBJEXT) \
        vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.$(OBJEXT) \
        vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.$(OBJEXT)
 am__objects_3 = vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_pthread_intercepts.$(OBJEXT) \
        vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_qtcore_intercepts.$(OBJEXT) \
        vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-drd_strmem_intercepts.$(OBJEXT)


@@ -274,6 +254,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -308,14 +289,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -399,7 +384,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -458,7 +445,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -473,8 +460,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -537,37 +524,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -576,32 +563,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -723,6 +706,7 @@ DRD_SOURCES_COMMON = \
   drd_clientobj.c       \
   drd_clientreq.c       \
   drd_cond.c            \
   drd_clientobj.c       \
   drd_clientreq.c       \
   drd_cond.c            \

+  drd_cond_initializer.c \

   drd_error.c           \
   drd_hb.c              \
   drd_load_store.c      \
   drd_error.c           \
   drd_hb.c              \
   drd_load_store.c      \


@@ -733,7 +717,9 @@ DRD_SOURCES_COMMON = \
   drd_semaphore.c       \
   drd_suppression.c
 
   drd_semaphore.c       \
   drd_suppression.c
 

-drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(DRD_SOURCES_COMMON)
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+       $(DRD_SOURCES_COMMON)
+

 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 


@@ -749,7 +735,16 @@ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(DRD_SOURCES_COMMON)
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(DRD_SOURCES_COMMON)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 


@@ -765,6 +760,13 @@ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

+@VGCONF_HAVE_PLATFORM_SEC_TRUE@drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+

 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 VGPRELOAD_DRD_SOURCES_COMMON = \
   drd_pthread_intercepts.c     \
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 VGPRELOAD_DRD_SOURCES_COMMON = \
   drd_pthread_intercepts.c     \


@@ -803,8 +805,7 @@ vgpreload_drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -865,6 +866,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientobj.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_clientreq.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_hb.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_load_store.Po@am__quote@


@@ -879,6 +881,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientobj.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_clientreq.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_hb.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_load_store.Po@am__quote@


@@ -979,6 +982,20 @@ drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.obj: drd_cond.c
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.obj `if test -f 'drd_cond.c'; then $(CYGPATH_W) 'drd_cond.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond.c'; fi`
 
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond.obj `if test -f 'drd_cond.c'; then $(CYGPATH_W) 'drd_cond.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond.c'; fi`
 

+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o: drd_cond_initializer.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o `test -f 'drd_cond_initializer.c' || echo '$(srcdir)/'`drd_cond_initializer.c
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='drd_cond_initializer.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.o `test -f 'drd_cond_initializer.c' || echo '$(srcdir)/'`drd_cond_initializer.c
+
+drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj: drd_cond_initializer.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj `if test -f 'drd_cond_initializer.c'; then $(CYGPATH_W) 'drd_cond_initializer.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond_initializer.c'; fi`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='drd_cond_initializer.c' object='drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_cond_initializer.obj `if test -f 'drd_cond_initializer.c'; then $(CYGPATH_W) 'drd_cond_initializer.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond_initializer.c'; fi`
+

 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o: drd_error.c
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o `test -f 'drd_error.c' || echo '$(srcdir)/'`drd_error.c
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Po
 drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o: drd_error.c
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Tpo -c -o drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.o `test -f 'drd_error.c' || echo '$(srcdir)/'`drd_error.c
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_PRI@_@VGCONF_OS@-drd_error.Po


@@ -1175,6 +1192,20 @@ drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.obj: drd_cond.c
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.obj `if test -f 'drd_cond.c'; then $(CYGPATH_W) 'drd_cond.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond.c'; fi`
 
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond.obj `if test -f 'drd_cond.c'; then $(CYGPATH_W) 'drd_cond.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond.c'; fi`
 

+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o: drd_cond_initializer.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o `test -f 'drd_cond_initializer.c' || echo '$(srcdir)/'`drd_cond_initializer.c
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='drd_cond_initializer.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.o `test -f 'drd_cond_initializer.c' || echo '$(srcdir)/'`drd_cond_initializer.c
+
+drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj: drd_cond_initializer.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj `if test -f 'drd_cond_initializer.c'; then $(CYGPATH_W) 'drd_cond_initializer.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond_initializer.c'; fi`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='drd_cond_initializer.c' object='drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_cond_initializer.obj `if test -f 'drd_cond_initializer.c'; then $(CYGPATH_W) 'drd_cond_initializer.c'; else $(CYGPATH_W) '$(srcdir)/drd_cond_initializer.c'; fi`
+

 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o: drd_error.c
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o `test -f 'drd_error.c' || echo '$(srcdir)/'`drd_error.c
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Po
 drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o: drd_error.c
 @am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS) $(CPPFLAGS) $(drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) -MT drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o -MD -MP -MF $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Tpo -c -o drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.o `test -f 'drd_error.c' || echo '$(srcdir)/'`drd_error.c
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Tpo $(DEPDIR)/drd_@VGCONF_ARCH_SEC@_@VGCONF_OS@-drd_error.Po


@@ -1599,16 +1630,14 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(pkgincludedir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done
 all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(pkgincludedir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -1625,7 +1654,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -1634,7 +1662,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1705,9 +1732,8 @@ ps-am:
 
 uninstall-am: uninstall-pkgincludeHEADERS
 
 
 uninstall-am: uninstall-pkgincludeHEADERS
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1790,65 +1816,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_clientreq.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_clientreq.c
index 852348e3bbffb44c94458785dc1b6a9df6e9d51a..9a78b796417ddd71731929149249730d641ba43a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_clientreq.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_clientreq.c
@@ -174,6 +174,11 @@ static Bool handle_client_request(ThreadId vg_tid, UWord* arg, UWord* ret)
       DRD_(rwlock_pre_unlock)(arg[1], user_rwlock);
       break;
 
       DRD_(rwlock_pre_unlock)(arg[1], user_rwlock);
       break;
 

+   case VG_USERREQ__SET_PTHREAD_COND_INITIALIZER:
+      DRD_(pthread_cond_initializer) = (Addr)arg[1];
+      DRD_(pthread_cond_initializer_size) = arg[2];
+      break;
+

    case VG_USERREQ__DRD_START_NEW_SEGMENT:
       DRD_(thread_new_segment)(DRD_(PtThreadIdToDrdThreadId)(arg[1]));
       break;
    case VG_USERREQ__DRD_START_NEW_SEGMENT:
       DRD_(thread_new_segment)(DRD_(PtThreadIdToDrdThreadId)(arg[1]));
       break;

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_clientreq.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_clientreq.h
index f059c6683959de9c99f729155ac4fa1974280342..2f63170391c28ade401f84b45e6fcb8abd004032 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_clientreq.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_clientreq.h
@@ -45,8 +45,14 @@
  * source files.
  */
 enum {
  * source files.
  */
 enum {

+   /* Declare the address and size of a variable with value
+    * PTHREAD_COND_INITIALIZER.
+    */
+   VG_USERREQ__SET_PTHREAD_COND_INITIALIZER = VG_USERREQ_TOOL_BASE('D', 'r'),
+   /* args: address, size. */
+

    /* To ask the drd tool to start a new segment in the specified thread. */
    /* To ask the drd tool to start a new segment in the specified thread. */

-   VG_USERREQ__DRD_START_NEW_SEGMENT = VG_USERREQ_TOOL_BASE('D', 'r'),
+   VG_USERREQ__DRD_START_NEW_SEGMENT,

    /* args: POSIX thread ID. */
 
    /* Tell drd the pthread_t of the running thread. */
    /* args: POSIX thread ID. */
 
    /* Tell drd the pthread_t of the running thread. */

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond.c
index 456b290f3e7a750a6b6675317b52da797132ef5a..bef880f825058c75e74237e0b978a0ddb15a9fbd 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond.c
@@ -29,6 +29,7 @@
 #include "drd_mutex.h"
 #include "pub_tool_errormgr.h"    /* VG_(maybe_record_error)() */
 #include "pub_tool_libcassert.h"  /* tl_assert()               */
 #include "drd_mutex.h"
 #include "pub_tool_errormgr.h"    /* VG_(maybe_record_error)() */
 #include "pub_tool_libcassert.h"  /* tl_assert()               */

+#include "pub_tool_libcbase.h"    /* VG_(memcmp)()             */

 #include "pub_tool_libcprint.h"   /* VG_(printf)()             */
 #include "pub_tool_machine.h"     /* VG_(get_IP)()             */
 #include "pub_tool_threadstate.h" /* VG_(get_running_tid)()    */
 #include "pub_tool_libcprint.h"   /* VG_(printf)()             */
 #include "pub_tool_machine.h"     /* VG_(get_IP)()             */
 #include "pub_tool_threadstate.h" /* VG_(get_running_tid)()    */


@@ -45,6 +46,12 @@ static Bool DRD_(s_report_signal_unlocked) = True;
 static Bool DRD_(s_trace_cond);
 
 
 static Bool DRD_(s_trace_cond);
 
 

+/* Global variables. */
+
+Addr DRD_(pthread_cond_initializer);
+int DRD_(pthread_cond_initializer_size);
+
+

 /* Function definitions. */
 
 void DRD_(cond_set_report_signal_unlocked)(const Bool r)
 /* Function definitions. */
 
 void DRD_(cond_set_report_signal_unlocked)(const Bool r)


@@ -382,12 +389,17 @@ void DRD_(cond_pre_signal)(Addr const cond)
                    cond);
    }
 
                    cond);
    }
 

-   if (!p)
+   tl_assert(DRD_(pthread_cond_initializer));
+   if (!p && VG_(memcmp)((void*)cond, (void*)DRD_(pthread_cond_initializer),
+                         DRD_(pthread_cond_initializer_size)) != 0)

    {
       not_initialized(cond);
       return;
    }
 
    {
       not_initialized(cond);
       return;
    }
 

+   if (!p)
+      p = cond_get_or_allocate(cond);
+

    cond_signal(DRD_(thread_get_running_tid)(), p);
 }
 
    cond_signal(DRD_(thread_get_running_tid)(), p);
 }
 


@@ -405,11 +417,16 @@ void DRD_(cond_pre_broadcast)(Addr const cond)
    }
 
    p = DRD_(cond_get)(cond);
    }
 
    p = DRD_(cond_get)(cond);

-   if (!p)
+   tl_assert(DRD_(pthread_cond_initializer));
+   if (!p && VG_(memcmp)((void*)cond, (void*)DRD_(pthread_cond_initializer),
+                         DRD_(pthread_cond_initializer_size)) != 0)

    {
       not_initialized(cond);
       return;
    }
 
    {
       not_initialized(cond);
       return;
    }
 

+   if (!p)
+      p = cond_get_or_allocate(cond);
+

    cond_signal(DRD_(thread_get_running_tid)(), p);
 }
    cond_signal(DRD_(thread_get_running_tid)(), p);
 }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond.h
index a511912d570e8fd1f881c03f2e2038e2baac5f61..755fe82b3c3ada4a7cf3e1910d00dab9f224f0b1 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond.h
@@ -36,6 +36,12 @@
 struct cond_info;
 
 
 struct cond_info;
 
 

+/* Variable declarations. */
+
+extern Addr DRD_(pthread_cond_initializer);
+extern int DRD_(pthread_cond_initializer_size);
+
+

 /* Function declarations. */
 
 void DRD_(cond_set_report_signal_unlocked)(const Bool r);
 /* Function declarations. */
 
 void DRD_(cond_set_report_signal_unlocked)(const Bool r);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond_initializer.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond_initializer.c
new file mode 100644 (file)
index 0000000..ab041f0
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_cond_initializer.c
@@ -0,0 +1,8 @@
+/* Make the value of PTHREAD_COND_INITIALIZER available to DRD. */
+
+#include "drd_cond.h"
+#include <pthread.h>
+
+static pthread_cond_t pthread_cond_initializer = PTHREAD_COND_INITIALIZER;
+Addr DRD_(pthread_cond_initializer) = (Addr)&pthread_cond_initializer;
+int DRD_(pthread_cond_initializer_size) = sizeof(pthread_cond_initializer);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_pthread_intercepts.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_pthread_intercepts.c
index bead0e9859c61ce0e4b623d64210a0ddf22de37e..f3026edd3dfc2aa6f220888a856d9ff8ec611b68 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_pthread_intercepts.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_pthread_intercepts.c
@@ -339,10 +339,8 @@ static void DRD_(set_main_thread_state)(void)
    // Make sure that DRD knows about the main thread's POSIX thread ID.
    VALGRIND_DO_CLIENT_REQUEST(res, -1, VG_USERREQ__SET_PTHREADID,
                               pthread_self(), 0, 0, 0, 0);
    // Make sure that DRD knows about the main thread's POSIX thread ID.
    VALGRIND_DO_CLIENT_REQUEST(res, -1, VG_USERREQ__SET_PTHREADID,
                               pthread_self(), 0, 0, 0, 0);

-

 }
 
 }
 

-

 /*
  * Note: as of today there exist three different versions of pthread_create
  * in Linux:
 /*
  * Note: as of today there exist three different versions of pthread_create
  * in Linux:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_semaphore.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_semaphore.c
index 77c34c99ec24394678201424d3c996705599ed67..1cb03a570a411ade21bd7011595c5abdafc2f3ff 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_semaphore.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/drd_semaphore.c
@@ -337,6 +337,7 @@ void DRD_(semaphore_pre_wait)(const Addr semaphore)
 {
    struct semaphore_info* p;
 
 {
    struct semaphore_info* p;
 

+   tl_assert(semaphore < semaphore + 1);

    p = drd_semaphore_get_or_allocate(semaphore);
    tl_assert(p);
    p->waiters++;
    p = drd_semaphore_get_or_allocate(semaphore);
    tl_assert(p);
    p->waiters++;

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/scripts/download-and-build-gcc b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/scripts/download-and-build-gcc
index 9197824116f2c7960170db4983e441bb998e0f33..8b8cd4d9d24590d54fcb210702c0963224e1b77c 100755 (executable)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/scripts/download-and-build-gcc
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/scripts/download-and-build-gcc
@@ -14,20 +14,26 @@ SRC=$HOME/software/gcc-${GCC_VERSION}
 BUILD=${SRC}-build
 TAR=gcc-${GCC_VERSION}.tar.bz2
 PREFIX=$HOME/gcc-${GCC_VERSION}
 BUILD=${SRC}-build
 TAR=gcc-${GCC_VERSION}.tar.bz2
 PREFIX=$HOME/gcc-${GCC_VERSION}

+GMP_PREFIX=/usr
+#GMP_PREFIX=$HOME/gmp-5.0.1
+MPFR_PREFIX=/usr
+#MPFR_PREFIX=$HOME/mpfr-2.4.2
+MPC_PREFIX=/usr
+#MPC_PREFIX=$HOME/mpc-0.8.1

 export LC_ALL=C
 export MAKEFLAGS="-j$(($(grep -c '^processor' /proc/cpuinfo) + 1))"
 
 export LC_ALL=C
 export MAKEFLAGS="-j$(($(grep -c '^processor' /proc/cpuinfo) + 1))"
 

-if [ ! -e /usr/include/gmp.h ]; then
+if [ ! -e $GMP_PREFIX/include/gmp.h ]; then

   echo "Please install the gmp library development package first."
   exit 1
 fi
 
   echo "Please install the gmp library development package first."
   exit 1
 fi
 

-if [ ! -e /usr/include/mpfr.h ]; then
+if [ ! -e $MPFR_PREFIX/include/mpfr.h ]; then

   echo "Please install the mpfr library development package first."
   exit 1
 fi
 
   echo "Please install the mpfr library development package first."
   exit 1
 fi
 

-if [ ! -e /usr/include/mpc.h ]; then
+if [ ! -e $MPC_PREFIX/include/mpc.h ]; then

   echo "Please install the mpc library development package first."
   exit 1
 fi
   echo "Please install the mpc library development package first."
   exit 1
 fi


@@ -59,6 +65,9 @@ ${SRC}/configure            \
   --enable-languages=c,c++  \
   --enable-threads=posix    \
   --enable-tls              \
   --enable-languages=c,c++  \
   --enable-threads=posix    \
   --enable-tls              \

-  --prefix=$PREFIX
+  --prefix=$PREFIX          \
+  --with-gmp=$GMP_PREFIX    \
+  --with-mpfr=$MPFR_PREFIX  \
+  --with-mpc=$MPC_PREFIX

 
 time { make -s && make -s install; }
 
 time { make -s && make -s install; }

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/Makefile.am
index 08d24aa7fe019aa8d5c139fbcbfa96ca1014c1d4..857d2275e0a2c4d93bfad077c8b383ec371d189a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/Makefile.am
@@ -11,7 +11,8 @@ dist_noinst_SCRIPTS =             \
        supported_sem_init
 
 noinst_HEADERS =                                    \
        supported_sem_init
 
 noinst_HEADERS =                                    \

-       tsan_thread_wrappers_pthread.h
+       tsan_thread_wrappers_pthread.h              \
+       unified_annotations.h

 
 EXTRA_DIST =                                        \
        annotate_barrier.stderr.exp                 \
 
 EXTRA_DIST =                                        \
        annotate_barrier.stderr.exp                 \


@@ -159,6 +160,8 @@ EXTRA_DIST =                                        \
        pth_process_shared_mutex.vgtest             \
        pth_spinlock.stderr.exp                     \
        pth_spinlock.vgtest                         \
        pth_process_shared_mutex.vgtest             \
        pth_spinlock.stderr.exp                     \
        pth_spinlock.vgtest                         \

+       pth_uninitialized_cond.stderr.exp           \
+       pth_uninitialized_cond.vgtest               \

        qt4_atomic.stderr.exp                       \
        qt4_atomic.vgtest                           \
        qt4_mutex.stderr.exp                        \
        qt4_atomic.stderr.exp                       \
        qt4_atomic.vgtest                           \
        qt4_mutex.stderr.exp                        \


@@ -280,6 +283,7 @@ check_PROGRAMS =      \
   pth_inconsistent_cond_wait \
   pth_mutex_reinit    \
   pth_process_shared_mutex   \
   pth_inconsistent_cond_wait \
   pth_mutex_reinit    \
   pth_process_shared_mutex   \

+  pth_uninitialized_cond \

   recursive_mutex     \
   rwlock_race         \
   rwlock_test         \
   recursive_mutex     \
   rwlock_race         \
   rwlock_test         \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/Makefile.in
index bf684f68cc5002e57be4f14e97a3212fcd7dafdc..e3594acbe92cb56451cbe21727a8ba44337e20ed 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/Makefile.in
@@ -59,7 +59,8 @@ check_PROGRAMS = annotate_hb_err$(EXEEXT) annotate_hb_race$(EXEEXT) \
        pth_cond_race$(EXEEXT) pth_create_chain$(EXEEXT) \
        pth_detached$(EXEEXT) pth_detached_sem$(EXEEXT) \
        pth_inconsistent_cond_wait$(EXEEXT) pth_mutex_reinit$(EXEEXT) \
        pth_cond_race$(EXEEXT) pth_create_chain$(EXEEXT) \
        pth_detached$(EXEEXT) pth_detached_sem$(EXEEXT) \
        pth_inconsistent_cond_wait$(EXEEXT) pth_mutex_reinit$(EXEEXT) \

-       pth_process_shared_mutex$(EXEEXT) recursive_mutex$(EXEEXT) \
+       pth_process_shared_mutex$(EXEEXT) \
+       pth_uninitialized_cond$(EXEEXT) recursive_mutex$(EXEEXT) \

        rwlock_race$(EXEEXT) rwlock_test$(EXEEXT) \
        rwlock_type_checking$(EXEEXT) sem_as_mutex$(EXEEXT) \
        sem_open$(EXEEXT) sigalrm$(EXEEXT) thread_name$(EXEEXT) \
        rwlock_race$(EXEEXT) rwlock_test$(EXEEXT) \
        rwlock_type_checking$(EXEEXT) sem_as_mutex$(EXEEXT) \
        sem_open$(EXEEXT) sigalrm$(EXEEXT) thread_name$(EXEEXT) \


@@ -279,6 +280,10 @@ pth_spinlock_SOURCES = pth_spinlock.c
 pth_spinlock_OBJECTS = pth_spinlock.$(OBJEXT)
 pth_spinlock_LDADD = $(LDADD)
 pth_spinlock_DEPENDENCIES =
 pth_spinlock_OBJECTS = pth_spinlock.$(OBJEXT)
 pth_spinlock_LDADD = $(LDADD)
 pth_spinlock_DEPENDENCIES =

+pth_uninitialized_cond_SOURCES = pth_uninitialized_cond.c
+pth_uninitialized_cond_OBJECTS = pth_uninitialized_cond.$(OBJEXT)
+pth_uninitialized_cond_LDADD = $(LDADD)
+pth_uninitialized_cond_DEPENDENCIES =

 am__qt4_atomic_SOURCES_DIST = qt4_atomic.cpp
 @HAVE_QTCORE_QATOMICINT_TRUE@am_qt4_atomic_OBJECTS =  \
 @HAVE_QTCORE_QATOMICINT_TRUE@  qt4_atomic-qt4_atomic.$(OBJEXT)
 am__qt4_atomic_SOURCES_DIST = qt4_atomic.cpp
 @HAVE_QTCORE_QATOMICINT_TRUE@am_qt4_atomic_OBJECTS =  \
 @HAVE_QTCORE_QATOMICINT_TRUE@  qt4_atomic-qt4_atomic.$(OBJEXT)


@@ -392,12 +397,12 @@ SOURCES = annotate_barrier.c annotate_hb_err.c annotate_hb_race.c \
        pth_create_glibc_2_0.c pth_detached.c pth_detached_sem.c \
        pth_inconsistent_cond_wait.c pth_mutex_reinit.c \
        pth_process_shared_mutex.c pth_spinlock.c \
        pth_create_glibc_2_0.c pth_detached.c pth_detached_sem.c \
        pth_inconsistent_cond_wait.c pth_mutex_reinit.c \
        pth_process_shared_mutex.c pth_spinlock.c \

-       $(qt4_atomic_SOURCES) $(qt4_mutex_SOURCES) \
-       $(qt4_rwlock_SOURCES) $(qt4_semaphore_SOURCES) \
-       recursive_mutex.c rwlock_race.c rwlock_test.c \
-       rwlock_type_checking.c sem_as_mutex.c sem_open.c sigalrm.c \
-       thread_name.c trylock.c $(tsan_unittest_SOURCES) unit_bitmap.c \
-       unit_vc.c
+       pth_uninitialized_cond.c $(qt4_atomic_SOURCES) \
+       $(qt4_mutex_SOURCES) $(qt4_rwlock_SOURCES) \
+       $(qt4_semaphore_SOURCES) recursive_mutex.c rwlock_race.c \
+       rwlock_test.c rwlock_type_checking.c sem_as_mutex.c sem_open.c \
+       sigalrm.c thread_name.c trylock.c $(tsan_unittest_SOURCES) \
+       unit_bitmap.c unit_vc.c

 DIST_SOURCES = annotate_barrier.c annotate_hb_err.c annotate_hb_race.c \
        annotate_ignore_rw.c annotate_ignore_write.c \
        annotate_publish_hg.c annotate_rwlock.c \
 DIST_SOURCES = annotate_barrier.c annotate_hb_err.c annotate_hb_race.c \
        annotate_ignore_rw.c annotate_ignore_write.c \
        annotate_publish_hg.c annotate_rwlock.c \


@@ -413,8 +418,8 @@ DIST_SOURCES = annotate_barrier.c annotate_hb_err.c annotate_hb_race.c \
        pth_create_glibc_2_0.c pth_detached.c pth_detached_sem.c \
        pth_inconsistent_cond_wait.c pth_mutex_reinit.c \
        pth_process_shared_mutex.c pth_spinlock.c \
        pth_create_glibc_2_0.c pth_detached.c pth_detached_sem.c \
        pth_inconsistent_cond_wait.c pth_mutex_reinit.c \
        pth_process_shared_mutex.c pth_spinlock.c \

-       $(am__qt4_atomic_SOURCES_DIST) $(am__qt4_mutex_SOURCES_DIST) \
-       $(am__qt4_rwlock_SOURCES_DIST) \
+       pth_uninitialized_cond.c $(am__qt4_atomic_SOURCES_DIST) \
+       $(am__qt4_mutex_SOURCES_DIST) $(am__qt4_rwlock_SOURCES_DIST) \

        $(am__qt4_semaphore_SOURCES_DIST) recursive_mutex.c \
        rwlock_race.c rwlock_test.c rwlock_type_checking.c \
        sem_as_mutex.c sem_open.c sigalrm.c thread_name.c trylock.c \
        $(am__qt4_semaphore_SOURCES_DIST) recursive_mutex.c \
        rwlock_race.c rwlock_test.c rwlock_type_checking.c \
        sem_as_mutex.c sem_open.c sigalrm.c thread_name.c trylock.c \


@@ -460,6 +465,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -494,14 +500,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -584,7 +594,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -643,7 +655,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -658,8 +670,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -730,7 +742,8 @@ dist_noinst_SCRIPTS = \
        supported_sem_init
 
 noinst_HEADERS = \
        supported_sem_init
 
 noinst_HEADERS = \

-       tsan_thread_wrappers_pthread.h
+       tsan_thread_wrappers_pthread.h              \
+       unified_annotations.h

 
 EXTRA_DIST = \
        annotate_barrier.stderr.exp                 \
 
 EXTRA_DIST = \
        annotate_barrier.stderr.exp                 \


@@ -878,6 +891,8 @@ EXTRA_DIST = \
        pth_process_shared_mutex.vgtest             \
        pth_spinlock.stderr.exp                     \
        pth_spinlock.vgtest                         \
        pth_process_shared_mutex.vgtest             \
        pth_spinlock.stderr.exp                     \
        pth_spinlock.vgtest                         \

+       pth_uninitialized_cond.stderr.exp           \
+       pth_uninitialized_cond.vgtest               \

        qt4_atomic.stderr.exp                       \
        qt4_atomic.vgtest                           \
        qt4_mutex.stderr.exp                        \
        qt4_atomic.stderr.exp                       \
        qt4_atomic.vgtest                           \
        qt4_mutex.stderr.exp                        \


@@ -1169,6 +1184,9 @@ pth_process_shared_mutex$(EXEEXT): $(pth_process_shared_mutex_OBJECTS) $(pth_pro
 pth_spinlock$(EXEEXT): $(pth_spinlock_OBJECTS) $(pth_spinlock_DEPENDENCIES) 
        @rm -f pth_spinlock$(EXEEXT)
        $(LINK) $(pth_spinlock_OBJECTS) $(pth_spinlock_LDADD) $(LIBS)
 pth_spinlock$(EXEEXT): $(pth_spinlock_OBJECTS) $(pth_spinlock_DEPENDENCIES) 
        @rm -f pth_spinlock$(EXEEXT)
        $(LINK) $(pth_spinlock_OBJECTS) $(pth_spinlock_LDADD) $(LIBS)

+pth_uninitialized_cond$(EXEEXT): $(pth_uninitialized_cond_OBJECTS) $(pth_uninitialized_cond_DEPENDENCIES) 
+       @rm -f pth_uninitialized_cond$(EXEEXT)
+       $(LINK) $(pth_uninitialized_cond_OBJECTS) $(pth_uninitialized_cond_LDADD) $(LIBS)

 qt4_atomic$(EXEEXT): $(qt4_atomic_OBJECTS) $(qt4_atomic_DEPENDENCIES) 
        @rm -f qt4_atomic$(EXEEXT)
        $(qt4_atomic_LINK) $(qt4_atomic_OBJECTS) $(qt4_atomic_LDADD) $(LIBS)
 qt4_atomic$(EXEEXT): $(qt4_atomic_OBJECTS) $(qt4_atomic_DEPENDENCIES) 
        @rm -f qt4_atomic$(EXEEXT)
        $(qt4_atomic_LINK) $(qt4_atomic_OBJECTS) $(qt4_atomic_LDADD) $(LIBS)


@@ -1263,6 +1281,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_mutex_reinit.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_process_shared_mutex.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_spinlock.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_mutex_reinit.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_process_shared_mutex.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_spinlock.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pth_uninitialized_cond.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/qt4_atomic-qt4_atomic.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/qt4_mutex-qt4_mutex.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/qt4_rwlock-qt4_rwlock.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/qt4_atomic-qt4_atomic.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/qt4_mutex-qt4_mutex.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/qt4_rwlock-qt4_rwlock.Po@am__quote@

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.c
new file mode 100644 (file)
index 0000000..6acfbc7
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.c
@@ -0,0 +1,28 @@
+/* Test program to verify whether DRD only complains about uninitialized
+ * condition variables for dynamically allocated memory.
+ */
+
+
+#include <pthread.h>
+#include <stdio.h>
+
+
+static pthread_cond_t s_cond1 = PTHREAD_COND_INITIALIZER;
+static pthread_cond_t s_cond2 = PTHREAD_COND_INITIALIZER;
+
+
+int main(int argc, char** argv)
+{
+    fprintf(stderr, "Statically initialized condition variable.\n");
+
+    pthread_cond_signal(&s_cond1);
+
+    fprintf(stderr, "Uninitialized condition variable.\n");
+
+    *((char*)&s_cond2 + sizeof(s_cond2) - 1) ^= 1;
+    pthread_cond_signal(&s_cond2);
+
+    fprintf(stderr, "Done.\n");
+
+    return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.stderr.exp
new file mode 100644 (file)
index 0000000..a693944
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.stderr.exp
@@ -0,0 +1,10 @@
+
+Statically initialized condition variable.
+Uninitialized condition variable.
+condition variable has not been initialized: cond 0x........
+   at 0x........: pthread_cond_signal (drd_pthread_intercepts.c:?)
+   by 0x........: main (pth_uninitialized_cond.c:?)
+
+Done.
+
+ERROR SUMMARY: 1 errors from 1 contexts (suppressed: 0 from 0)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.vgtest
new file mode 100644 (file)
index 0000000..fe03139
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/pth_uninitialized_cond.vgtest
@@ -0,0 +1,3 @@
+prereq: test -e pth_uninitialized_cond && ./supported_libpthread
+vgopts: --read-var-info=yes --check-stack-var=yes
+prog: pth_uninitialized_cond

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/tsan_unittest.cpp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/tsan_unittest.cpp
index eb4562100108dca823a421dc12074f1cc9157c97..6ba123d7626a10988e3eda43004a4c6253d9951b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/tsan_unittest.cpp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/drd/tests/tsan_unittest.cpp
@@ -6620,8 +6620,8 @@ void Getter() {
     }
     usleep(1000);
   }
     }
     usleep(1000);
   }

-  printf("T=%d: non_zero_received=%d\n", 
-         (int)pthread_self(), non_zero_received);
+  printf("T=%zd: non_zero_received=%d\n", 
+         (size_t)pthread_self(), non_zero_received);

 } 
 
 void Run() {
 } 
 
 void Run() {

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/Makefile.am
index aa7f40b4108354c24ef365426225cb3ffb295fd2..78d9e53287cfdeff18cb02391e270c190dffa51b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/Makefile.am
@@ -13,7 +13,8 @@ endif
 
 BBV_SOURCES_COMMON = bbv_main.c
 
 
 BBV_SOURCES_COMMON = bbv_main.c
 

-exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = $(BBV_SOURCES_COMMON)
+exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = \
+       $(BBV_SOURCES_COMMON)

 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \


@@ -24,8 +25,16 @@ exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 if VGCONF_HAVE_PLATFORM_SEC

-exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = $(BBV_SOURCES_COMMON)
+exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
+       $(BBV_SOURCES_COMMON)

 exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \
 exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \


@@ -36,4 +45,10 @@ exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 endif

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/Makefile.in
index cf3edd3ce20d66a345b133b6fc7490e91ecffeb1..9781d4f64a9ac9cb50a784150ff64371001eb616 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/Makefile.in
@@ -43,25 +43,9 @@ build_triplet = @build@
 host_triplet = @host@
 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
 host_triplet = @host@
 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = exp-bbv-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)
 noinst_PROGRAMS = exp-bbv-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = exp-bbv-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = exp-bbv-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = exp-bbv
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = exp-bbv
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4


@@ -79,10 +63,6 @@ am__objects_1 =  \
 am_exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
 am_exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o \
-       $@

 am__exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = bbv_main.c
 am__objects_2 =  \
        exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbv_main.$(OBJEXT)
 am__exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = bbv_main.c
 am__objects_2 =  \
        exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@-bbv_main.$(OBJEXT)


@@ -90,10 +70,6 @@ am__objects_2 =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o \
-       $@

 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 am__depfiles_maybe = depfiles
 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 am__depfiles_maybe = depfiles


@@ -184,6 +160,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -218,14 +195,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -309,7 +290,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -368,7 +351,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -383,8 +366,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -447,37 +430,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -486,32 +469,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -590,7 +569,9 @@ LIBREPLACEMALLOC_LDFLAGS_X86_L4RE = \
 
 EXTRA_DIST = docs/bbv-manual.xml
 BBV_SOURCES_COMMON = bbv_main.c
 
 EXTRA_DIST = docs/bbv-manual.xml
 BBV_SOURCES_COMMON = bbv_main.c

-exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(BBV_SOURCES_COMMON)
+exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+       $(BBV_SOURCES_COMMON)
+

 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 


@@ -606,7 +587,16 @@ exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(BBV_SOURCES_COMMON)
+exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(BBV_SOURCES_COMMON)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 


@@ -622,8 +612,14 @@ exp_bbv_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(exp_bbv_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -912,13 +908,11 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
 all-am: Makefile $(PROGRAMS) all-local
 installdirs: installdirs-recursive
 installdirs-am:

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -935,7 +929,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -944,7 +937,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1015,9 +1007,8 @@ ps-am:
 
 uninstall-am:
 
 
 uninstall-am:
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1099,65 +1090,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/Makefile.in
index 3d8fe46b659fc5ec4f8246902dc181b62ca6ea51..8f603b819b1a5e6d31227bd925bc50d2047b01ba 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/Makefile.in
@@ -143,6 +143,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -177,14 +178,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -267,7 +272,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -326,7 +333,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -341,8 +348,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/amd64-linux/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/amd64-linux/Makefile.in
index 2d307b1775e63bc07aa8474ef60e55b0c6a6bc61..7a9f172f2c43da9e58006a066fda644efc901788 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/amd64-linux/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/amd64-linux/Makefile.in
@@ -132,6 +132,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -166,14 +167,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -256,7 +261,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -315,7 +322,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -330,8 +337,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/ppc32-linux/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/ppc32-linux/Makefile.in
index 30f59e5a83cbcbc100a79e36d3b55c5db7888647..c61fac04ef4b3db99ce2e734195446fd0bf26ee8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/ppc32-linux/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/ppc32-linux/Makefile.in
@@ -115,6 +115,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -149,14 +150,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -239,7 +244,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -298,7 +305,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -313,8 +320,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/x86-linux/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/x86-linux/Makefile.in
index 31d0ebe03f1765274f789d0775721045cfb1d942..7a61225ded25dcc698a2abcf38ae121e9091f02b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/x86-linux/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/x86-linux/Makefile.in
@@ -115,6 +115,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -149,14 +150,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -239,7 +244,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -298,7 +305,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -313,8 +320,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/x86/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/x86/Makefile.in
index b8d9429aa6b299562f2bb8d9d837868b48ba4a8a..ef4940950779cadcfb79c2d031a97e414589c706 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/x86/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-bbv/tests/x86/Makefile.in
@@ -124,6 +124,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -158,14 +159,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -248,7 +253,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -307,7 +314,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -322,8 +329,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck.supp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck.supp
index 83dcf29f2d8e8a1edd5e4ac6c74c08e5ffa12ccf..fd077d60c97d361c6aad6fa89e59b685563904d8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck.supp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck.supp
@@ -55,3 +55,33 @@
    fun:(below main)
 }
 
    fun:(below main)
 }
 

+
+# Invalid read of size 16
+#    at 0x5643A5C: ??? (strcpy.S:94)
+#    by 0x50C6A99: XtResolvePathname (in /usr/lib/libXt.so.6.0.0)
+#    by 0x50C3856: XtScreenDatabase (in /usr/lib/libXt.so.6.0.0)
+#    by 0x50C4386: _XtDisplayInitialize (in /usr/lib/libXt.so.6.0.0)
+{
+   Ubuntu 10.04 x86_64, SSEised strcpy, can't intercept
+   exp-ptrcheck:Heap
+   obj:/*lib*/libc-2.*so*
+   obj:/*lib*/libX*so*
+}
+{
+   Ubuntu 10.04 x86_64, SSEised strcpy, can't intercept - 2
+   exp-ptrcheck:Heap
+   obj:/*lib*/libc-2.*so*
+   obj:/*lib*/libICE*so*
+}
+{
+   Ubuntu 10.04 x86_64, SSEised strcpy, can't intercept - 3
+   exp-ptrcheck:Heap
+   obj:/*lib*/libc-2.*so*
+   obj:/*lib*/libglib*so*
+}
+{
+   Ubuntu 10.04 x86_64, SSEised strcpy, can't intercept - 4
+   exp-ptrcheck:Heap
+   obj:/*lib*/libc-2.*so*
+   obj:/*lib*/libfontconfig*so*
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/Makefile.am
index 5a9ffa4a17efd3d85b6712d9dc9612ccc075b1b5..3ccc47817d5d873fa050275ca1a6a8386bbe3edf 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/Makefile.am
@@ -38,6 +38,13 @@ exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
        $(EXP_PTRCHECK_SOURCES_COMMON)
 if VGCONF_HAVE_PLATFORM_SEC
 exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
        $(EXP_PTRCHECK_SOURCES_COMMON)


@@ -51,6 +58,12 @@ exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 #----------------------------------------------------------------------------
 endif
 
 #----------------------------------------------------------------------------


@@ -79,6 +92,7 @@ vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
 vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+

 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = \
        $(VGPRELOAD_EXP_PTRCHECK_SOURCES_COMMON)
 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = \
        $(VGPRELOAD_EXP_PTRCHECK_SOURCES_COMMON)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/Makefile.in
index 996a3de88764a7ed423481e05c8b994d181026cd..f64036e67a5b1f471531b85c7a58133e243be9b3 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/Makefile.in
@@ -45,29 +45,13 @@ host_triplet = @host@
 DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
        $(top_srcdir)/Makefile.tool.am
 DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
        $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = exp-ptrcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_exp-ptrcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)
 noinst_PROGRAMS = exp-ptrcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_exp-ptrcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = exp-ptrcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = exp-ptrcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_14 = vgpreload_exp-ptrcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = vgpreload_exp-ptrcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so

 subdir = exp-ptrcheck
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = exp-ptrcheck
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -89,10 +73,6 @@ am_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am__objects_1)
 exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
        $(am__objects_1)
 exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) \
-       $(LDFLAGS) -o $@

 am__exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST =  \
        h_main.c pc_common.c pc_main.c sg_main.c
 am__objects_2 =  \
 am__exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST =  \
        h_main.c pc_common.c pc_main.c sg_main.c
 am__objects_2 =  \


@@ -104,10 +84,6 @@ am__objects_2 =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) \
-       $(LDFLAGS) -o $@

 am__objects_3 = vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-h_intercepts.$(OBJEXT)
 am_vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =  \
        $(am__objects_3)
 am__objects_3 = vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-h_intercepts.$(OBJEXT)
 am_vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =  \
        $(am__objects_3)


@@ -229,6 +205,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -263,14 +240,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -354,7 +335,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -413,7 +396,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -428,8 +411,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -492,37 +475,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start
+
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -531,32 +514,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64
+

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -667,6 +646,13 @@ exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

+exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(EXP_PTRCHECK_SOURCES_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(EXP_PTRCHECK_SOURCES_COMMON)
 


@@ -685,6 +671,13 @@ exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

+@VGCONF_HAVE_PLATFORM_SEC_TRUE@exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(exp_ptrcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+

 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 VGPRELOAD_EXP_PTRCHECK_SOURCES_COMMON = h_intercepts.c
 vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 VGPRELOAD_EXP_PTRCHECK_SOURCES_COMMON = h_intercepts.c
 vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \


@@ -719,8 +712,7 @@ vgpreload_exp_ptrcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -1135,13 +1127,11 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
 all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -1158,7 +1148,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -1167,7 +1156,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1238,9 +1226,8 @@ ps-am:
 
 uninstall-am:
 
 
 uninstall-am:
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1322,65 +1309,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/h_intercepts.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/h_intercepts.c
index 812d52c97ec76a8d41dd8a6a6a73dbc4012e6350..54fbc624deda753717b1afbf8fa934fed3e083d6 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/h_intercepts.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/h_intercepts.c
@@ -126,12 +126,61 @@ STRNLEN(VG_Z_LIBC_SONAME, strnlen)
 
 STRLEN(VG_Z_LIBC_SONAME,          strlen)
 #if defined(VGO_linux)
 
 STRLEN(VG_Z_LIBC_SONAME,          strlen)
 #if defined(VGO_linux)

+STRLEN(VG_Z_LIBC_SONAME,          __GI_strlen)

 STRLEN(VG_Z_LD_LINUX_SO_2,        strlen)
 STRLEN(VG_Z_LD_LINUX_X86_64_SO_2, strlen)
 STRLEN(VG_Z_LD_SO_1,              strlen)
 #endif
 
 
 STRLEN(VG_Z_LD_LINUX_SO_2,        strlen)
 STRLEN(VG_Z_LD_LINUX_X86_64_SO_2, strlen)
 STRLEN(VG_Z_LD_SO_1,              strlen)
 #endif
 
 

+#define STRCPY(soname, fnname) \
+   char* VG_REPLACE_FUNCTION_ZU(soname, fnname) ( char* dst, const char* src ); \
+   char* VG_REPLACE_FUNCTION_ZU(soname, fnname) ( char* dst, const char* src ) \
+   { \
+      Char* dst_orig = dst; \
+      \
+      while (*src) *dst++ = *src++; \
+      *dst = 0; \
+      \
+      return dst_orig; \
+   }
+
+STRCPY(VG_Z_LIBC_SONAME, strcpy)
+#if defined(VGO_linux)
+STRCPY(VG_Z_LIBC_SONAME, __GI_strcpy)
+#elif defined(VGO_darwin)
+STRCPY(VG_Z_DYLD,        strcpy)
+#endif
+
+
+#define STRNCMP(soname, fnname) \
+   int VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+          ( const char* s1, const char* s2, SizeT nmax ); \
+   int VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+          ( const char* s1, const char* s2, SizeT nmax ) \
+   { \
+      SizeT n = 0; \
+      while (True) { \
+         if (n >= nmax) return 0; \
+         if (*s1 == 0 && *s2 == 0) return 0; \
+         if (*s1 == 0) return -1; \
+         if (*s2 == 0) return 1; \
+         \
+         if (*(unsigned char*)s1 < *(unsigned char*)s2) return -1; \
+         if (*(unsigned char*)s1 > *(unsigned char*)s2) return 1; \
+         \
+         s1++; s2++; n++; \
+      } \
+   }
+
+STRNCMP(VG_Z_LIBC_SONAME, strncmp)
+#if defined(VGO_linux)
+STRNCMP(VG_Z_LIBC_SONAME, __GI_strncmp)
+#elif defined(VGO_darwin)
+STRNCMP(VG_Z_DYLD,        strncmp)
+#endif
+
+

 #define STRCMP(soname, fnname) \
    int VG_REPLACE_FUNCTION_ZU(soname,fnname) \
           ( const char* s1, const char* s2 ); \
 #define STRCMP(soname, fnname) \
    int VG_REPLACE_FUNCTION_ZU(soname,fnname) \
           ( const char* s1, const char* s2 ); \


@@ -154,6 +203,7 @@ STRLEN(VG_Z_LD_SO_1,              strlen)
 
 STRCMP(VG_Z_LIBC_SONAME,          strcmp)
 #if defined(VGO_linux)
 
 STRCMP(VG_Z_LIBC_SONAME,          strcmp)
 #if defined(VGO_linux)

+STRCMP(VG_Z_LIBC_SONAME,          __GI_strcmp)

 STRCMP(VG_Z_LD_LINUX_X86_64_SO_2, strcmp)
 STRCMP(VG_Z_LD64_SO_1,            strcmp)
 #endif
 STRCMP(VG_Z_LD_LINUX_X86_64_SO_2, strcmp)
 STRCMP(VG_Z_LD64_SO_1,            strcmp)
 #endif


@@ -264,6 +314,85 @@ GLIBC232_RAWMEMCHR(VG_Z_LIBC_SONAME, __GI___rawmemchr)
 #endif
 
 
 #endif
 
 

+#define STRSTR(soname, fnname) \
+   void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* haystack, void* needle); \
+   void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* haystack, void* needle) \
+   { \
+      UChar* h = (UChar*)haystack; \
+      UChar* n = (UChar*)needle; \
+      \
+      /* find the length of n, not including terminating zero */ \
+      UWord nlen = 0; \
+      while (n[nlen]) nlen++; \
+      \
+      /* if n is the empty string, match immediately. */ \
+      if (nlen == 0) return h; \
+      \
+      /* assert(nlen >= 1); */ \
+      UChar n0 = n[0]; \
+      \
+      while (1) { \
+         UChar hh = *h; \
+         if (hh == 0) return NULL; \
+         if (hh != n0) { h++; continue; } \
+         \
+         UWord i; \
+         for (i = 0; i < nlen; i++) { \
+            if (n[i] != h[i]) \
+               break; \
+         } \
+         /* assert(i >= 0 && i <= nlen); */ \
+         if (i == nlen) \
+            return h; \
+         \
+         h++; \
+      } \
+   }
+
+#if defined(VGO_linux)
+STRSTR(VG_Z_LIBC_SONAME,          strstr)
+#endif
+
+
+#define STRPBRK(soname, fnname) \
+   void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* sV, void* acceptV); \
+   void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* sV, void* acceptV) \
+   { \
+      UChar* s = (UChar*)sV; \
+      UChar* accept = (UChar*)acceptV; \
+      \
+      /*  find the length of 'accept', not including terminating zero */ \
+      UWord nacc = 0; \
+      while (accept[nacc]) nacc++; \
+      \
+      /* if n is the empty string, fail immediately. */ \
+      if (nacc == 0) return NULL; \
+      \
+      /* assert(nacc >= 1); */ \
+      while (1) { \
+         UWord i; \
+         UChar sc = *s; \
+         if (sc == 0) \
+            break; \
+         for (i = 0; i < nacc; i++) { \
+            if (sc == accept[i]) \
+               return s; \
+         } \
+         s++; \
+      } \
+      \
+      return NULL; \
+   }
+
+#if defined(VGO_linux)
+STRPBRK(VG_Z_LIBC_SONAME,          strpbrk)
+#endif
+
+

 /*--------------------------------------------------------------------*/
 /*--- end                                          pc_intercepts.c ---*/
 /*--------------------------------------------------------------------*/
 /*--------------------------------------------------------------------*/
 /*--- end                                          pc_intercepts.c ---*/
 /*--------------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/h_main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/h_main.c
index d92ee209ac217512f52590ef11294085e9683946..03b2bfa76605e924a3d2c15a14d44d97fe033845 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/h_main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/h_main.c
@@ -2330,6 +2330,9 @@ static void setup_post_syscall_table ( void )
       ADD(0, __NR_getuid32);
 #     endif
       ADD(0, __NR_getxattr);
       ADD(0, __NR_getuid32);
 #     endif
       ADD(0, __NR_getxattr);

+#     if defined(__NR_ioperm)
+      ADD(0, __NR_ioperm);
+#     endif

       ADD(0, __NR_inotify_add_watch);
       ADD(0, __NR_inotify_init);
 #     if defined(__NR_inotify_init1)
       ADD(0, __NR_inotify_add_watch);
       ADD(0, __NR_inotify_init);
 #     if defined(__NR_inotify_init1)


@@ -2399,6 +2402,7 @@ static void setup_post_syscall_table ( void )
 #     if defined(__NR_semop)
       ADD(0, __NR_semop);
 #     endif
 #     if defined(__NR_semop)
       ADD(0, __NR_semop);
 #     endif

+      ADD(0, __NR_sendfile);

 #     if defined(__NR_sendto)
       ADD(0, __NR_sendto);
 #     endif
 #     if defined(__NR_sendto)
       ADD(0, __NR_sendto);
 #     endif


@@ -2410,9 +2414,11 @@ static void setup_post_syscall_table ( void )
       ADD(0, __NR_set_thread_area);
 #     endif
       ADD(0, __NR_set_tid_address);
       ADD(0, __NR_set_thread_area);
 #     endif
       ADD(0, __NR_set_tid_address);

+      ADD(0, __NR_setgid);

       ADD(0, __NR_setfsgid);
       ADD(0, __NR_setfsuid);
       ADD(0, __NR_setgid);
       ADD(0, __NR_setfsgid);
       ADD(0, __NR_setfsuid);
       ADD(0, __NR_setgid);

+      ADD(0, __NR_setgroups);

       ADD(0, __NR_setitimer);
       ADD(0, __NR_setpgid);
       ADD(0, __NR_setpriority);
       ADD(0, __NR_setitimer);
       ADD(0, __NR_setpgid);
       ADD(0, __NR_setpriority);


@@ -4335,7 +4341,7 @@ void instrument_arithop ( PCEnv* pce,
          case Iop_CmpEQ32x2: case Iop_CmpEQ16x4: case Iop_CmpGT8Sx8:
          case Iop_CmpGT32Sx2: case Iop_CmpGT16Sx4: case Iop_MulHi16Sx4:
          case Iop_Mul16x4: case Iop_ShlN32x2: case Iop_ShlN16x4:
          case Iop_CmpEQ32x2: case Iop_CmpEQ16x4: case Iop_CmpGT8Sx8:
          case Iop_CmpGT32Sx2: case Iop_CmpGT16Sx4: case Iop_MulHi16Sx4:
          case Iop_Mul16x4: case Iop_ShlN32x2: case Iop_ShlN16x4:

-         case Iop_SarN32x2: case Iop_SarN16x4: case Iop_ShrN32x2:
+         case Iop_SarN32x2: case Iop_SarN16x4: case Iop_ShrN32x2: case Iop_ShrN8x8:

          case Iop_ShrN16x4: case Iop_Sub8x8: case Iop_Sub32x2:
          case Iop_QSub8Sx8: case Iop_QSub16Sx4: case Iop_QSub8Ux8:
          case Iop_QSub16Ux4: case Iop_Sub16x4: case Iop_InterleaveHI8x8:
          case Iop_ShrN16x4: case Iop_Sub8x8: case Iop_Sub32x2:
          case Iop_QSub8Sx8: case Iop_QSub16Sx4: case Iop_QSub8Ux8:
          case Iop_QSub16Ux4: case Iop_Sub16x4: case Iop_InterleaveHI8x8:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/tests/Makefile.in
index dc1a39820d7242dd33b00270fcafa1bbb5fa93fe..0e77fe99a301e0e7385f6eb599854a6a67f35274 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/exp-ptrcheck/tests/Makefile.in
@@ -254,6 +254,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -288,14 +289,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -378,7 +383,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -437,7 +444,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -452,8 +459,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/glibc-2.X-drd.supp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/glibc-2.X-drd.supp
index 0711a69accb20bee79bc13226b069d91d3899bd5..98b594b64eb56bf6314716097ff1138fb1742370 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/glibc-2.X-drd.supp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/glibc-2.X-drd.supp
@@ -41,6 +41,14 @@
 #    fun:_ZNSsC1ERKSs
 # }
 
 #    fun:_ZNSsC1ERKSs
 # }
 

+{
+   drd-libstdc++-cxa_guard_release
+   drd:CondErr
+   fun:pthread_cond_broadcast@*
+   fun:__cxa_guard_release
+}
+
+

 #
 # Suppression patterns for libpthread.
 #
 #
 # Suppression patterns for libpthread.
 #


@@ -63,12 +71,22 @@
    ...
    fun:__deallocate_stack
 }
    ...
    fun:__deallocate_stack
 }

+{
+   drd-libpthread-__free_stacks
+   drd:ConflictingAccess
+   fun:__free_stacks
+}

 {
    drd-libpthread-__free_tcb
    drd:ConflictingAccess
    ...
    fun:__free_tcb
 }
 {
    drd-libpthread-__free_tcb
    drd:ConflictingAccess
    ...
    fun:__free_tcb
 }

+{
+   drd-libpthread-__nptl_deallocate_tsd
+   drd:ConflictingAccess
+   fun:__nptl_deallocate_tsd
+}

 {
    drd-libpthread-pthread_detach
    drd:ConflictingAccess
 {
    drd-libpthread-pthread_detach
    drd:ConflictingAccess


@@ -81,12 +99,23 @@
    ...
    fun:_Unwind_ForcedUnwind
 }
    ...
    fun:_Unwind_ForcedUnwind
 }

+{
+   drd-libpthread-_Unwind_GetCFA
+   drd:ConflictingAccess
+   fun:_Unwind_GetCFA
+}

 {
    drd-libpthread-_Unwind_Resume
    drd:ConflictingAccess
    ...
    fun:_Unwind_Resume
 }
 {
    drd-libpthread-_Unwind_Resume
    drd:ConflictingAccess
    ...
    fun:_Unwind_Resume
 }

+{
+   drd-libpthread-?
+   drd:ConflictingAccess
+   obj:/lib/libgcc_s.so.1
+   obj:/lib/libpthread-2.11.2.so
+}

 {
    drd-libpthread-nanosleep
    drd:ConflictingAccess
 {
    drd-libpthread-nanosleep
    drd:ConflictingAccess


@@ -146,6 +175,7 @@
 {
    drd-libglib-access-g_threads_got_initialized
    drd:ConflictingAccess
 {
    drd-libglib-access-g_threads_got_initialized
    drd:ConflictingAccess

+   ...

    fun:_ZN27QEventDispatcherGlibPrivateC1EP13_GMainContext
    fun:_ZN20QEventDispatcherGlibC1EP7QObject
    obj:/usr/lib*/libQtCore.so.4.*
    fun:_ZN27QEventDispatcherGlibPrivateC1EP13_GMainContext
    fun:_ZN20QEventDispatcherGlibC1EP7QObject
    obj:/usr/lib*/libQtCore.so.4.*


@@ -187,7 +217,6 @@
    drd-libQtCore-deref-that-calls-QThreadData-destructor
    drd:ConflictingAccess
    fun:_ZN11QThreadDataD1Ev
    drd-libQtCore-deref-that-calls-QThreadData-destructor
    drd:ConflictingAccess
    fun:_ZN11QThreadDataD1Ev

-   fun:_ZN11QThreadData5derefEv

    obj:/usr/lib*/libQtCore.so.4.*
 }
 {
    obj:/usr/lib*/libQtCore.so.4.*
 }
 {


@@ -220,14 +249,20 @@
    drd:ConflictingAccess
    fun:_ZN10QMutexPool3getEPKv
 }
    drd:ConflictingAccess
    fun:_ZN10QMutexPool3getEPKv
 }

+{
+   drd-libQtCore-qt_gettime_is_monotonic()
+   drd:ConflictingAccess
+   fun:_Z23qt_gettime_is_monotonicv
+}

 
 #
 # Suppression patterns for libboost.
 #
 
 # Suppress the races on boost::once_flag::epoch and on
 
 #
 # Suppression patterns for libboost.
 #
 
 # Suppress the races on boost::once_flag::epoch and on

-# boost::detail::once_global_epoch. See also the source file
-# boost/thread/pthread/once.hpp in the Boost source tree.
+# boost::detail::this_thread_epoch. See also the source file
+# boost/thread/pthread/once.hpp in the Boost source tree
+# (https://svn.boost.org/trac/boost/browser/trunk/boost/thread/pthread/once.hpp).

 {
    drd-libboost-boost::call_once<void (*)()>(boost::once_flag&, void (*)())
    drd:ConflictingAccess
 {
    drd-libboost-boost::call_once<void (*)()>(boost::once_flag&, void (*)())
    drd:ConflictingAccess


@@ -239,9 +274,18 @@
    drd:ConflictingAccess
    fun:_ZN5boost6detail25get_once_per_thread_epochEv
 }
    drd:ConflictingAccess
    fun:_ZN5boost6detail25get_once_per_thread_epochEv
 }

+# Suppress the race reports on boost::detail::current_thread_tls_key. See also
+# https://svn.boost.org/trac/boost/ticket/3526 for more information about why
+# the access pattern of current_thread_tls_key is safe.

 {
    drd-libboost-boost::detail::get_current_thread_data()
    drd:ConflictingAccess
    ...
    fun:_ZN5boost6detail23get_current_thread_dataEv
 }
 {
    drd-libboost-boost::detail::get_current_thread_data()
    drd:ConflictingAccess
    ...
    fun:_ZN5boost6detail23get_current_thread_dataEv
 }

+{
+   drd-libboost-boost::detail::set_current_thread_data(boost::detail::thread_data_base*)
+   drd:ConflictingAccess
+   ...
+   fun:_ZN5boost6detail23set_current_thread_dataEPNS0_16thread_data_baseE
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/glibc-2.X.supp.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/glibc-2.X.supp.in
index ef85328b44d5f16c69bcae85f6a6bf016ba8c3c8..935bd747f6034442be10d23df107f0edad3cef8f 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/glibc-2.X.supp.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/glibc-2.X.supp.in
@@ -228,3 +228,11 @@
    obj:/lib/libpthread-0.10.so
    fun:pthread_create
 }
    obj:/lib/libpthread-0.10.so
    fun:pthread_create
 }

+
+##----------------------------------------------------------------------##
+# Ubuntu 10.04 on ARM (Thumb).  Not sure why this is necessary.
+{
+   U1004-ARM-_dl_relocate_object
+   Memcheck:Cond
+   fun:_dl_relocate_object
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/Makefile.am
index 795266a1a73fdb71ec32cebe048dad738b52b310..300e25b495d4f1be5ac56dbb7dfff2a06a19e6b2 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/Makefile.am
@@ -35,7 +35,8 @@ HELGRIND_SOURCES_COMMON = \
        hg_wordset.c \
        libhb_core.c
 
        hg_wordset.c \
        libhb_core.c
 

-helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = $(HELGRIND_SOURCES_COMMON)
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = \
+       $(HELGRIND_SOURCES_COMMON)

 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \


@@ -46,8 +47,16 @@ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 if VGCONF_HAVE_PLATFORM_SEC

-helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = $(HELGRIND_SOURCES_COMMON)
+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
+       $(HELGRIND_SOURCES_COMMON)

 helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \
 helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \


@@ -58,6 +67,12 @@ helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 #----------------------------------------------------------------------------
 endif
 
 #----------------------------------------------------------------------------


@@ -86,6 +101,7 @@ vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
 vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+

 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = \
        $(VGPRELOAD_HELGRIND_SOURCES_COMMON)
 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = \
        $(VGPRELOAD_HELGRIND_SOURCES_COMMON)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/Makefile.in
index 1fe1caf3837168e26b9a9a02a313862f01ded522..6f5b29c26d9bf1047228d93b3562454aad31d0c8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/Makefile.in
@@ -45,29 +45,13 @@ host_triplet = @host@
 DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
        $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
 DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
        $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)
 noinst_PROGRAMS = helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_helgrind-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_14 = vgpreload_helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = vgpreload_helgrind-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so

 subdir = helgrind
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = helgrind
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -90,10 +74,6 @@ am__objects_1 =  \
 am_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
 am_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) \
-       -o $@

 am__helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = hg_basics.c \
        hg_errors.c hg_lock_n_thread.c hg_main.c hg_wordset.c \
        libhb_core.c
 am__helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = hg_basics.c \
        hg_errors.c hg_lock_n_thread.c hg_main.c hg_wordset.c \
        libhb_core.c


@@ -108,10 +88,6 @@ am__objects_2 =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) \
-       -o $@

 am__objects_3 = vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.$(OBJEXT)
 am_vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =  \
        $(am__objects_3)
 am__objects_3 = vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-hg_intercepts.$(OBJEXT)
 am_vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =  \
        $(am__objects_3)


@@ -251,6 +227,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -285,14 +262,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -376,7 +357,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -435,7 +418,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -450,8 +433,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -514,37 +497,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -553,32 +536,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -680,7 +659,9 @@ HELGRIND_SOURCES_COMMON = \
        hg_wordset.c \
        libhb_core.c
 
        hg_wordset.c \
        libhb_core.c
 

-helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(HELGRIND_SOURCES_COMMON)
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+       $(HELGRIND_SOURCES_COMMON)
+

 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 


@@ -696,7 +677,16 @@ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(HELGRIND_SOURCES_COMMON)
+helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(HELGRIND_SOURCES_COMMON)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 


@@ -712,6 +702,13 @@ helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

+@VGCONF_HAVE_PLATFORM_SEC_TRUE@helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(helgrind_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+

 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 VGPRELOAD_HELGRIND_SOURCES_COMMON = hg_intercepts.c
 vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 VGPRELOAD_HELGRIND_SOURCES_COMMON = hg_intercepts.c
 vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \


@@ -746,8 +743,7 @@ vgpreload_helgrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -1242,16 +1238,14 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(pkgincludedir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done
 all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(pkgincludedir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -1268,7 +1262,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -1277,7 +1270,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1348,9 +1340,8 @@ ps-am:
 
 uninstall-am: uninstall-pkgincludeHEADERS
 
 
 uninstall-am: uninstall-pkgincludeHEADERS
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1433,65 +1424,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_errors.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_errors.c
index a1ece966df8ab6cca1054b9ed460d233225b3f76..497fe58f0124173f9dc10c32b529758c4f3ffc25 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_errors.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_errors.c
@@ -222,8 +222,10 @@ typedef
             ExeContext* after_ec;
          } LockOrder;
          struct {
             ExeContext* after_ec;
          } LockOrder;
          struct {

-            Thread* thr;
-            HChar*  errstr; /* persistent, in tool-arena */
+            Thread*     thr;
+            HChar*      errstr; /* persistent, in tool-arena */
+            HChar*      auxstr; /* optional, persistent, in tool-arena */
+            ExeContext* auxctx; /* optional */

          } Misc;
       } XE;
    }
          } Misc;
       } XE;
    }


@@ -507,7 +509,8 @@ void HG_(record_error_PthAPIerror) ( Thread* thr, HChar* fnname,
                             XE_PthAPIerror, 0, NULL, &xe );
 }
 
                             XE_PthAPIerror, 0, NULL, &xe );
 }
 

-void HG_(record_error_Misc) ( Thread* thr, HChar* errstr )
+void HG_(record_error_Misc_w_aux) ( Thread* thr, HChar* errstr,
+                                    HChar* auxstr, ExeContext* auxctx )

 {
    XError xe;
    tl_assert( HG_(is_sane_Thread)(thr) );
 {
    XError xe;
    tl_assert( HG_(is_sane_Thread)(thr) );


@@ -516,6 +519,8 @@ void HG_(record_error_Misc) ( Thread* thr, HChar* errstr )
    xe.tag = XE_Misc;
    xe.XE.Misc.thr    = thr;
    xe.XE.Misc.errstr = string_table_strdup(errstr);
    xe.tag = XE_Misc;
    xe.XE.Misc.thr    = thr;
    xe.XE.Misc.errstr = string_table_strdup(errstr);

+   xe.XE.Misc.auxstr = auxstr ? string_table_strdup(auxstr) : NULL;
+   xe.XE.Misc.auxctx = auxctx;

    // FIXME: tid vs thr
    tl_assert( HG_(is_sane_ThreadId)(thr->coretid) );
    tl_assert( thr->coretid != VG_INVALID_THREADID );
    // FIXME: tid vs thr
    tl_assert( HG_(is_sane_ThreadId)(thr->coretid) );
    tl_assert( thr->coretid != VG_INVALID_THREADID );


@@ -523,6 +528,11 @@ void HG_(record_error_Misc) ( Thread* thr, HChar* errstr )
                             XE_Misc, 0, NULL, &xe );
 }
 
                             XE_Misc, 0, NULL, &xe );
 }
 

+void HG_(record_error_Misc) ( Thread* thr, HChar* errstr )
+{
+   HG_(record_error_Misc_w_aux)(thr, errstr, NULL, NULL);
+}
+

 Bool HG_(eq_Error) ( VgRes not_used, Error* e1, Error* e2 )
 {
    XError *xe1, *xe2;
 Bool HG_(eq_Error) ( VgRes not_used, Error* e1, Error* e2 )
 {
    XError *xe1, *xe2;


@@ -716,6 +726,11 @@ void HG_(pp_Error) ( Error* err )
                (Int)xe->XE.Misc.thr->errmsg_index );
          emit( "  </xwhat>\n" );
          VG_(pp_ExeContext)( VG_(get_error_where)(err) );
                (Int)xe->XE.Misc.thr->errmsg_index );
          emit( "  </xwhat>\n" );
          VG_(pp_ExeContext)( VG_(get_error_where)(err) );

+         if (xe->XE.Misc.auxstr) {
+            emit("  <auxwhat>%s</auxwhat>\n", xe->XE.Misc.auxstr);
+            if (xe->XE.Misc.auxctx)
+               VG_(pp_ExeContext)( xe->XE.Misc.auxctx );
+         }

 
       } else {
 
 
       } else {
 


@@ -723,6 +738,11 @@ void HG_(pp_Error) ( Error* err )
                (Int)xe->XE.Misc.thr->errmsg_index,
                xe->XE.Misc.errstr );
          VG_(pp_ExeContext)( VG_(get_error_where)(err) );
                (Int)xe->XE.Misc.thr->errmsg_index,
                xe->XE.Misc.errstr );
          VG_(pp_ExeContext)( VG_(get_error_where)(err) );

+         if (xe->XE.Misc.auxstr) {
+            emit(" %s\n", xe->XE.Misc.auxstr);
+            if (xe->XE.Misc.auxctx)
+               VG_(pp_ExeContext)( xe->XE.Misc.auxctx );
+         }

 
       }
       break;
 
       }
       break;

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_errors.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_errors.h
index 3714346497cd4b52fa18f477ad8f568fea963f82..2a19fe36bb3499bf83944bbc195948d74ac91fd0 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_errors.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_errors.h
@@ -59,7 +59,10 @@ void HG_(record_error_UnlockBogus)    ( Thread*, Addr );
 void HG_(record_error_PthAPIerror)    ( Thread*, HChar*, Word, HChar* );
 void HG_(record_error_LockOrder)      ( Thread*, Addr, Addr,
                                         ExeContext*, ExeContext* );
 void HG_(record_error_PthAPIerror)    ( Thread*, HChar*, Word, HChar* );
 void HG_(record_error_LockOrder)      ( Thread*, Addr, Addr,
                                         ExeContext*, ExeContext* );

-void HG_(record_error_Misc)           ( Thread*, HChar* );
+void HG_(record_error_Misc_w_aux)     ( Thread*, HChar* errstr,
+                                        HChar* auxstr, ExeContext* auxctx );
+void HG_(record_error_Misc)           ( Thread* thr, HChar* errstr );
+

 
 /* Statistics pertaining to error management. */
 extern ULong HG_(stats__LockN_to_P_queries);
 
 /* Statistics pertaining to error management. */
 extern ULong HG_(stats__LockN_to_P_queries);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_main.c
index ab9da5d0deae6c715a69a3f6c81ee76a58ebc0ba..1be4f1382b37e854eb9cf592965e31c4d81f2022 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/hg_main.c
@@ -1980,8 +1980,14 @@ static void evh__HG_PTHREAD_MUTEX_LOCK_PRE ( ThreadId tid,
          this is a real lock operation (not a speculative "tryLock"
          kind of thing).  Duh.  Deadlock coming up; but at least
          produce an error message. */
          this is a real lock operation (not a speculative "tryLock"
          kind of thing).  Duh.  Deadlock coming up; but at least
          produce an error message. */

-      HG_(record_error_Misc)( thr, "Attempt to re-lock a "
-                                   "non-recursive lock I already hold" );
+      HChar* errstr = "Attempt to re-lock a "
+                      "non-recursive lock I already hold";
+      HChar* auxstr = "Lock was previously acquired";
+      if (lk->acquired_at) {
+         HG_(record_error_Misc_w_aux)( thr, errstr, auxstr, lk->acquired_at );
+      } else {
+         HG_(record_error_Misc)( thr, errstr );
+      }

    }
 }
 
    }
 }
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/libhb_core.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/libhb_core.c
index 004ce69fbfff0561afcfe46c91807ac894dc830d..ce3f889fb7496e12e65565a0200251e79689165e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/libhb_core.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/libhb_core.c
@@ -5711,7 +5711,8 @@ void libhb_so_recv ( Thr* thr, SO* so, Bool strong_recv )
          //VtsID__rcinc(thr->viW);
       }
 
          //VtsID__rcinc(thr->viW);
       }
 

-      Filter__clear(thr->filter, "libhb_so_recv");
+      if (thr->filter)
+         Filter__clear(thr->filter, "libhb_so_recv");

       note_local_Kw_n_stack_for(thr);
 
       if (strong_recv) 
       note_local_Kw_n_stack_for(thr);
 
       if (strong_recv) 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/tests/Makefile.in
index eb01b57b89837e4db1bba524b4d47d5b36054467..630d77b64c37950ba748247d3f7215f2121084aa 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/helgrind/tests/Makefile.in
@@ -316,6 +316,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -350,14 +351,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -440,7 +445,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -499,7 +506,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -514,8 +521,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/Makefile.in
index 6f3cc2a8b2b29b4454605e41d3e2b4725abc5d08..8df74bbbe060929e266fff6afa3d8a335683fc5e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/Makefile.in
@@ -110,6 +110,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -144,14 +145,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_l4re.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_l4re.h
index 8eec5a01e14b1a23b17e9788373b8702e38d9d9d..8975c1e0e5bbefb74246d8730e4e60921782efe8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_l4re.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_l4re.h
@@ -99,7 +99,7 @@ EXTERN_C void vcap_init(void);
  * \param envp - old environment
  * \return pointer to new environment
  */
  * \param envp - old environment
  * \return pointer to new environment
  */

-void *l4re_vcap_modify_env(struct ume_auxv *envp);
+void *l4re_vcap_modify_env(struct ume_auxv *envp, Addr client_l4re_env_addr);

 
 extern void *client_env;
 extern unsigned int client_env_size;
 
 extern void *client_env;
 extern unsigned int client_env_size;

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_clientstate.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_clientstate.h
index 9431783f67cffed75c3eeb7452d15c2122e52686..81df4e5060ebc21f25d5687b4b257fbaef9ea928 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_clientstate.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_clientstate.h
@@ -60,7 +60,7 @@ extern Int VG_(args_for_valgrind_noexecpass);
 
 /* The name of the client executable, as specified on the command
    line. */
 
 /* The name of the client executable, as specified on the command
    line. */

-extern HChar* VG_(args_the_exename);
+extern const HChar* VG_(args_the_exename);

 
 
 #endif   // __PUB_TOOL_CLIENTSTATE_H
 
 
 #endif   // __PUB_TOOL_CLIENTSTATE_H

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_libcprint.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_libcprint.h
index c205515950cf27ebbc5107e2439079c11b49708e..1621851336d1253f475e20aa1960a1e552279b75 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_libcprint.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_libcprint.h
@@ -32,19 +32,9 @@
 #define __PUB_TOOL_LIBCPRINT_H
 
 /* ---------------------------------------------------------------------
 #define __PUB_TOOL_LIBCPRINT_H
 
 /* ---------------------------------------------------------------------

-   Basic printing
+   Formatting functions

    ------------------------------------------------------------------ */
 
    ------------------------------------------------------------------ */
 

-/* Note that they all output to the file descriptor given by the
-   --log-fd/--log-file/--log-socket argument, which defaults to 2
-   (stderr).  Hence no need for VG_(fprintf)().
-*/
-extern UInt VG_(printf)   ( const HChar *format, ... )
-                          PRINTF_CHECK(1, 2);
-
-extern UInt VG_(vprintf)  ( const HChar *format, va_list vargs )
-                          PRINTF_CHECK(1, 0);
-

 extern UInt VG_(sprintf)  ( Char* buf, const HChar* format, ... )
                           PRINTF_CHECK(2, 3);
 
 extern UInt VG_(sprintf)  ( Char* buf, const HChar* format, ... )
                           PRINTF_CHECK(2, 3);
 


@@ -59,65 +49,93 @@ extern UInt VG_(vsnprintf)( Char* buf, Int size,
                                        const HChar *format, va_list vargs )
                           PRINTF_CHECK(3, 0);
 
                                        const HChar *format, va_list vargs )
                           PRINTF_CHECK(3, 0);
 

-/* Yet another, totally general, version of vprintf, which hands all
-   output bytes to CHAR_SINK, passing it OPAQUE as the second arg. */
-extern void VG_(vcbprintf)( void(*char_sink)(HChar, void* opaque),
-                            void* opaque,
-                            const HChar* format, va_list vargs );
-
-/* These are the same as the non "_xml" versions above, except the
-   output goes on the selected XML output channel instead of the
-   normal one.
-*/
-extern UInt VG_(printf_xml)  ( const HChar *format, ... )
-                             PRINTF_CHECK(1, 2);
-
-extern UInt VG_(vprintf_xml) ( const HChar *format, va_list vargs )
-                             PRINTF_CHECK(1, 0);
-
-extern UInt VG_(printf_xml_no_f_c) ( const HChar *format, ... );
-

 // Percentify n/m with d decimal places.  Includes the '%' symbol at the end.
 // Right justifies in 'buf'.
 extern void VG_(percentify)(ULong n, ULong m, UInt d, Int n_buf, char buf[]);
 
 
 /* ---------------------------------------------------------------------
 // Percentify n/m with d decimal places.  Includes the '%' symbol at the end.
 // Right justifies in 'buf'.
 extern void VG_(percentify)(ULong n, ULong m, UInt d, Int n_buf, char buf[]);
 
 
 /* ---------------------------------------------------------------------

-   Messages for the user
+   Output-printing functions

    ------------------------------------------------------------------ */
 
    ------------------------------------------------------------------ */
 

+// Note that almost all output goes to the file descriptor given by the
+// --log-fd/--log-file/--log-socket argument, which defaults to 2 (stderr).
+// (Except that some text always goes to stdout/stderr at startup, and
+// debugging messages always go to stderr.)  Hence no need for
+// VG_(fprintf)().
+

 /* No, really.  I _am_ that strange. */
 #define OINK(nnn) VG_(message)(Vg_DebugMsg, "OINK %d\n",nnn)
 
 /* No, really.  I _am_ that strange. */
 #define OINK(nnn) VG_(message)(Vg_DebugMsg, "OINK %d\n",nnn)
 

-/* Print a message prefixed by "??<pid>?? "; '?' depends on the VgMsgKind.
+/* Print a message with a prefix that depends on the VgMsgKind.

    Should be used for all user output. */
 
 typedef
    Should be used for all user output. */
 
 typedef

-   enum { Vg_UserMsg,         /* '?' == '=' */
-          Vg_DebugMsg,        /* '?' == '-' */
-          Vg_DebugExtraMsg,   /* '?' == '+' */
-          Vg_ClientMsg        /* '?' == '*' */
+   enum {                 // Prefix
+      Vg_FailMsg,         // "valgrind:"
+      Vg_UserMsg,         // "==pid=="
+      Vg_DebugMsg,        // "--pid--"
+      Vg_ClientMsg        // "**pid**"

    }
    VgMsgKind;
 
    }
    VgMsgKind;
 

-/* Send a single-part message.  The format specification may contain
-   any ISO C format specifier or %t.  No attempt is made to let the
-   compiler verify consistency of the format string and the argument
-   list. */
+// These print output that isn't prefixed with anything, and should be
+// used in very few cases, such as printing usage messages.
+extern UInt VG_(printf)   ( const HChar *format, ... )
+                          PRINTF_CHECK(1, 2);
+extern UInt VG_(vprintf)  ( const HChar *format, va_list vargs )
+                          PRINTF_CHECK(1, 0);
+
+// The "_no_f_c" functions here are just like their non-"_no_f_c" counterparts
+// but without the PRINTF_CHECK, so they can be used with our non-standard %t
+// format specifier.
+
+// These are the same as the non "_xml" versions above, except the
+// output goes on the selected XML output channel instead of the
+// normal one.
+extern UInt VG_(printf_xml)  ( const HChar *format, ... )
+                             PRINTF_CHECK(1, 2);
+
+extern UInt VG_(vprintf_xml) ( const HChar *format, va_list vargs )
+                             PRINTF_CHECK(1, 0);
+
+extern UInt VG_(printf_xml_no_f_c) ( const HChar *format, ... );
+
+/* Yet another, totally general, version of vprintf, which hands all
+   output bytes to CHAR_SINK, passing it OPAQUE as the second arg. */
+extern void VG_(vcbprintf)( void(*char_sink)(HChar, void* opaque),
+                            void* opaque,
+                            const HChar* format, va_list vargs );
+

 extern UInt VG_(message_no_f_c)( VgMsgKind kind, const HChar* format, ... );
 extern UInt VG_(message_no_f_c)( VgMsgKind kind, const HChar* format, ... );

-/* Send a single-part message.  The format specification may contain
-   any ISO C format specifier. The gcc compiler will verify
-   consistency of the format string and the argument list. */

 extern UInt VG_(message)( VgMsgKind kind, const HChar* format, ... )
 extern UInt VG_(message)( VgMsgKind kind, const HChar* format, ... )

-  PRINTF_CHECK(2, 3);
+   PRINTF_CHECK(2, 3);

 
 extern UInt VG_(vmessage)( VgMsgKind kind, const HChar* format, va_list vargs )
 
 extern UInt VG_(vmessage)( VgMsgKind kind, const HChar* format, va_list vargs )

-  PRINTF_CHECK(2, 0);
+   PRINTF_CHECK(2, 0);

 
 // Short-cuts for VG_(message)().
 
 // Short-cuts for VG_(message)().

+
+// This is used for messages printed due to start-up failures that occur
+// before the preamble is printed, eg. due a bad executable.
+extern UInt VG_(fmsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2);
+
+// This is used if an option was bad for some reason.  Note: don't use it just
+// because an option was unrecognised -- return 'False' from
+// VG_(tdict).tool_process_cmd_line_option) to indicate that -- use it if eg.
+// an option was given an inappropriate argument.  This function prints an
+// error message, then shuts down the entire system.
+__attribute__((noreturn))
+extern void VG_(fmsg_bad_option) ( HChar* opt, const HChar* format, ... )
+   PRINTF_CHECK(2, 3);
+
+// This is used for messages that are interesting to the user:  info about
+// their program (eg. preamble, tool error messages, postamble) or stuff they
+// requested.

 extern UInt VG_(umsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2);
 extern UInt VG_(umsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2);

+
+// This is used for debugging messages that are only of use to developers.

 extern UInt VG_(dmsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2);
 extern UInt VG_(dmsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2);

-extern UInt VG_(emsg)( const HChar* format, ... ) PRINTF_CHECK(1, 2);

 
 /* Flush any output cached by previous calls to VG_(message) et al. */
 extern void VG_(message_flush) ( void );
 
 /* Flush any output cached by previous calls to VG_(message) et al. */
 extern void VG_(message_flush) ( void );

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_libcproc.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_libcproc.h
index cd87912962293856e736caa7fd6aad4de67a9b5f..2770dda6a0c88c8adafcb5110a6145936f908f82 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_libcproc.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_libcproc.h
@@ -44,6 +44,10 @@ extern Char* VG_(getenv) ( Char* name );
 /* Path to all our library/aux files */
 extern const Char *VG_(libdir);
 
 /* Path to all our library/aux files */
 extern const Char *VG_(libdir);
 

+// The name of the LD_PRELOAD-equivalent variable.  It varies across
+// platforms.
+extern const Char* VG_(LD_PRELOAD_var_name);
+

 /* ---------------------------------------------------------------------
    Important syscalls
    ------------------------------------------------------------------ */
 /* ---------------------------------------------------------------------
    Important syscalls
    ------------------------------------------------------------------ */

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_machine.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_machine.h
index 0809a9c428f64b19049dadb7734268decabe1b95..2c9e19c749e21422c50ac676dc02632b431bd6d0 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_machine.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_machine.h
@@ -59,7 +59,7 @@
                                        // Supplement 1.7
 
 #elif defined(VGP_arm_linux)
                                        // Supplement 1.7
 
 #elif defined(VGP_arm_linux)

-#  define VG_MIN_INSTR_SZB          4
+#  define VG_MIN_INSTR_SZB          2

 #  define VG_MAX_INSTR_SZB          4 
 #  define VG_CLREQ_SZB             28
 #  define VG_STACK_REDZONE_SZB      0
 #  define VG_MAX_INSTR_SZB          4 
 #  define VG_CLREQ_SZB             28
 #  define VG_STACK_REDZONE_SZB      0


@@ -106,13 +106,11 @@
 #endif
 
 // Guest state accessors
 #endif
 
 // Guest state accessors

-extern Addr VG_(get_SP) ( ThreadId tid );
-extern Addr VG_(get_IP) ( ThreadId tid );
-extern Addr VG_(get_FP) ( ThreadId tid );
-extern Addr VG_(get_LR) ( ThreadId tid );
+// Are mostly in the core_ header.
+//  Only these two are available to tools.
+Addr VG_(get_IP) ( ThreadId tid );
+Addr VG_(get_SP) ( ThreadId tid );

 
 

-extern void VG_(set_SP) ( ThreadId tid, Addr sp );
-extern void VG_(set_IP) ( ThreadId tid, Addr ip );

 
 // For get/set, 'area' is where the asked-for guest state will be copied
 // into/from.  If shadowNo == 0, the real (non-shadow) guest state is
 
 // For get/set, 'area' is where the asked-for guest state will be copied
 // into/from.  If shadowNo == 0, the real (non-shadow) guest state is

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_options.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_options.h
index f28cc7097017ea1b3337467a937fbc648d38d278..7f85492518ba340acfa5ce2a9d4e90f53accb206 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_options.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_options.h
@@ -77,7 +77,7 @@
       Long n = VG_(strtoll10)( val, &s ); \
       (qq_var) = n; \
       /* Check for non-numeralness, or overflow. */ \
       Long n = VG_(strtoll10)( val, &s ); \
       (qq_var) = n; \
       /* Check for non-numeralness, or overflow. */ \

-      if ('\0' != s[0] || (qq_var) != n) VG_(err_bad_option)(qq_arg); \
+      if ('\0' != s[0] || (qq_var) != n) VG_(fmsg_bad_option)(qq_arg, ""); \

       True; \
      }) \
     )
       True; \
      }) \
     )


@@ -91,15 +91,16 @@
       Char* s; \
       Long n = VG_(strtoll##qq_base)( val, &s ); \
       (qq_var) = n; \
       Char* s; \
       Long n = VG_(strtoll##qq_base)( val, &s ); \
       (qq_var) = n; \

+      /* MMM: separate the two cases, and explain the problem;  likewise */ \
+      /* for all the other macros in this file. */ \

       /* Check for non-numeralness, or overflow. */ \
       /* Nb: it will overflow if qq_var is unsigned and qq_val is negative! */ \
       /* Check for non-numeralness, or overflow. */ \
       /* Nb: it will overflow if qq_var is unsigned and qq_val is negative! */ \

-      if ('\0' != s[0] || (qq_var) != n) VG_(err_bad_option)(qq_arg); \
+      if ('\0' != s[0] || (qq_var) != n) VG_(fmsg_bad_option)(qq_arg, ""); \

       /* Check bounds. */ \
       if ((qq_var) < (qq_lo) || (qq_var) > (qq_hi)) { \
       /* Check bounds. */ \
       if ((qq_var) < (qq_lo) || (qq_var) > (qq_hi)) { \

-         VG_(message)(Vg_UserMsg, \
-                      "'%s' argument must be between %lld and %lld\n", \
-                      (qq_option), (Long)(qq_lo), (Long)(qq_hi)); \
-         VG_(err_bad_option)(qq_arg); \
+         VG_(fmsg_bad_option)(qq_arg, \
+            "'%s' argument must be between %lld and %lld\n", \
+            (qq_option), (Long)(qq_lo), (Long)(qq_hi)); \

       } \
       True; \
      }) \
       } \
       True; \
      }) \


@@ -124,7 +125,7 @@
       double n = VG_(strtod)( val, &s ); \
       (qq_var) = n; \
       /* Check for non-numeralness */ \
       double n = VG_(strtod)( val, &s ); \
       (qq_var) = n; \
       /* Check for non-numeralness */ \

-      if ('\0' != s[0]) VG_(err_bad_option)(qq_arg); \
+      if ('\0' != s[0]) VG_(fmsg_bad_option)(qq_arg, ""); \

       True; \
      }) \
     )
       True; \
      }) \
     )


@@ -165,15 +166,6 @@ extern Int   VG_(clo_backtrace_size);
 extern Bool VG_(clo_show_below_main);
 
 
 extern Bool VG_(clo_show_below_main);
 
 

-/* Call this if a recognised option was bad for some reason.  Note:
-   don't use it just because an option was unrecognised -- return
-   'False' from VG_(tdict).tool_process_cmd_line_option) to indicate that --
-   use it if eg. an option was given an inappropriate argument.
-   This function prints an error message, then shuts down the entire system.
-   It returns a Bool so it can be used in the _CLO_ macros. */
-__attribute__((noreturn))
-extern void VG_(err_bad_option) ( Char* opt );
-

 /* Used to expand file names.  "option_name" is the option name, eg.
    "--log-file".  'format' is what follows, eg. "cachegrind.out.%p".  In
    'format': 
 /* Used to expand file names.  "option_name" is the option name, eg.
    "--log-file".  'format' is what follows, eg. "cachegrind.out.%p".  In
    'format': 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_tooliface.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_tooliface.h
index bb39097cf18217a56d21bc2dbc036da61729bd3e..ac346b9ec29a67b609f1cbd9656b844569aa500b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_tooliface.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/pub_tool_tooliface.h
@@ -374,10 +374,17 @@ extern void VG_(needs_superblock_discards) (
 
 /* Tool defines its own command line options? */
 extern void VG_(needs_command_line_options) (
 
 /* Tool defines its own command line options? */
 extern void VG_(needs_command_line_options) (

-   // Return True if option was recognised.  Presumably sets some state to
-   // record the option as well.  Nb: tools can assume that the argv will
-   // never disappear.  So they can, for example, store a pointer to a string
-   // within an option, rather than having to make a copy.
+   // Return True if option was recognised, False if it wasn't (but also see
+   // below).  Presumably sets some state to record the option as well.  
+   //
+   // Nb: tools can assume that the argv will never disappear.  So they can,
+   // for example, store a pointer to a string within an option, rather than
+   // having to make a copy.
+   //
+   // Options (and combinations of options) should be checked in this function
+   // if possible rather than in post_clo_init(), and if they are bad then
+   // VG_(fmsg_bad_option)() should be called.  This ensures that the
+   // messaging is consistent with command line option errors from the core.

    Bool (*process_cmd_line_option)(Char* argv),
 
    // Print out command line usage for options for normal tool operation.
    Bool (*process_cmd_line_option)(Char* argv),
 
    // Print out command line usage for options for normal tool operation.

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/valgrind.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/valgrind.h
index 0f5b376624533ac26529d1942ef6df2ffa8f698d..4f0f4de24b9ff223f6ec62103ab3365d1a446c10 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/valgrind.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/valgrind.h
@@ -112,6 +112,7 @@
 #undef PLAT_ppc32_aix5
 #undef PLAT_x86_darwin
 #undef PLAT_amd64_darwin
 #undef PLAT_ppc32_aix5
 #undef PLAT_x86_darwin
 #undef PLAT_amd64_darwin

+#undef PLAT_x86_win32

 #undef PLAT_x86_linux
 #undef PLAT_amd64_linux
 #undef PLAT_ppc32_linux
 #undef PLAT_x86_linux
 #undef PLAT_amd64_linux
 #undef PLAT_ppc32_linux


@@ -126,6 +127,8 @@
 #  define PLAT_x86_darwin 1
 #elif defined(__APPLE__) && defined(__x86_64__)
 #  define PLAT_amd64_darwin 1
 #  define PLAT_x86_darwin 1
 #elif defined(__APPLE__) && defined(__x86_64__)
 #  define PLAT_amd64_darwin 1

+#elif defined(__MINGW32__) || defined(__CYGWIN32__) || defined(_WIN32) && defined(_M_IX86)
+#  define PLAT_x86_win32 1

 #elif defined(__linux__) && defined(__i386__)
 #  define PLAT_x86_linux 1
 #elif defined(__linux__) && defined(__x86_64__)
 #elif defined(__linux__) && defined(__i386__)
 #  define PLAT_x86_linux 1
 #elif defined(__linux__) && defined(__x86_64__)


@@ -201,7 +204,7 @@
 
 /* ------------------------- x86-{linux,darwin} ---------------- */
 
 
 /* ------------------------- x86-{linux,darwin} ---------------- */
 

-#if defined(PLAT_x86_linux)  ||  defined(PLAT_x86_darwin)
+#if defined(PLAT_x86_linux)  ||  defined(PLAT_x86_darwin)  ||  defined(PLAT_x86_win32) && defined(__GNUC__)

 
 typedef
    struct { 
 
 typedef
    struct { 


@@ -251,7 +254,62 @@ typedef
                      __SPECIAL_INSTRUCTION_PREAMBLE               \
                      /* call-noredir *%EAX */                     \
                      "xchgl %%edx,%%edx\n\t"
                      __SPECIAL_INSTRUCTION_PREAMBLE               \
                      /* call-noredir *%EAX */                     \
                      "xchgl %%edx,%%edx\n\t"

-#endif /* PLAT_x86_linux || PLAT_x86_darwin */
+#endif /* PLAT_x86_linux || PLAT_x86_darwin || PLAT_x86_win32 && __GNUC__ */
+
+/* ------------------------- x86-Win32 ------------------------- */
+
+#if defined(PLAT_x86_win32) && !defined(__GNUC__)
+
+typedef
+   struct { 
+      unsigned int nraddr; /* where's the code? */
+   }
+   OrigFn;
+
+#if defined(_MSC_VER)
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE                            \
+                     __asm rol edi, 3  __asm rol edi, 13          \
+                     __asm rol edi, 29 __asm rol edi, 19
+
+#define VALGRIND_DO_CLIENT_REQUEST(                               \
+        _zzq_rlval, _zzq_default, _zzq_request,                   \
+        _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+  { volatile unsigned int _zzq_args[6];                           \
+    volatile unsigned int _zzq_result;                            \
+    _zzq_args[0] = (unsigned int)(ptrdiff_t)(_zzq_request);       \
+    _zzq_args[1] = (unsigned int)(ptrdiff_t)(_zzq_arg1);          \
+    _zzq_args[2] = (unsigned int)(ptrdiff_t)(_zzq_arg2);          \
+    _zzq_args[3] = (unsigned int)(ptrdiff_t)(_zzq_arg3);          \
+    _zzq_args[4] = (unsigned int)(ptrdiff_t)(_zzq_arg4);          \
+    _zzq_args[5] = (unsigned int)(ptrdiff_t)(_zzq_arg5);          \
+    __asm { __asm lea eax, _zzq_args __asm mov edx, _zzq_default  \
+            __SPECIAL_INSTRUCTION_PREAMBLE                        \
+            /* %EDX = client_request ( %EAX ) */                  \
+            __asm xchg ebx,ebx                                    \
+            __asm mov _zzq_result, edx                            \
+    }                                                             \
+    _zzq_rlval = _zzq_result;                                     \
+  }
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval)                       \
+  { volatile OrigFn* _zzq_orig = &(_zzq_rlval);                   \
+    volatile unsigned int __addr;                                 \
+    __asm { __SPECIAL_INSTRUCTION_PREAMBLE                        \
+            /* %EAX = guest_NRADDR */                             \
+            __asm xchg ecx,ecx                                    \
+            __asm mov __addr, eax                                 \
+    }                                                             \
+    _zzq_orig->nraddr = __addr;                                   \
+  }
+
+#define VALGRIND_CALL_NOREDIR_EAX ERROR
+
+#else
+#error Unsupported compiler.
+#endif
+
+#endif /* PLAT_x86_win32 */

 
 /* ------------------------ amd64-{linux,darwin} --------------- */
 
 
 /* ------------------------ amd64-{linux,darwin} --------------- */
 


@@ -4159,7 +4217,10 @@ typedef
           VG_USERREQ__STACK_CHANGE     = 0x1503,
 
           /* Wine support */
           VG_USERREQ__STACK_CHANGE     = 0x1503,
 
           /* Wine support */

-          VG_USERREQ__LOAD_PDB_DEBUGINFO = 0x1601
+          VG_USERREQ__LOAD_PDB_DEBUGINFO = 0x1601,
+
+          /* Querying of debug info. */
+          VG_USERREQ__MAP_IP_TO_SRCLOC = 0x1701

    } Vg_ClientRequest;
 
 #if !defined(__GNUC__)
    } Vg_ClientRequest;
 
 #if !defined(__GNUC__)


@@ -4170,6 +4231,7 @@ typedef
    is, 0 if running natively, 1 if running under Valgrind, 2 if
    running under Valgrind which is running under another Valgrind,
    etc. */
    is, 0 if running natively, 1 if running under Valgrind, 2 if
    running under Valgrind which is running under another Valgrind,
    etc. */

+#if !defined(_MSC_VER)

 #define RUNNING_ON_VALGRIND  __extension__                        \
    ({unsigned int _qzz_res;                                       \
     VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* if not */,          \
 #define RUNNING_ON_VALGRIND  __extension__                        \
    ({unsigned int _qzz_res;                                       \
     VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* if not */,          \


@@ -4177,6 +4239,17 @@ typedef
                                0, 0, 0, 0, 0);                    \
     _qzz_res;                                                     \
    })
                                0, 0, 0, 0, 0);                    \
     _qzz_res;                                                     \
    })

+#else /* defined(_MSC_VER) */
+#define RUNNING_ON_VALGRIND vg_RunningOnValgrind()
+static __inline unsigned int vg_RunningOnValgrind(void)
+{
+    unsigned int _qzz_res;
+    VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0 /* if not */,
+                               VG_USERREQ__RUNNING_ON_VALGRIND,
+                               0, 0, 0, 0, 0);
+    return _qzz_res;
+}
+#endif

 
 
 /* Discard translation of code in the range [_qzz_addr .. _qzz_addr +
 
 
 /* Discard translation of code in the range [_qzz_addr .. _qzz_addr +


@@ -4203,10 +4276,12 @@ typedef
 
 #else /* NVALGRIND */
 
 
 #else /* NVALGRIND */
 

+#if !defined(_MSC_VER)

 /* Modern GCC will optimize the static routine out if unused,
    and unused attribute will shut down warnings about it.  */
 static int VALGRIND_PRINTF(const char *format, ...)
    __attribute__((format(__printf__, 1, 2), __unused__));
 /* Modern GCC will optimize the static routine out if unused,
    and unused attribute will shut down warnings about it.  */
 static int VALGRIND_PRINTF(const char *format, ...)
    __attribute__((format(__printf__, 1, 2), __unused__));

+#endif

 static int
 VALGRIND_PRINTF(const char *format, ...)
 {
 static int
 VALGRIND_PRINTF(const char *format, ...)
 {


@@ -4222,8 +4297,10 @@ VALGRIND_PRINTF(const char *format, ...)
    return (int)_qzz_res;
 }
 
    return (int)_qzz_res;
 }
 

+#if !defined(_MSC_VER)

 static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
    __attribute__((format(__printf__, 1, 2), __unused__));
 static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
    __attribute__((format(__printf__, 1, 2), __unused__));

+#endif

 static int
 VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
 {
 static int
 VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
 {


@@ -4524,6 +4601,17 @@ VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
                                fd, ptr, total_size, delta, 0);    \
    }
 
                                fd, ptr, total_size, delta, 0);    \
    }
 

+/* Map a code address to a source file name and line number.  buf64
+   must point to a 64-byte buffer in the caller's address space.  The
+   result will be dumped in there and is guaranteed to be zero
+   terminated.  If no info is found, the first byte is set to zero. */
+#define VALGRIND_MAP_IP_TO_SRCLOC(addr, buf64)                    \
+   {unsigned int _qzz_res;                                        \
+    VALGRIND_DO_CLIENT_REQUEST(_qzz_res, 0,                       \
+                               VG_USERREQ__MAP_IP_TO_SRCLOC,      \
+                               addr, buf64, 0, 0, 0);             \
+   }
+

 
 #undef PLAT_x86_linux
 #undef PLAT_amd64_linux
 
 #undef PLAT_x86_linux
 #undef PLAT_amd64_linux

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-arm-linux.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-arm-linux.h
index ab745bbea8bede2ddd2e671065d642996b9a279c..65da4e037752a7d45e35354160d7472ee4325c94 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-arm-linux.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-arm-linux.h
@@ -474,13 +474,6 @@ struct vki_termios {
         ((nr)   << _VKI_IOC_NRSHIFT) | \
         ((size) << _VKI_IOC_SIZESHIFT))
 
         ((nr)   << _VKI_IOC_NRSHIFT) | \
         ((size) << _VKI_IOC_SIZESHIFT))
 

-/* provoke compile error for invalid uses of size argument */
-#define _VKI_IOC_TYPECHECK(t) \
-       ((sizeof(t) == sizeof(t[1]) && \
-         sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) \
-        ? sizeof(t) \
-        : /*cause gcc to complain about division by zero*/(1/0) )
-

 /* used to create numbers */
 #define _VKI_IO(type,nr)       _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
 #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size)))
 /* used to create numbers */
 #define _VKI_IO(type,nr)       _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
 #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size)))

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-darwin.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-darwin.h
index 06d9118082d5cca01ceb4a3875de541353836b02..e1663b8b0e65c4dcada7ea8de7911d4f173b7702 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-darwin.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-darwin.h
@@ -792,6 +792,11 @@ typedef
 typedef struct eventreq vki_eventreq;
 
 
 typedef struct eventreq vki_eventreq;
 
 

+#include <sys/acl.h>
+
+#define vki_kauth_filesec kauth_filesec
+
+

 #include <sys/ptrace.h>
 
 #define VKI_PTRACE_TRACEME   PT_TRACE_ME
 #include <sys/ptrace.h>
 
 #define VKI_PTRACE_TRACEME   PT_TRACE_ME


@@ -1021,6 +1026,10 @@ struct ByteRangeLockPB2
 #define        VKI_A_GETPINFO_ADDR     A_GETPINFO_ADDR 
 #define        VKI_A_GETKAUDIT A_GETKAUDIT     
 #define        VKI_A_SETKAUDIT A_SETKAUDIT     
 #define        VKI_A_GETPINFO_ADDR     A_GETPINFO_ADDR 
 #define        VKI_A_GETKAUDIT A_GETKAUDIT     
 #define        VKI_A_SETKAUDIT A_SETKAUDIT     

+#if DARWIN_VERS >= DARWIN_10_6
+#define VKI_A_SENDTRIGGER A_SENDTRIGGER
+#define VKI_A_GETSINFO_ADDR A_GETSINFO_ADDR
+#endif

 
 
 #include <sys/aio.h>
 
 
 #include <sys/aio.h>

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-linux.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-linux.h
index 395a059da25a6bc46dcb94e892634826df3435aa..beff378b3140a14357bc157b35900d3cbef9cf9e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-linux.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-linux.h
@@ -93,6 +93,34 @@
 #  error Unknown platform
 #endif
 
 #  error Unknown platform
 #endif
 

+//----------------------------------------------------------------------
+// VKI_STATIC_ASSERT(). Inspired by BUILD_BUG_ON() from
+// linux-2.6.34/include/linux/kernel.h
+//----------------------------------------------------------------------
+
+/*
+ * Evaluates to zero if 'expr' is true and forces a compilation error if
+ * 'expr' is false. Can be used in a context where no comma expressions
+ * are allowed.
+ */
+#ifdef __cplusplus
+template <bool b> struct vki_static_assert { int m_bitfield:(2*b-1); };
+#define VKI_STATIC_ASSERT(expr)                         \
+    (sizeof(vki_static_assert<(expr)>) - sizeof(int))
+#else
+#define VKI_STATIC_ASSERT(expr) (sizeof(struct { int:-!(expr); }))
+#endif
+
+//----------------------------------------------------------------------
+// Based on _IOC_TYPECHECK() from linux-2.6.34/asm-generic/ioctl.h
+//----------------------------------------------------------------------
+
+/* provoke compile error for invalid uses of size argument */
+#define _VKI_IOC_TYPECHECK(t)                                           \
+    (VKI_STATIC_ASSERT((sizeof(t) == sizeof(t[1])                       \
+                        && sizeof(t) < (1 << _VKI_IOC_SIZEBITS)))       \
+     + sizeof(t))
+

 //----------------------------------------------------------------------
 // From linux-2.6.8.1/include/linux/compiler.h
 //----------------------------------------------------------------------
 //----------------------------------------------------------------------
 // From linux-2.6.8.1/include/linux/compiler.h
 //----------------------------------------------------------------------

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-ppc32-linux.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-ppc32-linux.h
index 224397d69a6ff9fa836f79feb8bd4280594c9e18..858f9417a188b9e948217a7ef1133aa52f0916ef 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-ppc32-linux.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-ppc32-linux.h
@@ -515,13 +515,6 @@ struct vki_termios {
          ((nr)   << _VKI_IOC_NRSHIFT) | \
          ((size) << _VKI_IOC_SIZESHIFT))
 
          ((nr)   << _VKI_IOC_NRSHIFT) | \
          ((size) << _VKI_IOC_SIZESHIFT))
 

-/* provoke compile error for invalid uses of size argument */
-#define _VKI_IOC_TYPECHECK(t) \
-       ((sizeof(t) == sizeof(t[1]) && \
-         sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) \
-        ? sizeof(t) \
-        : /*cause gcc to complain about division by zero*/(1/0) )
-

 /* used to create numbers */
 #define _VKI_IO(type,nr)                       _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
 #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size)))
 /* used to create numbers */
 #define _VKI_IO(type,nr)                       _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
 #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size)))

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-ppc64-linux.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-ppc64-linux.h
index c310741e72645513bafb563196dce399d42c7a22..4d786bb242680638edc439eaa6ea005da9bfd250 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-ppc64-linux.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-ppc64-linux.h
@@ -558,13 +558,6 @@ struct vki_termios {
          ((nr)   << _VKI_IOC_NRSHIFT) | \
          ((size) << _VKI_IOC_SIZESHIFT))
 
          ((nr)   << _VKI_IOC_NRSHIFT) | \
          ((size) << _VKI_IOC_SIZESHIFT))
 

-/* provoke compile error for invalid uses of size argument */
-#define _VKI_IOC_TYPECHECK(t) \
-       ((sizeof(t) == sizeof(t[1]) && \
-         sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) \
-        ? sizeof(t) \
-        : /*cause gcc to complain about division by zero*/(1/0) )
-

 /* used to create numbers */
 #define _VKI_IO(type,nr)            _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
 #define _VKI_IOR(type,nr,size)      _VKI_IOC(_VKI_IOC_READ,(type),(nr), \
 /* used to create numbers */
 #define _VKI_IO(type,nr)            _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
 #define _VKI_IOR(type,nr,size)      _VKI_IOC(_VKI_IOC_READ,(type),(nr), \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-scnums-arm-linux.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-scnums-arm-linux.h
index 559c87ecfa9c6e2a7f6563224232b8c6d565728c..24f28054bc85faa35820fe871586c9314934c11c 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-scnums-arm-linux.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-scnums-arm-linux.h
@@ -370,7 +370,7 @@
 #define __NR_readlinkat                        332
 #define __NR_fchmodat                  333
 #define __NR_faccessat                 334
 #define __NR_readlinkat                        332
 #define __NR_fchmodat                  333
 #define __NR_faccessat                 334

-                                       /* 335 for pselect6 */
+#define __NR_pselect6                  335 /* JRS 20100812: is this correct? */

                                        /* 336 for ppoll */
 #define __NR_unshare                   337
 #define __NR_set_robust_list           338
                                        /* 336 for ppoll */
 #define __NR_unshare                   337
 #define __NR_set_robust_list           338

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-scnums-darwin.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-scnums-darwin.h
index c02cdac4717ad503f8160caf588109dee3dd0f6c..f39f28ebb5e2d6136b93b0312e24795da5affade 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-scnums-darwin.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-scnums-darwin.h
@@ -32,6 +32,9 @@
 #define __VKI_SCNUMS_DARWIN_H
 
 
 #define __VKI_SCNUMS_DARWIN_H
 
 

+// need DARWIN_10_x definitions
+#include "config.h"
+

 // osfmk/mach/i386/syscall_sw.h
 
 // There are two syscall number encodings in Darwin.
 // osfmk/mach/i386/syscall_sw.h
 
 // There are two syscall number encodings in Darwin.


@@ -376,7 +379,11 @@
 #define __NR_sigreturn      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(184)
 #define __NR_chud           VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(185)
                        /* 186  */
 #define __NR_sigreturn      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(184)
 #define __NR_chud           VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(185)
                        /* 186  */

+#if DARWIN_VERS >= DARWIN_10_6
+#define __NR_fdatasync      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(187)
+#else

                        /* 187  */
                        /* 187  */

+#endif

 #define        __NR_stat           VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(188)
 #define        __NR_fstat          VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(189)
 #define        __NR_lstat          VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(190)
 #define        __NR_stat           VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(188)
 #define        __NR_fstat          VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(189)
 #define        __NR_lstat          VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(190)


@@ -403,8 +410,13 @@
 #define        __NR_ATPgetreq      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(211)
 #define        __NR_ATPgetrsp      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(212)
                        /* 213  Reserved for AppleTalk */
 #define        __NR_ATPgetreq      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(211)
 #define        __NR_ATPgetrsp      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(212)
                        /* 213  Reserved for AppleTalk */

-#define        __NR_kqueue_from_portset_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(214)
-#define        __NR_kqueue_portset_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(215)
+#if DARWIN_VERS >= DARWIN_10_6
+                        /* 214  old kqueue_from_portset_np*/
+                        /* 215  old kqueue_portset_np*/
+#else
+#define __NR_kqueue_from_portset_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(214)
+#define __NR_kqueue_portset_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(215)
+#endif

 #define        __NR_mkcomplex      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(216)
 #define        __NR_statv          VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(217)
 #define        __NR_lstatv         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(218)
 #define        __NR_mkcomplex      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(216)
 #define        __NR_statv          VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(217)
 #define        __NR_lstatv         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(218)


@@ -413,12 +425,17 @@
 #define        __NR_setattrlist    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(221)
 #define        __NR_getdirentriesattr VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(222)
 #define        __NR_exchangedata   VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(223)
 #define        __NR_setattrlist    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(221)
 #define        __NR_getdirentriesattr VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(222)
 #define        __NR_exchangedata   VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(223)

-                       /* 224  checkuseraccess */
+                       /* 224  old checkuseraccess */

 #define        __NR_searchfs       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(225)
 #define        __NR_delete         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(226)
 #define        __NR_copyfile       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(227)
 #define        __NR_searchfs       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(225)
 #define        __NR_delete         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(226)
 #define        __NR_copyfile       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(227)

+#if DARWIN_VERS >= DARWIN_10_6
+#define __NR_fgetattrlist   VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(228)
+#define __NR_fsetattrlist   VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(229)
+#else

                        /* 228  */
                        /* 229  */
                        /* 228  */
                        /* 229  */

+#endif

 #define        __NR_poll           VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(230)
 #define        __NR_watchevent     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(231)
 #define        __NR_waitevent      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(232)
 #define        __NR_poll           VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(230)
 #define        __NR_watchevent     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(231)
 #define        __NR_waitevent      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(232)


@@ -434,7 +451,11 @@
 #define        __NR_fsctl          VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(242)
 #define        __NR_initgroups     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(243)
 #define __NR_posix_spawn    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(244)
 #define        __NR_fsctl          VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(242)
 #define        __NR_initgroups     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(243)
 #define __NR_posix_spawn    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(244)

+#if DARWIN_VERS >= DARWIN_10_6
+#define __NR_ffsctl         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(245)
+#else

                        /* 245  */
                        /* 245  */

+#endif

                        /* 246  */
 #define __NR_nfsclnt        VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(247)
 #define __NR_fhopen         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(248)
                        /* 246  */
 #define __NR_nfsclnt        VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(247)
 #define __NR_fhopen         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(248)


@@ -485,23 +506,27 @@
 #define        __NR_identitysvc    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(293)
 #define        __NR_shared_region_check_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(294)
 #define        __NR_shared_region_map_np   VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(295)
 #define        __NR_identitysvc    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(293)
 #define        __NR_shared_region_check_np VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(294)
 #define        __NR_shared_region_map_np   VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(295)

+#if DARWIN_VERS >= DARWIN_10_6
+#define __NR_vm_pressure_monitor    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(296)
+#else

                        /* 296  old load_shared_file */
                        /* 296  old load_shared_file */

+#endif

                        /* 297  old reset_shared_file */
                        /* 298  old new_system_shared_regions */
                        /* 299  old shared_region_map_file_np */
                        /* 300  old shared_region_make_private_np */
                        /* 297  old reset_shared_file */
                        /* 298  old new_system_shared_regions */
                        /* 299  old shared_region_map_file_np */
                        /* 300  old shared_region_make_private_np */

-#define __NR___pthread_mutex_destroy VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(301)
-#define __NR___pthread_mutex_init VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(302)
-#define __NR___pthread_mutex_lock VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(303)
-#define __NR___pthread_mutex_trylock VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(304)
-#define __NR___pthread_mutex_unlock VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(305)
-#define __NR___pthread_cond_init VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(306)
-#define __NR___pthread_cond_destroy VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(307)
-#define __NR___pthread_cond_broadcast VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(308)
-#define __NR___pthread_cond_signal VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(309)
+                       /* 301 */
+                       /* 302 */
+                       /* 303 */
+                       /* 304 */
+                       /* 305 */
+                       /* 306 */
+                       /* 307 */
+                       /* 308 */
+                       /* 309 */

 #define        __NR_getsid         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(310)
 #define        __NR_settid_with_pid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(311)
 #define        __NR_getsid         VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(310)
 #define        __NR_settid_with_pid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(311)

-#define __NR___pthread_cond_timedwait VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(312)
+                       /* 312 */

 #define        __NR_aio_fsync      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(313)
 #define        __NR_aio_return     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(314)
 #define        __NR_aio_suspend    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(315)
 #define        __NR_aio_fsync      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(313)
 #define        __NR_aio_return     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(314)
 #define        __NR_aio_suspend    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(315)


@@ -510,7 +535,7 @@
 #define        __NR_aio_read       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(318)
 #define        __NR_aio_write      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(319)
 #define        __NR_lio_listio     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(320)
 #define        __NR_aio_read       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(318)
 #define        __NR_aio_write      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(319)
 #define        __NR_lio_listio     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(320)

-#define __NR___pthread_cond_wait VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(321)
+                       /* 321 */

 #define __NR_iopolicysys    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(322)
                        /* 323  */
 #define        __NR_mlockall       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(324)
 #define __NR_iopolicysys    VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(322)
                        /* 323  */
 #define        __NR_mlockall       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(324)


@@ -559,10 +584,18 @@
 #define __NR_bsdthread_register VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(366)
 #define __NR_workq_open     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(367)
 #define __NR_workq_ops      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(368)
 #define __NR_bsdthread_register VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(366)
 #define __NR_workq_open     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(367)
 #define __NR_workq_ops      VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(368)

+#if DARWIN_VERS >= DARWIN_10_6
+#define __NR_kevent64       VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(369)
+#else

                        /* 369  */
                        /* 369  */

+#endif

                        /* 370  */
                        /* 371  */
                        /* 370  */
                        /* 371  */

+#if DARWIN_VERS >= DARWIN_10_6
+#define __NR___thread_selfid VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(372)  // was UX64
+#else

                        /* 372  */
                        /* 372  */

+#endif

                        /* 373  */
                        /* 374  */
                        /* 375  */
                        /* 373  */
                        /* 374  */
                        /* 375  */


@@ -617,7 +650,19 @@
 #define __NR___mac_mount            VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(424)
 #define __NR___mac_get_mount        VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(425)
 #define __NR___mac_getfsstat        VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(426)
 #define __NR___mac_mount            VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(424)
 #define __NR___mac_get_mount        VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(425)
 #define __NR___mac_getfsstat        VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(426)

+#if DARWIN_VERS >= DARWIN_10_6
+#define __NR_fsgetpath              VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(427)
+#define __NR_audit_session_self     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(428)
+#define __NR_audit_session_join     VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(429)
+#endif
+
+#if DARWIN_VERS < DARWIN_10_6

 #define        __NR_MAXSYSCALL             VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(427)
 #define        __NR_MAXSYSCALL             VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(427)

+#elif DARWIN_VERSION < DARWIN_10_7
+#define        __NR_MAXSYSCALL             VG_DARWIN_SYSCALL_CONSTRUCT_UNIX(430)
+#else
+#error unknown darwin version
+#endif

 
 #define __NR_DARWIN_FAKE_SIGRETURN (1 + __NR_MAXSYSCALL)
 
 
 #define __NR_DARWIN_FAKE_SIGRETURN (1 + __NR_MAXSYSCALL)
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-x86-linux.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-x86-linux.h
index e45a0ed639aa9fddc67408409fdb3e09dd0d4608..0d50529467122202408fbe48dadd2cac48f37e0a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-x86-linux.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/include/vki/vki-x86-linux.h
@@ -479,13 +479,6 @@ struct vki_termios {
         ((nr)   << _VKI_IOC_NRSHIFT) | \
         ((size) << _VKI_IOC_SIZESHIFT))
 
         ((nr)   << _VKI_IOC_NRSHIFT) | \
         ((size) << _VKI_IOC_SIZESHIFT))
 

-/* provoke compile error for invalid uses of size argument */
-#define _VKI_IOC_TYPECHECK(t) \
-       ((sizeof(t) == sizeof(t[1]) && \
-         sizeof(t) < (1 << _VKI_IOC_SIZEBITS)) \
-        ? sizeof(t) \
-        : /*cause gcc to complain about division by zero*/(1/0) )
-

 /* used to create numbers */
 #define _VKI_IO(type,nr)       _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
 #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size)))
 /* used to create numbers */
 #define _VKI_IO(type,nr)       _VKI_IOC(_VKI_IOC_NONE,(type),(nr),0)
 #define _VKI_IOR(type,nr,size) _VKI_IOC(_VKI_IOC_READ,(type),(nr),(_VKI_IOC_TYPECHECK(size)))

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/Makefile.am
index ba38e70482f3de278a122122846bfa7830ac149d..39ada21fddc6715948f8a6f14700959285edb780 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/Makefile.am
@@ -13,7 +13,8 @@ endif
 
 LACKEY_SOURCES_COMMON = lk_main.c
 
 
 LACKEY_SOURCES_COMMON = lk_main.c
 

-lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = $(LACKEY_SOURCES_COMMON)
+lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = \
+       $(LACKEY_SOURCES_COMMON)

 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \


@@ -24,8 +25,16 @@ lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 if VGCONF_HAVE_PLATFORM_SEC

-lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = $(LACKEY_SOURCES_COMMON)
+lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
+       $(LACKEY_SOURCES_COMMON)

 lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \
 lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \


@@ -36,5 +45,11 @@ lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 endif
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/Makefile.in
index c8d17063b38718d6d95c5fe5bbbe59c115643762..7c7f54f54bdc2acc822b6ec1c9d408c83e63bcf7 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/Makefile.in
@@ -43,25 +43,9 @@ build_triplet = @build@
 host_triplet = @host@
 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
 host_triplet = @host@
 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = lackey-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)
 noinst_PROGRAMS = lackey-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = lackey-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = lackey-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = lackey
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = lackey
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4


@@ -79,10 +63,6 @@ am__objects_1 =  \
 am_lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
 am_lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o \
-       $@

 am__lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = lk_main.c
 am__objects_2 =  \
        lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@-lk_main.$(OBJEXT)
 am__lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = lk_main.c
 am__objects_2 =  \
        lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@-lk_main.$(OBJEXT)


@@ -90,10 +70,6 @@ am__objects_2 =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o \
-       $@

 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 am__depfiles_maybe = depfiles
 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 am__depfiles_maybe = depfiles


@@ -184,6 +160,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -218,14 +195,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -309,7 +290,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -368,7 +351,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -383,8 +366,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -447,37 +430,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -486,32 +469,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -590,7 +569,9 @@ LIBREPLACEMALLOC_LDFLAGS_X86_L4RE = \
 
 EXTRA_DIST = docs/lk-manual.xml
 LACKEY_SOURCES_COMMON = lk_main.c
 
 EXTRA_DIST = docs/lk-manual.xml
 LACKEY_SOURCES_COMMON = lk_main.c

-lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(LACKEY_SOURCES_COMMON)
+lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+       $(LACKEY_SOURCES_COMMON)
+

 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 


@@ -606,7 +587,16 @@ lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(LACKEY_SOURCES_COMMON)
+lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LACKEY_SOURCES_COMMON)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 


@@ -622,8 +612,14 @@ lackey_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(lackey_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -912,13 +908,11 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
 all-am: Makefile $(PROGRAMS) all-local
 installdirs: installdirs-recursive
 installdirs-am:

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -935,7 +929,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -944,7 +937,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1015,9 +1007,8 @@ ps-am:
 
 uninstall-am:
 
 
 uninstall-am:
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1099,65 +1090,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/tests/Makefile.in
index 1c58258a2fa81d2c6c2b94aea2e202f5320586b9..9c0dd75b1fcde52b2a8e582e2a3e78f746587456 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/lackey/tests/Makefile.in
@@ -86,6 +86,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -120,14 +121,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/Makefile.am
index 32c54dd032ebfec5a09d3bd230c6561a78271059..94bcd68bc81fcd424febef747314faaff2ef1126 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/Makefile.am
@@ -23,7 +23,8 @@ endif
 
 MASSIF_SOURCES_COMMON = ms_main.c
 
 
 MASSIF_SOURCES_COMMON = ms_main.c
 

-massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = $(MASSIF_SOURCES_COMMON)
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = \
+       $(MASSIF_SOURCES_COMMON)

 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \


@@ -34,8 +35,16 @@ massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 if VGCONF_HAVE_PLATFORM_SEC

-massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = $(MASSIF_SOURCES_COMMON)
+massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
+       $(MASSIF_SOURCES_COMMON)

 massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \
 massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \


@@ -46,6 +55,12 @@ massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 #----------------------------------------------------------------------------
 endif
 
 #----------------------------------------------------------------------------


@@ -71,6 +86,7 @@ vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+

 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = 
 vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS     = \
 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = 
 vgpreload_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_CPPFLAGS     = \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/Makefile.in
index 53376196bb9e8aee053bd906f412c85a9e5dde4c..fc8c022a0cb34d92793bb5d4f15580400372dc57 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/Makefile.in
@@ -45,29 +45,13 @@ host_triplet = @host@
 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(srcdir)/ms_print.in $(top_srcdir)/Makefile.all.am \
        $(top_srcdir)/Makefile.tool.am
 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(srcdir)/ms_print.in $(top_srcdir)/Makefile.all.am \
        $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)
 noinst_PROGRAMS = massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_massif-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_14 = vgpreload_massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = vgpreload_massif-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so

 subdir = massif
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = massif
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -85,10 +69,6 @@ am__objects_1 =  \
 am_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
 am_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o \
-       $@

 am__massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = ms_main.c
 am__objects_2 =  \
        massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.$(OBJEXT)
 am__massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = ms_main.c
 am__objects_2 =  \
        massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@-ms_main.$(OBJEXT)


@@ -96,10 +76,6 @@ am__objects_2 =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o \
-       $@

 am_vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = $(am_vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS)
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD = $(LDADD)
 am_vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS = $(am_vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS)
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDADD = $(LDADD)


@@ -233,6 +209,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -267,14 +244,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -358,7 +339,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -417,7 +400,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -432,8 +415,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -496,37 +479,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -535,32 +518,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -647,7 +626,9 @@ EXTRA_DIST = \
 #----------------------------------------------------------------------------
 bin_SCRIPTS = ms_print
 MASSIF_SOURCES_COMMON = ms_main.c
 #----------------------------------------------------------------------------
 bin_SCRIPTS = ms_print
 MASSIF_SOURCES_COMMON = ms_main.c

-massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(MASSIF_SOURCES_COMMON)
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+       $(MASSIF_SOURCES_COMMON)
+

 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 


@@ -663,7 +644,16 @@ massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(MASSIF_SOURCES_COMMON)
+massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(MASSIF_SOURCES_COMMON)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 


@@ -679,6 +669,13 @@ massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

+@VGCONF_HAVE_PLATFORM_SEC_TRUE@massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(massif_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+

 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = 
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = 
 vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_CPPFLAGS = \


@@ -708,8 +705,7 @@ vgpreload_massif_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -1040,16 +1036,14 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) $(SCRIPTS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(bindir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done
 all-am: Makefile $(PROGRAMS) $(SCRIPTS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(bindir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -1066,7 +1060,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -1075,7 +1068,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1146,9 +1138,8 @@ ps-am:
 
 uninstall-am: uninstall-binSCRIPTS
 
 
 uninstall-am: uninstall-binSCRIPTS
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1230,65 +1221,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/docs/ms-manual.xml b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/docs/ms-manual.xml
index 22feac7b22b66ecc65e66b503ff334ffd8135e06..9e318c51f8cf13eaf8570d4142971dd1704f9dee 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/docs/ms-manual.xml
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/docs/ms-manual.xml
@@ -545,11 +545,11 @@ file, which will almost certainly make it unreadable by ms_print.</para>
 
 
 <sect2 id="ms-manual.not-measured"
 
 
 <sect2 id="ms-manual.not-measured"

-       xreflabel="Memory Allocations Not Measured by Massif">
-<title>Memory Allocations Not Measured by Massif</title>
+       xreflabel="Measuring All Memory in a Process">
+<title>Measuring All Memory in a Process</title>

 <para>
 <para>

-It is worth emphasising that Massif measures only heap memory, i.e. memory
-allocated with
+It is worth emphasising that by default Massif measures only heap memory, i.e.
+memory allocated with

 <function>malloc</function>,
 <function>calloc</function>,
 <function>realloc</function>,
 <function>malloc</function>,
 <function>calloc</function>,
 <function>realloc</function>,


@@ -576,13 +576,49 @@ not the lower-level system calls.
 
 <para>
 Furthermore, a client program may use these lower-level system calls
 
 <para>
 Furthermore, a client program may use these lower-level system calls

-directly to allocate memory.  Massif does not measure these.  Nor does it
-measure the size of code, data and BSS segments.  Therefore, the numbers
-reported by Massif may be significantly smaller than those reported by tools
-such as <filename>top</filename> that measure a program's total size in
+directly to allocate memory.  By default, Massif does not measure these.  Nor
+does it measure the size of code, data and BSS segments.  Therefore, the
+numbers reported by Massif may be significantly smaller than those reported by
+tools such as <filename>top</filename> that measure a program's total size in

 memory.
 </para>
 
 memory.
 </para>
 

+<para>
+However, if you wish to measure <emphasis>all</emphasis> the memory used by
+your program, you can use the <option>--pages-as-heap=yes</option>.  When this
+option is enabled, Massif's normal heap block profiling is replaced by
+lower-level page profiling.  Every page allocated via
+<function>mmap</function> and similar system calls is treated as a distinct
+block.  This means that code, data and BSS segments are all measured, as they
+are just memory pages.  Even the stack is measured, since it is ultimately
+allocated (and extended when necessary) via <function>mmap</function>;  for
+this reason <option>--stacks=yes</option> is not allowed in conjunction with
+<option>--pages-as-heap=yes</option>.
+</para>
+
+<para>
+After <option>--pages-as-heap=yes</option> is used, ms_print's output is
+mostly unchanged.  One difference is that the start of each detailed snapshot
+says:
+</para>
+
+<screen><![CDATA[
+(page allocation syscalls) mmap/mremap/brk, --alloc-fns, etc.
+]]></screen>
+
+<para>instead of the usual</para>:
+
+<screen><![CDATA[
+(heap allocation functions) malloc/new/new[], --alloc-fns, etc.
+]]></screen>
+
+<para>
+The stack traces in the output may be more difficult to read, and interpreting
+them may require some detailed understanding of the lower levels of a program
+like the memory allocators.  But for some programs having the full information
+about memory usage can be very useful.
+</para>
+

 </sect2>
 
 
 </sect2>
 
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/ms_main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/ms_main.c
index 320e23d97d35fc92790a6cc717c71492b151d977..c34d27b805cda9ac4bcaa5595ae2c55196171a75 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/ms_main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/ms_main.c
@@ -176,6 +176,7 @@ Number of snapshots: 50
 #include "pub_tool_options.h"
 #include "pub_tool_replacemalloc.h"
 #include "pub_tool_stacktrace.h"
 #include "pub_tool_options.h"
 #include "pub_tool_replacemalloc.h"
 #include "pub_tool_stacktrace.h"

+#include "pub_tool_threadstate.h"

 #include "pub_tool_tooliface.h"
 #include "pub_tool_xarray.h"
 #include "pub_tool_clientstate.h"
 #include "pub_tool_tooliface.h"
 #include "pub_tool_xarray.h"
 #include "pub_tool_clientstate.h"


@@ -190,6 +191,10 @@ Number of snapshots: 50
 // of detail, enough to tell how many bytes each line of code is responsible
 // for, more or less.  The main data structure is a tree representing the
 // call tree beneath all the allocation functions like malloc().
 // of detail, enough to tell how many bytes each line of code is responsible
 // for, more or less.  The main data structure is a tree representing the
 // call tree beneath all the allocation functions like malloc().

+// (Alternatively, if --pages-as-heap=yes is specified, memory is tracked at
+// the page level, and each page is treated much like a heap block.  We use
+// "heap" throughout below to cover this case because the concepts are all the
+// same.)

 //
 // "Snapshots" are recordings of the memory usage.  There are two basic
 // kinds:
 //
 // "Snapshots" are recordings of the memory usage.  There are two basic
 // kinds:


@@ -280,14 +285,17 @@ static SizeT peak_snapshot_total_szB = 0;
 // memory.  An alternative to milliseconds as a unit of program "time".
 static ULong total_allocs_deallocs_szB = 0;
 
 // memory.  An alternative to milliseconds as a unit of program "time".
 static ULong total_allocs_deallocs_szB = 0;
 

-// We don't start taking snapshots until the first basic block is executed,
-// rather than doing it in ms_post_clo_init (which is the obvious spot), for
-// two reasons.
+// When running with --heap=yes --pages-as-heap=no, we don't start taking
+// snapshots until the first basic block is executed, rather than doing it in
+// ms_post_clo_init (which is the obvious spot), for two reasons.

 // - It lets us ignore stack events prior to that, because they're not
 //   really proper ones and just would screw things up.
 // - Because there's still some core initialisation to do, and so there
 //   would be an artificial time gap between the first and second snapshots.
 //
 // - It lets us ignore stack events prior to that, because they're not
 //   really proper ones and just would screw things up.
 // - Because there's still some core initialisation to do, and so there
 //   would be an artificial time gap between the first and second snapshots.
 //

+// When running with --heap=yes --pages-as-heap=yes, snapshots start much
+// earlier due to new_mem_startup so this isn't relevant.
+//

 static Bool have_started_executing_code = False;
 
 //------------------------------------------------------------//
 static Bool have_started_executing_code = False;
 
 //------------------------------------------------------------//


@@ -393,12 +401,13 @@ static Char* TimeUnit_to_string(TimeUnit time_unit)
    }
 }
 
    }
 }
 

-static Bool clo_heap            = True;
+static Bool   clo_heap            = True;

    // clo_heap_admin is deliberately a word-sized type.  At one point it was
    // a UInt, but this caused problems on 64-bit machines when it was
    // multiplied by a small negative number and then promoted to a
    // word-sized type -- it ended up with a value of 4.2 billion.  Sigh.
 static SSizeT clo_heap_admin      = 8;
    // clo_heap_admin is deliberately a word-sized type.  At one point it was
    // a UInt, but this caused problems on 64-bit machines when it was
    // multiplied by a small negative number and then promoted to a
    // word-sized type -- it ended up with a value of 4.2 billion.  Sigh.
 static SSizeT clo_heap_admin      = 8;

+static Bool   clo_pages_as_heap   = False;

 static Bool   clo_stacks          = False;
 static Int    clo_depth           = 30;
 static double clo_threshold       = 1.0;  // percentage
 static Bool   clo_stacks          = False;
 static Int    clo_depth           = 30;
 static double clo_threshold       = 1.0;  // percentage


@@ -417,29 +426,39 @@ static Bool ms_process_cmd_line_option(Char* arg)
    // Remember the arg for later use.
    VG_(addToXA)(args_for_massif, &arg);
 
    // Remember the arg for later use.
    VG_(addToXA)(args_for_massif, &arg);
 

-        if VG_BOOL_CLO(arg, "--heap",   clo_heap)   {}
-   else if VG_BOOL_CLO(arg, "--stacks", clo_stacks) {}
-
-   else if VG_BINT_CLO(arg, "--heap-admin", clo_heap_admin, 0, 1024) {}
-   else if VG_BINT_CLO(arg, "--depth",      clo_depth, 1, MAX_DEPTH) {}
+        if VG_BOOL_CLO(arg, "--heap",           clo_heap)   {}
+   else if VG_BINT_CLO(arg, "--heap-admin",     clo_heap_admin, 0, 1024) {}

 
 

-   else if VG_DBL_CLO(arg, "--threshold",  clo_threshold) {}
-
-   else if VG_DBL_CLO(arg, "--peak-inaccuracy", clo_peak_inaccuracy) {}
+   else if VG_BOOL_CLO(arg, "--stacks",         clo_stacks) {}

 
 

-   else if VG_BINT_CLO(arg, "--detailed-freq", clo_detailed_freq, 1, 10000) {}
-   else if VG_BINT_CLO(arg, "--max-snapshots", clo_max_snapshots, 10, 1000) {}
+   else if VG_BOOL_CLO(arg, "--pages-as-heap",  clo_pages_as_heap) {}

 
 

-   else if VG_XACT_CLO(arg, "--time-unit=i",  clo_time_unit, TimeI)  {}
-   else if VG_XACT_CLO(arg, "--time-unit=ms", clo_time_unit, TimeMS) {}
-   else if VG_XACT_CLO(arg, "--time-unit=B",  clo_time_unit, TimeB)  {}
+   else if VG_BINT_CLO(arg, "--depth",          clo_depth, 1, MAX_DEPTH) {}

 
 

-   else if VG_STR_CLO(arg, "--alloc-fn", tmp_str) {
+   else if VG_STR_CLO(arg, "--alloc-fn",        tmp_str) {

       VG_(addToXA)(alloc_fns, &tmp_str);
    }
       VG_(addToXA)(alloc_fns, &tmp_str);
    }

-   else if VG_STR_CLO(arg, "--ignore-fn", tmp_str) {
+   else if VG_STR_CLO(arg, "--ignore-fn",       tmp_str) {

       VG_(addToXA)(ignore_fns, &tmp_str);
    }
       VG_(addToXA)(ignore_fns, &tmp_str);
    }

+
+   else if VG_DBL_CLO(arg, "--threshold",  clo_threshold) {
+      if (clo_threshold < 0 || clo_threshold > 100) {
+         VG_(fmsg_bad_option)(arg,
+            "--threshold must be between 0.0 and 100.0\n");
+      }
+   }
+
+   else if VG_DBL_CLO(arg, "--peak-inaccuracy", clo_peak_inaccuracy) {}
+
+   else if VG_XACT_CLO(arg, "--time-unit=i",    clo_time_unit, TimeI)  {}
+   else if VG_XACT_CLO(arg, "--time-unit=ms",   clo_time_unit, TimeMS) {}
+   else if VG_XACT_CLO(arg, "--time-unit=B",    clo_time_unit, TimeB)  {}
+
+   else if VG_BINT_CLO(arg, "--detailed-freq",  clo_detailed_freq, 1, 10000) {}
+
+   else if VG_BINT_CLO(arg, "--max-snapshots",  clo_max_snapshots, 10, 1000) {}
+

    else if VG_STR_CLO(arg, "--massif-out-file", clo_massif_out_file) {}
 
    else
    else if VG_STR_CLO(arg, "--massif-out-file", clo_massif_out_file) {}
 
    else


@@ -455,6 +474,7 @@ static void ms_print_usage(void)
 "    --heap-admin=<size>       average admin bytes per heap block;\n"
 "                               ignored if --heap=no [8]\n"
 "    --stacks=no|yes           profile stack(s) [no]\n"
 "    --heap-admin=<size>       average admin bytes per heap block;\n"
 "                               ignored if --heap=no [8]\n"
 "    --stacks=no|yes           profile stack(s) [no]\n"

+"    --pages-as-heap=no|yes    profile memory at the page level [no]\n"

 "    --depth=<number>          depth of contexts [30]\n"
 "    --alloc-fn=<name>         specify <name> as an alloc function [empty]\n"
 "    --ignore-fn=<name>        ignore heap allocations within <name> [empty]\n"
 "    --depth=<number>          depth of contexts [30]\n"
 "    --alloc-fn=<name>         specify <name> as an alloc function [empty]\n"
 "    --ignore-fn=<name>        ignore heap allocations within <name> [empty]\n"


@@ -842,7 +862,7 @@ static Bool fn_should_be_ignored(Addr ip)
 // Nb: it's possible to end up with an empty trace, eg. if 'main' is marked
 // as an alloc-fn.  This is ok.
 static
 // Nb: it's possible to end up with an empty trace, eg. if 'main' is marked
 // as an alloc-fn.  This is ok.
 static

-Int get_IPs( ThreadId tid, Bool is_custom_alloc, Addr ips[])
+Int get_IPs( ThreadId tid, Bool exclude_first_entry, Addr ips[])

 {
    static Char buf[BUF_LEN];
    Int n_ips, i, n_alloc_fns_removed;
 {
    static Char buf[BUF_LEN];
    Int n_ips, i, n_alloc_fns_removed;


@@ -877,11 +897,11 @@ Int get_IPs( ThreadId tid, Bool is_custom_alloc, Addr ips[])
       // If the original stack trace is smaller than asked-for, redo=False.
       if (n_ips < clo_depth + overestimate) { redo = False; }
 
       // If the original stack trace is smaller than asked-for, redo=False.
       if (n_ips < clo_depth + overestimate) { redo = False; }
 

-      // Filter out alloc fns.  If it's a non-custom block, we remove the
-      // first entry (which will be one of malloc, __builtin_new, etc)
-      // without looking at it, because VG_(get_fnname) is expensive (it
-      // involves calls to VG_(malloc)/VG_(free)).
-      n_alloc_fns_removed = ( is_custom_alloc ? 0 : 1 );
+      // Filter out alloc fns.  If requested, we automatically remove the
+      // first entry (which presumably will be something like malloc or
+      // __builtin_new that we're sure to filter out) without looking at it,
+      // because VG_(get_fnname) is expensive.
+      n_alloc_fns_removed = ( exclude_first_entry ? 1 : 0 );

       for (i = n_alloc_fns_removed; i < n_ips; i++) {
          if (VG_(get_fnname)(ips[i], buf, BUF_LEN)) {
             if (is_member_fn(alloc_fns, buf)) {
       for (i = n_alloc_fns_removed; i < n_ips; i++) {
          if (VG_(get_fnname)(ips[i], buf, BUF_LEN)) {
             if (is_member_fn(alloc_fns, buf)) {


@@ -912,14 +932,14 @@ Int get_IPs( ThreadId tid, Bool is_custom_alloc, Addr ips[])
 
 // Gets an XCon and puts it in the tree.  Returns the XCon's bottom-XPt.
 // Unless the allocation should be ignored, in which case we return NULL.
 
 // Gets an XCon and puts it in the tree.  Returns the XCon's bottom-XPt.
 // Unless the allocation should be ignored, in which case we return NULL.

-static XPt* get_XCon( ThreadId tid, Bool is_custom_alloc )
+static XPt* get_XCon( ThreadId tid, Bool exclude_first_entry )

 {
    static Addr ips[MAX_IPS];
    Int i;
    XPt* xpt = alloc_xpt;
 
    // After this call, the IPs we want are in ips[0]..ips[n_ips-1].
 {
    static Addr ips[MAX_IPS];
    Int i;
    XPt* xpt = alloc_xpt;
 
    // After this call, the IPs we want are in ips[0]..ips[n_ips-1].

-   Int n_ips = get_IPs(tid, is_custom_alloc, ips);
+   Int n_ips = get_IPs(tid, exclude_first_entry, ips);

 
    // Should we ignore this allocation?  (Nb: n_ips can be zero, eg. if
    // 'main' is marked as an alloc-fn.)
 
    // Should we ignore this allocation?  (Nb: n_ips can be zero, eg. if
    // 'main' is marked as an alloc-fn.)


@@ -996,7 +1016,7 @@ static XPt* get_XCon( ThreadId tid, Bool is_custom_alloc )
 // Update 'szB' of every XPt in the XCon, by percolating upwards.
 static void update_XCon(XPt* xpt, SSizeT space_delta)
 {
 // Update 'szB' of every XPt in the XCon, by percolating upwards.
 static void update_XCon(XPt* xpt, SSizeT space_delta)
 {

-   tl_assert(True == clo_heap);
+   tl_assert(clo_heap);

    tl_assert(NULL != xpt);
 
    if (0 == space_delta)
    tl_assert(NULL != xpt);
 
    if (0 == space_delta)


@@ -1323,7 +1343,9 @@ take_snapshot(Snapshot* snapshot, SnapshotKind kind, Time my_time,
               Bool is_detailed)
 {
    tl_assert(!is_snapshot_in_use(snapshot));
               Bool is_detailed)
 {
    tl_assert(!is_snapshot_in_use(snapshot));

-   tl_assert(have_started_executing_code);
+   if (!clo_pages_as_heap) {
+      tl_assert(have_started_executing_code);
+   }

 
    // Heap and heap admin.
    if (clo_heap) {
 
    // Heap and heap admin.
    if (clo_heap) {


@@ -1518,31 +1540,11 @@ static void update_heap_stats(SSizeT heap_szB_delta, Int heap_extra_szB_delta)
 }
 
 static
 }
 
 static

-void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB,
-                  Bool is_zeroed )
+void* record_block( ThreadId tid, void* p, SizeT req_szB, SizeT slop_szB,
+                    Bool exclude_first_entry, Bool maybe_snapshot )

 {
 {

-   HP_Chunk* hc;
-   Bool is_custom_alloc = (NULL != p);
-   SizeT actual_szB, slop_szB;
-
-   if ((SSizeT)req_szB < 0) return NULL;
-
-   // Allocate and zero if necessary
-   if (!p) {
-      p = VG_(cli_malloc)( req_alignB, req_szB );
-      if (!p) {
-         return NULL;
-      }
-      if (is_zeroed) VG_(memset)(p, 0, req_szB);
-      actual_szB = VG_(malloc_usable_size)(p);
-      tl_assert(actual_szB >= req_szB);
-      slop_szB = actual_szB - req_szB;
-   } else {
-      slop_szB = 0;
-   }
-

    // Make new HP_Chunk node, add to malloc_list
    // Make new HP_Chunk node, add to malloc_list

-   hc           = VG_(malloc)("ms.main.nb.1", sizeof(HP_Chunk));
+   HP_Chunk* hc = VG_(malloc)("ms.main.rb.1", sizeof(HP_Chunk));

    hc->req_szB  = req_szB;
    hc->slop_szB = slop_szB;
    hc->data     = (Addr)p;
    hc->req_szB  = req_szB;
    hc->slop_szB = slop_szB;
    hc->data     = (Addr)p;


@@ -1550,9 +1552,9 @@ void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB,
    VG_(HT_add_node)(malloc_list, hc);
 
    if (clo_heap) {
    VG_(HT_add_node)(malloc_list, hc);
 
    if (clo_heap) {

-      VERB(3, "<<< new_mem_heap (%lu, %lu)\n", req_szB, slop_szB);
+      VERB(3, "<<< record_block (%lu, %lu)\n", req_szB, slop_szB);

 
 

-      hc->where = get_XCon( tid, is_custom_alloc );
+      hc->where = get_XCon( tid, exclude_first_entry );

 
       if (hc->where) {
          // Update statistics.
 
       if (hc->where) {
          // Update statistics.


@@ -1565,7 +1567,9 @@ void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB,
          update_XCon(hc->where, req_szB);
 
          // Maybe take a snapshot.
          update_XCon(hc->where, req_szB);
 
          // Maybe take a snapshot.

-         maybe_take_snapshot(Normal, "  alloc");
+         if (maybe_snapshot) {
+            maybe_take_snapshot(Normal, "  alloc");
+         }

 
       } else {
          // Ignored allocation.
 
       } else {
          // Ignored allocation.


@@ -1581,7 +1585,33 @@ void* new_block ( ThreadId tid, void* p, SizeT req_szB, SizeT req_alignB,
 }
 
 static __inline__
 }
 
 static __inline__

-void die_block ( void* p, Bool custom_free )
+void* alloc_and_record_block ( ThreadId tid, SizeT req_szB, SizeT req_alignB,
+                               Bool is_zeroed )
+{
+   SizeT actual_szB, slop_szB;
+   void* p;
+
+   if ((SSizeT)req_szB < 0) return NULL;
+
+   // Allocate and zero if necessary.
+   p = VG_(cli_malloc)( req_alignB, req_szB );
+   if (!p) {
+      return NULL;
+   }
+   if (is_zeroed) VG_(memset)(p, 0, req_szB);
+   actual_szB = VG_(malloc_usable_size)(p);
+   tl_assert(actual_szB >= req_szB);
+   slop_szB = actual_szB - req_szB;
+
+   // Record block.
+   record_block(tid, p, req_szB, slop_szB, /*exclude_first_entry*/True,
+                /*maybe_snapshot*/True);
+
+   return p;
+}
+
+static __inline__
+void unrecord_block ( void* p, Bool maybe_snapshot )

 {
    // Remove HP_Chunk from malloc_list
    HP_Chunk* hc = VG_(HT_remove)(malloc_list, (UWord)p);
 {
    // Remove HP_Chunk from malloc_list
    HP_Chunk* hc = VG_(HT_remove)(malloc_list, (UWord)p);


@@ -1590,14 +1620,16 @@ void die_block ( void* p, Bool custom_free )
    }
 
    if (clo_heap) {
    }
 
    if (clo_heap) {

-      VERB(3, "<<< die_mem_heap\n");
+      VERB(3, "<<< unrecord_block\n");

 
       if (hc->where) {
          // Update statistics.
          n_heap_frees++;
 
          // Maybe take a peak snapshot, since it's a deallocation.
 
       if (hc->where) {
          // Update statistics.
          n_heap_frees++;
 
          // Maybe take a peak snapshot, since it's a deallocation.

-         maybe_take_snapshot(Peak, "de-PEAK");
+         if (maybe_snapshot) {
+            maybe_take_snapshot(Peak, "de-PEAK");
+         }

 
          // Update heap stats.
          update_heap_stats(-hc->req_szB, -clo_heap_admin - hc->slop_szB);
 
          // Update heap stats.
          update_heap_stats(-hc->req_szB, -clo_heap_admin - hc->slop_szB);


@@ -1606,7 +1638,9 @@ void die_block ( void* p, Bool custom_free )
          update_XCon(hc->where, -hc->req_szB);
 
          // Maybe take a snapshot.
          update_XCon(hc->where, -hc->req_szB);
 
          // Maybe take a snapshot.

-         maybe_take_snapshot(Normal, "dealloc");
+         if (maybe_snapshot) {
+            maybe_take_snapshot(Normal, "dealloc");
+         }

 
       } else {
          n_ignored_heap_frees++;
 
       } else {
          n_ignored_heap_frees++;


@@ -1619,8 +1653,6 @@ void die_block ( void* p, Bool custom_free )
 
    // Actually free the chunk, and the heap block (if necessary)
    VG_(free)( hc );  hc = NULL;
 
    // Actually free the chunk, and the heap block (if necessary)
    VG_(free)( hc );  hc = NULL;

-   if (!custom_free)
-      VG_(cli_free)( p );

 }
 
 // Nb: --ignore-fn is tricky for realloc.  If the block's original alloc was
 }
 
 // Nb: --ignore-fn is tricky for realloc.  If the block's original alloc was


@@ -1630,7 +1662,7 @@ void die_block ( void* p, Bool custom_free )
 // growing such a block, but for consistency (it also simplifies things) we
 // ignore such reallocs as well.
 static __inline__
 // growing such a block, but for consistency (it also simplifies things) we
 // ignore such reallocs as well.
 static __inline__

-void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB )
+void* realloc_block ( ThreadId tid, void* p_old, SizeT new_req_szB )

 {
    HP_Chunk* hc;
    void*     p_new;
 {
    HP_Chunk* hc;
    void*     p_new;


@@ -1647,8 +1679,9 @@ void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB )
    old_req_szB  = hc->req_szB;
    old_slop_szB = hc->slop_szB;
 
    old_req_szB  = hc->req_szB;
    old_slop_szB = hc->slop_szB;
 

+   tl_assert(!clo_pages_as_heap);  // Shouldn't be here if --pages-as-heap=yes.

    if (clo_heap) {
    if (clo_heap) {

-      VERB(3, "<<< renew_mem_heap (%lu)\n", new_req_szB);
+      VERB(3, "<<< realloc_block (%lu)\n", new_req_szB);

 
       if (hc->where) {
          // Update statistics.
 
       if (hc->where) {
          // Update statistics.


@@ -1696,7 +1729,7 @@ void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB )
 
       // Update XTree.
       if (clo_heap) {
 
       // Update XTree.
       if (clo_heap) {

-         new_where = get_XCon( tid, /*custom_malloc*/False);
+         new_where = get_XCon( tid, /*exclude_first_entry*/True);

          if (!is_ignored && new_where) {
             hc->where = new_where;
             update_XCon(old_where, -old_req_szB);
          if (!is_ignored && new_where) {
             hc->where = new_where;
             update_XCon(old_where, -old_req_szB);


@@ -1745,47 +1778,50 @@ void* renew_block ( ThreadId tid, void* p_old, SizeT new_req_szB )
 
 static void* ms_malloc ( ThreadId tid, SizeT szB )
 {
 
 static void* ms_malloc ( ThreadId tid, SizeT szB )
 {

-   return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False );
+   return alloc_and_record_block( tid, szB, VG_(clo_alignment), /*is_zeroed*/False );

 }
 
 static void* ms___builtin_new ( ThreadId tid, SizeT szB )
 {
 }
 
 static void* ms___builtin_new ( ThreadId tid, SizeT szB )
 {

-   return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False );
+   return alloc_and_record_block( tid, szB, VG_(clo_alignment), /*is_zeroed*/False );

 }
 
 static void* ms___builtin_vec_new ( ThreadId tid, SizeT szB )
 {
 }
 
 static void* ms___builtin_vec_new ( ThreadId tid, SizeT szB )
 {

-   return new_block( tid, NULL, szB, VG_(clo_alignment), /*is_zeroed*/False );
+   return alloc_and_record_block( tid, szB, VG_(clo_alignment), /*is_zeroed*/False );

 }
 
 static void* ms_calloc ( ThreadId tid, SizeT m, SizeT szB )
 {
 }
 
 static void* ms_calloc ( ThreadId tid, SizeT m, SizeT szB )
 {

-   return new_block( tid, NULL, m*szB, VG_(clo_alignment), /*is_zeroed*/True );
+   return alloc_and_record_block( tid, m*szB, VG_(clo_alignment), /*is_zeroed*/True );

 }
 
 static void *ms_memalign ( ThreadId tid, SizeT alignB, SizeT szB )
 {
 }
 
 static void *ms_memalign ( ThreadId tid, SizeT alignB, SizeT szB )
 {

-   return new_block( tid, NULL, szB, alignB, False );
+   return alloc_and_record_block( tid, szB, alignB, False );

 }
 
 static void ms_free ( ThreadId tid __attribute__((unused)), void* p )
 {
 }
 
 static void ms_free ( ThreadId tid __attribute__((unused)), void* p )
 {

-   die_block( p, /*custom_free*/False );
+   unrecord_block(p, /*maybe_snapshot*/True);
+   VG_(cli_free)(p);

 }
 
 static void ms___builtin_delete ( ThreadId tid, void* p )
 {
 }
 
 static void ms___builtin_delete ( ThreadId tid, void* p )
 {

-   die_block( p, /*custom_free*/False);
+   unrecord_block(p, /*maybe_snapshot*/True);
+   VG_(cli_free)(p);

 }
 
 static void ms___builtin_vec_delete ( ThreadId tid, void* p )
 {
 }
 
 static void ms___builtin_vec_delete ( ThreadId tid, void* p )
 {

-   die_block( p, /*custom_free*/False );
+   unrecord_block(p, /*maybe_snapshot*/True);
+   VG_(cli_free)(p);

 }
 
 static void* ms_realloc ( ThreadId tid, void* p_old, SizeT new_szB )
 {
 }
 
 static void* ms_realloc ( ThreadId tid, void* p_old, SizeT new_szB )
 {

-   return renew_block(tid, p_old, new_szB);
+   return realloc_block(tid, p_old, new_szB);

 }
 
 static SizeT ms_malloc_usable_size ( ThreadId tid, void* p )
 }
 
 static SizeT ms_malloc_usable_size ( ThreadId tid, void* p )


@@ -1795,6 +1831,89 @@ static SizeT ms_malloc_usable_size ( ThreadId tid, void* p )
    return ( hc ? hc->req_szB + hc->slop_szB : 0 );
 }                                                            
 
    return ( hc ? hc->req_szB + hc->slop_szB : 0 );
 }                                                            
 

+//------------------------------------------------------------//
+//--- Page handling                                        ---//
+//------------------------------------------------------------//
+
+static
+void ms_record_page_mem ( Addr a, SizeT len )
+{
+   ThreadId tid = VG_(get_running_tid)();
+   Addr end;
+   tl_assert(VG_IS_PAGE_ALIGNED(len));
+   tl_assert(len >= VKI_PAGE_SIZE);
+   // Record the first N-1 pages as blocks, but don't do any snapshots.
+   for (end = a + len - VKI_PAGE_SIZE; a < end; a += VKI_PAGE_SIZE) {
+      record_block( tid, (void*)a, VKI_PAGE_SIZE, /*slop_szB*/0,
+                    /*exclude_first_entry*/False, /*maybe_snapshot*/False );
+   }
+   // Record the last page as a block, and maybe do a snapshot afterwards.
+   record_block( tid, (void*)a, VKI_PAGE_SIZE, /*slop_szB*/0,
+                 /*exclude_first_entry*/False, /*maybe_snapshot*/True );
+}
+
+static
+void ms_unrecord_page_mem( Addr a, SizeT len )
+{
+   Addr end;
+   tl_assert(VG_IS_PAGE_ALIGNED(len));
+   tl_assert(len >= VKI_PAGE_SIZE);
+   for (end = a + len - VKI_PAGE_SIZE; a < end; a += VKI_PAGE_SIZE) {
+      unrecord_block((void*)a, /*maybe_snapshot*/False);
+   }
+   unrecord_block((void*)a, /*maybe_snapshot*/True);
+}
+
+//------------------------------------------------------------//
+
+static
+void ms_new_mem_mmap ( Addr a, SizeT len,
+                       Bool rr, Bool ww, Bool xx, ULong di_handle )
+{
+   tl_assert(VG_IS_PAGE_ALIGNED(len));
+   ms_record_page_mem(a, len);
+}
+
+static
+void ms_new_mem_startup( Addr a, SizeT len,
+                         Bool rr, Bool ww, Bool xx, ULong di_handle )
+{
+   // startup maps are always be page-sized, except the trampoline page is
+   // marked by the core as only being the size of the trampoline itself,
+   // which is something like 57 bytes.  Round it up to page size.
+   len = VG_PGROUNDUP(len);
+   ms_record_page_mem(a, len);
+}
+
+static
+void ms_new_mem_brk ( Addr a, SizeT len, ThreadId tid )
+{
+   tl_assert(VG_IS_PAGE_ALIGNED(len));
+   ms_record_page_mem(a, len);
+}
+
+static
+void ms_copy_mem_remap( Addr from, Addr to, SizeT len)
+{
+   tl_assert(VG_IS_PAGE_ALIGNED(len));
+   ms_unrecord_page_mem(from, len);
+   ms_record_page_mem(to, len);
+}
+
+static
+void ms_die_mem_munmap( Addr a, SizeT len )
+{
+   tl_assert(VG_IS_PAGE_ALIGNED(len));
+   ms_unrecord_page_mem(a, len);
+}
+
+static
+void ms_die_mem_brk( Addr a, SizeT len )
+{
+   tl_assert(VG_IS_PAGE_ALIGNED(len));
+   ms_unrecord_page_mem(a, len);
+}
+

 //------------------------------------------------------------//
 //--- Stacks                                               ---//
 //------------------------------------------------------------//
 //------------------------------------------------------------//
 //--- Stacks                                               ---//
 //------------------------------------------------------------//


@@ -1862,17 +1981,16 @@ static Bool ms_handle_client_request ( ThreadId tid, UWord* argv, UWord* ret )
 {
    switch (argv[0]) {
    case VG_USERREQ__MALLOCLIKE_BLOCK: {
 {
    switch (argv[0]) {
    case VG_USERREQ__MALLOCLIKE_BLOCK: {

-      void* res;

       void* p   = (void*)argv[1];
       SizeT szB =        argv[2];
       void* p   = (void*)argv[1];
       SizeT szB =        argv[2];

-      res = new_block( tid, p, szB, /*alignB--ignored*/0, /*is_zeroed*/False );
-      tl_assert(res == p);
+      record_block( tid, p, szB, /*slop_szB*/0, /*exclude_first_entry*/False,
+                    /*maybe_snapshot*/True );

       *ret = 0;
       return True;
    }
    case VG_USERREQ__FREELIKE_BLOCK: {
       void* p = (void*)argv[1];
       *ret = 0;
       return True;
    }
    case VG_USERREQ__FREELIKE_BLOCK: {
       void* p = (void*)argv[1];

-      die_block( p, /*custom_free*/True );
+      unrecord_block(p, /*maybe_snapshot*/True);

       *ret = 0;
       return True;
    }
       *ret = 0;
       return True;
    }


@@ -2019,8 +2137,15 @@ static void pp_snapshot_SXPt(Int fd, SXPt* sxpt, Int depth, Char* depth_str,
     case SigSXPt:
       // Print the SXPt itself.
       if (0 == depth) {
     case SigSXPt:
       // Print the SXPt itself.
       if (0 == depth) {

-         ip_desc =
-            "(heap allocation functions) malloc/new/new[], --alloc-fns, etc.";
+         if (clo_heap) {
+            ip_desc = 
+               ( clo_pages_as_heap
+               ? "(page allocation syscalls) mmap/mremap/brk, --alloc-fns, etc."
+               : "(heap allocation functions) malloc/new/new[], --alloc-fns, etc."
+               );
+         } else {
+            // XXX: --alloc-fns?
+         }

       } else {
          // If it's main-or-below-main, we (if appropriate) ignore everything
          // below it by pretending it has no children.
       } else {
          // If it's main-or-below-main, we (if appropriate) ignore everything
          // below it by pretending it has no children.


@@ -2261,17 +2386,52 @@ static void ms_fini(Int exit_status)
 static void ms_post_clo_init(void)
 {
    Int i;
 static void ms_post_clo_init(void)
 {
    Int i;

+   Char* LD_PRELOAD_val;
+   Char* s;
+   Char* s2;

 
    // Check options.
 
    // Check options.

-   if (clo_threshold < 0 || clo_threshold > 100) {
-      VG_(umsg)("--threshold must be between 0.0 and 100.0\n");
-      VG_(err_bad_option)("--threshold");
+   if (clo_pages_as_heap) {
+      if (clo_stacks) {
+         VG_(fmsg_bad_option)(
+            "--pages-as-heap=yes together with --stacks=yes", "");
+      }

    }
    }

-
-   // If we have --heap=no, set --heap-admin to zero, just to make sure we
-   // don't accidentally use a non-zero heap-admin size somewhere.

    if (!clo_heap) {
    if (!clo_heap) {

-      clo_heap_admin = 0;
+      clo_pages_as_heap = False;
+   }
+
+   // If --pages-as-heap=yes we don't want malloc replacement to occur.  So we
+   // disable vgpreload_massif-$PLATFORM.so by removing it from LD_PRELOAD (or
+   // platform-equivalent).  We replace it entirely with spaces because then
+   // the linker doesn't complain (it does complain if we just change the name
+   // to a bogus file).  This is a bit of a hack, but LD_PRELOAD is setup well
+   // before tool initialisation, so this seems the best way to do it.
+   if (clo_pages_as_heap) {
+      clo_heap_admin = 0;     // No heap admin on pages.
+
+      LD_PRELOAD_val = VG_(getenv)( (Char*)VG_(LD_PRELOAD_var_name) );
+      tl_assert(LD_PRELOAD_val);
+
+      // Make sure the vgpreload_core-$PLATFORM entry is there, for sanity.
+      s2 = VG_(strstr)(LD_PRELOAD_val, "vgpreload_core");
+      tl_assert(s2);
+
+      // Now find the vgpreload_massif-$PLATFORM entry.
+      s2 = VG_(strstr)(LD_PRELOAD_val, "vgpreload_massif");
+      tl_assert(s2);
+
+      // Blank out everything to the previous ':', which must be there because
+      // of the preceding vgpreload_core-$PLATFORM entry.
+      for (s = s2; *s != ':'; s--) {
+         *s = ' ';
+      }
+
+      // Blank out everything to the end of the entry, which will be '\0' if
+      // LD_PRELOAD was empty before Valgrind started, or ':' otherwise.
+      for (s = s2; *s != ':' && *s != '\0'; s++) {
+         *s = ' ';
+      }

    }
 
    // Print alloc-fns and ignore-fns, if necessary.
    }
 
    // Print alloc-fns and ignore-fns, if necessary.


@@ -2300,6 +2460,17 @@ static void ms_post_clo_init(void)
       VG_(track_die_mem_stack_signal) ( die_mem_stack_signal );
    }
 
       VG_(track_die_mem_stack_signal) ( die_mem_stack_signal );
    }
 

+   if (clo_pages_as_heap) {
+      VG_(track_new_mem_startup) ( ms_new_mem_startup );
+      VG_(track_new_mem_brk)     ( ms_new_mem_brk     );
+      VG_(track_new_mem_mmap)    ( ms_new_mem_mmap    );
+
+      VG_(track_copy_mem_remap)  ( ms_copy_mem_remap  );
+
+      VG_(track_die_mem_brk)     ( ms_die_mem_brk     );
+      VG_(track_die_mem_munmap)  ( ms_die_mem_munmap  ); 
+   }
+

    // Initialise snapshot array, and sanity-check it.
    snapshots = VG_(malloc)("ms.main.mpoci.1", 
                            sizeof(Snapshot) * clo_max_snapshots);
    // Initialise snapshot array, and sanity-check it.
    snapshots = VG_(malloc)("ms.main.mpoci.1", 
                            sizeof(Snapshot) * clo_max_snapshots);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/perf/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/perf/Makefile.in
index 821cb2db48f464dfa9e8460f1b6c53854b2cf81c..cd0dec02431870c0c0b80030c2cc3e071095f891 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/perf/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/perf/Makefile.in
@@ -108,6 +108,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -142,14 +143,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -232,7 +237,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -291,7 +298,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -306,8 +313,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/tests/Makefile.in
index 1fdd735d31ee1f205366a21d101b6e46be3e2694..8e244c43e82567b2c92afa079554abd2e7f0fe2b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/massif/tests/Makefile.in
@@ -189,6 +189,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -223,14 +224,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -313,7 +318,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -372,7 +379,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -387,8 +394,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/Makefile.am
index 50849c568ad44526bcb9d9537d93345fe9dc669c..5f8fd2e2fe886a2ed50d4e65f929160f4d2a5c36 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/Makefile.am
@@ -31,7 +31,8 @@ MEMCHECK_SOURCES_COMMON = \
        mc_machine.c \
        mc_errors.c
 
        mc_machine.c \
        mc_errors.c
 

-memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = $(MEMCHECK_SOURCES_COMMON)
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = \
+       $(MEMCHECK_SOURCES_COMMON)

 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \


@@ -42,8 +43,16 @@ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 if VGCONF_HAVE_PLATFORM_SEC

-memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = $(MEMCHECK_SOURCES_COMMON)
+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
+       $(MEMCHECK_SOURCES_COMMON)

 memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \
 memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \


@@ -54,6 +63,12 @@ memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 mc_main.o: CFLAGS += -fomit-frame-pointer
 endif
 
 mc_main.o: CFLAGS += -fomit-frame-pointer


@@ -84,6 +99,7 @@ vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_DEPENDENCIES = \
 vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS      = \
        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+

 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = \
        $(VGPRELOAD_MEMCHECK_SOURCES_COMMON)
 if VGCONF_HAVE_PLATFORM_SEC
 vgpreload_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_so_SOURCES      = \
        $(VGPRELOAD_MEMCHECK_SOURCES_COMMON)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/Makefile.in
index 887cef867370dc1e2e414491923d90071f746155..484648bc021dd286a2a23c5e999a2f2ac5134a1d 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/Makefile.in
@@ -45,29 +45,13 @@ host_triplet = @host@
 DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
        $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
 DIST_COMMON = $(noinst_HEADERS) $(pkginclude_HEADERS) \
        $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)
 noinst_PROGRAMS = memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1) \
        vgpreload_memcheck-@VGCONF_ARCH_PRI@-@VGCONF_OS@.so$(EXEEXT) \
        $(am__EXEEXT_2)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_14 = vgpreload_memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_2 = vgpreload_memcheck-@VGCONF_ARCH_SEC@-@VGCONF_OS@.so

 subdir = memcheck
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = memcheck
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -90,10 +74,6 @@ am__objects_1 =  \
 am_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
 am_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) \
-       -o $@

 am__memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST =  \
        mc_leakcheck.c mc_malloc_wrappers.c mc_main.c mc_translate.c \
        mc_machine.c mc_errors.c
 am__memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST =  \
        mc_leakcheck.c mc_malloc_wrappers.c mc_main.c mc_translate.c \
        mc_machine.c mc_errors.c


@@ -108,10 +88,6 @@ am__objects_2 =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) \
-       -o $@

 am__objects_3 = vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.$(OBJEXT)
 am_vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =  \
        $(am__objects_3)
 am__objects_3 = vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so-mc_replace_strmem.$(OBJEXT)
 am_vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_OBJECTS =  \
        $(am__objects_3)


@@ -251,6 +227,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -285,14 +262,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -376,7 +357,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -435,7 +418,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -450,8 +433,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -514,37 +497,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -553,32 +536,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -674,7 +653,9 @@ MEMCHECK_SOURCES_COMMON = \
        mc_machine.c \
        mc_errors.c
 
        mc_machine.c \
        mc_errors.c
 

-memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(MEMCHECK_SOURCES_COMMON)
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+       $(MEMCHECK_SOURCES_COMMON)
+

 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 


@@ -690,7 +671,16 @@ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(MEMCHECK_SOURCES_COMMON)
+memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(MEMCHECK_SOURCES_COMMON)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 


@@ -706,6 +696,13 @@ memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

+@VGCONF_HAVE_PLATFORM_SEC_TRUE@memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(memcheck_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+

 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 VGPRELOAD_MEMCHECK_SOURCES_COMMON = mc_replace_strmem.c
 vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(noinst_PROGRAMS)
 VGPRELOAD_MEMCHECK_SOURCES_COMMON = mc_replace_strmem.c
 vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_SOURCES = \


@@ -740,8 +737,7 @@ vgpreload_memcheck_@VGCONF_ARCH_PRI@_@VGCONF_OS@_so_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(PRELOAD_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@) \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LIBREPLACEMALLOC_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -1236,16 +1232,14 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(pkgincludedir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done
 all-am: Makefile $(PROGRAMS) $(HEADERS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
        for dir in "$(DESTDIR)$(pkgincludedir)"; do \
          test -z "$$dir" || $(MKDIR_P) "$$dir"; \
        done

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -1262,7 +1256,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -1271,7 +1264,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1342,9 +1334,8 @@ ps-am:
 
 uninstall-am: uninstall-pkgincludeHEADERS
 
 
 uninstall-am: uninstall-pkgincludeHEADERS
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1427,65 +1418,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/docs/mc-manual.xml b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/docs/mc-manual.xml
index 3ee00f21dc69193b8582aeae2eb68ba3e1c47c39..4c75629d1f61d70df88971a2814bca97f2808413 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/docs/mc-manual.xml
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/docs/mc-manual.xml
@@ -620,6 +620,16 @@ criteria:</para>
     </listitem>
   </varlistentry>
 
     </listitem>
   </varlistentry>
 

+  <varlistentry id="opt.show-possibly-lost" xreflabel="--show-possibly-lost">
+    <term>
+      <option><![CDATA[--show-possibly-lost=<yes|no> [default: yes] ]]></option>
+    </term>
+    <listitem>
+      <para>When disabled, the memory leak detector will not show "possibly lost" blocks.  
+      </para>
+    </listitem>
+  </varlistentry>
+

   <varlistentry id="opt.leak-resolution" xreflabel="--leak-resolution">
     <term>
       <option><![CDATA[--leak-resolution=<low|med|high> [default: high] ]]></option>
   <varlistentry id="opt.leak-resolution" xreflabel="--leak-resolution">
     <term>
       <option><![CDATA[--leak-resolution=<low|med|high> [default: high] ]]></option>

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_errors.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_errors.c
index e30855e18aad7e03680f4015853e612d5a85cb80..64cb805b6d59b10730a18dc77a3b2b46dab572bf 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_errors.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_errors.c
@@ -770,6 +770,7 @@ void MC_(pp_Error) ( Error* err )
    for the --workaround-gcc296-bugs kludge. */
 static Bool is_just_below_ESP( Addr esp, Addr aa )
 {
    for the --workaround-gcc296-bugs kludge. */
 static Bool is_just_below_ESP( Addr esp, Addr aa )
 {

+   esp -= VG_STACK_REDZONE_SZB;

    if (esp > aa && (esp - aa) <= VG_GCC296_BUG_STACK_SLOP)
       return True;
    else
    if (esp > aa && (esp - aa) <= VG_GCC296_BUG_STACK_SLOP)
       return True;
    else

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_include.h b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_include.h
index 76061985ff190787ea949b7c142a1b5059f87eaa..c2ef03eb65fa0f5a9658f1ed00118bec2780900a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_include.h
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_include.h
@@ -395,6 +395,9 @@ extern VgRes MC_(clo_leak_resolution);
 /* In leak check, show reachable-but-not-freed blocks?  default: NO */
 extern Bool MC_(clo_show_reachable);
 
 /* In leak check, show reachable-but-not-freed blocks?  default: NO */
 extern Bool MC_(clo_show_reachable);
 

+/* In leak check, show possibly-lost blocks?  default: YES */
+extern Bool MC_(clo_show_possibly_lost);
+

 /* Assume accesses immediately below %esp are due to gcc-2.96 bugs.
  * default: NO */
 extern Bool MC_(clo_workaround_gcc296_bugs);
 /* Assume accesses immediately below %esp are due to gcc-2.96 bugs.
  * default: NO */
 extern Bool MC_(clo_workaround_gcc296_bugs);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_leakcheck.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_leakcheck.c
index 9bd050a6fa905d476ca713bca6edc86654e1eda7..2d3e6d6b7bf776ff2bc5b46a415f8ce051c715ff 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_leakcheck.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_leakcheck.c
@@ -845,7 +845,8 @@ static void print_results(ThreadId tid, Bool is_full_check)
       print_record = is_full_check &&
                      ( MC_(clo_show_reachable) ||
                        Unreached == lr->key.state || 
       print_record = is_full_check &&
                      ( MC_(clo_show_reachable) ||
                        Unreached == lr->key.state || 

-                       Possible  == lr->key.state );
+                       ( MC_(clo_show_possibly_lost) && 
+                         Possible  == lr->key.state ) );

       // We don't count a leaks as errors with --leak-check=summary.
       // Otherwise you can get high error counts with few or no error
       // messages, which can be confusing.  Also, you could argue that
       // We don't count a leaks as errors with --leak-check=summary.
       // Otherwise you can get high error counts with few or no error
       // messages, which can be confusing.  Also, you could argue that

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_machine.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_machine.c
index 823e7ae2f8e1a9ab41aa12cafc6f221842f15c90..61494d9e3c490c43daa21e4fff5f7d194f83753e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_machine.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_machine.c
@@ -536,6 +536,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
    if (o >= GOF(XMM13) && o+sz <= GOF(XMM13)+SZB(XMM13)) return GOF(XMM13);
    if (o >= GOF(XMM14) && o+sz <= GOF(XMM14)+SZB(XMM14)) return GOF(XMM14);
    if (o >= GOF(XMM15) && o+sz <= GOF(XMM15)+SZB(XMM15)) return GOF(XMM15);
    if (o >= GOF(XMM13) && o+sz <= GOF(XMM13)+SZB(XMM13)) return GOF(XMM13);
    if (o >= GOF(XMM14) && o+sz <= GOF(XMM14)+SZB(XMM14)) return GOF(XMM14);
    if (o >= GOF(XMM15) && o+sz <= GOF(XMM15)+SZB(XMM15)) return GOF(XMM15);

+   if (o >= GOF(XMM16) && o+sz <= GOF(XMM16)+SZB(XMM16)) return GOF(XMM16);

 
    /* MMX accesses to FP regs.  Need to allow for 32-bit references
       due to dirty helpers for frstor etc, which reference the entire
 
    /* MMX accesses to FP regs.  Need to allow for 32-bit references
       due to dirty helpers for frstor etc, which reference the entire


@@ -710,7 +711,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
    if (o == GOF(R14) && sz == 4) return o;
 
    /* EAZG: These may be completely wrong. */
    if (o == GOF(R14) && sz == 4) return o;
 
    /* EAZG: These may be completely wrong. */

-   if (o == GOF(R15)   && sz == 4) return -1; /* slot unused */
+   if (o == GOF(R15T)  && sz == 4) return -1; /* slot unused */

    if (o == GOF(CC_OP) && sz == 4) return -1; /* slot unused */
 
    if (o == GOF(CC_DEP1) && sz == 4) return o;
    if (o == GOF(CC_OP) && sz == 4) return -1; /* slot unused */
 
    if (o == GOF(CC_DEP1) && sz == 4) return o;


@@ -718,6 +719,8 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
 
    if (o == GOF(CC_NDEP) && sz == 4) return -1; /* slot unused */
 
 
    if (o == GOF(CC_NDEP) && sz == 4) return -1; /* slot unused */
 

+   if (o == GOF(QFLAG32) && sz == 4) return o;
+

    //if (o == GOF(SYSCALLNO)     && sz == 4) return -1; /* slot unused */
    //if (o == GOF(CC)     && sz == 4) return -1; /* slot unused */
    //if (o == GOF(EMWARN)     && sz == 4) return -1; /* slot unused */
    //if (o == GOF(SYSCALLNO)     && sz == 4) return -1; /* slot unused */
    //if (o == GOF(CC)     && sz == 4) return -1; /* slot unused */
    //if (o == GOF(EMWARN)     && sz == 4) return -1; /* slot unused */


@@ -726,6 +729,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
 
    if (o == GOF(FPSCR)    && sz == 4) return -1;
    if (o == GOF(TPIDRURO) && sz == 4) return -1;
 
    if (o == GOF(FPSCR)    && sz == 4) return -1;
    if (o == GOF(TPIDRURO) && sz == 4) return -1;

+   if (o == GOF(ITSTATE)  && sz == 4) return -1;

 
    if (o >= GOF(D0)  && o+sz <= GOF(D0) +SZB(D0))  return GOF(D0);
    if (o >= GOF(D1)  && o+sz <= GOF(D1) +SZB(D1))  return GOF(D1);
 
    if (o >= GOF(D0)  && o+sz <= GOF(D0) +SZB(D0))  return GOF(D0);
    if (o >= GOF(D1)  && o+sz <= GOF(D1) +SZB(D1))  return GOF(D1);

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_main.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_main.c
index 20cefc7bbd25a52824c656cb26c74c979211094b..0dee75c063c709f65990036ab811bd3cc7f6f1d4 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_main.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_main.c
@@ -4747,6 +4747,7 @@ Long          MC_(clo_freelist_vol)           = 10*1000*1000LL;
 LeakCheckMode MC_(clo_leak_check)             = LC_Summary;
 VgRes         MC_(clo_leak_resolution)        = Vg_HighRes;
 Bool          MC_(clo_show_reachable)         = False;
 LeakCheckMode MC_(clo_leak_check)             = LC_Summary;
 VgRes         MC_(clo_leak_resolution)        = Vg_HighRes;
 Bool          MC_(clo_show_reachable)         = False;

+Bool          MC_(clo_show_possibly_lost)     = True;

 Bool          MC_(clo_workaround_gcc296_bugs) = False;
 Int           MC_(clo_malloc_fill)            = -1;
 Int           MC_(clo_free_fill)              = -1;
 Bool          MC_(clo_workaround_gcc296_bugs) = False;
 Int           MC_(clo_malloc_fill)            = -1;
 Int           MC_(clo_free_fill)              = -1;


@@ -4755,8 +4756,6 @@ Int           MC_(clo_mc_level)               = 2;
 static Bool mc_process_cmd_line_options(Char* arg)
 {
    Char* tmp_str;
 static Bool mc_process_cmd_line_options(Char* arg)
 {
    Char* tmp_str;

-   Char* bad_level_msg =
-      "ERROR: --track-origins=yes has no effect when --undef-value-errors=no";

 
    tl_assert( MC_(clo_mc_level) >= 1 && MC_(clo_mc_level) <= 3 );
 
 
    tl_assert( MC_(clo_mc_level) >= 1 && MC_(clo_mc_level) <= 3 );
 


@@ -4771,8 +4770,7 @@ static Bool mc_process_cmd_line_options(Char* arg)
    */
    if (0 == VG_(strcmp)(arg, "--undef-value-errors=no")) {
       if (MC_(clo_mc_level) == 3) {
    */
    if (0 == VG_(strcmp)(arg, "--undef-value-errors=no")) {
       if (MC_(clo_mc_level) == 3) {

-         VG_(message)(Vg_DebugMsg, "%s\n", bad_level_msg);
-         return False;
+         goto bad_level;

       } else {
          MC_(clo_mc_level) = 1;
          return True;
       } else {
          MC_(clo_mc_level) = 1;
          return True;


@@ -4790,8 +4788,7 @@ static Bool mc_process_cmd_line_options(Char* arg)
    }
    if (0 == VG_(strcmp)(arg, "--track-origins=yes")) {
       if (MC_(clo_mc_level) == 1) {
    }
    if (0 == VG_(strcmp)(arg, "--track-origins=yes")) {
       if (MC_(clo_mc_level) == 1) {

-         VG_(message)(Vg_DebugMsg, "%s\n", bad_level_msg);
-         return False;
+         goto bad_level;

       } else {
          MC_(clo_mc_level) = 3;
          return True;
       } else {
          MC_(clo_mc_level) = 3;
          return True;


@@ -4800,6 +4797,8 @@ static Bool mc_process_cmd_line_options(Char* arg)
 
        if VG_BOOL_CLO(arg, "--partial-loads-ok", MC_(clo_partial_loads_ok)) {}
    else if VG_BOOL_CLO(arg, "--show-reachable",   MC_(clo_show_reachable))   {}
 
        if VG_BOOL_CLO(arg, "--partial-loads-ok", MC_(clo_partial_loads_ok)) {}
    else if VG_BOOL_CLO(arg, "--show-reachable",   MC_(clo_show_reachable))   {}

+   else if VG_BOOL_CLO(arg, "--show-possibly-lost",
+                                            MC_(clo_show_possibly_lost))     {}

    else if VG_BOOL_CLO(arg, "--workaround-gcc296-bugs",
                                             MC_(clo_workaround_gcc296_bugs)) {}
 
    else if VG_BOOL_CLO(arg, "--workaround-gcc296-bugs",
                                             MC_(clo_workaround_gcc296_bugs)) {}
 


@@ -4857,6 +4856,11 @@ static Bool mc_process_cmd_line_options(Char* arg)
       return VG_(replacement_malloc_process_cmd_line_option)(arg);
 
    return True;
       return VG_(replacement_malloc_process_cmd_line_option)(arg);
 
    return True;

+
+
+  bad_level:
+   VG_(fmsg_bad_option)(arg,
+      "--track-origins=yes has no effect when --undef-value-errors=no.\n");

 }
 
 static void mc_print_usage(void)
 }
 
 static void mc_print_usage(void)


@@ -4865,6 +4869,8 @@ static void mc_print_usage(void)
 "    --leak-check=no|summary|full     search for memory leaks at exit?  [summary]\n"
 "    --leak-resolution=low|med|high   differentiation of leak stack traces [high]\n"
 "    --show-reachable=no|yes          show reachable blocks in leak check? [no]\n"
 "    --leak-check=no|summary|full     search for memory leaks at exit?  [summary]\n"
 "    --leak-resolution=low|med|high   differentiation of leak stack traces [high]\n"
 "    --show-reachable=no|yes          show reachable blocks in leak check? [no]\n"

+"    --show-possibly-lost=no|yes      show possibly lost blocks in leak check?\n"
+"                                     [yes]\n"

 "    --undef-value-errors=no|yes      check for undefined value errors [yes]\n"
 "    --track-origins=no|yes           show origins of undefined values? [no]\n"
 "    --partial-loads-ok=no|yes        too hard to explain here; see manual [no]\n"
 "    --undef-value-errors=no|yes      check for undefined value errors [yes]\n"
 "    --track-origins=no|yes           show origins of undefined values? [no]\n"
 "    --partial-loads-ok=no|yes        too hard to explain here; see manual [no]\n"

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_replace_strmem.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_replace_strmem.c
index e7cae0494e2f36ec960337371f378fa86a09a1c7..d500367f38aa4365f19ab326de76b7bcfb1606a1 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_replace_strmem.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_replace_strmem.c
@@ -455,42 +455,68 @@ MEMCHR(VG_Z_DYLD,        memchr)
    void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
             ( void *dst, const void *src, SizeT len ) \
    { \
    void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
             ( void *dst, const void *src, SizeT len ) \
    { \

-      register char *d; \
-      register char *s; \
-      \
-      if (len == 0) \
-         return dst; \
-      \

       if (is_overlap(dst, src, len, len)) \
          RECORD_OVERLAP_ERROR("memcpy", dst, src, len); \
       \
       if (is_overlap(dst, src, len, len)) \
          RECORD_OVERLAP_ERROR("memcpy", dst, src, len); \
       \

-      if ( dst > src ) { \
-         d = (char *)dst + len - 1; \
-         s = (char *)src + len - 1; \
-         while ( len >= 4 ) { \
-            *d-- = *s--; \
-            *d-- = *s--; \
-            *d-- = *s--; \
-            *d-- = *s--; \
-            len -= 4; \
+      const Addr WS = sizeof(UWord); /* 8 or 4 */ \
+      const Addr WM = WS - 1;        /* 7 or 3 */ \
+      \
+      if (dst < src) { \
+      \
+         /* Copying backwards. */ \
+         SizeT n = len; \
+         Addr  d = (Addr)dst; \
+         Addr  s = (Addr)src; \
+         \
+         if (((s^d) & WM) == 0) { \
+            /* s and d have same UWord alignment. */ \
+            /* Pull up to a UWord boundary. */ \
+            while ((s & WM) != 0 && n >= 1) \
+               { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \
+            /* Copy UWords. */ \
+            while (n >= WS) \
+               { *(UWord*)d = *(UWord*)s; s += WS; d += WS; n -= WS; } \
+            if (n == 0) \
+               return dst; \

          } \
          } \

-         while ( len-- ) { \
-            *d-- = *s--; \
+         if (((s|d) & 1) == 0) { \
+            /* Both are 16-aligned; copy what we can thusly. */ \
+            while (n >= 2) \
+               { *(UShort*)d = *(UShort*)s; s += 2; d += 2; n -= 2; } \

          } \
          } \

-      } else if ( dst < src ) { \
-         d = (char *)dst; \
-         s = (char *)src; \
-         while ( len >= 4 ) { \
-            *d++ = *s++; \
-            *d++ = *s++; \
-            *d++ = *s++; \
-            *d++ = *s++; \
-            len -= 4; \
+         /* Copy leftovers, or everything if misaligned. */ \
+         while (n >= 1) \
+            { *(UChar*)d = *(UChar*)s; s += 1; d += 1; n -= 1; } \
+      \
+      } else if (dst > src) { \
+      \
+         SizeT n = len; \
+         Addr  d = ((Addr)dst) + n; \
+         Addr  s = ((Addr)src) + n; \
+         \
+         /* Copying forwards. */ \
+         if (((s^d) & WM) == 0) { \
+            /* s and d have same UWord alignment. */ \
+            /* Back down to a UWord boundary. */ \
+            while ((s & WM) != 0 && n >= 1) \
+               { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \
+            /* Copy UWords. */ \
+            while (n >= WS) \
+               { s -= WS; d -= WS; *(UWord*)d = *(UWord*)s; n -= WS; } \
+            if (n == 0) \
+               return dst; \

          } \
          } \

-         while ( len-- ) { \
-            *d++ = *s++; \
+         if (((s|d) & 1) == 0) { \
+            /* Both are 16-aligned; copy what we can thusly. */ \
+            while (n >= 2) \
+               { s -= 2; d -= 2; *(UShort*)d = *(UShort*)s; n -= 2; } \

          } \
          } \

+         /* Copy leftovers, or everything if misaligned. */ \
+         while (n >= 1) \
+            { s -= 1; d -= 1; *(UChar*)d = *(UChar*)s; n -= 1; } \
+         \

       } \
       } \

+      \

       return dst; \
    }
 
       return dst; \
    }
 


@@ -584,18 +610,16 @@ STPCPY(VG_Z_DYLD,                 stpcpy)
    void* VG_REPLACE_FUNCTION_ZU(soname,fnname)(void *s, Int c, SizeT n); \
    void* VG_REPLACE_FUNCTION_ZU(soname,fnname)(void *s, Int c, SizeT n) \
    { \
    void* VG_REPLACE_FUNCTION_ZU(soname,fnname)(void *s, Int c, SizeT n); \
    void* VG_REPLACE_FUNCTION_ZU(soname,fnname)(void *s, Int c, SizeT n) \
    { \

-      unsigned char *cp = s; \
-      while (n >= 4) { \
-         cp[0] = c; \
-         cp[1] = c; \
-         cp[2] = c; \
-         cp[3] = c; \
-         cp += 4; \
-         n -= 4; \
-      } \
-      while (n--) { \
-         *cp++ = c; \
-      } \
+      Addr a  = (Addr)s;   \
+      UInt c4 = (c & 0xFF); \
+      c4 = (c4 << 8) | c4; \
+      c4 = (c4 << 16) | c4; \
+      while ((a & 3) != 0 && n >= 1) \
+         { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \
+      while (n >= 4) \
+         { *(UInt*)a = c4; a += 4; n -= 4; } \
+      while (n >= 1) \
+         { *(UChar*)a = (UChar)c; a += 1; n -= 1; } \

       return s; \
    }
 
       return s; \
    }
 


@@ -867,6 +891,153 @@ GLIBC25_MEMPCPY(VG_Z_LD_SO_1,     mempcpy) /* ld.so.1 */
 GLIBC26___MEMCPY_CHK(VG_Z_LIBC_SONAME, __memcpy_chk)
 
 
 GLIBC26___MEMCPY_CHK(VG_Z_LIBC_SONAME, __memcpy_chk)
 
 

+#define STRSTR(soname, fnname) \
+   void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* haystack, void* needle); \
+   void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* haystack, void* needle) \
+   { \
+      UChar* h = (UChar*)haystack; \
+      UChar* n = (UChar*)needle; \
+      \
+      /* find the length of n, not including terminating zero */ \
+      UWord nlen = 0; \
+      while (n[nlen]) nlen++; \
+      \
+      /* if n is the empty string, match immediately. */ \
+      if (nlen == 0) return h; \
+      \
+      /* assert(nlen >= 1); */ \
+      UChar n0 = n[0]; \
+      \
+      while (1) { \
+         UChar hh = *h; \
+         if (hh == 0) return NULL; \
+         if (hh != n0) { h++; continue; } \
+         \
+         UWord i; \
+         for (i = 0; i < nlen; i++) { \
+            if (n[i] != h[i]) \
+               break; \
+         } \
+         /* assert(i >= 0 && i <= nlen); */ \
+         if (i == nlen) \
+            return h; \
+         \
+         h++; \
+      } \
+   }
+
+#if defined(VGO_linux)
+STRSTR(VG_Z_LIBC_SONAME,          strstr)
+#endif
+
+
+#define STRPBRK(soname, fnname) \
+   void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* sV, void* acceptV); \
+   void* VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* sV, void* acceptV) \
+   { \
+      UChar* s = (UChar*)sV; \
+      UChar* accept = (UChar*)acceptV; \
+      \
+      /*  find the length of 'accept', not including terminating zero */ \
+      UWord nacc = 0; \
+      while (accept[nacc]) nacc++; \
+      \
+      /* if n is the empty string, fail immediately. */ \
+      if (nacc == 0) return NULL; \
+      \
+      /* assert(nacc >= 1); */ \
+      while (1) { \
+         UWord i; \
+         UChar sc = *s; \
+         if (sc == 0) \
+            break; \
+         for (i = 0; i < nacc; i++) { \
+            if (sc == accept[i]) \
+               return s; \
+         } \
+         s++; \
+      } \
+      \
+      return NULL; \
+   }
+
+#if defined(VGO_linux)
+STRPBRK(VG_Z_LIBC_SONAME,          strpbrk)
+#endif
+
+
+#define STRCSPN(soname, fnname) \
+   SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* sV, void* rejectV); \
+   SizeT VG_REPLACE_FUNCTION_ZU(soname,fnname) \
+         (void* sV, void* rejectV) \
+   { \
+      UChar* s = (UChar*)sV; \
+      UChar* reject = (UChar*)rejectV; \
+      \
+      /* find the length of 'reject', not including terminating zero */ \
+      UWord nrej = 0; \
+      while (reject[nrej]) nrej++; \
+      \
+      UWord len = 0; \
+      while (1) { \
+         UWord i; \
+         UChar sc = *s; \
+         if (sc == 0) \
+            break; \
+         for (i = 0; i < nrej; i++) { \
+            if (sc == reject[i]) \
+               break; \
+         } \
+         /* assert(i >= 0 && i <= nrej); */ \
+         if (i < nrej) \
+            break; \
+         s++; \
+         len++; \
+      } \
+      \
+      return len; \
+   }
+
+#if defined(VGO_linux)
+STRCSPN(VG_Z_LIBC_SONAME,          strcspn)
+#endif
+
+
+// And here's a validated strspn replacement, should it
+// become necessary.
+//UWord mystrspn( UChar* s, UChar* accept )
+//{
+//   /* find the length of 'accept', not including terminating zero */
+//   UWord nacc = 0;
+//   while (accept[nacc]) nacc++;
+//   if (nacc == 0) return 0;
+//
+//   UWord len = 0;
+//   while (1) {
+//      UWord i;
+//      UChar sc = *s;
+//      if (sc == 0)
+//         break;
+//      for (i = 0; i < nacc; i++) {
+//         if (sc == accept[i])
+//            break;
+//      }
+//      assert(i >= 0 && i <= nacc);
+//      if (i == nacc)
+//         break;
+//      s++;
+//      len++;
+//   }
+//
+//   return len;
+//}
+
+

 /*------------------------------------------------------------*/
 /*--- Improve definedness checking of process environment  ---*/
 /*------------------------------------------------------------*/
 /*------------------------------------------------------------*/
 /*--- Improve definedness checking of process environment  ---*/
 /*------------------------------------------------------------*/

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_translate.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_translate.c
index 3531363f6929b7e0548b7393af33ac0bbf37fb4a..394bec29c2182eb242658832fb2d24b02f18a841 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_translate.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/mc_translate.c
@@ -398,6 +398,8 @@ void assign ( HChar cat, MCEnv* mce, IRTemp tmp, IRExpr* expr ) {
 }
 
 /* build various kinds of expressions */
 }
 
 /* build various kinds of expressions */

+#define triop(_op, _arg1, _arg2, _arg3) \
+                                 IRExpr_Triop((_op),(_arg1),(_arg2),(_arg3))

 #define binop(_op, _arg1, _arg2) IRExpr_Binop((_op),(_arg1),(_arg2))
 #define unop(_op, _arg)          IRExpr_Unop((_op),(_arg))
 #define mkU8(_n)                 IRExpr_Const(IRConst_U8(_n))
 #define binop(_op, _arg1, _arg2) IRExpr_Binop((_op),(_arg1),(_arg2))
 #define unop(_op, _arg)          IRExpr_Unop((_op),(_arg))
 #define mkU8(_n)                 IRExpr_Const(IRConst_U8(_n))


@@ -1849,6 +1851,28 @@ IRAtom* unary64F0x2 ( MCEnv* mce, IRAtom* vatomX )
    return at;
 }
 
    return at;
 }
 

+/* --- --- ... and ... 32Fx2 versions of the same --- --- */
+
+static
+IRAtom* binary32Fx2 ( MCEnv* mce, IRAtom* vatomX, IRAtom* vatomY )
+{
+   IRAtom* at;
+   tl_assert(isShadowAtom(mce, vatomX));
+   tl_assert(isShadowAtom(mce, vatomY));
+   at = mkUifU64(mce, vatomX, vatomY);
+   at = assignNew('V', mce, Ity_I64, mkPCast32x2(mce, at));
+   return at;
+}
+
+static
+IRAtom* unary32Fx2 ( MCEnv* mce, IRAtom* vatomX )
+{
+   IRAtom* at;
+   tl_assert(isShadowAtom(mce, vatomX));
+   at = assignNew('V', mce, Ity_I64, mkPCast32x2(mce, vatomX));
+   return at;
+}
+

 /* --- --- Vector saturated narrowing --- --- */
 
 /* This is quite subtle.  What to do is simple:
 /* --- --- Vector saturated narrowing --- --- */
 
 /* This is quite subtle.  What to do is simple:


@@ -1918,6 +1942,54 @@ IRAtom* vectorNarrow64 ( MCEnv* mce, IROp narrow_op,
    return at3;
 }
 
    return at3;
 }
 

+static
+IRAtom* vectorShortenV128 ( MCEnv* mce, IROp shorten_op,
+                          IRAtom* vatom1)
+{
+   IRAtom *at1, *at2;
+   IRAtom* (*pcast)( MCEnv*, IRAtom* );
+   switch (shorten_op) {
+      case Iop_Shorten16x8: pcast = mkPCast16x8; break;
+      case Iop_Shorten32x4: pcast = mkPCast32x4; break;
+      case Iop_Shorten64x2: pcast = mkPCast64x2; break;
+      case Iop_QShortenS16Sx8: pcast = mkPCast16x8; break;
+      case Iop_QShortenU16Sx8: pcast = mkPCast16x8; break;
+      case Iop_QShortenU16Ux8: pcast = mkPCast16x8; break;
+      case Iop_QShortenS32Sx4: pcast = mkPCast32x4; break;
+      case Iop_QShortenU32Sx4: pcast = mkPCast32x4; break;
+      case Iop_QShortenU32Ux4: pcast = mkPCast32x4; break;
+      case Iop_QShortenS64Sx2: pcast = mkPCast64x2; break;
+      case Iop_QShortenU64Sx2: pcast = mkPCast64x2; break;
+      case Iop_QShortenU64Ux2: pcast = mkPCast64x2; break;
+      default: VG_(tool_panic)("vectorShortenV128");
+   }
+   tl_assert(isShadowAtom(mce,vatom1));
+   at1 = assignNew('V', mce, Ity_V128, pcast(mce, vatom1));
+   at2 = assignNew('V', mce, Ity_I64, unop(shorten_op, at1));
+   return at2;
+}
+
+static
+IRAtom* vectorLongenI64 ( MCEnv* mce, IROp longen_op,
+                           IRAtom* vatom1)
+{
+   IRAtom *at1, *at2;
+   IRAtom* (*pcast)( MCEnv*, IRAtom* );
+   switch (longen_op) {
+      case Iop_Longen8Ux8: pcast = mkPCast16x8; break;
+      case Iop_Longen8Sx8: pcast = mkPCast16x8; break;
+      case Iop_Longen16Ux4: pcast = mkPCast32x4; break;
+      case Iop_Longen16Sx4: pcast = mkPCast32x4; break;
+      case Iop_Longen32Ux2: pcast = mkPCast64x2; break;
+      case Iop_Longen32Sx2: pcast = mkPCast64x2; break;
+      default: VG_(tool_panic)("vectorLongenI64");
+   }
+   tl_assert(isShadowAtom(mce,vatom1));
+   at1 = assignNew('V', mce, Ity_V128, unop(longen_op, vatom1));
+   at2 = assignNew('V', mce, Ity_V128, pcast(mce, at1));
+   return at2;
+}
+

 
 /* --- --- Vector integer arithmetic --- --- */
 
 
 /* --- --- Vector integer arithmetic --- --- */
 


@@ -1990,6 +2062,15 @@ IRAtom* binary32Ix2 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 )
    return at;   
 }
 
    return at;   
 }
 

+static
+IRAtom* binary64Ix1 ( MCEnv* mce, IRAtom* vatom1, IRAtom* vatom2 )
+{
+   IRAtom* at;
+   at = mkUifU64(mce, vatom1, vatom2);
+   at = mkPCastTo(mce, Ity_I64, at);
+   return at;
+}
+

 
 /*------------------------------------------------------------*/
 /*--- Generate shadow values from all kinds of IRExprs.    ---*/
 
 /*------------------------------------------------------------*/
 /*--- Generate shadow values from all kinds of IRExprs.    ---*/


@@ -2077,6 +2158,17 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce,
       case Iop_DivF32:
          /* I32(rm) x F32 x F32 -> I32 */
          return mkLazy3(mce, Ity_I32, vatom1, vatom2, vatom3);
       case Iop_DivF32:
          /* I32(rm) x F32 x F32 -> I32 */
          return mkLazy3(mce, Ity_I32, vatom1, vatom2, vatom3);

+      case Iop_ExtractV128:
+         complainIfUndefined(mce, atom3);
+         return assignNew('V', mce, Ity_V128, triop(op, vatom1, vatom2, atom3));
+      case Iop_Extract64:
+         complainIfUndefined(mce, atom3);
+         return assignNew('V', mce, Ity_I64, triop(op, vatom1, vatom2, atom3));
+      case Iop_SetElem8x8:
+      case Iop_SetElem16x4:
+      case Iop_SetElem32x2:
+         complainIfUndefined(mce, atom2);
+         return assignNew('V', mce, Ity_I64, triop(op, vatom1, atom2, vatom3));

       default:
          ppIROp(op);
          VG_(tool_panic)("memcheck:expr2vbits_Triop");
       default:
          ppIROp(op);
          VG_(tool_panic)("memcheck:expr2vbits_Triop");


@@ -2107,6 +2199,7 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
 
       /* 64-bit SIMD */
 
 
       /* 64-bit SIMD */
 

+      case Iop_ShrN8x8:

       case Iop_ShrN16x4:
       case Iop_ShrN32x2:
       case Iop_SarN8x8:
       case Iop_ShrN16x4:
       case Iop_ShrN32x2:
       case Iop_SarN8x8:


@@ -2125,20 +2218,29 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
          return vectorNarrow64(mce, op, vatom1, vatom2);
 
       case Iop_Min8Ux8:
          return vectorNarrow64(mce, op, vatom1, vatom2);
 
       case Iop_Min8Ux8:

+      case Iop_Min8Sx8:

       case Iop_Max8Ux8:
       case Iop_Max8Ux8:

+      case Iop_Max8Sx8:

       case Iop_Avg8Ux8:
       case Iop_QSub8Sx8:
       case Iop_QSub8Ux8:
       case Iop_Sub8x8:
       case Iop_CmpGT8Sx8:
       case Iop_Avg8Ux8:
       case Iop_QSub8Sx8:
       case Iop_QSub8Ux8:
       case Iop_Sub8x8:
       case Iop_CmpGT8Sx8:

+      case Iop_CmpGT8Ux8:

       case Iop_CmpEQ8x8:
       case Iop_QAdd8Sx8:
       case Iop_QAdd8Ux8:
       case Iop_CmpEQ8x8:
       case Iop_QAdd8Sx8:
       case Iop_QAdd8Ux8:

+      case Iop_QSal8x8:
+      case Iop_QShl8x8:

       case Iop_Add8x8:
       case Iop_Add8x8:

+      case Iop_Mul8x8:
+      case Iop_PolynomialMul8x8:

          return binary8Ix8(mce, vatom1, vatom2);
 
       case Iop_Min16Sx4:
          return binary8Ix8(mce, vatom1, vatom2);
 
       case Iop_Min16Sx4:

+      case Iop_Min16Ux4:

       case Iop_Max16Sx4:
       case Iop_Max16Sx4:

+      case Iop_Max16Ux4:

       case Iop_Avg16Ux4:
       case Iop_QSub16Ux4:
       case Iop_QSub16Sx4:
       case Iop_Avg16Ux4:
       case Iop_QSub16Ux4:
       case Iop_QSub16Sx4:


@@ -2147,19 +2249,136 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_MulHi16Sx4:
       case Iop_MulHi16Ux4:
       case Iop_CmpGT16Sx4:
       case Iop_MulHi16Sx4:
       case Iop_MulHi16Ux4:
       case Iop_CmpGT16Sx4:

+      case Iop_CmpGT16Ux4:

       case Iop_CmpEQ16x4:
       case Iop_QAdd16Sx4:
       case Iop_QAdd16Ux4:
       case Iop_CmpEQ16x4:
       case Iop_QAdd16Sx4:
       case Iop_QAdd16Ux4:

+      case Iop_QSal16x4:
+      case Iop_QShl16x4:

       case Iop_Add16x4:
       case Iop_Add16x4:

+      case Iop_QDMulHi16Sx4:
+      case Iop_QRDMulHi16Sx4:

          return binary16Ix4(mce, vatom1, vatom2);
 
       case Iop_Sub32x2:
       case Iop_Mul32x2:
          return binary16Ix4(mce, vatom1, vatom2);
 
       case Iop_Sub32x2:
       case Iop_Mul32x2:

+      case Iop_Max32Sx2:
+      case Iop_Max32Ux2:
+      case Iop_Min32Sx2:
+      case Iop_Min32Ux2:

       case Iop_CmpGT32Sx2:
       case Iop_CmpGT32Sx2:

+      case Iop_CmpGT32Ux2:

       case Iop_CmpEQ32x2:
       case Iop_Add32x2:
       case Iop_CmpEQ32x2:
       case Iop_Add32x2:

+      case Iop_QAdd32Ux2:
+      case Iop_QAdd32Sx2:
+      case Iop_QSub32Ux2:
+      case Iop_QSub32Sx2:
+      case Iop_QSal32x2:
+      case Iop_QShl32x2:
+      case Iop_QDMulHi32Sx2:
+      case Iop_QRDMulHi32Sx2:

          return binary32Ix2(mce, vatom1, vatom2);
 
          return binary32Ix2(mce, vatom1, vatom2);
 

+      case Iop_QSub64Ux1:
+      case Iop_QSub64Sx1:
+      case Iop_QAdd64Ux1:
+      case Iop_QAdd64Sx1:
+      case Iop_QSal64x1:
+      case Iop_QShl64x1:
+      case Iop_Sal64x1:
+         return binary64Ix1(mce, vatom1, vatom2);
+
+      case Iop_QShlN8Sx8:
+      case Iop_QShlN8x8:
+      case Iop_QSalN8x8:
+         complainIfUndefined(mce, atom2);
+         return mkPCast8x8(mce, vatom1);
+
+      case Iop_QShlN16Sx4:
+      case Iop_QShlN16x4:
+      case Iop_QSalN16x4:
+         complainIfUndefined(mce, atom2);
+         return mkPCast16x4(mce, vatom1);
+
+      case Iop_QShlN32Sx2:
+      case Iop_QShlN32x2:
+      case Iop_QSalN32x2:
+         complainIfUndefined(mce, atom2);
+         return mkPCast32x2(mce, vatom1);
+
+      case Iop_QShlN64Sx1:
+      case Iop_QShlN64x1:
+      case Iop_QSalN64x1:
+         complainIfUndefined(mce, atom2);
+         return mkPCast32x2(mce, vatom1);
+
+      case Iop_PwMax32Sx2:
+      case Iop_PwMax32Ux2:
+      case Iop_PwMin32Sx2:
+      case Iop_PwMin32Ux2:
+      case Iop_PwMax32Fx2:
+      case Iop_PwMin32Fx2:
+         return assignNew('V', mce, Ity_I64, binop(Iop_PwMax32Ux2, mkPCast32x2(mce, vatom1),
+                     mkPCast32x2(mce, vatom2)));
+
+      case Iop_PwMax16Sx4:
+      case Iop_PwMax16Ux4:
+      case Iop_PwMin16Sx4:
+      case Iop_PwMin16Ux4:
+         return assignNew('V', mce, Ity_I64, binop(Iop_PwMax16Ux4, mkPCast16x4(mce, vatom1),
+                     mkPCast16x4(mce, vatom2)));
+
+      case Iop_PwMax8Sx8:
+      case Iop_PwMax8Ux8:
+      case Iop_PwMin8Sx8:
+      case Iop_PwMin8Ux8:
+         return assignNew('V', mce, Ity_I64, binop(Iop_PwMax8Ux8, mkPCast8x8(mce, vatom1),
+                     mkPCast8x8(mce, vatom2)));
+
+      case Iop_PwAdd32x2:
+      case Iop_PwAdd32Fx2:
+         return mkPCast32x2(mce,
+               assignNew('V', mce, Ity_I64, binop(Iop_PwAdd32x2, mkPCast32x2(mce, vatom1),
+                     mkPCast32x2(mce, vatom2))));
+
+      case Iop_PwAdd16x4:
+         return mkPCast16x4(mce,
+               assignNew('V', mce, Ity_I64, binop(op, mkPCast16x4(mce, vatom1),
+                     mkPCast16x4(mce, vatom2))));
+
+      case Iop_PwAdd8x8:
+         return mkPCast8x8(mce,
+               assignNew('V', mce, Ity_I64, binop(op, mkPCast8x8(mce, vatom1),
+                     mkPCast8x8(mce, vatom2))));
+
+      case Iop_Shl8x8:
+      case Iop_Shr8x8:
+      case Iop_Sar8x8:
+      case Iop_Sal8x8:
+         return mkUifU64(mce,
+                   assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2)),
+                   mkPCast8x8(mce,vatom2)
+                );
+
+      case Iop_Shl16x4:
+      case Iop_Shr16x4:
+      case Iop_Sar16x4:
+      case Iop_Sal16x4:
+         return mkUifU64(mce,
+                   assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2)),
+                   mkPCast16x4(mce,vatom2)
+                );
+
+      case Iop_Shl32x2:
+      case Iop_Shr32x2:
+      case Iop_Sar32x2:
+      case Iop_Sal32x2:
+         return mkUifU64(mce,
+                   assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2)),
+                   mkPCast32x2(mce,vatom2)
+                );
+

       /* 64-bit data-steering */
       case Iop_InterleaveLO32x2:
       case Iop_InterleaveLO16x4:
       /* 64-bit data-steering */
       case Iop_InterleaveLO32x2:
       case Iop_InterleaveLO16x4:


@@ -2167,10 +2386,26 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_InterleaveHI32x2:
       case Iop_InterleaveHI16x4:
       case Iop_InterleaveHI8x8:
       case Iop_InterleaveHI32x2:
       case Iop_InterleaveHI16x4:
       case Iop_InterleaveHI8x8:

+      case Iop_CatOddLanes8x8:
+      case Iop_CatEvenLanes8x8:

       case Iop_CatOddLanes16x4:
       case Iop_CatEvenLanes16x4:
       case Iop_CatOddLanes16x4:
       case Iop_CatEvenLanes16x4:

+      case Iop_InterleaveOddLanes8x8:
+      case Iop_InterleaveEvenLanes8x8:
+      case Iop_InterleaveOddLanes16x4:
+      case Iop_InterleaveEvenLanes16x4:

          return assignNew('V', mce, Ity_I64, binop(op, vatom1, vatom2));
 
          return assignNew('V', mce, Ity_I64, binop(op, vatom1, vatom2));
 

+      case Iop_GetElem8x8:
+         complainIfUndefined(mce, atom2);
+         return assignNew('V', mce, Ity_I8, binop(op, vatom1, atom2));
+      case Iop_GetElem16x4:
+         complainIfUndefined(mce, atom2);
+         return assignNew('V', mce, Ity_I16, binop(op, vatom1, atom2));
+      case Iop_GetElem32x2:
+         complainIfUndefined(mce, atom2);
+         return assignNew('V', mce, Ity_I32, binop(op, vatom1, atom2));
+

       /* Perm8x8: rearrange values in left arg using steering values
         from right arg.  So rearrange the vbits in the same way but
         pessimise wrt steering values. */
       /* Perm8x8: rearrange values in left arg using steering values
         from right arg.  So rearrange the vbits in the same way but
         pessimise wrt steering values. */


@@ -2183,16 +2418,18 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
 
       /* V128-bit SIMD */
 
 
       /* V128-bit SIMD */
 

+      case Iop_ShrN8x16:

       case Iop_ShrN16x8:
       case Iop_ShrN32x4:
       case Iop_ShrN64x2:
       case Iop_ShrN16x8:
       case Iop_ShrN32x4:
       case Iop_ShrN64x2:

+      case Iop_SarN8x16:

       case Iop_SarN16x8:
       case Iop_SarN32x4:
       case Iop_SarN16x8:
       case Iop_SarN32x4:

+      case Iop_SarN64x2:
+      case Iop_ShlN8x16:

       case Iop_ShlN16x8:
       case Iop_ShlN32x4:
       case Iop_ShlN64x2:
       case Iop_ShlN16x8:
       case Iop_ShlN32x4:
       case Iop_ShlN64x2:

-      case Iop_ShlN8x16:
-      case Iop_SarN8x16:

          /* Same scheme as with all other shifts.  Note: 22 Oct 05:
             this is wrong now, scalar shifts are done properly lazily.
             Vector shifts should be fixed too. */
          /* Same scheme as with all other shifts.  Note: 22 Oct 05:
             this is wrong now, scalar shifts are done properly lazily.
             Vector shifts should be fixed too. */


@@ -2203,6 +2440,7 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_Shl8x16:
       case Iop_Shr8x16:
       case Iop_Sar8x16:
       case Iop_Shl8x16:
       case Iop_Shr8x16:
       case Iop_Sar8x16:

+      case Iop_Sal8x16:

       case Iop_Rol8x16:
          return mkUifUV128(mce,
                    assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),
       case Iop_Rol8x16:
          return mkUifUV128(mce,
                    assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),


@@ -2212,6 +2450,7 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_Shl16x8:
       case Iop_Shr16x8:
       case Iop_Sar16x8:
       case Iop_Shl16x8:
       case Iop_Shr16x8:
       case Iop_Sar16x8:

+      case Iop_Sal16x8:

       case Iop_Rol16x8:
          return mkUifUV128(mce,
                    assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),
       case Iop_Rol16x8:
          return mkUifUV128(mce,
                    assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),


@@ -2221,12 +2460,36 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_Shl32x4:
       case Iop_Shr32x4:
       case Iop_Sar32x4:
       case Iop_Shl32x4:
       case Iop_Shr32x4:
       case Iop_Sar32x4:

+      case Iop_Sal32x4:

       case Iop_Rol32x4:
          return mkUifUV128(mce,
                    assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),
                    mkPCast32x4(mce,vatom2)
                 );
 
       case Iop_Rol32x4:
          return mkUifUV128(mce,
                    assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),
                    mkPCast32x4(mce,vatom2)
                 );
 

+      case Iop_Shl64x2:
+      case Iop_Shr64x2:
+      case Iop_Sar64x2:
+      case Iop_Sal64x2:
+         return mkUifUV128(mce,
+                   assignNew('V', mce, Ity_V128, binop(op, vatom1, atom2)),
+                   mkPCast64x2(mce,vatom2)
+                );
+
+      case Iop_F32ToFixed32Ux4_RZ:
+      case Iop_F32ToFixed32Sx4_RZ:
+      case Iop_Fixed32UToF32x4_RN:
+      case Iop_Fixed32SToF32x4_RN:
+         complainIfUndefined(mce, atom2);
+         return mkPCast32x4(mce, vatom1);
+
+      case Iop_F32ToFixed32Ux2_RZ:
+      case Iop_F32ToFixed32Sx2_RZ:
+      case Iop_Fixed32UToF32x2_RN:
+      case Iop_Fixed32SToF32x2_RN:
+         complainIfUndefined(mce, atom2);
+         return mkPCast32x2(mce, vatom1);
+

       case Iop_QSub8Ux16:
       case Iop_QSub8Sx16:
       case Iop_Sub8x16:
       case Iop_QSub8Ux16:
       case Iop_QSub8Sx16:
       case Iop_Sub8x16:


@@ -2241,7 +2504,11 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_Avg8Sx16:
       case Iop_QAdd8Ux16:
       case Iop_QAdd8Sx16:
       case Iop_Avg8Sx16:
       case Iop_QAdd8Ux16:
       case Iop_QAdd8Sx16:

+      case Iop_QSal8x16:
+      case Iop_QShl8x16:

       case Iop_Add8x16:
       case Iop_Add8x16:

+      case Iop_Mul8x16:
+      case Iop_PolynomialMul8x16:

          return binary8Ix16(mce, vatom1, vatom2);
 
       case Iop_QSub16Ux8:
          return binary8Ix16(mce, vatom1, vatom2);
 
       case Iop_QSub16Ux8:


@@ -2261,7 +2528,11 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_Avg16Sx8:
       case Iop_QAdd16Ux8:
       case Iop_QAdd16Sx8:
       case Iop_Avg16Sx8:
       case Iop_QAdd16Ux8:
       case Iop_QAdd16Sx8:

+      case Iop_QSal16x8:
+      case Iop_QShl16x8:

       case Iop_Add16x8:
       case Iop_Add16x8:

+      case Iop_QDMulHi16Sx8:
+      case Iop_QRDMulHi16Sx8:

          return binary16Ix8(mce, vatom1, vatom2);
 
       case Iop_Sub32x4:
          return binary16Ix8(mce, vatom1, vatom2);
 
       case Iop_Sub32x4:


@@ -2272,6 +2543,8 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_QAdd32Ux4:
       case Iop_QSub32Sx4:
       case Iop_QSub32Ux4:
       case Iop_QAdd32Ux4:
       case Iop_QSub32Sx4:
       case Iop_QSub32Ux4:

+      case Iop_QSal32x4:
+      case Iop_QShl32x4:

       case Iop_Avg32Ux4:
       case Iop_Avg32Sx4:
       case Iop_Add32x4:
       case Iop_Avg32Ux4:
       case Iop_Avg32Sx4:
       case Iop_Add32x4:


@@ -2279,10 +2552,20 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_Max32Sx4:
       case Iop_Min32Ux4:
       case Iop_Min32Sx4:
       case Iop_Max32Sx4:
       case Iop_Min32Ux4:
       case Iop_Min32Sx4:

+      case Iop_Mul32x4:
+      case Iop_QDMulHi32Sx4:
+      case Iop_QRDMulHi32Sx4:

          return binary32Ix4(mce, vatom1, vatom2);
 
       case Iop_Sub64x2:
       case Iop_Add64x2:
          return binary32Ix4(mce, vatom1, vatom2);
 
       case Iop_Sub64x2:
       case Iop_Add64x2:

+      case Iop_CmpGT64Sx2:
+      case Iop_QSal64x2:
+      case Iop_QShl64x2:
+      case Iop_QAdd64Ux2:
+      case Iop_QAdd64Sx2:
+      case Iop_QSub64Ux2:
+      case Iop_QSub64Sx2:

          return binary64Ix2(mce, vatom1, vatom2);
 
       case Iop_QNarrow32Sx4:
          return binary64Ix2(mce, vatom1, vatom2);
 
       case Iop_QNarrow32Sx4:


@@ -2327,8 +2610,22 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_CmpGT32Fx4:
       case Iop_CmpGE32Fx4:
       case Iop_Add32Fx4:
       case Iop_CmpGT32Fx4:
       case Iop_CmpGE32Fx4:
       case Iop_Add32Fx4:

+      case Iop_Recps32Fx4:
+      case Iop_Rsqrts32Fx4:

          return binary32Fx4(mce, vatom1, vatom2);      
 
          return binary32Fx4(mce, vatom1, vatom2);      
 

+      case Iop_Sub32Fx2:
+      case Iop_Mul32Fx2:
+      case Iop_Min32Fx2:
+      case Iop_Max32Fx2:
+      case Iop_CmpEQ32Fx2:
+      case Iop_CmpGT32Fx2:
+      case Iop_CmpGE32Fx2:
+      case Iop_Add32Fx2:
+      case Iop_Recps32Fx2:
+      case Iop_Rsqrts32Fx2:
+         return binary32Fx2(mce, vatom1, vatom2);      
+

       case Iop_Sub32F0x4:
       case Iop_Mul32F0x4:
       case Iop_Min32F0x4:
       case Iop_Sub32F0x4:
       case Iop_Mul32F0x4:
       case Iop_Min32F0x4:


@@ -2341,6 +2638,63 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_Add32F0x4:
          return binary32F0x4(mce, vatom1, vatom2);      
 
       case Iop_Add32F0x4:
          return binary32F0x4(mce, vatom1, vatom2);      
 

+      case Iop_QShlN8Sx16:
+      case Iop_QShlN8x16:
+      case Iop_QSalN8x16:
+         complainIfUndefined(mce, atom2);
+         return mkPCast8x16(mce, vatom1);
+
+      case Iop_QShlN16Sx8:
+      case Iop_QShlN16x8:
+      case Iop_QSalN16x8:
+         complainIfUndefined(mce, atom2);
+         return mkPCast16x8(mce, vatom1);
+
+      case Iop_QShlN32Sx4:
+      case Iop_QShlN32x4:
+      case Iop_QSalN32x4:
+         complainIfUndefined(mce, atom2);
+         return mkPCast32x4(mce, vatom1);
+
+      case Iop_QShlN64Sx2:
+      case Iop_QShlN64x2:
+      case Iop_QSalN64x2:
+         complainIfUndefined(mce, atom2);
+         return mkPCast32x4(mce, vatom1);
+
+      case Iop_Mull32Sx2:
+      case Iop_Mull32Ux2:
+      case Iop_QDMulLong32Sx2:
+         return vectorLongenI64(mce, Iop_Longen32Sx2,
+               mkUifU64(mce, vatom1, vatom2));
+
+      case Iop_Mull16Sx4:
+      case Iop_Mull16Ux4:
+      case Iop_QDMulLong16Sx4:
+         return vectorLongenI64(mce, Iop_Longen16Sx4,
+               mkUifU64(mce, vatom1, vatom2));
+
+      case Iop_Mull8Sx8:
+      case Iop_Mull8Ux8:
+      case Iop_PolynomialMull8x8:
+         return vectorLongenI64(mce, Iop_Longen8Sx8,
+               mkUifU64(mce, vatom1, vatom2));
+
+      case Iop_PwAdd32x4:
+         return mkPCast32x4(mce,
+               assignNew('V', mce, Ity_V128, binop(op, mkPCast32x4(mce, vatom1),
+                     mkPCast32x4(mce, vatom2))));
+
+      case Iop_PwAdd16x8:
+         return mkPCast16x8(mce,
+               assignNew('V', mce, Ity_V128, binop(op, mkPCast16x8(mce, vatom1),
+                     mkPCast16x8(mce, vatom2))));
+
+      case Iop_PwAdd8x16:
+         return mkPCast8x16(mce,
+               assignNew('V', mce, Ity_V128, binop(op, mkPCast8x16(mce, vatom1),
+                     mkPCast8x16(mce, vatom2))));
+

       /* V128-bit data-steering */
       case Iop_SetV128lo32:
       case Iop_SetV128lo64:
       /* V128-bit data-steering */
       case Iop_SetV128lo32:
       case Iop_SetV128lo64:


@@ -2353,8 +2707,33 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
       case Iop_InterleaveHI32x4:
       case Iop_InterleaveHI16x8:
       case Iop_InterleaveHI8x16:
       case Iop_InterleaveHI32x4:
       case Iop_InterleaveHI16x8:
       case Iop_InterleaveHI8x16:

+      case Iop_CatOddLanes8x16:
+      case Iop_CatOddLanes16x8:
+      case Iop_CatOddLanes32x4:
+      case Iop_CatEvenLanes8x16:
+      case Iop_CatEvenLanes16x8:
+      case Iop_CatEvenLanes32x4:
+      case Iop_InterleaveOddLanes8x16:
+      case Iop_InterleaveOddLanes16x8:
+      case Iop_InterleaveOddLanes32x4:
+      case Iop_InterleaveEvenLanes8x16:
+      case Iop_InterleaveEvenLanes16x8:
+      case Iop_InterleaveEvenLanes32x4:

          return assignNew('V', mce, Ity_V128, binop(op, vatom1, vatom2));
          return assignNew('V', mce, Ity_V128, binop(op, vatom1, vatom2));

- 
+
+      case Iop_GetElem8x16:
+         complainIfUndefined(mce, atom2);
+         return assignNew('V', mce, Ity_I8, binop(op, vatom1, atom2));
+      case Iop_GetElem16x8:
+         complainIfUndefined(mce, atom2);
+         return assignNew('V', mce, Ity_I16, binop(op, vatom1, atom2));
+      case Iop_GetElem32x4:
+         complainIfUndefined(mce, atom2);
+         return assignNew('V', mce, Ity_I32, binop(op, vatom1, atom2));
+      case Iop_GetElem64x2:
+         complainIfUndefined(mce, atom2);
+         return assignNew('V', mce, Ity_I64, binop(op, vatom1, atom2));
+

      /* Perm8x16: rearrange values in left arg using steering values
         from right arg.  So rearrange the vbits in the same way but
         pessimise wrt steering values. */
      /* Perm8x16: rearrange values in left arg using steering values
         from right arg.  So rearrange the vbits in the same way but
         pessimise wrt steering values. */


@@ -2426,6 +2805,7 @@ IRAtom* expr2vbits_Binop ( MCEnv* mce,
          /* I32(rm) x I64/F64 -> I64/F64 */
          return mkLazy2(mce, Ity_I64, vatom1, vatom2);
 
          /* I32(rm) x I64/F64 -> I64/F64 */
          return mkLazy2(mce, Ity_I64, vatom1, vatom2);
 

+      case Iop_RoundF32toInt:

       case Iop_SqrtF32:
          /* I32(rm) x I32/F32 -> I32/F32 */
          return mkLazy2(mce, Ity_I32, vatom1, vatom2);
       case Iop_SqrtF32:
          /* I32(rm) x I32/F32 -> I32/F32 */
          return mkLazy2(mce, Ity_I32, vatom1, vatom2);


@@ -2674,8 +3054,21 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_RoundF32x4_RP:
       case Iop_RoundF32x4_RN:
       case Iop_RoundF32x4_RZ:
       case Iop_RoundF32x4_RP:
       case Iop_RoundF32x4_RN:
       case Iop_RoundF32x4_RZ:

+      case Iop_Recip32x4:
+      case Iop_Abs32Fx4:
+      case Iop_Neg32Fx4:
+      case Iop_Rsqrte32Fx4:

          return unary32Fx4(mce, vatom);
 
          return unary32Fx4(mce, vatom);
 

+      case Iop_I32UtoFx2:
+      case Iop_I32StoFx2:
+      case Iop_Recip32Fx2:
+      case Iop_Recip32x2:
+      case Iop_Abs32Fx2:
+      case Iop_Neg32Fx2:
+      case Iop_Rsqrte32Fx2:
+         return unary32Fx2(mce, vatom);
+

       case Iop_Sqrt32F0x4:
       case Iop_RSqrt32F0x4:
       case Iop_Recip32F0x4:
       case Iop_Sqrt32F0x4:
       case Iop_RSqrt32F0x4:
       case Iop_Recip32F0x4:


@@ -2686,6 +3079,12 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_Dup8x16:
       case Iop_Dup16x8:
       case Iop_Dup32x4:
       case Iop_Dup8x16:
       case Iop_Dup16x8:
       case Iop_Dup32x4:

+      case Iop_Reverse16_8x16:
+      case Iop_Reverse32_8x16:
+      case Iop_Reverse32_16x8:
+      case Iop_Reverse64_8x16:
+      case Iop_Reverse64_16x8:
+      case Iop_Reverse64_32x4:

          return assignNew('V', mce, Ity_V128, unop(op, vatom));
 
       case Iop_F32toF64: 
          return assignNew('V', mce, Ity_V128, unop(op, vatom));
 
       case Iop_F32toF64: 


@@ -2720,6 +3119,15 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_V128HIto64:
       case Iop_128HIto64:
       case Iop_128to64:
       case Iop_V128HIto64:
       case Iop_128HIto64:
       case Iop_128to64:

+      case Iop_Dup8x8:
+      case Iop_Dup16x4:
+      case Iop_Dup32x2:
+      case Iop_Reverse16_8x8:
+      case Iop_Reverse32_8x8:
+      case Iop_Reverse32_16x4:
+      case Iop_Reverse64_8x8:
+      case Iop_Reverse64_16x4:
+      case Iop_Reverse64_32x2:

          return assignNew('V', mce, Ity_I64, unop(op, vatom));
 
       case Iop_64to32:
          return assignNew('V', mce, Ity_I64, unop(op, vatom));
 
       case Iop_64to32:


@@ -2765,6 +3173,106 @@ IRExpr* expr2vbits_Unop ( MCEnv* mce, IROp op, IRAtom* atom )
       case Iop_Not1:
          return vatom;
 
       case Iop_Not1:
          return vatom;
 

+      case Iop_CmpNEZ8x8:
+      case Iop_Cnt8x8:
+      case Iop_Clz8Sx8:
+      case Iop_Cls8Sx8:
+      case Iop_Abs8x8:
+         return mkPCast8x8(mce, vatom);
+
+      case Iop_CmpNEZ8x16:
+      case Iop_Cnt8x16:
+      case Iop_Clz8Sx16:
+      case Iop_Cls8Sx16:
+      case Iop_Abs8x16:
+         return mkPCast8x16(mce, vatom);
+
+      case Iop_CmpNEZ16x4:
+      case Iop_Clz16Sx4:
+      case Iop_Cls16Sx4:
+      case Iop_Abs16x4:
+         return mkPCast16x4(mce, vatom);
+
+      case Iop_CmpNEZ16x8:
+      case Iop_Clz16Sx8:
+      case Iop_Cls16Sx8:
+      case Iop_Abs16x8:
+         return mkPCast16x8(mce, vatom);
+
+      case Iop_CmpNEZ32x2:
+      case Iop_Clz32Sx2:
+      case Iop_Cls32Sx2:
+      case Iop_FtoI32Ux2_RZ:
+      case Iop_FtoI32Sx2_RZ:
+      case Iop_Abs32x2:
+         return mkPCast32x2(mce, vatom);
+
+      case Iop_CmpNEZ32x4:
+      case Iop_Clz32Sx4:
+      case Iop_Cls32Sx4:
+      case Iop_FtoI32Ux4_RZ:
+      case Iop_FtoI32Sx4_RZ:
+      case Iop_Abs32x4:
+         return mkPCast32x4(mce, vatom);
+
+      case Iop_CmpwNEZ64:
+         return mkPCastTo(mce, Ity_I64, vatom);
+
+      case Iop_CmpNEZ64x2:
+         return mkPCast64x2(mce, vatom);
+
+      case Iop_Shorten16x8:
+      case Iop_Shorten32x4:
+      case Iop_Shorten64x2:
+      case Iop_QShortenS16Sx8:
+      case Iop_QShortenU16Sx8:
+      case Iop_QShortenU16Ux8:
+      case Iop_QShortenS32Sx4:
+      case Iop_QShortenU32Sx4:
+      case Iop_QShortenU32Ux4:
+      case Iop_QShortenS64Sx2:
+      case Iop_QShortenU64Sx2:
+      case Iop_QShortenU64Ux2:
+         return vectorShortenV128(mce, op, vatom);
+
+      case Iop_Longen8Sx8:
+      case Iop_Longen8Ux8:
+      case Iop_Longen16Sx4:
+      case Iop_Longen16Ux4:
+      case Iop_Longen32Sx2:
+      case Iop_Longen32Ux2:
+         return vectorLongenI64(mce, op, vatom);
+
+      case Iop_PwAddL32Ux2:
+      case Iop_PwAddL32Sx2:
+         return mkPCastTo(mce, Ity_I64,
+               assignNew('V', mce, Ity_I64, unop(op, mkPCast32x2(mce, vatom))));
+
+      case Iop_PwAddL16Ux4:
+      case Iop_PwAddL16Sx4:
+         return mkPCast32x2(mce,
+               assignNew('V', mce, Ity_I64, unop(op, mkPCast16x4(mce, vatom))));
+
+      case Iop_PwAddL8Ux8:
+      case Iop_PwAddL8Sx8:
+         return mkPCast16x4(mce,
+               assignNew('V', mce, Ity_I64, unop(op, mkPCast8x8(mce, vatom))));
+
+      case Iop_PwAddL32Ux4:
+      case Iop_PwAddL32Sx4:
+         return mkPCast64x2(mce,
+               assignNew('V', mce, Ity_V128, unop(op, mkPCast32x4(mce, vatom))));
+
+      case Iop_PwAddL16Ux8:
+      case Iop_PwAddL16Sx8:
+         return mkPCast32x4(mce,
+               assignNew('V', mce, Ity_V128, unop(op, mkPCast16x8(mce, vatom))));
+
+      case Iop_PwAddL8Ux16:
+      case Iop_PwAddL8Sx16:
+         return mkPCast16x8(mce,
+               assignNew('V', mce, Ity_V128, unop(op, mkPCast8x16(mce, vatom))));
+

       default:
          ppIROp(op);
          VG_(tool_panic)("memcheck:expr2vbits_Unop");
       default:
          ppIROp(op);
          VG_(tool_panic)("memcheck:expr2vbits_Unop");

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/perf/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/perf/Makefile.in
index 2f482910131162768c80e8c2a87a4160898f83e0..169c3b1736c91752a2ab182f93e5eceaef856dba 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/perf/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/perf/Makefile.in
@@ -108,6 +108,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -142,14 +143,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -232,7 +237,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -291,7 +298,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -306,8 +313,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/Makefile.am
index 12bb97e44eb119de948e7226a843d47b725bf710..c8914762bb63e8e27a0d162d971703d24d58c385 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/Makefile.am
@@ -23,12 +23,16 @@ endif
 if VGCONF_PLATFORMS_INCLUDE_X86_LINUX
 SUBDIRS += x86-linux
 endif
 if VGCONF_PLATFORMS_INCLUDE_X86_LINUX
 SUBDIRS += x86-linux
 endif

+if VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX
+SUBDIRS += amd64-linux
+endif

 
 

-DIST_SUBDIRS = x86 amd64 linux darwin x86-linux .
+DIST_SUBDIRS = x86 amd64 linux darwin x86-linux amd64-linux .

 
 dist_noinst_SCRIPTS = \
        filter_addressable \
        filter_allocs \
 
 dist_noinst_SCRIPTS = \
        filter_addressable \
        filter_allocs \

+       filter_leak_cases_possible \

        filter_stderr filter_xml \
        filter_varinfo3
 
        filter_stderr filter_xml \
        filter_varinfo3
 


@@ -71,6 +75,7 @@ EXTRA_DIST = \
        inline.stderr.exp inline.stdout.exp inline.vgtest \
        leak-0.vgtest leak-0.stderr.exp \
        leak-cases-full.vgtest leak-cases-full.stderr.exp \
        inline.stderr.exp inline.stdout.exp inline.vgtest \
        leak-0.vgtest leak-0.stderr.exp \
        leak-cases-full.vgtest leak-cases-full.stderr.exp \

+       leak-cases-possible.vgtest leak-cases-possible.stderr.exp \

        leak-cases-summary.vgtest leak-cases-summary.stderr.exp \
        leak-cycle.vgtest leak-cycle.stderr.exp \
        leak-pool-0.vgtest leak-pool-0.stderr.exp \
        leak-cases-summary.vgtest leak-cases-summary.stderr.exp \
        leak-cycle.vgtest leak-cycle.stderr.exp \
        leak-pool-0.vgtest leak-pool-0.stderr.exp \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/Makefile.in
index d6d893ab0619a36e0f4bdd80402ca17775b06a8f..550f12df87c925018007c8555bc7401dfdf55148 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/Makefile.in
@@ -59,6 +59,7 @@ DIST_COMMON = $(dist_noinst_SCRIPTS) $(noinst_HEADERS) \
 
 # Platform-specific tests
 @VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_5 = x86-linux
 
 # Platform-specific tests
 @VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_5 = x86-linux

+@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_6 = amd64-linux

 check_PROGRAMS = addressable$(EXEEXT) atomic_incs$(EXEEXT) \
        badaddrvalue$(EXEEXT) badfree$(EXEEXT) badjump$(EXEEXT) \
        badjump2$(EXEEXT) badloop$(EXEEXT) badpoll$(EXEEXT) \
 check_PROGRAMS = addressable$(EXEEXT) atomic_incs$(EXEEXT) \
        badaddrvalue$(EXEEXT) badfree$(EXEEXT) badjump$(EXEEXT) \
        badjump2$(EXEEXT) badloop$(EXEEXT) badpoll$(EXEEXT) \


@@ -100,8 +101,8 @@ check_PROGRAMS = addressable$(EXEEXT) atomic_incs$(EXEEXT) \
        wrap1$(EXEEXT) wrap2$(EXEEXT) wrap3$(EXEEXT) wrap4$(EXEEXT) \
        wrap5$(EXEEXT) wrap6$(EXEEXT) wrap7$(EXEEXT) \
        wrap7so.so$(EXEEXT) wrap8$(EXEEXT) writev$(EXEEXT)
        wrap1$(EXEEXT) wrap2$(EXEEXT) wrap3$(EXEEXT) wrap4$(EXEEXT) \
        wrap5$(EXEEXT) wrap6$(EXEEXT) wrap7$(EXEEXT) \
        wrap7so.so$(EXEEXT) wrap8$(EXEEXT) writev$(EXEEXT)

-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_6 = -mfloat-abi=softfp

 @VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_7 = -mfloat-abi=softfp
 @VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_7 = -mfloat-abi=softfp

+@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_8 = -mfloat-abi=softfp

 subdir = memcheck/tests
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = memcheck/tests
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -662,6 +663,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -696,14 +698,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -786,7 +792,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -845,7 +853,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -860,8 +868,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -915,19 +923,20 @@ AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
 # Nb: Tools need to augment these flags with an arch-selection option, such
 # as $(AM_FLAG_M3264_PRI).
 AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI) \
 # Nb: Tools need to augment these flags with an arch-selection option, such
 # as $(AM_FLAG_M3264_PRI).
 AM_CFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI) \

-       $(am__append_6)
-AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI) \

        $(am__append_7)
        $(am__append_7)

+AM_CXXFLAGS = -Winline -Wall -Wshadow -g $(AM_FLAG_M3264_PRI) \
+       $(am__append_8)

 # Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
 # automake;  see comments in Makefile.all.am for more detail.
 AM_CCASFLAGS = $(AM_CPPFLAGS)
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
 SUBDIRS = . $(am__append_1) $(am__append_2) $(am__append_3) \
 # Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
 # automake;  see comments in Makefile.all.am for more detail.
 AM_CCASFLAGS = $(AM_CPPFLAGS)
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
 SUBDIRS = . $(am__append_1) $(am__append_2) $(am__append_3) \

-       $(am__append_4) $(am__append_5)
-DIST_SUBDIRS = x86 amd64 linux darwin x86-linux .
+       $(am__append_4) $(am__append_5) $(am__append_6)
+DIST_SUBDIRS = x86 amd64 linux darwin x86-linux amd64-linux .

 dist_noinst_SCRIPTS = \
        filter_addressable \
        filter_allocs \
 dist_noinst_SCRIPTS = \
        filter_addressable \
        filter_allocs \

+       filter_leak_cases_possible \

        filter_stderr filter_xml \
        filter_varinfo3
 
        filter_stderr filter_xml \
        filter_varinfo3
 


@@ -969,6 +978,7 @@ EXTRA_DIST = \
        inline.stderr.exp inline.stdout.exp inline.vgtest \
        leak-0.vgtest leak-0.stderr.exp \
        leak-cases-full.vgtest leak-cases-full.stderr.exp \
        inline.stderr.exp inline.stdout.exp inline.vgtest \
        leak-0.vgtest leak-0.stderr.exp \
        leak-cases-full.vgtest leak-cases-full.stderr.exp \

+       leak-cases-possible.vgtest leak-cases-possible.stderr.exp \

        leak-cases-summary.vgtest leak-cases-summary.stderr.exp \
        leak-cycle.vgtest leak-cycle.stderr.exp \
        leak-pool-0.vgtest leak-pool-0.stderr.exp \
        leak-cases-summary.vgtest leak-cases-summary.stderr.exp \
        leak-cycle.vgtest leak-cycle.stderr.exp \
        leak-pool-0.vgtest leak-pool-0.stderr.exp \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/Makefile.am
new file mode 100644 (file)
index 0000000..9b31b80
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/Makefile.am
@@ -0,0 +1,21 @@
+
+include $(top_srcdir)/Makefile.tool-tests.am
+
+dist_noinst_SCRIPTS = \
+       filter_stderr filter_defcfaexpr
+
+EXTRA_DIST = \
+       defcfaexpr.vgtest defcfaexpr.stderr.exp \
+       int3-amd64.vgtest int3-amd64.stderr.exp int3-amd64.stdout.exp
+
+check_PROGRAMS = \
+       defcfaexpr \
+       int3-amd64
+
+
+AM_CFLAGS    += @FLAG_M64@
+AM_CXXFLAGS  += @FLAG_M64@
+AM_CCASFLAGS += @FLAG_M64@
+
+defcfaexpr_SOURCES     = defcfaexpr.S
+

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/Makefile.in
new file mode 100644 (file)
index 0000000..cbbe02b
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/Makefile.in
@@ -0,0 +1,741 @@
+# Makefile.in generated by automake 1.11.1 from Makefile.am.
+# @configure_input@
+
+# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+# 2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+@SET_MAKE@
+
+# This file is used for tool tests, and also in perf/Makefile.am.
+
+# This file should be included (directly or indirectly) by every
+# Makefile.am that builds programs.  And also the top-level Makefile.am.
+
+#----------------------------------------------------------------------------
+# Global stuff
+#----------------------------------------------------------------------------
+
+VPATH = @srcdir@
+pkgdatadir = $(datadir)/@PACKAGE@
+pkgincludedir = $(includedir)/@PACKAGE@
+pkglibdir = $(libdir)/@PACKAGE@
+pkglibexecdir = $(libexecdir)/@PACKAGE@
+am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
+install_sh_DATA = $(install_sh) -c -m 644
+install_sh_PROGRAM = $(install_sh) -c
+install_sh_SCRIPT = $(install_sh) -c
+INSTALL_HEADER = $(INSTALL_DATA)
+transform = $(program_transform_name)
+NORMAL_INSTALL = :
+PRE_INSTALL = :
+POST_INSTALL = :
+NORMAL_UNINSTALL = :
+PRE_UNINSTALL = :
+POST_UNINSTALL = :
+build_triplet = @build@
+host_triplet = @host@
+DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
+       $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
+       $(top_srcdir)/Makefile.tool-tests.am
+check_PROGRAMS = defcfaexpr$(EXEEXT) int3-amd64$(EXEEXT)
+subdir = memcheck/tests/amd64-linux
+ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+am__aclocal_m4_deps = $(top_srcdir)/configure.in
+am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
+       $(ACLOCAL_M4)
+mkinstalldirs = $(install_sh) -d
+CONFIG_HEADER = $(top_builddir)/config.h
+CONFIG_CLEAN_FILES =
+CONFIG_CLEAN_VPATH_FILES =
+am_defcfaexpr_OBJECTS = defcfaexpr.$(OBJEXT)
+defcfaexpr_OBJECTS = $(am_defcfaexpr_OBJECTS)
+defcfaexpr_LDADD = $(LDADD)
+int3_amd64_SOURCES = int3-amd64.c
+int3_amd64_OBJECTS = int3-amd64.$(OBJEXT)
+int3_amd64_LDADD = $(LDADD)
+SCRIPTS = $(dist_noinst_SCRIPTS)
+DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
+depcomp = $(SHELL) $(top_srcdir)/depcomp
+am__depfiles_maybe = depfiles
+am__mv = mv -f
+CPPASCOMPILE = $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
+       $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CCASFLAGS) $(CCASFLAGS)
+COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
+       $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
+CCLD = $(CC)
+LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
+SOURCES = $(defcfaexpr_SOURCES) int3-amd64.c
+DIST_SOURCES = $(defcfaexpr_SOURCES) int3-amd64.c
+ETAGS = etags
+CTAGS = ctags
+DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
+ACLOCAL = @ACLOCAL@
+AMTAR = @AMTAR@
+AR = @AR@
+AUTOCONF = @AUTOCONF@
+AUTOHEADER = @AUTOHEADER@
+AUTOMAKE = @AUTOMAKE@
+AWK = @AWK@
+BOOST_CFLAGS = @BOOST_CFLAGS@
+BOOST_LIBS = @BOOST_LIBS@
+CC = @CC@
+CCAS = @CCAS@
+CCASDEPMODE = @CCASDEPMODE@
+CCASFLAGS = @CCASFLAGS@
+CCDEPMODE = @CCDEPMODE@
+CFLAGS = @CFLAGS@
+CPP = @CPP@
+CPPFLAGS = @CPPFLAGS@
+CXX = @CXX@
+CXXDEPMODE = @CXXDEPMODE@
+CXXFLAGS = @CXXFLAGS@
+CYGPATH_W = @CYGPATH_W@
+DEFAULT_SUPP = @DEFAULT_SUPP@
+DEFS = @DEFS@
+DEPDIR = @DEPDIR@
+DIFF = @DIFF@
+ECHO_C = @ECHO_C@
+ECHO_N = @ECHO_N@
+ECHO_T = @ECHO_T@
+EGREP = @EGREP@
+EXEEXT = @EXEEXT@
+FLAG_FNO_STACK_PROTECTOR = @FLAG_FNO_STACK_PROTECTOR@
+FLAG_M32 = @FLAG_M32@
+FLAG_M64 = @FLAG_M64@
+FLAG_MAIX32 = @FLAG_MAIX32@
+FLAG_MAIX64 = @FLAG_MAIX64@
+FLAG_MMMX = @FLAG_MMMX@
+FLAG_MSSE = @FLAG_MSSE@
+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@
+FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
+FLAG_W_EXTRA = @FLAG_W_EXTRA@
+FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
+FLAG_W_NO_FORMAT_ZERO_LENGTH = @FLAG_W_NO_FORMAT_ZERO_LENGTH@
+FLAG_W_NO_UNINITIALIZED = @FLAG_W_NO_UNINITIALIZED@
+GDB = @GDB@
+GENERATED_SUPP = @GENERATED_SUPP@
+GLIBC_VERSION = @GLIBC_VERSION@
+GREP = @GREP@
+INSTALL = @INSTALL@
+INSTALL_DATA = @INSTALL_DATA@
+INSTALL_PROGRAM = @INSTALL_PROGRAM@
+INSTALL_SCRIPT = @INSTALL_SCRIPT@
+INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
+LDFLAGS = @LDFLAGS@
+LIBOBJS = @LIBOBJS@
+LIBS = @LIBS@
+LN_S = @LN_S@
+LTLIBOBJS = @LTLIBOBJS@
+MAINT = @MAINT@
+MAKEINFO = @MAKEINFO@
+MKDIR_P = @MKDIR_P@
+MPI_CC = @MPI_CC@
+OBJEXT = @OBJEXT@
+PACKAGE = @PACKAGE@
+PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
+PACKAGE_NAME = @PACKAGE_NAME@
+PACKAGE_STRING = @PACKAGE_STRING@
+PACKAGE_TARNAME = @PACKAGE_TARNAME@
+PACKAGE_URL = @PACKAGE_URL@
+PACKAGE_VERSION = @PACKAGE_VERSION@
+PATH_SEPARATOR = @PATH_SEPARATOR@
+PERL = @PERL@
+PKG_CONFIG = @PKG_CONFIG@
+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@
+PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
+QTCORE_CFLAGS = @QTCORE_CFLAGS@
+QTCORE_LIBS = @QTCORE_LIBS@
+RANLIB = @RANLIB@
+SED = @SED@
+SET_MAKE = @SET_MAKE@
+SHELL = @SHELL@
+STRIP = @STRIP@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@
+VERSION = @VERSION@
+VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
+VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
+VGCONF_OS = @VGCONF_OS@
+VGCONF_PLATFORM_PRI_CAPS = @VGCONF_PLATFORM_PRI_CAPS@
+VGCONF_PLATFORM_SEC_CAPS = @VGCONF_PLATFORM_SEC_CAPS@
+abs_builddir = @abs_builddir@
+abs_srcdir = @abs_srcdir@
+abs_top_builddir = @abs_top_builddir@
+abs_top_srcdir = @abs_top_srcdir@
+ac_ct_CC = @ac_ct_CC@
+ac_ct_CXX = @ac_ct_CXX@
+am__include = @am__include@
+am__leading_dot = @am__leading_dot@
+am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
+bindir = @bindir@
+build = @build@
+build_alias = @build_alias@
+build_cpu = @build_cpu@
+build_os = @build_os@
+build_vendor = @build_vendor@
+builddir = @builddir@
+datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
+dvidir = @dvidir@
+exec_prefix = @exec_prefix@
+host = @host@
+host_alias = @host_alias@
+host_cpu = @host_cpu@
+host_os = @host_os@
+host_vendor = @host_vendor@
+htmldir = @htmldir@
+includedir = @includedir@
+infodir = @infodir@
+install_sh = @install_sh@
+libdir = @libdir@
+libexecdir = @libexecdir@
+localedir = @localedir@
+localstatedir = @localstatedir@
+mandir = @mandir@
+mkdir_p = @mkdir_p@
+oldincludedir = @oldincludedir@
+pdfdir = @pdfdir@
+prefix = @prefix@
+program_transform_name = @program_transform_name@
+psdir = @psdir@
+sbindir = @sbindir@
+sharedstatedir = @sharedstatedir@
+srcdir = @srcdir@
+sysconfdir = @sysconfdir@
+target_alias = @target_alias@
+top_build_prefix = @top_build_prefix@
+top_builddir = @top_builddir@
+top_srcdir = @top_srcdir@
+inplacedir = $(top_builddir)/.in_place
+
+#----------------------------------------------------------------------------
+# Flags
+#----------------------------------------------------------------------------
+
+# Baseline flags for all compilations.  Aim here is to maximise
+# performance and get whatever useful warnings we can out of gcc.
+AM_CFLAGS_BASE = \
+       -O2 -g \
+       -Wall \
+       -Wmissing-prototypes \
+       -Wshadow \
+       -Wpointer-arith \
+       -Wstrict-prototypes \
+       -Wmissing-declarations \
+       @FLAG_W_NO_FORMAT_ZERO_LENGTH@ \
+       -fno-strict-aliasing
+
+@VGCONF_OS_IS_DARWIN_FALSE@AM_CFLAGS_PIC = -fpic -O -g -fno-omit-frame-pointer -fno-strict-aliasing
+
+# These flags are used for building the preload shared objects.
+# The aim is to give reasonable performance but also to have good
+# stack traces, since users often see stack traces extending 
+# into (and through) the preloads.
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+
+@VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
+@VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
+@VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
+@VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/VEX/pub \
+@VGCONF_OS_IS_L4RE_FALSE@      -I$(top_builddir)/VEX/pub \
+@VGCONF_OS_IS_L4RE_FALSE@      -DVGA_@VGCONF_ARCH_PRI@=1 \
+@VGCONF_OS_IS_L4RE_FALSE@      -DVGO_@VGCONF_OS@=1 \
+@VGCONF_OS_IS_L4RE_FALSE@      -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+
+# Flags for specific targets.
+#
+# Nb: the AM_CPPFLAGS_* values are suitable for building tools and auxprogs.
+# For building the core, coregrind/Makefile.am files add some extra things.
+#
+# Also: in newer versions of automake (1.10 onwards?) asm files ending with
+# '.S' are considered "pre-processed" (as opposed to those ending in '.s')
+# and so the CPPFLAGS are passed to the assembler.  But this is not true for
+# older automakes (e.g. 1.8.5, 1.9.6), sigh.  So we include
+# AM_CPPFLAGS_<PLATFORM> in each AM_CCASFLAGS_<PLATFORM> variable.  This
+# means some of the flags are duplicated on systems with newer versions of
+# automake, but this does not really matter and seems hard to avoid.
+@VGCONF_OS_IS_L4RE_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = $(L4_CPPFLAGS)\
+@VGCONF_OS_IS_L4RE_TRUE@       -I$(top_srcdir) \
+@VGCONF_OS_IS_L4RE_TRUE@       -I$(top_srcdir)/include \
+@VGCONF_OS_IS_L4RE_TRUE@       -I$(top_srcdir)/VEX/pub \
+@VGCONF_OS_IS_L4RE_TRUE@       -I$(top_builddir)/VEX/pub \
+@VGCONF_OS_IS_L4RE_TRUE@       -DVGA_@VGCONF_ARCH_PRI@=1 \
+@VGCONF_OS_IS_L4RE_TRUE@       -DVGO_@VGCONF_OS@=1 \
+@VGCONF_OS_IS_L4RE_TRUE@       -DVGP_@VGCONF_ARCH_PRI@_@VGCONF_OS@=1
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@ = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        -I$(top_srcdir) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        -I$(top_srcdir)/include \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        -I$(top_srcdir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        -I$(top_builddir)/VEX/pub \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        -DVGA_@VGCONF_ARCH_SEC@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        -DVGO_@VGCONF_OS@=1 \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        -DVGP_@VGCONF_ARCH_SEC@_@VGCONF_OS@=1
+
+AM_FLAG_M3264_X86_LINUX = @FLAG_M32@
+AM_CFLAGS_X86_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+                               $(AM_CFLAGS_BASE)
+
+AM_CCASFLAGS_X86_LINUX = $(AM_CPPFLAGS_X86_LINUX) @FLAG_M32@ -g
+AM_FLAG_M3264_AMD64_LINUX = @FLAG_M64@
+AM_CFLAGS_AMD64_LINUX = @FLAG_M64@ -fomit-frame-pointer \
+                               @PREFERRED_STACK_BOUNDARY@ $(AM_CFLAGS_BASE)
+
+AM_CCASFLAGS_AMD64_LINUX = $(AM_CPPFLAGS_AMD64_LINUX) @FLAG_M64@ -g
+AM_FLAG_M3264_PPC32_LINUX = @FLAG_M32@
+AM_CFLAGS_PPC32_LINUX = @FLAG_M32@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_LINUX = $(AM_CPPFLAGS_PPC32_LINUX) @FLAG_M32@ -g
+AM_FLAG_M3264_PPC64_LINUX = @FLAG_M64@
+AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
+AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
+AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+                               $(AM_CFLAGS_BASE) -marm
+
+AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
+AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
+AM_CFLAGS_PPC32_AIX5 = @FLAG_MAIX32@ -mcpu=powerpc $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC32_AIX5 = $(AM_CPPFLAGS_PPC32_AIX5) \
+                           @FLAG_MAIX32@ -mcpu=powerpc -g
+
+AM_FLAG_M3264_PPC64_AIX5 = @FLAG_MAIX64@
+AM_CFLAGS_PPC64_AIX5 = @FLAG_MAIX64@ -mcpu=powerpc64 $(AM_CFLAGS_BASE)
+AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
+                           @FLAG_MAIX64@ -mcpu=powerpc64 -g
+
+AM_FLAG_M3264_X86_DARWIN = -arch i386
+AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC
+
+AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
+AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
+AM_CFLAGS_AMD64_DARWIN = $(WERROR) -arch x86_64 $(AM_CFLAGS_BASE) \
+                           -mmacosx-version-min=10.5 -fno-stack-protector
+
+AM_CCASFLAGS_AMD64_DARWIN = $(AM_CPPFLAGS_AMD64_DARWIN) -arch x86_64 -g
+AM_FLAG_M3264_X86_L4RE = @FLAG_M32@
+AM_CFLAGS_X86_L4RE = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
+                                                $(L4_CFLAGS) $(AM_CFLAGS_BASE)
+
+AM_CCASFLAGS_X86_L4RE = $(L4_CPPFLAGS) @FLAG_M32@ -g
+AM_CXXFLAGS_X86_L4RE = $(L4_CXXFLAGS) @FLAG_M32@
+#AM_CPPFLAGS_X86_L4RE   = $(L4_CPPFLAGS) $(AM_CPPFLAGS_X86_L4RE)
+
+# Flags for the primary target.  These must be used to build the
+# regtests and performance tests.  In fact, these must be used to
+# build anything which is built only once on a dual-arch build.
+#
+AM_FLAG_M3264_PRI = $(AM_FLAG_M3264_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CPPFLAGS_PRI = $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CFLAGS_PRI = $(AM_CFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CCASFLAGS_PRI = $(AM_CCASFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+AM_CXXFLAGS_PRI = $(AM_CXXFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
+@VGCONF_HAVE_PLATFORM_SEC_FALSE@AM_FLAG_M3264_SEC = 
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@AM_FLAG_M3264_SEC = $(AM_FLAG_M3264_@VGCONF_PLATFORM_SEC_CAPS@)
+
+# Baseline link flags for making vgpreload shared objects.
+#
+PRELOAD_LDFLAGS_COMMON_LINUX = -nodefaultlibs -shared -Wl,-z,interpose,-z,initfirst
+PRELOAD_LDFLAGS_COMMON_AIX5 = -nodefaultlibs -shared -Wl,-G -Wl,-bnogc
+PRELOAD_LDFLAGS_COMMON_DARWIN = -dynamic -dynamiclib -all_load
+PRELOAD_LDFLAGS_COMMON_L4RE = -nodefaultlibs -shared -Wl,-z,interpose,-z,initfirst
+PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+PRELOAD_LDFLAGS_PPC32_AIX5 = $(PRELOAD_LDFLAGS_COMMON_AIX5)  @FLAG_MAIX32@
+PRELOAD_LDFLAGS_PPC64_AIX5 = $(PRELOAD_LDFLAGS_COMMON_AIX5)  @FLAG_MAIX64@
+PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+PRELOAD_LDFLAGS_X86_L4RE = $(PRELOAD_LDFLAGS_COMMON_L4RE) @FLAG_M32@
+AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/include \
+               -I$(top_srcdir)/coregrind -I$(top_builddir)/include \
+               -I$(top_srcdir)/VEX/pub \
+               -DVGA_$(VGCONF_ARCH_PRI)=1 \
+               -DVGO_$(VGCONF_OS)=1 \
+               -DVGP_$(VGCONF_ARCH_PRI)_$(VGCONF_OS)=1
+
+# Nb: Tools need to augment these flags with an arch-selection option, such
+# as $(AM_FLAG_M3264_PRI).
+AM_CFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+AM_CXXFLAGS = -Winline -Wall -Wshadow -g @FLAG_M64@
+# Include AM_CPPFLAGS in AM_CCASFLAGS to allow for older versions of
+# automake;  see comments in Makefile.all.am for more detail.
+AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M64@
+@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+dist_noinst_SCRIPTS = \
+       filter_stderr filter_defcfaexpr
+
+EXTRA_DIST = \
+       defcfaexpr.vgtest defcfaexpr.stderr.exp \
+       int3-amd64.vgtest int3-amd64.stderr.exp int3-amd64.stdout.exp
+
+defcfaexpr_SOURCES = defcfaexpr.S
+all: all-am
+
+.SUFFIXES:
+.SUFFIXES: .S .c .o .obj
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
+       @for dep in $?; do \
+         case '$(am__configure_deps)' in \
+           *$$dep*) \
+             ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \
+               && { if test -f $@; then exit 0; else break; fi; }; \
+             exit 1;; \
+         esac; \
+       done; \
+       echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign memcheck/tests/amd64-linux/Makefile'; \
+       $(am__cd) $(top_srcdir) && \
+         $(AUTOMAKE) --foreign memcheck/tests/amd64-linux/Makefile
+.PRECIOUS: Makefile
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+       @case '$?' in \
+         *config.status*) \
+           cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
+         *) \
+           echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
+           cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
+       esac;
+
+$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
+       cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+
+$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps)
+       cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps)
+       cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
+$(am__aclocal_m4_deps):
+
+clean-checkPROGRAMS:
+       -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
+defcfaexpr$(EXEEXT): $(defcfaexpr_OBJECTS) $(defcfaexpr_DEPENDENCIES) 
+       @rm -f defcfaexpr$(EXEEXT)
+       $(LINK) $(defcfaexpr_OBJECTS) $(defcfaexpr_LDADD) $(LIBS)
+int3-amd64$(EXEEXT): $(int3_amd64_OBJECTS) $(int3_amd64_DEPENDENCIES) 
+       @rm -f int3-amd64$(EXEEXT)
+       $(LINK) $(int3_amd64_OBJECTS) $(int3_amd64_LDADD) $(LIBS)
+
+mostlyclean-compile:
+       -rm -f *.$(OBJEXT)
+
+distclean-compile:
+       -rm -f *.tab.c
+
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/defcfaexpr.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/int3-amd64.Po@am__quote@
+
+.S.o:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@        $(CPPASCOMPILE) -c -o $@ $<
+
+.S.obj:
+@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCCAS_FALSE@        $(CPPASCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+
+.c.o:
+@am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
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+@am__fastdepCC_FALSE@  $(COMPILE) -c $<
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+.c.obj:
+@am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
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+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+       list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+       unique=`for i in $$list; do \
+           if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+         done | \
+         $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+             END { if (nonempty) { for (i in files) print i; }; }'`; \
+       mkid -fID $$unique
+tags: TAGS
+
+TAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
+               $(TAGS_FILES) $(LISP)
+       set x; \
+       here=`pwd`; \
+       list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
+       unique=`for i in $$list; do \
+           if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+         done | \
+         $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
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+       shift; \
+       if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
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+         if test $$# -gt 0; then \
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+             "$$@" $$unique; \
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+           $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
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+         fi; \
+       fi
+ctags: CTAGS
+CTAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
+               $(TAGS_FILES) $(LISP)
+       list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
+       unique=`for i in $$list; do \
+           if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+         done | \
+         $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
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+       test -z "$(CTAGS_ARGS)$$unique" \
+         || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+            $$unique
+
+GTAGS:
+       here=`$(am__cd) $(top_builddir) && pwd` \
+         && $(am__cd) $(top_srcdir) \
+         && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
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+
+distdir: $(DISTFILES)
+       @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+       topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+       list='$(DISTFILES)'; \
+         dist_files=`for file in $$list; do echo $$file; done | \
+         sed -e "s|^$$srcdirstrip/||;t" \
+             -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+       case $$dist_files in \
+         */*) $(MKDIR_P) `echo "$$dist_files" | \
+                          sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
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+       esac; \
+       for file in $$dist_files; do \
+         if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+         if test -d $$d/$$file; then \
+           dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+           if test -d "$(distdir)/$$file"; then \
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+           fi; \
+           if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
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+             find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+           fi; \
+           cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+         else \
+           test -f "$(distdir)/$$file" \
+           || cp -p $$d/$$file "$(distdir)/$$file" \
+           || exit 1; \
+         fi; \
+       done
+check-am: all-am
+       $(MAKE) $(AM_MAKEFLAGS) $(check_PROGRAMS)
+       $(MAKE) $(AM_MAKEFLAGS) check-local
+check: check-am
+all-am: Makefile $(SCRIPTS)
+installdirs:
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+install-exec: install-exec-am
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+uninstall: uninstall-am
+
+install-am: all-am
+       @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
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+installcheck: installcheck-am
+install-strip:
+       $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+         install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+         `test -z '$(STRIP)' || \
+           echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+
+distclean-generic:
+       -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+       -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+
+maintainer-clean-generic:
+       @echo "This command is intended for maintainers to use"
+       @echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-checkPROGRAMS clean-generic clean-local mostlyclean-am
+
+distclean: distclean-am
+       -rm -rf ./$(DEPDIR)
+       -rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+       distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am:
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
+
+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+       -rm -rf ./$(DEPDIR)
+       -rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am:
+
+.MAKE: check-am install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am check-local clean \
+       clean-checkPROGRAMS clean-generic clean-local ctags distclean \
+       distclean-compile distclean-generic distclean-tags distdir dvi \
+       dvi-am html html-am info info-am install install-am \
+       install-data install-data-am install-dvi install-dvi-am \
+       install-exec install-exec-am install-html install-html-am \
+       install-info install-info-am install-man install-pdf \
+       install-pdf-am install-ps install-ps-am install-strip \
+       installcheck installcheck-am installdirs maintainer-clean \
+       maintainer-clean-generic mostlyclean mostlyclean-compile \
+       mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+       uninstall-am
+
+
+# This used to be required when Vex had a handwritten Makefile.  It
+# shouldn't be needed any more, though.
+
+#----------------------------------------------------------------------------
+# noinst_PROGRAMS and noinst_DSYMS targets
+#----------------------------------------------------------------------------
+
+# On Darwin, for a program 'p', the DWARF debug info is stored in the
+# directory 'p.dSYM'.  This must be generated after the executable is
+# created, with 'dsymutil p'.  We could redefine LINK with a script that
+# executes 'dsymutil' after linking, but that's a pain.  Instead we use this
+# hook so that every time "make check" is run, we subsequently invoke
+# 'dsymutil' on all the executables that lack a .dSYM directory, or that are
+# newer than their corresponding .dSYM directory.
+build-noinst_DSYMS: $(noinst_DSYMS)
+       for f in $(noinst_DSYMS); do \
+         if [ ! -e $$f.dSYM  -o  $$f -nt $$f.dSYM ] ; then \
+             echo "dsymutil $$f"; \
+             dsymutil $$f; \
+         fi; \
+       done
+
+# This is used by coregrind/Makefile.am and Makefile.tool.am for doing
+# "in-place" installs.  It copies $(noinst_PROGRAMS) into $inplacedir.
+# It needs to be depended on by an 'all-local' rule.
+inplace-noinst_PROGRAMS: $(noinst_PROGRAMS)
+       mkdir -p $(inplacedir); \
+       for f in $(noinst_PROGRAMS) ; do \
+         rm -f $(inplacedir)/$$f; \
+         ln -f -s ../$(subdir)/$$f $(inplacedir); \
+       done
+
+# Similar to inplace-noinst_PROGRAMS
+inplace-noinst_DSYMS: build-noinst_DSYMS
+       mkdir -p $(inplacedir); \
+       for f in $(noinst_DSYMS); do \
+         rm -f $(inplacedir)/$$f.dSYM; \
+         ln -f -s ../$(subdir)/$$f.dSYM $(inplacedir); \
+       done
+
+# This is used by coregrind/Makefile.am and by <tool>/Makefile.am for doing
+# "make install".  It copies $(noinst_PROGRAMS) into $prefix/lib/valgrind/.
+# It needs to be depended on by an 'install-exec-local' rule.
+install-noinst_PROGRAMS: $(noinst_PROGRAMS)
+       $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+       for f in $(noinst_PROGRAMS); do \
+         $(INSTALL_PROGRAM) $$f $(DESTDIR)$(pkglibdir); \
+       done
+
+# Similar to install-noinst_PROGRAMS.
+# Nb: we don't use $(INSTALL_PROGRAM) here because it doesn't work with
+# directories.  XXX: not sure whether the resulting permissions will be
+# correct when using 'cp -R'...
+install-noinst_DSYMS: build-noinst_DSYMS
+       $(mkinstalldirs) $(DESTDIR)$(pkglibdir); \
+       for f in $(noinst_DSYMS); do \
+         cp -R $$f.dSYM $(DESTDIR)$(pkglibdir); \
+       done
+
+# This needs to be depended on by a 'clean-local' rule.
+clean-noinst_DSYMS:
+       for f in $(noinst_DSYMS); do \
+         rm -rf $$f.dSYM; \
+       done
+
+check-local: build-noinst_DSYMS
+
+clean-local: clean-noinst_DSYMS
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.S b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.S
new file mode 100644 (file)
index 0000000..23306b2
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.S
@@ -0,0 +1,186 @@
+
+/* This is really horrible.  It checks that the
+   stack unwinder understands DW_CFA_def_cfa_expression.  It is
+   the result of compiling this:
+       
+void bbb ( long x )
+{
+  __asm__ __volatile__(
+      "cmp %0,%0\n\t"
+      "jz .Lxyzzy\n"
+      ".Lxyzzy:\n\t"
+      : : "r"(x) : "cc"
+      );
+}
+
+void aaa ( long x ) {
+  bbb(x);
+}
+
+int main ( void )
+{
+  long *p = malloc(8);
+  aaa( *p );
+  return 0;
+}
+
+and bracketing the cmp/jz insns with a move down/up by 256 of %rsp.
+The .jz causes memcheck to complain, hence unwind the stack, but
+that cannot be successfully done unless the return address can
+be found.  Hence the handwritten CFI below uses
+DW_CFA_def_cfa_expression to make that possible.
+
+The CFI below isn't really right in that aaa appears twice
+in the backtrace
+
+==12868== Conditional jump or move depends on uninitialised value(s)
+==12868==    at 0x400512: bbb (in /home/sewardj/VgTRUNK/trunk/mad0)
+==12868==    by 0x400520: aaa (in /home/sewardj/VgTRUNK/trunk/mad0)
+==12868==    by 0x400520: aaa (in /home/sewardj/VgTRUNK/trunk/mad0)
+==12868==    by 0x400538: main (in /home/sewardj/VgTRUNK/trunk/mad0)
+
+but GDB behaves the same, so I'm not too concerned - indicates
+the problem is with the handwritten CFI and not with
+V's interpretation of it.
+*/     
+       
+       
+       .file   "bad0.c"
+       .text
+
+
+.globl bbb
+       .type   bbb, @function
+bbb:
+.LFB2:
+.Lbbb1:
+       subq $256,%rsp
+.Lbbb2:
+       cmp %rdi,%rdi
+       jz .Lxyzzy
+.Lxyzzy:
+       addq $256,%rsp
+.Lbbb3:
+       ret
+.Lbbb4:
+.LFE2:
+       .size   bbb, .-bbb
+
+       
+       
+.globl aaa
+       .type   aaa, @function
+aaa:
+.LFB3:
+       call    bbb
+       rep ; ret
+.LFE3:
+       .size   aaa, .-aaa
+.globl main
+       .type   main, @function
+main:
+.LFB4:
+       subq    $8, %rsp
+.LCFI0:
+       movl    $8, %edi
+       call    malloc
+       movq    (%rax), %rdi
+       call    aaa
+       movl    $0, %eax
+       addq    $8, %rsp
+       ret
+.LFE4:
+       .size   main, .-main
+       .section        .eh_frame,"a",@progbits
+.Lframe1:
+       .long   .LECIE1-.LSCIE1
+.LSCIE1:
+       .long   0x0
+       .byte   0x1
+       .string "zR"
+       .uleb128 0x1
+       .sleb128 -8
+       .byte   0x10
+       .uleb128 0x1
+       .byte   0x3
+       .byte   0xc
+       .uleb128 0x7
+       .uleb128 0x8
+       .byte   0x90
+       .uleb128 0x1
+       .align 8
+.LECIE1:
+
+/* start of the FDE for bbb */
+.LSFDE1:
+       .long   .LEFDE1-.LASFDE1        /* length of FDE */
+.LASFDE1:
+       .long   .LASFDE1-.Lframe1       /* CIE pointer */
+       .long   .LFB2                   /* & bbb */
+       .long   .LFE2-.LFB2             /* sizeof(bbb) */
+       .uleb128 0                      /* augmentation length */
+       .byte   0x40 + .Lbbb2 - .Lbbb1  /* _advance_loc to .Lbbb2 */
+
+       /* For the section in between .Lbbb2 and .Lbbb3, set the
+       CFA to be %rsp+256, and set the return address (dwarf r16)
+       to be *(CFA+0). */
+       .byte     0x0f  /* _def_cfa_expression */
+       .uleb128  .Lexpr1e-.Lexpr1s /* length of expression */
+.Lexpr1s:
+       .byte   0x77    /* DW_OP_breg7 == %rsp + sleb128(0) */
+       .sleb128 0
+       .byte   0x40    /* DW_OP_lit16 */
+       .byte   0x40    /* DW_OP_lit16 */
+       .byte   0x1e    /* DW_OP_mul */
+       .byte   0x22    /* DW_OP_plus */
+.Lexpr1e:
+       .byte 0x90      /* _cfa_offset: r16 = *(cfa+0) */
+       .uleb128 0
+
+       .byte   0x40 + .Lbbb3 - .Lbbb2  /* _advance_loc to .Lbbb3 */
+
+       /* For the section .Lbbb3 to .Lbbb4, should set CFA back to
+       something sensible.  This tries to do it but still causes
+       GDB to show an extraneous aaa frame on the stack.  Oh well. */
+       /* Now set CFA back to %rsp+0 */
+       .byte     0x0f  /* _def_cfa_expression */
+       .uleb128  .Lexpr2e-.Lexpr2s /* length of expression */
+.Lexpr2s:
+       .byte   0x77    /* DW_OP_breg7 == %rsp + sleb128(0) */
+       .sleb128 0
+       .byte   0x30    /* DW_OP_lit0 */
+       .byte   0x1c    /* DW_OP_minus */
+.Lexpr2e:
+       .byte 0x90      /* _cfa_offset: r16 = *(cfa+0) */
+       .uleb128 0
+
+       .byte   0x40 + .Lbbb4 - .Lbbb3  /* _advance_loc to .Lbbb4 */
+       .uleb128 0x0                    /* ??? */
+       .align 8
+.LEFDE1:
+/* end of the FDE for bbb */
+       
+.LSFDE3:
+       .long   .LEFDE3-.LASFDE3
+.LASFDE3:
+       .long   .LASFDE3-.Lframe1
+       .long   .LFB3
+       .long   .LFE3-.LFB3
+       .uleb128 0x0
+       .align 8
+.LEFDE3:
+.LSFDE5:
+       .long   .LEFDE5-.LASFDE5
+.LASFDE5:
+       .long   .LASFDE5-.Lframe1
+       .long   .LFB4
+       .long   .LFE4-.LFB4
+       .uleb128 0x0
+       .byte   0x4
+       .long   .LCFI0-.LFB4
+       .byte   0xe
+       .uleb128 0x10
+       .align 8
+.LEFDE5:
+       .ident  "GCC: (GNU) 4.1.2 20061115 (prerelease) (SUSE Linux)"
+       .section        .note.GNU-stack,"",@progbits

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.stderr.exp
new file mode 100644 (file)
index 0000000..16112c4
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.stderr.exp
@@ -0,0 +1,6 @@
+Conditional jump or move depends on uninitialised value(s)
+   at 0x........: bbb (bogus.S:0)
+   by 0x........: aaa (bogus.S:0)
+   by 0x........: aaa (bogus.S:0)
+   by 0x........: main (bogus.S:0)
+

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.vgtest
new file mode 100644 (file)
index 0000000..2016f32
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/defcfaexpr.vgtest
@@ -0,0 +1,3 @@
+prog: defcfaexpr
+stderr_filter: filter_defcfaexpr
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/filter_defcfaexpr b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/filter_defcfaexpr
new file mode 100644 (file)
index 0000000..5f4af58
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/filter_defcfaexpr
@@ -0,0 +1,28 @@
+#! /bin/sh
+
+# change 
+#
+# ==6019==    at 0x400512: bbb (in 
+#           /home/sewardj/VgTRUNK/trunk/memcheck/tests/amd64/defcfaexpr)
+#
+# to
+#
+# ==6019==    at 0x400512: bbb (in bogus.S:0)
+#
+# and then to
+#
+# ==6019==    at 0x400512: bbb (bogus.S:0)
+#
+# Then the standard ./filter_stderr won't screw it up any more,
+# instead producing what we want, which is
+#
+#   at 0x........: bbb (bogus.S:0)
+#
+# where the important point is that the function name is intact.
+# since the point of this test is to check that V can unwind the
+# stack given the unusual CFAs describing it.
+
+
+sed "s/\/.*\/tests\/amd64-linux\/defcfaexpr/bogus.S:0/" | \
+      sed "s/(in /(/" | \
+      ./filter_stderr

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/filter_stderr b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/filter_stderr
new file mode 100644 (file)
index 0000000..0ae9313
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/filter_stderr
@@ -0,0 +1,3 @@
+#! /bin/sh
+
+../filter_stderr

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.c
new file mode 100644 (file)
index 0000000..3a0fb0c
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.c
@@ -0,0 +1,52 @@
+
+#undef _GNU_SOURCE
+#define _GNU_SOURCE 1
+
+#include <signal.h>
+#include <stdio.h>
+#include <sys/ucontext.h>
+
+static char* rip_at_sig = NULL;
+
+static void int_handler(int signum, siginfo_t *si, void *uc_arg)
+{
+   ucontext_t *uc = (ucontext_t *)uc_arg;
+   /* Note that uc->uc_mcontext is an embedded struct, not a pointer */
+   mcontext_t *mc = &(uc->uc_mcontext);
+   void *pc = (void*)mc->gregs[REG_RIP];
+   printf("in int_handler, RIP is ...\n");
+   rip_at_sig = pc;
+}
+
+static void register_handler(int sig, void *handler)
+{
+   struct sigaction sa;
+   sa.sa_flags = SA_RESTART | SA_SIGINFO;
+   sigfillset(&sa.sa_mask);
+   sa.sa_sigaction = handler;
+   sigaction(sig, &sa, NULL);
+}
+
+int main(void) {
+   char *intaddr = NULL;
+   puts("main");
+   register_handler(SIGTRAP, int_handler);
+   asm volatile(
+      "movabsq $zz_int, %%rdx\n"
+      "mov %%rdx, %0\n"
+      "zz_int:\n"
+      "int $3\n"
+      : /* no outputs */
+      : "m" (intaddr) /* input: address of var to store target addr to */
+      : /* clobbers */ "rdx"
+      );
+   /* intaddr is the address of the int 3 insn.  rip_at_sig is the PC
+      after the exception, which should be the next insn along.
+      Hence: */
+   if (intaddr != NULL && rip_at_sig != NULL
+       && rip_at_sig == intaddr+1)
+     printf("PASS\n");
+   else
+     printf("FAIL\n");
+   return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.stdout.exp
new file mode 100644 (file)
index 0000000..5bcea36
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.stdout.exp
@@ -0,0 +1,3 @@
+main
+in int_handler, RIP is ...
+PASS

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.vgtest
new file mode 100644 (file)
index 0000000..1992aa3
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64-linux/int3-amd64.vgtest
@@ -0,0 +1,2 @@
+prog: int3-amd64
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/Makefile.am
index a48a105edc9126dac4b72b2bf5871f6eba18903b..d276e992c466b4bfdd1e6bd14d2ada9bfbb45ae9 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/Makefile.am
@@ -12,26 +12,19 @@ EXTRA_DIST = \
        bt_everything.stderr.exp bt_everything.stdout.exp \
                bt_everything.vgtest \
        bug132146.vgtest bug132146.stderr.exp bug132146.stdout.exp \
        bt_everything.stderr.exp bt_everything.stdout.exp \
                bt_everything.vgtest \
        bug132146.vgtest bug132146.stderr.exp bug132146.stdout.exp \

-       defcfaexpr.vgtest defcfaexpr.stderr.exp filter_defcfaexpr \

        fxsave-amd64.vgtest fxsave-amd64.stdout.exp fxsave-amd64.stderr.exp \
        fxsave-amd64.vgtest fxsave-amd64.stdout.exp fxsave-amd64.stderr.exp \

-       int3-amd64.vgtest int3-amd64.stdout.exp int3-amd64.stderr.exp \

        more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \
        sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \
        xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \
        xor-undef-amd64.vgtest
 
        more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \
        sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \
        xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \
        xor-undef-amd64.vgtest
 

-check_PROGRAMS = bt_everything bug132146 fxsave-amd64 \
-               xor-undef-amd64
-
-# DDD: not sure if these ones should work on Darwin or not... if not, should
-# be moved into amd64-linux/.
-if ! VGCONF_OS_IS_DARWIN
-   check_PROGRAMS += \
-       defcfaexpr \
-       int3-amd64 \
+check_PROGRAMS = \
+       bt_everything \
+       bug132146 \
+       fxsave-amd64 \

        more_x87_fp \
        more_x87_fp \

-       sse_memory
-endif
+       sse_memory \
+       xor-undef-amd64

 
 AM_CFLAGS    += @FLAG_M64@
 AM_CXXFLAGS  += @FLAG_M64@
 
 AM_CFLAGS    += @FLAG_M64@
 AM_CXXFLAGS  += @FLAG_M64@


@@ -41,4 +34,3 @@ more_x87_fp_CFLAGS    = $(AM_CFLAGS) -O -ffast-math -mfpmath=387 \
                                -mfancy-math-387
 more_x87_fp_LDADD      = -lm
 
                                -mfancy-math-387
 more_x87_fp_LDADD      = -lm
 

-defcfaexpr_SOURCES     = defcfaexpr.S

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/Makefile.in
index 10305f7e7a11155009008b645d5ab2b84203c579..bbe9a368d25b4e4d81e858fa7d237dc8dd603b83 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/Makefile.in
@@ -47,16 +47,8 @@ DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
        $(top_srcdir)/Makefile.tool-tests.am
 check_PROGRAMS = bt_everything$(EXEEXT) bug132146$(EXEEXT) \
        $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
        $(top_srcdir)/Makefile.tool-tests.am
 check_PROGRAMS = bt_everything$(EXEEXT) bug132146$(EXEEXT) \

-       fxsave-amd64$(EXEEXT) xor-undef-amd64$(EXEEXT) $(am__EXEEXT_1)
-
-# DDD: not sure if these ones should work on Darwin or not... if not, should
-# be moved into amd64-linux/.
-@VGCONF_OS_IS_DARWIN_FALSE@am__append_1 = \
-@VGCONF_OS_IS_DARWIN_FALSE@    defcfaexpr \
-@VGCONF_OS_IS_DARWIN_FALSE@    int3-amd64 \
-@VGCONF_OS_IS_DARWIN_FALSE@    more_x87_fp \
-@VGCONF_OS_IS_DARWIN_FALSE@    sse_memory
-
+       fxsave-amd64$(EXEEXT) more_x87_fp$(EXEEXT) sse_memory$(EXEEXT) \
+       xor-undef-amd64$(EXEEXT)

 subdir = memcheck/tests/amd64
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = memcheck/tests/amd64
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -66,25 +58,15 @@ mkinstalldirs = $(install_sh) -d
 CONFIG_HEADER = $(top_builddir)/config.h
 CONFIG_CLEAN_FILES =
 CONFIG_CLEAN_VPATH_FILES =
 CONFIG_HEADER = $(top_builddir)/config.h
 CONFIG_CLEAN_FILES =
 CONFIG_CLEAN_VPATH_FILES =

-@VGCONF_OS_IS_DARWIN_FALSE@am__EXEEXT_1 = defcfaexpr$(EXEEXT) \
-@VGCONF_OS_IS_DARWIN_FALSE@    int3-amd64$(EXEEXT) \
-@VGCONF_OS_IS_DARWIN_FALSE@    more_x87_fp$(EXEEXT) \
-@VGCONF_OS_IS_DARWIN_FALSE@    sse_memory$(EXEEXT)

 bt_everything_SOURCES = bt_everything.c
 bt_everything_OBJECTS = bt_everything.$(OBJEXT)
 bt_everything_LDADD = $(LDADD)
 bug132146_SOURCES = bug132146.c
 bug132146_OBJECTS = bug132146.$(OBJEXT)
 bug132146_LDADD = $(LDADD)
 bt_everything_SOURCES = bt_everything.c
 bt_everything_OBJECTS = bt_everything.$(OBJEXT)
 bt_everything_LDADD = $(LDADD)
 bug132146_SOURCES = bug132146.c
 bug132146_OBJECTS = bug132146.$(OBJEXT)
 bug132146_LDADD = $(LDADD)

-am_defcfaexpr_OBJECTS = defcfaexpr.$(OBJEXT)
-defcfaexpr_OBJECTS = $(am_defcfaexpr_OBJECTS)
-defcfaexpr_LDADD = $(LDADD)

 fxsave_amd64_SOURCES = fxsave-amd64.c
 fxsave_amd64_OBJECTS = fxsave-amd64.$(OBJEXT)
 fxsave_amd64_LDADD = $(LDADD)
 fxsave_amd64_SOURCES = fxsave-amd64.c
 fxsave_amd64_OBJECTS = fxsave-amd64.$(OBJEXT)
 fxsave_amd64_LDADD = $(LDADD)

-int3_amd64_SOURCES = int3-amd64.c
-int3_amd64_OBJECTS = int3-amd64.$(OBJEXT)
-int3_amd64_LDADD = $(LDADD)

 more_x87_fp_SOURCES = more_x87_fp.c
 more_x87_fp_OBJECTS = more_x87_fp-more_x87_fp.$(OBJEXT)
 more_x87_fp_DEPENDENCIES =
 more_x87_fp_SOURCES = more_x87_fp.c
 more_x87_fp_OBJECTS = more_x87_fp-more_x87_fp.$(OBJEXT)
 more_x87_fp_DEPENDENCIES =


@@ -101,18 +83,14 @@ DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 am__depfiles_maybe = depfiles
 am__mv = mv -f
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 am__depfiles_maybe = depfiles
 am__mv = mv -f

-CPPASCOMPILE = $(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
-       $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CCASFLAGS) $(CCASFLAGS)

 COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
        $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
 CCLD = $(CC)
 LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
 COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
        $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
 CCLD = $(CC)
 LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@

-SOURCES = bt_everything.c bug132146.c $(defcfaexpr_SOURCES) \
-       fxsave-amd64.c int3-amd64.c more_x87_fp.c sse_memory.c \
-       xor-undef-amd64.c
-DIST_SOURCES = bt_everything.c bug132146.c $(defcfaexpr_SOURCES) \
-       fxsave-amd64.c int3-amd64.c more_x87_fp.c sse_memory.c \
-       xor-undef-amd64.c
+SOURCES = bt_everything.c bug132146.c fxsave-amd64.c more_x87_fp.c \
+       sse_memory.c xor-undef-amd64.c
+DIST_SOURCES = bt_everything.c bug132146.c fxsave-amd64.c \
+       more_x87_fp.c sse_memory.c xor-undef-amd64.c

 ETAGS = etags
 CTAGS = ctags
 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
 ETAGS = etags
 CTAGS = ctags
 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)


@@ -153,6 +131,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -187,14 +166,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -277,7 +260,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -336,7 +321,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -351,8 +336,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -420,9 +405,7 @@ EXTRA_DIST = \
        bt_everything.stderr.exp bt_everything.stdout.exp \
                bt_everything.vgtest \
        bug132146.vgtest bug132146.stderr.exp bug132146.stdout.exp \
        bt_everything.stderr.exp bt_everything.stdout.exp \
                bt_everything.vgtest \
        bug132146.vgtest bug132146.stderr.exp bug132146.stdout.exp \

-       defcfaexpr.vgtest defcfaexpr.stderr.exp filter_defcfaexpr \

        fxsave-amd64.vgtest fxsave-amd64.stdout.exp fxsave-amd64.stderr.exp \
        fxsave-amd64.vgtest fxsave-amd64.stdout.exp fxsave-amd64.stderr.exp \

-       int3-amd64.vgtest int3-amd64.stdout.exp int3-amd64.stderr.exp \

        more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \
        sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \
        xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \
        more_x87_fp.stderr.exp more_x87_fp.stdout.exp more_x87_fp.vgtest \
        sse_memory.stderr.exp sse_memory.stdout.exp sse_memory.vgtest \
        xor-undef-amd64.stderr.exp xor-undef-amd64.stdout.exp \


@@ -432,11 +415,10 @@ more_x87_fp_CFLAGS = $(AM_CFLAGS) -O -ffast-math -mfpmath=387 \
                                -mfancy-math-387
 
 more_x87_fp_LDADD = -lm
                                -mfancy-math-387
 
 more_x87_fp_LDADD = -lm

-defcfaexpr_SOURCES = defcfaexpr.S

 all: all-am
 
 .SUFFIXES:
 all: all-am
 
 .SUFFIXES:

-.SUFFIXES: .S .c .o .obj
+.SUFFIXES: .c .o .obj

 $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
        @for dep in $?; do \
          case '$(am__configure_deps)' in \
 $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/Makefile.tool-tests.am $(top_srcdir)/Makefile.all.am $(am__configure_deps)
        @for dep in $?; do \
          case '$(am__configure_deps)' in \


@@ -476,15 +458,9 @@ bt_everything$(EXEEXT): $(bt_everything_OBJECTS) $(bt_everything_DEPENDENCIES)
 bug132146$(EXEEXT): $(bug132146_OBJECTS) $(bug132146_DEPENDENCIES) 
        @rm -f bug132146$(EXEEXT)
        $(LINK) $(bug132146_OBJECTS) $(bug132146_LDADD) $(LIBS)
 bug132146$(EXEEXT): $(bug132146_OBJECTS) $(bug132146_DEPENDENCIES) 
        @rm -f bug132146$(EXEEXT)
        $(LINK) $(bug132146_OBJECTS) $(bug132146_LDADD) $(LIBS)

-defcfaexpr$(EXEEXT): $(defcfaexpr_OBJECTS) $(defcfaexpr_DEPENDENCIES) 
-       @rm -f defcfaexpr$(EXEEXT)
-       $(LINK) $(defcfaexpr_OBJECTS) $(defcfaexpr_LDADD) $(LIBS)

 fxsave-amd64$(EXEEXT): $(fxsave_amd64_OBJECTS) $(fxsave_amd64_DEPENDENCIES) 
        @rm -f fxsave-amd64$(EXEEXT)
        $(LINK) $(fxsave_amd64_OBJECTS) $(fxsave_amd64_LDADD) $(LIBS)
 fxsave-amd64$(EXEEXT): $(fxsave_amd64_OBJECTS) $(fxsave_amd64_DEPENDENCIES) 
        @rm -f fxsave-amd64$(EXEEXT)
        $(LINK) $(fxsave_amd64_OBJECTS) $(fxsave_amd64_LDADD) $(LIBS)

-int3-amd64$(EXEEXT): $(int3_amd64_OBJECTS) $(int3_amd64_DEPENDENCIES) 
-       @rm -f int3-amd64$(EXEEXT)
-       $(LINK) $(int3_amd64_OBJECTS) $(int3_amd64_LDADD) $(LIBS)

 more_x87_fp$(EXEEXT): $(more_x87_fp_OBJECTS) $(more_x87_fp_DEPENDENCIES) 
        @rm -f more_x87_fp$(EXEEXT)
        $(more_x87_fp_LINK) $(more_x87_fp_OBJECTS) $(more_x87_fp_LDADD) $(LIBS)
 more_x87_fp$(EXEEXT): $(more_x87_fp_OBJECTS) $(more_x87_fp_DEPENDENCIES) 
        @rm -f more_x87_fp$(EXEEXT)
        $(more_x87_fp_LINK) $(more_x87_fp_OBJECTS) $(more_x87_fp_LDADD) $(LIBS)


@@ -503,27 +479,11 @@ distclean-compile:
 
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bt_everything.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132146.Po@am__quote@
 
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bt_everything.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bug132146.Po@am__quote@

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/defcfaexpr.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxsave-amd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fxsave-amd64.Po@am__quote@

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/int3-amd64.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/more_x87_fp-more_x87_fp.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sse_memory.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xor-undef-amd64.Po@am__quote@
 
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/more_x87_fp-more_x87_fp.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sse_memory.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xor-undef-amd64.Po@am__quote@
 

-.S.o:
-@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-@am__fastdepCCAS_FALSE@        $(CPPASCOMPILE) -c -o $@ $<
-
-.S.obj:
-@am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'`
-@am__fastdepCCAS_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    source='$<' object='$@' libtool=no @AMDEPBACKSLASH@
-@AMDEP_TRUE@@am__fastdepCCAS_FALSE@    DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
-@am__fastdepCCAS_FALSE@        $(CPPASCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
-

 .c.o:
 @am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
 .c.o:
 @am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
 @am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.S b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.S
index 23306b25e187925abe75ce20c4be0c928b77900d..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.S
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.S
@@ -1,186 +0,0 @@
-
-/* This is really horrible.  It checks that the
-   stack unwinder understands DW_CFA_def_cfa_expression.  It is
-   the result of compiling this:
-       
-void bbb ( long x )
-{
-  __asm__ __volatile__(
-      "cmp %0,%0\n\t"
-      "jz .Lxyzzy\n"
-      ".Lxyzzy:\n\t"
-      : : "r"(x) : "cc"
-      );
-}
-
-void aaa ( long x ) {
-  bbb(x);
-}
-
-int main ( void )
-{
-  long *p = malloc(8);
-  aaa( *p );
-  return 0;
-}
-
-and bracketing the cmp/jz insns with a move down/up by 256 of %rsp.
-The .jz causes memcheck to complain, hence unwind the stack, but
-that cannot be successfully done unless the return address can
-be found.  Hence the handwritten CFI below uses
-DW_CFA_def_cfa_expression to make that possible.
-
-The CFI below isn't really right in that aaa appears twice
-in the backtrace
-
-==12868== Conditional jump or move depends on uninitialised value(s)
-==12868==    at 0x400512: bbb (in /home/sewardj/VgTRUNK/trunk/mad0)
-==12868==    by 0x400520: aaa (in /home/sewardj/VgTRUNK/trunk/mad0)
-==12868==    by 0x400520: aaa (in /home/sewardj/VgTRUNK/trunk/mad0)
-==12868==    by 0x400538: main (in /home/sewardj/VgTRUNK/trunk/mad0)
-
-but GDB behaves the same, so I'm not too concerned - indicates
-the problem is with the handwritten CFI and not with
-V's interpretation of it.
-*/     
-       
-       
-       .file   "bad0.c"
-       .text
-
-
-.globl bbb
-       .type   bbb, @function
-bbb:
-.LFB2:
-.Lbbb1:
-       subq $256,%rsp
-.Lbbb2:
-       cmp %rdi,%rdi
-       jz .Lxyzzy
-.Lxyzzy:
-       addq $256,%rsp
-.Lbbb3:
-       ret
-.Lbbb4:
-.LFE2:
-       .size   bbb, .-bbb
-
-       
-       
-.globl aaa
-       .type   aaa, @function
-aaa:
-.LFB3:
-       call    bbb
-       rep ; ret
-.LFE3:
-       .size   aaa, .-aaa
-.globl main
-       .type   main, @function
-main:
-.LFB4:
-       subq    $8, %rsp
-.LCFI0:
-       movl    $8, %edi
-       call    malloc
-       movq    (%rax), %rdi
-       call    aaa
-       movl    $0, %eax
-       addq    $8, %rsp
-       ret
-.LFE4:
-       .size   main, .-main
-       .section        .eh_frame,"a",@progbits
-.Lframe1:
-       .long   .LECIE1-.LSCIE1
-.LSCIE1:
-       .long   0x0
-       .byte   0x1
-       .string "zR"
-       .uleb128 0x1
-       .sleb128 -8
-       .byte   0x10
-       .uleb128 0x1
-       .byte   0x3
-       .byte   0xc
-       .uleb128 0x7
-       .uleb128 0x8
-       .byte   0x90
-       .uleb128 0x1
-       .align 8
-.LECIE1:
-
-/* start of the FDE for bbb */
-.LSFDE1:
-       .long   .LEFDE1-.LASFDE1        /* length of FDE */
-.LASFDE1:
-       .long   .LASFDE1-.Lframe1       /* CIE pointer */
-       .long   .LFB2                   /* & bbb */
-       .long   .LFE2-.LFB2             /* sizeof(bbb) */
-       .uleb128 0                      /* augmentation length */
-       .byte   0x40 + .Lbbb2 - .Lbbb1  /* _advance_loc to .Lbbb2 */
-
-       /* For the section in between .Lbbb2 and .Lbbb3, set the
-       CFA to be %rsp+256, and set the return address (dwarf r16)
-       to be *(CFA+0). */
-       .byte     0x0f  /* _def_cfa_expression */
-       .uleb128  .Lexpr1e-.Lexpr1s /* length of expression */
-.Lexpr1s:
-       .byte   0x77    /* DW_OP_breg7 == %rsp + sleb128(0) */
-       .sleb128 0
-       .byte   0x40    /* DW_OP_lit16 */
-       .byte   0x40    /* DW_OP_lit16 */
-       .byte   0x1e    /* DW_OP_mul */
-       .byte   0x22    /* DW_OP_plus */
-.Lexpr1e:
-       .byte 0x90      /* _cfa_offset: r16 = *(cfa+0) */
-       .uleb128 0
-
-       .byte   0x40 + .Lbbb3 - .Lbbb2  /* _advance_loc to .Lbbb3 */
-
-       /* For the section .Lbbb3 to .Lbbb4, should set CFA back to
-       something sensible.  This tries to do it but still causes
-       GDB to show an extraneous aaa frame on the stack.  Oh well. */
-       /* Now set CFA back to %rsp+0 */
-       .byte     0x0f  /* _def_cfa_expression */
-       .uleb128  .Lexpr2e-.Lexpr2s /* length of expression */
-.Lexpr2s:
-       .byte   0x77    /* DW_OP_breg7 == %rsp + sleb128(0) */
-       .sleb128 0
-       .byte   0x30    /* DW_OP_lit0 */
-       .byte   0x1c    /* DW_OP_minus */
-.Lexpr2e:
-       .byte 0x90      /* _cfa_offset: r16 = *(cfa+0) */
-       .uleb128 0
-
-       .byte   0x40 + .Lbbb4 - .Lbbb3  /* _advance_loc to .Lbbb4 */
-       .uleb128 0x0                    /* ??? */
-       .align 8
-.LEFDE1:
-/* end of the FDE for bbb */
-       
-.LSFDE3:
-       .long   .LEFDE3-.LASFDE3
-.LASFDE3:
-       .long   .LASFDE3-.Lframe1
-       .long   .LFB3
-       .long   .LFE3-.LFB3
-       .uleb128 0x0
-       .align 8
-.LEFDE3:
-.LSFDE5:
-       .long   .LEFDE5-.LASFDE5
-.LASFDE5:
-       .long   .LASFDE5-.Lframe1
-       .long   .LFB4
-       .long   .LFE4-.LFB4
-       .uleb128 0x0
-       .byte   0x4
-       .long   .LCFI0-.LFB4
-       .byte   0xe
-       .uleb128 0x10
-       .align 8
-.LEFDE5:
-       .ident  "GCC: (GNU) 4.1.2 20061115 (prerelease) (SUSE Linux)"
-       .section        .note.GNU-stack,"",@progbits

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.stderr.exp
index 16112c4ae5328cc3a9a71e20a50c752b19073fb3..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.stderr.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.stderr.exp
@@ -1,6 +0,0 @@
-Conditional jump or move depends on uninitialised value(s)
-   at 0x........: bbb (bogus.S:0)
-   by 0x........: aaa (bogus.S:0)
-   by 0x........: aaa (bogus.S:0)
-   by 0x........: main (bogus.S:0)
-

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.vgtest
index 2016f32a246fdefd50d4e4e9532d72186483985a..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.vgtest
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/defcfaexpr.vgtest
@@ -1,3 +0,0 @@
-prog: defcfaexpr
-stderr_filter: filter_defcfaexpr
-vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/filter_defcfaexpr b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/filter_defcfaexpr
index 7fa1afee71996408ac2a5aedc8cb4a676ae133c6..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100755 (executable)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/filter_defcfaexpr
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/filter_defcfaexpr
@@ -1,28 +0,0 @@
-#! /bin/sh
-
-# change 
-#
-# ==6019==    at 0x400512: bbb (in 
-#           /home/sewardj/VgTRUNK/trunk/memcheck/tests/amd64/defcfaexpr)
-#
-# to
-#
-# ==6019==    at 0x400512: bbb (in bogus.S:0)
-#
-# and then to
-#
-# ==6019==    at 0x400512: bbb (bogus.S:0)
-#
-# Then the standard ./filter_stderr won't screw it up any more,
-# instead producing what we want, which is
-#
-#   at 0x........: bbb (bogus.S:0)
-#
-# where the important point is that the function name is intact.
-# since the point of this test is to check that V can unwind the
-# stack given the unusual CFAs describing it.
-
-
-sed "s/\/.*\/tests\/amd64\/defcfaexpr/bogus.S:0/" | \
-      sed "s/(in /(/" | \
-      ./filter_stderr

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.c
index 3a0fb0c8b0ff4f85a8f6b278ed621d8d873b44e7..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.c
@@ -1,52 +0,0 @@
-
-#undef _GNU_SOURCE
-#define _GNU_SOURCE 1
-
-#include <signal.h>
-#include <stdio.h>
-#include <sys/ucontext.h>
-
-static char* rip_at_sig = NULL;
-
-static void int_handler(int signum, siginfo_t *si, void *uc_arg)
-{
-   ucontext_t *uc = (ucontext_t *)uc_arg;
-   /* Note that uc->uc_mcontext is an embedded struct, not a pointer */
-   mcontext_t *mc = &(uc->uc_mcontext);
-   void *pc = (void*)mc->gregs[REG_RIP];
-   printf("in int_handler, RIP is ...\n");
-   rip_at_sig = pc;
-}
-
-static void register_handler(int sig, void *handler)
-{
-   struct sigaction sa;
-   sa.sa_flags = SA_RESTART | SA_SIGINFO;
-   sigfillset(&sa.sa_mask);
-   sa.sa_sigaction = handler;
-   sigaction(sig, &sa, NULL);
-}
-
-int main(void) {
-   char *intaddr = NULL;
-   puts("main");
-   register_handler(SIGTRAP, int_handler);
-   asm volatile(
-      "movabsq $zz_int, %%rdx\n"
-      "mov %%rdx, %0\n"
-      "zz_int:\n"
-      "int $3\n"
-      : /* no outputs */
-      : "m" (intaddr) /* input: address of var to store target addr to */
-      : /* clobbers */ "rdx"
-      );
-   /* intaddr is the address of the int 3 insn.  rip_at_sig is the PC
-      after the exception, which should be the next insn along.
-      Hence: */
-   if (intaddr != NULL && rip_at_sig != NULL
-       && rip_at_sig == intaddr+1)
-     printf("PASS\n");
-   else
-     printf("FAIL\n");
-   return 0;
-}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.stdout.exp
index 5bcea36782f76691ff1daf19a8ea451131e58ae2..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.stdout.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.stdout.exp
@@ -1,3 +0,0 @@
-main
-in int_handler, RIP is ...
-PASS

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.vgtest
index 1992aa3daa26e5067858eaea6aa42e5f210e19df..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.vgtest
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/int3-amd64.vgtest
@@ -1,2 +0,0 @@
-prog: int3-amd64
-vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/xor-undef-amd64.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/xor-undef-amd64.stderr.exp
index be1f9ed6d7e8121dcb6c178a1e75e4dc37ac4955..ab368954b3dcc760b02b092a50b21bf914bc2676 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/xor-undef-amd64.stderr.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/xor-undef-amd64.stderr.exp
@@ -1,4 +1,3 @@
-

 Conditional jump or move depends on uninitialised value(s)
    at 0x........: main (xor-undef-amd64.c:17)
 
 Conditional jump or move depends on uninitialised value(s)
    at 0x........: main (xor-undef-amd64.c:17)
 


@@ -14,13 +13,3 @@ Conditional jump or move depends on uninitialised value(s)
 Conditional jump or move depends on uninitialised value(s)
    at 0x........: main (xor-undef-amd64.c:117)
 
 Conditional jump or move depends on uninitialised value(s)
    at 0x........: main (xor-undef-amd64.c:117)
 

-
-HEAP SUMMARY:
-    in use at exit: 0 bytes in 0 blocks
-  total heap usage: 1 allocs, 1 frees, 48 bytes allocated
-
-For a detailed leak analysis, rerun with: --leak-check=full
-
-For counts of detected and suppressed errors, rerun with: -v
-Use --track-origins=yes to see where uninitialised values come from
-ERROR SUMMARY: 5 errors from 5 contexts (suppressed: 0 from 0)

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/xor-undef-amd64.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/xor-undef-amd64.vgtest
index b0a9be11d3b1bd10def1846c991f5bf9dc14fcff..6d75090d720bbf6a3bf8e1295b290e76b88cbcfa 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/xor-undef-amd64.vgtest
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/amd64/xor-undef-amd64.vgtest
@@ -1 +1,2 @@
 prog: xor-undef-amd64
 prog: xor-undef-amd64

+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/darwin/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/darwin/Makefile.in
index 492da75182492896c193fe147656d4c02ea292f7..dd2c35b45e9cc29bcd57179a98e89ba5e12fa030 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/darwin/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/darwin/Makefile.in
@@ -135,6 +135,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -169,14 +170,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -259,7 +264,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -318,7 +325,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -333,8 +340,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/filter_leak_cases_possible b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/filter_leak_cases_possible
new file mode 100644 (file)
index 0000000..1b50c53
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/filter_leak_cases_possible
@@ -0,0 +1,4 @@
+#! /bin/sh
+
+./filter_stderr |
+sed -e 's/^leaked.*$//' -e 's/^dubious.*$//' -e 's/^reachable.*$//' -e 's/^suppressed:.*$//'

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/leak-cases-possible.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/leak-cases-possible.stderr.exp
new file mode 100644 (file)
index 0000000..78ad60f
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/leak-cases-possible.stderr.exp
@@ -0,0 +1,22 @@
+
+
+
+
+16 bytes in 1 blocks are definitely lost in loss record ... of ...
+   at 0x........: malloc (vg_replace_malloc.c:...)
+   by 0x........: mk (leak-cases.c:52)
+   by 0x........: f (leak-cases.c:74)
+   by 0x........: main (leak-cases.c:107)
+
+32 (16 direct, 16 indirect) bytes in 1 blocks are definitely lost in loss record ... of ...
+   at 0x........: malloc (vg_replace_malloc.c:...)
+   by 0x........: mk (leak-cases.c:52)
+   by 0x........: f (leak-cases.c:76)
+   by 0x........: main (leak-cases.c:107)
+
+32 (16 direct, 16 indirect) bytes in 1 blocks are definitely lost in loss record ... of ...
+   at 0x........: malloc (vg_replace_malloc.c:...)
+   by 0x........: mk (leak-cases.c:52)
+   by 0x........: f (leak-cases.c:91)
+   by 0x........: main (leak-cases.c:107)
+

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/leak-cases-possible.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/leak-cases-possible.vgtest
new file mode 100644 (file)
index 0000000..146e1b9
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/leak-cases-possible.vgtest
@@ -0,0 +1,3 @@
+prog: leak-cases
+vgopts: -q --leak-check=full --leak-resolution=high --show-possibly-lost=no
+stderr_filter: filter_leak_cases_possible

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/linux/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/linux/Makefile.in
index fb9b56f26d9b6e792419450039b94a7bd1966cf4..4204097aa071daecf3b0364939f077cdd3894d9c 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/linux/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/linux/Makefile.in
@@ -135,6 +135,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -169,14 +170,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -259,7 +264,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -318,7 +325,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -333,8 +340,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/long_namespace_xml.cpp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/long_namespace_xml.cpp
index 0275a579dd7b60ddc803e36b4f6dc69dafe20148..cd34d0613b6adab23eef0a6613f9ccbc8ed8fbe4 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/long_namespace_xml.cpp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/long_namespace_xml.cpp
@@ -14,23 +14,34 @@ int main () {
 
 #else
 
 
 #else
 

+#define N1 abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz
+
+#define N2 ABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZ
+

 #include <iostream>
 #include <stdlib.h>
 #include <iostream>
 #include <stdlib.h>

+#include <stdint.h>
+

 using namespace std;
 
 using namespace std;
 

-namespace abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefgh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-  namespace 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{
+// A function that returns p in such a way that gcc 4.5.x does not recognize
+// that it returns p. Prevents that the optimizer throws the assignment away
+// that occurs just before the free() call.
+static char* idem(char* p) { return (char*)((uintptr_t)p * 2 / 2); }
+
+namespace N1 {
+  namespace N2 {

     void f() {
       cout << "I'm in an asininely long namespace!" << endl;
       char *ptr = (char *)malloc (4);
     void f() {
       cout << "I'm in an asininely long namespace!" << endl;
       char *ptr = (char *)malloc (4);

-      ptr[5] = 0;
+      idem(ptr)[5] = 0;

       free(ptr);
     }
   }
 }
 
 int main() {
       free(ptr);
     }
   }
 }
 
 int main() {

-  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OPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZABCDEFGHIJKLMNOPQRSTUVWXYZ::f();
+  N1::N2::f();

   return 0;
 }
 
   return 0;
 }
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86-linux/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86-linux/Makefile.in
index 284278d6fd2c440418419c61463764925fa93eb1..0920102a5ce4144d227899b426da460686b4d7b2 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86-linux/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86-linux/Makefile.in
@@ -135,6 +135,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -169,14 +170,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -259,7 +264,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -318,7 +325,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -333,8 +340,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86-linux/scalar.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86-linux/scalar.stderr.exp
index 0aa67af1308cc019989ed9d76a94336fb33f4d23..a09a6d64a8bbe24e6664a7e39e637f8331aeed59 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86-linux/scalar.stderr.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86-linux/scalar.stderr.exp
@@ -230,10 +230,6 @@ Syscall param mount(flags) contains uninitialised byte(s)
 Syscall param mount(data) contains uninitialised byte(s)
    ...
 
 Syscall param mount(data) contains uninitialised byte(s)
    ...
 

-Syscall param mount(source) points to unaddressable byte(s)
-   ...
- Address 0x........ is not stack'd, malloc'd or (recently) free'd
-

 Syscall param mount(target) points to unaddressable byte(s)
    ...
  Address 0x........ is not stack'd, malloc'd or (recently) free'd
 Syscall param mount(target) points to unaddressable byte(s)
    ...
  Address 0x........ is not stack'd, malloc'd or (recently) free'd


@@ -505,9 +501,6 @@ Syscall param fcntl(arg) contains uninitialised byte(s)
 -----------------------------------------------------
  55:          __NR_fcntl (GETLK) 1s 0m
 -----------------------------------------------------
 -----------------------------------------------------
  55:          __NR_fcntl (GETLK) 1s 0m
 -----------------------------------------------------

-
-More than 100 errors detected.  Subsequent errors
-will still be recorded, but in less detail than before.

 Syscall param fcntl(lock) contains uninitialised byte(s)
    ...
 
 Syscall param fcntl(lock) contains uninitialised byte(s)
    ...
 


@@ -517,6 +510,9 @@ Syscall param fcntl(lock) contains uninitialised byte(s)
 -----------------------------------------------------
  57:        __NR_setpgid 2s 0m
 -----------------------------------------------------
 -----------------------------------------------------
  57:        __NR_setpgid 2s 0m
 -----------------------------------------------------

+
+More than 100 errors detected.  Subsequent errors
+will still be recorded, but in less detail than before.

 Syscall param setpgid(pid) contains uninitialised byte(s)
    ...
 
 Syscall param setpgid(pid) contains uninitialised byte(s)
    ...
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86/Makefile.in
index f5fe251f7a05ef04fbf0f1fb23db4b8e7c993312..e7435613fb27f294eaba07aafb86c76a96703583 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/memcheck/tests/x86/Makefile.in
@@ -157,6 +157,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -191,14 +192,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -281,7 +286,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -340,7 +347,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -355,8 +362,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/mpi/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/mpi/Makefile.in
index d2903203c2ec85ed2d5c7263b2dd8cefa86a28f6..c7126c6ae8107136b90f3267d271c635def7bae5 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/mpi/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/mpi/Makefile.in
@@ -136,6 +136,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -170,14 +171,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -260,7 +265,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -319,7 +326,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -334,8 +341,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/nightly/conf/cellbuzz-cross.sendmail b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/nightly/conf/cellbuzz-cross.sendmail
index 3720e0e6d071d715f91a5f15cb3692a049bdb7e8..ec079a56b3399945c3c6921d734a81781f7f8439 100755 (executable)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/nightly/conf/cellbuzz-cross.sendmail
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/nightly/conf/cellbuzz-cross.sendmail
@@ -3,9 +3,9 @@
 # use: georgia-tech-cellbuzz.sendmail subject file-to-mail [file-to-attach]
 # Don't forget to set the variables 'from' and 'realname' in ~/.muttrc !
 
 # use: georgia-tech-cellbuzz.sendmail subject file-to-mail [file-to-attach]
 # Don't forget to set the variables 'from' and 'realname' in ~/.muttrc !
 

-sender="bart.vanassche@gmail.com"
+sender="bvanassche@acm.org"

 recipients="valgrind-developers@lists.sourceforge.net"
 recipients="valgrind-developers@lists.sourceforge.net"

-#recipients="bart.vanassche@gmail.com"
+#recipients="bvanassche@acm.org"

 if [ $# -ge 3 ]; then
   gzip -9 <"$3" >"$3.gz"
   mutt -s "$1" -a "$3.gz" ${recipients} < "$2"
 if [ $# -ge 3 ]; then
   gzip -9 <"$3" >"$3.gz"
   mutt -s "$1" -a "$3.gz" ${recipients} < "$2"

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/nightly/conf/cellbuzz-native.sendmail b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/nightly/conf/cellbuzz-native.sendmail
index 3720e0e6d071d715f91a5f15cb3692a049bdb7e8..ec079a56b3399945c3c6921d734a81781f7f8439 100755 (executable)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/nightly/conf/cellbuzz-native.sendmail
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/nightly/conf/cellbuzz-native.sendmail
@@ -3,9 +3,9 @@
 # use: georgia-tech-cellbuzz.sendmail subject file-to-mail [file-to-attach]
 # Don't forget to set the variables 'from' and 'realname' in ~/.muttrc !
 
 # use: georgia-tech-cellbuzz.sendmail subject file-to-mail [file-to-attach]
 # Don't forget to set the variables 'from' and 'realname' in ~/.muttrc !
 

-sender="bart.vanassche@gmail.com"
+sender="bvanassche@acm.org"

 recipients="valgrind-developers@lists.sourceforge.net"
 recipients="valgrind-developers@lists.sourceforge.net"

-#recipients="bart.vanassche@gmail.com"
+#recipients="bvanassche@acm.org"

 if [ $# -ge 3 ]; then
   gzip -9 <"$3" >"$3.gz"
   mutt -s "$1" -a "$3.gz" ${recipients} < "$2"
 if [ $# -ge 3 ]; then
   gzip -9 <"$3" >"$3.gz"
   mutt -s "$1" -a "$3.gz" ${recipients} < "$2"

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/Makefile.am
index a1affd3457e4db521634c6e440637d8b682cb2d0..753687eecbaa1da6c41e516b1ea128ccce9e81d8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/Makefile.am
@@ -13,7 +13,8 @@ endif
 
 NONE_SOURCES_COMMON = nl_main.c
 
 
 NONE_SOURCES_COMMON = nl_main.c
 

-none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = $(NONE_SOURCES_COMMON)
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = \
+       $(NONE_SOURCES_COMMON)

 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS       = \


@@ -24,8 +25,16 @@ none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@)
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)

+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+

 if VGCONF_HAVE_PLATFORM_SEC
 if VGCONF_HAVE_PLATFORM_SEC

-none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = $(NONE_SOURCES_COMMON)
+none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES      = \
+       $(NONE_SOURCES_COMMON)

 none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \
 none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS     = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS       = \


@@ -36,6 +45,12 @@ none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDADD        = \
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
        $(TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@)
 none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS      = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)

+none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_SEC@ \
+       $(LINK) \
+       $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+       $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)

 endif
 
 
 endif
 
 

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/Makefile.in
index dca1ad8746b60f811ed94179d883fb467feb19ea..ac061af74ee2e72c70233d7747439a2ec946d5ab 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/Makefile.in
@@ -43,25 +43,9 @@ build_triplet = @build@
 host_triplet = @host@
 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am
 host_triplet = @host@
 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
        $(top_srcdir)/Makefile.all.am $(top_srcdir)/Makefile.tool.am

-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_1 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_LINUX_TRUE@am__append_2 = $(top_builddir)/valt_load_address_x86_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_3 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX_TRUE@am__append_4 = $(top_builddir)/valt_load_address_amd64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_5 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX_TRUE@am__append_6 = $(top_builddir)/valt_load_address_ppc32_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_7 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX_TRUE@am__append_8 = $(top_builddir)/valt_load_address_ppc64_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_9 = $(top_builddir)/valt_load_address_arm_linux.lds
-@VGCONF_PLATFORMS_INCLUDE_ARM_LINUX_TRUE@am__append_10 = $(top_builddir)/valt_load_address_arm_linux.lds
-# No need to generate $(top_builddir)/valt_load_address*.lds; the final
-# executables can be linked to be at any address.  They will be relocated by
-# AIX kernel when they are loaded.
-# Ditto
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_11 = $(top_builddir)/valt_load_address_x86_l4re.lds
-@VGCONF_PLATFORMS_INCLUDE_X86_L4RE_TRUE@am__append_12 = $(top_builddir)/valt_load_address_x86_l4re.lds

 noinst_PROGRAMS = none-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)
 noinst_PROGRAMS = none-@VGCONF_ARCH_PRI@-@VGCONF_OS@$(EXEEXT) \
        $(am__EXEEXT_1)

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_13 = none-@VGCONF_ARCH_SEC@-@VGCONF_OS@
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@am__append_1 = none-@VGCONF_ARCH_SEC@-@VGCONF_OS@

 @VGCONF_HAVE_PLATFORM_SEC_FALSE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = none
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 @VGCONF_HAVE_PLATFORM_SEC_FALSE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_DEPENDENCIES =
 subdir = none
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4


@@ -78,18 +62,12 @@ am__objects_1 = none_@VGCONF_ARCH_PRI@_@VGCONF_OS@-nl_main.$(OBJEXT)
 am_none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)
 am_none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS = $(am__objects_1)
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS =  \
        $(am_none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_OBJECTS)

-none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o $@

 am__none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = nl_main.c
 am__objects_2 = none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.$(OBJEXT)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@am_none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)
 am__none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES_DIST = nl_main.c
 am__objects_2 = none_@VGCONF_ARCH_SEC@_@VGCONF_OS@-nl_main.$(OBJEXT)
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@am_none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(am__objects_2)
 none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS =  \
        $(am_none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_OBJECTS)

-none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = $(CCLD) \
-       $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) $(CFLAGS) \
-       $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS) $(LDFLAGS) -o $@

 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 am__depfiles_maybe = depfiles
 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 am__depfiles_maybe = depfiles


@@ -180,6 +158,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -214,14 +193,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -305,7 +288,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -364,7 +349,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -379,8 +364,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -443,37 +428,37 @@ TOOL_LDADD_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@TOOL_LDADD_@VGCONF_PLATFORM_SEC_CAPS@ = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_SEC_CAPS@) $(TOOL_LDADD_COMMON)
 

-TOOL_LDFLAGS_COMMON_LINUX = -static \
-       -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ \
-       -nodefaultlibs -nostartfiles -u _start

 
 

-TOOL_LDFLAGS_COMMON_AIX5 = -static -Wl,-e_start_valgrind
-TOOL_LDFLAGS_COMMON_DARWIN = -nodefaultlibs -nostartfiles \
-       -Wl,-u,__start -Wl,-e,__start -Wl,-bind_at_load /usr/lib/dyld
+# -Wl,--build-id=none is needed when linking tools on Linux. Without this
+# flag newer ld versions (2.20 and later) create a .note.gnu.build-id at the
+# default text segment address, which of course means the resulting executable
+# is unusable. So we have to tell ld not to generate that, with --build-id=none.
+TOOL_LDFLAGS_COMMON_LINUX = \
+       -static -nodefaultlibs -nostartfiles -u _start @FLAG_NO_BUILD_ID@
+
+TOOL_LDFLAGS_COMMON_AIX5 = \
+       -static -Wl,-e_start_valgrind
+
+TOOL_LDFLAGS_COMMON_DARWIN = \
+       -nodefaultlibs -nostartfiles -Wl,-u,__start -Wl,-e,__start

 
 

-TOOL_LDFLAGS_COMMON_L4RE = -static \
-        -Wl,-defsym,valt_load_address=@VALT_LOAD_ADDRESS@ -Ttext=@VALT_LOAD_ADDRESS@ \
-     -nodefaultlibs -nostartfiles -u _start
+TOOL_LDFLAGS_COMMON_L4RE = \
+        -static -nodefaultlibs -nostartfiles -u _start

 
 TOOL_LDFLAGS_X86_LINUX = \
 
 TOOL_LDFLAGS_X86_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_AMD64_LINUX = \
 
 TOOL_LDFLAGS_AMD64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_amd64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_PPC32_LINUX = \
 
 TOOL_LDFLAGS_PPC32_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc32_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC64_LINUX = \
 
 TOOL_LDFLAGS_PPC64_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_ppc64_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@

 
 TOOL_LDFLAGS_ARM_LINUX = \
 
 TOOL_LDFLAGS_ARM_LINUX = \

-       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_arm_linux.lds
+       $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@

 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@
 
 TOOL_LDFLAGS_PPC32_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX32@


@@ -482,32 +467,28 @@ TOOL_LDFLAGS_PPC64_AIX5 = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \
        $(TOOL_LDFLAGS_COMMON_AIX5) @FLAG_MAIX64@ -Wl,-bbigtoc
 
 TOOL_LDFLAGS_X86_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386 \
-       -Wl,-seg1addr,0xf0080000 \
-       -Wl,-stack_addr,0xf0080000 -Wl,-stack_size,0x80000 \
-       -Wl,-pagezero_size,0xf0000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch i386

 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \
 
 TOOL_LDADD_X86_L4RE = \
        $(TOOL_DEPENDENCIES_@VGCONF_PLATFORM_PRI_CAPS@) \
        $(L4_LDFLAGS) $(L4_CRTN) $(TOOL_LDADD_COMMON)
 
 TOOL_LDFLAGS_X86_L4RE = \

-       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@ \
-       -Wl,-T,$(top_builddir)/valt_load_address_x86_l4re.lds
+       -nostdinc -nostdlib $(L4_CRT0) $(TOOL_LDFLAGS_COMMON_L4RE) @FLAG_M32@

 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \
 
 
 # pagezero can't be unmapped and remapped. Use stack instead.
 # GrP fixme no stack guard
 TOOL_LDFLAGS_AMD64_DARWIN = \

-       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64 \
-       -Wl,-seg1addr,0x7fff55000000 \
-       -Wl,-stack_addr,0x7fff50080000 -Wl,-stack_size,0x7ffe50080000 \
-       -Wl,-pagezero_size,0x100000000
+       $(TOOL_LDFLAGS_COMMON_DARWIN) -arch x86_64

 
 

-BUILT_SOURCES = $(am__append_1) $(am__append_3) $(am__append_5) \
-       $(am__append_7) $(am__append_9) $(am__append_11)
-CLEANFILES = $(am__append_2) $(am__append_4) $(am__append_6) \
-       $(am__append_8) $(am__append_10) $(am__append_12)
+
+# NB for 64-bit darwin.  We may want to set -Wl,-pagezero_size to
+# something smaller than the default of 4G, so as to facilitate
+# loading clients who are also linked thusly (currently m_ume.c
+# will fail to load them).  Although such setting is probably
+# better done in link_tool_exe.c.
+#      -Wl,-pagezero_size,0x100000000

 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff
 
 #----------------------------------------------------------------------------
 # vgpreload_<tool>-<platform>.a stuff


@@ -586,7 +567,9 @@ LIBREPLACEMALLOC_LDFLAGS_X86_L4RE = \
 
 EXTRA_DIST = docs/nl-manual.xml
 NONE_SOURCES_COMMON = nl_main.c
 
 EXTRA_DIST = docs/nl-manual.xml
 NONE_SOURCES_COMMON = nl_main.c

-none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = $(NONE_SOURCES_COMMON)
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES = \
+       $(NONE_SOURCES_COMMON)
+

 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CPPFLAGS = \
        $(AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 


@@ -602,7 +585,16 @@ none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDADD = \
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 
 none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_PRI_CAPS@)
 

-@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = $(NONE_SOURCES_COMMON)
+none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LINK = \
+       $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+       @VALT_LOAD_ADDRESS_PRI@ \
+       $(LINK) \
+       $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_CFLAGS) \
+       $(none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS)
+
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_SOURCES = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(NONE_SOURCES_COMMON)
+

 @VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CPPFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(AM_CPPFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 


@@ -618,8 +610,14 @@ none_@VGCONF_ARCH_PRI@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS = \
 @VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(TOOL_LDFLAGS_@VGCONF_PLATFORM_SEC_CAPS@)
 

-all: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) all-recursive
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LINK = \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(top_builddir)/coregrind/link_tool_exe_@VGCONF_OS@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        @VALT_LOAD_ADDRESS_SEC@ \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(LINK) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_CFLAGS) \
+@VGCONF_HAVE_PLATFORM_SEC_TRUE@        $(none_@VGCONF_ARCH_SEC@_@VGCONF_OS@_LDFLAGS)
+
+all: all-recursive

 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj
 
 .SUFFIXES:
 .SUFFIXES: .c .o .obj


@@ -908,13 +906,11 @@ distdir: $(DISTFILES)
          fi; \
        done
 check-am: all-am
          fi; \
        done
 check-am: all-am

-check: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) check-recursive
+check: check-recursive

 all-am: Makefile $(PROGRAMS) all-local
 installdirs: installdirs-recursive
 installdirs-am:
 all-am: Makefile $(PROGRAMS) all-local
 installdirs: installdirs-recursive
 installdirs-am:

-install: $(BUILT_SOURCES)
-       $(MAKE) $(AM_MAKEFLAGS) install-recursive
+install: install-recursive

 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive
 install-exec: install-exec-recursive
 install-data: install-data-recursive
 uninstall: uninstall-recursive


@@ -931,7 +927,6 @@ install-strip:
 mostlyclean-generic:
 
 clean-generic:
 mostlyclean-generic:
 
 clean-generic:

-       -test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)

 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 distclean-generic:
        -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)


@@ -940,7 +935,6 @@ distclean-generic:
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."
 maintainer-clean-generic:
        @echo "This command is intended for maintainers to use"
        @echo "it deletes files that may require special tools to rebuild."

-       -test -z "$(BUILT_SOURCES)" || rm -f $(BUILT_SOURCES)

 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \
 clean: clean-recursive
 
 clean-am: clean-generic clean-local clean-noinstPROGRAMS \


@@ -1011,9 +1005,8 @@ ps-am:
 
 uninstall-am:
 
 
 uninstall-am:
 

-.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \
-       ctags-recursive install install-am install-strip \
-       tags-recursive
+.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) ctags-recursive \
+       install-am install-strip tags-recursive

 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \
 
 .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \
        all all-am all-local check check-am clean clean-generic \


@@ -1095,65 +1088,6 @@ clean-noinst_DSYMS:
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done
        for f in $(noinst_DSYMS); do \
          rm -rf $$f.dSYM; \
        done

-# GrP untested, possibly hopeless
-
-# Generate a linker script for linking the binaries.  This is the
-# standard gcc linker script, except hacked so that an alternative
-# load address can be specified by (1) asking gcc to use this script
-# (-Wl,-T,valt_load_address.lds) and (2) setting the symbol
-# valt_load_address to the required value
-# (-Wl,-defsym,valt_load_address=0x70000000).
-#
-# Extract ld's default linker script and hack it to our needs.
-# First we cut everything above and below the "=====..." lines at the top
-# and bottom.
-# Then we have to replace the load address with "valt_load_address".
-# The line to replace in has one of the following two forms:
-#
-#   . = 0x08048000 + SIZEOF_HEADERS;
-#
-# or
-#   PROVIDE (__executable_start = 0x08048000); . = 0x08048000 + SIZEOF_HEADERS;
-#
-# So we search for the line with a hex value "+ SIZEOF_HEADERS", and replace
-# all the hex values in that line with "valt_load_address".
-$(top_builddir)/valt_load_address_x86_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_amd64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc32_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_ppc64_linux.lds: Makefile
-       $(CC) -m64 -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_arm_linux.lds: Makefile
-       $(CC) @FLAG_M32@ -Wl,--verbose -nostdlib 2>&1 | sed \
-               -e '1,/^=====\+$$/d' \
-               -e '/^=====\+$$/,/.\*/d' \
-               -e '/\. = \(0x[0-9A-Fa-f]\+\|SEGMENT_START("[^"]\+", 0x[0-9A-Fa-f]\+)\) + SIZEOF_HEADERS/s/0x[0-9A-Fa-f]\+/valt_load_address/g' > $@ \
-       || rm -f $@
-
-$(top_builddir)/valt_load_address_x86_l4re.lds: Makefile $(L4_LDS_stat_bin)
-       cat $(L4_LDS_stat_bin) > $(top_builddir)/valt_load_address_x86_l4re.lds

 
 #----------------------------------------------------------------------------
 # General stuff
 
 #----------------------------------------------------------------------------
 # General stuff

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/Makefile.am
index a299436fca5867d8ddb5db85895800e64f15c63d..d2d71866a12779963c0ec868720b4c5c93aa8799 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/Makefile.am
@@ -114,7 +114,7 @@ EXTRA_DIST = \
        readline1.stderr.exp readline1.stdout.exp \
        readline1.vgtest \
        require-text-symbol-1.vgtest \
        readline1.stderr.exp readline1.stdout.exp \
        readline1.vgtest \
        require-text-symbol-1.vgtest \

-               require-text-symbol-1.stderr.exp
+               require-text-symbol-1.stderr.exp \

        require-text-symbol-2.vgtest \
                require-text-symbol-2.stderr.exp-libcso6 \
        res_search.stderr.exp res_search.stdout.exp res_search.vgtest \
        require-text-symbol-2.vgtest \
                require-text-symbol-2.stderr.exp-libcso6 \
        res_search.stderr.exp res_search.stdout.exp res_search.vgtest \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/Makefile.in
index 74e1114ed5eb635bd7cb41fa13e5059786472104..af5be156014d86657af30c0949a96bdfd3bdb6e9 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/Makefile.in
@@ -472,6 +472,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -506,14 +507,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -596,7 +601,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -655,7 +662,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -670,8 +677,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -812,7 +819,43 @@ EXTRA_DIST = \
        readline1.stderr.exp readline1.stdout.exp \
        readline1.vgtest \
        require-text-symbol-1.vgtest \
        readline1.stderr.exp readline1.stdout.exp \
        readline1.vgtest \
        require-text-symbol-1.vgtest \

-               require-text-symbol-1.stderr.exp
+               require-text-symbol-1.stderr.exp \
+       require-text-symbol-2.vgtest \
+               require-text-symbol-2.stderr.exp-libcso6 \
+       res_search.stderr.exp res_search.stdout.exp res_search.vgtest \
+       resolv.stderr.exp resolv.stdout.exp resolv.vgtest \
+       rlimit_nofile.stderr.exp rlimit_nofile.stdout.exp rlimit_nofile.vgtest \
+       selfrun.stderr.exp selfrun.stdout.exp selfrun.vgtest \
+       sem.stderr.exp sem.stdout.exp sem.vgtest \
+       semlimit.stderr.exp semlimit.stdout.exp semlimit.vgtest \
+       shell shell.vgtest shell.stderr.exp shell.stderr.exp-dash \
+           shell.stdout.exp \
+       shell_badinterp shell_badinterp.vgtest shell_badinterp.stderr.exp \
+       shell_binaryfile shell_binaryfile.vgtest shell_binaryfile.stderr.exp \
+       shell_dir.vgtest shell_dir.stderr.exp \
+       shell_nonexec.vgtest shell_nonexec.stderr.exp \
+       shell_nosuchfile.vgtest shell_nosuchfile.stderr.exp \
+       shell_valid1 shell_valid1.vgtest shell_valid1.stderr.exp \
+       shell_valid2 shell_valid2.vgtest shell_valid2.stderr.exp \
+       shell_valid3 shell_valid3.vgtest shell_valid3.stderr.exp \
+       shell_zerolength shell_zerolength.vgtest shell_zerolength.stderr.exp \
+           shell_zerolength.stderr.exp-dash \
+       sha1_test.stderr.exp sha1_test.vgtest \
+       shortpush.stderr.exp shortpush.vgtest \
+       shorts.stderr.exp shorts.vgtest \
+       sigstackgrowth.stdout.exp sigstackgrowth.stderr.exp sigstackgrowth.vgtest \
+       stackgrowth.stdout.exp stackgrowth.stderr.exp stackgrowth.vgtest \
+       syscall-restart1.vgtest syscall-restart1.stdout.exp syscall-restart1.stderr.exp \
+       syscall-restart2.vgtest syscall-restart2.stdout.exp syscall-restart2.stderr.exp \
+       syslog.vgtest syslog.stderr.exp \
+       system.stderr.exp system.vgtest \
+       thread-exits.stderr.exp thread-exits.stdout.exp thread-exits.vgtest \
+       threaded-fork.stderr.exp threaded-fork.stdout.exp threaded-fork.vgtest \
+       threadederrno.stderr.exp threadederrno.stdout.exp \
+       threadederrno.vgtest \
+       timestamp.stderr.exp timestamp.vgtest \
+       tls.vgtest tls.stderr.exp tls.stdout.exp  \
+       vgprintf.stderr.exp vgprintf.vgtest

 
 
 # Extra stuff for C tests
 
 
 # Extra stuff for C tests


@@ -1667,42 +1710,6 @@ clean-noinst_DSYMS:
 check-local: build-noinst_DSYMS
 
 clean-local: clean-noinst_DSYMS
 check-local: build-noinst_DSYMS
 
 clean-local: clean-noinst_DSYMS

-       require-text-symbol-2.vgtest \
-               require-text-symbol-2.stderr.exp-libcso6 \
-       res_search.stderr.exp res_search.stdout.exp res_search.vgtest \
-       resolv.stderr.exp resolv.stdout.exp resolv.vgtest \
-       rlimit_nofile.stderr.exp rlimit_nofile.stdout.exp rlimit_nofile.vgtest \
-       selfrun.stderr.exp selfrun.stdout.exp selfrun.vgtest \
-       sem.stderr.exp sem.stdout.exp sem.vgtest \
-       semlimit.stderr.exp semlimit.stdout.exp semlimit.vgtest \
-       shell shell.vgtest shell.stderr.exp shell.stderr.exp-dash \
-           shell.stdout.exp \
-       shell_badinterp shell_badinterp.vgtest shell_badinterp.stderr.exp \
-       shell_binaryfile shell_binaryfile.vgtest shell_binaryfile.stderr.exp \
-       shell_dir.vgtest shell_dir.stderr.exp \
-       shell_nonexec.vgtest shell_nonexec.stderr.exp \
-       shell_nosuchfile.vgtest shell_nosuchfile.stderr.exp \
-       shell_valid1 shell_valid1.vgtest shell_valid1.stderr.exp \
-       shell_valid2 shell_valid2.vgtest shell_valid2.stderr.exp \
-       shell_valid3 shell_valid3.vgtest shell_valid3.stderr.exp \
-       shell_zerolength shell_zerolength.vgtest shell_zerolength.stderr.exp \
-           shell_zerolength.stderr.exp-dash \
-       sha1_test.stderr.exp sha1_test.vgtest \
-       shortpush.stderr.exp shortpush.vgtest \
-       shorts.stderr.exp shorts.vgtest \
-       sigstackgrowth.stdout.exp sigstackgrowth.stderr.exp sigstackgrowth.vgtest \
-       stackgrowth.stdout.exp stackgrowth.stderr.exp stackgrowth.vgtest \
-       syscall-restart1.vgtest syscall-restart1.stdout.exp syscall-restart1.stderr.exp \
-       syscall-restart2.vgtest syscall-restart2.stdout.exp syscall-restart2.stderr.exp \
-       syslog.vgtest syslog.stderr.exp \
-       system.stderr.exp system.vgtest \
-       thread-exits.stderr.exp thread-exits.stdout.exp thread-exits.vgtest \
-       threaded-fork.stderr.exp threaded-fork.stdout.exp threaded-fork.vgtest \
-       threadederrno.stderr.exp threadederrno.stdout.exp \
-       threadederrno.vgtest \
-       timestamp.stderr.exp timestamp.vgtest \
-       tls.vgtest tls.stderr.exp tls.stdout.exp  \
-       vgprintf.stderr.exp vgprintf.vgtest

 
 # Tell versions [3.59,3.63) of GNU make to not export all variables.
 # Otherwise a system limit (for SysV at least) may be exceeded.
 
 # Tell versions [3.59,3.63) of GNU make to not export all variables.
 # Otherwise a system limit (for SysV at least) may be exceeded.

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/Makefile.am
index 51ec345ce2c3202b1d99572cd8bbdbf2879cf356..38e1ebbc3547b1312eef8fc69c4de9465ee3f0fa 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/Makefile.am
@@ -16,6 +16,9 @@ endif
 # Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS, 
 # to avoid packaging screwups if 'make dist' is run on a machine
 # which failed the BUILD_SSE3_TESTS test in configure.in.
 # Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS, 
 # to avoid packaging screwups if 'make dist' is run on a machine
 # which failed the BUILD_SSE3_TESTS test in configure.in.

+
+## FIXME: move lzcnt64 to SSE4 conditionalisation, when that happens.
+

 EXTRA_DIST = \
        amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \
        bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \
 EXTRA_DIST = \
        amd64locked.vgtest amd64locked.stdout.exp amd64locked.stderr.exp \
        bug127521-64.vgtest bug127521-64.stdout.exp bug127521-64.stderr.exp \


@@ -37,6 +40,7 @@ EXTRA_DIST = \
        insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
        jrcxz.stderr.exp jrcxz.stdout.exp jrcxz.vgtest \
        looper.stderr.exp looper.stdout.exp looper.vgtest \
        insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
        jrcxz.stderr.exp jrcxz.stdout.exp jrcxz.vgtest \
        looper.stderr.exp looper.stdout.exp looper.vgtest \

+       lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \

        nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
        nibz_bennee_mmap.vgtest \
        rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \
        nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
        nibz_bennee_mmap.vgtest \
        rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \


@@ -48,17 +52,20 @@ EXTRA_DIST = \
        ssse3_misaligned.vgtest \
        ssse3_misaligned.c \
        slahf-amd64.stderr.exp slahf-amd64.stdout.exp \
        ssse3_misaligned.vgtest \
        ssse3_misaligned.c \
        slahf-amd64.stderr.exp slahf-amd64.stdout.exp \

-       slahf-amd64.vgtest
+       slahf-amd64.vgtest \
+       xadd.stderr.exp xadd.stdout.exp xadd.vgtest

 
 check_PROGRAMS = \
        amd64locked \
        bug127521-64 bug132813-amd64 bug132918 \
        clc \
        $(INSN_TESTS) \
 
 check_PROGRAMS = \
        amd64locked \
        bug127521-64 bug132813-amd64 bug132918 \
        clc \
        $(INSN_TESTS) \

+       lzcnt64 \

        rcl-amd64 \
        redundantRexW \
        smc1 \
        rcl-amd64 \
        redundantRexW \
        smc1 \

-       nibz_bennee_mmap
+       nibz_bennee_mmap \
+       xadd

 if BUILD_SSSE3_TESTS
  check_PROGRAMS += ssse3_misaligned
 endif
 if BUILD_SSSE3_TESTS
  check_PROGRAMS += ssse3_misaligned
 endif

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/Makefile.in
index 123a38c9b186b66fea5d3a120f283ad0ab615253..9e9deeb55056fd11ac60a25d3ac335ea52931d3e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/Makefile.in
@@ -50,9 +50,9 @@ DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
 @BUILD_SSSE3_TESTS_TRUE@am__append_2 = insn_ssse3
 check_PROGRAMS = amd64locked$(EXEEXT) bug127521-64$(EXEEXT) \
        bug132813-amd64$(EXEEXT) bug132918$(EXEEXT) clc$(EXEEXT) \
 @BUILD_SSSE3_TESTS_TRUE@am__append_2 = insn_ssse3
 check_PROGRAMS = amd64locked$(EXEEXT) bug127521-64$(EXEEXT) \
        bug132813-amd64$(EXEEXT) bug132918$(EXEEXT) clc$(EXEEXT) \

-       $(am__EXEEXT_3) rcl-amd64$(EXEEXT) redundantRexW$(EXEEXT) \
-       smc1$(EXEEXT) nibz_bennee_mmap$(EXEEXT) $(am__EXEEXT_4) \
-       $(am__EXEEXT_5)
+       $(am__EXEEXT_3) lzcnt64$(EXEEXT) rcl-amd64$(EXEEXT) \
+       redundantRexW$(EXEEXT) smc1$(EXEEXT) nibz_bennee_mmap$(EXEEXT) \
+       xadd$(EXEEXT) $(am__EXEEXT_4) $(am__EXEEXT_5)

 @BUILD_SSSE3_TESTS_TRUE@am__append_3 = ssse3_misaligned
 
 # DDD: these need to be made to work on Darwin like the x86/ ones were.
 @BUILD_SSSE3_TESTS_TRUE@am__append_3 = ssse3_misaligned
 
 # DDD: these need to be made to work on Darwin like the x86/ ones were.


@@ -147,6 +147,9 @@ jrcxz_LDADD = $(LDADD)
 looper_SOURCES = looper.c
 looper_OBJECTS = looper.$(OBJEXT)
 looper_LDADD = $(LDADD)
 looper_SOURCES = looper.c
 looper_OBJECTS = looper.$(OBJEXT)
 looper_LDADD = $(LDADD)

+lzcnt64_SOURCES = lzcnt64.c
+lzcnt64_OBJECTS = lzcnt64.$(OBJEXT)
+lzcnt64_LDADD = $(LDADD)

 nibz_bennee_mmap_SOURCES = nibz_bennee_mmap.c
 nibz_bennee_mmap_OBJECTS = nibz_bennee_mmap.$(OBJEXT)
 nibz_bennee_mmap_LDADD = $(LDADD)
 nibz_bennee_mmap_SOURCES = nibz_bennee_mmap.c
 nibz_bennee_mmap_OBJECTS = nibz_bennee_mmap.$(OBJEXT)
 nibz_bennee_mmap_LDADD = $(LDADD)


@@ -168,6 +171,9 @@ smc1_LDADD = $(LDADD)
 ssse3_misaligned_SOURCES = ssse3_misaligned.c
 ssse3_misaligned_OBJECTS = ssse3_misaligned.$(OBJEXT)
 ssse3_misaligned_LDADD = $(LDADD)
 ssse3_misaligned_SOURCES = ssse3_misaligned.c
 ssse3_misaligned_OBJECTS = ssse3_misaligned.$(OBJEXT)
 ssse3_misaligned_LDADD = $(LDADD)

+xadd_SOURCES = xadd.c
+xadd_OBJECTS = xadd.$(OBJEXT)
+xadd_LDADD = $(LDADD)

 SCRIPTS = $(dist_noinst_SCRIPTS)
 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp
 SCRIPTS = $(dist_noinst_SCRIPTS)
 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
 depcomp = $(SHELL) $(top_srcdir)/depcomp


@@ -182,16 +188,16 @@ SOURCES = amd64locked.c bug127521-64.c bug132813-amd64.c bug132918.c \
        fcmovnu.c fxtract.c $(insn_basic_SOURCES) $(insn_fpu_SOURCES) \
        $(insn_mmx_SOURCES) $(insn_sse_SOURCES) $(insn_sse2_SOURCES) \
        $(insn_sse3_SOURCES) $(insn_ssse3_SOURCES) jrcxz.c looper.c \
        fcmovnu.c fxtract.c $(insn_basic_SOURCES) $(insn_fpu_SOURCES) \
        $(insn_mmx_SOURCES) $(insn_sse_SOURCES) $(insn_sse2_SOURCES) \
        $(insn_sse3_SOURCES) $(insn_ssse3_SOURCES) jrcxz.c looper.c \

-       nibz_bennee_mmap.c rcl-amd64.c redundantRexW.c shrld.c \
-       slahf-amd64.c smc1.c ssse3_misaligned.c
+       lzcnt64.c nibz_bennee_mmap.c rcl-amd64.c redundantRexW.c \
+       shrld.c slahf-amd64.c smc1.c ssse3_misaligned.c xadd.c

 DIST_SOURCES = amd64locked.c bug127521-64.c bug132813-amd64.c \
        bug132918.c bug137714-amd64.c bug156404-amd64.c clc.c \
        faultstatus.c fcmovnu.c fxtract.c $(insn_basic_SOURCES) \
        $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) $(insn_sse_SOURCES) \
        $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
 DIST_SOURCES = amd64locked.c bug127521-64.c bug132813-amd64.c \
        bug132918.c bug137714-amd64.c bug156404-amd64.c clc.c \
        faultstatus.c fcmovnu.c fxtract.c $(insn_basic_SOURCES) \
        $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) $(insn_sse_SOURCES) \
        $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \

-       $(insn_ssse3_SOURCES) jrcxz.c looper.c nibz_bennee_mmap.c \
-       rcl-amd64.c redundantRexW.c shrld.c slahf-amd64.c smc1.c \
-       ssse3_misaligned.c
+       $(insn_ssse3_SOURCES) jrcxz.c looper.c lzcnt64.c \
+       nibz_bennee_mmap.c rcl-amd64.c redundantRexW.c shrld.c \
+       slahf-amd64.c smc1.c ssse3_misaligned.c xadd.c

 ETAGS = etags
 CTAGS = ctags
 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
 ETAGS = etags
 CTAGS = ctags
 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)


@@ -232,6 +238,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -266,14 +273,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -356,7 +367,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -415,7 +428,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -430,8 +443,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -519,6 +532,7 @@ EXTRA_DIST = \
        insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
        jrcxz.stderr.exp jrcxz.stdout.exp jrcxz.vgtest \
        looper.stderr.exp looper.stdout.exp looper.vgtest \
        insn_ssse3.stdout.exp insn_ssse3.stderr.exp insn_ssse3.vgtest \
        jrcxz.stderr.exp jrcxz.stdout.exp jrcxz.vgtest \
        looper.stderr.exp looper.stdout.exp looper.vgtest \

+       lzcnt64.stderr.exp lzcnt64.stdout.exp lzcnt64.vgtest \

        nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
        nibz_bennee_mmap.vgtest \
        rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \
        nibz_bennee_mmap.stderr.exp nibz_bennee_mmap.stdout.exp \
        nibz_bennee_mmap.vgtest \
        rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \


@@ -530,7 +544,8 @@ EXTRA_DIST = \
        ssse3_misaligned.vgtest \
        ssse3_misaligned.c \
        slahf-amd64.stderr.exp slahf-amd64.stdout.exp \
        ssse3_misaligned.vgtest \
        ssse3_misaligned.c \
        slahf-amd64.stderr.exp slahf-amd64.stdout.exp \

-       slahf-amd64.vgtest
+       slahf-amd64.vgtest \
+       xadd.stderr.exp xadd.stdout.exp xadd.vgtest

 
 
 # generic C ones
 
 
 # generic C ones


@@ -645,6 +660,9 @@ jrcxz$(EXEEXT): $(jrcxz_OBJECTS) $(jrcxz_DEPENDENCIES)
 looper$(EXEEXT): $(looper_OBJECTS) $(looper_DEPENDENCIES) 
        @rm -f looper$(EXEEXT)
        $(LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)
 looper$(EXEEXT): $(looper_OBJECTS) $(looper_DEPENDENCIES) 
        @rm -f looper$(EXEEXT)
        $(LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)

+lzcnt64$(EXEEXT): $(lzcnt64_OBJECTS) $(lzcnt64_DEPENDENCIES) 
+       @rm -f lzcnt64$(EXEEXT)
+       $(LINK) $(lzcnt64_OBJECTS) $(lzcnt64_LDADD) $(LIBS)

 nibz_bennee_mmap$(EXEEXT): $(nibz_bennee_mmap_OBJECTS) $(nibz_bennee_mmap_DEPENDENCIES) 
        @rm -f nibz_bennee_mmap$(EXEEXT)
        $(LINK) $(nibz_bennee_mmap_OBJECTS) $(nibz_bennee_mmap_LDADD) $(LIBS)
 nibz_bennee_mmap$(EXEEXT): $(nibz_bennee_mmap_OBJECTS) $(nibz_bennee_mmap_DEPENDENCIES) 
        @rm -f nibz_bennee_mmap$(EXEEXT)
        $(LINK) $(nibz_bennee_mmap_OBJECTS) $(nibz_bennee_mmap_LDADD) $(LIBS)


@@ -666,6 +684,9 @@ smc1$(EXEEXT): $(smc1_OBJECTS) $(smc1_DEPENDENCIES)
 ssse3_misaligned$(EXEEXT): $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_DEPENDENCIES) 
        @rm -f ssse3_misaligned$(EXEEXT)
        $(LINK) $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_LDADD) $(LIBS)
 ssse3_misaligned$(EXEEXT): $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_DEPENDENCIES) 
        @rm -f ssse3_misaligned$(EXEEXT)
        $(LINK) $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_LDADD) $(LIBS)

+xadd$(EXEEXT): $(xadd_OBJECTS) $(xadd_DEPENDENCIES) 
+       @rm -f xadd$(EXEEXT)
+       $(LINK) $(xadd_OBJECTS) $(xadd_LDADD) $(LIBS)

 
 mostlyclean-compile:
        -rm -f *.$(OBJEXT)
 
 mostlyclean-compile:
        -rm -f *.$(OBJEXT)


@@ -692,6 +713,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_ssse3.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jrcxz.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/looper.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/insn_ssse3.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jrcxz.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/looper.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lzcnt64.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nibz_bennee_mmap.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rcl-amd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/redundantRexW.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nibz_bennee_mmap.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/rcl-amd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/redundantRexW.Po@am__quote@


@@ -699,6 +721,7 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/slahf-amd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/smc1.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ssse3_misaligned.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/slahf-amd64.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/smc1.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ssse3_misaligned.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xadd.Po@am__quote@

 
 .c.o:
 @am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
 
 .c.o:
 @am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/bug132918.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/bug132918.stdout.exp
index 9427c84c9594f9da8c0708f4c3a45d41944071cf..f12f46d8046709042917fe04e47dfc45648f9a7e 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/bug132918.stdout.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/bug132918.stdout.exp
@@ -1,6 +1,6 @@
 xx1 -> 0x4200 8.300000
 xx2 -> 0x0000 1.440000
 xx1 -> 0x4200 8.300000
 xx2 -> 0x0000 1.440000

-xx -> 0x0000 nan
+xx -> 0x0000 -nan

 xx -> 0x0000 0.809017
 xx -> 0x0000 0.309018
 xx -> 0x0000 -0.309015
 xx -> 0x0000 0.809017
 xx -> 0x0000 0.309018
 xx -> 0x0000 -0.309015

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/fxtract.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/fxtract.stdout.exp
index 4508fd6b69fd2eaaa3b7204620389f8f6deaed66..b82f306b04779dc4b503a5008288d6fd97bf38e6 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/fxtract.stdout.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/fxtract.stdout.exp
@@ -40,7 +40,7 @@
  2.7049662808e+02  ->   1.0566274534   8.0000000000
  0.0000000000e+00  ->   0.0000000000           -inf
               inf  ->            inf            inf
  2.7049662808e+02  ->   1.0566274534   8.0000000000
  0.0000000000e+00  ->   0.0000000000           -inf
               inf  ->            inf            inf

-              nan  ->            nan            nan
+             -nan  ->           -nan           -nan

 7.2124891681e-308  ->   1.6207302828 -1021.0000000000
 5.7982756057e-308  ->   1.3029400313 -1021.0000000000
 4.3840620434e-308  ->   1.9702995595 -1022.0000000000
 7.2124891681e-308  ->   1.6207302828 -1021.0000000000
 5.7982756057e-308  ->   1.3029400313 -1021.0000000000
 4.3840620434e-308  ->   1.9702995595 -1022.0000000000

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/insn_fpu.def b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/insn_fpu.def
index 2393d9ac9a1a6694643581946c734bc14bb5eade..c99815eee768018c7bdd8851c029b7a8272cd0ad 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/insn_fpu.def
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/insn_fpu.def
@@ -210,14 +210,14 @@ fildq m64.sq[123456787654321] => st0.ps[123456787654321.0]
 fildq m64.sq[-123456787654321] => st0.ps[-123456787654321.0]
 fildq m64.sq[123456787654321] => st0.pd[123456787654321.0]
 fildq m64.sq[-123456787654321] => st0.pd[-123456787654321.0]
 fildq m64.sq[-123456787654321] => st0.ps[-123456787654321.0]
 fildq m64.sq[123456787654321] => st0.pd[123456787654321.0]
 fildq m64.sq[-123456787654321] => st0.pd[-123456787654321.0]

-#fists fpucw[0xc00,0x000] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1235] st0.ps[1234.5678]
-#fists fpucw[0xc00,0x000] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1235] st0.ps[-1234.5678]
-#fists fpucw[0xc00,0x400] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1234] st0.ps[1234.5678]
-#fists fpucw[0xc00,0x400] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1235] st0.ps[-1234.5678]
-#fists fpucw[0xc00,0x800] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1235] st0.ps[1234.5678]
-#fists fpucw[0xc00,0x800] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1234] st0.ps[-1234.5678]
-#fists fpucw[0xc00,0xc00] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1234] st0.ps[1234.5678]
-#fists fpucw[0xc00,0xc00] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1234] st0.ps[-1234.5678]
+fists fpucw[0xc00,0x000] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1235] st0.ps[1234.5678]
+fists fpucw[0xc00,0x000] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1235] st0.ps[-1234.5678]
+fists fpucw[0xc00,0x400] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1234] st0.ps[1234.5678]
+fists fpucw[0xc00,0x400] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1235] st0.ps[-1234.5678]
+fists fpucw[0xc00,0x800] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1235] st0.ps[1234.5678]
+fists fpucw[0xc00,0x800] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1234] st0.ps[-1234.5678]
+fists fpucw[0xc00,0xc00] st0.ps[1234.5678] : m16.sw[0] => 0.sw[1234] st0.ps[1234.5678]
+fists fpucw[0xc00,0xc00] st0.ps[-1234.5678] : m16.sw[0] => 0.sw[-1234] st0.ps[-1234.5678]

 fistl fpucw[0xc00,0x000] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234568] st0.pd[1234567.7654321]
 fistl fpucw[0xc00,0x000] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234568] st0.pd[-1234567.7654321]
 fistl fpucw[0xc00,0x400] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234567] st0.pd[1234567.7654321]
 fistl fpucw[0xc00,0x000] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234568] st0.pd[1234567.7654321]
 fistl fpucw[0xc00,0x000] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234568] st0.pd[-1234567.7654321]
 fistl fpucw[0xc00,0x400] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234567] st0.pd[1234567.7654321]


@@ -226,14 +226,14 @@ fistl fpucw[0xc00,0x800] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234568] st
 fistl fpucw[0xc00,0x800] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234567] st0.pd[-1234567.7654321]
 fistl fpucw[0xc00,0xc00] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234567] st0.pd[1234567.7654321]
 fistl fpucw[0xc00,0xc00] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234567] st0.pd[-1234567.7654321]
 fistl fpucw[0xc00,0x800] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234567] st0.pd[-1234567.7654321]
 fistl fpucw[0xc00,0xc00] st0.pd[1234567.7654321] : m32.sd[0] => 0.sd[1234567] st0.pd[1234567.7654321]
 fistl fpucw[0xc00,0xc00] st0.pd[-1234567.7654321] : m32.sd[0] => 0.sd[-1234567] st0.pd[-1234567.7654321]

-#fistps fpucw[0xc00,0x000] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1235] st0.ps[1111.1111]
-#fistps fpucw[0xc00,0x000] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1235] st0.ps[1111.1111]
-#fistps fpucw[0xc00,0x400] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1234] st0.ps[1111.1111]
-#fistps fpucw[0xc00,0x400] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1235] st0.ps[1111.1111]
-#fistps fpucw[0xc00,0x800] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1235] st0.ps[1111.1111]
-#fistps fpucw[0xc00,0x800] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1234] st0.ps[1111.1111]
-#fistps fpucw[0xc00,0xc00] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1234] st0.ps[1111.1111]
-#fistps fpucw[0xc00,0xc00] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1234] st0.ps[1111.1111]
+fistps fpucw[0xc00,0x000] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1235] st0.ps[1111.1111]
+fistps fpucw[0xc00,0x000] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1235] st0.ps[1111.1111]
+fistps fpucw[0xc00,0x400] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1234] st0.ps[1111.1111]
+fistps fpucw[0xc00,0x400] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1235] st0.ps[1111.1111]
+fistps fpucw[0xc00,0x800] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1235] st0.ps[1111.1111]
+fistps fpucw[0xc00,0x800] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1234] st0.ps[1111.1111]
+fistps fpucw[0xc00,0xc00] st0.ps[1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[1234] st0.ps[1111.1111]
+fistps fpucw[0xc00,0xc00] st0.ps[-1234.5678] st1.ps[1111.1111] : m16.sw[0] => 0.sw[-1234] st0.ps[1111.1111]

 fistpl fpucw[0xc00,0x000] st0.pd[1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[1234568] st0.ps[1111.1111]
 fistpl fpucw[0xc00,0x000] st0.pd[-1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[-1234568] st0.ps[1111.1111]
 fistpl fpucw[0xc00,0x400] st0.pd[1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[1234567] st0.ps[1111.1111]
 fistpl fpucw[0xc00,0x000] st0.pd[1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[1234568] st0.ps[1111.1111]
 fistpl fpucw[0xc00,0x000] st0.pd[-1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[-1234568] st0.ps[1111.1111]
 fistpl fpucw[0xc00,0x400] st0.pd[1234567.7654321] st1.ps[1111.1111] : m32.sd[0] => 0.sd[1234567] st0.ps[1111.1111]

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/insn_fpu.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/insn_fpu.stdout.exp
index c790618b6710b6c5fe36fd445bb0fb7e697a51b4..2dbaa07ce06cdc477aa1c5457ddbf1ce78fc1edb 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/insn_fpu.stdout.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/insn_fpu.stdout.exp
@@ -210,6 +210,14 @@ fildq_1 ... ok
 fildq_2 ... ok
 fildq_3 ... ok
 fildq_4 ... ok
 fildq_2 ... ok
 fildq_3 ... ok
 fildq_4 ... ok

+fists_1 ... ok
+fists_2 ... ok
+fists_3 ... ok
+fists_4 ... ok
+fists_5 ... ok
+fists_6 ... ok
+fists_7 ... ok
+fists_8 ... ok

 fistl_1 ... ok
 fistl_2 ... ok
 fistl_3 ... ok
 fistl_1 ... ok
 fistl_2 ... ok
 fistl_3 ... ok


@@ -218,6 +226,14 @@ fistl_5 ... ok
 fistl_6 ... ok
 fistl_7 ... ok
 fistl_8 ... ok
 fistl_6 ... ok
 fistl_7 ... ok
 fistl_8 ... ok

+fistps_1 ... ok
+fistps_2 ... ok
+fistps_3 ... ok
+fistps_4 ... ok
+fistps_5 ... ok
+fistps_6 ... ok
+fistps_7 ... ok
+fistps_8 ... ok

 fistpl_1 ... ok
 fistpl_2 ... ok
 fistpl_3 ... ok
 fistpl_1 ... ok
 fistpl_2 ... ok
 fistpl_3 ... ok

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.c
new file mode 100644 (file)
index 0000000..22fa353
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.c
@@ -0,0 +1,93 @@
+
+#include <stdio.h>
+
+typedef  unsigned long long int  ULong;
+typedef  unsigned int            UInt;
+
+__attribute__((noinline))
+void do_lzcnt64 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+  ULong block[3] = { arg, 0ULL, 0ULL };
+  __asm__ __volatile__(
+    "movabsq $0x5555555555555555, %%r11" "\n\t"
+    "lzcntq 0(%0), %%r11"     "\n\t"
+    "movq %%r11, 8(%0)"       "\n\t"
+    "pushfq"                  "\n\t"
+    "popq %%r11"              "\n\t"
+    "movq %%r11, 16(%0)"      "\n"
+    : : "r"(&block[0]) : "r11","cc","memory"
+  );
+  *res = block[1];
+  *flags = block[2] & 0x8d5;
+}
+
+__attribute__((noinline))
+void do_lzcnt32 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+  ULong block[3] = { arg, 0ULL, 0ULL };
+  __asm__ __volatile__(
+    "movabsq $0x5555555555555555, %%r11" "\n\t"
+    "lzcntl 0(%0), %%r11d"    "\n\t"
+    "movq %%r11, 8(%0)"       "\n\t"
+    "pushfq"                  "\n\t"
+    "popq %%r11"              "\n\t"
+    "movq %%r11, 16(%0)"      "\n"
+    : : "r"(&block[0]) : "r11","cc","memory"
+  );
+  *res = block[1];
+  *flags = block[2] & 0x8d5;
+}
+
+__attribute__((noinline))
+void do_lzcnt16 ( /*OUT*/UInt* flags, /*OUT*/ULong* res, ULong arg )
+{
+  ULong block[3] = { arg, 0ULL, 0ULL };
+  __asm__ __volatile__(
+    "movabsq $0x5555555555555555, %%r11" "\n\t"
+    "lzcntw 0(%0), %%r11w"    "\n\t"
+    "movq %%r11, 8(%0)"       "\n\t"
+    "pushfq"                  "\n\t"
+    "popq %%r11"              "\n\t"
+    "movq %%r11, 16(%0)"      "\n"
+    : : "r"(&block[0]) : "r11","cc","memory"
+  );
+  *res = block[1];
+  *flags = block[2] & 0x8d5;
+}
+
+int main ( void )
+{
+   ULong w;
+
+   w = 0xFEDC192837475675ULL;
+   while (1) {
+      ULong res;
+      UInt  flags;
+      do_lzcnt64(&flags, &res, w);
+      printf("lzcntq %016llx -> %016llx %04x\n", w, res, flags);
+      if (w == 0) break;
+      w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+   }
+
+   w = 0xFEDC192837475675ULL;
+   while (1) {
+      ULong res;
+      UInt  flags;
+      do_lzcnt32(&flags, &res, w);
+      printf("lzcntl %016llx -> %016llx %04x\n", w, res, flags);
+      if (w == 0) break;
+      w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+   }
+
+   w = 0xFEDC192837475675ULL;
+   while (1) {
+      ULong res;
+      UInt  flags;
+      do_lzcnt16(&flags, &res, w);
+      printf("lzcntw %016llx -> %016llx %04x\n", w, res, flags);
+      if (w == 0) break;
+      w = ((w >> 2) | (w >> 1)) + (w / 17ULL);
+   }
+
+   return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.stdout.exp
new file mode 100644 (file)
index 0000000..fd73687
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.stdout.exp
@@ -0,0 +1,375 @@
+lzcntq fedc192837475675 -> 0000000000000000 0040
+lzcntq 8efcf23ad7e922f3 -> 0000000000000000 0040
+lzcntq 7068b90cdf850938 -> 0000000000000001 0000
+lzcntq 42db3e5ed85503a5 -> 0000000000000001 0000
+lzcntq 35eea72efbea67d7 -> 0000000000000002 0000
+lzcntq 232c23d3b476ef47 -> 0000000000000002 0000
+lzcntq 1bf0c1bf27fbb3ab -> 0000000000000003 0000
+lzcntq 11a1311a29a562ea -> 0000000000000003 0000
+lzcntq 0e02582b8350ffd0 -> 0000000000000004 0000
+lzcntq 0854b4408f5b9e17 -> 0000000000000004 0000
+lzcntq 06bcf33434328063 -> 0000000000000005 0000
+lzcntq 0464f596e5f3ab8a -> 0000000000000005 0000
+lzcntq 037dac8063df281c -> 0000000000000006 0000
+lzcntq 0234910d6d0cfe89 -> 0000000000000006 0000
+lzcntq 01c0a27d7eaa2575 -> 0000000000000007 0000
+lzcntq 010adda943af43d8 -> 0000000000000007 0000
+lzcntq 00d7b2ae8c91c8ce -> 0000000000000008 0000
+lzcntq 008cae284a0c2065 -> 0000000000000008 0000
+lzcntq 006fc6190eb4fc04 -> 0000000000000009 0000
+lzcntq 004686bd6e829ce5 -> 0000000000000009 0000
+lzcntq 00380a0b248034f1 -> 000000000000000a 0000
+lzcntq 0021536a650d4fc6 -> 000000000000000a 0000
+lzcntq 001af3d8d0c8c068 -> 000000000000000b 0000
+lzcntq 001193de10460316 -> 000000000000000b 0000
+lzcntq 000df6b241dd45c1 -> 000000000000000c 0000
+lzcntq 0008d24469947f91 -> 000000000000000c 0000
+lzcntq 0007028a17f7fc21 -> 000000000000000d 0000
+lzcntq 00042b77370e9574 -> 000000000000000d 0000
+lzcntq 00035ecaa6c8cb9c -> 000000000000000e 0000
+lzcntq 000232b89c5ca207 -> 000000000000000e 0000
+lzcntq 0001bf185a53fb83 -> 000000000000000f 0000
+lzcntq 00011a1af9c2f08e -> 000000000000000f 0000
+lzcntq 0000e0282bc137ba -> 0000000000000010 0000
+lzcntq 0000854daa0b4caf -> 0000000000000010 0000
+lzcntq 00006bcf63e2fc01 -> 0000000000000011 0000
+lzcntq 0000464f7852a469 -> 0000000000000011 0000
+lzcntq 000037dac915aa8f -> 0000000000000012 0000
+lzcntq 0000234911b3280d -> 0000000000000012 0000
+lzcntq 00001c0a2862c244 -> 0000000000000013 0000
+lzcntq 000010addcd6577a -> 0000000000000013 0000
+lzcntq 00000d7b2a9b6ac9 -> 0000000000000014 0000
+lzcntq 000008cae2719cd4 -> 0000000000000014 0000
+lzcntq 000006fc61694403 -> 0000000000000015 0000
+lzcntq 000004686be70610 -> 0000000000000015 0000
+lzcntq 00000380a0af0023 -> 0000000000000016 0000
+lzcntq 0000021536a82984 -> 0000000000000016 0000
+lzcntq 000001af3d8f8abd -> 0000000000000017 0000
+lzcntq 000001193de14a82 -> 0000000000000017 0000
+lzcntq 000000df6b24569d -> 0000000000000018 0000
+lzcntq 0000008d2446cc8e -> 0000000000000018 0000
+lzcntq 0000007028a18af6 -> 0000000000000019 0000
+lzcntq 00000042b7735995 -> 0000000000000019 0000
+lzcntq 00000035ecaa6d9d -> 000000000000001a 0000
+lzcntq 000000232b89c661 -> 000000000000001a 0000
+lzcntq 0000001bf185a509 -> 000000000000001b 0000
+lzcntq 00000011a1af9c11 -> 000000000000001b 0000
+lzcntq 0000000e0282bbfd -> 000000000000001c 0000
+lzcntq 0000000854daa1a4 -> 000000000000001c 0000
+lzcntq 00000006bcf63eb9 -> 000000000000001d 0000
+lzcntq 0000000464f78590 -> 000000000000001d 0000
+lzcntq 000000037dac916c -> 000000000000001e 0000
+lzcntq 0000000234911b32 -> 000000000000001e 0000
+lzcntq 00000001c0a2862b -> 000000000000001f 0000
+lzcntq 000000010addcd65 -> 000000000000001f 0000
+lzcntq 00000000d7b2a9b5 -> 0000000000000020 0000
+lzcntq 000000008cae2718 -> 0000000000000020 0000
+lzcntq 000000006fc61693 -> 0000000000000021 0000
+lzcntq 000000004686be6e -> 0000000000000021 0000
+lzcntq 00000000380a0af2 -> 0000000000000022 0000
+lzcntq 0000000021536a83 -> 0000000000000022 0000
+lzcntq 000000001af3d8f7 -> 0000000000000023 0000
+lzcntq 000000001193de15 -> 0000000000000023 0000
+lzcntq 000000000df6b244 -> 0000000000000024 0000
+lzcntq 0000000008d2446b -> 0000000000000024 0000
+lzcntq 0000000007028a18 -> 0000000000000025 0000
+lzcntq 00000000042b7735 -> 0000000000000025 0000
+lzcntq 00000000035ecaa5 -> 0000000000000026 0000
+lzcntq 000000000232b89b -> 0000000000000026 0000
+lzcntq 0000000001bf185a -> 0000000000000027 0000
+lzcntq 00000000011a1af9 -> 0000000000000027 0000
+lzcntq 0000000000e0282a -> 0000000000000028 0000
+lzcntq 0000000000854da9 -> 0000000000000028 0000
+lzcntq 00000000006bcf62 -> 0000000000000029 0000
+lzcntq 0000000000464f77 -> 0000000000000029 0000
+lzcntq 000000000037dac9 -> 000000000000002a 0000
+lzcntq 0000000000234910 -> 000000000000002a 0000
+lzcntq 00000000001c0a27 -> 000000000000002b 0000
+lzcntq 000000000010add9 -> 000000000000002b 0000
+lzcntq 00000000000d7b28 -> 000000000000002c 0000
+lzcntq 000000000008cae0 -> 000000000000002c 0000
+lzcntq 000000000006fc5f -> 000000000000002d 0000
+lzcntq 0000000000046871 -> 000000000000002d 0000
+lzcntq 000000000003809d -> 000000000000002e 0000
+lzcntq 000000000002152c -> 000000000000002e 0000
+lzcntq 000000000001af3b -> 000000000000002f 0000
+lzcntq 000000000001193c -> 000000000000002f 0000
+lzcntq 000000000000df6a -> 0000000000000030 0000
+lzcntq 0000000000008d23 -> 0000000000000030 0000
+lzcntq 0000000000007026 -> 0000000000000031 0000
+lzcntq 00000000000042b3 -> 0000000000000031 0000
+lzcntq 00000000000035e9 -> 0000000000000032 0000
+lzcntq 0000000000002329 -> 0000000000000032 0000
+lzcntq 0000000000001bef -> 0000000000000033 0000
+lzcntq 00000000000011a3 -> 0000000000000033 0000
+lzcntq 0000000000000e02 -> 0000000000000034 0000
+lzcntq 0000000000000853 -> 0000000000000034 0000
+lzcntq 00000000000006ba -> 0000000000000035 0000
+lzcntq 0000000000000464 -> 0000000000000035 0000
+lzcntq 000000000000037d -> 0000000000000036 0000
+lzcntq 0000000000000233 -> 0000000000000036 0000
+lzcntq 00000000000001be -> 0000000000000037 0000
+lzcntq 0000000000000119 -> 0000000000000037 0000
+lzcntq 00000000000000de -> 0000000000000038 0000
+lzcntq 000000000000008c -> 0000000000000038 0000
+lzcntq 000000000000006f -> 0000000000000039 0000
+lzcntq 0000000000000045 -> 0000000000000039 0000
+lzcntq 0000000000000037 -> 000000000000003a 0000
+lzcntq 0000000000000022 -> 000000000000003a 0000
+lzcntq 000000000000001b -> 000000000000003b 0000
+lzcntq 0000000000000010 -> 000000000000003b 0000
+lzcntq 000000000000000c -> 000000000000003c 0000
+lzcntq 0000000000000007 -> 000000000000003d 0000
+lzcntq 0000000000000003 -> 000000000000003e 0000
+lzcntq 0000000000000001 -> 000000000000003f 0000
+lzcntq 0000000000000000 -> 0000000000000040 0001
+lzcntl fedc192837475675 -> 0000000000000002 0000
+lzcntl 8efcf23ad7e922f3 -> 0000000000000000 0040
+lzcntl 7068b90cdf850938 -> 0000000000000000 0040
+lzcntl 42db3e5ed85503a5 -> 0000000000000000 0040
+lzcntl 35eea72efbea67d7 -> 0000000000000000 0040
+lzcntl 232c23d3b476ef47 -> 0000000000000000 0040
+lzcntl 1bf0c1bf27fbb3ab -> 0000000000000002 0000
+lzcntl 11a1311a29a562ea -> 0000000000000002 0000
+lzcntl 0e02582b8350ffd0 -> 0000000000000000 0040
+lzcntl 0854b4408f5b9e17 -> 0000000000000000 0040
+lzcntl 06bcf33434328063 -> 0000000000000002 0000
+lzcntl 0464f596e5f3ab8a -> 0000000000000000 0040
+lzcntl 037dac8063df281c -> 0000000000000001 0000
+lzcntl 0234910d6d0cfe89 -> 0000000000000001 0000
+lzcntl 01c0a27d7eaa2575 -> 0000000000000001 0000
+lzcntl 010adda943af43d8 -> 0000000000000001 0000
+lzcntl 00d7b2ae8c91c8ce -> 0000000000000000 0040
+lzcntl 008cae284a0c2065 -> 0000000000000001 0000
+lzcntl 006fc6190eb4fc04 -> 0000000000000004 0000
+lzcntl 004686bd6e829ce5 -> 0000000000000001 0000
+lzcntl 00380a0b248034f1 -> 0000000000000002 0000
+lzcntl 0021536a650d4fc6 -> 0000000000000001 0000
+lzcntl 001af3d8d0c8c068 -> 0000000000000000 0040
+lzcntl 001193de10460316 -> 0000000000000003 0000
+lzcntl 000df6b241dd45c1 -> 0000000000000001 0000
+lzcntl 0008d24469947f91 -> 0000000000000001 0000
+lzcntl 0007028a17f7fc21 -> 0000000000000003 0000
+lzcntl 00042b77370e9574 -> 0000000000000002 0000
+lzcntl 00035ecaa6c8cb9c -> 0000000000000000 0040
+lzcntl 000232b89c5ca207 -> 0000000000000000 0040
+lzcntl 0001bf185a53fb83 -> 0000000000000001 0000
+lzcntl 00011a1af9c2f08e -> 0000000000000000 0040
+lzcntl 0000e0282bc137ba -> 0000000000000002 0000
+lzcntl 0000854daa0b4caf -> 0000000000000000 0040
+lzcntl 00006bcf63e2fc01 -> 0000000000000001 0000
+lzcntl 0000464f7852a469 -> 0000000000000001 0000
+lzcntl 000037dac915aa8f -> 0000000000000000 0040
+lzcntl 0000234911b3280d -> 0000000000000003 0000
+lzcntl 00001c0a2862c244 -> 0000000000000002 0000
+lzcntl 000010addcd6577a -> 0000000000000000 0040
+lzcntl 00000d7b2a9b6ac9 -> 0000000000000002 0000
+lzcntl 000008cae2719cd4 -> 0000000000000000 0040
+lzcntl 000006fc61694403 -> 0000000000000001 0000
+lzcntl 000004686be70610 -> 0000000000000001 0000
+lzcntl 00000380a0af0023 -> 0000000000000000 0040
+lzcntl 0000021536a82984 -> 0000000000000002 0000
+lzcntl 000001af3d8f8abd -> 0000000000000002 0000
+lzcntl 000001193de14a82 -> 0000000000000002 0000
+lzcntl 000000df6b24569d -> 0000000000000001 0000
+lzcntl 0000008d2446cc8e -> 0000000000000002 0000
+lzcntl 0000007028a18af6 -> 0000000000000002 0000
+lzcntl 00000042b7735995 -> 0000000000000000 0040
+lzcntl 00000035ecaa6d9d -> 0000000000000000 0040
+lzcntl 000000232b89c661 -> 0000000000000002 0000
+lzcntl 0000001bf185a509 -> 0000000000000000 0040
+lzcntl 00000011a1af9c11 -> 0000000000000000 0040
+lzcntl 0000000e0282bbfd -> 0000000000000006 0000
+lzcntl 0000000854daa1a4 -> 0000000000000001 0000
+lzcntl 00000006bcf63eb9 -> 0000000000000000 0040
+lzcntl 0000000464f78590 -> 0000000000000001 0000
+lzcntl 000000037dac916c -> 0000000000000001 0000
+lzcntl 0000000234911b32 -> 0000000000000002 0000
+lzcntl 00000001c0a2862b -> 0000000000000000 0040
+lzcntl 000000010addcd65 -> 0000000000000004 0000
+lzcntl 00000000d7b2a9b5 -> 0000000000000000 0040
+lzcntl 000000008cae2718 -> 0000000000000000 0040
+lzcntl 000000006fc61693 -> 0000000000000001 0000
+lzcntl 000000004686be6e -> 0000000000000001 0000
+lzcntl 00000000380a0af2 -> 0000000000000002 0000
+lzcntl 0000000021536a83 -> 0000000000000002 0000
+lzcntl 000000001af3d8f7 -> 0000000000000003 0000
+lzcntl 000000001193de15 -> 0000000000000003 0000
+lzcntl 000000000df6b244 -> 0000000000000004 0000
+lzcntl 0000000008d2446b -> 0000000000000004 0000
+lzcntl 0000000007028a18 -> 0000000000000005 0000
+lzcntl 00000000042b7735 -> 0000000000000005 0000
+lzcntl 00000000035ecaa5 -> 0000000000000006 0000
+lzcntl 000000000232b89b -> 0000000000000006 0000
+lzcntl 0000000001bf185a -> 0000000000000007 0000
+lzcntl 00000000011a1af9 -> 0000000000000007 0000
+lzcntl 0000000000e0282a -> 0000000000000008 0000
+lzcntl 0000000000854da9 -> 0000000000000008 0000
+lzcntl 00000000006bcf62 -> 0000000000000009 0000
+lzcntl 0000000000464f77 -> 0000000000000009 0000
+lzcntl 000000000037dac9 -> 000000000000000a 0000
+lzcntl 0000000000234910 -> 000000000000000a 0000
+lzcntl 00000000001c0a27 -> 000000000000000b 0000
+lzcntl 000000000010add9 -> 000000000000000b 0000
+lzcntl 00000000000d7b28 -> 000000000000000c 0000
+lzcntl 000000000008cae0 -> 000000000000000c 0000
+lzcntl 000000000006fc5f -> 000000000000000d 0000
+lzcntl 0000000000046871 -> 000000000000000d 0000
+lzcntl 000000000003809d -> 000000000000000e 0000
+lzcntl 000000000002152c -> 000000000000000e 0000
+lzcntl 000000000001af3b -> 000000000000000f 0000
+lzcntl 000000000001193c -> 000000000000000f 0000
+lzcntl 000000000000df6a -> 0000000000000010 0000
+lzcntl 0000000000008d23 -> 0000000000000010 0000
+lzcntl 0000000000007026 -> 0000000000000011 0000
+lzcntl 00000000000042b3 -> 0000000000000011 0000
+lzcntl 00000000000035e9 -> 0000000000000012 0000
+lzcntl 0000000000002329 -> 0000000000000012 0000
+lzcntl 0000000000001bef -> 0000000000000013 0000
+lzcntl 00000000000011a3 -> 0000000000000013 0000
+lzcntl 0000000000000e02 -> 0000000000000014 0000
+lzcntl 0000000000000853 -> 0000000000000014 0000
+lzcntl 00000000000006ba -> 0000000000000015 0000
+lzcntl 0000000000000464 -> 0000000000000015 0000
+lzcntl 000000000000037d -> 0000000000000016 0000
+lzcntl 0000000000000233 -> 0000000000000016 0000
+lzcntl 00000000000001be -> 0000000000000017 0000
+lzcntl 0000000000000119 -> 0000000000000017 0000
+lzcntl 00000000000000de -> 0000000000000018 0000
+lzcntl 000000000000008c -> 0000000000000018 0000
+lzcntl 000000000000006f -> 0000000000000019 0000
+lzcntl 0000000000000045 -> 0000000000000019 0000
+lzcntl 0000000000000037 -> 000000000000001a 0000
+lzcntl 0000000000000022 -> 000000000000001a 0000
+lzcntl 000000000000001b -> 000000000000001b 0000
+lzcntl 0000000000000010 -> 000000000000001b 0000
+lzcntl 000000000000000c -> 000000000000001c 0000
+lzcntl 0000000000000007 -> 000000000000001d 0000
+lzcntl 0000000000000003 -> 000000000000001e 0000
+lzcntl 0000000000000001 -> 000000000000001f 0000
+lzcntl 0000000000000000 -> 0000000000000020 0001
+lzcntw fedc192837475675 -> 5555555555550001 0000
+lzcntw 8efcf23ad7e922f3 -> 5555555555550002 0000
+lzcntw 7068b90cdf850938 -> 5555555555550004 0000
+lzcntw 42db3e5ed85503a5 -> 5555555555550006 0000
+lzcntw 35eea72efbea67d7 -> 5555555555550001 0000
+lzcntw 232c23d3b476ef47 -> 5555555555550000 0040
+lzcntw 1bf0c1bf27fbb3ab -> 5555555555550000 0040
+lzcntw 11a1311a29a562ea -> 5555555555550001 0000
+lzcntw 0e02582b8350ffd0 -> 5555555555550000 0040
+lzcntw 0854b4408f5b9e17 -> 5555555555550000 0040
+lzcntw 06bcf33434328063 -> 5555555555550000 0040
+lzcntw 0464f596e5f3ab8a -> 5555555555550000 0040
+lzcntw 037dac8063df281c -> 5555555555550002 0000
+lzcntw 0234910d6d0cfe89 -> 5555555555550000 0040
+lzcntw 01c0a27d7eaa2575 -> 5555555555550002 0000
+lzcntw 010adda943af43d8 -> 5555555555550001 0000
+lzcntw 00d7b2ae8c91c8ce -> 5555555555550000 0040
+lzcntw 008cae284a0c2065 -> 5555555555550002 0000
+lzcntw 006fc6190eb4fc04 -> 5555555555550000 0040
+lzcntw 004686bd6e829ce5 -> 5555555555550000 0040
+lzcntw 00380a0b248034f1 -> 5555555555550002 0000
+lzcntw 0021536a650d4fc6 -> 5555555555550001 0000
+lzcntw 001af3d8d0c8c068 -> 5555555555550000 0040
+lzcntw 001193de10460316 -> 5555555555550006 0000
+lzcntw 000df6b241dd45c1 -> 5555555555550001 0000
+lzcntw 0008d24469947f91 -> 5555555555550001 0000
+lzcntw 0007028a17f7fc21 -> 5555555555550000 0040
+lzcntw 00042b77370e9574 -> 5555555555550000 0040
+lzcntw 00035ecaa6c8cb9c -> 5555555555550000 0040
+lzcntw 000232b89c5ca207 -> 5555555555550000 0040
+lzcntw 0001bf185a53fb83 -> 5555555555550000 0040
+lzcntw 00011a1af9c2f08e -> 5555555555550000 0040
+lzcntw 0000e0282bc137ba -> 5555555555550002 0000
+lzcntw 0000854daa0b4caf -> 5555555555550001 0000
+lzcntw 00006bcf63e2fc01 -> 5555555555550000 0040
+lzcntw 0000464f7852a469 -> 5555555555550000 0040
+lzcntw 000037dac915aa8f -> 5555555555550000 0040
+lzcntw 0000234911b3280d -> 5555555555550002 0000
+lzcntw 00001c0a2862c244 -> 5555555555550000 0040
+lzcntw 000010addcd6577a -> 5555555555550001 0000
+lzcntw 00000d7b2a9b6ac9 -> 5555555555550001 0000
+lzcntw 000008cae2719cd4 -> 5555555555550000 0040
+lzcntw 000006fc61694403 -> 5555555555550001 0000
+lzcntw 000004686be70610 -> 5555555555550005 0000
+lzcntw 00000380a0af0023 -> 555555555555000a 0000
+lzcntw 0000021536a82984 -> 5555555555550002 0000
+lzcntw 000001af3d8f8abd -> 5555555555550000 0040
+lzcntw 000001193de14a82 -> 5555555555550001 0000
+lzcntw 000000df6b24569d -> 5555555555550001 0000
+lzcntw 0000008d2446cc8e -> 5555555555550000 0040
+lzcntw 0000007028a18af6 -> 5555555555550000 0040
+lzcntw 00000042b7735995 -> 5555555555550001 0000
+lzcntw 00000035ecaa6d9d -> 5555555555550001 0000
+lzcntw 000000232b89c661 -> 5555555555550000 0040
+lzcntw 0000001bf185a509 -> 5555555555550000 0040
+lzcntw 00000011a1af9c11 -> 5555555555550000 0040
+lzcntw 0000000e0282bbfd -> 5555555555550000 0040
+lzcntw 0000000854daa1a4 -> 5555555555550000 0040
+lzcntw 00000006bcf63eb9 -> 5555555555550002 0000
+lzcntw 0000000464f78590 -> 5555555555550000 0040
+lzcntw 000000037dac916c -> 5555555555550000 0040
+lzcntw 0000000234911b32 -> 5555555555550003 0000
+lzcntw 00000001c0a2862b -> 5555555555550000 0040
+lzcntw 000000010addcd65 -> 5555555555550000 0040
+lzcntw 00000000d7b2a9b5 -> 5555555555550000 0040
+lzcntw 000000008cae2718 -> 5555555555550002 0000
+lzcntw 000000006fc61693 -> 5555555555550003 0000
+lzcntw 000000004686be6e -> 5555555555550000 0040
+lzcntw 00000000380a0af2 -> 5555555555550004 0000
+lzcntw 0000000021536a83 -> 5555555555550001 0000
+lzcntw 000000001af3d8f7 -> 5555555555550000 0040
+lzcntw 000000001193de15 -> 5555555555550000 0040
+lzcntw 000000000df6b244 -> 5555555555550000 0040
+lzcntw 0000000008d2446b -> 5555555555550001 0000
+lzcntw 0000000007028a18 -> 5555555555550000 0040
+lzcntw 00000000042b7735 -> 5555555555550001 0000
+lzcntw 00000000035ecaa5 -> 5555555555550000 0040
+lzcntw 000000000232b89b -> 5555555555550000 0040
+lzcntw 0000000001bf185a -> 5555555555550003 0000
+lzcntw 00000000011a1af9 -> 5555555555550003 0000
+lzcntw 0000000000e0282a -> 5555555555550002 0000
+lzcntw 0000000000854da9 -> 5555555555550001 0000
+lzcntw 00000000006bcf62 -> 5555555555550000 0040
+lzcntw 0000000000464f77 -> 5555555555550001 0000
+lzcntw 000000000037dac9 -> 5555555555550000 0040
+lzcntw 0000000000234910 -> 5555555555550001 0000
+lzcntw 00000000001c0a27 -> 5555555555550004 0000
+lzcntw 000000000010add9 -> 5555555555550000 0040
+lzcntw 00000000000d7b28 -> 5555555555550001 0000
+lzcntw 000000000008cae0 -> 5555555555550000 0040
+lzcntw 000000000006fc5f -> 5555555555550000 0040
+lzcntw 0000000000046871 -> 5555555555550001 0000
+lzcntw 000000000003809d -> 5555555555550000 0040
+lzcntw 000000000002152c -> 5555555555550003 0000
+lzcntw 000000000001af3b -> 5555555555550000 0040
+lzcntw 000000000001193c -> 5555555555550003 0000
+lzcntw 000000000000df6a -> 5555555555550000 0040
+lzcntw 0000000000008d23 -> 5555555555550000 0040
+lzcntw 0000000000007026 -> 5555555555550001 0000
+lzcntw 00000000000042b3 -> 5555555555550001 0000
+lzcntw 00000000000035e9 -> 5555555555550002 0000
+lzcntw 0000000000002329 -> 5555555555550002 0000
+lzcntw 0000000000001bef -> 5555555555550003 0000
+lzcntw 00000000000011a3 -> 5555555555550003 0000
+lzcntw 0000000000000e02 -> 5555555555550004 0000
+lzcntw 0000000000000853 -> 5555555555550004 0000
+lzcntw 00000000000006ba -> 5555555555550005 0000
+lzcntw 0000000000000464 -> 5555555555550005 0000
+lzcntw 000000000000037d -> 5555555555550006 0000
+lzcntw 0000000000000233 -> 5555555555550006 0000
+lzcntw 00000000000001be -> 5555555555550007 0000
+lzcntw 0000000000000119 -> 5555555555550007 0000
+lzcntw 00000000000000de -> 5555555555550008 0000
+lzcntw 000000000000008c -> 5555555555550008 0000
+lzcntw 000000000000006f -> 5555555555550009 0000
+lzcntw 0000000000000045 -> 5555555555550009 0000
+lzcntw 0000000000000037 -> 555555555555000a 0000
+lzcntw 0000000000000022 -> 555555555555000a 0000
+lzcntw 000000000000001b -> 555555555555000b 0000
+lzcntw 0000000000000010 -> 555555555555000b 0000
+lzcntw 000000000000000c -> 555555555555000c 0000
+lzcntw 0000000000000007 -> 555555555555000d 0000
+lzcntw 0000000000000003 -> 555555555555000e 0000
+lzcntw 0000000000000001 -> 555555555555000f 0000
+lzcntw 0000000000000000 -> 5555555555550010 0001

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.vgtest
new file mode 100644 (file)
index 0000000..74d82b5
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/lzcnt64.vgtest
@@ -0,0 +1,3 @@
+prog: lzcnt64
+prereq: ../../../tests/x86_amd64_features amd64-lzcnt
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/pcmpstr64.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/pcmpstr64.c
new file mode 100644 (file)
index 0000000..c655ffb
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/pcmpstr64.c
@@ -0,0 +1,1095 @@
+
+/* Tests in detail the core arithmetic for pcmp{e,i}str{i,m} using
+   pcmpistri to drive it.  Does not check the e-vs-i or i-vs-m
+   aspect. */
+
+#include <string.h>
+#include <stdio.h>
+#include <assert.h>
+
+typedef  unsigned int   UInt;
+typedef  signed int     Int;
+typedef  unsigned char  UChar;
+typedef  unsigned long long int ULong;
+typedef  UChar          Bool;
+#define False ((Bool)0)
+#define True  ((Bool)1)
+
+//typedef  unsigned char  V128[16];
+typedef
+   union {
+      UChar uChar[16];
+      UInt  uInt[4];
+   }
+   V128;
+
+#define SHIFT_O   11
+#define SHIFT_S   7
+#define SHIFT_Z   6
+#define SHIFT_A   4
+#define SHIFT_C   0
+#define SHIFT_P   2
+
+#define MASK_O    (1ULL << SHIFT_O)
+#define MASK_S    (1ULL << SHIFT_S)
+#define MASK_Z    (1ULL << SHIFT_Z)
+#define MASK_A    (1ULL << SHIFT_A)
+#define MASK_C    (1ULL << SHIFT_C)
+#define MASK_P    (1ULL << SHIFT_P)
+
+
+UInt clz32 ( UInt x )
+{
+   Int y, m, n;
+   y = -(x >> 16);
+   m = (y >> 16) & 16;
+   n = 16 - m;
+   x = x >> m;
+   y = x - 0x100;
+   m = (y >> 16) & 8;
+   n = n + m;
+   x = x << m;
+   y = x - 0x1000;
+   m = (y >> 16) & 4;
+   n = n + m;
+   x = x << m;
+   y = x - 0x4000;
+   m = (y >> 16) & 2;
+   n = n + m;
+   x = x << m;
+   y = x >> 14;
+   m = y & ~(y >> 1);
+   return n + 2 - m;
+}
+
+UInt ctz32 ( UInt x )
+{
+   return 32 - clz32((~x) & (x-1));
+}
+
+void expand ( V128* dst, char* summary )
+{
+   Int i;
+   assert( strlen(summary) == 16 );
+   for (i = 0; i < 16; i++) {
+      UChar xx = 0;
+      UChar x = summary[15-i];
+      if      (x >= '0' && x <= '9') { xx = x - '0'; }
+      else if (x >= 'A' && x <= 'F') { xx = x - 'A' + 10; }
+      else if (x >= 'a' && x <= 'f') { xx = x - 'a' + 10; }
+      else assert(0);
+
+      assert(xx < 16);
+      xx = (xx << 4) | xx;
+      assert(xx < 256);
+      dst->uChar[i] = xx;
+   }
+}
+
+void try_istri ( char* which,
+                 UInt(*h_fn)(V128*,V128*),
+                 UInt(*s_fn)(V128*,V128*),
+                 char* summL, char* summR )
+{
+   assert(strlen(which) == 2);
+   V128 argL, argR;
+   expand(&argL, summL);
+   expand(&argR, summR);
+   UInt h_res = h_fn(&argL, &argR);
+   UInt s_res = s_fn(&argL, &argR);
+   printf("istri %s  %s %s -> %08x %08x %s\n",
+          which, summL, summR, h_res, s_res, h_res == s_res ? "" : "!!!!");
+}
+
+UInt zmask_from_V128 ( V128* arg )
+{
+   UInt i, res = 0;
+   for (i = 0; i < 16; i++) {
+      res |=  ((arg->uChar[i] == 0) ? 1 : 0) << i;
+   }
+   return res;
+}
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       GENERAL                        //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+
+/* Given partial results from a pcmpXstrX operation (intRes1,
+   basically), generate an I format (index value for ECX) output, and
+   also the new OSZACP flags.
+*/
+static
+void pcmpXstrX_WRK_gen_output_fmt_I(/*OUT*/V128* resV,
+                                    /*OUT*/UInt* resOSZACP,
+                                    UInt intRes1,
+                                    UInt zmaskL, UInt zmaskR,
+                                    UInt validL,
+                                    UInt pol, UInt idx )
+{
+   assert((pol >> 2) == 0);
+   assert((idx >> 1) == 0);
+
+   UInt intRes2 = 0;
+   switch (pol) {
+      case 0: intRes2 = intRes1;          break; // pol +
+      case 1: intRes2 = ~intRes1;         break; // pol -
+      case 2: intRes2 = intRes1;          break; // pol m+
+      case 3: intRes2 = intRes1 ^ validL; break; // pol m-
+   }
+   intRes2 &= 0xFFFF;
+
+   // generate ecx value
+   UInt newECX = 0;
+   if (idx) {
+     // index of ms-1-bit
+     newECX = intRes2 == 0 ? 16 : (31 - clz32(intRes2));
+   } else {
+     // index of ls-1-bit
+     newECX = intRes2 == 0 ? 16 : ctz32(intRes2);
+   }
+
+   *(UInt*)(&resV[0]) = newECX;
+
+   // generate new flags, common to all ISTRI and ISTRM cases
+   *resOSZACP    // A, P are zero
+     = ((intRes2 == 0) ? 0 : MASK_C) // C == 0 iff intRes2 == 0
+     | ((zmaskL == 0)  ? 0 : MASK_Z) // Z == 1 iff any in argL is 0
+     | ((zmaskR == 0)  ? 0 : MASK_S) // S == 1 iff any in argR is 0
+     | ((intRes2 & 1) << SHIFT_O);   // O == IntRes2[0]
+}
+
+
+/* Compute result and new OSZACP flags for all PCMP{E,I}STR{I,M}
+   variants.
+
+   For xSTRI variants, the new ECX value is placed in the 32 bits
+   pointed to by *resV.  For xSTRM variants, the result is a 128 bit
+   value and is placed at *resV in the obvious way.
+
+   For all variants, the new OSZACP value is placed at *resOSZACP.
+
+   argLV and argRV are the vector args.  The caller must prepare a
+   16-bit mask for each, zmaskL and zmaskR.  For ISTRx variants this
+   must be 1 for each zero byte of of the respective arg.  For ESTRx
+   variants this is derived from the explicit length indication, and
+   must be 0 in all places except at the bit index corresponding to
+   the valid length (0 .. 16).  If the valid length is 16 then the
+   mask must be all zeroes.  In all cases, bits 31:16 must be zero.
+
+   imm8 is the original immediate from the instruction.  isSTRM
+   indicates whether this is a xSTRM or xSTRI variant, which controls
+   how much of *res is written.
+
+   If the given imm8 case can be handled, the return value is True.
+   If not, False is returned, and neither *res not *resOSZACP are
+   altered.
+*/
+
+Bool pcmpXstrX_WRK ( /*OUT*/V128* resV,
+                     /*OUT*/UInt* resOSZACP,
+                     V128* argLV,  V128* argRV,
+                     UInt zmaskL, UInt zmaskR,
+                     UInt imm8,   Bool isSTRM )
+{
+   assert(imm8 < 0x80);
+   assert((zmaskL >> 16) == 0);
+   assert((zmaskR >> 16) == 0);
+
+   /* Explicitly reject any imm8 values that haven't been validated,
+      even if they would probably work.  Life is too short to have
+      unvalidated cases in the code base. */
+   switch (imm8) {
+      case 0x02: case 0x08: case 0x0C: case 0x12: case 0x1A:
+      case 0x3A: case 0x44: case 0x4A:
+         break;
+      default:
+         return False;
+   }
+
+   UInt fmt = (imm8 >> 0) & 3; // imm8[1:0]  data format
+   UInt agg = (imm8 >> 2) & 3; // imm8[3:2]  aggregation fn
+   UInt pol = (imm8 >> 4) & 3; // imm8[5:4]  polarity
+   UInt idx = (imm8 >> 6) & 1; // imm8[6]    1==msb/bytemask
+
+   /*----------------------------------------*/
+   /*-- strcmp on byte data                --*/
+   /*----------------------------------------*/
+
+   if (agg == 2/*equal each, aka strcmp*/
+       && (fmt == 0/*ub*/ || fmt == 2/*sb*/)
+       && !isSTRM) {
+      Int    i;
+      UChar* argL = (UChar*)argLV;
+      UChar* argR = (UChar*)argRV;
+      UInt boolResII = 0;
+      for (i = 15; i >= 0; i--) {
+         UChar cL  = argL[i];
+         UChar cR  = argR[i];
+         boolResII = (boolResII << 1) | (cL == cR ? 1 : 0);
+      }
+      UInt validL = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt validR = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+
+      // do invalidation, common to all equal-each cases
+      UInt intRes1
+         = (boolResII & validL & validR)  // if both valid, use cmpres
+           | (~ (validL | validR));       // if both invalid, force 1
+                                          // else force 0
+      intRes1 &= 0xFFFF;
+
+      // generate I-format output
+      pcmpXstrX_WRK_gen_output_fmt_I(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx
+      );
+
+      return True;
+   }
+
+   /*----------------------------------------*/
+   /*-- set membership on byte data        --*/
+   /*----------------------------------------*/
+
+   if (agg == 0/*equal any, aka find chars in a set*/
+       && (fmt == 0/*ub*/ || fmt == 2/*sb*/)
+       && !isSTRM) {
+      /* argL: the string,  argR: charset */
+      UInt   si, ci;
+      UChar* argL    = (UChar*)argLV;
+      UChar* argR    = (UChar*)argRV;
+      UInt   boolRes = 0;
+      UInt   validL  = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt   validR  = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+
+      for (si = 0; si < 16; si++) {
+         if ((validL & (1 << si)) == 0)
+            // run off the end of the string.
+            break;
+         UInt m = 0;
+         for (ci = 0; ci < 16; ci++) {
+            if ((validR & (1 << ci)) == 0) break;
+            if (argR[ci] == argL[si]) { m = 1; break; }
+         }
+         boolRes |= (m << si);
+      }
+
+      // boolRes is "pre-invalidated"
+      UInt intRes1 = boolRes & 0xFFFF;
+   
+      // generate I-format output
+      pcmpXstrX_WRK_gen_output_fmt_I(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx
+      );
+
+      return True;
+   }
+
+   /*----------------------------------------*/
+   /*-- substring search on byte data      --*/
+   /*----------------------------------------*/
+
+   if (agg == 3/*equal ordered, aka substring search*/
+       && (fmt == 0/*ub*/ || fmt == 2/*sb*/)
+       && !isSTRM) {
+
+      /* argL: haystack,  argR: needle */
+      UInt   ni, hi;
+      UChar* argL    = (UChar*)argLV;
+      UChar* argR    = (UChar*)argRV;
+      UInt   boolRes = 0;
+      UInt   validL  = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt   validR  = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+      for (hi = 0; hi < 16; hi++) {
+         if ((validL & (1 << hi)) == 0)
+            // run off the end of the haystack
+            break;
+         UInt m = 1;
+         for (ni = 0; ni < 16; ni++) {
+            if ((validR & (1 << ni)) == 0) break;
+            UInt i = ni + hi;
+            if (i >= 16) break;
+            if (argL[i] != argR[ni]) { m = 0; break; }
+         }
+         boolRes |= (m << hi);
+      }
+
+      // boolRes is "pre-invalidated"
+      UInt intRes1 = boolRes & 0xFFFF;
+
+      // generate I-format output
+      pcmpXstrX_WRK_gen_output_fmt_I(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx
+      );
+
+      return True;
+   }
+
+   /*----------------------------------------*/
+   /*-- ranges, unsigned byte data         --*/
+   /*----------------------------------------*/
+
+   if (agg == 1/*ranges*/
+       && fmt == 0/*ub*/
+       && !isSTRM) {
+
+      /* argL: string,  argR: range-pairs */
+      UInt   ri, si;
+      UChar* argL    = (UChar*)argLV;
+      UChar* argR    = (UChar*)argRV;
+      UInt   boolRes = 0;
+      UInt   validL  = ~(zmaskL | -zmaskL);  // not(left(zmaskL))
+      UInt   validR  = ~(zmaskR | -zmaskR);  // not(left(zmaskR))
+      for (si = 0; si < 16; si++) {
+         if ((validL & (1 << si)) == 0)
+            // run off the end of the string
+            break;
+         UInt m = 0;
+         for (ri = 0; ri < 16; ri += 2) {
+            if ((validR & (3 << ri)) != (3 << ri)) break;
+            if (argR[ri] <= argL[si] && argL[si] <= argR[ri+1]) { 
+               m = 1; break;
+            }
+         }
+         boolRes |= (m << si);
+      }
+
+      // boolRes is "pre-invalidated"
+      UInt intRes1 = boolRes & 0xFFFF;
+
+      // generate I-format output
+      pcmpXstrX_WRK_gen_output_fmt_I(
+         resV, resOSZACP,
+         intRes1, zmaskL, zmaskR, validL, pol, idx
+      );
+
+      return True;
+   }
+
+   return False;
+}
+
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       ISTRI_4A                       //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_4A ( V128* argL, V128* argR )
+{
+   V128 block[2];
+   memcpy(&block[0], argL, sizeof(V128));
+   memcpy(&block[1], argR, sizeof(V128));
+   ULong res, flags;
+   __asm__ __volatile__(
+      "subq      $1024,  %%rsp"             "\n\t"
+      "movdqu    0(%2),  %%xmm2"            "\n\t"
+      "movdqu    16(%2), %%xmm11"           "\n\t"
+      "pcmpistri $0x4A,  %%xmm2, %%xmm11"   "\n\t"
+      "pushfq"                              "\n\t"
+      "popq      %%rdx"                     "\n\t"
+      "movq      %%rcx,  %0"                "\n\t"
+      "movq      %%rdx,  %1"                "\n\t"
+      "addq      $1024,  %%rsp"             "\n\t"
+      : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+      : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+   );
+   return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_4A ( V128* argLU, V128* argRU )
+{
+   V128 resV;
+   UInt resOSZACP, resECX;
+   Bool ok
+      = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+                       zmask_from_V128(argLU),
+                       zmask_from_V128(argRU),
+                       0x4A, False/*!isSTRM*/
+        );
+   assert(ok);
+   resECX = resV.uInt[0];
+   return (resOSZACP << 16) | resECX;
+}
+
+void istri_4A ( void )
+{
+   char* wot = "4A";
+   UInt(*h)(V128*,V128*) = h_pcmpistri_4A;
+   UInt(*s)(V128*,V128*) = s_pcmpistri_4A;
+
+   try_istri(wot,h,s, "0000000000000000", "0000000000000000"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); 
+   try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa"); 
+
+   try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa"); 
+
+   try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000"); 
+}
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       ISTRI_3A                       //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_3A ( V128* argL, V128* argR )
+{
+   V128 block[2];
+   memcpy(&block[0], argL, sizeof(V128));
+   memcpy(&block[1], argR, sizeof(V128));
+   ULong res, flags;
+   __asm__ __volatile__(
+      "subq      $1024,  %%rsp"             "\n\t"
+      "movdqu    0(%2),  %%xmm2"            "\n\t"
+      "movdqu    16(%2), %%xmm11"           "\n\t"
+      "pcmpistri $0x3A,  %%xmm2, %%xmm11"   "\n\t"
+      "pushfq"                              "\n\t"
+      "popq      %%rdx"                     "\n\t"
+      "movq      %%rcx,  %0"                "\n\t"
+      "movq      %%rdx,  %1"                "\n\t"
+      "addq      $1024,  %%rsp"             "\n\t"
+      : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+      : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+   );
+   return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_3A ( V128* argLU, V128* argRU )
+{
+   V128 resV;
+   UInt resOSZACP, resECX;
+   Bool ok
+      = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+                       zmask_from_V128(argLU),
+                       zmask_from_V128(argRU),
+                       0x3A, False/*!isSTRM*/
+        );
+   assert(ok);
+   resECX = resV.uInt[0];
+   return (resOSZACP << 16) | resECX;
+}
+
+void istri_3A ( void )
+{
+   char* wot = "3A";
+   UInt(*h)(V128*,V128*) = h_pcmpistri_3A;
+   UInt(*s)(V128*,V128*) = s_pcmpistri_3A;
+
+   try_istri(wot,h,s, "0000000000000000", "0000000000000000"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); 
+   try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa"); 
+
+   try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa"); 
+
+   try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000"); 
+}
+
+
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       ISTRI_0C                       //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+__attribute__((noinline))
+UInt h_pcmpistri_0C ( V128* argL, V128* argR )
+{
+   V128 block[2];
+   memcpy(&block[0], argL, sizeof(V128));
+   memcpy(&block[1], argR, sizeof(V128));
+   ULong res = 0, flags = 0;
+   __asm__ __volatile__(
+      "movdqa    0(%2),  %%xmm2"            "\n\t"
+      "movdqa    16(%2), %%xmm11"           "\n\t"
+      "pcmpistri $0x0C,  %%xmm2, %%xmm11"   "\n\t"
+      //"pcmpistrm $0x0C,  %%xmm2, %%xmm11"   "\n\t"
+      //"movd %%xmm0, %%ecx" "\n\t"
+      "pushfq"                              "\n\t"
+      "popq      %%rdx"                     "\n\t"
+      "movq      %%rcx,  %0"                "\n\t"
+      "movq      %%rdx,  %1"                "\n\t"
+      : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+      : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+   );
+   return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_0C ( V128* argLU, V128* argRU )
+{
+   V128 resV;
+   UInt resOSZACP, resECX;
+   Bool ok
+      = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+                       zmask_from_V128(argLU),
+                       zmask_from_V128(argRU),
+                       0x0C, False/*!isSTRM*/
+        );
+   assert(ok);
+   resECX = resV.uInt[0];
+   return (resOSZACP << 16) | resECX;
+}
+
+void istri_0C ( void )
+{
+   char* wot = "0C";
+   UInt(*h)(V128*,V128*) = h_pcmpistri_0C;
+   UInt(*s)(V128*,V128*) = s_pcmpistri_0C;
+   
+   try_istri(wot,h,s, "111111111abcde11", "00000000000abcde"); 
+
+   try_istri(wot,h,s, "111111111abcde11", "0000abcde00abcde"); 
+
+   try_istri(wot,h,s, "1111111111abcde1", "00000000000abcde"); 
+   try_istri(wot,h,s, "11111111111abcde", "00000000000abcde"); 
+   try_istri(wot,h,s, "111111111111abcd", "00000000000abcde"); 
+
+   try_istri(wot,h,s, "111abcde1abcde11", "00000000000abcde"); 
+
+   try_istri(wot,h,s, "11abcde11abcde11", "00000000000abcde"); 
+   try_istri(wot,h,s, "1abcde111abcde11", "00000000000abcde"); 
+   try_istri(wot,h,s, "abcde1111abcde11", "00000000000abcde"); 
+   try_istri(wot,h,s, "bcde11111abcde11", "00000000000abcde"); 
+   try_istri(wot,h,s, "cde111111abcde11", "00000000000abcde"); 
+
+   try_istri(wot,h,s, "01abcde11abcde11", "00000000000abcde"); 
+   try_istri(wot,h,s, "00abcde11abcde11", "00000000000abcde"); 
+   try_istri(wot,h,s, "000bcde11abcde11", "00000000000abcde"); 
+
+   try_istri(wot,h,s, "00abcde10abcde11", "00000000000abcde"); 
+   try_istri(wot,h,s, "00abcde100bcde11", "00000000000abcde"); 
+
+   try_istri(wot,h,s, "1111111111111234", "0000000000000000"); 
+   try_istri(wot,h,s, "1111111111111234", "0000000000000001"); 
+   try_istri(wot,h,s, "1111111111111234", "0000000000000011"); 
+
+   try_istri(wot,h,s, "1111111111111234", "1111111111111234"); 
+   try_istri(wot,h,s, "a111111111111111", "000000000000000a"); 
+   try_istri(wot,h,s, "b111111111111111", "000000000000000a"); 
+}
+
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       ISTRI_08                       //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_08 ( V128* argL, V128* argR )
+{
+   V128 block[2];
+   memcpy(&block[0], argL, sizeof(V128));
+   memcpy(&block[1], argR, sizeof(V128));
+   ULong res, flags;
+   __asm__ __volatile__(
+      "subq      $1024,  %%rsp"             "\n\t"
+      "movdqu    0(%2),  %%xmm2"            "\n\t"
+      "movdqu    16(%2), %%xmm11"           "\n\t"
+      "pcmpistri $0x08,  %%xmm2, %%xmm11"   "\n\t"
+      "pushfq"                              "\n\t"
+      "popq      %%rdx"                     "\n\t"
+      "movq      %%rcx,  %0"                "\n\t"
+      "movq      %%rdx,  %1"                "\n\t"
+      "addq      $1024,  %%rsp"             "\n\t"
+      : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+      : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+   );
+   return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_08 ( V128* argLU, V128* argRU )
+{
+   V128 resV;
+   UInt resOSZACP, resECX;
+   Bool ok
+      = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+                       zmask_from_V128(argLU),
+                       zmask_from_V128(argRU),
+                       0x08, False/*!isSTRM*/
+        );
+   assert(ok);
+   resECX = resV.uInt[0];
+   return (resOSZACP << 16) | resECX;
+}
+
+void istri_08 ( void )
+{
+   char* wot = "08";
+   UInt(*h)(V128*,V128*) = h_pcmpistri_08;
+   UInt(*s)(V128*,V128*) = s_pcmpistri_08;
+
+   try_istri(wot,h,s, "0000000000000000", "0000000000000000"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); 
+   try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa"); 
+
+   try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa"); 
+
+   try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000"); 
+}
+
+
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       ISTRI_1A                       //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_1A ( V128* argL, V128* argR )
+{
+   V128 block[2];
+   memcpy(&block[0], argL, sizeof(V128));
+   memcpy(&block[1], argR, sizeof(V128));
+   ULong res, flags;
+   __asm__ __volatile__(
+      "subq      $1024,  %%rsp"             "\n\t"
+      "movdqu    0(%2),  %%xmm2"            "\n\t"
+      "movdqu    16(%2), %%xmm11"           "\n\t"
+      "pcmpistri $0x1A,  %%xmm2, %%xmm11"   "\n\t"
+      "pushfq"                              "\n\t"
+      "popq      %%rdx"                     "\n\t"
+      "movq      %%rcx,  %0"                "\n\t"
+      "movq      %%rdx,  %1"                "\n\t"
+      "addq      $1024,  %%rsp"             "\n\t"
+      : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+      : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+   );
+   return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_1A ( V128* argLU, V128* argRU )
+{
+   V128 resV;
+   UInt resOSZACP, resECX;
+   Bool ok
+      = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+                       zmask_from_V128(argLU),
+                       zmask_from_V128(argRU),
+                       0x1A, False/*!isSTRM*/
+        );
+   assert(ok);
+   resECX = resV.uInt[0];
+   return (resOSZACP << 16) | resECX;
+}
+
+void istri_1A ( void )
+{
+   char* wot = "1A";
+   UInt(*h)(V128*,V128*) = h_pcmpistri_1A;
+   UInt(*s)(V128*,V128*) = s_pcmpistri_1A;
+
+   try_istri(wot,h,s, "0000000000000000", "0000000000000000"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaa2aaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaa2aaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaa2aa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaa2aaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaa2aaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaa2a"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "baaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9aaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaaaaaa7aaa"); 
+   try_istri(wot,h,s, "b9baaaaaaaaaaaaa", "aaaaaaaa2aaa4aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaa0aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaa0aaa"); 
+   try_istri(wot,h,s, "aaaaaaaa0aaaaaaa", "aaaaaaaaaaaa0aaa"); 
+
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaa0aaa", "aaaaaaaa0aaaaaaa"); 
+
+   try_istri(wot,h,s, "0000000000000000", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "8000000000000000", "aaaaaaaa0aaaaaaa"); 
+   try_istri(wot,h,s, "0000000000000001", "aaaaaaaa0aaaaaaa"); 
+
+   try_istri(wot,h,s, "0000000000000000", "aaaaaaaaaaaaaaaa"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "0000000000000000"); 
+}
+
+
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       ISTRI_02                       //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_02 ( V128* argL, V128* argR )
+{
+   V128 block[2];
+   memcpy(&block[0], argL, sizeof(V128));
+   memcpy(&block[1], argR, sizeof(V128));
+   ULong res, flags;
+   __asm__ __volatile__(
+      "subq      $1024,  %%rsp"             "\n\t"
+      "movdqu    0(%2),  %%xmm2"            "\n\t"
+      "movdqu    16(%2), %%xmm11"           "\n\t"
+      "pcmpistri $0x02,  %%xmm2, %%xmm11"   "\n\t"
+//"pcmpistrm $0x02, %%xmm2, %%xmm11"   "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+      "pushfq"                              "\n\t"
+      "popq      %%rdx"                     "\n\t"
+      "movq      %%rcx,  %0"                "\n\t"
+      "movq      %%rdx,  %1"                "\n\t"
+      "addq      $1024,  %%rsp"             "\n\t"
+      : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+      : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+   );
+   return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_02 ( V128* argLU, V128* argRU )
+{
+   V128 resV;
+   UInt resOSZACP, resECX;
+   Bool ok
+      = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+                       zmask_from_V128(argLU),
+                       zmask_from_V128(argRU),
+                       0x02, False/*!isSTRM*/
+        );
+   assert(ok);
+   resECX = resV.uInt[0];
+   return (resOSZACP << 16) | resECX;
+}
+
+void istri_02 ( void )
+{
+   char* wot = "02";
+   UInt(*h)(V128*,V128*) = h_pcmpistri_02;
+   UInt(*s)(V128*,V128*) = s_pcmpistri_02;
+
+   try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab"); 
+   try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd"); 
+
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd"); 
+   try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd"); 
+   try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd"); 
+   try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd"); 
+   try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd"); 
+
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0"); 
+
+   try_istri(wot,h,s, "0000000000000000", "0000000000000000"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd"); 
+   try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba"); 
+   try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb"); 
+   try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba"); 
+
+   try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0"); 
+
+   try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe"); 
+   try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe"); 
+}
+
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       ISTRI_12                       //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_12 ( V128* argL, V128* argR )
+{
+   V128 block[2];
+   memcpy(&block[0], argL, sizeof(V128));
+   memcpy(&block[1], argR, sizeof(V128));
+   ULong res, flags;
+   __asm__ __volatile__(
+      "subq      $1024,  %%rsp"             "\n\t"
+      "movdqu    0(%2),  %%xmm2"            "\n\t"
+      "movdqu    16(%2), %%xmm11"           "\n\t"
+      "pcmpistri $0x12,  %%xmm2, %%xmm11"   "\n\t"
+//"pcmpistrm $0x12, %%xmm2, %%xmm11"   "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+      "pushfq"                              "\n\t"
+      "popq      %%rdx"                     "\n\t"
+      "movq      %%rcx,  %0"                "\n\t"
+      "movq      %%rdx,  %1"                "\n\t"
+      "addq      $1024,  %%rsp"             "\n\t"
+      : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+      : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+   );
+   return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_12 ( V128* argLU, V128* argRU )
+{
+   V128 resV;
+   UInt resOSZACP, resECX;
+   Bool ok
+      = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+                       zmask_from_V128(argLU),
+                       zmask_from_V128(argRU),
+                       0x12, False/*!isSTRM*/
+        );
+   assert(ok);
+   resECX = resV.uInt[0];
+   return (resOSZACP << 16) | resECX;
+}
+
+void istri_12 ( void )
+{
+   char* wot = "12";
+   UInt(*h)(V128*,V128*) = h_pcmpistri_12;
+   UInt(*s)(V128*,V128*) = s_pcmpistri_12;
+
+   try_istri(wot,h,s, "abcdacbdabcdabcd", "000000000000000a"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000000b"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "00000000000000ab"); 
+   try_istri(wot,h,s, "abcdabc0abcdabcd", "000000000000abcd"); 
+
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd"); 
+   try_istri(wot,h,s, "0bcdabcdabcdabcd", "000000000000abcd"); 
+   try_istri(wot,h,s, "abcdabcdabcda0cd", "000000000000abcd"); 
+   try_istri(wot,h,s, "abcdabcdabcdab0d", "000000000000abcd"); 
+   try_istri(wot,h,s, "abcdabcdabcdabc0", "000000000000abcd"); 
+
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abcd"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000a0cd"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000ab0d"); 
+   try_istri(wot,h,s, "abcdabcdabcdabcd", "000000000000abc0"); 
+
+   try_istri(wot,h,s, "0000000000000000", "0000000000000000"); 
+   try_istri(wot,h,s, "aaaaaaaaaaaaaaaa", "aaaaaaaaaaaaaaaa"); 
+
+   try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000abcd"); 
+   try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000dcba"); 
+   try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000bbbb"); 
+   try_istri(wot,h,s, "0000abcdabcdabcd", "000000000000baba"); 
+
+   try_istri(wot,h,s, "0000abcdabcdabcd", "00000000000baba0"); 
+
+   try_istri(wot,h,s, "0ddc0ffeebadf00d", "00000000cafebabe"); 
+   try_istri(wot,h,s, "0ddc0ffeebadfeed", "00000000cafebabe"); 
+}
+
+
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                       ISTRI_44                       //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+UInt h_pcmpistri_44 ( V128* argL, V128* argR )
+{
+   V128 block[2];
+   memcpy(&block[0], argL, sizeof(V128));
+   memcpy(&block[1], argR, sizeof(V128));
+   ULong res, flags;
+   __asm__ __volatile__(
+      "subq      $1024,  %%rsp"             "\n\t"
+      "movdqu    0(%2),  %%xmm2"            "\n\t"
+      "movdqu    16(%2), %%xmm11"           "\n\t"
+      "pcmpistri $0x44,  %%xmm2, %%xmm11"   "\n\t"
+//"pcmpistrm $0x04, %%xmm2, %%xmm11"   "\n\t"
+//"movd %%xmm0, %%ecx" "\n\t"
+      "pushfq"                              "\n\t"
+      "popq      %%rdx"                     "\n\t"
+      "movq      %%rcx,  %0"                "\n\t"
+      "movq      %%rdx,  %1"                "\n\t"
+      "addq      $1024,  %%rsp"             "\n\t"
+      : /*out*/ "=r"(res), "=r"(flags) : "r"/*in*/(&block[0])
+      : "rcx","rdx","xmm0","xmm2","xmm11","cc","memory"
+   );
+   return ((flags & 0x8D5) << 16) | (res & 0xFFFF);
+}
+
+UInt s_pcmpistri_44 ( V128* argLU, V128* argRU )
+{
+   V128 resV;
+   UInt resOSZACP, resECX;
+   Bool ok
+      = pcmpXstrX_WRK( &resV, &resOSZACP, argLU, argRU,
+                       zmask_from_V128(argLU),
+                       zmask_from_V128(argRU),
+                       0x44, False/*!isSTRM*/
+        );
+   assert(ok);
+   resECX = resV.uInt[0];
+   return (resOSZACP << 16) | resECX;
+}
+
+void istri_44 ( void )
+{
+   char* wot = "44";
+   UInt(*h)(V128*,V128*) = h_pcmpistri_44;
+   UInt(*s)(V128*,V128*) = s_pcmpistri_44;
+
+   try_istri(wot,h,s, "aaaabbbbccccdddd", "00000000000000bc"); 
+   try_istri(wot,h,s, "aaaabbbbccccdddd", "00000000000000cb"); 
+   try_istri(wot,h,s, "baaabbbbccccdddd", "00000000000000cb"); 
+   try_istri(wot,h,s, "baaabbbbccccdddc", "00000000000000cb"); 
+
+   try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000cb"); 
+   try_istri(wot,h,s, "bbbbbbbb0bbbbbbb", "00000000000000cb"); 
+   try_istri(wot,h,s, "bbbbbbbbbbbbbb0b", "00000000000000cb"); 
+   try_istri(wot,h,s, "bbbbbbbbbbbbbbb0", "00000000000000cb"); 
+   try_istri(wot,h,s, "0000000000000000", "00000000000000cb"); 
+
+   try_istri(wot,h,s, "0000000000000000", "0000000000000000"); 
+
+   try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "00000000000000cb"); 
+   try_istri(wot,h,s, "bbbbbbbbbbbbbbbb", "000000000000000b"); 
+   try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000062cb"); 
+
+   try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000002cb"); 
+   try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "00000000000000cb"); 
+   try_istri(wot,h,s, "b4b4b4b4b4b4b4b4", "000000000000000b");
+
+   try_istri(wot,h,s, "0123456789abcdef", "000000fecb975421");
+   try_istri(wot,h,s, "123456789abcdef1", "000000fecb975421");
+
+   try_istri(wot,h,s, "0123456789abcdef", "00000000dca86532");
+   try_istri(wot,h,s, "123456789abcdef1", "00000000dca86532");
+}
+
+
+
+
+
+//////////////////////////////////////////////////////////
+//                                                      //
+//                         main                         //
+//                                                      //
+//////////////////////////////////////////////////////////
+
+int main ( void )
+{
+   istri_4A();
+   istri_3A();
+   istri_08();
+   istri_1A();
+   istri_02();
+   istri_0C();
+   istri_12();
+   istri_44();
+   return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/pcmpxstrx64.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/pcmpxstrx64.c
new file mode 100644 (file)
index 0000000..6d67aa7
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/pcmpxstrx64.c
@@ -0,0 +1,334 @@
+
+/* Tests e-vs-i or i-vs-m aspects for pcmp{e,i}str{i,m}.  Does not
+   check the core arithmetic in any detail.  */
+
+#include <string.h>
+#include <stdio.h>
+#include <assert.h>
+
+typedef  unsigned char  V128[16];
+typedef  unsigned int   UInt;
+typedef  signed int     Int;
+typedef  unsigned char  UChar;
+typedef  unsigned long long int ULong;
+typedef  UChar          Bool;
+#define False ((Bool)0)
+#define True  ((Bool)1)
+
+void show_V128 ( V128* vec )
+{
+   Int i;
+   for (i = 15; i >= 0; i--)
+      printf("%02x", (UInt)( (*vec)[i] ));
+}
+
+void expand ( V128* dst, char* summary )
+{
+   Int i;
+   assert( strlen(summary) == 16 );
+   for (i = 0; i < 16; i++) {
+      UChar xx = 0;
+      UChar x = summary[15-i];
+      if      (x >= '0' && x <= '9') { xx = x - '0'; }
+      else if (x >= 'A' && x <= 'F') { xx = x - 'A' + 10; }
+      else if (x >= 'a' && x <= 'f') { xx = x - 'a' + 10; }
+      else assert(0);
+
+      assert(xx < 16);
+      xx = (xx << 4) | xx;
+      assert(xx < 256);
+      (*dst)[i] = xx;
+   }
+}
+
+void one_test ( char* summL, ULong rdxIN, char* summR, ULong raxIN )
+{
+   V128 argL, argR;
+   expand( &argL, summL );
+   expand( &argR, summR );
+   printf("\n");
+   printf("rdx %016llx  argL ", rdxIN);
+   show_V128(&argL);
+   printf("  rax %016llx  argR ", raxIN);
+   show_V128(&argR);
+   printf("\n");
+
+   ULong block[ 2/*in:argL*/          // 0  0
+                + 2/*in:argR*/        // 2  16
+                + 1/*in:rdx*/         // 4  32
+                + 1/*in:rax*/         // 5  40
+                + 2/*inout:xmm0*/     // 6  48
+                + 1/*inout:rcx*/      // 8  64
+                + 1/*out:rflags*/ ];  // 9  72
+   assert(sizeof(block) == 80);
+
+   UChar* blockC = (UChar*)&block[0];
+
+   /* ---------------- ISTRI_4A ---------------- */
+   memset(blockC, 0x55, 80);
+   memcpy(blockC + 0,  &argL,  16);
+   memcpy(blockC + 16, &argR,  16);
+   memcpy(blockC + 24, &rdxIN, 8);
+   memcpy(blockC + 32, &raxIN, 8);
+   memcpy(blockC + 40, &rdxIN, 8);
+   __asm__ __volatile__(
+      "movupd    0(%0), %%xmm2"           "\n\t"
+      "movupd    16(%0), %%xmm13"         "\n\t"
+      "movq      32(%0), %%rdx"           "\n\t"
+      "movq      40(%0), %%rax"           "\n\t"
+      "movupd    48(%0), %%xmm0"          "\n\t"
+      "movw      64(%0), %%rcx"           "\n\t"
+      "pcmpistri $0x4A, %%xmm2, %%xmm13"  "\n\t"
+      "movupd    %%xmm0, 48(%0)"          "\n\t"
+      "movw      %%rcx, 64(%0)"           "\n\t"
+      "pushfq"                            "\n\t"
+      "popq      %%r15"                   "\n\t"
+      "movq      %%r15, 72(%0)"           "\n\t"
+      : /*out*/ 
+      : /*in*/"r"(blockC) 
+      : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+   );
+   printf("  istri $0x4A:  ");
+   printf("    xmm0 ");
+   show_V128( (V128*)(blockC+48) );
+   printf("  rcx %016llx  flags %08llx\n", block[8], block[9] & 0x8D5);
+
+   /* ---------------- ISTRI_0A ---------------- */
+   memset(blockC, 0x55, 80);
+   memcpy(blockC + 0,  &argL,  16);
+   memcpy(blockC + 16, &argR,  16);
+   memcpy(blockC + 24, &rdxIN, 8);
+   memcpy(blockC + 32, &raxIN, 8);
+   memcpy(blockC + 40, &rdxIN, 8);
+   __asm__ __volatile__(
+      "movupd    0(%0), %%xmm2"           "\n\t"
+      "movupd    16(%0), %%xmm13"         "\n\t"
+      "movq      32(%0), %%rdx"           "\n\t"
+      "movq      40(%0), %%rax"           "\n\t"
+      "movupd    48(%0), %%xmm0"          "\n\t"
+      "movw      64(%0), %%rcx"           "\n\t"
+      "pcmpistri $0x0A, %%xmm2, %%xmm13"  "\n\t"
+      "movupd    %%xmm0, 48(%0)"          "\n\t"
+      "movw      %%rcx, 64(%0)"           "\n\t"
+      "pushfq"                            "\n\t"
+      "popq      %%r15"                   "\n\t"
+      "movq      %%r15, 72(%0)"           "\n\t"
+      : /*out*/ 
+      : /*in*/"r"(blockC) 
+      : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+   );
+   printf("  istri $0x0A:  ");
+   printf("    xmm0 ");
+   show_V128( (V128*)(blockC+48) );
+   printf("  rcx %016llx  flags %08llx\n", block[8], block[9] & 0x8D5);
+
+   /* ---------------- ISTRM_4A ---------------- */
+   memset(blockC, 0x55, 80);
+   memcpy(blockC + 0,  &argL,  16);
+   memcpy(blockC + 16, &argR,  16);
+   memcpy(blockC + 24, &rdxIN, 8);
+   memcpy(blockC + 32, &raxIN, 8);
+   memcpy(blockC + 40, &rdxIN, 8);
+   __asm__ __volatile__(
+      "movupd    0(%0), %%xmm2"           "\n\t"
+      "movupd    16(%0), %%xmm13"         "\n\t"
+      "movq      32(%0), %%rdx"           "\n\t"
+      "movq      40(%0), %%rax"           "\n\t"
+      "movupd    48(%0), %%xmm0"          "\n\t"
+      "movw      64(%0), %%rcx"           "\n\t"
+      "pcmpistrm $0x4A, %%xmm2, %%xmm13"  "\n\t"
+      "movupd    %%xmm0, 48(%0)"          "\n\t"
+      "movw      %%rcx, 64(%0)"           "\n\t"
+      "pushfq"                            "\n\t"
+      "popq      %%r15"                   "\n\t"
+      "movq      %%r15, 72(%0)"           "\n\t"
+      : /*out*/ 
+      : /*in*/"r"(blockC) 
+      : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+   );
+   printf("  istrm $0x4A:  ");
+   printf("    xmm0 ");
+   show_V128( (V128*)(blockC+48) );
+   printf("  rcx %016llx  flags %08llx\n", block[8], block[9] & 0x8D5);
+
+   /* ---------------- ISTRM_0A ---------------- */
+   memset(blockC, 0x55, 80);
+   memcpy(blockC + 0,  &argL,  16);
+   memcpy(blockC + 16, &argR,  16);
+   memcpy(blockC + 24, &rdxIN, 8);
+   memcpy(blockC + 32, &raxIN, 8);
+   memcpy(blockC + 40, &rdxIN, 8);
+   __asm__ __volatile__(
+      "movupd    0(%0), %%xmm2"           "\n\t"
+      "movupd    16(%0), %%xmm13"         "\n\t"
+      "movq      32(%0), %%rdx"           "\n\t"
+      "movq      40(%0), %%rax"           "\n\t"
+      "movupd    48(%0), %%xmm0"          "\n\t"
+      "movw      64(%0), %%rcx"           "\n\t"
+      "pcmpistrm $0x0A, %%xmm2, %%xmm13"  "\n\t"
+      "movupd    %%xmm0, 48(%0)"          "\n\t"
+      "movw      %%rcx, 64(%0)"           "\n\t"
+      "pushfq"                            "\n\t"
+      "popq      %%r15"                   "\n\t"
+      "movq      %%r15, 72(%0)"           "\n\t"
+      : /*out*/ 
+      : /*in*/"r"(blockC) 
+      : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+   );
+   printf("  istrm $0x0A:  ");
+   printf("    xmm0 ");
+   show_V128( (V128*)(blockC+48) );
+   printf("  rcx %016llx  flags %08llx\n", block[8], block[9] & 0x8D5);
+
+   /* ---------------- ESTRI_4A ---------------- */
+   memset(blockC, 0x55, 80);
+   memcpy(blockC + 0,  &argL,  16);
+   memcpy(blockC + 16, &argR,  16);
+   memcpy(blockC + 24, &rdxIN, 8);
+   memcpy(blockC + 32, &raxIN, 8);
+   memcpy(blockC + 40, &rdxIN, 8);
+   __asm__ __volatile__(
+      "movupd    0(%0), %%xmm2"           "\n\t"
+      "movupd    16(%0), %%xmm13"         "\n\t"
+      "movq      32(%0), %%rdx"           "\n\t"
+      "movq      40(%0), %%rax"           "\n\t"
+      "movupd    48(%0), %%xmm0"          "\n\t"
+      "movw      64(%0), %%rcx"           "\n\t"
+      "pcmpestri $0x4A, %%xmm2, %%xmm13"  "\n\t"
+      "movupd    %%xmm0, 48(%0)"          "\n\t"
+      "movw      %%rcx, 64(%0)"           "\n\t"
+      "pushfq"                            "\n\t"
+      "popq      %%r15"                   "\n\t"
+      "movq      %%r15, 72(%0)"           "\n\t"
+      : /*out*/ 
+      : /*in*/"r"(blockC) 
+      : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+   );
+   printf("  estri $0x4A:  ");
+   printf("    xmm0 ");
+   show_V128( (V128*)(blockC+48) );
+   printf("  rcx %016llx  flags %08llx\n", block[8], block[9] & 0x8D5);
+
+   /* ---------------- ESTRI_0A ---------------- */
+   memset(blockC, 0x55, 80);
+   memcpy(blockC + 0,  &argL,  16);
+   memcpy(blockC + 16, &argR,  16);
+   memcpy(blockC + 24, &rdxIN, 8);
+   memcpy(blockC + 32, &raxIN, 8);
+   memcpy(blockC + 40, &rdxIN, 8);
+   __asm__ __volatile__(
+      "movupd    0(%0), %%xmm2"           "\n\t"
+      "movupd    16(%0), %%xmm13"         "\n\t"
+      "movq      32(%0), %%rdx"           "\n\t"
+      "movq      40(%0), %%rax"           "\n\t"
+      "movupd    48(%0), %%xmm0"          "\n\t"
+      "movw      64(%0), %%rcx"           "\n\t"
+      "pcmpestri $0x0A, %%xmm2, %%xmm13"  "\n\t"
+      "movupd    %%xmm0, 48(%0)"          "\n\t"
+      "movw      %%rcx, 64(%0)"           "\n\t"
+      "pushfq"                            "\n\t"
+      "popq      %%r15"                   "\n\t"
+      "movq      %%r15, 72(%0)"           "\n\t"
+      : /*out*/ 
+      : /*in*/"r"(blockC) 
+      : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+   );
+   printf("  estri $0x0A:  ");
+   printf("    xmm0 ");
+   show_V128( (V128*)(blockC+48) );
+   printf("  rcx %016llx  flags %08llx\n", block[8], block[9] & 0x8D5);
+
+   /* ---------------- ESTRM_4A ---------------- */
+   memset(blockC, 0x55, 80);
+   memcpy(blockC + 0,  &argL,  16);
+   memcpy(blockC + 16, &argR,  16);
+   memcpy(blockC + 24, &rdxIN, 8);
+   memcpy(blockC + 32, &raxIN, 8);
+   memcpy(blockC + 40, &rdxIN, 8);
+   __asm__ __volatile__(
+      "movupd    0(%0), %%xmm2"           "\n\t"
+      "movupd    16(%0), %%xmm13"         "\n\t"
+      "movq      32(%0), %%rdx"           "\n\t"
+      "movq      40(%0), %%rax"           "\n\t"
+      "movupd    48(%0), %%xmm0"          "\n\t"
+      "movw      64(%0), %%rcx"           "\n\t"
+      "pcmpestrm $0x4A, %%xmm2, %%xmm13"  "\n\t"
+      "movupd    %%xmm0, 48(%0)"          "\n\t"
+      "movw      %%rcx, 64(%0)"           "\n\t"
+      "pushfq"                            "\n\t"
+      "popq      %%r15"                   "\n\t"
+      "movq      %%r15, 72(%0)"           "\n\t"
+      : /*out*/ 
+      : /*in*/"r"(blockC) 
+      : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+   );
+   printf("  estrm $0x4A:  ");
+   printf("    xmm0 ");
+   show_V128( (V128*)(blockC+48) );
+   printf("  rcx %016llx  flags %08llx\n", block[8], block[9] & 0x8D5);
+
+   /* ---------------- ESTRM_0A ---------------- */
+   memset(blockC, 0x55, 80);
+   memcpy(blockC + 0,  &argL,  16);
+   memcpy(blockC + 16, &argR,  16);
+   memcpy(blockC + 24, &rdxIN, 8);
+   memcpy(blockC + 32, &raxIN, 8);
+   memcpy(blockC + 40, &rdxIN, 8);
+   __asm__ __volatile__(
+      "movupd    0(%0), %%xmm2"           "\n\t"
+      "movupd    16(%0), %%xmm13"         "\n\t"
+      "movq      32(%0), %%rdx"           "\n\t"
+      "movq      40(%0), %%rax"           "\n\t"
+      "movupd    48(%0), %%xmm0"          "\n\t"
+      "movw      64(%0), %%rcx"           "\n\t"
+      "pcmpestrm $0x0A, %%xmm2, %%xmm13"  "\n\t"
+      "movupd    %%xmm0, 48(%0)"          "\n\t"
+      "movw      %%rcx, 64(%0)"           "\n\t"
+      "pushfq"                            "\n\t"
+      "popq      %%r15"                   "\n\t"
+      "movq      %%r15, 72(%0)"           "\n\t"
+      : /*out*/ 
+      : /*in*/"r"(blockC) 
+      : /*trash*/"memory","cc","xmm2","xmm13","xmm0","rdx","rax","rcx","r15"
+   );
+   printf("  estrm $0x0A:  ");
+   printf("    xmm0 ");
+   show_V128( (V128*)(blockC+48) );
+   printf("  rcx %016llx  flags %08llx\n", block[8], block[9] & 0x8D5);
+
+
+
+
+}
+
+int main ( void )
+{
+   one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaa0aaaaaaa", 0 );
+   one_test("0000000000000000", 0, "aaaaaaaa0aaaaaaa", 0 );
+
+   one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaaaaaaaaaa", 0 );
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 0 );
+   one_test("aaaaaaaaaaaaaaaa", 0, "aaaaaaaaaaaaaaaa", 6 );
+
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 6 );
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 15 );
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 16 );
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", 17 );
+
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -6 );
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -15 );
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -16 );
+   one_test("aaaaaaaaaaaaaaaa", 5, "aaaaaaaaaaaaaaaa", -17 );
+
+   one_test("aaaaaaaaaaaaaaaa", 5,  "aaaaaaaaaaaaaaaa", 6 );
+   one_test("aaaaaaaaaaaaaaaa", 15, "aaaaaaaaaaaaaaaa", 6 );
+   one_test("aaaaaaaaaaaaaaaa", 16, "aaaaaaaaaaaaaaaa", 6 );
+   one_test("aaaaaaaaaaaaaaaa", 17, "aaaaaaaaaaaaaaaa", 6 );
+
+   one_test("aaaaaaaaaaaaaaaa", -5,  "aaaaaaaaaaaaaaaa", 6 );
+   one_test("aaaaaaaaaaaaaaaa", -15, "aaaaaaaaaaaaaaaa", 6 );
+   one_test("aaaaaaaaaaaaaaaa", -16, "aaaaaaaaaaaaaaaa", 6 );
+   one_test("aaaaaaaaaaaaaaaa", -17, "aaaaaaaaaaaaaaaa", 6 );
+
+   return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/sse4-64.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/sse4-64.c
new file mode 100644 (file)
index 0000000..467a03f
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/sse4-64.c
@@ -0,0 +1,2681 @@
+
+/* A program to test SSE4.1/SSE4.2 instructions. 
+   Revisions:  Nov.208     - wrote this file
+               Apr.10.2010 - added PEXTR* tests
+               Apr.16.2010 - added PINS*  tests
+*/
+
+/* HOW TO COMPILE:
+   gcc -m64 -g -O -Wall -o sse4-64 sse4-64.c
+*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+//#include "tests/malloc.h" // reenable when reintegrated
+#include <string.h>
+
+
+
+// rmme when reintegrated
+// Allocates a 16-aligned block.  Asserts if the allocation fails.
+#include <malloc.h>
+__attribute__((unused))
+static void* memalign16(size_t szB)
+{
+   void* x;
+#if defined(VGO_darwin)
+   // Darwin lacks memalign, but its malloc is always 16-aligned anyway.
+   x = malloc(szB);
+#else
+   x = memalign(16, szB);
+#endif
+   assert(x);
+   assert(0 == ((16-1) & (unsigned long)x));
+   return x;
+}
+
+
+
+typedef  unsigned char           V128[16];
+typedef  unsigned int            UInt;
+typedef  signed int              Int;
+typedef  unsigned char           UChar;
+typedef  unsigned long long int  ULong;
+
+typedef  unsigned char           Bool;
+#define False ((Bool)0)
+#define True  ((Bool)1)
+
+
+typedef
+   struct {
+      V128 arg1;
+      V128 arg2;
+      V128 res;
+   }
+   RRArgs;
+
+typedef
+   struct {
+      V128 arg1;
+      V128 res;
+   }
+   RMArgs;
+
+static void do64HLtoV128 ( /*OUT*/V128* res, ULong wHi, ULong wLo )
+{
+   // try to sidestep strict-aliasing snafus by memcpying explicitly
+   UChar* p = (UChar*)res;
+   memcpy(&p[8], (UChar*)&wHi, 8);
+   memcpy(&p[0], (UChar*)&wLo, 8);
+}
+
+static UChar randUChar ( void )
+{
+   static UInt seed = 80021;
+   seed = 1103515245 * seed + 12345;
+   return (seed >> 17) & 0xFF;
+}
+
+static ULong randULong ( void )
+{
+   Int i;
+   ULong r = 0;
+   for (i = 0; i < 8; i++) {
+      r = (r << 8) | (ULong)(0xFF & randUChar());
+   }
+   return r;
+}
+
+static void randV128 ( V128* v )
+{
+   Int i;
+   for (i = 0; i < 16; i++)
+      (*v)[i] = randUChar();
+}
+
+static void showV128 ( V128* v )
+{
+   Int i;
+   for (i = 15; i >= 0; i--)
+      printf("%02x", (Int)(*v)[i]);
+}
+
+static void showMaskedV128 ( V128* v, V128* mask )
+{
+   Int i;
+   for (i = 15; i >= 0; i--)
+      printf("%02x", (Int)( ((*v)[i]) & ((*mask)[i]) ));
+}
+
+static void showIGVV( char* rOrM, char* op, Int imm,
+                      ULong src64, V128* dst, V128* res )
+{
+   printf("%s %10s $%d ", rOrM, op, imm);
+   printf("%016llx", src64);
+   printf(" ");
+   showV128(dst);
+   printf(" ");
+   showV128(res);
+   printf("\n");
+}
+
+static void showIAG ( char* rOrM, char* op, Int imm,
+                      V128* argL, ULong argR, ULong res )
+{
+   printf("%s %10s $%d ", rOrM, op, imm);
+   showV128(argL);
+   printf(" ");
+   printf("%016llx", argR);
+   printf(" ");
+   printf("%016llx", res);
+   printf("\n");
+}
+
+static void showIAA ( char* rOrM, char* op, Int imm, RRArgs* rra, V128* rmask )
+{
+   printf("%s %10s $%d ", rOrM, op, imm);
+   showV128(&rra->arg1);
+   printf(" ");
+   showV128(&rra->arg2);
+   printf(" ");
+   showMaskedV128(&rra->res, rmask);
+   printf("\n");
+}
+
+static void showAA ( char* rOrM, char* op, RRArgs* rra, V128* rmask )
+{
+   printf("%s %10s ", rOrM, op);
+   showV128(&rra->arg1);
+   printf(" ");
+   showV128(&rra->arg2);
+   printf(" ");
+   showMaskedV128(&rra->res, rmask);
+   printf("\n");
+}
+
+/* Note: these are little endian.  Hence first byte is the least
+   significant byte of lane zero. */
+
+/* Mask for insns where all result bits are non-approximated. */
+static V128 AllMask  = { 0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF, 
+                         0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF };
+
+/* Mark for insns which produce approximated vector short results. */
+static V128 ApproxPS = { 0x00,0x00,0x80,0xFF, 0x00,0x00,0x80,0xFF, 
+                         0x00,0x00,0x80,0xFF, 0x00,0x00,0x80,0xFF };
+
+/* Mark for insns which produce approximated scalar short results. */
+static V128 ApproxSS = { 0x00,0x00,0x80,0xFF, 0xFF,0xFF,0xFF,0xFF,
+                         0xFF,0xFF,0xFF,0xFF, 0xFF,0xFF,0xFF,0xFF };
+
+static V128 fives    = { 0x55,0x55,0x55,0x55, 0x55,0x55,0x55,0x55,
+                         0x55,0x55,0x55,0x55, 0x55,0x55,0x55,0x55 };
+
+static V128 zeroes   = { 0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
+                         0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00 };
+
+double mkPosInf ( void ) { return 1.0 / 0.0; }
+double mkNegInf ( void ) { return -mkPosInf(); }
+double mkPosNan ( void ) { return 0.0 / 0.0; }
+double mkNegNan ( void ) { return -mkPosNan(); }
+
+
+#define DO_imm_r_r(_opname, _imm, _src, _dst)  \
+   {  \
+      V128 _tmp;  \
+      __asm__ __volatile__(  \
+         "movupd (%0), %%xmm2"    "\n\t"  \
+         "movupd (%1), %%xmm11"   "\n\t"  \
+         _opname " $" #_imm ", %%xmm2, %%xmm11"  "\n\t"  \
+         "movupd %%xmm11, (%2)" "\n"  \
+         : /*out*/ : /*in*/ "r"(&(_src)), "r"(&(_dst)), "r"(&(_tmp))  \
+         : "cc", "memory", "xmm2", "xmm11"                            \
+      );  \
+      RRArgs rra;  \
+      memcpy(&rra.arg1, &(_src), sizeof(V128));  \
+      memcpy(&rra.arg2, &(_dst), sizeof(V128));  \
+      memcpy(&rra.res,  &(_tmp), sizeof(V128));  \
+      showIAA("r", (_opname), (_imm), &rra, &AllMask);  \
+   }
+
+#define DO_imm_m_r(_opname, _imm, _src, _dst)  \
+   {  \
+      V128 _tmp;  \
+      V128* _srcM = memalign16(sizeof(V128));  \
+      memcpy(_srcM, &(_src), sizeof(V128));  \
+      __asm__ __volatile__(  \
+         "movupd (%1), %%xmm11"   "\n\t"  \
+         _opname " $" #_imm ", (%0), %%xmm11"  "\n\t"  \
+         "movupd %%xmm11, (%2)" "\n"  \
+         : /*out*/ : /*in*/ "r"(_srcM), "r"(&(_dst)), "r"(&(_tmp))  \
+         : "cc", "memory", "xmm11"  \
+      );  \
+      RRArgs rra;  \
+      memcpy(&rra.arg1, &(_src), sizeof(V128));  \
+      memcpy(&rra.arg2, &(_dst), sizeof(V128));  \
+      memcpy(&rra.res,  &(_tmp), sizeof(V128));  \
+      showIAA("m", (_opname), (_imm), &rra, &AllMask);  \
+      free(_srcM);  \
+   }
+
+#define DO_imm_mandr_r(_opname, _imm, _src, _dst)  \
+      DO_imm_r_r( _opname, _imm, _src, _dst ) \
+      DO_imm_m_r( _opname, _imm, _src, _dst )
+
+
+
+
+
+#define DO_r_r(_opname, _src, _dst)  \
+   {  \
+      V128 _tmp;  \
+      __asm__ __volatile__(  \
+         "movupd (%0), %%xmm2"    "\n\t"  \
+         "movupd (%1), %%xmm11"   "\n\t"  \
+         _opname " %%xmm2, %%xmm11"  "\n\t"  \
+         "movupd %%xmm11, (%2)" "\n"  \
+         : /*out*/ : /*in*/ "r"(&(_src)), "r"(&(_dst)), "r"(&(_tmp))  \
+         : "cc", "memory", "xmm2", "xmm11"  \
+      );  \
+      RRArgs rra;  \
+      memcpy(&rra.arg1, &(_src), sizeof(V128));  \
+      memcpy(&rra.arg2, &(_dst), sizeof(V128));  \
+      memcpy(&rra.res,  &(_tmp), sizeof(V128));  \
+      showAA("r", (_opname), &rra, &AllMask);  \
+   }
+
+#define DO_m_r(_opname, _src, _dst)  \
+   {  \
+      V128 _tmp;  \
+      V128* _srcM = memalign16(sizeof(V128));  \
+      memcpy(_srcM, &(_src), sizeof(V128));  \
+      __asm__ __volatile__(  \
+         "movupd (%1), %%xmm11"   "\n\t"  \
+         _opname " (%0), %%xmm11"  "\n\t"  \
+         "movupd %%xmm11, (%2)" "\n"  \
+         : /*out*/ : /*in*/ "r"(_srcM), "r"(&(_dst)), "r"(&(_tmp))  \
+         : "cc", "memory", "xmm11"  \
+      );  \
+      RRArgs rra;  \
+      memcpy(&rra.arg1, &(_src), sizeof(V128));  \
+      memcpy(&rra.arg2, &(_dst), sizeof(V128));  \
+      memcpy(&rra.res,  &(_tmp), sizeof(V128));  \
+      showAA("m", (_opname), &rra, &AllMask);  \
+      free(_srcM);  \
+   }
+
+#define DO_mandr_r(_opname, _src, _dst)  \
+      DO_r_r(_opname, _src, _dst) \
+      DO_m_r(_opname, _src, _dst)
+
+
+
+
+#define DO_imm_r_to_rscalar(_opname, _imm, _src, _dstsuffix)       \
+   {  \
+      ULong _scbefore = 0x5555555555555555ULL;  \
+      ULong _scafter  = 0xAAAAAAAAAAAAAAAAULL; \
+      /* This assumes that gcc won't make any of %0, %1, %2 */ \
+      /* be r11.  That should be ensured (cough, cough) */ \
+      /* by declaring r11 to be clobbered. */ \
+      __asm__ __volatile__(  \
+         "movupd (%0), %%xmm2"    "\n\t"  \
+         "movq   (%1), %%r11"   "\n\t"  \
+         _opname " $" #_imm ", %%xmm2, %%r11" _dstsuffix  "\n\t"  \
+         "movq   %%r11, (%2)" "\n"  \
+         : /*out*/ \
+         : /*in*/ "r"(&(_src)), "r"(&(_scbefore)), "r"(&(_scafter))  \
+         : "cc", "memory", "xmm2", "r11"  \
+      );  \
+      showIAG("r", (_opname), (_imm), &(_src), (_scbefore), (_scafter));  \
+   }
+
+#define DO_imm_r_to_mscalar(_opname, _imm, _src)   \
+   {  \
+      ULong _scbefore = 0x5555555555555555ULL;  \
+      ULong _scafter = _scbefore; \
+      __asm__ __volatile__(  \
+         "movupd (%0), %%xmm2"    "\n\t"  \
+         _opname " $" #_imm ", %%xmm2, (%1)"  "\n\t"  \
+         : /*out*/ \
+         : /*in*/ "r"(&(_src)), "r"(&(_scafter))  \
+         : "cc", "memory", "xmm2"  \
+      );  \
+      showIAG("m", (_opname), (_imm), &(_src), (_scbefore), (_scafter));  \
+   }
+
+#define DO_imm_r_to_mandrscalar(_opname, _imm, _src, _dstsuffix)   \
+      DO_imm_r_to_rscalar( _opname, _imm, _src, _dstsuffix )       \
+      DO_imm_r_to_mscalar( _opname, _imm, _src )
+
+
+
+
+
+
+
+
+#define DO_imm_rscalar_to_r(_opname, _imm, _src, _srcsuffix)       \
+   {  \
+      V128  dstv;         \
+      V128  res;          \
+      ULong src64 = (ULong)(_src); \
+      memcpy(dstv, fives, sizeof(dstv)); \
+      memcpy(res,  zeroes, sizeof(res)); \
+      /* This assumes that gcc won't make any of %0, %1, %2 */ \
+      /* be r11.  That should be ensured (cough, cough) */ \
+      /* by declaring r11 to be clobbered. */ \
+      __asm__ __volatile__(  \
+         "movupd (%0), %%xmm2"    "\n\t"   /*dstv*/   \
+         "movq   (%1), %%r11"     "\n\t"   /*src64*/  \
+         _opname " $" #_imm ", %%r11" _srcsuffix ", %%xmm2"   "\n\t"  \
+         "movupd  %%xmm2, (%2)" "\n" /*res*/                          \
+         : /*out*/ \
+         : /*in*/ "r"(&dstv), "r"(&src64), "r"(&res)  \
+         : "cc", "memory", "xmm2", "r11"  \
+      );  \
+      showIGVV("r", (_opname), (_imm), src64, &dstv, &res); \
+   }
+#define DO_imm_mscalar_to_r(_opname, _imm, _src)       \
+   {  \
+      V128  dstv;         \
+      V128  res;          \
+      ULong src64 = (ULong)(_src); \
+      memcpy(dstv, fives, sizeof(dstv)); \
+      memcpy(res,  zeroes, sizeof(res)); \
+      __asm__ __volatile__(  \
+         "movupd (%0), %%xmm2"    "\n\t"   /*dstv*/   \
+         _opname " $" #_imm ", (%1), %%xmm2"   "\n\t"  \
+         "movupd  %%xmm2, (%2)" "\n" /*res*/                          \
+         : /*out*/ \
+         : /*in*/ "r"(&dstv), "r"(&src64), "r"(&res)  \
+         : "cc", "memory", "xmm2"  \
+      );  \
+      showIGVV("m", (_opname), (_imm), src64, &dstv, &res); \
+   }
+
+#define DO_imm_mandrscalar_to_r(_opname, _imm, _src, _dstsuffix)   \
+      DO_imm_rscalar_to_r( _opname, _imm, _src, _dstsuffix )       \
+      DO_imm_mscalar_to_r( _opname, _imm, _src )
+
+
+
+
+
+void test_BLENDPD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_imm_mandr_r("blendpd", 0, src, dst);
+      DO_imm_mandr_r("blendpd", 1, src, dst);
+      DO_imm_mandr_r("blendpd", 2, src, dst);
+      DO_imm_mandr_r("blendpd", 3, src, dst);
+   }
+}
+
+void test_BLENDPS ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_imm_mandr_r("blendps", 0, src, dst);
+      DO_imm_mandr_r("blendps", 1, src, dst);
+      DO_imm_mandr_r("blendps", 2, src, dst);
+      DO_imm_mandr_r("blendps", 3, src, dst);
+      DO_imm_mandr_r("blendps", 4, src, dst);
+      DO_imm_mandr_r("blendps", 5, src, dst);
+      DO_imm_mandr_r("blendps", 6, src, dst);
+      DO_imm_mandr_r("blendps", 7, src, dst);
+      DO_imm_mandr_r("blendps", 8, src, dst);
+      DO_imm_mandr_r("blendps", 9, src, dst);
+      DO_imm_mandr_r("blendps", 10, src, dst);
+      DO_imm_mandr_r("blendps", 11, src, dst);
+      DO_imm_mandr_r("blendps", 12, src, dst);
+      DO_imm_mandr_r("blendps", 13, src, dst);
+      DO_imm_mandr_r("blendps", 14, src, dst);
+      DO_imm_mandr_r("blendps", 15, src, dst);
+   }
+}
+
+void test_DPPD ( void )
+{
+   V128 src, dst;
+   {
+      *(double*)(&src[0]) =  1.2345;
+      *(double*)(&src[8]) = -6.78910;
+      *(double*)(&dst[0]) = -11.121314;
+      *(double*)(&dst[8]) =  15.161718;
+      DO_imm_mandr_r("dppd", 0, src, dst);
+      DO_imm_mandr_r("dppd", 1, src, dst);
+      DO_imm_mandr_r("dppd", 2, src, dst);
+      DO_imm_mandr_r("dppd", 3, src, dst);
+      DO_imm_mandr_r("dppd", 4, src, dst);
+      DO_imm_mandr_r("dppd", 5, src, dst);
+      DO_imm_mandr_r("dppd", 6, src, dst);
+      DO_imm_mandr_r("dppd", 7, src, dst);
+      DO_imm_mandr_r("dppd", 8, src, dst);
+      DO_imm_mandr_r("dppd", 9, src, dst);
+      DO_imm_mandr_r("dppd", 10, src, dst);
+      DO_imm_mandr_r("dppd", 11, src, dst);
+      DO_imm_mandr_r("dppd", 12, src, dst);
+      DO_imm_mandr_r("dppd", 13, src, dst);
+      DO_imm_mandr_r("dppd", 14, src, dst);
+      DO_imm_mandr_r("dppd", 15, src, dst);
+      DO_imm_mandr_r("dppd", 16, src, dst);
+      DO_imm_mandr_r("dppd", 17, src, dst);
+      DO_imm_mandr_r("dppd", 18, src, dst);
+      DO_imm_mandr_r("dppd", 19, src, dst);
+      DO_imm_mandr_r("dppd", 20, src, dst);
+      DO_imm_mandr_r("dppd", 21, src, dst);
+      DO_imm_mandr_r("dppd", 22, src, dst);
+      DO_imm_mandr_r("dppd", 23, src, dst);
+      DO_imm_mandr_r("dppd", 24, src, dst);
+      DO_imm_mandr_r("dppd", 25, src, dst);
+      DO_imm_mandr_r("dppd", 26, src, dst);
+      DO_imm_mandr_r("dppd", 27, src, dst);
+      DO_imm_mandr_r("dppd", 28, src, dst);
+      DO_imm_mandr_r("dppd", 29, src, dst);
+      DO_imm_mandr_r("dppd", 30, src, dst);
+      DO_imm_mandr_r("dppd", 31, src, dst);
+      DO_imm_mandr_r("dppd", 32, src, dst);
+      DO_imm_mandr_r("dppd", 33, src, dst);
+      DO_imm_mandr_r("dppd", 34, src, dst);
+      DO_imm_mandr_r("dppd", 35, src, dst);
+      DO_imm_mandr_r("dppd", 36, src, dst);
+      DO_imm_mandr_r("dppd", 37, src, dst);
+      DO_imm_mandr_r("dppd", 38, src, dst);
+      DO_imm_mandr_r("dppd", 39, src, dst);
+      DO_imm_mandr_r("dppd", 40, src, dst);
+      DO_imm_mandr_r("dppd", 41, src, dst);
+      DO_imm_mandr_r("dppd", 42, src, dst);
+      DO_imm_mandr_r("dppd", 43, src, dst);
+      DO_imm_mandr_r("dppd", 44, src, dst);
+      DO_imm_mandr_r("dppd", 45, src, dst);
+      DO_imm_mandr_r("dppd", 46, src, dst);
+      DO_imm_mandr_r("dppd", 47, src, dst);
+      DO_imm_mandr_r("dppd", 48, src, dst);
+      DO_imm_mandr_r("dppd", 49, src, dst);
+      DO_imm_mandr_r("dppd", 50, src, dst);
+      DO_imm_mandr_r("dppd", 51, src, dst);
+      DO_imm_mandr_r("dppd", 52, src, dst);
+      DO_imm_mandr_r("dppd", 53, src, dst);
+      DO_imm_mandr_r("dppd", 54, src, dst);
+      DO_imm_mandr_r("dppd", 55, src, dst);
+      DO_imm_mandr_r("dppd", 56, src, dst);
+      DO_imm_mandr_r("dppd", 57, src, dst);
+      DO_imm_mandr_r("dppd", 58, src, dst);
+      DO_imm_mandr_r("dppd", 59, src, dst);
+      DO_imm_mandr_r("dppd", 60, src, dst);
+      DO_imm_mandr_r("dppd", 61, src, dst);
+      DO_imm_mandr_r("dppd", 62, src, dst);
+      DO_imm_mandr_r("dppd", 63, src, dst);
+      DO_imm_mandr_r("dppd", 64, src, dst);
+      DO_imm_mandr_r("dppd", 65, src, dst);
+      DO_imm_mandr_r("dppd", 66, src, dst);
+      DO_imm_mandr_r("dppd", 67, src, dst);
+      DO_imm_mandr_r("dppd", 68, src, dst);
+      DO_imm_mandr_r("dppd", 69, src, dst);
+      DO_imm_mandr_r("dppd", 70, src, dst);
+      DO_imm_mandr_r("dppd", 71, src, dst);
+      DO_imm_mandr_r("dppd", 72, src, dst);
+      DO_imm_mandr_r("dppd", 73, src, dst);
+      DO_imm_mandr_r("dppd", 74, src, dst);
+      DO_imm_mandr_r("dppd", 75, src, dst);
+      DO_imm_mandr_r("dppd", 76, src, dst);
+      DO_imm_mandr_r("dppd", 77, src, dst);
+      DO_imm_mandr_r("dppd", 78, src, dst);
+      DO_imm_mandr_r("dppd", 79, src, dst);
+      DO_imm_mandr_r("dppd", 80, src, dst);
+      DO_imm_mandr_r("dppd", 81, src, dst);
+      DO_imm_mandr_r("dppd", 82, src, dst);
+      DO_imm_mandr_r("dppd", 83, src, dst);
+      DO_imm_mandr_r("dppd", 84, src, dst);
+      DO_imm_mandr_r("dppd", 85, src, dst);
+      DO_imm_mandr_r("dppd", 86, src, dst);
+      DO_imm_mandr_r("dppd", 87, src, dst);
+      DO_imm_mandr_r("dppd", 88, src, dst);
+      DO_imm_mandr_r("dppd", 89, src, dst);
+      DO_imm_mandr_r("dppd", 90, src, dst);
+      DO_imm_mandr_r("dppd", 91, src, dst);
+      DO_imm_mandr_r("dppd", 92, src, dst);
+      DO_imm_mandr_r("dppd", 93, src, dst);
+      DO_imm_mandr_r("dppd", 94, src, dst);
+      DO_imm_mandr_r("dppd", 95, src, dst);
+      DO_imm_mandr_r("dppd", 96, src, dst);
+      DO_imm_mandr_r("dppd", 97, src, dst);
+      DO_imm_mandr_r("dppd", 98, src, dst);
+      DO_imm_mandr_r("dppd", 99, src, dst);
+      DO_imm_mandr_r("dppd", 100, src, dst);
+      DO_imm_mandr_r("dppd", 101, src, dst);
+      DO_imm_mandr_r("dppd", 102, src, dst);
+      DO_imm_mandr_r("dppd", 103, src, dst);
+      DO_imm_mandr_r("dppd", 104, src, dst);
+      DO_imm_mandr_r("dppd", 105, src, dst);
+      DO_imm_mandr_r("dppd", 106, src, dst);
+      DO_imm_mandr_r("dppd", 107, src, dst);
+      DO_imm_mandr_r("dppd", 108, src, dst);
+      DO_imm_mandr_r("dppd", 109, src, dst);
+      DO_imm_mandr_r("dppd", 110, src, dst);
+      DO_imm_mandr_r("dppd", 111, src, dst);
+      DO_imm_mandr_r("dppd", 112, src, dst);
+      DO_imm_mandr_r("dppd", 113, src, dst);
+      DO_imm_mandr_r("dppd", 114, src, dst);
+      DO_imm_mandr_r("dppd", 115, src, dst);
+      DO_imm_mandr_r("dppd", 116, src, dst);
+      DO_imm_mandr_r("dppd", 117, src, dst);
+      DO_imm_mandr_r("dppd", 118, src, dst);
+      DO_imm_mandr_r("dppd", 119, src, dst);
+      DO_imm_mandr_r("dppd", 120, src, dst);
+      DO_imm_mandr_r("dppd", 121, src, dst);
+      DO_imm_mandr_r("dppd", 122, src, dst);
+      DO_imm_mandr_r("dppd", 123, src, dst);
+      DO_imm_mandr_r("dppd", 124, src, dst);
+      DO_imm_mandr_r("dppd", 125, src, dst);
+      DO_imm_mandr_r("dppd", 126, src, dst);
+      DO_imm_mandr_r("dppd", 127, src, dst);
+      DO_imm_mandr_r("dppd", 128, src, dst);
+      DO_imm_mandr_r("dppd", 129, src, dst);
+      DO_imm_mandr_r("dppd", 130, src, dst);
+      DO_imm_mandr_r("dppd", 131, src, dst);
+      DO_imm_mandr_r("dppd", 132, src, dst);
+      DO_imm_mandr_r("dppd", 133, src, dst);
+      DO_imm_mandr_r("dppd", 134, src, dst);
+      DO_imm_mandr_r("dppd", 135, src, dst);
+      DO_imm_mandr_r("dppd", 136, src, dst);
+      DO_imm_mandr_r("dppd", 137, src, dst);
+      DO_imm_mandr_r("dppd", 138, src, dst);
+      DO_imm_mandr_r("dppd", 139, src, dst);
+      DO_imm_mandr_r("dppd", 140, src, dst);
+      DO_imm_mandr_r("dppd", 141, src, dst);
+      DO_imm_mandr_r("dppd", 142, src, dst);
+      DO_imm_mandr_r("dppd", 143, src, dst);
+      DO_imm_mandr_r("dppd", 144, src, dst);
+      DO_imm_mandr_r("dppd", 145, src, dst);
+      DO_imm_mandr_r("dppd", 146, src, dst);
+      DO_imm_mandr_r("dppd", 147, src, dst);
+      DO_imm_mandr_r("dppd", 148, src, dst);
+      DO_imm_mandr_r("dppd", 149, src, dst);
+      DO_imm_mandr_r("dppd", 150, src, dst);
+      DO_imm_mandr_r("dppd", 151, src, dst);
+      DO_imm_mandr_r("dppd", 152, src, dst);
+      DO_imm_mandr_r("dppd", 153, src, dst);
+      DO_imm_mandr_r("dppd", 154, src, dst);
+      DO_imm_mandr_r("dppd", 155, src, dst);
+      DO_imm_mandr_r("dppd", 156, src, dst);
+      DO_imm_mandr_r("dppd", 157, src, dst);
+      DO_imm_mandr_r("dppd", 158, src, dst);
+      DO_imm_mandr_r("dppd", 159, src, dst);
+      DO_imm_mandr_r("dppd", 160, src, dst);
+      DO_imm_mandr_r("dppd", 161, src, dst);
+      DO_imm_mandr_r("dppd", 162, src, dst);
+      DO_imm_mandr_r("dppd", 163, src, dst);
+      DO_imm_mandr_r("dppd", 164, src, dst);
+      DO_imm_mandr_r("dppd", 165, src, dst);
+      DO_imm_mandr_r("dppd", 166, src, dst);
+      DO_imm_mandr_r("dppd", 167, src, dst);
+      DO_imm_mandr_r("dppd", 168, src, dst);
+      DO_imm_mandr_r("dppd", 169, src, dst);
+      DO_imm_mandr_r("dppd", 170, src, dst);
+      DO_imm_mandr_r("dppd", 171, src, dst);
+      DO_imm_mandr_r("dppd", 172, src, dst);
+      DO_imm_mandr_r("dppd", 173, src, dst);
+      DO_imm_mandr_r("dppd", 174, src, dst);
+      DO_imm_mandr_r("dppd", 175, src, dst);
+      DO_imm_mandr_r("dppd", 176, src, dst);
+      DO_imm_mandr_r("dppd", 177, src, dst);
+      DO_imm_mandr_r("dppd", 178, src, dst);
+      DO_imm_mandr_r("dppd", 179, src, dst);
+      DO_imm_mandr_r("dppd", 180, src, dst);
+      DO_imm_mandr_r("dppd", 181, src, dst);
+      DO_imm_mandr_r("dppd", 182, src, dst);
+      DO_imm_mandr_r("dppd", 183, src, dst);
+      DO_imm_mandr_r("dppd", 184, src, dst);
+      DO_imm_mandr_r("dppd", 185, src, dst);
+      DO_imm_mandr_r("dppd", 186, src, dst);
+      DO_imm_mandr_r("dppd", 187, src, dst);
+      DO_imm_mandr_r("dppd", 188, src, dst);
+      DO_imm_mandr_r("dppd", 189, src, dst);
+      DO_imm_mandr_r("dppd", 190, src, dst);
+      DO_imm_mandr_r("dppd", 191, src, dst);
+      DO_imm_mandr_r("dppd", 192, src, dst);
+      DO_imm_mandr_r("dppd", 193, src, dst);
+      DO_imm_mandr_r("dppd", 194, src, dst);
+      DO_imm_mandr_r("dppd", 195, src, dst);
+      DO_imm_mandr_r("dppd", 196, src, dst);
+      DO_imm_mandr_r("dppd", 197, src, dst);
+      DO_imm_mandr_r("dppd", 198, src, dst);
+      DO_imm_mandr_r("dppd", 199, src, dst);
+      DO_imm_mandr_r("dppd", 200, src, dst);
+      DO_imm_mandr_r("dppd", 201, src, dst);
+      DO_imm_mandr_r("dppd", 202, src, dst);
+      DO_imm_mandr_r("dppd", 203, src, dst);
+      DO_imm_mandr_r("dppd", 204, src, dst);
+      DO_imm_mandr_r("dppd", 205, src, dst);
+      DO_imm_mandr_r("dppd", 206, src, dst);
+      DO_imm_mandr_r("dppd", 207, src, dst);
+      DO_imm_mandr_r("dppd", 208, src, dst);
+      DO_imm_mandr_r("dppd", 209, src, dst);
+      DO_imm_mandr_r("dppd", 210, src, dst);
+      DO_imm_mandr_r("dppd", 211, src, dst);
+      DO_imm_mandr_r("dppd", 212, src, dst);
+      DO_imm_mandr_r("dppd", 213, src, dst);
+      DO_imm_mandr_r("dppd", 214, src, dst);
+      DO_imm_mandr_r("dppd", 215, src, dst);
+      DO_imm_mandr_r("dppd", 216, src, dst);
+      DO_imm_mandr_r("dppd", 217, src, dst);
+      DO_imm_mandr_r("dppd", 218, src, dst);
+      DO_imm_mandr_r("dppd", 219, src, dst);
+      DO_imm_mandr_r("dppd", 220, src, dst);
+      DO_imm_mandr_r("dppd", 221, src, dst);
+      DO_imm_mandr_r("dppd", 222, src, dst);
+      DO_imm_mandr_r("dppd", 223, src, dst);
+      DO_imm_mandr_r("dppd", 224, src, dst);
+      DO_imm_mandr_r("dppd", 225, src, dst);
+      DO_imm_mandr_r("dppd", 226, src, dst);
+      DO_imm_mandr_r("dppd", 227, src, dst);
+      DO_imm_mandr_r("dppd", 228, src, dst);
+      DO_imm_mandr_r("dppd", 229, src, dst);
+      DO_imm_mandr_r("dppd", 230, src, dst);
+      DO_imm_mandr_r("dppd", 231, src, dst);
+      DO_imm_mandr_r("dppd", 232, src, dst);
+      DO_imm_mandr_r("dppd", 233, src, dst);
+      DO_imm_mandr_r("dppd", 234, src, dst);
+      DO_imm_mandr_r("dppd", 235, src, dst);
+      DO_imm_mandr_r("dppd", 236, src, dst);
+      DO_imm_mandr_r("dppd", 237, src, dst);
+      DO_imm_mandr_r("dppd", 238, src, dst);
+      DO_imm_mandr_r("dppd", 239, src, dst);
+      DO_imm_mandr_r("dppd", 240, src, dst);
+      DO_imm_mandr_r("dppd", 241, src, dst);
+      DO_imm_mandr_r("dppd", 242, src, dst);
+      DO_imm_mandr_r("dppd", 243, src, dst);
+      DO_imm_mandr_r("dppd", 244, src, dst);
+      DO_imm_mandr_r("dppd", 245, src, dst);
+      DO_imm_mandr_r("dppd", 246, src, dst);
+      DO_imm_mandr_r("dppd", 247, src, dst);
+      DO_imm_mandr_r("dppd", 248, src, dst);
+      DO_imm_mandr_r("dppd", 249, src, dst);
+      DO_imm_mandr_r("dppd", 250, src, dst);
+      DO_imm_mandr_r("dppd", 251, src, dst);
+      DO_imm_mandr_r("dppd", 252, src, dst);
+      DO_imm_mandr_r("dppd", 253, src, dst);
+      DO_imm_mandr_r("dppd", 254, src, dst);
+      DO_imm_mandr_r("dppd", 255, src, dst);
+   }
+}
+
+void test_DPPS ( void )
+{
+   V128 src, dst;
+   {
+      *(float*)(&src[0])  =   1.2;
+      *(float*)(&src[4])  =  -3.4;
+      *(float*)(&src[8])  =  -6.7;
+      *(float*)(&src[12]) =   8.9;
+      *(float*)(&dst[0])  = -10.11;
+      *(float*)(&dst[4])  =  12.13;
+      *(float*)(&dst[8])  =  14.15;
+      *(float*)(&dst[12]) = -16.17;
+      DO_imm_mandr_r("dpps", 0, src, dst);
+      DO_imm_mandr_r("dpps", 1, src, dst);
+      DO_imm_mandr_r("dpps", 2, src, dst);
+      DO_imm_mandr_r("dpps", 3, src, dst);
+      DO_imm_mandr_r("dpps", 4, src, dst);
+      DO_imm_mandr_r("dpps", 5, src, dst);
+      DO_imm_mandr_r("dpps", 6, src, dst);
+      DO_imm_mandr_r("dpps", 7, src, dst);
+      DO_imm_mandr_r("dpps", 8, src, dst);
+      DO_imm_mandr_r("dpps", 9, src, dst);
+      DO_imm_mandr_r("dpps", 10, src, dst);
+      DO_imm_mandr_r("dpps", 11, src, dst);
+      DO_imm_mandr_r("dpps", 12, src, dst);
+      DO_imm_mandr_r("dpps", 13, src, dst);
+      DO_imm_mandr_r("dpps", 14, src, dst);
+      DO_imm_mandr_r("dpps", 15, src, dst);
+      DO_imm_mandr_r("dpps", 16, src, dst);
+      DO_imm_mandr_r("dpps", 17, src, dst);
+      DO_imm_mandr_r("dpps", 18, src, dst);
+      DO_imm_mandr_r("dpps", 19, src, dst);
+      DO_imm_mandr_r("dpps", 20, src, dst);
+      DO_imm_mandr_r("dpps", 21, src, dst);
+      DO_imm_mandr_r("dpps", 22, src, dst);
+      DO_imm_mandr_r("dpps", 23, src, dst);
+      DO_imm_mandr_r("dpps", 24, src, dst);
+      DO_imm_mandr_r("dpps", 25, src, dst);
+      DO_imm_mandr_r("dpps", 26, src, dst);
+      DO_imm_mandr_r("dpps", 27, src, dst);
+      DO_imm_mandr_r("dpps", 28, src, dst);
+      DO_imm_mandr_r("dpps", 29, src, dst);
+      DO_imm_mandr_r("dpps", 30, src, dst);
+      DO_imm_mandr_r("dpps", 31, src, dst);
+      DO_imm_mandr_r("dpps", 32, src, dst);
+      DO_imm_mandr_r("dpps", 33, src, dst);
+      DO_imm_mandr_r("dpps", 34, src, dst);
+      DO_imm_mandr_r("dpps", 35, src, dst);
+      DO_imm_mandr_r("dpps", 36, src, dst);
+      DO_imm_mandr_r("dpps", 37, src, dst);
+      DO_imm_mandr_r("dpps", 38, src, dst);
+      DO_imm_mandr_r("dpps", 39, src, dst);
+      DO_imm_mandr_r("dpps", 40, src, dst);
+      DO_imm_mandr_r("dpps", 41, src, dst);
+      DO_imm_mandr_r("dpps", 42, src, dst);
+      DO_imm_mandr_r("dpps", 43, src, dst);
+      DO_imm_mandr_r("dpps", 44, src, dst);
+      DO_imm_mandr_r("dpps", 45, src, dst);
+      DO_imm_mandr_r("dpps", 46, src, dst);
+      DO_imm_mandr_r("dpps", 47, src, dst);
+      DO_imm_mandr_r("dpps", 48, src, dst);
+      DO_imm_mandr_r("dpps", 49, src, dst);
+      DO_imm_mandr_r("dpps", 50, src, dst);
+      DO_imm_mandr_r("dpps", 51, src, dst);
+      DO_imm_mandr_r("dpps", 52, src, dst);
+      DO_imm_mandr_r("dpps", 53, src, dst);
+      DO_imm_mandr_r("dpps", 54, src, dst);
+      DO_imm_mandr_r("dpps", 55, src, dst);
+      DO_imm_mandr_r("dpps", 56, src, dst);
+      DO_imm_mandr_r("dpps", 57, src, dst);
+      DO_imm_mandr_r("dpps", 58, src, dst);
+      DO_imm_mandr_r("dpps", 59, src, dst);
+      DO_imm_mandr_r("dpps", 60, src, dst);
+      DO_imm_mandr_r("dpps", 61, src, dst);
+      DO_imm_mandr_r("dpps", 62, src, dst);
+      DO_imm_mandr_r("dpps", 63, src, dst);
+      DO_imm_mandr_r("dpps", 64, src, dst);
+      DO_imm_mandr_r("dpps", 65, src, dst);
+      DO_imm_mandr_r("dpps", 66, src, dst);
+      DO_imm_mandr_r("dpps", 67, src, dst);
+      DO_imm_mandr_r("dpps", 68, src, dst);
+      DO_imm_mandr_r("dpps", 69, src, dst);
+      DO_imm_mandr_r("dpps", 70, src, dst);
+      DO_imm_mandr_r("dpps", 71, src, dst);
+      DO_imm_mandr_r("dpps", 72, src, dst);
+      DO_imm_mandr_r("dpps", 73, src, dst);
+      DO_imm_mandr_r("dpps", 74, src, dst);
+      DO_imm_mandr_r("dpps", 75, src, dst);
+      DO_imm_mandr_r("dpps", 76, src, dst);
+      DO_imm_mandr_r("dpps", 77, src, dst);
+      DO_imm_mandr_r("dpps", 78, src, dst);
+      DO_imm_mandr_r("dpps", 79, src, dst);
+      DO_imm_mandr_r("dpps", 80, src, dst);
+      DO_imm_mandr_r("dpps", 81, src, dst);
+      DO_imm_mandr_r("dpps", 82, src, dst);
+      DO_imm_mandr_r("dpps", 83, src, dst);
+      DO_imm_mandr_r("dpps", 84, src, dst);
+      DO_imm_mandr_r("dpps", 85, src, dst);
+      DO_imm_mandr_r("dpps", 86, src, dst);
+      DO_imm_mandr_r("dpps", 87, src, dst);
+      DO_imm_mandr_r("dpps", 88, src, dst);
+      DO_imm_mandr_r("dpps", 89, src, dst);
+      DO_imm_mandr_r("dpps", 90, src, dst);
+      DO_imm_mandr_r("dpps", 91, src, dst);
+      DO_imm_mandr_r("dpps", 92, src, dst);
+      DO_imm_mandr_r("dpps", 93, src, dst);
+      DO_imm_mandr_r("dpps", 94, src, dst);
+      DO_imm_mandr_r("dpps", 95, src, dst);
+      DO_imm_mandr_r("dpps", 96, src, dst);
+      DO_imm_mandr_r("dpps", 97, src, dst);
+      DO_imm_mandr_r("dpps", 98, src, dst);
+      DO_imm_mandr_r("dpps", 99, src, dst);
+      DO_imm_mandr_r("dpps", 100, src, dst);
+      DO_imm_mandr_r("dpps", 101, src, dst);
+      DO_imm_mandr_r("dpps", 102, src, dst);
+      DO_imm_mandr_r("dpps", 103, src, dst);
+      DO_imm_mandr_r("dpps", 104, src, dst);
+      DO_imm_mandr_r("dpps", 105, src, dst);
+      DO_imm_mandr_r("dpps", 106, src, dst);
+      DO_imm_mandr_r("dpps", 107, src, dst);
+      DO_imm_mandr_r("dpps", 108, src, dst);
+      DO_imm_mandr_r("dpps", 109, src, dst);
+      DO_imm_mandr_r("dpps", 110, src, dst);
+      DO_imm_mandr_r("dpps", 111, src, dst);
+      DO_imm_mandr_r("dpps", 112, src, dst);
+      DO_imm_mandr_r("dpps", 113, src, dst);
+      DO_imm_mandr_r("dpps", 114, src, dst);
+      DO_imm_mandr_r("dpps", 115, src, dst);
+      DO_imm_mandr_r("dpps", 116, src, dst);
+      DO_imm_mandr_r("dpps", 117, src, dst);
+      DO_imm_mandr_r("dpps", 118, src, dst);
+      DO_imm_mandr_r("dpps", 119, src, dst);
+      DO_imm_mandr_r("dpps", 120, src, dst);
+      DO_imm_mandr_r("dpps", 121, src, dst);
+      DO_imm_mandr_r("dpps", 122, src, dst);
+      DO_imm_mandr_r("dpps", 123, src, dst);
+      DO_imm_mandr_r("dpps", 124, src, dst);
+      DO_imm_mandr_r("dpps", 125, src, dst);
+      DO_imm_mandr_r("dpps", 126, src, dst);
+      DO_imm_mandr_r("dpps", 127, src, dst);
+      DO_imm_mandr_r("dpps", 128, src, dst);
+      DO_imm_mandr_r("dpps", 129, src, dst);
+      DO_imm_mandr_r("dpps", 130, src, dst);
+      DO_imm_mandr_r("dpps", 131, src, dst);
+      DO_imm_mandr_r("dpps", 132, src, dst);
+      DO_imm_mandr_r("dpps", 133, src, dst);
+      DO_imm_mandr_r("dpps", 134, src, dst);
+      DO_imm_mandr_r("dpps", 135, src, dst);
+      DO_imm_mandr_r("dpps", 136, src, dst);
+      DO_imm_mandr_r("dpps", 137, src, dst);
+      DO_imm_mandr_r("dpps", 138, src, dst);
+      DO_imm_mandr_r("dpps", 139, src, dst);
+      DO_imm_mandr_r("dpps", 140, src, dst);
+      DO_imm_mandr_r("dpps", 141, src, dst);
+      DO_imm_mandr_r("dpps", 142, src, dst);
+      DO_imm_mandr_r("dpps", 143, src, dst);
+      DO_imm_mandr_r("dpps", 144, src, dst);
+      DO_imm_mandr_r("dpps", 145, src, dst);
+      DO_imm_mandr_r("dpps", 146, src, dst);
+      DO_imm_mandr_r("dpps", 147, src, dst);
+      DO_imm_mandr_r("dpps", 148, src, dst);
+      DO_imm_mandr_r("dpps", 149, src, dst);
+      DO_imm_mandr_r("dpps", 150, src, dst);
+      DO_imm_mandr_r("dpps", 151, src, dst);
+      DO_imm_mandr_r("dpps", 152, src, dst);
+      DO_imm_mandr_r("dpps", 153, src, dst);
+      DO_imm_mandr_r("dpps", 154, src, dst);
+      DO_imm_mandr_r("dpps", 155, src, dst);
+      DO_imm_mandr_r("dpps", 156, src, dst);
+      DO_imm_mandr_r("dpps", 157, src, dst);
+      DO_imm_mandr_r("dpps", 158, src, dst);
+      DO_imm_mandr_r("dpps", 159, src, dst);
+      DO_imm_mandr_r("dpps", 160, src, dst);
+      DO_imm_mandr_r("dpps", 161, src, dst);
+      DO_imm_mandr_r("dpps", 162, src, dst);
+      DO_imm_mandr_r("dpps", 163, src, dst);
+      DO_imm_mandr_r("dpps", 164, src, dst);
+      DO_imm_mandr_r("dpps", 165, src, dst);
+      DO_imm_mandr_r("dpps", 166, src, dst);
+      DO_imm_mandr_r("dpps", 167, src, dst);
+      DO_imm_mandr_r("dpps", 168, src, dst);
+      DO_imm_mandr_r("dpps", 169, src, dst);
+      DO_imm_mandr_r("dpps", 170, src, dst);
+      DO_imm_mandr_r("dpps", 171, src, dst);
+      DO_imm_mandr_r("dpps", 172, src, dst);
+      DO_imm_mandr_r("dpps", 173, src, dst);
+      DO_imm_mandr_r("dpps", 174, src, dst);
+      DO_imm_mandr_r("dpps", 175, src, dst);
+      DO_imm_mandr_r("dpps", 176, src, dst);
+      DO_imm_mandr_r("dpps", 177, src, dst);
+      DO_imm_mandr_r("dpps", 178, src, dst);
+      DO_imm_mandr_r("dpps", 179, src, dst);
+      DO_imm_mandr_r("dpps", 180, src, dst);
+      DO_imm_mandr_r("dpps", 181, src, dst);
+      DO_imm_mandr_r("dpps", 182, src, dst);
+      DO_imm_mandr_r("dpps", 183, src, dst);
+      DO_imm_mandr_r("dpps", 184, src, dst);
+      DO_imm_mandr_r("dpps", 185, src, dst);
+      DO_imm_mandr_r("dpps", 186, src, dst);
+      DO_imm_mandr_r("dpps", 187, src, dst);
+      DO_imm_mandr_r("dpps", 188, src, dst);
+      DO_imm_mandr_r("dpps", 189, src, dst);
+      DO_imm_mandr_r("dpps", 190, src, dst);
+      DO_imm_mandr_r("dpps", 191, src, dst);
+      DO_imm_mandr_r("dpps", 192, src, dst);
+      DO_imm_mandr_r("dpps", 193, src, dst);
+      DO_imm_mandr_r("dpps", 194, src, dst);
+      DO_imm_mandr_r("dpps", 195, src, dst);
+      DO_imm_mandr_r("dpps", 196, src, dst);
+      DO_imm_mandr_r("dpps", 197, src, dst);
+      DO_imm_mandr_r("dpps", 198, src, dst);
+      DO_imm_mandr_r("dpps", 199, src, dst);
+      DO_imm_mandr_r("dpps", 200, src, dst);
+      DO_imm_mandr_r("dpps", 201, src, dst);
+      DO_imm_mandr_r("dpps", 202, src, dst);
+      DO_imm_mandr_r("dpps", 203, src, dst);
+      DO_imm_mandr_r("dpps", 204, src, dst);
+      DO_imm_mandr_r("dpps", 205, src, dst);
+      DO_imm_mandr_r("dpps", 206, src, dst);
+      DO_imm_mandr_r("dpps", 207, src, dst);
+      DO_imm_mandr_r("dpps", 208, src, dst);
+      DO_imm_mandr_r("dpps", 209, src, dst);
+      DO_imm_mandr_r("dpps", 210, src, dst);
+      DO_imm_mandr_r("dpps", 211, src, dst);
+      DO_imm_mandr_r("dpps", 212, src, dst);
+      DO_imm_mandr_r("dpps", 213, src, dst);
+      DO_imm_mandr_r("dpps", 214, src, dst);
+      DO_imm_mandr_r("dpps", 215, src, dst);
+      DO_imm_mandr_r("dpps", 216, src, dst);
+      DO_imm_mandr_r("dpps", 217, src, dst);
+      DO_imm_mandr_r("dpps", 218, src, dst);
+      DO_imm_mandr_r("dpps", 219, src, dst);
+      DO_imm_mandr_r("dpps", 220, src, dst);
+      DO_imm_mandr_r("dpps", 221, src, dst);
+      DO_imm_mandr_r("dpps", 222, src, dst);
+      DO_imm_mandr_r("dpps", 223, src, dst);
+      DO_imm_mandr_r("dpps", 224, src, dst);
+      DO_imm_mandr_r("dpps", 225, src, dst);
+      DO_imm_mandr_r("dpps", 226, src, dst);
+      DO_imm_mandr_r("dpps", 227, src, dst);
+      DO_imm_mandr_r("dpps", 228, src, dst);
+      DO_imm_mandr_r("dpps", 229, src, dst);
+      DO_imm_mandr_r("dpps", 230, src, dst);
+      DO_imm_mandr_r("dpps", 231, src, dst);
+      DO_imm_mandr_r("dpps", 232, src, dst);
+      DO_imm_mandr_r("dpps", 233, src, dst);
+      DO_imm_mandr_r("dpps", 234, src, dst);
+      DO_imm_mandr_r("dpps", 235, src, dst);
+      DO_imm_mandr_r("dpps", 236, src, dst);
+      DO_imm_mandr_r("dpps", 237, src, dst);
+      DO_imm_mandr_r("dpps", 238, src, dst);
+      DO_imm_mandr_r("dpps", 239, src, dst);
+      DO_imm_mandr_r("dpps", 240, src, dst);
+      DO_imm_mandr_r("dpps", 241, src, dst);
+      DO_imm_mandr_r("dpps", 242, src, dst);
+      DO_imm_mandr_r("dpps", 243, src, dst);
+      DO_imm_mandr_r("dpps", 244, src, dst);
+      DO_imm_mandr_r("dpps", 245, src, dst);
+      DO_imm_mandr_r("dpps", 246, src, dst);
+      DO_imm_mandr_r("dpps", 247, src, dst);
+      DO_imm_mandr_r("dpps", 248, src, dst);
+      DO_imm_mandr_r("dpps", 249, src, dst);
+      DO_imm_mandr_r("dpps", 250, src, dst);
+      DO_imm_mandr_r("dpps", 251, src, dst);
+      DO_imm_mandr_r("dpps", 252, src, dst);
+      DO_imm_mandr_r("dpps", 253, src, dst);
+      DO_imm_mandr_r("dpps", 254, src, dst);
+      DO_imm_mandr_r("dpps", 255, src, dst);
+   }
+}
+
+void test_INSERTPS ( void )
+{
+   V128 src, dst;
+   {
+      *(float*)(&src[0])  =   1.2;
+      *(float*)(&src[4])  =  -3.4;
+      *(float*)(&src[8])  =  -6.7;
+      *(float*)(&src[12]) =   8.9;
+      *(float*)(&dst[0])  = -10.11;
+      *(float*)(&dst[4])  =  12.13;
+      *(float*)(&dst[8])  =  14.15;
+      *(float*)(&dst[12]) = -16.17;
+      DO_imm_mandr_r("insertps", 0, src, dst);
+      DO_imm_mandr_r("insertps", 1, src, dst);
+      DO_imm_mandr_r("insertps", 2, src, dst);
+      DO_imm_mandr_r("insertps", 3, src, dst);
+      DO_imm_mandr_r("insertps", 4, src, dst);
+      DO_imm_mandr_r("insertps", 5, src, dst);
+      DO_imm_mandr_r("insertps", 6, src, dst);
+      DO_imm_mandr_r("insertps", 7, src, dst);
+      DO_imm_mandr_r("insertps", 8, src, dst);
+      DO_imm_mandr_r("insertps", 9, src, dst);
+      DO_imm_mandr_r("insertps", 10, src, dst);
+      DO_imm_mandr_r("insertps", 11, src, dst);
+      DO_imm_mandr_r("insertps", 12, src, dst);
+      DO_imm_mandr_r("insertps", 13, src, dst);
+      DO_imm_mandr_r("insertps", 14, src, dst);
+      DO_imm_mandr_r("insertps", 15, src, dst);
+      DO_imm_mandr_r("insertps", 16, src, dst);
+      DO_imm_mandr_r("insertps", 17, src, dst);
+      DO_imm_mandr_r("insertps", 18, src, dst);
+      DO_imm_mandr_r("insertps", 19, src, dst);
+      DO_imm_mandr_r("insertps", 20, src, dst);
+      DO_imm_mandr_r("insertps", 21, src, dst);
+      DO_imm_mandr_r("insertps", 22, src, dst);
+      DO_imm_mandr_r("insertps", 23, src, dst);
+      DO_imm_mandr_r("insertps", 24, src, dst);
+      DO_imm_mandr_r("insertps", 25, src, dst);
+      DO_imm_mandr_r("insertps", 26, src, dst);
+      DO_imm_mandr_r("insertps", 27, src, dst);
+      DO_imm_mandr_r("insertps", 28, src, dst);
+      DO_imm_mandr_r("insertps", 29, src, dst);
+      DO_imm_mandr_r("insertps", 30, src, dst);
+      DO_imm_mandr_r("insertps", 31, src, dst);
+      DO_imm_mandr_r("insertps", 32, src, dst);
+      DO_imm_mandr_r("insertps", 33, src, dst);
+      DO_imm_mandr_r("insertps", 34, src, dst);
+      DO_imm_mandr_r("insertps", 35, src, dst);
+      DO_imm_mandr_r("insertps", 36, src, dst);
+      DO_imm_mandr_r("insertps", 37, src, dst);
+      DO_imm_mandr_r("insertps", 38, src, dst);
+      DO_imm_mandr_r("insertps", 39, src, dst);
+      DO_imm_mandr_r("insertps", 40, src, dst);
+      DO_imm_mandr_r("insertps", 41, src, dst);
+      DO_imm_mandr_r("insertps", 42, src, dst);
+      DO_imm_mandr_r("insertps", 43, src, dst);
+      DO_imm_mandr_r("insertps", 44, src, dst);
+      DO_imm_mandr_r("insertps", 45, src, dst);
+      DO_imm_mandr_r("insertps", 46, src, dst);
+      DO_imm_mandr_r("insertps", 47, src, dst);
+      DO_imm_mandr_r("insertps", 48, src, dst);
+      DO_imm_mandr_r("insertps", 49, src, dst);
+      DO_imm_mandr_r("insertps", 50, src, dst);
+      DO_imm_mandr_r("insertps", 51, src, dst);
+      DO_imm_mandr_r("insertps", 52, src, dst);
+      DO_imm_mandr_r("insertps", 53, src, dst);
+      DO_imm_mandr_r("insertps", 54, src, dst);
+      DO_imm_mandr_r("insertps", 55, src, dst);
+      DO_imm_mandr_r("insertps", 56, src, dst);
+      DO_imm_mandr_r("insertps", 57, src, dst);
+      DO_imm_mandr_r("insertps", 58, src, dst);
+      DO_imm_mandr_r("insertps", 59, src, dst);
+      DO_imm_mandr_r("insertps", 60, src, dst);
+      DO_imm_mandr_r("insertps", 61, src, dst);
+      DO_imm_mandr_r("insertps", 62, src, dst);
+      DO_imm_mandr_r("insertps", 63, src, dst);
+      DO_imm_mandr_r("insertps", 64, src, dst);
+      DO_imm_mandr_r("insertps", 65, src, dst);
+      DO_imm_mandr_r("insertps", 66, src, dst);
+      DO_imm_mandr_r("insertps", 67, src, dst);
+      DO_imm_mandr_r("insertps", 68, src, dst);
+      DO_imm_mandr_r("insertps", 69, src, dst);
+      DO_imm_mandr_r("insertps", 70, src, dst);
+      DO_imm_mandr_r("insertps", 71, src, dst);
+      DO_imm_mandr_r("insertps", 72, src, dst);
+      DO_imm_mandr_r("insertps", 73, src, dst);
+      DO_imm_mandr_r("insertps", 74, src, dst);
+      DO_imm_mandr_r("insertps", 75, src, dst);
+      DO_imm_mandr_r("insertps", 76, src, dst);
+      DO_imm_mandr_r("insertps", 77, src, dst);
+      DO_imm_mandr_r("insertps", 78, src, dst);
+      DO_imm_mandr_r("insertps", 79, src, dst);
+      DO_imm_mandr_r("insertps", 80, src, dst);
+      DO_imm_mandr_r("insertps", 81, src, dst);
+      DO_imm_mandr_r("insertps", 82, src, dst);
+      DO_imm_mandr_r("insertps", 83, src, dst);
+      DO_imm_mandr_r("insertps", 84, src, dst);
+      DO_imm_mandr_r("insertps", 85, src, dst);
+      DO_imm_mandr_r("insertps", 86, src, dst);
+      DO_imm_mandr_r("insertps", 87, src, dst);
+      DO_imm_mandr_r("insertps", 88, src, dst);
+      DO_imm_mandr_r("insertps", 89, src, dst);
+      DO_imm_mandr_r("insertps", 90, src, dst);
+      DO_imm_mandr_r("insertps", 91, src, dst);
+      DO_imm_mandr_r("insertps", 92, src, dst);
+      DO_imm_mandr_r("insertps", 93, src, dst);
+      DO_imm_mandr_r("insertps", 94, src, dst);
+      DO_imm_mandr_r("insertps", 95, src, dst);
+      DO_imm_mandr_r("insertps", 96, src, dst);
+      DO_imm_mandr_r("insertps", 97, src, dst);
+      DO_imm_mandr_r("insertps", 98, src, dst);
+      DO_imm_mandr_r("insertps", 99, src, dst);
+      DO_imm_mandr_r("insertps", 100, src, dst);
+      DO_imm_mandr_r("insertps", 101, src, dst);
+      DO_imm_mandr_r("insertps", 102, src, dst);
+      DO_imm_mandr_r("insertps", 103, src, dst);
+      DO_imm_mandr_r("insertps", 104, src, dst);
+      DO_imm_mandr_r("insertps", 105, src, dst);
+      DO_imm_mandr_r("insertps", 106, src, dst);
+      DO_imm_mandr_r("insertps", 107, src, dst);
+      DO_imm_mandr_r("insertps", 108, src, dst);
+      DO_imm_mandr_r("insertps", 109, src, dst);
+      DO_imm_mandr_r("insertps", 110, src, dst);
+      DO_imm_mandr_r("insertps", 111, src, dst);
+      DO_imm_mandr_r("insertps", 112, src, dst);
+      DO_imm_mandr_r("insertps", 113, src, dst);
+      DO_imm_mandr_r("insertps", 114, src, dst);
+      DO_imm_mandr_r("insertps", 115, src, dst);
+      DO_imm_mandr_r("insertps", 116, src, dst);
+      DO_imm_mandr_r("insertps", 117, src, dst);
+      DO_imm_mandr_r("insertps", 118, src, dst);
+      DO_imm_mandr_r("insertps", 119, src, dst);
+      DO_imm_mandr_r("insertps", 120, src, dst);
+      DO_imm_mandr_r("insertps", 121, src, dst);
+      DO_imm_mandr_r("insertps", 122, src, dst);
+      DO_imm_mandr_r("insertps", 123, src, dst);
+      DO_imm_mandr_r("insertps", 124, src, dst);
+      DO_imm_mandr_r("insertps", 125, src, dst);
+      DO_imm_mandr_r("insertps", 126, src, dst);
+      DO_imm_mandr_r("insertps", 127, src, dst);
+      DO_imm_mandr_r("insertps", 128, src, dst);
+      DO_imm_mandr_r("insertps", 129, src, dst);
+      DO_imm_mandr_r("insertps", 130, src, dst);
+      DO_imm_mandr_r("insertps", 131, src, dst);
+      DO_imm_mandr_r("insertps", 132, src, dst);
+      DO_imm_mandr_r("insertps", 133, src, dst);
+      DO_imm_mandr_r("insertps", 134, src, dst);
+      DO_imm_mandr_r("insertps", 135, src, dst);
+      DO_imm_mandr_r("insertps", 136, src, dst);
+      DO_imm_mandr_r("insertps", 137, src, dst);
+      DO_imm_mandr_r("insertps", 138, src, dst);
+      DO_imm_mandr_r("insertps", 139, src, dst);
+      DO_imm_mandr_r("insertps", 140, src, dst);
+      DO_imm_mandr_r("insertps", 141, src, dst);
+      DO_imm_mandr_r("insertps", 142, src, dst);
+      DO_imm_mandr_r("insertps", 143, src, dst);
+      DO_imm_mandr_r("insertps", 144, src, dst);
+      DO_imm_mandr_r("insertps", 145, src, dst);
+      DO_imm_mandr_r("insertps", 146, src, dst);
+      DO_imm_mandr_r("insertps", 147, src, dst);
+      DO_imm_mandr_r("insertps", 148, src, dst);
+      DO_imm_mandr_r("insertps", 149, src, dst);
+      DO_imm_mandr_r("insertps", 150, src, dst);
+      DO_imm_mandr_r("insertps", 151, src, dst);
+      DO_imm_mandr_r("insertps", 152, src, dst);
+      DO_imm_mandr_r("insertps", 153, src, dst);
+      DO_imm_mandr_r("insertps", 154, src, dst);
+      DO_imm_mandr_r("insertps", 155, src, dst);
+      DO_imm_mandr_r("insertps", 156, src, dst);
+      DO_imm_mandr_r("insertps", 157, src, dst);
+      DO_imm_mandr_r("insertps", 158, src, dst);
+      DO_imm_mandr_r("insertps", 159, src, dst);
+      DO_imm_mandr_r("insertps", 160, src, dst);
+      DO_imm_mandr_r("insertps", 161, src, dst);
+      DO_imm_mandr_r("insertps", 162, src, dst);
+      DO_imm_mandr_r("insertps", 163, src, dst);
+      DO_imm_mandr_r("insertps", 164, src, dst);
+      DO_imm_mandr_r("insertps", 165, src, dst);
+      DO_imm_mandr_r("insertps", 166, src, dst);
+      DO_imm_mandr_r("insertps", 167, src, dst);
+      DO_imm_mandr_r("insertps", 168, src, dst);
+      DO_imm_mandr_r("insertps", 169, src, dst);
+      DO_imm_mandr_r("insertps", 170, src, dst);
+      DO_imm_mandr_r("insertps", 171, src, dst);
+      DO_imm_mandr_r("insertps", 172, src, dst);
+      DO_imm_mandr_r("insertps", 173, src, dst);
+      DO_imm_mandr_r("insertps", 174, src, dst);
+      DO_imm_mandr_r("insertps", 175, src, dst);
+      DO_imm_mandr_r("insertps", 176, src, dst);
+      DO_imm_mandr_r("insertps", 177, src, dst);
+      DO_imm_mandr_r("insertps", 178, src, dst);
+      DO_imm_mandr_r("insertps", 179, src, dst);
+      DO_imm_mandr_r("insertps", 180, src, dst);
+      DO_imm_mandr_r("insertps", 181, src, dst);
+      DO_imm_mandr_r("insertps", 182, src, dst);
+      DO_imm_mandr_r("insertps", 183, src, dst);
+      DO_imm_mandr_r("insertps", 184, src, dst);
+      DO_imm_mandr_r("insertps", 185, src, dst);
+      DO_imm_mandr_r("insertps", 186, src, dst);
+      DO_imm_mandr_r("insertps", 187, src, dst);
+      DO_imm_mandr_r("insertps", 188, src, dst);
+      DO_imm_mandr_r("insertps", 189, src, dst);
+      DO_imm_mandr_r("insertps", 190, src, dst);
+      DO_imm_mandr_r("insertps", 191, src, dst);
+      DO_imm_mandr_r("insertps", 192, src, dst);
+      DO_imm_mandr_r("insertps", 193, src, dst);
+      DO_imm_mandr_r("insertps", 194, src, dst);
+      DO_imm_mandr_r("insertps", 195, src, dst);
+      DO_imm_mandr_r("insertps", 196, src, dst);
+      DO_imm_mandr_r("insertps", 197, src, dst);
+      DO_imm_mandr_r("insertps", 198, src, dst);
+      DO_imm_mandr_r("insertps", 199, src, dst);
+      DO_imm_mandr_r("insertps", 200, src, dst);
+      DO_imm_mandr_r("insertps", 201, src, dst);
+      DO_imm_mandr_r("insertps", 202, src, dst);
+      DO_imm_mandr_r("insertps", 203, src, dst);
+      DO_imm_mandr_r("insertps", 204, src, dst);
+      DO_imm_mandr_r("insertps", 205, src, dst);
+      DO_imm_mandr_r("insertps", 206, src, dst);
+      DO_imm_mandr_r("insertps", 207, src, dst);
+      DO_imm_mandr_r("insertps", 208, src, dst);
+      DO_imm_mandr_r("insertps", 209, src, dst);
+      DO_imm_mandr_r("insertps", 210, src, dst);
+      DO_imm_mandr_r("insertps", 211, src, dst);
+      DO_imm_mandr_r("insertps", 212, src, dst);
+      DO_imm_mandr_r("insertps", 213, src, dst);
+      DO_imm_mandr_r("insertps", 214, src, dst);
+      DO_imm_mandr_r("insertps", 215, src, dst);
+      DO_imm_mandr_r("insertps", 216, src, dst);
+      DO_imm_mandr_r("insertps", 217, src, dst);
+      DO_imm_mandr_r("insertps", 218, src, dst);
+      DO_imm_mandr_r("insertps", 219, src, dst);
+      DO_imm_mandr_r("insertps", 220, src, dst);
+      DO_imm_mandr_r("insertps", 221, src, dst);
+      DO_imm_mandr_r("insertps", 222, src, dst);
+      DO_imm_mandr_r("insertps", 223, src, dst);
+      DO_imm_mandr_r("insertps", 224, src, dst);
+      DO_imm_mandr_r("insertps", 225, src, dst);
+      DO_imm_mandr_r("insertps", 226, src, dst);
+      DO_imm_mandr_r("insertps", 227, src, dst);
+      DO_imm_mandr_r("insertps", 228, src, dst);
+      DO_imm_mandr_r("insertps", 229, src, dst);
+      DO_imm_mandr_r("insertps", 230, src, dst);
+      DO_imm_mandr_r("insertps", 231, src, dst);
+      DO_imm_mandr_r("insertps", 232, src, dst);
+      DO_imm_mandr_r("insertps", 233, src, dst);
+      DO_imm_mandr_r("insertps", 234, src, dst);
+      DO_imm_mandr_r("insertps", 235, src, dst);
+      DO_imm_mandr_r("insertps", 236, src, dst);
+      DO_imm_mandr_r("insertps", 237, src, dst);
+      DO_imm_mandr_r("insertps", 238, src, dst);
+      DO_imm_mandr_r("insertps", 239, src, dst);
+      DO_imm_mandr_r("insertps", 240, src, dst);
+      DO_imm_mandr_r("insertps", 241, src, dst);
+      DO_imm_mandr_r("insertps", 242, src, dst);
+      DO_imm_mandr_r("insertps", 243, src, dst);
+      DO_imm_mandr_r("insertps", 244, src, dst);
+      DO_imm_mandr_r("insertps", 245, src, dst);
+      DO_imm_mandr_r("insertps", 246, src, dst);
+      DO_imm_mandr_r("insertps", 247, src, dst);
+      DO_imm_mandr_r("insertps", 248, src, dst);
+      DO_imm_mandr_r("insertps", 249, src, dst);
+      DO_imm_mandr_r("insertps", 250, src, dst);
+      DO_imm_mandr_r("insertps", 251, src, dst);
+      DO_imm_mandr_r("insertps", 252, src, dst);
+      DO_imm_mandr_r("insertps", 253, src, dst);
+      DO_imm_mandr_r("insertps", 254, src, dst);
+      DO_imm_mandr_r("insertps", 255, src, dst);
+   }
+}
+
+void test_MPSADBW ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_imm_mandr_r("mpsadbw", 0, src, dst);
+      DO_imm_mandr_r("mpsadbw", 1, src, dst);
+      DO_imm_mandr_r("mpsadbw", 2, src, dst);
+      DO_imm_mandr_r("mpsadbw", 3, src, dst);
+      DO_imm_mandr_r("mpsadbw", 4, src, dst);
+      DO_imm_mandr_r("mpsadbw", 5, src, dst);
+      DO_imm_mandr_r("mpsadbw", 6, src, dst);
+      DO_imm_mandr_r("mpsadbw", 7, src, dst);
+   }
+}
+
+void test_PACKUSDW ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      if (i < 9) {
+         randV128(&src);
+         randV128(&dst);
+      } else {
+         memset(&src, 0, sizeof(src));
+         memset(&dst, 0, sizeof(src));
+         src[0] = 0x11; src[1] = 0x22;
+         src[4] = 0x33; src[5] = 0x44;
+         src[8] = 0x55; src[9] = 0x66;
+         src[12] = 0x77; src[13] = 0x88;
+         dst[0] = 0xaa; dst[1] = 0xbb;
+         dst[4] = 0xcc; dst[5] = 0xdd;
+         dst[8] = 0xee; dst[9] = 0xff;
+         dst[12] = 0xa1; dst[13] = 0xb2;
+      }
+      DO_mandr_r("packusdw", src, dst);
+   }
+}
+
+void test_PBLENDW ( void )
+{
+   V128 src, dst;
+   randV128(&src);
+   randV128(&dst);
+   {
+      DO_imm_mandr_r("pblendw", 0, src, dst);
+      DO_imm_mandr_r("pblendw", 1, src, dst);
+      DO_imm_mandr_r("pblendw", 2, src, dst);
+      DO_imm_mandr_r("pblendw", 3, src, dst);
+      DO_imm_mandr_r("pblendw", 4, src, dst);
+      DO_imm_mandr_r("pblendw", 5, src, dst);
+      DO_imm_mandr_r("pblendw", 6, src, dst);
+      DO_imm_mandr_r("pblendw", 7, src, dst);
+      DO_imm_mandr_r("pblendw", 8, src, dst);
+      DO_imm_mandr_r("pblendw", 9, src, dst);
+      DO_imm_mandr_r("pblendw", 10, src, dst);
+      DO_imm_mandr_r("pblendw", 11, src, dst);
+      DO_imm_mandr_r("pblendw", 12, src, dst);
+      DO_imm_mandr_r("pblendw", 13, src, dst);
+      DO_imm_mandr_r("pblendw", 14, src, dst);
+      DO_imm_mandr_r("pblendw", 15, src, dst);
+      DO_imm_mandr_r("pblendw", 16, src, dst);
+      DO_imm_mandr_r("pblendw", 17, src, dst);
+      DO_imm_mandr_r("pblendw", 18, src, dst);
+      DO_imm_mandr_r("pblendw", 19, src, dst);
+      DO_imm_mandr_r("pblendw", 20, src, dst);
+      DO_imm_mandr_r("pblendw", 21, src, dst);
+      DO_imm_mandr_r("pblendw", 22, src, dst);
+      DO_imm_mandr_r("pblendw", 23, src, dst);
+      DO_imm_mandr_r("pblendw", 24, src, dst);
+      DO_imm_mandr_r("pblendw", 25, src, dst);
+      DO_imm_mandr_r("pblendw", 26, src, dst);
+      DO_imm_mandr_r("pblendw", 27, src, dst);
+      DO_imm_mandr_r("pblendw", 28, src, dst);
+      DO_imm_mandr_r("pblendw", 29, src, dst);
+      DO_imm_mandr_r("pblendw", 30, src, dst);
+      DO_imm_mandr_r("pblendw", 31, src, dst);
+      DO_imm_mandr_r("pblendw", 32, src, dst);
+      DO_imm_mandr_r("pblendw", 33, src, dst);
+      DO_imm_mandr_r("pblendw", 34, src, dst);
+      DO_imm_mandr_r("pblendw", 35, src, dst);
+      DO_imm_mandr_r("pblendw", 36, src, dst);
+      DO_imm_mandr_r("pblendw", 37, src, dst);
+      DO_imm_mandr_r("pblendw", 38, src, dst);
+      DO_imm_mandr_r("pblendw", 39, src, dst);
+      DO_imm_mandr_r("pblendw", 40, src, dst);
+      DO_imm_mandr_r("pblendw", 41, src, dst);
+      DO_imm_mandr_r("pblendw", 42, src, dst);
+      DO_imm_mandr_r("pblendw", 43, src, dst);
+      DO_imm_mandr_r("pblendw", 44, src, dst);
+      DO_imm_mandr_r("pblendw", 45, src, dst);
+      DO_imm_mandr_r("pblendw", 46, src, dst);
+      DO_imm_mandr_r("pblendw", 47, src, dst);
+      DO_imm_mandr_r("pblendw", 48, src, dst);
+      DO_imm_mandr_r("pblendw", 49, src, dst);
+      DO_imm_mandr_r("pblendw", 50, src, dst);
+      DO_imm_mandr_r("pblendw", 51, src, dst);
+      DO_imm_mandr_r("pblendw", 52, src, dst);
+      DO_imm_mandr_r("pblendw", 53, src, dst);
+      DO_imm_mandr_r("pblendw", 54, src, dst);
+      DO_imm_mandr_r("pblendw", 55, src, dst);
+      DO_imm_mandr_r("pblendw", 56, src, dst);
+      DO_imm_mandr_r("pblendw", 57, src, dst);
+      DO_imm_mandr_r("pblendw", 58, src, dst);
+      DO_imm_mandr_r("pblendw", 59, src, dst);
+      DO_imm_mandr_r("pblendw", 60, src, dst);
+      DO_imm_mandr_r("pblendw", 61, src, dst);
+      DO_imm_mandr_r("pblendw", 62, src, dst);
+      DO_imm_mandr_r("pblendw", 63, src, dst);
+      DO_imm_mandr_r("pblendw", 64, src, dst);
+      DO_imm_mandr_r("pblendw", 65, src, dst);
+      DO_imm_mandr_r("pblendw", 66, src, dst);
+      DO_imm_mandr_r("pblendw", 67, src, dst);
+      DO_imm_mandr_r("pblendw", 68, src, dst);
+      DO_imm_mandr_r("pblendw", 69, src, dst);
+      DO_imm_mandr_r("pblendw", 70, src, dst);
+      DO_imm_mandr_r("pblendw", 71, src, dst);
+      DO_imm_mandr_r("pblendw", 72, src, dst);
+      DO_imm_mandr_r("pblendw", 73, src, dst);
+      DO_imm_mandr_r("pblendw", 74, src, dst);
+      DO_imm_mandr_r("pblendw", 75, src, dst);
+      DO_imm_mandr_r("pblendw", 76, src, dst);
+      DO_imm_mandr_r("pblendw", 77, src, dst);
+      DO_imm_mandr_r("pblendw", 78, src, dst);
+      DO_imm_mandr_r("pblendw", 79, src, dst);
+      DO_imm_mandr_r("pblendw", 80, src, dst);
+      DO_imm_mandr_r("pblendw", 81, src, dst);
+      DO_imm_mandr_r("pblendw", 82, src, dst);
+      DO_imm_mandr_r("pblendw", 83, src, dst);
+      DO_imm_mandr_r("pblendw", 84, src, dst);
+      DO_imm_mandr_r("pblendw", 85, src, dst);
+      DO_imm_mandr_r("pblendw", 86, src, dst);
+      DO_imm_mandr_r("pblendw", 87, src, dst);
+      DO_imm_mandr_r("pblendw", 88, src, dst);
+      DO_imm_mandr_r("pblendw", 89, src, dst);
+      DO_imm_mandr_r("pblendw", 90, src, dst);
+      DO_imm_mandr_r("pblendw", 91, src, dst);
+      DO_imm_mandr_r("pblendw", 92, src, dst);
+      DO_imm_mandr_r("pblendw", 93, src, dst);
+      DO_imm_mandr_r("pblendw", 94, src, dst);
+      DO_imm_mandr_r("pblendw", 95, src, dst);
+      DO_imm_mandr_r("pblendw", 96, src, dst);
+      DO_imm_mandr_r("pblendw", 97, src, dst);
+      DO_imm_mandr_r("pblendw", 98, src, dst);
+      DO_imm_mandr_r("pblendw", 99, src, dst);
+      DO_imm_mandr_r("pblendw", 100, src, dst);
+      DO_imm_mandr_r("pblendw", 101, src, dst);
+      DO_imm_mandr_r("pblendw", 102, src, dst);
+      DO_imm_mandr_r("pblendw", 103, src, dst);
+      DO_imm_mandr_r("pblendw", 104, src, dst);
+      DO_imm_mandr_r("pblendw", 105, src, dst);
+      DO_imm_mandr_r("pblendw", 106, src, dst);
+      DO_imm_mandr_r("pblendw", 107, src, dst);
+      DO_imm_mandr_r("pblendw", 108, src, dst);
+      DO_imm_mandr_r("pblendw", 109, src, dst);
+      DO_imm_mandr_r("pblendw", 110, src, dst);
+      DO_imm_mandr_r("pblendw", 111, src, dst);
+      DO_imm_mandr_r("pblendw", 112, src, dst);
+      DO_imm_mandr_r("pblendw", 113, src, dst);
+      DO_imm_mandr_r("pblendw", 114, src, dst);
+      DO_imm_mandr_r("pblendw", 115, src, dst);
+      DO_imm_mandr_r("pblendw", 116, src, dst);
+      DO_imm_mandr_r("pblendw", 117, src, dst);
+      DO_imm_mandr_r("pblendw", 118, src, dst);
+      DO_imm_mandr_r("pblendw", 119, src, dst);
+      DO_imm_mandr_r("pblendw", 120, src, dst);
+      DO_imm_mandr_r("pblendw", 121, src, dst);
+      DO_imm_mandr_r("pblendw", 122, src, dst);
+      DO_imm_mandr_r("pblendw", 123, src, dst);
+      DO_imm_mandr_r("pblendw", 124, src, dst);
+      DO_imm_mandr_r("pblendw", 125, src, dst);
+      DO_imm_mandr_r("pblendw", 126, src, dst);
+      DO_imm_mandr_r("pblendw", 127, src, dst);
+      DO_imm_mandr_r("pblendw", 128, src, dst);
+      DO_imm_mandr_r("pblendw", 129, src, dst);
+      DO_imm_mandr_r("pblendw", 130, src, dst);
+      DO_imm_mandr_r("pblendw", 131, src, dst);
+      DO_imm_mandr_r("pblendw", 132, src, dst);
+      DO_imm_mandr_r("pblendw", 133, src, dst);
+      DO_imm_mandr_r("pblendw", 134, src, dst);
+      DO_imm_mandr_r("pblendw", 135, src, dst);
+      DO_imm_mandr_r("pblendw", 136, src, dst);
+      DO_imm_mandr_r("pblendw", 137, src, dst);
+      DO_imm_mandr_r("pblendw", 138, src, dst);
+      DO_imm_mandr_r("pblendw", 139, src, dst);
+      DO_imm_mandr_r("pblendw", 140, src, dst);
+      DO_imm_mandr_r("pblendw", 141, src, dst);
+      DO_imm_mandr_r("pblendw", 142, src, dst);
+      DO_imm_mandr_r("pblendw", 143, src, dst);
+      DO_imm_mandr_r("pblendw", 144, src, dst);
+      DO_imm_mandr_r("pblendw", 145, src, dst);
+      DO_imm_mandr_r("pblendw", 146, src, dst);
+      DO_imm_mandr_r("pblendw", 147, src, dst);
+      DO_imm_mandr_r("pblendw", 148, src, dst);
+      DO_imm_mandr_r("pblendw", 149, src, dst);
+      DO_imm_mandr_r("pblendw", 150, src, dst);
+      DO_imm_mandr_r("pblendw", 151, src, dst);
+      DO_imm_mandr_r("pblendw", 152, src, dst);
+      DO_imm_mandr_r("pblendw", 153, src, dst);
+      DO_imm_mandr_r("pblendw", 154, src, dst);
+      DO_imm_mandr_r("pblendw", 155, src, dst);
+      DO_imm_mandr_r("pblendw", 156, src, dst);
+      DO_imm_mandr_r("pblendw", 157, src, dst);
+      DO_imm_mandr_r("pblendw", 158, src, dst);
+      DO_imm_mandr_r("pblendw", 159, src, dst);
+      DO_imm_mandr_r("pblendw", 160, src, dst);
+      DO_imm_mandr_r("pblendw", 161, src, dst);
+      DO_imm_mandr_r("pblendw", 162, src, dst);
+      DO_imm_mandr_r("pblendw", 163, src, dst);
+      DO_imm_mandr_r("pblendw", 164, src, dst);
+      DO_imm_mandr_r("pblendw", 165, src, dst);
+      DO_imm_mandr_r("pblendw", 166, src, dst);
+      DO_imm_mandr_r("pblendw", 167, src, dst);
+      DO_imm_mandr_r("pblendw", 168, src, dst);
+      DO_imm_mandr_r("pblendw", 169, src, dst);
+      DO_imm_mandr_r("pblendw", 170, src, dst);
+      DO_imm_mandr_r("pblendw", 171, src, dst);
+      DO_imm_mandr_r("pblendw", 172, src, dst);
+      DO_imm_mandr_r("pblendw", 173, src, dst);
+      DO_imm_mandr_r("pblendw", 174, src, dst);
+      DO_imm_mandr_r("pblendw", 175, src, dst);
+      DO_imm_mandr_r("pblendw", 176, src, dst);
+      DO_imm_mandr_r("pblendw", 177, src, dst);
+      DO_imm_mandr_r("pblendw", 178, src, dst);
+      DO_imm_mandr_r("pblendw", 179, src, dst);
+      DO_imm_mandr_r("pblendw", 180, src, dst);
+      DO_imm_mandr_r("pblendw", 181, src, dst);
+      DO_imm_mandr_r("pblendw", 182, src, dst);
+      DO_imm_mandr_r("pblendw", 183, src, dst);
+      DO_imm_mandr_r("pblendw", 184, src, dst);
+      DO_imm_mandr_r("pblendw", 185, src, dst);
+      DO_imm_mandr_r("pblendw", 186, src, dst);
+      DO_imm_mandr_r("pblendw", 187, src, dst);
+      DO_imm_mandr_r("pblendw", 188, src, dst);
+      DO_imm_mandr_r("pblendw", 189, src, dst);
+      DO_imm_mandr_r("pblendw", 190, src, dst);
+      DO_imm_mandr_r("pblendw", 191, src, dst);
+      DO_imm_mandr_r("pblendw", 192, src, dst);
+      DO_imm_mandr_r("pblendw", 193, src, dst);
+      DO_imm_mandr_r("pblendw", 194, src, dst);
+      DO_imm_mandr_r("pblendw", 195, src, dst);
+      DO_imm_mandr_r("pblendw", 196, src, dst);
+      DO_imm_mandr_r("pblendw", 197, src, dst);
+      DO_imm_mandr_r("pblendw", 198, src, dst);
+      DO_imm_mandr_r("pblendw", 199, src, dst);
+      DO_imm_mandr_r("pblendw", 200, src, dst);
+      DO_imm_mandr_r("pblendw", 201, src, dst);
+      DO_imm_mandr_r("pblendw", 202, src, dst);
+      DO_imm_mandr_r("pblendw", 203, src, dst);
+      DO_imm_mandr_r("pblendw", 204, src, dst);
+      DO_imm_mandr_r("pblendw", 205, src, dst);
+      DO_imm_mandr_r("pblendw", 206, src, dst);
+      DO_imm_mandr_r("pblendw", 207, src, dst);
+      DO_imm_mandr_r("pblendw", 208, src, dst);
+      DO_imm_mandr_r("pblendw", 209, src, dst);
+      DO_imm_mandr_r("pblendw", 210, src, dst);
+      DO_imm_mandr_r("pblendw", 211, src, dst);
+      DO_imm_mandr_r("pblendw", 212, src, dst);
+      DO_imm_mandr_r("pblendw", 213, src, dst);
+      DO_imm_mandr_r("pblendw", 214, src, dst);
+      DO_imm_mandr_r("pblendw", 215, src, dst);
+      DO_imm_mandr_r("pblendw", 216, src, dst);
+      DO_imm_mandr_r("pblendw", 217, src, dst);
+      DO_imm_mandr_r("pblendw", 218, src, dst);
+      DO_imm_mandr_r("pblendw", 219, src, dst);
+      DO_imm_mandr_r("pblendw", 220, src, dst);
+      DO_imm_mandr_r("pblendw", 221, src, dst);
+      DO_imm_mandr_r("pblendw", 222, src, dst);
+      DO_imm_mandr_r("pblendw", 223, src, dst);
+      DO_imm_mandr_r("pblendw", 224, src, dst);
+      DO_imm_mandr_r("pblendw", 225, src, dst);
+      DO_imm_mandr_r("pblendw", 226, src, dst);
+      DO_imm_mandr_r("pblendw", 227, src, dst);
+      DO_imm_mandr_r("pblendw", 228, src, dst);
+      DO_imm_mandr_r("pblendw", 229, src, dst);
+      DO_imm_mandr_r("pblendw", 230, src, dst);
+      DO_imm_mandr_r("pblendw", 231, src, dst);
+      DO_imm_mandr_r("pblendw", 232, src, dst);
+      DO_imm_mandr_r("pblendw", 233, src, dst);
+      DO_imm_mandr_r("pblendw", 234, src, dst);
+      DO_imm_mandr_r("pblendw", 235, src, dst);
+      DO_imm_mandr_r("pblendw", 236, src, dst);
+      DO_imm_mandr_r("pblendw", 237, src, dst);
+      DO_imm_mandr_r("pblendw", 238, src, dst);
+      DO_imm_mandr_r("pblendw", 239, src, dst);
+      DO_imm_mandr_r("pblendw", 240, src, dst);
+      DO_imm_mandr_r("pblendw", 241, src, dst);
+      DO_imm_mandr_r("pblendw", 242, src, dst);
+      DO_imm_mandr_r("pblendw", 243, src, dst);
+      DO_imm_mandr_r("pblendw", 244, src, dst);
+      DO_imm_mandr_r("pblendw", 245, src, dst);
+      DO_imm_mandr_r("pblendw", 246, src, dst);
+      DO_imm_mandr_r("pblendw", 247, src, dst);
+      DO_imm_mandr_r("pblendw", 248, src, dst);
+      DO_imm_mandr_r("pblendw", 249, src, dst);
+      DO_imm_mandr_r("pblendw", 250, src, dst);
+      DO_imm_mandr_r("pblendw", 251, src, dst);
+      DO_imm_mandr_r("pblendw", 252, src, dst);
+      DO_imm_mandr_r("pblendw", 253, src, dst);
+      DO_imm_mandr_r("pblendw", 254, src, dst);
+      DO_imm_mandr_r("pblendw", 255, src, dst);
+   }
+}
+
+
+void test_PCMPEQQ ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      switch (i - 6) {
+         case 0: memset(&src[0], 0x55, 8);
+                 memset(&dst[0], 0x55, 8); break;
+         case 1: memset(&src[8], 0x55, 8);
+                 memset(&dst[8], 0x55, 8); break;
+         default:
+            break;
+      }
+      DO_mandr_r("pcmpeqq", src, dst);
+   }
+}
+
+
+void test_PEXTRB ( void )
+{
+   V128 src;
+   randV128(&src);
+   DO_imm_r_to_mandrscalar("pextrb", 0, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 1, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 2, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 3, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 4, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 5, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 6, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 7, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 8, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 9, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 10, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 11, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 12, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 13, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 14, src, "d");
+   DO_imm_r_to_mandrscalar("pextrb", 15, src, "d");
+}
+
+void test_PINSRB ( void )
+{
+   ULong src;
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 0, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 1, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 2, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 3, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 4, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 5, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 6, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 7, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 8, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 9, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 10, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 11, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 12, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 13, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 14, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrb", 15, src, "d");
+}
+
+
+void test_PEXTRW ( void )
+{
+   V128 src;
+   randV128(&src);
+   DO_imm_r_to_mandrscalar("pextrw", 0, src, "d");
+   DO_imm_r_to_mandrscalar("pextrw", 1, src, "d");
+   DO_imm_r_to_mandrscalar("pextrw", 2, src, "d");
+   DO_imm_r_to_mandrscalar("pextrw", 3, src, "d");
+   DO_imm_r_to_mandrscalar("pextrw", 4, src, "d");
+   DO_imm_r_to_mandrscalar("pextrw", 5, src, "d");
+   DO_imm_r_to_mandrscalar("pextrw", 6, src, "d");
+   DO_imm_r_to_mandrscalar("pextrw", 7, src, "d");
+}
+
+void test_PINSRW ( void )
+{
+   ULong src;
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrw", 0, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrw", 1, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrw", 2, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrw", 3, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrw", 4, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrw", 5, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrw", 6, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrw", 7, src, "d");
+}
+
+
+void test_PEXTRD ( void )
+{
+   V128 src;
+   randV128(&src);
+   DO_imm_r_to_mandrscalar("pextrd", 0, src, "d");
+   DO_imm_r_to_mandrscalar("pextrd", 1, src, "d");
+   DO_imm_r_to_mandrscalar("pextrd", 2, src, "d");
+   DO_imm_r_to_mandrscalar("pextrd", 3, src, "d");
+}
+
+void test_PINSRD ( void )
+{
+   ULong src;
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrd", 0, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrd", 1, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrd", 2, src, "d");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrd", 3, src, "d");
+}
+
+
+void test_PEXTRQ ( void )
+{
+   V128 src;
+   randV128(&src);
+   DO_imm_r_to_mandrscalar("pextrq", 0, src, "");
+   DO_imm_r_to_mandrscalar("pextrq", 1, src, "");
+}
+
+void test_PINSRQ ( void )
+{
+   ULong src;
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrq", 0, src, "");
+   src = randULong();
+   DO_imm_mandrscalar_to_r("pinsrq", 1, src, "");
+}
+
+
+void test_PHMINPOSUW ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("phminposuw", src, dst);
+   }
+}
+
+void test_PMAXSB ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmaxsb", src, dst);
+   }
+}
+
+void test_PMAXSD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmaxsd", src, dst);
+   }
+}
+
+void test_PMAXUD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmaxud", src, dst);
+   }
+}
+
+void test_PMAXUW ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmaxuw", src, dst);
+   }
+}
+
+void test_PMINSB ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pminsb", src, dst);
+   }
+}
+
+void test_PMINSD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pminsd", src, dst);
+   }
+}
+
+void test_PMINUD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pminud", src, dst);
+   }
+}
+
+void test_PMINUW ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pminuw", src, dst);
+   }
+}
+
+void test_PMOVSXBW ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovsxbw", src, dst);
+   }
+}
+
+void test_PMOVSXBD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovsxbd", src, dst);
+   }
+}
+
+void test_PMOVSXBQ ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovsxbq", src, dst);
+   }
+}
+
+void test_PMOVSXWD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovsxwd", src, dst);
+   }
+}
+
+void test_PMOVSXWQ ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovsxwq", src, dst);
+   }
+}
+
+void test_PMOVSXDQ ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovsxdq", src, dst);
+   }
+}
+
+void test_PMOVZXBW ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovzxbw", src, dst);
+   }
+}
+
+void test_PMOVZXBD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovzxbd", src, dst);
+   }
+}
+
+void test_PMOVZXBQ ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovzxbq", src, dst);
+   }
+}
+
+void test_PMOVZXWD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovzxwd", src, dst);
+   }
+}
+
+void test_PMOVZXWQ ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovzxwq", src, dst);
+   }
+}
+
+void test_PMOVZXDQ ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmovzxdq", src, dst);
+   }
+}
+
+void test_PMULDQ ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmuldq", src, dst);
+   }
+}
+
+
+void test_PMULLD ( void )
+{
+   V128 src, dst;
+   Int i;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pmulld", src, dst);
+   }
+}
+
+
+void test_POPCNTQ ( void )
+{
+   ULong block[4];
+   Int i;
+   ULong oszacp_mask = 0x8D5;
+   for (i = 0; i < 10; i++) {
+      block[0] = i == 0 ? 0 : randULong();
+      block[1] = randULong();
+      block[2] = randULong();
+      block[3] = randULong();
+      __asm__ __volatile__(
+         "movq %0,       %%rax"  "\n\t"
+         "movq 0(%%rax), %%rdi"  "\n\t"
+         "movq 8(%%rax), %%r11"  "\n\t"
+         "popcntq %%rdi, %%r11"  "\n\t"
+         "movq %%r11, 16(%%rax)"  "\n\t"
+         "pushfq"                 "\n\t"
+         "popq %%r12"             "\n\t"
+         "movq %%r12, 24(%%rax)"  "\n"
+         : /*out*/
+         : /*in*/"r"(&block[0])
+         : /*trash*/ "cc", "memory", "rdi", "r11", "r12"
+      );
+      printf("r popcntq  %016llx %016llx  %016llx %016llx\n",
+             block[0], block[1], block[2], block[3] & oszacp_mask);
+
+      block[0] = i == 0 ? 0 : randULong();
+      block[1] = randULong();
+      block[2] = randULong();
+      block[3] = randULong();
+      __asm__ __volatile__(
+         "movq %0,       %%rax"  "\n\t"
+         "movq 8(%%rax), %%r11"  "\n\t"
+         "popcntq 0(%%rax), %%r11"  "\n\t"
+         "movq %%r11, 16(%%rax)"  "\n\t"
+         "pushfq"                 "\n\t"
+         "popq %%r12"             "\n\t"
+         "movq %%r12, 24(%%rax)"  "\n"
+         : /*out*/
+         : /*in*/"r"(&block[0])
+         : /*trash*/ "cc", "memory", "r11", "r12"
+      );
+      printf("m popcntq  %016llx %016llx  %016llx %016llx\n",
+             block[0], block[1], block[2], block[3] & oszacp_mask);
+   }
+}
+
+
+void test_POPCNTL ( void )
+{
+   ULong block[4];
+   Int i;
+   ULong oszacp_mask = 0x8D5;
+   for (i = 0; i < 10; i++) {
+      block[0] = i == 0 ? 0 : randULong();
+      block[1] = randULong();
+      block[2] = randULong();
+      block[3] = randULong();
+      __asm__ __volatile__(
+         "movq %0,       %%rax"  "\n\t"
+         "movq 0(%%rax), %%rdi"  "\n\t"
+         "movq 8(%%rax), %%r11"  "\n\t"
+         "popcntl %%edi, %%r11d"  "\n\t"
+         "movq %%r11, 16(%%rax)"  "\n\t"
+         "pushfq"                 "\n\t"
+         "popq %%r12"             "\n\t"
+         "movq %%r12, 24(%%rax)"  "\n"
+         : /*out*/
+         : /*in*/"r"(&block[0])
+         : /*trash*/ "cc", "memory", "rdi", "r11", "r12"
+      );
+      printf("r popcntl  %016llx %016llx  %016llx %016llx\n",
+             block[0], block[1], block[2], block[3] & oszacp_mask);
+
+      block[0] = i == 0 ? 0 : randULong();
+      block[1] = randULong();
+      block[2] = randULong();
+      block[3] = randULong();
+      __asm__ __volatile__(
+         "movq %0,       %%rax"  "\n\t"
+         "movq 8(%%rax), %%r11"  "\n\t"
+         "popcntl 0(%%rax), %%r11d"  "\n\t"
+         "movq %%r11, 16(%%rax)"  "\n\t"
+         "pushfq"                 "\n\t"
+         "popq %%r12"             "\n\t"
+         "movq %%r12, 24(%%rax)"  "\n"
+         : /*out*/
+         : /*in*/"r"(&block[0])
+         : /*trash*/ "cc", "memory", "r11", "r12"
+      );
+      printf("m popcntl  %016llx %016llx  %016llx %016llx\n",
+             block[0], block[1], block[2], block[3] & oszacp_mask);
+   }
+}
+
+
+void test_POPCNTW ( void )
+{
+   ULong block[4];
+   Int i;
+   ULong oszacp_mask = 0x8D5;
+   for (i = 0; i < 10; i++) {
+      block[0] = i == 0 ? 0 : randULong();
+      block[1] = randULong();
+      block[2] = randULong();
+      block[3] = randULong();
+      __asm__ __volatile__(
+         "movq %0,       %%rax"  "\n\t"
+         "movq 0(%%rax), %%rdi"  "\n\t"
+         "movq 8(%%rax), %%r11"  "\n\t"
+         "popcntw %%di,  %%r11w"  "\n\t"
+         "movq %%r11, 16(%%rax)"  "\n\t"
+         "pushfq"                 "\n\t"
+         "popq %%r12"             "\n\t"
+         "movq %%r12, 24(%%rax)"  "\n"
+         : /*out*/
+         : /*in*/"r"(&block[0])
+         : /*trash*/ "cc", "memory", "rdi", "r11", "r12"
+      );
+      printf("r popcntw  %016llx %016llx  %016llx %016llx\n",
+             block[0], block[1], block[2], block[3] & oszacp_mask);
+
+      block[0] = i == 0 ? 0 : randULong();
+      block[1] = randULong();
+      block[2] = randULong();
+      block[3] = randULong();
+      __asm__ __volatile__(
+         "movq %0,       %%rax"  "\n\t"
+         "movq 8(%%rax), %%r11"  "\n\t"
+         "popcntw 0(%%rax), %%r11w"  "\n\t"
+         "movq %%r11, 16(%%rax)"  "\n\t"
+         "pushfq"                 "\n\t"
+         "popq %%r12"             "\n\t"
+         "movq %%r12, 24(%%rax)"  "\n"
+         : /*out*/
+         : /*in*/"r"(&block[0])
+         : /*trash*/ "cc", "memory", "r11", "r12"
+      );
+      printf("m popcntw  %016llx %016llx  %016llx %016llx\n",
+             block[0], block[1], block[2], block[3] & oszacp_mask);
+   }
+}
+
+
+void test_PCMPGTQ ( void )
+{
+   V128 spec[7];
+   do64HLtoV128( &spec[0], 0x0000000000000000ULL, 0xffffffffffffffffULL );
+   do64HLtoV128( &spec[1], 0x0000000000000001ULL, 0xfffffffffffffffeULL );
+   do64HLtoV128( &spec[2], 0x7fffffffffffffffULL, 0x8000000000000001ULL );
+   do64HLtoV128( &spec[3], 0x8000000000000000ULL, 0x8000000000000000ULL );
+   do64HLtoV128( &spec[4], 0x8000000000000001ULL, 0x7fffffffffffffffULL );
+   do64HLtoV128( &spec[5], 0xfffffffffffffffeULL, 0x0000000000000001ULL );
+   do64HLtoV128( &spec[6], 0xffffffffffffffffULL, 0x0000000000000000ULL );
+
+   V128 src, dst;
+   Int i, j;
+   for (i = 0; i < 10; i++) {
+      randV128(&src);
+      randV128(&dst);
+      DO_mandr_r("pcmpgtq", src, dst);
+   }
+   for (i = 0; i < 7; i++) {
+      for (j = 0; j < 7; j++) {
+         memcpy(&src, &spec[i], 16);
+         memcpy(&dst, &spec[j], 16);
+         DO_mandr_r("pcmpgtq", src, dst);
+      }
+   }
+}
+
+/* ------------ ROUNDSD ------------ */
+
+void do_ROUNDSD_000 ( Bool mem, V128* src, /*OUT*/V128* dst )
+{
+   if (mem) {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"       "\n\t"
+         "roundsd $0, (%0), %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"       "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11"
+      );
+   } else {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"         "\n\t"
+         "movupd  (%0), %%xmm2"          "\n\t"
+         "roundsd $0, %%xmm2, %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"         "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11","xmm2"
+      );
+   }
+}
+
+void do_ROUNDSD_001 ( Bool mem, V128* src, /*OUT*/V128* dst )
+{
+   if (mem) {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"       "\n\t"
+         "roundsd $1, (%0), %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"       "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11"
+      );
+   } else {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"         "\n\t"
+         "movupd  (%0), %%xmm2"          "\n\t"
+         "roundsd $1, %%xmm2, %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"         "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11","xmm2"
+      );
+   }
+}
+
+void do_ROUNDSD_010 ( Bool mem, V128* src, /*OUT*/V128* dst )
+{
+   if (mem) {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"       "\n\t"
+         "roundsd $2, (%0), %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"       "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11"
+      );
+   } else {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"         "\n\t"
+         "movupd  (%0), %%xmm2"          "\n\t"
+         "roundsd $2, %%xmm2, %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"         "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11","xmm2"
+      );
+   }
+}
+
+void do_ROUNDSD_011 ( Bool mem, V128* src, /*OUT*/V128* dst )
+{
+   if (mem) {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"       "\n\t"
+         "roundsd $3, (%0), %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"       "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11"
+      );
+   } else {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"         "\n\t"
+         "movupd  (%0), %%xmm2"          "\n\t"
+         "roundsd $3, %%xmm2, %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"         "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11","xmm2"
+      );
+   }
+}
+
+
+void test_ROUNDSD_w_immediate_rounding ( void )
+{
+   double vals[22];
+   Int i = 0;
+   vals[i++] = 0.0;
+   vals[i++] = -0.0;
+   vals[i++] = mkPosInf();
+   vals[i++] = mkNegInf();
+   vals[i++] = mkPosNan();
+   vals[i++] = mkNegNan();
+   vals[i++] = -1.3;
+   vals[i++] = -1.1;
+   vals[i++] = -0.9;
+   vals[i++] = -0.7;
+   vals[i++] = -0.50001;
+   vals[i++] = -0.49999;
+   vals[i++] = -0.3;
+   vals[i++] = -0.1;
+   vals[i++] = 0.1;
+   vals[i++] = 0.3;
+   vals[i++] = 0.49999;
+   vals[i++] = 0.50001;
+   vals[i++] = 0.7;
+   vals[i++] = 0.9;
+   vals[i++] = 1.1;
+   vals[i++] = 1.3;
+   assert(i == 22);
+
+   for (i = 0; i < sizeof(vals)/sizeof(vals[0]); i++) {
+      V128 src, dst;
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 8);
+      do_ROUNDSD_000(False/*reg*/, &src, &dst);
+      printf("r roundsd_000  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", vals[i], *(double*)(&dst[0]));
+      printf("\n");
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 8);
+      do_ROUNDSD_000(True/*mem*/, &src, &dst);
+      printf("m roundsd_000  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", vals[i], *(double*)(&dst[0]));
+      printf("\n");
+
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 8);
+      do_ROUNDSD_001(False/*reg*/, &src, &dst);
+      printf("r roundsd_001  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", vals[i], *(double*)(&dst[0]));
+      printf("\n");
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 8);
+      do_ROUNDSD_001(True/*mem*/, &src, &dst);
+      printf("m roundsd_001  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", vals[i], *(double*)(&dst[0]));
+      printf("\n");
+
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 8);
+      do_ROUNDSD_010(False/*reg*/, &src, &dst);
+      printf("r roundsd_010  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", vals[i], *(double*)(&dst[0]));
+      printf("\n");
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 8);
+      do_ROUNDSD_010(True/*mem*/, &src, &dst);
+      printf("m roundsd_010  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", vals[i], *(double*)(&dst[0]));
+      printf("\n");
+
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 8);
+      do_ROUNDSD_011(False/*reg*/, &src, &dst);
+      printf("r roundsd_011  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", vals[i], *(double*)(&dst[0]));
+      printf("\n");
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 8);
+      do_ROUNDSD_011(True/*mem*/, &src, &dst);
+      printf("m roundsd_011  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", vals[i], *(double*)(&dst[0]));
+      printf("\n");
+   }
+}
+
+/* ------------ ROUNDSS ------------ */
+
+void do_ROUNDSS_000 ( Bool mem, V128* src, /*OUT*/V128* dst )
+{
+   if (mem) {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"       "\n\t"
+         "roundss $0, (%0), %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"       "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11"
+      );
+   } else {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"         "\n\t"
+         "movupd  (%0), %%xmm2"          "\n\t"
+         "roundss $0, %%xmm2, %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"         "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11","xmm2"
+      );
+   }
+}
+
+void do_ROUNDSS_001 ( Bool mem, V128* src, /*OUT*/V128* dst )
+{
+   if (mem) {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"       "\n\t"
+         "roundss $1, (%0), %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"       "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11"
+      );
+   } else {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"         "\n\t"
+         "movupd  (%0), %%xmm2"          "\n\t"
+         "roundss $1, %%xmm2, %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"         "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11","xmm2"
+      );
+   }
+}
+
+void do_ROUNDSS_010 ( Bool mem, V128* src, /*OUT*/V128* dst )
+{
+   if (mem) {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"       "\n\t"
+         "roundss $2, (%0), %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"       "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11"
+      );
+   } else {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"         "\n\t"
+         "movupd  (%0), %%xmm2"          "\n\t"
+         "roundss $2, %%xmm2, %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"         "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11","xmm2"
+      );
+   }
+}
+
+void do_ROUNDSS_011 ( Bool mem, V128* src, /*OUT*/V128* dst )
+{
+   if (mem) {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"       "\n\t"
+         "roundss $3, (%0), %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"       "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11"
+      );
+   } else {
+      __asm__ __volatile__(
+         "movupd  (%1), %%xmm11"         "\n\t"
+         "movupd  (%0), %%xmm2"          "\n\t"
+         "roundss $3, %%xmm2, %%xmm11"   "\n\t"
+         "movupd  %%xmm11, (%1)"         "\n"
+         : /*OUT*/
+         : /*IN*/ "r"(src), "r"(dst)
+         : /*TRASH*/ "xmm11","xmm2"
+      );
+   }
+}
+
+
+void test_ROUNDSS_w_immediate_rounding ( void )
+{
+   float vals[22];
+   Int i = 0;
+   vals[i++] = 0.0;
+   vals[i++] = -0.0;
+   vals[i++] = mkPosInf();
+   vals[i++] = mkNegInf();
+   vals[i++] = mkPosNan();
+   vals[i++] = mkNegNan();
+   vals[i++] = -1.3;
+   vals[i++] = -1.1;
+   vals[i++] = -0.9;
+   vals[i++] = -0.7;
+   vals[i++] = -0.50001;
+   vals[i++] = -0.49999;
+   vals[i++] = -0.3;
+   vals[i++] = -0.1;
+   vals[i++] = 0.1;
+   vals[i++] = 0.3;
+   vals[i++] = 0.49999;
+   vals[i++] = 0.50001;
+   vals[i++] = 0.7;
+   vals[i++] = 0.9;
+   vals[i++] = 1.1;
+   vals[i++] = 1.3;
+   assert(i == 22);
+
+   for (i = 0; i < sizeof(vals)/sizeof(vals[0]); i++) {
+      V128 src, dst;
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 4);
+      do_ROUNDSS_000(False/*reg*/, &src, &dst);
+      printf("r roundss_000  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", (double)vals[i], (double)*(float*)(&dst[0]));
+      printf("\n");
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 4);
+      do_ROUNDSS_000(True/*mem*/, &src, &dst);
+      printf("m roundss_000  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", (double)vals[i], (double)*(float*)(&dst[0]));
+      printf("\n");
+
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 4);
+      do_ROUNDSS_001(False/*reg*/, &src, &dst);
+      printf("r roundss_001  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", (double)vals[i], (double)*(float*)(&dst[0]));
+      printf("\n");
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 4);
+      do_ROUNDSS_001(True/*mem*/, &src, &dst);
+      printf("m roundss_001  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", (double)vals[i], (double)*(float*)(&dst[0]));
+      printf("\n");
+
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 4);
+      do_ROUNDSS_010(False/*reg*/, &src, &dst);
+      printf("r roundss_010  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", (double)vals[i], (double)*(float*)(&dst[0]));
+      printf("\n");
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 4);
+      do_ROUNDSS_010(True/*mem*/, &src, &dst);
+      printf("m roundss_010  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", (double)vals[i], (double)*(float*)(&dst[0]));
+      printf("\n");
+
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 4);
+      do_ROUNDSS_011(False/*reg*/, &src, &dst);
+      printf("r roundss_011  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", (double)vals[i], (double)*(float*)(&dst[0]));
+      printf("\n");
+
+      randV128(&src);
+      randV128(&dst);
+      memcpy(&src[0], &vals[i], 4);
+      do_ROUNDSS_011(True/*mem*/, &src, &dst);
+      printf("m roundss_011  ");
+      showV128(&src);
+      printf(" ");
+      showV128(&dst);
+      printf("  %10f %10f", (double)vals[i], (double)*(float*)(&dst[0]));
+      printf("\n");
+   }
+}
+
+void test_PTEST ( void )
+{
+   const Int ntests = 8;
+   V128 spec[ntests];
+   do64HLtoV128( &spec[0], 0x0000000000000000ULL, 0x0000000000000000ULL );
+   do64HLtoV128( &spec[1], 0x0000000000000000ULL, 0x0000000000000001ULL );
+   do64HLtoV128( &spec[2], 0x0000000000000001ULL, 0x0000000000000000ULL );
+   do64HLtoV128( &spec[3], 0x0000000000000001ULL, 0x0000000000000001ULL );
+   do64HLtoV128( &spec[4], 0xffffffffffffffffULL, 0xffffffffffffffffULL );
+   do64HLtoV128( &spec[5], 0xffffffffffffffffULL, 0xfffffffffffffffeULL );
+   do64HLtoV128( &spec[6], 0xfffffffffffffffeULL, 0xffffffffffffffffULL );
+   do64HLtoV128( &spec[7], 0xfffffffffffffffeULL, 0xfffffffffffffffeULL );
+   V128 block[2];
+   Int i, j;
+   ULong flags;
+   for (i = 0; i < ntests; i++) {
+      for (j = 0; j < ntests; j++) {
+         memcpy(&block[0], &spec[i], 16);
+         memcpy(&block[1], &spec[j], 16);
+         __asm__ __volatile__(
+            "subq $256, %%rsp"        "\n\t"
+            "movupd 0(%1), %%xmm2"    "\n\t"
+            "ptest 16(%1), %%xmm2"    "\n\t"
+            "pushfq"                  "\n\t"
+            "popq %0"                 "\n\t"
+            "addq $256, %%rsp"        "\n\t"
+            : /*out*/"=r"(flags) : /*in*/ "r"(&block[0]) :
+            "xmm2", "memory", "cc"
+         );
+         printf("r   ptest ");
+         showV128(&block[0]);
+         printf(" ");
+         showV128(&block[1]);
+         printf(" -> eflags %04x\n", (UInt)flags & 0x8D5);
+      }
+   }
+}
+
+int main ( int argc, char** argv )
+{
+#if 1
+   // ------ SSE 4.1 ------
+   test_BLENDPD();        // done Apr.01.2010
+   test_BLENDPS();        // done Apr.02.2010
+   //test_PBLENDW();
+   // BLENDVPD
+   // BLENDVPS
+   test_DPPD();           // done Apr.08.2010
+   test_DPPS();           // done Apr.09.2010
+   // EXTRACTPS
+   test_INSERTPS();       // done Apr.01.2010
+   // MOVNTDQA
+   //test_MPSADBW();
+   //test_PACKUSDW();
+   // PBLENDVB
+   //test_PCMPEQQ();
+   test_PEXTRB();         // done Apr.15.2010
+   test_PEXTRD();         // done Apr.14.2010
+   test_PEXTRQ();         // done Apr.14.2010
+   test_PEXTRW();         // done Apr.14.2010
+   test_PINSRQ();         // done Apr.16.2010
+   test_PINSRD();         // todo
+   //test_PINSRW();         // todo
+   test_PINSRB();         // todo
+   //test_PHMINPOSUW();
+   test_PMAXSB();
+   test_PMAXSD();         // done Apr.09.2010
+   test_PMAXUD();         // done Apr.16.2010
+   test_PMAXUW();
+   test_PMINSB();
+   test_PMINSD();         // done Apr.09.2010
+   test_PMINUD();
+   test_PMINUW();
+   test_PMOVSXBW();       // done Apr.02.2010
+   test_PMOVSXBD();       // done Mar.30.2010
+   test_PMOVSXBQ();       // done Mar.30.2010
+   test_PMOVSXWD();       // done Mar.31.2010
+   test_PMOVSXWQ();       // done Mar.31.2010
+   test_PMOVSXDQ();       // done Mar.31.2010
+   test_PMOVZXBW();       // done Mar.28.2010
+   test_PMOVZXBD();       // done Mar.29.2010
+   test_PMOVZXBQ();       // done Mar.29.2010
+   test_PMOVZXWD();       // done Mar.28.2010
+   test_PMOVZXWQ();       // done Mar.29.2010
+   test_PMOVZXDQ();       // done Mar.29.2010
+   test_POPCNTW();
+   test_POPCNTL();
+   test_POPCNTQ();
+   //test_PMULDQ();
+   test_PMULLD();
+   test_PTEST();
+   // ROUNDPD
+   // ROUNDPS
+   // ROUNDSD
+   // ROUNDSS
+   test_ROUNDSD_w_immediate_rounding();
+   test_ROUNDSS_w_immediate_rounding();
+   // ------ SSE 4.2 ------
+   test_PCMPGTQ();
+#else
+   test_PTEST();
+#endif
+
+   return 0;
+
+   //////////////////
+
+   Int sse1 = 0, sse2 = 0;
+
+   if (argc == 2 && 0==strcmp(argv[1], "sse1")) {
+      sse1 = 1;
+   }
+   else
+   if (argc == 2 && 0==strcmp(argv[1], "sse2")) {
+      sse2 = 1;
+   }
+   else
+   if (argc == 2 && 0==strcmp(argv[1], "all")) {
+      sse1 = sse2 = 1;
+   }
+   else {
+      fprintf(stderr, "usage: sse_memory [sse1|sse2|all]\n");
+      return 0;
+   }
+
+   return 0;   
+}
+

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.c
new file mode 100644 (file)
index 0000000..38d4f20
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.c
@@ -0,0 +1,51 @@
+
+#include "config.h"
+#include <stdio.h>
+#include <assert.h>
+
+/* Simple test program, no race.
+   Tests the 'xadd' exchange-and-add instruction with {r,r} operands, which is rarely generated by compilers. */
+
+#undef PLAT_x86_linux
+#undef PLAT_amd64_linux
+#undef PLAT_ppc32_linux
+#undef PLAT_ppc64_linux
+#undef PLAT_ppc32_aix5
+#undef PLAT_ppc64_aix5
+
+#if !defined(_AIX) && defined(__i386__)
+#  define PLAT_x86_linux 1
+#elif !defined(_AIX) && defined(__x86_64__)
+#  define PLAT_amd64_linux 1
+#endif
+
+
+#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux)
+#  define XADD_R_R(_addr,_lval) \
+       __asm__ __volatile__( \
+       "xadd %1, %0" \
+       : /*out*/ "=r"(_lval),"=r"(_addr) \
+       : /*in*/  "0"(_lval),"1"(_addr) \
+       : "flags" \
+       )
+#else
+#  error "Unsupported architecture"
+#endif
+
+int main ( void )
+{
+   long d = 20, s = 2;
+   long xadd_r_r_res;
+#define XADD_R_R_RES 42
+   
+   XADD_R_R(s, d);
+   xadd_r_r_res = s + d;
+   assert(xadd_r_r_res == XADD_R_R_RES);
+
+   if (xadd_r_r_res == XADD_R_R_RES)
+      printf("success\n");
+   else
+      printf("failure\n");
+
+   return xadd_r_r_res;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.stdout.exp
new file mode 100644 (file)
index 0000000..2e9ba47
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.stdout.exp
@@ -0,0 +1 @@
+success

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.vgtest
new file mode 100644 (file)
index 0000000..2cb1bee
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/amd64/xadd.vgtest
@@ -0,0 +1,2 @@
+prog: xadd
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/Makefile.am
index 6c713e56f1f7046de1bcde6ef619068245bdf4fd..a0a3eeadb5b69e7d79c28a4534c6a8226cab213c 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/Makefile.am
@@ -4,16 +4,35 @@ include $(top_srcdir)/Makefile.tool-tests.am
 dist_noinst_SCRIPTS = filter_stderr
 
 EXTRA_DIST = \
 dist_noinst_SCRIPTS = filter_stderr
 
 EXTRA_DIST = \

-       v6int.stdout.exp v6int.stderr.exp v6int.vgtest
+       neon128.stdout.exp neon128.stderr.exp neon128.vgtest \
+       neon64.stdout.exp neon64.stderr.exp neon64.vgtest \
+       v6intARM.stdout.exp v6intARM.stderr.exp v6intARM.vgtest \
+       v6intThumb.stdout.exp v6intThumb.stderr.exp v6intThumb.vgtest

 
 check_PROGRAMS = \
 
 check_PROGRAMS = \

-       v6int
+       neon128 \
+       neon64 \
+       v6intARM \
+       v6intThumb

 
 AM_CFLAGS    += @FLAG_M32@
 AM_CXXFLAGS  += @FLAG_M32@
 AM_CCASFLAGS += @FLAG_M32@
 
 
 AM_CFLAGS    += @FLAG_M32@
 AM_CXXFLAGS  += @FLAG_M32@
 AM_CCASFLAGS += @FLAG_M32@
 

-# need to specify cpu here because inline assembly in v6int.c
-# contains various v6 and v7 insns, which the assembler by
-# default rejects.
-v6int_CFLAGS   = $(AM_CFLAGS) -g -O -mcpu=cortex-a8
+# These two are specific to their ARM/Thumb respectively and so we
+# hardwire -marm/-mthumb.  neon64 and neon128 are compilable on both,
+# however, ask for them to be compiled on thumb, as that looks
+# like that's going to be the more common use case.  They also
+# need special helping w.r.t -mfpu and -mfloat-abi, though.
+# Also force -O0 since -O takes hundreds of MB of memory 
+# for v6intThumb.c.
+v6intARM_CFLAGS   = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -marm
+v6intThumb_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
+
+neon128_CFLAGS    = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+                       -mfpu=neon -mfloat-abi=softfp \
+                       -mthumb
+
+neon64_CFLAGS     = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+                       -mfpu=neon -mfloat-abi=softfp \
+                       -mthumb

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/Makefile.in
index 0fddd0e1855d8a9c5340008f3dce3ce3034a5b9b..3244100b4fb111432e461dee42ab6128099ab392 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/Makefile.in
@@ -46,7 +46,8 @@ host_triplet = @host@
 DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
        $(top_srcdir)/Makefile.tool-tests.am
 DIST_COMMON = $(dist_noinst_SCRIPTS) $(srcdir)/Makefile.am \
        $(srcdir)/Makefile.in $(top_srcdir)/Makefile.all.am \
        $(top_srcdir)/Makefile.tool-tests.am

-check_PROGRAMS = v6int$(EXEEXT)
+check_PROGRAMS = neon128$(EXEEXT) neon64$(EXEEXT) v6intARM$(EXEEXT) \
+       v6intThumb$(EXEEXT)

 subdir = none/tests/arm
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in
 subdir = none/tests/arm
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/configure.in


@@ -56,10 +57,25 @@ mkinstalldirs = $(install_sh) -d
 CONFIG_HEADER = $(top_builddir)/config.h
 CONFIG_CLEAN_FILES =
 CONFIG_CLEAN_VPATH_FILES =
 CONFIG_HEADER = $(top_builddir)/config.h
 CONFIG_CLEAN_FILES =
 CONFIG_CLEAN_VPATH_FILES =

-v6int_SOURCES = v6int.c
-v6int_OBJECTS = v6int-v6int.$(OBJEXT)
-v6int_LDADD = $(LDADD)
-v6int_LINK = $(CCLD) $(v6int_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+neon128_SOURCES = neon128.c
+neon128_OBJECTS = neon128-neon128.$(OBJEXT)
+neon128_LDADD = $(LDADD)
+neon128_LINK = $(CCLD) $(neon128_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+       $(LDFLAGS) -o $@
+neon64_SOURCES = neon64.c
+neon64_OBJECTS = neon64-neon64.$(OBJEXT)
+neon64_LDADD = $(LDADD)
+neon64_LINK = $(CCLD) $(neon64_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+       $(LDFLAGS) -o $@
+v6intARM_SOURCES = v6intARM.c
+v6intARM_OBJECTS = v6intARM-v6intARM.$(OBJEXT)
+v6intARM_LDADD = $(LDADD)
+v6intARM_LINK = $(CCLD) $(v6intARM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
+       $(LDFLAGS) -o $@
+v6intThumb_SOURCES = v6intThumb.c
+v6intThumb_OBJECTS = v6intThumb-v6intThumb.$(OBJEXT)
+v6intThumb_LDADD = $(LDADD)
+v6intThumb_LINK = $(CCLD) $(v6intThumb_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \

        $(LDFLAGS) -o $@
 SCRIPTS = $(dist_noinst_SCRIPTS)
 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)
        $(LDFLAGS) -o $@
 SCRIPTS = $(dist_noinst_SCRIPTS)
 DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir)


@@ -70,8 +86,8 @@ COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
        $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
 CCLD = $(CC)
 LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
        $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
 CCLD = $(CC)
 LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@

-SOURCES = v6int.c
-DIST_SOURCES = v6int.c
+SOURCES = neon128.c neon64.c v6intARM.c v6intThumb.c
+DIST_SOURCES = neon128.c neon64.c v6intARM.c v6intThumb.c

 ETAGS = etags
 CTAGS = ctags
 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
 ETAGS = etags
 CTAGS = ctags
 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)


@@ -112,6 +128,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -146,14 +163,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -236,7 +257,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -295,7 +318,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -310,8 +333,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -372,13 +395,29 @@ AM_CCASFLAGS = $(AM_CPPFLAGS) @FLAG_M32@
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
 dist_noinst_SCRIPTS = filter_stderr
 EXTRA_DIST = \
 @VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
 dist_noinst_SCRIPTS = filter_stderr
 EXTRA_DIST = \

-       v6int.stdout.exp v6int.stderr.exp v6int.vgtest
+       neon128.stdout.exp neon128.stderr.exp neon128.vgtest \
+       neon64.stdout.exp neon64.stderr.exp neon64.vgtest \
+       v6intARM.stdout.exp v6intARM.stderr.exp v6intARM.vgtest \
+       v6intThumb.stdout.exp v6intThumb.stderr.exp v6intThumb.vgtest
+
+
+# These two are specific to their ARM/Thumb respectively and so we
+# hardwire -marm/-mthumb.  neon64 and neon128 are compilable on both,
+# however, ask for them to be compiled on thumb, as that looks
+# like that's going to be the more common use case.  They also
+# need special helping w.r.t -mfpu and -mfloat-abi, though.
+# Also force -O0 since -O takes hundreds of MB of memory 
+# for v6intThumb.c.
+v6intARM_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -marm
+v6intThumb_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 -mthumb
+neon128_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+                       -mfpu=neon -mfloat-abi=softfp \
+                       -mthumb
+
+neon64_CFLAGS = $(AM_CFLAGS) -g -O0 -mcpu=cortex-a8 \
+                       -mfpu=neon -mfloat-abi=softfp \
+                       -mthumb

 
 

-
-# need to specify cpu here because inline assembly in v6int.c
-# contains various v6 and v7 insns, which the assembler by
-# default rejects.
-v6int_CFLAGS = $(AM_CFLAGS) -g -O -mcpu=cortex-a8

 all: all-am
 
 .SUFFIXES:
 all: all-am
 
 .SUFFIXES:


@@ -416,9 +455,18 @@ $(am__aclocal_m4_deps):
 
 clean-checkPROGRAMS:
        -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)
 
 clean-checkPROGRAMS:
        -test -z "$(check_PROGRAMS)" || rm -f $(check_PROGRAMS)

-v6int$(EXEEXT): $(v6int_OBJECTS) $(v6int_DEPENDENCIES) 
-       @rm -f v6int$(EXEEXT)
-       $(v6int_LINK) $(v6int_OBJECTS) $(v6int_LDADD) $(LIBS)
+neon128$(EXEEXT): $(neon128_OBJECTS) $(neon128_DEPENDENCIES) 
+       @rm -f neon128$(EXEEXT)
+       $(neon128_LINK) $(neon128_OBJECTS) $(neon128_LDADD) $(LIBS)
+neon64$(EXEEXT): $(neon64_OBJECTS) $(neon64_DEPENDENCIES) 
+       @rm -f neon64$(EXEEXT)
+       $(neon64_LINK) $(neon64_OBJECTS) $(neon64_LDADD) $(LIBS)
+v6intARM$(EXEEXT): $(v6intARM_OBJECTS) $(v6intARM_DEPENDENCIES) 
+       @rm -f v6intARM$(EXEEXT)
+       $(v6intARM_LINK) $(v6intARM_OBJECTS) $(v6intARM_LDADD) $(LIBS)
+v6intThumb$(EXEEXT): $(v6intThumb_OBJECTS) $(v6intThumb_DEPENDENCIES) 
+       @rm -f v6intThumb$(EXEEXT)
+       $(v6intThumb_LINK) $(v6intThumb_OBJECTS) $(v6intThumb_LDADD) $(LIBS)

 
 mostlyclean-compile:
        -rm -f *.$(OBJEXT)
 
 mostlyclean-compile:
        -rm -f *.$(OBJEXT)


@@ -426,7 +474,10 @@ mostlyclean-compile:
 distclean-compile:
        -rm -f *.tab.c
 
 distclean-compile:
        -rm -f *.tab.c
 

-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v6int-v6int.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/neon128-neon128.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/neon64-neon64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v6intARM-v6intARM.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/v6intThumb-v6intThumb.Po@am__quote@

 
 .c.o:
 @am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
 
 .c.o:
 @am__fastdepCC_TRUE@   $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<


@@ -442,19 +493,61 @@ distclean-compile:
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(COMPILE) -c `$(CYGPATH_W) '$<'`
 
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @am__fastdepCC_FALSE@  $(COMPILE) -c `$(CYGPATH_W) '$<'`
 

-v6int-v6int.o: v6int.c
-@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6int_CFLAGS) $(CFLAGS) -MT v6int-v6int.o -MD -MP -MF $(DEPDIR)/v6int-v6int.Tpo -c -o v6int-v6int.o `test -f 'v6int.c' || echo '$(srcdir)/'`v6int.c
-@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/v6int-v6int.Tpo $(DEPDIR)/v6int-v6int.Po
-@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='v6int.c' object='v6int-v6int.o' libtool=no @AMDEPBACKSLASH@
+neon128-neon128.o: neon128.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon128_CFLAGS) $(CFLAGS) -MT neon128-neon128.o -MD -MP -MF $(DEPDIR)/neon128-neon128.Tpo -c -o neon128-neon128.o `test -f 'neon128.c' || echo '$(srcdir)/'`neon128.c
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/neon128-neon128.Tpo $(DEPDIR)/neon128-neon128.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='neon128.c' object='neon128-neon128.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon128_CFLAGS) $(CFLAGS) -c -o neon128-neon128.o `test -f 'neon128.c' || echo '$(srcdir)/'`neon128.c
+
+neon128-neon128.obj: neon128.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon128_CFLAGS) $(CFLAGS) -MT neon128-neon128.obj -MD -MP -MF $(DEPDIR)/neon128-neon128.Tpo -c -o neon128-neon128.obj `if test -f 'neon128.c'; then $(CYGPATH_W) 'neon128.c'; else $(CYGPATH_W) '$(srcdir)/neon128.c'; fi`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/neon128-neon128.Tpo $(DEPDIR)/neon128-neon128.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='neon128.c' object='neon128-neon128.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon128_CFLAGS) $(CFLAGS) -c -o neon128-neon128.obj `if test -f 'neon128.c'; then $(CYGPATH_W) 'neon128.c'; else $(CYGPATH_W) '$(srcdir)/neon128.c'; fi`
+
+neon64-neon64.o: neon64.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon64_CFLAGS) $(CFLAGS) -MT neon64-neon64.o -MD -MP -MF $(DEPDIR)/neon64-neon64.Tpo -c -o neon64-neon64.o `test -f 'neon64.c' || echo '$(srcdir)/'`neon64.c
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/neon64-neon64.Tpo $(DEPDIR)/neon64-neon64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='neon64.c' object='neon64-neon64.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon64_CFLAGS) $(CFLAGS) -c -o neon64-neon64.o `test -f 'neon64.c' || echo '$(srcdir)/'`neon64.c
+
+neon64-neon64.obj: neon64.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon64_CFLAGS) $(CFLAGS) -MT neon64-neon64.obj -MD -MP -MF $(DEPDIR)/neon64-neon64.Tpo -c -o neon64-neon64.obj `if test -f 'neon64.c'; then $(CYGPATH_W) 'neon64.c'; else $(CYGPATH_W) '$(srcdir)/neon64.c'; fi`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/neon64-neon64.Tpo $(DEPDIR)/neon64-neon64.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='neon64.c' object='neon64-neon64.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(neon64_CFLAGS) $(CFLAGS) -c -o neon64-neon64.obj `if test -f 'neon64.c'; then $(CYGPATH_W) 'neon64.c'; else $(CYGPATH_W) '$(srcdir)/neon64.c'; fi`
+
+v6intARM-v6intARM.o: v6intARM.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intARM_CFLAGS) $(CFLAGS) -MT v6intARM-v6intARM.o -MD -MP -MF $(DEPDIR)/v6intARM-v6intARM.Tpo -c -o v6intARM-v6intARM.o `test -f 'v6intARM.c' || echo '$(srcdir)/'`v6intARM.c
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/v6intARM-v6intARM.Tpo $(DEPDIR)/v6intARM-v6intARM.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='v6intARM.c' object='v6intARM-v6intARM.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intARM_CFLAGS) $(CFLAGS) -c -o v6intARM-v6intARM.o `test -f 'v6intARM.c' || echo '$(srcdir)/'`v6intARM.c
+
+v6intARM-v6intARM.obj: v6intARM.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intARM_CFLAGS) $(CFLAGS) -MT v6intARM-v6intARM.obj -MD -MP -MF $(DEPDIR)/v6intARM-v6intARM.Tpo -c -o v6intARM-v6intARM.obj `if test -f 'v6intARM.c'; then $(CYGPATH_W) 'v6intARM.c'; else $(CYGPATH_W) '$(srcdir)/v6intARM.c'; fi`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/v6intARM-v6intARM.Tpo $(DEPDIR)/v6intARM-v6intARM.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='v6intARM.c' object='v6intARM-v6intARM.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intARM_CFLAGS) $(CFLAGS) -c -o v6intARM-v6intARM.obj `if test -f 'v6intARM.c'; then $(CYGPATH_W) 'v6intARM.c'; else $(CYGPATH_W) '$(srcdir)/v6intARM.c'; fi`
+
+v6intThumb-v6intThumb.o: v6intThumb.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intThumb_CFLAGS) $(CFLAGS) -MT v6intThumb-v6intThumb.o -MD -MP -MF $(DEPDIR)/v6intThumb-v6intThumb.Tpo -c -o v6intThumb-v6intThumb.o `test -f 'v6intThumb.c' || echo '$(srcdir)/'`v6intThumb.c
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/v6intThumb-v6intThumb.Tpo $(DEPDIR)/v6intThumb-v6intThumb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='v6intThumb.c' object='v6intThumb-v6intThumb.o' libtool=no @AMDEPBACKSLASH@

 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

-@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6int_CFLAGS) $(CFLAGS) -c -o v6int-v6int.o `test -f 'v6int.c' || echo '$(srcdir)/'`v6int.c
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intThumb_CFLAGS) $(CFLAGS) -c -o v6intThumb-v6intThumb.o `test -f 'v6intThumb.c' || echo '$(srcdir)/'`v6intThumb.c

 
 

-v6int-v6int.obj: v6int.c
-@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6int_CFLAGS) $(CFLAGS) -MT v6int-v6int.obj -MD -MP -MF $(DEPDIR)/v6int-v6int.Tpo -c -o v6int-v6int.obj `if test -f 'v6int.c'; then $(CYGPATH_W) 'v6int.c'; else $(CYGPATH_W) '$(srcdir)/v6int.c'; fi`
-@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/v6int-v6int.Tpo $(DEPDIR)/v6int-v6int.Po
-@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='v6int.c' object='v6int-v6int.obj' libtool=no @AMDEPBACKSLASH@
+v6intThumb-v6intThumb.obj: v6intThumb.c
+@am__fastdepCC_TRUE@   $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intThumb_CFLAGS) $(CFLAGS) -MT v6intThumb-v6intThumb.obj -MD -MP -MF $(DEPDIR)/v6intThumb-v6intThumb.Tpo -c -o v6intThumb-v6intThumb.obj `if test -f 'v6intThumb.c'; then $(CYGPATH_W) 'v6intThumb.c'; else $(CYGPATH_W) '$(srcdir)/v6intThumb.c'; fi`
+@am__fastdepCC_TRUE@   $(am__mv) $(DEPDIR)/v6intThumb-v6intThumb.Tpo $(DEPDIR)/v6intThumb-v6intThumb.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@      source='v6intThumb.c' object='v6intThumb-v6intThumb.obj' libtool=no @AMDEPBACKSLASH@

 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
 @AMDEP_TRUE@@am__fastdepCC_FALSE@      DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@

-@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6int_CFLAGS) $(CFLAGS) -c -o v6int-v6int.obj `if test -f 'v6int.c'; then $(CYGPATH_W) 'v6int.c'; else $(CYGPATH_W) '$(srcdir)/v6int.c'; fi`
+@am__fastdepCC_FALSE@  $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(v6intThumb_CFLAGS) $(CFLAGS) -c -o v6intThumb-v6intThumb.obj `if test -f 'v6intThumb.c'; then $(CYGPATH_W) 'v6intThumb.c'; else $(CYGPATH_W) '$(srcdir)/v6intThumb.c'; fi`

 
 ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
        list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
 
 ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
        list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.c
new file mode 100644 (file)
index 0000000..9b122fe
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.c
@@ -0,0 +1,3093 @@
+
+/* How to compile:
+
+   gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \
+       -marm -o neon128-a neon128.c
+
+   or
+
+   gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \
+       -mthumb -o neon128-t neon128.c
+
+*/
+
+#include <stdio.h>
+#include <math.h>
+
+#ifndef __thumb__
+// ARM
+#define MOVE_to_FPSCR_from_R4 \
+      ".word 0xEEE14A10 @ vmsr FPSCR, r4\n\t"
+#define MOVE_to_R4_from_FPSCR \
+      ".word 0xEEF14A10 @ vmrs r4, FPSCR\n\t"
+#endif
+
+#ifdef __thumb__
+// Thumb
+#define MOVE_to_FPSCR_from_R4 \
+      ".word 0x4A10EEE1 @ vmsr FPSCR, r4\n\t"
+#define MOVE_to_R4_from_FPSCR \
+      ".word 0x4A10EEF1 @ vmrs r4, FPSCR\n\t"
+#endif
+
+static inline unsigned int f2u(float x) {
+    union {
+        float f;
+        unsigned int u;
+    } cvt;
+    cvt.f = x;
+    return cvt.u;
+}
+
+/* test macros to generate and output the result of a single instruction */
+
+#define TESTINSN_imm(instruction, QD, imm) \
+{ \
+  unsigned int out[4]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      instruction ", #" #imm "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out) \
+      : #QD, "memory" \
+      ); \
+  printf("%s, #" #imm " :: Qd 0x%08x 0x%08x 0x%08x 0x%08x\n", \
+      instruction, out[3], out[2], out[1], out[0]); \
+}
+
+#define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \
+{ \
+  unsigned int out[4]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval) \
+      : #QD, #QM, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x\n", \
+      instruction, out[3], out[2], out[1], out[0], QMval); \
+}
+
+#define TESTINSN_un_q(instruction, QD, QM, QMtype, QMval) \
+{ \
+  unsigned int out[4]; \
+  unsigned int fpscr; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "mov r4, #0\n\t" \
+      MOVE_to_FPSCR_from_R4 \
+      "vdup." #QMtype " " #QM ", %2\n\t" \
+      instruction "\n\t" \
+      "vstmia %1, {" #QD "}\n\t" \
+      MOVE_to_R4_from_FPSCR \
+      "mov %0, r4" \
+      : "=r" (fpscr) \
+      : "r" (out), "r" (QMval) \
+      : #QD, #QM, "memory", "r4" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+          "  fpscr: %08x\n", \
+      instruction, out[3], out[2], out[1], out[0], QMval, fpscr); \
+}
+
+#define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out[4]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      "vdup." #QNtype " " #QN ", %2\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval), "r" (QNval) \
+      : #QD, #QM, #QN, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x\n", \
+      instruction, out[3], out[2], out[1], out[0], QMval, QNval); \
+}
+
+#define TESTINSN_bin_f(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out[4]; \
+\
+  __asm__ volatile( \
+      "vdup.i32 " #QD ", %3\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      "vdup." #QNtype " " #QN ", %2\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval), "r" (QNval), "r" (0x3f800000) \
+      : #QD, #QM, #QN, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x\n", \
+      instruction, out[3], out[2], out[1], out[0], QMval, QNval); \
+}
+
+#define TESTINSN_bin_q(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out[4]; \
+  unsigned int fpscr; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "mov r4, #0\n\t" \
+      MOVE_to_FPSCR_from_R4 \
+      "vdup." #QMtype " " #QM ", %2\n\t" \
+      "vdup." #QNtype " " #QN ", %3\n\t" \
+      instruction "\n\t" \
+      "vstmia %1, {" #QD "}\n\t" \
+      MOVE_to_R4_from_FPSCR \
+      "mov %0, r4" \
+      : "=r" (fpscr) \
+      : "r" (out), "r" (QMval), "r" (QNval) \
+      : #QD, #QM, #QN, "memory", "r4" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x  fpscr: %08x\n", \
+      instruction, out[3], out[2], out[1], out[0], QMval, QNval, fpscr); \
+}
+
+#define TESTINSN_dual(instruction, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out1[4]; \
+  unsigned int out2[4]; \
+\
+  __asm__ volatile( \
+      "vdup." #QMtype " " #QM ", %2\n\t" \
+      "vdup." #QNtype " " #QN ", %3\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QM "}\n\t" \
+      "vstmia %1, {" #QN "}\n\t" \
+      : \
+      : "r" (out1), "r" (out2), "r" (QMval), "r" (QNval) \
+      : #QM, #QN, "memory" \
+      ); \
+  printf("%s :: Qm 0x%08x 0x%08x 0x%08x 0x%08x  Qn 0x%08x 0x%08x 0x%08x 0x%08x" \
+      "  Qm (" #QMtype ")0x%08x  Qn (" #QNtype ")0x%08x\n", \
+      instruction, out1[3], out1[2], out1[1], out1[0], \
+      out2[3], out2[2], out2[1], out2[0], QMval, QNval); \
+}
+
+// Ditto TESTING_bin(), but in QD all zeros
+#define TESTINSN_bin_0s(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out[4]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x00" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      "vdup." #QNtype " " #QN ", %2\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval), "r" (QNval) \
+      : #QD, #QM, #QN, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x\n", \
+      instruction, out[3], out[2], out[1], out[0], QMval, QNval); \
+}
+
+#if 0
+#define TESTINSN_2reg_shift(instruction, QD, QM, QMtype, QMval, imm) \
+{ \
+  unsigned int out[4]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      instruction ", #" #imm "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval) \
+      : #QD, #QM, "memory" \
+      ); \
+  printf("%s, #" #imm " :: Qd 0x%08x 0x%08x 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x", \
+      instruction, out[3], out[2], out[1], out[0], QMval); \
+}
+#endif
+
+int main(int argc, char **argv)
+{
+    printf("----- VMOV (immediate) -----\n");
+    TESTINSN_imm("vmov.i32 q0", q0, 0x7);
+    TESTINSN_imm("vmov.i16 q1", q1, 0x7);
+    TESTINSN_imm("vmov.i8 q2", q2, 0x7);
+    TESTINSN_imm("vmov.i32 q5", q5, 0x700);
+    TESTINSN_imm("vmov.i16 q7", q7, 0x700);
+    TESTINSN_imm("vmov.i32 q10", q10, 0x70000);
+    TESTINSN_imm("vmov.i32 q12", q12, 0x7000000);
+    TESTINSN_imm("vmov.i32 q13", q13, 0x7FF);
+    TESTINSN_imm("vmov.i32 q14", q14, 0x7FFFF);
+    TESTINSN_imm("vmov.i64 q15", q15, 0xFF0000FF00FFFF00);
+
+    printf("----- VMVN (immediate) -----\n");
+    TESTINSN_imm("vmvn.i32 q0", q0, 0x7);
+    TESTINSN_imm("vmvn.i16 q1", q1, 0x7);
+    TESTINSN_imm("vmvn.i8 q2", q2, 0x7);
+    TESTINSN_imm("vmvn.i32 q5", q5, 0x700);
+    TESTINSN_imm("vmvn.i16 q7", q7, 0x700);
+    TESTINSN_imm("vmvn.i32 q10", q10, 0x70000);
+    TESTINSN_imm("vmvn.i32 q13", q13, 0x7000000);
+    TESTINSN_imm("vmvn.i32 q11", q11, 0x7FF);
+    TESTINSN_imm("vmvn.i32 q14", q14, 0x7FFFF);
+    TESTINSN_imm("vmvn.i64 q15", q15, 0xFF0000FF00FFFF00);
+
+    printf("----- VORR (immediate) -----\n");
+    TESTINSN_imm("vorr.i32 q0", q0, 0x7);
+    TESTINSN_imm("vorr.i16 q2", q2, 0x7);
+    TESTINSN_imm("vorr.i32 q8", q8, 0x700);
+    TESTINSN_imm("vorr.i16 q6", q6, 0x700);
+    TESTINSN_imm("vorr.i32 q14", q14, 0x70000);
+    TESTINSN_imm("vorr.i32 q15", q15, 0x7000000);
+
+    printf("----- VBIC (immediate) -----\n");
+    TESTINSN_imm("vbic.i32 q0", q0, 0x7);
+    TESTINSN_imm("vbic.i16 q3", q3, 0x7);
+    TESTINSN_imm("vbic.i32 q5", q5, 0x700);
+    TESTINSN_imm("vbic.i16 q8", q8, 0x700);
+    TESTINSN_imm("vbic.i32 q10", q10, 0x70000);
+    TESTINSN_imm("vbic.i32 q15", q15, 0x7000000);
+
+    printf("---- VMVN (register) ----\n");
+    TESTINSN_un("vmvn q0, q1", q0, q1, i32, 24);
+    TESTINSN_un("vmvn q10, q15", q10, q15, i32, 24);
+    TESTINSN_un("vmvn q0, q14", q0, q14, i32, 24);
+
+    printf("---- VMOV (register) ----\n");
+    TESTINSN_un("vmov q0, q1", q0, q1, i32, 24);
+    TESTINSN_un("vmov q10, q15", q10, q15, i32, 24);
+    TESTINSN_un("vmov q0, q14", q0, q14, i32, 24);
+
+    printf("---- VDUP (ARM core register) (tested indirectly) ----\n");
+    TESTINSN_un("vmov q0, q1", q0, q1, i8, 7);
+    TESTINSN_un("vmov q10, q11", q10, q11, i16, 7);
+    TESTINSN_un("vmov q0, q15", q0, q15, i32, 7);
+
+    printf("---- VADD ----\n");
+    TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vadd.i64 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vadd.i16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vadd.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vadd.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vadd.i16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vadd.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vadd.i64 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vadd.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vadd.i64 q13, q14, q15", q13, q14, i32, 140, q15, i32, 120);
+
+    printf("---- VSUB ----\n");
+    TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vsub.i64 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vsub.i16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vsub.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vsub.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vsub.i16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vsub.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vsub.i64 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vsub.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vsub.i64 q13, q14, q15", q13, q14, i32, 140, q15, i32, 120);
+
+    printf("---- VAND ----\n");
+    TESTINSN_bin("vand q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
+    TESTINSN_bin("vand q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
+    TESTINSN_bin("vand q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
+    TESTINSN_bin("vand q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
+
+    printf("---- VBIC ----\n");
+    TESTINSN_bin("vbic q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
+    TESTINSN_bin("vbic q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
+    TESTINSN_bin("vbic q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
+    TESTINSN_bin("vbic q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
+
+    printf("---- VORR ----\n");
+    TESTINSN_bin("vorr q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
+    TESTINSN_bin("vorr q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
+    TESTINSN_bin("vorr q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
+    TESTINSN_bin("vorr q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
+
+    printf("---- VORN ----\n");
+    TESTINSN_bin("vorn q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
+    TESTINSN_bin("vorn q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
+    TESTINSN_bin("vorn q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
+    TESTINSN_bin("vorn q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
+
+    printf("---- VEOR ----\n");
+    TESTINSN_bin("veor q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
+    TESTINSN_bin("veor q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
+    TESTINSN_bin("veor q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
+    TESTINSN_bin("veor q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
+    TESTINSN_bin("veor q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
+    TESTINSN_bin("veor q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
+    TESTINSN_bin("veor q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
+    TESTINSN_bin("veor q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
+
+    printf("---- VBSL ----\n");
+    TESTINSN_bin("vbsl q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
+    TESTINSN_bin("vbsl q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
+    TESTINSN_bin("vbsl q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
+    TESTINSN_bin("vbsl q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
+    TESTINSN_bin("vbsl q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
+    TESTINSN_bin("vbsl q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
+    TESTINSN_bin("vbsl q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
+    TESTINSN_bin("vbsl q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
+
+    printf("---- VBIT ----\n");
+    TESTINSN_bin("vbit q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
+    TESTINSN_bin("vbit q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
+    TESTINSN_bin("vbit q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
+    TESTINSN_bin("vbit q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
+    TESTINSN_bin("vbit q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
+    TESTINSN_bin("vbit q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
+    TESTINSN_bin("vbit q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
+    TESTINSN_bin("vbit q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
+
+    printf("---- VBIF ----\n");
+    TESTINSN_bin("vbif q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x77);
+    TESTINSN_bin("vbif q4, q6, q5", q4, q6, i8, 0xff, q5, i16, 0x57);
+    TESTINSN_bin("vbif q10, q11, q12", q10, q11, i8, 0xfe, q12, i8, 0xed);
+    TESTINSN_bin("vbif q15, q15, q15", q15, q15, i8, 0xff, q15, i8, 0xff);
+    TESTINSN_bin("vbif q0, q1, q2", q0, q1, i8, 0x24, q2, i16, 0x73);
+    TESTINSN_bin("vbif q7, q3, q0", q7, q3, i8, 0x24, q0, i16, 0xff);
+    TESTINSN_bin("vbif q4, q4, q4", q4, q4, i16, 0xff, q4, i16, 0xff);
+    TESTINSN_bin("vbif q2, q3, q15", q2, q3, i32, 0x24, q15, i32, 0x1f);
+
+    printf("---- VEXT ----\n");
+    TESTINSN_bin("vext.8 q0, q1, q2, #0", q0, q1, i8, 0x77, q2, i8, 0xff);
+    TESTINSN_bin("vext.8 q0, q1, q2, #1", q0, q1, i8, 0x77, q2, i8, 0xff);
+    TESTINSN_bin("vext.8 q0, q1, q2, #9", q0, q1, i8, 0x77, q2, i8, 0xff);
+    TESTINSN_bin("vext.8 q0, q1, q2, #15", q0, q1, i8, 0x77, q2, i8, 0xff);
+    TESTINSN_bin("vext.8 q10, q11, q12, #4", q10, q11, i8, 0x77, q12, i8, 0xff);
+    TESTINSN_bin("vext.8 q0, q5, q15, #12", q0, q5, i8, 0x77, q15, i8, 0xff);
+
+    printf("---- VHADD ----\n");
+    TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i8, 141, q2, i8, 121);
+    TESTINSN_bin("vhadd.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i8, 141, q2, i8, 121);
+    TESTINSN_bin("vhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VHSUB ----\n");
+    TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhsub.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhsub.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhsub.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhsub.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhsub.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vhsub.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VQADD ----\n");
+    TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqadd.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VQSUB ----\n");
+    TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqsub.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqsub.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqsub.s8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqsub.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqsub.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin_q("vqsub.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VRHADD ----\n");
+    TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
+    TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vrhadd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VCGT ----\n");
+    TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
+    TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
+    TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
+    TESTINSN_bin("vcgt.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
+    TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 3, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 2, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VCGE ----\n");
+    TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
+    TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
+    TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
+    TESTINSN_bin("vcge.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 140);
+    TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 3, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 2, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 3, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 2, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VSHL (register) ----\n");
+    TESTINSN_bin("vshl.s8 q0, q1, q2", q0, q1, i32, 24, q2, i32, 1);
+    TESTINSN_bin("vshl.s8 q8, q1, q12", q8, q1, i32, 24, q12, i32, 8);
+    TESTINSN_bin("vshl.s8 q10, q11, q7", q10, q11, i32, 24, q7, i32, 4);
+    TESTINSN_bin("vshl.s16 q3, q8, q11", q3, q8, i32, 14, q11, i32, 2);
+    TESTINSN_bin("vshl.s16 q5, q12, q14", q5, q12, i32, (1 << 30), q14, i32, 1);
+    TESTINSN_bin("vshl.s16 q15, q2, q1", q15, q2, i32, (1 << 30), q1, i32, 11);
+    TESTINSN_bin("vshl.s32 q9, q12, q15", q9, q12, i32, (1 << 31) + 2, q15, i32, 2);
+    TESTINSN_bin("vshl.s32 q11, q2, q0", q11, q2, i32, -1, q0, i32, 12);
+    TESTINSN_bin("vshl.s32 q5, q2, q3", q5, q2, i32, (1 << 30), q3, i32, 21);
+    TESTINSN_bin("vshl.s64 q15, q12, q4", q15, q12, i32, 5, q4, i32, 20);
+    TESTINSN_bin("vshl.s64 q8, q2, q4", q8, q2, i32, 15, q4, i32, 4);
+    TESTINSN_bin("vshl.s64 q5, q12, q4", q5, q12, i32, (1 << 31) + 1, q4, i32, 30);
+    TESTINSN_bin("vshl.u8 q0, q1, q2", q0, q1, i32, 24, q2, i32, 1);
+    TESTINSN_bin("vshl.u8 q8, q1, q12", q8, q1, i32, 24, q12, i32, 8);
+    TESTINSN_bin("vshl.u8 q10, q11, q7", q10, q11, i32, 24, q7, i32, 4);
+    TESTINSN_bin("vshl.u16 q3, q8, q11", q3, q8, i32, 14, q11, i32, 2);
+    TESTINSN_bin("vshl.u16 q5, q12, q14", q5, q12, i32, (1 << 30), q14, i32, 1);
+    TESTINSN_bin("vshl.u16 q15, q2, q1", q15, q2, i32, (1 << 30), q1, i32, 11);
+    TESTINSN_bin("vshl.u32 q9, q12, q15", q9, q12, i32, (1 << 31) + 2, q15, i32, 2);
+    TESTINSN_bin("vshl.u32 q11, q2, q0", q11, q2, i32, -1, q0, i32, 12);
+    TESTINSN_bin("vshl.u32 q5, q2, q3", q5, q2, i32, (1 << 30), q3, i32, 21);
+    TESTINSN_bin("vshl.u64 q15, q12, q4", q15, q12, i32, 5, q4, i32, 20);
+    TESTINSN_bin("vshl.u64 q8, q2, q4", q8, q2, i32, 15, q4, i32, 4);
+    TESTINSN_bin("vshl.u64 q5, q12, q4", q5, q12, i32, (1 << 31) + 1, q4, i32, 30);
+
+    printf("---- VQSHL (register) ----\n");
+    TESTINSN_bin_q("vqshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
+    TESTINSN_bin_q("vqshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
+    TESTINSN_bin_q("vqshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
+    TESTINSN_bin_q("vqshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
+    TESTINSN_bin_q("vqshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
+    TESTINSN_bin_q("vqshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
+    TESTINSN_bin_q("vqshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
+    TESTINSN_bin_q("vqshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
+    TESTINSN_bin_q("vqshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
+    TESTINSN_bin_q("vqshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
+    TESTINSN_bin_q("vqshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
+    TESTINSN_bin_q("vqshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
+    TESTINSN_bin_q("vqshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
+    TESTINSN_bin_q("vqshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
+    TESTINSN_bin_q("vqshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
+    TESTINSN_bin_q("vqshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
+    TESTINSN_bin_q("vqshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
+    TESTINSN_bin_q("vqshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
+    TESTINSN_bin_q("vqshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
+    TESTINSN_bin_q("vqshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
+    TESTINSN_bin_q("vqshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
+    TESTINSN_bin_q("vqshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
+    TESTINSN_bin_q("vqshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
+    TESTINSN_bin_q("vqshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin_q("vqshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
+    TESTINSN_bin_q("vqshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
+    TESTINSN_bin_q("vqshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
+    TESTINSN_bin_q("vqshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
+    TESTINSN_bin_q("vqshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
+    TESTINSN_bin_q("vqshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
+    TESTINSN_bin_q("vqshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
+    TESTINSN_bin_q("vqshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
+    TESTINSN_bin_q("vqshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
+    TESTINSN_bin_q("vqshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
+    TESTINSN_bin_q("vqshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
+    TESTINSN_bin_q("vqshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
+    TESTINSN_bin_q("vqshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
+    TESTINSN_bin_q("vqshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
+    TESTINSN_bin_q("vqshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
+    TESTINSN_bin_q("vqshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
+    TESTINSN_bin_q("vqshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
+    TESTINSN_bin_q("vqshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
+    TESTINSN_bin_q("vqshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
+    TESTINSN_bin_q("vqshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
+    TESTINSN_bin_q("vqshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
+    TESTINSN_bin_q("vqshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
+    TESTINSN_bin_q("vqshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
+    TESTINSN_bin_q("vqshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VQSHL / VQSHLU (immediate) ----\n");
+    TESTINSN_un_q("vqshl.s64 q0, q1, #1", q0, q1, i32, 1);
+    TESTINSN_un_q("vqshl.s64 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #63", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #60", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #59", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #58", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #17", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #63", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #60", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.s64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.s32 q10, q11, #1", q10, q11, i32, 1);
+    TESTINSN_un_q("vqshl.s32 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #31", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #28", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #27", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #26", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #17", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #31", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #29", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.s32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.s16 q9, q8, #1", q9, q8, i32, 1);
+    TESTINSN_un_q("vqshl.s16 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshl.s16 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshl.s16 q9, q8, #15", q9, q8, i32, 16);
+    TESTINSN_un_q("vqshl.s16 q5, q4, #12", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s16 q5, q4, #11", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s16 q5, q4, #10", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s16 q5, q4, #4", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s16 q5, q4, #15", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.s16 q5, q4, #12", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.s16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.s8 q0, q1, #1", q0, q1, i32, 1);
+    TESTINSN_un_q("vqshl.s8 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #7", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #4", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #3", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #2", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #1", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #7", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #5", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.s8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.u64 q0, q1, #1", q0, q1, i32, 1);
+    TESTINSN_un_q("vqshl.u64 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #63", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #60", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #59", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #58", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #17", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #63", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #60", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.u64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.u32 q10, q11, #1", q10, q11, i32, 1);
+    TESTINSN_un_q("vqshl.u32 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #31", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #28", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #27", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #26", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #17", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #31", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #29", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.u32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.u16 q9, q8, #1", q9, q8, i32, 1);
+    TESTINSN_un_q("vqshl.u16 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshl.u16 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshl.u16 q9, q8, #15", q9, q8, i32, 16);
+    TESTINSN_un_q("vqshl.u16 q5, q4, #12", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u16 q5, q4, #11", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u16 q5, q4, #10", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u16 q5, q4, #4", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u16 q5, q4, #15", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.u16 q5, q4, #12", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.u16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.u8 q0, q1, #1", q0, q1, i32, 1);
+    TESTINSN_un_q("vqshl.u8 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #7", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #4", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #3", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #2", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #1", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #7", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #5", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshl.u8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshlu.s64 q0, q1, #1", q0, q1, i32, 1);
+    TESTINSN_un_q("vqshlu.s64 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #63", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #60", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #59", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #58", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #17", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #63", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #60", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshlu.s64 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshlu.s32 q10, q11, #1", q10, q11, i32, 1);
+    TESTINSN_un_q("vqshlu.s32 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #31", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #28", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #27", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #26", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #17", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #31", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #29", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshlu.s32 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshlu.s16 q9, q8, #1", q9, q8, i32, 1);
+    TESTINSN_un_q("vqshlu.s16 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshlu.s16 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshlu.s16 q9, q8, #15", q9, q8, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 q5, q4, #12", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 q5, q4, #11", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 q5, q4, #10", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 q5, q4, #4", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 q5, q4, #15", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshlu.s16 q5, q4, #12", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshlu.s16 q5, q4, #7", q5, q4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshlu.s8 q0, q1, #1", q0, q1, i32, 1);
+    TESTINSN_un_q("vqshlu.s8 q15, q14, #1", q15, q14, i32, -127);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #0", q5, q4, i32, -127);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #7", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #4", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #3", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #2", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #1", q5, q4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #7", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #5", q5, q4, i32, -1);
+    TESTINSN_un_q("vqshlu.s8 q5, q4, #2", q5, q4, i32, (1 << 31) + 2);
+
+    printf("---- VQRSHL (register) ----\n");
+    TESTINSN_bin_q("vqrshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
+    TESTINSN_bin_q("vqrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
+    TESTINSN_bin_q("vqrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
+    TESTINSN_bin_q("vqrshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
+    TESTINSN_bin_q("vqrshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
+    TESTINSN_bin_q("vqrshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
+    TESTINSN_bin_q("vqrshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
+    TESTINSN_bin_q("vqrshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
+    TESTINSN_bin_q("vqrshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
+    TESTINSN_bin_q("vqrshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
+    TESTINSN_bin_q("vqrshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
+    TESTINSN_bin_q("vqrshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
+    TESTINSN_bin_q("vqrshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
+    TESTINSN_bin_q("vqrshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
+    TESTINSN_bin_q("vqrshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
+    TESTINSN_bin_q("vqrshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
+    TESTINSN_bin_q("vqrshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
+    TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin_q("vqrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin_q("vqrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin_q("vqrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
+    TESTINSN_bin_q("vqrshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
+    TESTINSN_bin_q("vqrshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
+    TESTINSN_bin_q("vqrshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
+    TESTINSN_bin_q("vqrshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
+    TESTINSN_bin_q("vqrshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin_q("vqrshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
+    TESTINSN_bin_q("vqrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
+    TESTINSN_bin_q("vqrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
+    TESTINSN_bin_q("vqrshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
+    TESTINSN_bin_q("vqrshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
+    TESTINSN_bin_q("vqrshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
+    TESTINSN_bin_q("vqrshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
+    TESTINSN_bin_q("vqrshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
+    TESTINSN_bin_q("vqrshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
+    TESTINSN_bin_q("vqrshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
+    TESTINSN_bin_q("vqrshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
+    TESTINSN_bin_q("vqrshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
+    TESTINSN_bin_q("vqrshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
+    TESTINSN_bin_q("vqrshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
+    TESTINSN_bin_q("vqrshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
+    TESTINSN_bin_q("vqrshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
+    TESTINSN_bin_q("vqrshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
+    TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
+    TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin_q("vqrshl.u16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin_q("vqrshl.u32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin_q("vqrshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
+    TESTINSN_bin_q("vqrshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
+    TESTINSN_bin_q("vqrshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
+    TESTINSN_bin_q("vqrshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
+    TESTINSN_bin_q("vqrshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VRSHL (register) ----\n");
+    TESTINSN_bin("vrshl.s64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
+    TESTINSN_bin("vrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
+    TESTINSN_bin("vrshl.s64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
+    TESTINSN_bin("vrshl.s64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
+    TESTINSN_bin("vrshl.s64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
+    TESTINSN_bin("vrshl.s64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
+    TESTINSN_bin("vrshl.s32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
+    TESTINSN_bin("vrshl.s32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
+    TESTINSN_bin("vrshl.s32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
+    TESTINSN_bin("vrshl.s32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
+    TESTINSN_bin("vrshl.s32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
+    TESTINSN_bin("vrshl.s32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
+    TESTINSN_bin("vrshl.s16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
+    TESTINSN_bin("vrshl.s16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
+    TESTINSN_bin("vrshl.s16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
+    TESTINSN_bin("vrshl.s16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
+    TESTINSN_bin("vrshl.s16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
+    TESTINSN_bin("vrshl.s16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
+    TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin("vrshl.s16 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin("vrshl.s32 q2, q7, q11", q2, q7, i32, -1, q11, i32, 0);
+    TESTINSN_bin("vrshl.s8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
+    TESTINSN_bin("vrshl.s8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
+    TESTINSN_bin("vrshl.s8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
+    TESTINSN_bin("vrshl.s8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
+    TESTINSN_bin("vrshl.s8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
+    TESTINSN_bin("vrshl.s8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vrshl.u64 q0, q1, q2", q0, q1, i32, 1, q2, i32, 1);
+    TESTINSN_bin("vrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, 1);
+    TESTINSN_bin("vrshl.u64 q3, q4, q5", q3, q4, i32, -127, q5, i32, -3);
+    TESTINSN_bin("vrshl.u64 q0, q1, q2", q0, q1, i32, 16, q2, i32, 14);
+    TESTINSN_bin("vrshl.u64 q13, q14, q15", q13, q14, i32, -17, q15, i32, -26);
+    TESTINSN_bin("vrshl.u64 q7, q8, q2", q7, q8, i32, 24, q2, i32, -60);
+    TESTINSN_bin("vrshl.u32 q3, q4, q15", q3, q4, i32, 127, q15, i32, -30);
+    TESTINSN_bin("vrshl.u32 q2, q8, q4", q2, q8, i32, -11, q4, i32, -4);
+    TESTINSN_bin("vrshl.u32 q12, q11, q13", q12, q11, i32, -120, q13, i32, -9);
+    TESTINSN_bin("vrshl.u32 q0, q1, q2", q0, q1, i32, 34, q2, i32, -7);
+    TESTINSN_bin("vrshl.u32 q9, q10, q11", q9, q10, i32, (1 << 31) + 8, q11, i32, -1);
+    TESTINSN_bin("vrshl.u32 q13, q3, q5", q13, q3, i32, (1 << 27), q5, i32, 3);
+    TESTINSN_bin("vrshl.u16 q11, q10, q2", q11, q10, i32, (1 << 31), q2, i32, -31);
+    TESTINSN_bin("vrshl.u16 q3, q14, q7", q3, q14, i32, (1 << 31), q7, i32, -3);
+    TESTINSN_bin("vrshl.u16 q0, q11, q2", q0, q11, i32, (1 << 31) + 256, q2, i32, -1);
+    TESTINSN_bin("vrshl.u16 q1, q2, q3", q1, q2, i32, (1 << 31) + 256, q3, i32, -31);
+    TESTINSN_bin("vrshl.u16 q3, q4, q5", q3, q4, i32, (1 << 31) + (1 << 29), q5, i32, -13);
+    TESTINSN_bin("vrshl.u16 q0, q15, q2", q0, q15, i32, 1, q2, i32, 30);
+    TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, 40);
+    TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, 0xf, q11, i32, -1);
+    TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, -1, q11, i32, -1);
+    TESTINSN_bin("vrshl.u8 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin("vrshl.u16 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin("vrshl.u32 q2, q7, q11", q2, q7, i32, -2, q11, i32, -1);
+    TESTINSN_bin("vrshl.u8 q13, q1, q2", q13, q1, i32, -4, q2, i32, 30);
+    TESTINSN_bin("vrshl.u8 q3, q7, q5", q3, q7, i32, (1 << 31) + 11, q5, i32, 3);
+    TESTINSN_bin("vrshl.u8 q10, q11, q12", q10, q11, i32, (1 << 16), q12, i32, 16);
+    TESTINSN_bin("vrshl.u8 q6, q7, q8", q6, q7, i32, (1 << 30), q8, i32, 2);
+    TESTINSN_bin("vrshl.u8 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VMAX (integer) ----\n");
+    TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
+    TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 121);
+    TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vmax.s8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmax.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 120);
+    TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmax.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmax.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VMIN (integer) ----\n");
+    TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
+    TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 121);
+    TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vmin.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmin.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 250, q2, i32, 120);
+    TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, 120, q2, i32, 120);
+    TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 140);
+    TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vmin.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VABD ----\n");
+    TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
+    TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, -120);
+    TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vabd.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200);
+    TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, -140, q2, i32, 120);
+    TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vabd.u8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200);
+    TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VABA ----\n");
+    TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 121);
+    TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vaba.s8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200);
+    TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.s8 q5, q7, q5", q5, q7, i32, (1 << 31) + 4, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+    TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, 25, q2, i32, 120);
+    TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vaba.u8 q5, q7, q5", q5, q7, i32, -255, q5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u8 q5, q7, q5", q5, q7, i32, (1 << 31) + 1, q5, i32, -200);
+    TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.u8 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u16 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u32 q0, q1, q2", q0, q1, i32, (1 << 31) + 4, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VABAL ----\n");
+    TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabal.s8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200);
+    TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabal.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.s32 q10, d31, d12", q10, d31, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabal.u8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.u8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200);
+    TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabal.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabal.u32 q10, d11, d12", q10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VABDL ----\n");
+    TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabdl.s8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200);
+    TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabdl.s8 q5, d7, d5", q5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.s16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.s32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.s32 q10, d31, d12", q10, d31, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabdl.u8 q5, d7, d5", q5, d7, i32, -255, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.u8 q5, d7, d5", q5, d7, i32, (1 << 31) + 1, d5, i32, -200);
+    TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabdl.u8 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.u16 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.u32 q0, d1, d2", q0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabdl.u32 q10, d11, d12", q10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VTST ----\n");
+    TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vtst.32 q3, q4, q5", q3, q4, i32, 140, q5, i32, 120);
+    TESTINSN_bin("vtst.16 q6, q7, q8", q6, q7, i32, 120, q8, i32, 120);
+    TESTINSN_bin("vtst.8 q9, q10, q12", q9, q10, i32, 140, q12, i32, 120);
+    TESTINSN_bin("vtst.8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vtst.16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1);
+    TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vtst.8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, 2);
+    TESTINSN_bin("vtst.16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1);
+    TESTINSN_bin("vtst.32 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vtst.32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VCEQ ----\n");
+    TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vceq.i32 q3, q4, q5", q3, q4, i32, 140, q5, i32, 120);
+    TESTINSN_bin("vceq.i16 q6, q7, q8", q6, q7, i32, 120, q8, i32, 120);
+    TESTINSN_bin("vceq.i8 q9, q10, q12", q9, q10, i32, 140, q12, i32, 120);
+    TESTINSN_bin("vceq.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vceq.i16 q0, q1, q2", q0, q1, i32, (1 << 14) + 1, q2, i32, (1 << 14) + 1);
+    TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vceq.i8 q0, q1, q2", q0, q1, i32, (1 << 31) + 1, q2, i32, 2);
+    TESTINSN_bin("vceq.i16 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 14) + 1);
+    TESTINSN_bin("vceq.i32 q0, q1, q2", q0, q1, i32, 1, q2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vceq.i32 q10, q11, q12", q10, q11, i32, 24, q12, i32, 120);
+
+    printf("---- VMLA ----\n");
+    TESTINSN_bin("vmla.i32 q0, q1, q2", q0, q1, i32, -24, q2, i32, 120);
+    TESTINSN_bin("vmla.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, 120);
+    TESTINSN_bin("vmla.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
+    TESTINSN_bin("vmla.i16 q7, q1, q2", q7, q1, i32, 0x140, q2, i32, 0x120);
+    TESTINSN_bin("vmla.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, -120);
+    TESTINSN_bin("vmla.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
+    TESTINSN_bin("vmla.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i16 q14, q5, q9", q14, q5, i32, (1 << 14) + 1, q9, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmla.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
+    TESTINSN_bin("vmla.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmla.i32 q10, q11, q15", q10, q11, i32, 24, q15, i32, -120);
+
+    printf("---- VMLS ----\n");
+    TESTINSN_bin("vmls.i32 q0, q1, q2", q0, q1, i32, -24, q2, i32, 120);
+    TESTINSN_bin("vmls.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120);
+    TESTINSN_bin("vmls.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
+    TESTINSN_bin("vmls.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vmls.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
+    TESTINSN_bin("vmls.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmls.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmls.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
+    TESTINSN_bin("vmls.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmls.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmls.i32 q10, q11, q15", q10, q11, i32, -24, q15, i32, 120);
+
+    printf("---- VMUL ----\n");
+    TESTINSN_bin("vmul.i32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin("vmul.i32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120);
+    TESTINSN_bin("vmul.i16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
+    TESTINSN_bin("vmul.i8 q0, q1, q2", q0, q1, i32, 140, q2, i32, 120);
+    TESTINSN_bin("vmul.i8 q10, q11, q12", q10, q11, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
+    TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmul.i8 q10, q11, q12", q10, q11, i32, (1 << 25) + 0xfeb2, q12, i32, (1 << 13) + 0xdf);
+    TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12);
+    TESTINSN_bin("vmul.i8 q10, q13, q12", q10, q13, i32, (1 << 5) + 1, q12, i32, (1 << 3) + 2);
+    TESTINSN_bin("vmul.i16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmul.i32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120);
+    TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 3, q2, i32, 3);
+    TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 12, q2, i8, 0x0f);
+
+    printf("---- VMUL (by scalar) ----\n");
+    TESTINSN_bin("vmul.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmul.i32 q15, q8, d7[1]", q15, q8, i32, 140, d4, i32, -120);
+    TESTINSN_bin("vmul.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmul.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmul.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmul.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VMLA (by scalar) ----\n");
+    TESTINSN_bin("vmla.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmla.i32 q15, q8, d7[1]", q15, q8, i32, 140, d7, i32, -120);
+    TESTINSN_bin("vmla.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmla.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmla.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmla.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VMLS (by scalar) ----\n");
+    TESTINSN_bin("vmls.i32 q0, q1, d4[0]", q0, q1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmls.i32 q15, q8, d7[1]", q15, q8, i32, 140, d7, i32, -120);
+    TESTINSN_bin("vmls.i16 q10, q9, d7[3]", q10, q9, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmls.i16 q4, q5, d6[2]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmls.i32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmls.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmls.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmls.i16 q4, q5, d6[0]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmls.i32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VMULL (by scalar) ----\n");
+    TESTINSN_bin("vmull.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmull.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120);
+    TESTINSN_bin("vmull.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmull.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmull.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmull.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmull.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120);
+    TESTINSN_bin("vmull.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmull.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmull.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmull.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VMLAL (by scalar) ----\n");
+    TESTINSN_bin("vmlal.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmlal.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120);
+    TESTINSN_bin("vmlal.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlal.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmlal.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlal.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmlal.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120);
+    TESTINSN_bin("vmlal.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmlal.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlal.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmlal.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VMLSL (by scalar) ----\n");
+    TESTINSN_bin("vmlsl.s32 q0, d2, d4[0]", q0, d2, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmlsl.s32 q15, d8, d7[1]", q15, d8, i32, 140, d7, i32, -120);
+    TESTINSN_bin("vmlsl.s16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.s32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlsl.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmlsl.s16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.s32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlsl.u32 q0, d1, d4[0]", q0, d1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmlsl.u32 q15, d8, d7[1]", q15, d8, i32, 140, d4, i32, -120);
+    TESTINSN_bin("vmlsl.u16 q10, d31, d7[3]", q10, d31, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmlsl.u16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.u32 q4, d7, d15[1]", q4, d7, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlsl.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmlsl.u16 q4, d5, d6[0]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.u32 q7, d7, d1[1]", q7, d7, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VRSHR ----\n");
+    TESTINSN_un("vrshr.s8 q0, q1, #0", q0, q1, i32, -1);
+    TESTINSN_un("vrshr.s8 q0, q1, #1", q0, q1, i32, -1);
+    TESTINSN_un("vrshr.s16 q3, q4, #2", q3, q4, i32, -0x7c);
+    TESTINSN_un("vrshr.s32 q2, q5, #31", q2, q5, i32, -1);
+    TESTINSN_un("vrshr.s8 q6, q7, #7", q6, q7, i32, 0xffff);
+    TESTINSN_un("vrshr.s16 q8, q9, #12", q8, q9, i32, -10);
+    TESTINSN_un("vrshr.s32 q10, q11, #5", q10, q11, i32, 10234);
+    TESTINSN_un("vrshr.u8 q12, q13, #1", q12, q13, i32, -1);
+    TESTINSN_un("vrshr.u16 q14, q15, #11", q14, q15, i32, -1);
+    TESTINSN_un("vrshr.u32 q10, q11, #9", q10, q11, i32, 1000);
+    TESTINSN_un("vrshr.u8 q7, q13, #7", q7, q13, i32, -1);
+    TESTINSN_un("vrshr.u16 q8, q1, #5", q8, q1, i32, 0xabcf);
+    TESTINSN_un("vrshr.u32 q12, q3, #15", q12, q3, i32, -0x1b0);
+    TESTINSN_un("vrshr.u64 q0, q1, #42", q0, q1, i32, -1);
+    TESTINSN_un("vrshr.s64 q6, q7, #12", q6, q7, i32, 0xfac);
+    TESTINSN_un("vrshr.u64 q8, q4, #9", q8, q4, i32, 13560);
+    TESTINSN_un("vrshr.s64 q9, q12, #11", q9, q12, i32, 98710);
+
+    printf("---- VRSRA ----\n");
+    TESTINSN_un("vrsra.s8 q0, q1, #1", q0, q1, i32, -1);
+    TESTINSN_un("vrsra.s16 q3, q4, #2", q3, q4, i32, -0x7c);
+    TESTINSN_un("vrsra.s32 q2, q5, #31", q2, q5, i32, -1);
+    TESTINSN_un("vrsra.s8 q6, q7, #7", q6, q7, i32, 0xffff);
+    TESTINSN_un("vrsra.s16 q8, q9, #12", q8, q9, i32, -10);
+    TESTINSN_un("vrsra.s32 q10, q11, #5", q10, q11, i32, 10234);
+    TESTINSN_un("vrsra.u8 q12, q13, #1", q12, q13, i32, -1);
+    TESTINSN_un("vrsra.u16 q14, q15, #11", q14, q15, i32, -1);
+    TESTINSN_un("vrsra.u32 q10, q11, #9", q10, q11, i32, 1000);
+    TESTINSN_un("vrsra.u8 q7, q13, #7", q7, q13, i32, -1);
+    TESTINSN_un("vrsra.u16 q8, q1, #5", q8, q1, i32, 0xabcf);
+    TESTINSN_un("vrsra.u32 q12, q3, #15", q12, q3, i32, -0x1b0);
+    TESTINSN_un("vrsra.u64 q0, q1, #42", q0, q1, i32, -1);
+    TESTINSN_un("vrsra.s64 q6, q7, #12", q6, q7, i32, 0xfac);
+    TESTINSN_un("vrsra.u64 q8, q4, #9", q8, q4, i32, 13560);
+    TESTINSN_un("vrsra.s64 q9, q12, #11", q9, q12, i32, 98710);
+
+    printf("---- VSHR ----\n");
+    TESTINSN_un("vshr.s8 q0, q1, #0", q0, q1, i32, -1);
+    TESTINSN_un("vshr.s8 q0, q1, #1", q0, q1, i32, -1);
+    TESTINSN_un("vshr.s16 q3, q4, #2", q3, q4, i32, -0x7c);
+    TESTINSN_un("vshr.s32 q2, q5, #31", q2, q5, i32, -1);
+    TESTINSN_un("vshr.s8 q6, q7, #7", q6, q7, i32, 0xffff);
+    TESTINSN_un("vshr.s16 q8, q9, #12", q8, q9, i32, -10);
+    TESTINSN_un("vshr.s32 q10, q11, #5", q10, q11, i32, 10234);
+    TESTINSN_un("vshr.u8 q12, q13, #1", q12, q13, i32, -1);
+    TESTINSN_un("vshr.u16 q14, q15, #11", q14, q15, i32, -1);
+    TESTINSN_un("vshr.u32 q10, q11, #9", q10, q11, i32, 1000);
+    TESTINSN_un("vshr.u8 q7, q13, #7", q7, q13, i32, -1);
+    TESTINSN_un("vshr.u16 q8, q1, #5", q8, q1, i32, 0xabcf);
+    TESTINSN_un("vshr.u32 q12, q3, #15", q12, q3, i32, -0x1b0);
+    TESTINSN_un("vshr.u64 q0, q1, #42", q0, q1, i32, -1);
+    TESTINSN_un("vshr.s64 q6, q7, #12", q6, q7, i32, 0xfac);
+    TESTINSN_un("vshr.u64 q8, q4, #9", q8, q4, i32, 13560);
+    TESTINSN_un("vshr.s64 q9, q12, #11", q9, q12, i32, 98710);
+
+    printf("---- VSRA ----\n");
+    TESTINSN_un("vsra.s8 q0, q1, #1", q0, q1, i32, -1);
+    TESTINSN_un("vsra.s16 q3, q4, #2", q3, q4, i32, -0x7c);
+    TESTINSN_un("vsra.s32 q2, q5, #31", q2, q5, i32, -1);
+    TESTINSN_un("vsra.s8 q6, q7, #7", q6, q7, i32, 0xffff);
+    TESTINSN_un("vsra.s16 q8, q9, #12", q8, q9, i32, -10);
+    TESTINSN_un("vsra.s32 q10, q11, #5", q10, q11, i32, 10234);
+    TESTINSN_un("vsra.u8 q12, q13, #1", q12, q13, i32, -1);
+    TESTINSN_un("vsra.u16 q14, q15, #11", q14, q15, i32, -1);
+    TESTINSN_un("vsra.u32 q10, q11, #9", q10, q11, i32, 1000);
+    TESTINSN_un("vsra.u8 q7, q13, #7", q7, q13, i32, -1);
+    TESTINSN_un("vsra.u16 q8, q1, #5", q8, q1, i32, 0xabcf);
+    TESTINSN_un("vsra.u32 q12, q3, #15", q12, q3, i32, -0x1b0);
+    TESTINSN_un("vsra.u64 q0, q1, #42", q0, q1, i32, -1);
+    TESTINSN_un("vsra.s64 q6, q7, #12", q6, q7, i32, 0xfac);
+    TESTINSN_un("vsra.u64 q8, q4, #9", q8, q4, i32, 13560);
+    TESTINSN_un("vsra.s64 q9, q12, #11", q9, q12, i32, 98710);
+
+    printf("---- VSRI ----\n");
+    TESTINSN_un("vsri.16 q0, q1, #1", q0, q1, i32, -1);
+    TESTINSN_un("vsri.16 q3, q4, #2", q3, q4, i32, -0x7c);
+    TESTINSN_un("vsri.32 q2, q5, #31", q2, q5, i32, -1);
+    TESTINSN_un("vsri.8 q6, q7, #7", q6, q7, i32, 0xffff);
+    TESTINSN_un("vsri.16 q8, q9, #12", q8, q9, i32, -10);
+    TESTINSN_un("vsri.32 q10, q11, #5", q10, q11, i32, 10234);
+    TESTINSN_un("vsri.8 q12, q13, #1", q12, q13, i32, -1);
+    TESTINSN_un("vsri.16 q14, q15, #11", q14, q15, i32, -1);
+    TESTINSN_un("vsri.32 q10, q11, #9", q10, q11, i32, 1000);
+    TESTINSN_un("vsri.8 q7, q13, #7", q7, q13, i32, -1);
+    TESTINSN_un("vsri.16 q8, q1, #5", q8, q1, i32, 0xabcf);
+    TESTINSN_un("vsri.32 q12, q3, #15", q12, q3, i32, -0x1b0);
+    TESTINSN_un("vsri.64 q0, q1, #42", q0, q1, i32, -1);
+    TESTINSN_un("vsri.64 q6, q7, #12", q6, q7, i32, 0xfac);
+    TESTINSN_un("vsri.64 q8, q4, #9", q8, q4, i32, 13560);
+    TESTINSN_un("vsri.64 q9, q12, #11", q9, q12, i32, 98710);
+
+    printf("---- VMOVL ----\n");
+    TESTINSN_un("vmovl.u32 q0, d2", q0, d2, i32, 0x42);
+    TESTINSN_un("vmovl.u16 q15, d2", q15, d2, i32, 0x42);
+    TESTINSN_un("vmovl.u8 q3, d31", q0, d31, i32, 0x42);
+    TESTINSN_un("vmovl.s32 q0, d2", q0, d2, i32, 0x42);
+    TESTINSN_un("vmovl.s16 q15, d2", q15, d2, i32, 0x42);
+    TESTINSN_un("vmovl.s8 q3, d31", q0, d31, i32, 0x42);
+    TESTINSN_un("vmovl.u32 q0, d2", q0, d2, i8, 0xed);
+    TESTINSN_un("vmovl.u16 q15, d2", q15, d2, i8, 0xed);
+    TESTINSN_un("vmovl.u8 q3, d31", q0, d31, i8, 0xed);
+    TESTINSN_un("vmovl.s32 q0, d2", q0, d2, i8, 0xed);
+    TESTINSN_un("vmovl.s16 q15, d2", q15, d2, i8, 0xed);
+    TESTINSN_un("vmovl.s8 q3, d31", q0, d31, i8, 0xed);
+
+    printf("---- VABS ----\n");
+    TESTINSN_un("vabs.s32 q0, q1", q0, q1, i32, 0x73);
+    TESTINSN_un("vabs.s16 q15, q4", q15, q4, i32, 0x73);
+    TESTINSN_un("vabs.s8 q8, q7", q8, q7, i32, 0x73);
+    TESTINSN_un("vabs.s32 q0, q1", q0, q1, i32, 0xfe);
+    TESTINSN_un("vabs.s16 q15, q4", q15, q4, i32, 0xef);
+    TESTINSN_un("vabs.s8 q8, q7", q8, q7, i32, 0xde);
+    TESTINSN_un("vabs.s32 q0, q1", q0, q1, i16, 0xfe0a);
+    TESTINSN_un("vabs.s16 q15, q4", q15, q4, i16, 0xef0b);
+    TESTINSN_un("vabs.s8 q8, q7", q8, q7, i16, 0xde0c);
+
+    printf("---- VQABS ----\n");
+    TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 0x73);
+    TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 1 << 31);
+    TESTINSN_un_q("vqabs.s16 q0, q1", q0, q1, i32, 1 << 31);
+    TESTINSN_un_q("vqabs.s8 q0, q1", q0, q1, i32, 1 << 31);
+    TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i32, 0x73);
+    TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i32, 0x73);
+    TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i32, 0xfe);
+    TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i32, 0xef);
+    TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i32, 0xde);
+    TESTINSN_un_q("vqabs.s32 q0, q1", q0, q1, i16, 0xfe0a);
+    TESTINSN_un_q("vqabs.s16 q15, q4", q15, q4, i16, 0xef0b);
+    TESTINSN_un_q("vqabs.s8 q8, q7", q8, q7, i16, 0xde0c);
+
+    printf("---- VADDW ----\n");
+    TESTINSN_bin("vaddw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0x12);
+    TESTINSN_bin("vaddw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0xe2);
+    TESTINSN_bin("vaddw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
+
+    printf("---- VADDL ----\n");
+    TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0x12);
+    TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0xe2);
+    TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i8, 0x99, d31, i8, 0x12);
+    TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vaddl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.s8 q0, d2, d31", q0, d2, i8, 0x93, d31, i8, 0xe2);
+    TESTINSN_bin("vaddl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
+    TESTINSN_bin("vaddl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
+
+    printf("---- VSUBW ----\n");
+    TESTINSN_bin("vsubw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0x12);
+    TESTINSN_bin("vsubw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubw.s32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubw.s16 q15, q14, d4", q15, q14, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubw.s8 q0, q1, d31", q0, q1, i32, 0x73, d31, i8, 0xe2);
+    TESTINSN_bin("vsubw.u32 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubw.u16 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubw.u8 q0, q1, d4", q0, q1, i32, 0x73, d4, i8, 0xe2);
+
+    printf("---- VSUBL ----\n");
+    TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0x12);
+    TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i32, 0x73, d31, i8, 0xe2);
+    TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i32, 0x73, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i8, 0x99, d31, i8, 0x12);
+    TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0x12);
+    TESTINSN_bin("vsubl.s32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.s16 q15, d14, d4", q15, d14, i8, 0x93, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.s8 q0, d2, d31", q0, d2, i8, 0x93, d31, i8, 0xe2);
+    TESTINSN_bin("vsubl.u32 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.u16 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
+    TESTINSN_bin("vsubl.u8 q0, d2, d4", q0, d2, i8, 0x93, d4, i8, 0xe2);
+
+    printf("---- VCEQ #0 ----\n");
+    TESTINSN_un("vceq.i32 q0, q1, #0", q0, q1, i32, 0x21);
+    TESTINSN_un("vceq.i16 q2, q1, #0", q2, q1, i32, 0x21);
+    TESTINSN_un("vceq.i8 q10, q11, #0", q10, q11, i32, 0x21);
+    TESTINSN_un("vceq.i32 q0, q1, #0", q0, q1, i32, 0x0);
+    TESTINSN_un("vceq.i16 q2, q1, #0", q2, q1, i32, 0x0);
+    TESTINSN_un("vceq.i8 q10, q11, #0", q10, q11, i32, 0x0);
+
+    printf("---- VCGT #0 ----\n");
+    TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i32, 0x21);
+    TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i32, 0x21);
+    TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i32, 0x21);
+    TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i32, 0x0);
+    TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i32, 0x0);
+    TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i32, 0x0);
+    TESTINSN_un("vcgt.s32 q0, q1, #0", q0, q1, i8, 0xef);
+    TESTINSN_un("vcgt.s16 q2, q1, #0", q2, q1, i8, 0xed);
+    TESTINSN_un("vcgt.s8 q10, q11, #0", q10, q11, i8, 0xae);
+
+    printf("---- VCGE #0 ----\n");
+    TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0x21);
+    TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0x21);
+    TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0x21);
+    TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0x0);
+    TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0x0);
+    TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0x0);
+    TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i8, 0xef);
+    TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i8, 0xed);
+    TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i8, 0xae);
+    TESTINSN_un("vcge.s32 q0, q1, #0", q0, q1, i32, 0xef);
+    TESTINSN_un("vcge.s16 q2, q1, #0", q2, q1, i32, 0xed);
+    TESTINSN_un("vcge.s8 q10, q11, #0", q10, q11, i32, 0xae);
+
+    printf("---- VCLE #0 ----\n");
+    TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i32, 0x21);
+    TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i32, 0x21);
+    TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i32, 0x21);
+    TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i32, 0x0);
+    TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i32, 0x0);
+    TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i32, 0x0);
+    TESTINSN_un("vcle.s32 q0, q1, #0", q0, q1, i8, 0xef);
+    TESTINSN_un("vcle.s16 q2, q1, #0", q2, q1, i8, 0xed);
+    TESTINSN_un("vcle.s8 q10, q11, #0", q10, q11, i8, 0xae);
+
+    printf("---- VCLT #0 ----\n");
+    TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0x21);
+    TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0x21);
+    TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0x21);
+    TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0x0);
+    TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0x0);
+    TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0x0);
+    TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i8, 0xef);
+    TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i8, 0xed);
+    TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i8, 0xae);
+    TESTINSN_un("vclt.s32 q0, q1, #0", q0, q1, i32, 0xef);
+    TESTINSN_un("vclt.s16 q2, q1, #0", q2, q1, i32, 0xed);
+    TESTINSN_un("vclt.s8 q10, q11, #0", q10, q11, i32, 0xae);
+
+    printf("---- VCNT ----\n");
+    TESTINSN_un("vcnt.8 q0, q1", q0, q1, i32, 0xac3d25eb);
+    TESTINSN_un("vcnt.8 q11, q14", q11, q14, i32, 0xac3d25eb);
+    TESTINSN_un("vcnt.8 q6, q2", q6, q2, i32, 0xad0eb);
+
+    printf("---- VCLS ----\n");
+    TESTINSN_un("vcls.s8 q0, q1", q0, q1, i32, 0x21);
+    TESTINSN_un("vcls.s8 q10, q15", q10, q15, i8, 0x82);
+    TESTINSN_un("vcls.s16 q0, q1", q0, q1, i32, 0x21);
+    TESTINSN_un("vcls.s16 q15, q10", q15, q10, i8, 0x82);
+    TESTINSN_un("vcls.s32 q6, q1", q6, q1, i32, 0x21);
+    TESTINSN_un("vcls.s32 q10, q5", q10, q5, i8, 0x82);
+    TESTINSN_un("vcls.s8 q2, q4", q2, q4, i8, 0xff);
+    TESTINSN_un("vcls.s16 q2, q4", q2, q4, i8, 0xff);
+    TESTINSN_un("vcls.s32 q2, q4", q2, q4, i8, 0xff);
+    TESTINSN_un("vcls.s8 q2, q4", q2, q4, i16, 0xffef);
+    TESTINSN_un("vcls.s16 q2, q4", q2, q4, i16, 0xffef);
+    TESTINSN_un("vcls.s32 q2, q4", q2, q4, i16, 0xffef);
+    TESTINSN_un("vcls.s8 q2, q4", q2, q4, i8, 0x00);
+    TESTINSN_un("vcls.s16 q2, q4", q2, q4, i8, 0x00);
+    TESTINSN_un("vcls.s32 q2, q4", q2, q4, i8, 0x00);
+    TESTINSN_un("vcls.s8 q2, q4", q2, q4, i16, 0x00ef);
+    TESTINSN_un("vcls.s16 q2, q4", q2, q4, i16, 0x00ef);
+    TESTINSN_un("vcls.s32 q2, q4", q2, q4, i16, 0x00ef);
+
+    printf("---- VCLZ ----\n");
+    TESTINSN_un("vclz.i8 q0, q1", q0, q1, i32, 0x21);
+    TESTINSN_un("vclz.i8 q10, q15", q10, q15, i8, 0x82);
+    TESTINSN_un("vclz.i16 q0, q1", q0, q1, i32, 0x21);
+    TESTINSN_un("vclz.i16 q15, q10", q15, q10, i8, 0x82);
+    TESTINSN_un("vclz.i32 q6, q1", q6, q1, i32, 0x21);
+    TESTINSN_un("vclz.i32 q10, q5", q10, q5, i8, 0x82);
+    TESTINSN_un("vclz.i8 q2, q4", q2, q4, i8, 0xff);
+    TESTINSN_un("vclz.i16 q2, q4", q2, q4, i8, 0xff);
+    TESTINSN_un("vclz.i32 q2, q4", q2, q4, i8, 0xff);
+    TESTINSN_un("vclz.i8 q2, q4", q2, q4, i16, 0xffef);
+    TESTINSN_un("vclz.i16 q2, q4", q2, q4, i16, 0xffef);
+    TESTINSN_un("vclz.i32 q2, q4", q2, q4, i16, 0xffef);
+    TESTINSN_un("vclz.i8 q2, q4", q2, q4, i8, 0x00);
+    TESTINSN_un("vclz.i16 q2, q4", q2, q4, i8, 0x00);
+    TESTINSN_un("vclz.i32 q2, q4", q2, q4, i8, 0x00);
+    TESTINSN_un("vclz.i8 q2, q4", q2, q4, i16, 0x00ef);
+    TESTINSN_un("vclz.i16 q2, q4", q2, q4, i16, 0x00ef);
+    TESTINSN_un("vclz.i32 q2, q4", q2, q4, i16, 0x00ef);
+
+    printf("---- VSLI ----\n");
+    TESTINSN_un("vsli.16 q0, q1, #1", q0, q1, i32, -1);
+    TESTINSN_un("vsli.16 q3, q4, #2", q3, q4, i32, -0x7c);
+    TESTINSN_un("vsli.32 q2, q5, #31", q2, q5, i32, -1);
+    TESTINSN_un("vsli.8 q6, q7, #7", q6, q7, i32, 0xffff);
+    TESTINSN_un("vsli.16 q8, q9, #12", q8, q9, i32, -10);
+    TESTINSN_un("vsli.32 q10, q11, #5", q10, q11, i32, 10234);
+    TESTINSN_un("vsli.8 q12, q13, #1", q12, q13, i32, -1);
+    TESTINSN_un("vsli.16 q14, q15, #11", q14, q15, i32, -1);
+    TESTINSN_un("vsli.32 q10, q11, #9", q10, q11, i32, 1000);
+    TESTINSN_un("vsli.8 q7, q13, #7", q7, q13, i32, -1);
+    TESTINSN_un("vsli.16 q8, q1, #1", q8, q1, i32, 0xabcf);
+    TESTINSN_un("vsli.32 q12, q3, #15", q12, q3, i32, -0x1b0);
+    TESTINSN_un("vsli.64 q0, q1, #42", q0, q1, i32, -1);
+    TESTINSN_un("vsli.64 q6, q7, #12", q6, q7, i32, 0xfac);
+    TESTINSN_un("vsli.64 q8, q4, #9", q8, q4, i32, 13560);
+    TESTINSN_un("vsli.64 q9, q12, #11", q9, q12, i32, 98710);
+
+    printf("---- VPADDL ----\n");
+    TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, 24);
+    TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpaddl.u16 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpaddl.u8 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpaddl.u8 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.u16 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.u32 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.u32 q10, q11", q10, q11, i32, 24);
+    TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, 24);
+    TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpaddl.s16 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpaddl.s8 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpaddl.s8 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.s16 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.s32 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.s32 q10, q11", q10, q11, i32, 24);
+
+    printf("---- VPADAL ----\n");
+    TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, 24);
+    TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpadal.u16 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpadal.u8 q0, q1", q0, q1, i8, 140);
+    TESTINSN_un("vpadal.u8 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.u16 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.u32 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.u32 q10, q11", q10, q11, i32, 24);
+    TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, 24);
+    TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpadal.s16 q0, q1", q0, q1, i32, 140);
+    TESTINSN_un("vpadal.s8 q0, q1", q0, q1, i8, 140);
+    TESTINSN_un("vpadal.s8 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.s16 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.s32 q0, q1", q0, q1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.s32 q10, q11", q10, q11, i32, 24);
+
+    printf("---- VZIP ----\n");
+    TESTINSN_dual("vzip.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34);
+    TESTINSN_dual("vzip.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34);
+    TESTINSN_dual("vzip.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34);
+    TESTINSN_dual("vzip.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vzip.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vzip.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d);
+
+    printf("---- VUZP ----\n");
+    TESTINSN_dual("vuzp.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34);
+    TESTINSN_dual("vuzp.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34);
+    TESTINSN_dual("vuzp.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34);
+    TESTINSN_dual("vuzp.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vuzp.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vuzp.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d);
+
+    printf("---- VTRN ----\n");
+    TESTINSN_dual("vtrn.32 q0, q1", q0, i8, 0x12, q1, i8, 0x34);
+    TESTINSN_dual("vtrn.16 q1, q0", q0, i8, 0x12, q1, i8, 0x34);
+    TESTINSN_dual("vtrn.8 q10, q11", q10, i8, 0x12, q11, i8, 0x34);
+    TESTINSN_dual("vtrn.32 q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vtrn.16 q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vtrn.8 q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d);
+
+    printf("---- VSWP ----\n");
+    TESTINSN_dual("vswp q0, q1", q0, i8, 0x12, q1, i8, 0x34);
+    TESTINSN_dual("vswp q1, q0", q0, i8, 0x12, q1, i8, 0x34);
+    TESTINSN_dual("vswp q10, q11", q10, i8, 0x12, q11, i8, 0x34);
+    TESTINSN_dual("vswp q0, q1", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vswp q1, q0", q0, i32, 0x12345678, q1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vswp q10, q11", q10, i32, 0x12345678, q11, i32, 0x0a0b0c0d);
+
+    printf("---- VDUP ----\n");
+    TESTINSN_un("vdup.8 q2, d2[0]", q2, d2, i32, 0xabc4657);
+    TESTINSN_un("vdup.8 q3, d3[2]", q3, d3, i32, 0x7a1b3);
+    TESTINSN_un("vdup.8 q1, d0[7]", q1, d0, i32, 0x713aaa);
+    TESTINSN_un("vdup.8 q0, d4[3]", q0, d4, i32, 0xaa713);
+    TESTINSN_un("vdup.8 q4, d28[4]", q4, d28, i32, 0x7b1c3);
+    TESTINSN_un("vdup.16 q7, d19[3]", q7, d19, i32, 0x713ffff);
+    TESTINSN_un("vdup.16 q15, d31[0]", q15, d31, i32, 0x7f00fa);
+    TESTINSN_un("vdup.16 q6, d2[0]", q6, d2, i32, 0xffabcde);
+    TESTINSN_un("vdup.16 q8, d22[3]", q8, d22, i32, 0x713);
+    TESTINSN_un("vdup.16 q9, d2[0]", q9, d2, i32, 0x713);
+    TESTINSN_un("vdup.32 q10, d17[1]", q10, d17, i32, 0x713);
+    TESTINSN_un("vdup.32 q15, d11[0]", q15, d11, i32, 0x3);
+    TESTINSN_un("vdup.32 q10, d29[1]", q10, d29, i32, 0xf00000aa);
+    TESTINSN_un("vdup.32 q12, d0[1]", q12, d0, i32, 0xf);
+    TESTINSN_un("vdup.32 q13, d13[0]", q13, d13, i32, -1);
+
+    printf("---- VQDMULL ----\n");
+    TESTINSN_bin_q("vqdmull.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqdmull.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin_q("vqdmull.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin_q("vqdmull.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmull.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmull.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmull.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+
+    printf("---- VQDMULL (by scalar) ----\n");
+    TESTINSN_bin_q("vqdmull.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120);
+    TESTINSN_bin_q("vqdmull.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120);
+    TESTINSN_bin_q("vqdmull.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12);
+    TESTINSN_bin_q("vqdmull.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmull.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmull.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmull.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmull.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmull.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmull.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30);
+
+    printf("---- VQDMLSL ----\n");
+    TESTINSN_bin_q("vqdmlsl.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqdmlsl.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin_q("vqdmlsl.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmlsl.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+
+    printf("---- VQDMLSL (by scalar) ----\n");
+    TESTINSN_bin_q("vqdmlsl.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120);
+    TESTINSN_bin_q("vqdmlsl.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120);
+    TESTINSN_bin_q("vqdmlsl.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12);
+    TESTINSN_bin_q("vqdmlsl.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlsl.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmlsl.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlsl.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlsl.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30);
+
+    printf("---- VQDMLAL ----\n");
+    TESTINSN_bin_q("vqdmlal.s32 q0, d1, d2", q0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqdmlal.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin_q("vqdmlal.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmlal.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+
+    printf("---- VQDMLAL (by scalar) ----\n");
+    TESTINSN_bin_q("vqdmlal.s32 q0, d1, d7[0]", q0, d1, i32, 24, d7, i32, 120);
+    TESTINSN_bin_q("vqdmlal.s32 q6, d7, d6[0]", q6, d7, i32, 140, d6, i32, -120);
+    TESTINSN_bin_q("vqdmlal.s16 q9, d11, d7[2]", q9, d11, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[1]", q4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[0]", q7, d8, i32, (1 << 31), d3, i32, 12);
+    TESTINSN_bin_q("vqdmlal.s16 q4, d5, d6[2]", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmlal.s32 q7, d8, d3[1]", q7, d8, i32, (1 << 31) + 1, d3, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmlal.s32 q10, d11, d15[1]", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmlal.s32 q10, d30, d1[0]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlal.s16 q10, d30, d1[1]", q10, d30, i32, 1 << 31, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlal.s32 q10, d30, d1[1]", q10, d30, i32, 1 << 30, d1, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmlal.s16 q10, d30, d1[3]", q10, d30, i32, 1 << 31, d1, i32, 1 << 30);
+
+    printf("---- VQDMULH ----\n");
+    TESTINSN_bin_q("vqdmulh.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin_q("vqdmulh.s32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120);
+    TESTINSN_bin_q("vqdmulh.s16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
+    TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12);
+    TESTINSN_bin_q("vqdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120);
+    TESTINSN_bin_q("vqdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 30, q15, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 30);
+
+    printf("---- VQDMULH (by scalar) ----\n");
+    TESTINSN_bin_q("vqdmulh.s32 q0, q1, d6[0]", q0, q1, i32, 24, d6, i32, 120);
+    TESTINSN_bin_q("vqdmulh.s32 q6, q7, d1[1]", q6, q7, i32, 140, d1, i32, -120);
+    TESTINSN_bin_q("vqdmulh.s16 q9, q11, d7[0]", q9, q11, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[1]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[1]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin_q("vqdmulh.s16 q4, q5, d6[2]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 q10, q11, d15[0]", q10, q11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s16 q10, q14, d7[3]", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 30, d15, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s16 q10, q14, d7[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 30);
+
+    printf("---- VSHL (immediate) ----\n");
+    TESTINSN_un("vshl.i64 q0, q1, #1", q0, q1, i32, 24);
+    TESTINSN_un("vshl.i64 q5, q2, #1", q5, q2, i32, (1 << 30));
+    TESTINSN_un("vshl.i64 q9, q12, #2", q9, q12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshl.i64 q11, q2, #12", q11, q2, i32, -1);
+    TESTINSN_un("vshl.i64 q15, q12, #63", q15, q12, i32, 5);
+    TESTINSN_un("vshl.i64 q5, q12, #62", q5, q12, i32, (1 << 31) + 1);
+    TESTINSN_un("vshl.i32 q0, q1, #1", q0, q1, i32, 24);
+    TESTINSN_un("vshl.i32 q5, q2, #1", q5, q2, i32, (1 << 30));
+    TESTINSN_un("vshl.i32 q9, q12, #2", q9, q12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshl.i32 q11, q2, #12", q11, q2, i32, -1);
+    TESTINSN_un("vshl.i32 q15, q12, #20", q15, q12, i32, 5);
+    TESTINSN_un("vshl.i32 q5, q12, #30", q5, q12, i32, (1 << 31) + 1);
+    TESTINSN_un("vshl.i16 q0, q1, #1", q0, q1, i16, 24);
+    TESTINSN_un("vshl.i16 q5, q2, #1", q5, q2, i32, (1 << 30));
+    TESTINSN_un("vshl.i16 q9, q12, #2", q9, q12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshl.i16 q11, q2, #12", q11, q2, i16, -1);
+    TESTINSN_un("vshl.i16 q15, q12, #3", q15, q12, i16, 5);
+    TESTINSN_un("vshl.i16 q5, q12, #14", q5, q12, i32, (1 << 31) + 1);
+    TESTINSN_un("vshl.i8 q0, q1, #1", q0, q1, i8, 24);
+    TESTINSN_un("vshl.i8 q5, q2, #1", q5, q2, i32, (1 << 30));
+    TESTINSN_un("vshl.i8 q9, q12, #2", q9, q12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshl.i8 q11, q2, #7", q11, q2, i8, -1);
+    TESTINSN_un("vshl.i8 q15, q12, #3", q15, q12, i8, 5);
+    TESTINSN_un("vshl.i8 q5, q12, #6", q5, q12, i32, (1 << 31) + 1);
+
+    printf("---- VNEG ----\n");
+    TESTINSN_un("vneg.s32 q0, q1", q0, q1, i32, 0x73);
+    TESTINSN_un("vneg.s16 q15, q4", q15, q4, i32, 0x73);
+    TESTINSN_un("vneg.s8 q8, q7", q8, q7, i32, 0x73);
+    TESTINSN_un("vneg.s32 q0, q1", q0, q1, i32, 0xfe);
+    TESTINSN_un("vneg.s16 q15, q4", q15, q4, i32, 0xef);
+    TESTINSN_un("vneg.s8 q8, q7", q8, q7, i32, 0xde);
+    TESTINSN_un("vneg.s32 q0, q1", q0, q1, i16, 0xfe0a);
+    TESTINSN_un("vneg.s16 q15, q4", q15, q4, i16, 0xef0b);
+    TESTINSN_un("vneg.s8 q8, q7", q8, q7, i16, 0xde0c);
+
+    printf("---- VQNEG ----\n");
+    TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 0x73);
+    TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 1 << 31);
+    TESTINSN_un_q("vqneg.s16 q0, q1", q0, q1, i32, 1 << 31);
+    TESTINSN_un_q("vqneg.s8 q0, q1", q0, q1, i32, 1 << 31);
+    TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i32, 0x73);
+    TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i32, 0x73);
+    TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i32, 0xfe);
+    TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i32, 0xef);
+    TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i32, 0xde);
+    TESTINSN_un_q("vqneg.s32 q0, q1", q0, q1, i16, 0xfe0a);
+    TESTINSN_un_q("vqneg.s16 q15, q4", q15, q4, i16, 0xef0b);
+    TESTINSN_un_q("vqneg.s8 q8, q7", q8, q7, i16, 0xde0c);
+
+    printf("---- VREV ----\n");
+    TESTINSN_un("vrev64.8 q0, q1", q0, q1, i32, 0xaabbccdd);
+    TESTINSN_un("vrev64.16 q10, q15", q10, q15, i32, 0xaabbccdd);
+    TESTINSN_un("vrev64.32 q1, q14", q1, q14, i32, 0xaabbccdd);
+    TESTINSN_un("vrev32.8 q0, q1", q0, q1, i32, 0xaabbccdd);
+    TESTINSN_un("vrev32.16 q10, q15", q10, q15, i32, 0xaabbccdd);
+    TESTINSN_un("vrev16.8 q0, q1", q0, q1, i32, 0xaabbccdd);
+
+    printf("---- VSHLL ----\n");
+    TESTINSN_un("vshll.s32 q0, d1, #1", q0, d1, i32, 24);
+    TESTINSN_un("vshll.s32 q5, d2, #1", q5, d2, i32, (1 << 30));
+    TESTINSN_un("vshll.s32 q9, d12, #2", q9, d12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshll.u32 q11, d2, #12", q11, d2, i32, -1);
+    TESTINSN_un("vshll.u32 q15, d12, #20", q15, d12, i32, 5);
+    TESTINSN_un("vshll.u32 q5, d22, #30", q5, d22, i32, (1 << 31) + 1);
+    TESTINSN_un("vshll.s16 q0, d1, #1", q0, d1, i16, 24);
+    TESTINSN_un("vshll.s16 q5, d2, #1", q5, d2, i32, (1 << 30));
+    TESTINSN_un("vshll.s16 q9, d12, #2", q9, d12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshll.u16 q11, d2, #12", q11, d2, i16, -1);
+    TESTINSN_un("vshll.u16 q15, d22, #3", q15, d22, i16, 5);
+    TESTINSN_un("vshll.u16 q5, d12, #14", q5, d12, i32, (1 << 31) + 1);
+    TESTINSN_un("vshll.s8 q0, d1, #1", q0, d1, i8, 24);
+    TESTINSN_un("vshll.s8 q5, d2, #1", q5, d2, i32, (1 << 30));
+    TESTINSN_un("vshll.s8 q9, d12, #2", q9, d12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshll.u8 q11, d2, #7", q11, d2, i8, -1);
+    TESTINSN_un("vshll.u8 q15, d19, #3", q15, d19, i8, 5);
+    TESTINSN_un("vshll.u8 q5, d12, #6", q5, d12, i32, (1 << 31) + 1);
+
+    printf("---- VSHLL (max shift) ----\n");
+    TESTINSN_un("vshll.i32 q0, d1, #32", q0, d1, i32, 24);
+    TESTINSN_un("vshll.i32 q5, d2, #32", q5, d2, i32, (1 << 30));
+    TESTINSN_un("vshll.i32 q11, d2, #32", q11, d2, i32, -1);
+    TESTINSN_un("vshll.i32 q15, d12, #32", q15, d12, i32, 5);
+    TESTINSN_un("vshll.i16 q0, d1, #16", q0, d1, i16, 24);
+    TESTINSN_un("vshll.i16 q5, d2, #16", q5, d2, i32, (1 << 30));
+    TESTINSN_un("vshll.i16 q11, d2, #16", q11, d2, i16, -1);
+    TESTINSN_un("vshll.i16 q15, d22, #16", q15, d22, i16, 5);
+    TESTINSN_un("vshll.i8 q0, d1, #8", q0, d1, i8, 24);
+    TESTINSN_un("vshll.i8 q5, d2, #8", q5, d2, i32, (1 << 30));
+    TESTINSN_un("vshll.i8 q11, d2, #8", q11, d2, i8, -1);
+    TESTINSN_un("vshll.i8 q15, d19, #8", q15, d19, i8, 5);
+
+    printf("---- VMULL ----\n");
+    TESTINSN_bin("vmull.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmull.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmull.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmull.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmull.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmull.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmull.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmull.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmull.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmull.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmull.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmull.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmull.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmull.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmull.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmull.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
+    TESTINSN_bin("vmull.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin("vmull.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmull.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin("vmull.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
+    TESTINSN_bin("vmull.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin("vmull.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmull.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin("vmull.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.p8 q9, d11, d12", q9, d11, i32, 0x1a4b0c, d12, i32, 0xd1e2f0);
+    TESTINSN_bin("vmull.p8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmull.p8 q4, d15, d26", q4, d15, i32, (1 << 14) - 0xabcd, d26, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmull.p8 q14, d5, d6", q14, d5, i32, (1 << 28) + 0xefe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmull.p8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmull.p8 q10, d27, d31", q10, d27, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmull.p8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmull.p8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmull.p8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+
+    printf("---- VMLAL ----\n");
+    TESTINSN_bin("vmlal.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmlal.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmlal.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmlal.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlal.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmlal.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmlal.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmlal.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmlal.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlal.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmlal.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmlal.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmlal.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlal.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmlal.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmlal.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmlal.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmlal.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlal.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmlal.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
+    TESTINSN_bin("vmlal.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin("vmlal.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlal.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin("vmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlal.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlal.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
+    TESTINSN_bin("vmlal.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin("vmlal.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlal.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin("vmlal.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlal.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+
+    printf("---- VMLSL ----\n");
+    TESTINSN_bin("vmlsl.s8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmlsl.s8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmlsl.s8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmlsl.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlsl.s8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmlsl.u8 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmlsl.u8 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmlsl.u8 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmlsl.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlsl.u8 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmlsl.s16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmlsl.s16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmlsl.s16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlsl.s16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmlsl.u16 q0, d1, d12", q0, d1, i32, 0xabcd4, d12, i32, 0xcefab1);
+    TESTINSN_bin("vmlsl.u16 q9, d11, d12", q9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 0xaa2);
+    TESTINSN_bin("vmlsl.u16 q4, d5, d6", q4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 0x2bbc2d);
+    TESTINSN_bin("vmlsl.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlsl.u16 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+    TESTINSN_bin("vmlsl.s32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
+    TESTINSN_bin("vmlsl.s32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin("vmlsl.s32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlsl.s32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin("vmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlsl.s32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlsl.u32 q0, d1, d2", q0, d1, i32, 0xaabbcc4, d2, i32, 0x1b2c0a);
+    TESTINSN_bin("vmlsl.u32 q6, d7, d8", q6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin("vmlsl.u32 q7, d8, d9", q7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmlsl.u32 q10, d11, d15", q10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin("vmlsl.u32 q10, d30, d31", q10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin("vmlsl.u32 q10, d30, d31", q10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+
+    printf("---- VQRDMULH ----\n");
+    TESTINSN_bin_q("vqrdmulh.s32 q0, q1, q2", q0, q1, i32, 24, q2, i32, 120);
+    TESTINSN_bin_q("vqrdmulh.s32 q6, q7, q8", q6, q7, i32, 140, q8, i32, -120);
+    TESTINSN_bin_q("vqrdmulh.s16 q9, q11, q12", q9, q11, i32, 0x140, q12, i32, 0x120);
+    TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) + 1, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 14) - 0xabcd, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31), q9, i32, 12);
+    TESTINSN_bin_q("vqrdmulh.s16 q4, q5, q6", q4, q5, i32, (1 << 28) + 0xfe, q6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 q7, q8, q9", q7, q8, i32, (1 << 31) + 1, q9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 q10, q11, q15", q10, q11, i32, 24, q15, i32, 120);
+    TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
+    TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, (1 << 31) + 1);
+    TESTINSN_bin_q("vqrdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 31);
+    TESTINSN_bin_q("vqrdmulh.s32 q10, q14, q15", q10, q14, i32, 1 << 30, q15, i32, 1 << 31);
+    TESTINSN_bin_q("vqrdmulh.s16 q10, q14, q15", q10, q14, i32, 1 << 31, q15, i32, 1 << 30);
+
+    printf("---- VQRDMULH (by scalar) ----\n");
+    TESTINSN_bin_q("vqrdmulh.s32 q0, q1, d6[0]", q0, q1, i32, 24, d6, i32, 120);
+    TESTINSN_bin_q("vqrdmulh.s32 q6, q7, d1[1]", q6, q7, i32, 140, d1, i32, -120);
+    TESTINSN_bin_q("vqrdmulh.s16 q9, q11, d7[0]", q9, q11, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[0]", q4, q5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[1]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[1]", q4, q5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin_q("vqrdmulh.s16 q4, q5, d6[2]", q4, q5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 q7, q8, d9[0]", q7, q8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 q10, q11, d15[0]", q10, q11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqrdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 31);
+    TESTINSN_bin_q("vqrdmulh.s16 q10, q14, d7[3]", q10, q14, i32, 1 << 31, q15, i32, (1 << 31) + 1);
+    TESTINSN_bin_q("vqrdmulh.s32 q10, q14, d15[1]", q10, q14, i32, 1 << 30, d15, i32, 1 << 31);
+    TESTINSN_bin_q("vqrdmulh.s16 q10, q14, d7[1]", q10, q14, i32, 1 << 31, d7, i32, 1 << 30);
+
+    printf("---- VADD (fp) ----\n");
+    TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vadd.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vadd.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vadd.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vadd.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vadd.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vadd.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vadd.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vadd.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vadd.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vadd.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vadd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VSUB (fp) ----\n");
+    TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(24.89), q5, i32, f2u(1346));
+    TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vsub.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vsub.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vsub.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vsub.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vsub.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vsub.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vsub.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vsub.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vsub.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vsub.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vsub.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VABD (fp) ----\n");
+    TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vabd.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vabd.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vabd.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vabd.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vabd.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vabd.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vabd.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vabd.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vabd.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vabd.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vabd.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VMUL (fp) ----\n");
+    TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vmul.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vmul.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vmul.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vmul.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vmul.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vmul.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vmul.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vmul.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vmul.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vmul.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmul.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VMLA (fp) ----\n");
+    TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin_f("vmla.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin_f("vmla.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin_f("vmla.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin_f("vmla.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin_f("vmla.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin_f("vmla.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin_f("vmla.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin_f("vmla.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin_f("vmla.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin_f("vmla.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VMLA (fp by scalar) ----\n");
+    TESTINSN_bin_f("vmla.f32 q0, q1, d4[0]", q0, q1, i32, f2u(24), d4, i32, f2u(120));
+    TESTINSN_bin_f("vmla.f32 q15, q8, d7[1]", q15, q8, i32, f2u(140), d7, i32, f2u(-120));
+    TESTINSN_bin_f("vmla.f32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin_f("vmla.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin_f("vmla.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+    TESTINSN_bin_f("vmla.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e22), d1, i32, f2u(1e-19));
+    TESTINSN_bin_f("vmla.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e12), d1, i32, f2u(1e11));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VMLS (fp) ----\n");
+    TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin_f("vmls.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin_f("vmls.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin_f("vmls.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin_f("vmls.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin_f("vmls.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin_f("vmls.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin_f("vmls.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin_f("vmls.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin_f("vmls.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin_f("vmls.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VMLS (fp by scalar) ----\n");
+    TESTINSN_bin_f("vmls.f32 q0, q1, d4[0]", q0, q1, i32, f2u(24), d4, i32, f2u(120));
+    TESTINSN_bin_f("vmls.f32 q15, q8, d7[1]", q15, q8, i32, f2u(140), d7, i32, f2u(-120));
+    TESTINSN_bin_f("vmls.f32 q4, q8, d15[1]", q4, q8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin_f("vmls.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin_f("vmls.f32 q7, q8, d1[1]", q7, q8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+    TESTINSN_bin_f("vmls.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e22), d1, i32, f2u(1e-19));
+    TESTINSN_bin_f("vmls.f32 q7, q8, d1[0]", q7, q8, i32, f2u(1e12), d1, i32, f2u(1e11));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 q0, q1, d2[0]", q0, q1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VCVT (integer <-> fp) ----\n");
+    TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vcvt.u32.f32 q10, q11", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vcvt.u32.f32 q15, q4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vcvt.u32.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vcvt.u32.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vcvt.s32.f32 q10, q11", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vcvt.s32.f32 q15, q4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vcvt.s32.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vcvt.s32.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, 7);
+    TESTINSN_un("vcvt.f32.u32 q10, q11", q10, q11, i32, 1 << 31);
+    TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vcvt.f32.u32 q0, q1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vcvt.f32.u32 q0, q14", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, 7);
+    TESTINSN_un("vcvt.f32.s32 q10, q11", q10, q11, i32, 1 << 31);
+    TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vcvt.f32.s32 q0, q1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vcvt.f32.s32 q0, q14", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vcvt.u32.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
+    TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vcvt.s32.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VCVT (fixed <-> fp) ----\n");
+    TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vcvt.u32.f32 q10, q11, #1", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vcvt.u32.f32 q15, q4, #32", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vcvt.u32.f32 q15, q4, #7", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vcvt.u32.f32 q15, q4, #4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vcvt.u32.f32 q12, q8, #3", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vcvt.u32.f32 q12, q8, #3", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vcvt.s32.f32 q0, q1, #5", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vcvt.s32.f32 q10, q11, #1", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vcvt.s32.f32 q15, q4, #8", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vcvt.s32.f32 q15, q4, #2", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vcvt.s32.f32 q15, q4, #1", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vcvt.s32.f32 q12, q8, #2", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vcvt.s32.f32 q12, q8, #2", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vcvt.f32.u32 q0, q1, #5", q0, q1, i32, 7);
+    TESTINSN_un("vcvt.f32.u32 q10, q11, #9", q10, q11, i32, 1 << 31);
+    TESTINSN_un("vcvt.f32.u32 q0, q1, #4", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vcvt.f32.u32 q0, q1, #6", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vcvt.f32.u32 q0, q14, #5", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vcvt.f32.s32 q0, q1, #12", q0, q1, i32, 7);
+    TESTINSN_un("vcvt.f32.s32 q10, q11, #8", q10, q11, i32, 1 << 31);
+    TESTINSN_un("vcvt.f32.s32 q0, q1, #2", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vcvt.f32.s32 q0, q1, #1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vcvt.f32.s32 q0, q14, #6", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vcvt.u32.f32 q0, q1, #3", q0, q1, i32, f2u(-INFINITY));
+    TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vcvt.s32.f32 q0, q1, #3", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VMAX (fp) ----\n");
+    TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vmax.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vmax.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vmax.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vmax.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vmax.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vmax.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vmax.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vmax.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vmax.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vmax.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmax.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VMIN (fp) ----\n");
+    TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vmin.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vmin.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vmin.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vmin.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vmin.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vmin.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vmin.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vmin.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vmin.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vmin.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmin.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VRECPE ----\n");
+    TESTINSN_un("vrecpe.u32 q0, q1", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vrecpe.u32 q10, q11", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vrecpe.u32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vrecpe.u32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vrecpe.u32 q0, q1", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vrecpe.u32 q10, q11", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vrecpe.u32 q15, q4", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vrecpe.f32 q15, q4", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vrecpe.f32 q15, q4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vrecpe.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vrecpe.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, 7);
+    TESTINSN_un("vrecpe.f32 q10, q11", q10, q11, i32, 1 << 31);
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vrecpe.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, 7);
+    TESTINSN_un("vrecpe.f32 q10, q11", q10, q11, i32, 1 << 31);
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vrecpe.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vrecpe.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VRECPS ----\n");
+    TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vrecps.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vrecps.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vrecps.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vrecps.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vrecps.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vrecps.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vrecps.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vrecps.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vrecps.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vrecps.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrecps.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VABS (fp) ----\n");
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vabs.f32 q15, q4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vabs.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, 7);
+    TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, 1 << 31);
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vabs.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, 7);
+    TESTINSN_un("vabs.f32 q10, q11", q10, q11, i32, 1 << 31);
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vabs.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vabs.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VCGT (fp) ----\n");
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
+    TESTINSN_bin("vcgt.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
+    TESTINSN_bin("vcgt.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
+    TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vcgt.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vcgt.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vcgt.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vcgt.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vcgt.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vcgt.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vcgt.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vcgt.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vcgt.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vcgt.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VCGE (fp) ----\n");
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
+    TESTINSN_bin("vcge.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
+    TESTINSN_bin("vcge.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
+    TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vcge.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vcge.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vcge.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vcge.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vcge.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vcge.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vcge.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vcge.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vcge.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vcge.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VACGT (fp) ----\n");
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
+    TESTINSN_bin("vacgt.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
+    TESTINSN_bin("vacgt.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
+    TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vacgt.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vacgt.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vacgt.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vacgt.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vacgt.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vacgt.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vacgt.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vacgt.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vacgt.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vacgt.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacgt.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VACGE (fp) ----\n");
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
+    TESTINSN_bin("vacge.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
+    TESTINSN_bin("vacge.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
+    TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vacge.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vacge.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vacge.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vacge.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vacge.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vacge.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vacge.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vacge.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vacge.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vacge.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacge.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VCEQ (fp) ----\n");
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.5), q2, i32, f2u(-0.5));
+    TESTINSN_bin("vceq.f32 q2, q15, q12", q2, q15, i32, f2u(-0.53), q12, i32, f2u(0.52));
+    TESTINSN_bin("vceq.f32 q15, q7, q8", q15, q7, i32, f2u(231.45), q7, i32, f2u(231.45));
+    TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vceq.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vceq.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vceq.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vceq.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vceq.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vceq.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vceq.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vceq.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vceq.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vceq.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0), q2, i32, f2u(0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(1.0/1024.0), q2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-1.0/1024.0), q2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(2342+1.0/1024.0), q2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-2342+1.0/1024.0), q2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(89276+1.0/1024.0), q2, i32, f2u(89276+1.0/1024.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vceq.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VCEQ (fp) #0 ----\n");
+    TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
+    TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, 0x1);
+    TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
+    TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
+    TESTINSN_un("vceq.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
+    TESTINSN_un("vceq.f32 q10, q15, #0", q10, q15, i32, 0x0);
+    TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vceq.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VCGT (fp) #0 ----\n");
+    TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
+    TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, 0x1);
+    TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
+    TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
+    TESTINSN_un("vcgt.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
+    TESTINSN_un("vcgt.f32 q10, q15, #0", q10, q15, i32, 0x0);
+    TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vcgt.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VCLT (fp) #0 ----\n");
+    TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
+    TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, 0x1);
+    TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
+    TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
+    TESTINSN_un("vclt.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
+    TESTINSN_un("vclt.f32 q10, q15, #0", q10, q15, i32, 0x0);
+    TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vclt.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VCGE (fp) #0 ----\n");
+    TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
+    TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, 0x1);
+    TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
+    TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
+    TESTINSN_un("vcge.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
+    TESTINSN_un("vcge.f32 q10, q15, #0", q10, q15, i32, 0x0);
+    TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vcge.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VCLE (fp) #0 ----\n");
+    TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, 0x01000000);
+    TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, 0x1);
+    TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, 1 << 31);
+    TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, f2u(23.04));
+    TESTINSN_un("vcle.f32 q2, q1, #0", q2, q1, i32, f2u(-23.04));
+    TESTINSN_un("vcle.f32 q10, q15, #0", q10, q15, i32, 0x0);
+    TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vcle.f32 q0, q1, #0", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VNEG (fp) ----\n");
+    TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, 0x01000000);
+    TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, 0x1);
+    TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, 1 << 31);
+    TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, f2u(23.04));
+    TESTINSN_un("vneg.f32 q2, q1", q2, q1, i32, f2u(-23.04));
+    TESTINSN_un("vneg.f32 q10, q15", q10, q15, i32, 0x0);
+    TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vneg.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
+
+    printf("---- VRSQRTS ----\n");
+    TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(23.04), q2, i32, f2u(-45.5687));
+    TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(-347856.475), q5, i32, f2u(1346));
+    TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(-45786.476));
+    TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(95867.76), q7, i32, f2u(17065));
+    TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(-45667.24), q2, i32, f2u(-248562.76));
+    TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(24), q5, i32, f2u(1346));
+    TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(48755), q2, i32, f2u(1089));
+    TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(214), q7, i32, f2u(1752065));
+    TESTINSN_bin("vrsqrts.f32 q0, q11, q12", q0, q11, i32, f2u(356047.56), q12, i32, f2u(5867.009));
+    TESTINSN_bin("vrsqrts.f32 q7, q1, q6", q7, q1, i32, f2u(34.00046), q6, i32, f2u(0.0024575));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(2754), q2, i32, f2u(107));
+    TESTINSN_bin("vrsqrts.f32 q3, q4, q5", q3, q4, i32, f2u(874), q5, i32, f2u(1384.6));
+    TESTINSN_bin("vrsqrts.f32 q10, q11, q2", q10, q11, i32, f2u(487.587), q2, i32, f2u(109));
+    TESTINSN_bin("vrsqrts.f32 q9, q5, q7", q9, q5, i32, f2u(2146), q7, i32, f2u(1752));
+    TESTINSN_bin("vrsqrts.f32 q0, q11, q12", q0, q11, i32, f2u(-56.25), q12, i32, f2u(-5786.47));
+    TESTINSN_bin("vrsqrts.f32 q7, q1, q6", q7, q1, i32, f2u(456.2489562), q6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vrsqrts.f32 q0, q5, q2", q0, q5, i32, f2u(532.987), q2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vrsqrts.f32 q10, q13, q15", q10, q13, i32, f2u(-485.2457), q15, i32, f2u(-567.245));
+    TESTINSN_bin("vrsqrts.f32 q10, q13, q15", q10, q13, i32, f2u(278456.45), q15, i32, f2u(8756.0076));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(876988654), q2, i32, f2u(1224808797));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(NAN));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(1.0));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(0.0));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(NAN), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(NAN));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(1.0));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(0.0));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(0.0), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(INFINITY), q2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(NAN));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(1.0));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(0.0));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrsqrts.f32 q0, q1, q2", q0, q1, i32, f2u(-INFINITY), q2, i32, f2u(-INFINITY));
+
+    printf("---- VRSQRTE (fp) ----\n");
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(3.2));
+    TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, f2u(3e22));
+    TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(3e9));
+    TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-0.5));
+    TESTINSN_un("vrsqrte.f32 q15, q4", q15, q4, i32, f2u(-7.1));
+    TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vrsqrte.f32 q12, q8", q12, q8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, 7);
+    TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, 1 << 31); 
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vrsqrte.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, 7);
+    TESTINSN_un("vrsqrte.f32 q10, q11", q10, q11, i32, 1 << 31); 
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) + 1);
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, (1U << 31) - 1);
+    TESTINSN_un("vrsqrte.f32 q0, q14", q0, q14, i32, 0x30a0bcef);
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(NAN));
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(0.0));
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(INFINITY));
+    TESTINSN_un("vrsqrte.f32 q0, q1", q0, q1, i32, f2u(-INFINITY));
+
+    return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.stdout.exp
new file mode 100644 (file)
index 0000000..fe1ca66
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.stdout.exp
@@ -0,0 +1,2746 @@
+----- VMOV (immediate) -----
+vmov.i32 q0, #0x7 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007
+vmov.i16 q1, #0x7 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007
+vmov.i8 q2, #0x7 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707
+vmov.i32 q5, #0x700 :: Qd 0x00000700 0x00000700 0x00000700 0x00000700
+vmov.i16 q7, #0x700 :: Qd 0x07000700 0x07000700 0x07000700 0x07000700
+vmov.i32 q10, #0x70000 :: Qd 0x00070000 0x00070000 0x00070000 0x00070000
+vmov.i32 q12, #0x7000000 :: Qd 0x07000000 0x07000000 0x07000000 0x07000000
+vmov.i32 q13, #0x7FF :: Qd 0x000007ff 0x000007ff 0x000007ff 0x000007ff
+vmov.i32 q14, #0x7FFFF :: Qd 0x0007ffff 0x0007ffff 0x0007ffff 0x0007ffff
+vmov.i64 q15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00 0xff0000ff 0x00ffff00
+----- VMVN (immediate) -----
+vmvn.i32 q0, #0x7 :: Qd 0xfffffff8 0xfffffff8 0xfffffff8 0xfffffff8
+vmvn.i16 q1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8 0xfff8fff8 0xfff8fff8
+vmvn.i8 q2, #0x7 :: Qd 0xf8f8f8f8 0xf8f8f8f8 0xf8f8f8f8 0xf8f8f8f8
+vmvn.i32 q5, #0x700 :: Qd 0xfffff8ff 0xfffff8ff 0xfffff8ff 0xfffff8ff
+vmvn.i16 q7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff 0xf8fff8ff 0xf8fff8ff
+vmvn.i32 q10, #0x70000 :: Qd 0xfff8ffff 0xfff8ffff 0xfff8ffff 0xfff8ffff
+vmvn.i32 q13, #0x7000000 :: Qd 0xf8ffffff 0xf8ffffff 0xf8ffffff 0xf8ffffff
+vmvn.i32 q11, #0x7FF :: Qd 0xfffff800 0xfffff800 0xfffff800 0xfffff800
+vmvn.i32 q14, #0x7FFFF :: Qd 0xfff80000 0xfff80000 0xfff80000 0xfff80000
+vmvn.i64 q15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff 0x00ffff00 0xff0000ff
+----- VORR (immediate) -----
+vorr.i32 q0, #0x7 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557
+vorr.i16 q2, #0x7 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557
+vorr.i32 q8, #0x700 :: Qd 0x55555755 0x55555755 0x55555755 0x55555755
+vorr.i16 q6, #0x700 :: Qd 0x57555755 0x57555755 0x57555755 0x57555755
+vorr.i32 q14, #0x70000 :: Qd 0x55575555 0x55575555 0x55575555 0x55575555
+vorr.i32 q15, #0x7000000 :: Qd 0x57555555 0x57555555 0x57555555 0x57555555
+----- VBIC (immediate) -----
+vbic.i32 q0, #0x7 :: Qd 0x55555550 0x55555550 0x55555550 0x55555550
+vbic.i16 q3, #0x7 :: Qd 0x55505550 0x55505550 0x55505550 0x55505550
+vbic.i32 q5, #0x700 :: Qd 0x55555055 0x55555055 0x55555055 0x55555055
+vbic.i16 q8, #0x700 :: Qd 0x50555055 0x50555055 0x50555055 0x50555055
+vbic.i32 q10, #0x70000 :: Qd 0x55505555 0x55505555 0x55505555 0x55505555
+vbic.i32 q15, #0x7000000 :: Qd 0x50555555 0x50555555 0x50555555 0x50555555
+---- VMVN (register) ----
+vmvn q0, q1 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7  Qm (i32)0x00000018
+vmvn q10, q15 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7  Qm (i32)0x00000018
+vmvn q0, q14 :: Qd 0xffffffe7 0xffffffe7 0xffffffe7 0xffffffe7  Qm (i32)0x00000018
+---- VMOV (register) ----
+vmov q0, q1 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018  Qm (i32)0x00000018
+vmov q10, q15 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018  Qm (i32)0x00000018
+vmov q0, q14 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018  Qm (i32)0x00000018
+---- VDUP (ARM core register) (tested indirectly) ----
+vmov q0, q1 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707  Qm (i8)0x00000007
+vmov q10, q11 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007  Qm (i16)0x00000007
+vmov q0, q15 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007  Qm (i32)0x00000007
+---- VADD ----
+vadd.i32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078
+vadd.i64 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vadd.i32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vadd.i16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vadd.i8 q0, q1, q2 :: Qd 0x00000004 0x00000004 0x00000004 0x00000004  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vadd.i8 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vadd.i16 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vadd.i32 q0, q1, q2 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vadd.i64 q0, q1, q2 :: Qd 0x00000004 0x00000003 0x00000004 0x00000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vadd.i32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078
+vadd.i64 q13, q14, q15 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078
+---- VSUB ----
+vsub.i32 q0, q1, q2 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vsub.i64 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vsub.i32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vsub.i16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vsub.i8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vsub.i8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vsub.i16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vsub.i32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vsub.i64 q0, q1, q2 :: Qd 0xfffffffe 0xffffffff 0xfffffffe 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vsub.i32 q10, q11, q12 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vsub.i64 q13, q14, q15 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+---- VAND ----
+vand q0, q1, q2 :: Qd 0x00240024 0x00240024 0x00240024 0x00240024  Qm (i8)0x00000024  Qn (i16)0x00000077
+vand q4, q6, q5 :: Qd 0x00570057 0x00570057 0x00570057 0x00570057  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vand q10, q11, q12 :: Qd 0xecececec 0xecececec 0xecececec 0xecececec  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vand q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+---- VBIC ----
+vbic q0, q1, q2 :: Qd 0x24002400 0x24002400 0x24002400 0x24002400  Qm (i8)0x00000024  Qn (i16)0x00000077
+vbic q4, q6, q5 :: Qd 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vbic q10, q11, q12 :: Qd 0x12121212 0x12121212 0x12121212 0x12121212  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vbic q15, q15, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+---- VORR ----
+vorr q0, q1, q2 :: Qd 0x24772477 0x24772477 0x24772477 0x24772477  Qm (i8)0x00000024  Qn (i16)0x00000073
+vorr q7, q3, q0 :: Qd 0x24ff24ff 0x24ff24ff 0x24ff24ff 0x24ff24ff  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vorr q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vorr q2, q3, q15 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VORN ----
+vorn q0, q1, q2 :: Qd 0xffacffac 0xffacffac 0xffacffac 0xffacffac  Qm (i8)0x00000024  Qn (i16)0x00000073
+vorn q7, q3, q0 :: Qd 0xff24ff24 0xff24ff24 0xff24ff24 0xff24ff24  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vorn q4, q4, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vorn q2, q3, q15 :: Qd 0xffffffe4 0xffffffe4 0xffffffe4 0xffffffe4  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VEOR ----
+veor q0, q1, q2 :: Qd 0x24532453 0x24532453 0x24532453 0x24532453  Qm (i8)0x00000024  Qn (i16)0x00000077
+veor q4, q6, q5 :: Qd 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8 0xffa8ffa8  Qm (i8)0x000000ff  Qn (i16)0x00000057
+veor q10, q11, q12 :: Qd 0x13131313 0x13131313 0x13131313 0x13131313  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+veor q15, q15, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+veor q0, q1, q2 :: Qd 0x24572457 0x24572457 0x24572457 0x24572457  Qm (i8)0x00000024  Qn (i16)0x00000073
+veor q7, q3, q0 :: Qd 0x24db24db 0x24db24db 0x24db24db 0x24db24db  Qm (i8)0x00000024  Qn (i16)0x000000ff
+veor q4, q4, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+veor q2, q3, q15 :: Qd 0x0000003b 0x0000003b 0x0000003b 0x0000003b  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VBSL ----
+vbsl q0, q1, q2 :: Qd 0x04260426 0x04260426 0x04260426 0x04260426  Qm (i8)0x00000024  Qn (i16)0x00000077
+vbsl q4, q6, q5 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vbsl q10, q11, q12 :: Qd 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vbsl q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+vbsl q0, q1, q2 :: Qd 0x04260426 0x04260426 0x04260426 0x04260426  Qm (i8)0x00000024  Qn (i16)0x00000073
+vbsl q7, q3, q0 :: Qd 0x04ae04ae 0x04ae04ae 0x04ae04ae 0x04ae04ae  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vbsl q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vbsl q2, q3, q15 :: Qd 0x0000000e 0x0000000e 0x0000000e 0x0000000e  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VBIT ----
+vbit q0, q1, q2 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524  Qm (i8)0x00000024  Qn (i16)0x00000077
+vbit q4, q6, q5 :: Qd 0x55575557 0x55575557 0x55575557 0x55575557  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vbit q10, q11, q12 :: Qd 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc 0xfcfcfcfc  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vbit q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+vbit q0, q1, q2 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524  Qm (i8)0x00000024  Qn (i16)0x00000073
+vbit q7, q3, q0 :: Qd 0x55245524 0x55245524 0x55245524 0x55245524  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vbit q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vbit q2, q3, q15 :: Qd 0x55555544 0x55555544 0x55555544 0x55555544  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VBIF ----
+vbif q0, q1, q2 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455  Qm (i8)0x00000024  Qn (i16)0x00000077
+vbif q4, q6, q5 :: Qd 0xfffdfffd 0xfffdfffd 0xfffdfffd 0xfffdfffd  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vbif q10, q11, q12 :: Qd 0x57575757 0x57575757 0x57575757 0x57575757  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vbif q15, q15, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+vbif q0, q1, q2 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455  Qm (i8)0x00000024  Qn (i16)0x00000073
+vbif q7, q3, q0 :: Qd 0x24552455 0x24552455 0x24552455 0x24552455  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vbif q4, q4, q4 :: Qd 0x00ff00ff 0x00ff00ff 0x00ff00ff 0x00ff00ff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vbif q2, q3, q15 :: Qd 0x00000035 0x00000035 0x00000035 0x00000035  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VEXT ----
+vext.8 q0, q1, q2, #0 :: Qd 0x77777777 0x77777777 0x77777777 0x77777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 q0, q1, q2, #1 :: Qd 0xff777777 0x77777777 0x77777777 0x77777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 q0, q1, q2, #9 :: Qd 0xffffffff 0xffffffff 0xff777777 0x77777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 q0, q1, q2, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffff77  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 q10, q11, q12, #4 :: Qd 0xffffffff 0x77777777 0x77777777 0x77777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 q0, q5, q15, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0x77777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+---- VHADD ----
+vhadd.s32 q0, q1, q2 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhadd.s32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.s16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.s8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.s8 q0, q1, q2 :: Qd 0x03030303 0x03030303 0x03030303 0x03030303  Qm (i8)0x0000008d  Qn (i8)0x00000079
+vhadd.s8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.s32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhadd.u32 q0, q1, q2 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhadd.u32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.u16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.u8 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.u8 q0, q1, q2 :: Qd 0x83838383 0x83838383 0x83838383 0x83838383  Qm (i8)0x0000008d  Qn (i8)0x00000079
+vhadd.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.u32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VHSUB ----
+vhsub.s32 q0, q1, q2 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhsub.s32 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.s16 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.s8 q0, q1, q2 :: Qd 0x0000008a 0x0000008a 0x0000008a 0x0000008a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.s32 q10, q11, q12 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhsub.u32 q0, q1, q2 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhsub.u32 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.u16 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.u8 q0, q1, q2 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.u32 q10, q11, q12 :: Qd 0xffffffd0 0xffffffd0 0xffffffd0 0xffffffd0  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VQADD ----
+vqadd.s32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.s32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.s16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.s8 q0, q1, q2 :: Qd 0x00000004 0x00000004 0x00000004 0x00000004  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.s8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.s32 q0, q1, q2 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.s32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.u32 q0, q1, q2 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.u32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.u16 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 08000000
+vqadd.u8 q0, q1, q2 :: Qd 0xff000003 0xff000003 0xff000003 0xff000003  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.u16 q0, q1, q2 :: Qd 0xffff0003 0xffff0003 0xffff0003 0xffff0003  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.u32 q10, q11, q12 :: Qd 0x00000090 0x00000090 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+---- VQSUB ----
+vqsub.s32 q0, q1, q2 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.s32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.s16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.s8 q0, q1, q2 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 08000000
+vqsub.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqsub.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqsub.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqsub.s32 q10, q11, q12 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+vqsub.u32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.u16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.u8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqsub.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqsub.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqsub.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+---- VRHADD ----
+vrhadd.s32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049  Qm (i32)0x00000019  Qn (i32)0x00000078
+vrhadd.s32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049  Qm (i32)0x00000019  Qn (i32)0x00000079
+vrhadd.s32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.s16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.s8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.s32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.s32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+vrhadd.u32 q0, q1, q2 :: Qd 0x00000049 0x00000049 0x00000049 0x00000049  Qm (i32)0x00000019  Qn (i32)0x00000078
+vrhadd.u32 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.u16 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.u8 q0, q1, q2 :: Qd 0x00000082 0x00000082 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.u8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.u16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.u32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.u32 q10, q11, q12 :: Qd 0x00000048 0x00000048 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VCGT ----
+vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000078
+vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000079
+vcgt.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.s8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.s8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcgt.s8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcgt.s8 q5, q7, q5 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.s16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.s8 q5, q7, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.s8 q5, q7, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.s16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.s32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000078
+vcgt.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcgt.u8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.u16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.u8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.u16 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VCGE ----
+vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000078
+vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000079
+vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.s8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.s8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcge.s16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcge.s8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcge.s8 q5, q7, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.s8 q5, q7, q5 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.s16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.s8 q5, q7, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.s16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.s32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.s32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+vcge.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000078
+vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.u8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.u16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.u8 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.u16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.u32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.u32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VSHL (register) ----
+vshl.s8 q0, q1, q2 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030  Qm (i32)0x00000018  Qn (i32)0x00000001
+vshl.s8 q8, q1, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000008
+vshl.s8 q10, q11, q7 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080  Qm (i32)0x00000018  Qn (i32)0x00000004
+vshl.s16 q3, q8, q11 :: Qd 0x00000038 0x00000038 0x00000038 0x00000038  Qm (i32)0x0000000e  Qn (i32)0x00000002
+vshl.s16 q5, q12, q14 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000001
+vshl.s16 q15, q2, q1 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x0000000b
+vshl.s32 q9, q12, q15 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x80000002  Qn (i32)0x00000002
+vshl.s32 q11, q2, q0 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000  Qm (i32)0xffffffff  Qn (i32)0x0000000c
+vshl.s32 q5, q2, q3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x40000000  Qn (i32)0x00000015
+vshl.s64 q15, q12, q4 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000  Qm (i32)0x00000005  Qn (i32)0x00000014
+vshl.s64 q8, q2, q4 :: Qd 0x000000f0 0x000000f0 0x000000f0 0x000000f0  Qm (i32)0x0000000f  Qn (i32)0x00000004
+vshl.s64 q5, q12, q4 :: Qd 0x60000000 0x40000000 0x60000000 0x40000000  Qm (i32)0x80000001  Qn (i32)0x0000001e
+vshl.u8 q0, q1, q2 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030  Qm (i32)0x00000018  Qn (i32)0x00000001
+vshl.u8 q8, q1, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000008
+vshl.u8 q10, q11, q7 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080  Qm (i32)0x00000018  Qn (i32)0x00000004
+vshl.u16 q3, q8, q11 :: Qd 0x00000038 0x00000038 0x00000038 0x00000038  Qm (i32)0x0000000e  Qn (i32)0x00000002
+vshl.u16 q5, q12, q14 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000001
+vshl.u16 q15, q2, q1 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x0000000b
+vshl.u32 q9, q12, q15 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x80000002  Qn (i32)0x00000002
+vshl.u32 q11, q2, q0 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000  Qm (i32)0xffffffff  Qn (i32)0x0000000c
+vshl.u32 q5, q2, q3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x40000000  Qn (i32)0x00000015
+vshl.u64 q15, q12, q4 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000  Qm (i32)0x00000005  Qn (i32)0x00000014
+vshl.u64 q8, q2, q4 :: Qd 0x000000f0 0x000000f0 0x000000f0 0x000000f0  Qm (i32)0x0000000f  Qn (i32)0x00000004
+vshl.u64 q5, q12, q4 :: Qd 0x60000000 0x40000000 0x60000000 0x40000000  Qm (i32)0x80000001  Qn (i32)0x0000001e
+---- VQSHL (register) ----
+vqshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001  fpscr: 00000000
+vqshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02  Qm (i32)0xffffff81  Qn (i32)0x00000001  fpscr: 00000000
+vqshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd  fpscr: 00000000
+vqshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e  fpscr: 00000000
+vqshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffbff 0xffffffff 0xfffffbff  Qm (i32)0xffffffef  Qn (i32)0xffffffe6  fpscr: 00000000
+vqshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4  fpscr: 00000000
+vqshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2  fpscr: 00000000
+vqshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc  fpscr: 00000000
+vqshl.s32 q12, q11, q13 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffff88  Qn (i32)0xfffffff7  fpscr: 00000000
+vqshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9  fpscr: 00000000
+vqshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004  Qm (i32)0x80000008  Qn (i32)0xffffffff  fpscr: 00000000
+vqshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003  fpscr: 00000000
+vqshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1  fpscr: 00000000
+vqshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd  fpscr: 00000000
+vqshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080  Qm (i32)0x80000100  Qn (i32)0xffffffff  fpscr: 00000000
+vqshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1  fpscr: 00000000
+vqshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3  fpscr: 00000000
+vqshl.s16 q0, q15, q2 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff  Qm (i32)0x00000001  Qn (i32)0x0000001e  fpscr: 08000000
+vqshl.s8 q2, q7, q11 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80  Qm (i32)0xffffffff  Qn (i32)0x00000028  fpscr: 08000000
+vqshl.s8 q13, q1, q2 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80  Qm (i32)0xfffffffc  Qn (i32)0x0000001e  fpscr: 08000000
+vqshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003  fpscr: 00000000
+vqshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010  fpscr: 00000000
+vqshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002  fpscr: 00000000
+vqshl.s8 q10, q11, q12 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+vqshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001  fpscr: 00000000
+vqshl.u64 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffff81  Qn (i32)0x00000001  fpscr: 08000000
+vqshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd  fpscr: 00000000
+vqshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e  fpscr: 00000000
+vqshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffbff 0x0000003f 0xfffffbff  Qm (i32)0xffffffef  Qn (i32)0xffffffe6  fpscr: 00000000
+vqshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4  fpscr: 00000000
+vqshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2  fpscr: 00000000
+vqshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc  fpscr: 00000000
+vqshl.u32 q12, q11, q13 :: Qd 0x007fffff 0x007fffff 0x007fffff 0x007fffff  Qm (i32)0xffffff88  Qn (i32)0xfffffff7  fpscr: 00000000
+vqshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9  fpscr: 00000000
+vqshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004  Qm (i32)0x80000008  Qn (i32)0xffffffff  fpscr: 00000000
+vqshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003  fpscr: 00000000
+vqshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1  fpscr: 00000000
+vqshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd  fpscr: 00000000
+vqshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080  Qm (i32)0x80000100  Qn (i32)0xffffffff  fpscr: 00000000
+vqshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1  fpscr: 00000000
+vqshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3  fpscr: 00000000
+vqshl.u16 q0, q15, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00000001  Qn (i32)0x0000001e  fpscr: 08000000
+vqshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000028  fpscr: 08000000
+vqshl.u8 q13, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xfffffffc  Qn (i32)0x0000001e  fpscr: 08000000
+vqshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003  fpscr: 00000000
+vqshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010  fpscr: 00000000
+vqshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002  fpscr: 00000000
+vqshl.u8 q10, q11, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+---- VQSHL / VQSHLU (immediate) ----
+vqshl.s64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshl.s64 q15, q14, #1 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.s64 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.s64 q5, q4, #63 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s64 q5, q4, #60 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s64 q5, q4, #59 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s64 q5, q4, #58 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.s64 q5, q4, #63 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000  Qm (i32)0xffffffff  fpscr: 00000000
+vqshl.s64 q5, q4, #60 :: Qd 0xf0000000 0x00000000 0xf0000000 0x00000000  Qm (i32)0xffffffff  fpscr: 00000000
+vqshl.s64 q5, q4, #7 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000  Qm (i32)0x80000002  fpscr: 08000000
+vqshl.s32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshl.s32 q15, q14, #1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.s32 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.s32 q5, q4, #31 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s32 q5, q4, #28 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s32 q5, q4, #27 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.s32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.s32 q5, q4, #31 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0xffffffff  fpscr: 00000000
+vqshl.s32 q5, q4, #29 :: Qd 0xe0000000 0xe0000000 0xe0000000 0xe0000000  Qm (i32)0xffffffff  fpscr: 00000000
+vqshl.s32 q5, q4, #7 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x80000002  fpscr: 08000000
+vqshl.s16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshl.s16 q15, q14, #1 :: Qd 0xfffeff02 0xfffeff02 0xfffeff02 0xfffeff02  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.s16 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.s16 q9, q8, #15 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s16 q5, q4, #12 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s16 q5, q4, #11 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.s16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.s16 q5, q4, #15 :: Qd 0x80008000 0x80008000 0x80008000 0x80008000  Qm (i32)0xffffffff  fpscr: 00000000
+vqshl.s16 q5, q4, #12 :: Qd 0xf000f000 0xf000f000 0xf000f000 0xf000f000  Qm (i32)0xffffffff  fpscr: 00000000
+vqshl.s16 q5, q4, #7 :: Qd 0x80000100 0x80000100 0x80000100 0x80000100  Qm (i32)0x80000002  fpscr: 08000000
+vqshl.s8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshl.s8 q15, q14, #1 :: Qd 0xfefefe80 0xfefefe80 0xfefefe80 0xfefefe80  Qm (i32)0xffffff81  fpscr: 08000000
+vqshl.s8 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.s8 q5, q4, #7 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s8 q5, q4, #4 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s8 q5, q4, #3 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.s8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.s8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.s8 q5, q4, #7 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080  Qm (i32)0xffffffff  fpscr: 00000000
+vqshl.s8 q5, q4, #5 :: Qd 0xe0e0e0e0 0xe0e0e0e0 0xe0e0e0e0 0xe0e0e0e0  Qm (i32)0xffffffff  fpscr: 00000000
+vqshl.s8 q5, q4, #2 :: Qd 0x80000008 0x80000008 0x80000008 0x80000008  Qm (i32)0x80000002  fpscr: 08000000
+vqshl.u64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshl.u64 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffff81  fpscr: 08000000
+vqshl.u64 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.u64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u64 q5, q4, #59 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u64 q5, q4, #58 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr: 08000000
+vqshl.u64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr: 08000000
+vqshl.u64 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000002  fpscr: 08000000
+vqshl.u32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshl.u32 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffff81  fpscr: 08000000
+vqshl.u32 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.u32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u32 q5, q4, #28 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u32 q5, q4, #27 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr: 08000000
+vqshl.u32 q5, q4, #29 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr: 08000000
+vqshl.u32 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000002  fpscr: 08000000
+vqshl.u16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshl.u16 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffff81  fpscr: 08000000
+vqshl.u16 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.u16 q9, q8, #15 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u16 q5, q4, #12 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u16 q5, q4, #11 :: Qd 0x00008000 0x00008000 0x00008000 0x00008000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u16 q5, q4, #15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr: 08000000
+vqshl.u16 q5, q4, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr: 08000000
+vqshl.u16 q5, q4, #7 :: Qd 0xffff0100 0xffff0100 0xffff0100 0xffff0100  Qm (i32)0x80000002  fpscr: 08000000
+vqshl.u8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshl.u8 q15, q14, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffff81  fpscr: 08000000
+vqshl.u8 q5, q4, #0 :: Qd 0xffffff81 0xffffff81 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr: 00000000
+vqshl.u8 q5, q4, #7 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u8 q5, q4, #4 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x00000010  fpscr: 08000000
+vqshl.u8 q5, q4, #3 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020  Qm (i32)0x00000010  fpscr: 00000000
+vqshl.u8 q5, q4, #7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr: 08000000
+vqshl.u8 q5, q4, #5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr: 08000000
+vqshl.u8 q5, q4, #2 :: Qd 0xff000008 0xff000008 0xff000008 0xff000008  Qm (i32)0x80000002  fpscr: 08000000
+vqshlu.s64 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshlu.s64 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr: 08000000
+vqshlu.s64 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr: 08000000
+vqshlu.s64 q5, q4, #63 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s64 q5, q4, #60 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s64 q5, q4, #59 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s64 q5, q4, #58 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s64 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s64 q5, q4, #63 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr: 08000000
+vqshlu.s64 q5, q4, #60 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr: 08000000
+vqshlu.s64 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000002  fpscr: 08000000
+vqshlu.s32 q10, q11, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshlu.s32 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr: 08000000
+vqshlu.s32 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr: 08000000
+vqshlu.s32 q5, q4, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s32 q5, q4, #28 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s32 q5, q4, #27 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s32 q5, q4, #26 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s32 q5, q4, #17 :: Qd 0x00200000 0x00200000 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s32 q5, q4, #31 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr: 08000000
+vqshlu.s32 q5, q4, #29 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr: 08000000
+vqshlu.s32 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000002  fpscr: 08000000
+vqshlu.s16 q9, q8, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshlu.s16 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr: 08000000
+vqshlu.s16 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr: 08000000
+vqshlu.s16 q9, q8, #15 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s16 q5, q4, #12 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s16 q5, q4, #11 :: Qd 0x00008000 0x00008000 0x00008000 0x00008000  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s16 q5, q4, #10 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s16 q5, q4, #4 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s16 q5, q4, #15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr: 08000000
+vqshlu.s16 q5, q4, #12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr: 08000000
+vqshlu.s16 q5, q4, #7 :: Qd 0x00000100 0x00000100 0x00000100 0x00000100  Qm (i32)0x80000002  fpscr: 08000000
+vqshlu.s8 q0, q1, #1 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr: 00000000
+vqshlu.s8 q15, q14, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr: 08000000
+vqshlu.s8 q5, q4, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr: 08000000
+vqshlu.s8 q5, q4, #7 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s8 q5, q4, #4 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x00000010  fpscr: 08000000
+vqshlu.s8 q5, q4, #3 :: Qd 0x00000080 0x00000080 0x00000080 0x00000080  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s8 q5, q4, #2 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s8 q5, q4, #1 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020  Qm (i32)0x00000010  fpscr: 00000000
+vqshlu.s8 q5, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr: 08000000
+vqshlu.s8 q5, q4, #5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr: 08000000
+vqshlu.s8 q5, q4, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x80000002  fpscr: 08000000
+---- VQRSHL (register) ----
+vqrshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001  fpscr: 00000000
+vqrshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02  Qm (i32)0xffffff81  Qn (i32)0x00000001  fpscr: 00000000
+vqrshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd  fpscr: 00000000
+vqrshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e  fpscr: 00000000
+vqrshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffc00 0xffffffff 0xfffffc00  Qm (i32)0xffffffef  Qn (i32)0xffffffe6  fpscr: 00000000
+vqrshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4  fpscr: 00000000
+vqrshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2  fpscr: 00000000
+vqrshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc  fpscr: 00000000
+vqrshl.s32 q12, q11, q13 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff88  Qn (i32)0xfffffff7  fpscr: 00000000
+vqrshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9  fpscr: 00000000
+vqrshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004  Qm (i32)0x80000008  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003  fpscr: 00000000
+vqrshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1  fpscr: 00000000
+vqrshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd  fpscr: 00000000
+vqrshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080  Qm (i32)0x80000100  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1  fpscr: 00000000
+vqrshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3  fpscr: 00000000
+vqrshl.s16 q0, q15, q2 :: Qd 0x00007fff 0x00007fff 0x00007fff 0x00007fff  Qm (i32)0x00000001  Qn (i32)0x0000001e  fpscr: 08000000
+vqrshl.s8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s8 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s16 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s32 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s8 q2, q7, q11 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s16 q2, q7, q11 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.s16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.s8 q2, q7, q11 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80  Qm (i32)0xffffffff  Qn (i32)0x00000028  fpscr: 08000000
+vqrshl.s8 q13, q1, q2 :: Qd 0xffffff80 0xffffff80 0xffffff80 0xffffff80  Qm (i32)0xfffffffc  Qn (i32)0x0000001e  fpscr: 08000000
+vqrshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003  fpscr: 00000000
+vqrshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010  fpscr: 00000000
+vqrshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002  fpscr: 00000000
+vqrshl.s8 q10, q11, q12 :: Qd 0x0000007f 0x0000007f 0x0000007f 0x0000007f  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+vqrshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001  fpscr: 00000000
+vqrshl.u64 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffff81  Qn (i32)0x00000001  fpscr: 08000000
+vqrshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd  fpscr: 00000000
+vqrshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e  fpscr: 00000000
+vqrshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffc00 0x0000003f 0xfffffc00  Qm (i32)0xffffffef  Qn (i32)0xffffffe6  fpscr: 00000000
+vqrshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4  fpscr: 00000000
+vqrshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2  fpscr: 00000000
+vqrshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc  fpscr: 00000000
+vqrshl.u32 q12, q11, q13 :: Qd 0x00800000 0x00800000 0x00800000 0x00800000  Qm (i32)0xffffff88  Qn (i32)0xfffffff7  fpscr: 00000000
+vqrshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9  fpscr: 00000000
+vqrshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004  Qm (i32)0x80000008  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003  fpscr: 00000000
+vqrshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1  fpscr: 00000000
+vqrshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd  fpscr: 00000000
+vqrshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080  Qm (i32)0x80000100  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1  fpscr: 00000000
+vqrshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3  fpscr: 00000000
+vqrshl.u16 q0, q15, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00000001  Qn (i32)0x0000001e  fpscr: 08000000
+vqrshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000028  fpscr: 08000000
+vqrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080  Qm (i32)0xffffffff  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u8 q2, q7, q11 :: Qd 0x8080807f 0x8080807f 0x8080807f 0x8080807f  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u16 q2, q7, q11 :: Qd 0x80007fff 0x80007fff 0x80007fff 0x80007fff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u32 q2, q7, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.u16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.u32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.u8 q13, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xfffffffc  Qn (i32)0x0000001e  fpscr: 08000000
+vqrshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003  fpscr: 00000000
+vqrshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010  fpscr: 00000000
+vqrshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002  fpscr: 00000000
+vqrshl.u8 q10, q11, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+---- VRSHL (register) ----
+vrshl.s64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001
+vrshl.s64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02  Qm (i32)0xffffff81  Qn (i32)0x00000001
+vrshl.s64 q3, q4, q5 :: Qd 0xfffffff0 0x3ffffff0 0xfffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd
+vrshl.s64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e
+vrshl.s64 q13, q14, q15 :: Qd 0xffffffff 0xfffffc00 0xffffffff 0xfffffc00  Qm (i32)0xffffffef  Qn (i32)0xffffffe6
+vrshl.s64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4
+vrshl.s32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2
+vrshl.s32 q2, q8, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc
+vrshl.s32 q12, q11, q13 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffff88  Qn (i32)0xfffffff7
+vrshl.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9
+vrshl.s32 q9, q10, q11 :: Qd 0xc0000004 0xc0000004 0xc0000004 0xc0000004  Qm (i32)0x80000008  Qn (i32)0xffffffff
+vrshl.s32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003
+vrshl.s16 q11, q10, q2 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1
+vrshl.s16 q3, q14, q7 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd
+vrshl.s16 q0, q11, q2 :: Qd 0xc0000080 0xc0000080 0xc0000080 0xc0000080  Qm (i32)0x80000100  Qn (i32)0xffffffff
+vrshl.s16 q1, q2, q3 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1
+vrshl.s16 q3, q4, q5 :: Qd 0xd0000000 0xd0000000 0xd0000000 0xd0000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3
+vrshl.s16 q0, q15, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000001  Qn (i32)0x0000001e
+vrshl.s8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.s16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.s32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.s8 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.s16 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.s32 q2, q7, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.s8 q2, q7, q11 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.s16 q2, q7, q11 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.s8 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000
+vrshl.s16 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000
+vrshl.s32 q2, q7, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000
+vrshl.s8 q2, q7, q11 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0xffffffff  Qn (i32)0x00000028
+vrshl.s8 q13, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0xfffffffc  Qn (i32)0x0000001e
+vrshl.s8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003
+vrshl.s8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010
+vrshl.s8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002
+vrshl.s8 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+vrshl.u64 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001
+vrshl.u64 q3, q4, q5 :: Qd 0xffffff03 0xffffff02 0xffffff03 0xffffff02  Qm (i32)0xffffff81  Qn (i32)0x00000001
+vrshl.u64 q3, q4, q5 :: Qd 0x1ffffff0 0x3ffffff0 0x1ffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd
+vrshl.u64 q0, q1, q2 :: Qd 0x00040000 0x00040000 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e
+vrshl.u64 q13, q14, q15 :: Qd 0x0000003f 0xfffffc00 0x0000003f 0xfffffc00  Qm (i32)0xffffffef  Qn (i32)0xffffffe6
+vrshl.u64 q7, q8, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4
+vrshl.u32 q3, q4, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2
+vrshl.u32 q2, q8, q4 :: Qd 0x0fffffff 0x0fffffff 0x0fffffff 0x0fffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc
+vrshl.u32 q12, q11, q13 :: Qd 0x00800000 0x00800000 0x00800000 0x00800000  Qm (i32)0xffffff88  Qn (i32)0xfffffff7
+vrshl.u32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9
+vrshl.u32 q9, q10, q11 :: Qd 0x40000004 0x40000004 0x40000004 0x40000004  Qm (i32)0x80000008  Qn (i32)0xffffffff
+vrshl.u32 q13, q3, q5 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003
+vrshl.u16 q11, q10, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1
+vrshl.u16 q3, q14, q7 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd
+vrshl.u16 q0, q11, q2 :: Qd 0x40000080 0x40000080 0x40000080 0x40000080  Qm (i32)0x80000100  Qn (i32)0xffffffff
+vrshl.u16 q1, q2, q3 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1
+vrshl.u16 q3, q4, q5 :: Qd 0x50000000 0x50000000 0x50000000 0x50000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3
+vrshl.u16 q0, q15, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000001  Qn (i32)0x0000001e
+vrshl.u8 q2, q7, q11 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0xffffffff  Qn (i32)0x00000028
+vrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.u8 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.u16 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.u32 q2, q7, q11 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.u8 q2, q7, q11 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.u16 q2, q7, q11 :: Qd 0x80008000 0x80008000 0x80008000 0x80008000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.u32 q2, q7, q11 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.u8 q2, q7, q11 :: Qd 0x8080807f 0x8080807f 0x8080807f 0x8080807f  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.u16 q2, q7, q11 :: Qd 0x80007fff 0x80007fff 0x80007fff 0x80007fff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.u32 q2, q7, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.u8 q13, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0xfffffffc  Qn (i32)0x0000001e
+vrshl.u8 q3, q7, q5 :: Qd 0x80000058 0x80000058 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003
+vrshl.u8 q10, q11, q12 :: Qd 0x00010000 0x00010000 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010
+vrshl.u8 q6, q7, q8 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002
+vrshl.u8 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VMAX (integer) ----
+vmax.s32 q0, q1, q2 :: Qd 0x00000079 0x00000079 0x00000079 0x00000079  Qm (i32)0x00000019  Qn (i32)0x00000079
+vmax.s32 q0, q1, q2 :: Qd 0x000000fa 0x000000fa 0x000000fa 0x000000fa  Qm (i32)0x000000fa  Qn (i32)0x00000079
+vmax.s32 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vmax.s16 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmax.s8 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vmax.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.s16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.s32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.s8 q5, q7, q5 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.s16 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.s32 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.s32 q10, q11, q12 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmax.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x00000019  Qn (i32)0x00000078
+vmax.u32 q0, q1, q2 :: Qd 0x000000fa 0x000000fa 0x000000fa 0x000000fa  Qm (i32)0x000000fa  Qn (i32)0x00000078
+vmax.u32 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vmax.u16 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmax.u8 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vmax.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.u8 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.u16 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.u32 q0, q1, q2 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.u8 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.u16 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.u32 q0, q1, q2 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.u32 q10, q11, q12 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VMIN (integer) ----
+vmin.s32 q0, q1, q2 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019  Qm (i32)0x00000019  Qn (i32)0x00000079
+vmin.s32 q0, q1, q2 :: Qd 0x00000079 0x00000079 0x00000079 0x00000079  Qm (i32)0x000000fa  Qn (i32)0x00000079
+vmin.s32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmin.s16 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vmin.s8 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vmin.s8 q5, q7, q5 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.s8 q5, q7, q5 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.s16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.s32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.s8 q5, q7, q5 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.s16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.s32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.s32 q10, q11, q12 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmin.u32 q0, q1, q2 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019  Qm (i32)0x00000019  Qn (i32)0x00000078
+vmin.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x000000fa  Qn (i32)0x00000078
+vmin.u32 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmin.u16 q0, q1, q2 :: Qd 0x00000078 0x00000078 0x00000078 0x00000078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vmin.u8 q0, q1, q2 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vmin.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.u8 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.u16 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.u32 q0, q1, q2 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.u8 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.u16 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.u32 q0, q1, q2 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.u32 q10, q11, q12 :: Qd 0x00000018 0x00000018 0x00000018 0x00000018  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VABD ----
+vabd.s32 q0, q1, q2 :: Qd 0x0000005f 0x0000005f 0x0000005f 0x0000005f  Qm (i32)0x00000019  Qn (i32)0x00000078
+vabd.s32 q0, q1, q2 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060  Qm (i32)0x00000019  Qn (i32)0x00000079
+vabd.s32 q0, q1, q2 :: Qd 0x00000104 0x00000104 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vabd.s16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabd.s8 q0, q1, q2 :: Qd 0x000000ec 0x000000ec 0x000000ec 0x000000ec  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabd.s8 q5, q7, q5 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.s8 q5, q7, q5 :: Qd 0x7f010101 0x7f010101 0x7f010101 0x7f010101  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vabd.s8 q5, q7, q5 :: Qd 0x7f010137 0x7f010137 0x7f010137 0x7f010137  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vabd.s16 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.s32 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.s8 q5, q7, q5 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.s16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.s32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.s8 q5, q7, q5 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.s16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.s32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.s32 q10, q11, q12 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060  Qm (i32)0x00000018  Qn (i32)0x00000078
+vabd.u32 q0, q1, q2 :: Qd 0x0000005f 0x0000005f 0x0000005f 0x0000005f  Qm (i32)0x00000019  Qn (i32)0x00000078
+vabd.u32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabd.u16 q0, q1, q2 :: Qd 0xfffffefc 0xfffffefc 0xfffffefc 0xfffffefc  Qm (i32)0xffffff74  Qn (i32)0x00000078
+vabd.u8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabd.u8 q5, q7, q5 :: Qd 0x7fffff01 0x7fffff01 0x7fffff01 0x7fffff01  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vabd.u8 q5, q7, q5 :: Qd 0x7fffff37 0x7fffff37 0x7fffff37 0x7fffff37  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vabd.u8 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.u16 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.u32 q0, q1, q2 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.u8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.u16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.u32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.u8 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.u16 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.u32 q0, q1, q2 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.u32 q10, q11, q12 :: Qd 0x00000060 0x00000060 0x00000060 0x00000060  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VABA ----
+vaba.s32 q0, q1, q2 :: Qd 0x555555b4 0x555555b4 0x555555b4 0x555555b4  Qm (i32)0x00000019  Qn (i32)0x00000078
+vaba.s32 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5  Qm (i32)0x00000019  Qn (i32)0x00000079
+vaba.s32 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.s16 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.s8 q0, q1, q2 :: Qd 0x55555541 0x55555541 0x55555541 0x55555541  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.s8 q5, q7, q5 :: Qd 0x80000003 0x80000003 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.s8 q5, q7, q5 :: Qd 0xff010103 0xff010103 0xff010103 0xff010103  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vaba.s8 q5, q7, q5 :: Qd 0x7e00006f 0x7e00006f 0x7e00006f 0x7e00006f  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vaba.s16 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.s32 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.s8 q5, q7, q5 :: Qd 0x80000005 0x80000005 0x80000005 0x80000005  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.s16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.s32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.s8 q5, q7, q5 :: Qd 0x80000004 0x80000004 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.s16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.s32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.s32 q10, q11, q12 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5  Qm (i32)0x00000018  Qn (i32)0x00000078
+vaba.u32 q0, q1, q2 :: Qd 0x555555b4 0x555555b4 0x555555b4 0x555555b4  Qm (i32)0x00000019  Qn (i32)0x00000078
+vaba.u32 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.u16 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.u8 q0, q1, q2 :: Qd 0x55555569 0x55555569 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.u8 q5, q7, q5 :: Qd 0xffffff03 0xffffff03 0xffffff03 0xffffff03  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vaba.u8 q5, q7, q5 :: Qd 0x7efefe6f 0x7efefe6f 0x7efefe6f 0x7efefe6f  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vaba.u8 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.u16 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.u32 q0, q1, q2 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.u8 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.u16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.u32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.u8 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.u16 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.u32 q0, q1, q2 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.u32 q10, q11, q12 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VABAL ----
+vabal.s32 q0, d1, d2 :: Qd 0x00000019 0x00000078 0x55555555 0x555555b4  Qm (i32)0x00000019  Qn (i32)0x00000078
+vabal.s32 q0, d1, d2 :: Qd 0x00000019 0x00000079 0x55555555 0x555555b5  Qm (i32)0x00000019  Qn (i32)0x00000079
+vabal.s32 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabal.s16 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabal.s8 q0, d1, d2 :: Qd 0x0000008c 0x00000178 0x55555555 0x55555641  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555556 0x55555555 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabal.s8 q5, d7, d5 :: Qd 0x55d45556 0x55565556 0x55d45556 0x55565556  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vabal.s8 q5, d7, d5 :: Qd 0x55d45556 0x5556558c 0x55d45556 0x5556558c  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vabal.s16 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabal.s32 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555557 0x55555555 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabal.s16 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabal.s32 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabal.s8 q5, d7, d5 :: Qd 0x55555555 0x55555557 0x55555555 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabal.s16 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabal.s32 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabal.s32 q10, d31, d12 :: Qd 0x55555555 0x555555b5 0x55555555 0x555555b5  Qm (i32)0x00000018  Qn (i32)0x00000078
+vabal.u32 q0, d1, d2 :: Qd 0x00000019 0x00000078 0x55555555 0x555555b4  Qm (i32)0x00000019  Qn (i32)0x00000078
+vabal.u32 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabal.u16 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabal.u8 q0, d1, d2 :: Qd 0x0000008c 0x000000a0 0x55555555 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabal.u8 q5, d7, d5 :: Qd 0x55d45654 0x56545556 0x55d45654 0x56545556  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vabal.u8 q5, d7, d5 :: Qd 0x55d45654 0x5654558c 0x55d45654 0x5654558c  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vabal.u8 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabal.u16 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabal.u32 q0, d1, d2 :: Qd 0x80000001 0x80000002 0x55555555 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabal.u8 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabal.u16 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabal.u32 q0, d1, d2 :: Qd 0x80000001 0x80000003 0x55555555 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabal.u8 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabal.u16 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabal.u32 q0, d1, d2 :: Qd 0x80000004 0x80000006 0x55555555 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabal.u32 q10, d11, d12 :: Qd 0x55555555 0x555555b5 0x55555555 0x555555b5  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VABDL ----
+vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x0000005f 0x00000000 0x0000005f  Qm (i32)0x00000019  Qn (i32)0x00000078
+vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060  Qm (i32)0x00000019  Qn (i32)0x00000079
+vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabdl.s8 q0, d1, d2 :: Qd 0x00000000 0x000000ec 0x00000000 0x000000ec  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabdl.s8 q5, d7, d5 :: Qd 0x007f0001 0x00010001 0x007f0001 0x00010001  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vabdl.s8 q5, d7, d5 :: Qd 0x007f0001 0x00010037 0x007f0001 0x00010037  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabdl.s8 q5, d7, d5 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabdl.s16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabdl.s32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabdl.s32 q10, d31, d12 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060  Qm (i32)0x00000018  Qn (i32)0x00000078
+vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x0000005f 0x00000000 0x0000005f  Qm (i32)0x00000019  Qn (i32)0x00000078
+vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000014 0x00000000 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabdl.u8 q5, d7, d5 :: Qd 0x007f00ff 0x00ff0001 0x007f00ff 0x00ff0001  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vabdl.u8 q5, d7, d5 :: Qd 0x007f00ff 0x00ff0037 0x007f00ff 0x00ff0037  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000001 0x00000000 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabdl.u8 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabdl.u16 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabdl.u32 q0, d1, d2 :: Qd 0x00000000 0x00000002 0x00000000 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabdl.u32 q10, d11, d12 :: Qd 0x00000000 0x00000060 0x00000000 0x00000060  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VTST ----
+vtst.32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000018  Qn (i32)0x00000078
+vtst.32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vtst.16 q6, q7, q8 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vtst.8 q9, q10, q12 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vtst.8 q0, q1, q2 :: Qd 0xff000000 0xff000000 0xff000000 0xff000000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vtst.16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00004001  Qn (i32)0x00004001
+vtst.32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vtst.8 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x00000002
+vtst.16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00004001  Qn (i32)0x00004001
+vtst.32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000001  Qn (i32)0x80000002
+vtst.32 q10, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VCEQ ----
+vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+vceq.i32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vceq.i16 q6, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vceq.i8 q9, q10, q12 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vceq.i8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0x80000001  Qn (i32)0x80000002
+vceq.i16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00004001  Qn (i32)0x00004001
+vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vceq.i8 q0, q1, q2 :: Qd 0x00ffff00 0x00ffff00 0x00ffff00 0x00ffff00  Qm (i32)0x80000001  Qn (i32)0x00000002
+vceq.i16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000  Qm (i32)0x00000001  Qn (i32)0x00004001
+vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000001  Qn (i32)0x80000002
+vceq.i32 q10, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VMLA ----
+vmla.i32 q0, q1, q2 :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15  Qm (i32)0xffffffe8  Qn (i32)0x00000078
+vmla.i32 q6, q7, q8 :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmla.i16 q9, q11, q12 :: Qd 0x5555bd55 0x5555bd55 0x5555bd55 0x5555bd55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmla.i16 q7, q1, q2 :: Qd 0x5555bd55 0x5555bd55 0x5555bd55 0x5555bd55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmla.i8 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmla.i8 q10, q11, q12 :: Qd 0x5555559f 0x5555559f 0x5555559f 0x5555559f  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmla.i16 q4, q5, q6 :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmla.i16 q14, q5, q9 :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmla.i32 q7, q8, q9 :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.i8 q10, q13, q12 :: Qd 0x5555559f 0x5555559f 0x5555559f 0x5555559f  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmla.i16 q4, q5, q6 :: Qd 0x55551751 0x55551751 0x55551751 0x55551751  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmla.i32 q7, q8, q9 :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.i32 q10, q11, q15 :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15  Qm (i32)0x00000018  Qn (i32)0xffffff88
+---- VMLS ----
+vmls.i32 q0, q1, q2 :: Qd 0x55556095 0x55556095 0x55556095 0x55556095  Qm (i32)0xffffffe8  Qn (i32)0x00000078
+vmls.i32 q6, q7, q8 :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmls.i16 q9, q11, q12 :: Qd 0x5555ed55 0x5555ed55 0x5555ed55 0x5555ed55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmls.i8 q0, q1, q2 :: Qd 0x555555b5 0x555555b5 0x555555b5 0x555555b5  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmls.i8 q10, q11, q12 :: Qd 0x5555550b 0x5555550b 0x5555550b 0x5555550b  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmls.i16 q4, q5, q6 :: Qd 0x5555b553 0x5555b553 0x5555b553 0x5555b553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmls.i32 q7, q8, q9 :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.i8 q10, q13, q12 :: Qd 0x5555550b 0x5555550b 0x5555550b 0x5555550b  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmls.i16 q4, q5, q6 :: Qd 0x55559359 0x55559359 0x55559359 0x55559359  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmls.i32 q7, q8, q9 :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.i32 q10, q11, q15 :: Qd 0x55556095 0x55556095 0x55556095 0x55556095  Qm (i32)0xffffffe8  Qn (i32)0x00000078
+---- VMUL ----
+vmul.i32 q0, q1, q2 :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmul.i32 q6, q7, q8 :: Qd 0xffffbe60 0xffffbe60 0xffffbe60 0xffffbe60  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmul.i16 q9, q11, q12 :: Qd 0x00006800 0x00006800 0x00006800 0x00006800  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmul.i8 q0, q1, q2 :: Qd 0x000000a0 0x000000a0 0x000000a0 0x000000a0  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmul.i8 q10, q11, q12 :: Qd 0x0000004a 0x0000004a 0x0000004a 0x0000004a  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmul.i16 q4, q5, q6 :: Qd 0x0000a002 0x0000a002 0x0000a002 0x0000a002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmul.i32 q7, q8, q9 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmul.i8 q10, q11, q12 :: Qd 0x0000c00e 0x0000c00e 0x0000c00e 0x0000c00e  Qm (i32)0x0200feb2  Qn (i32)0x000020df
+vmul.i16 q4, q5, q6 :: Qd 0x00008866 0x00008866 0x00008866 0x00008866  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmul.i32 q7, q8, q9 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x0000000c
+vmul.i8 q10, q13, q12 :: Qd 0x0000004a 0x0000004a 0x0000004a 0x0000004a  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmul.i16 q4, q5, q6 :: Qd 0x0000c1fc 0x0000c1fc 0x0000c1fc 0x0000c1fc  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmul.i32 q7, q8, q9 :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmul.i32 q10, q11, q15 :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmul.p8 q0, q1, q2 :: Qd 0x00000005 0x00000005 0x00000005 0x00000005  Qm (i32)0x00000003  Qn (i32)0x00000003
+vmul.p8 q0, q1, q2 :: Qd 0x00000044 0x00000044 0x00000044 0x00000044  Qm (i32)0x0000000c  Qn (i8)0x0000000f
+---- VMUL (by scalar) ----
+vmul.i32 q0, q1, d4[0] :: Qd 0x00000b40 0x00000b40 0x00000b40 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmul.i32 q15, q8, d7[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmul.i16 q10, q9, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmul.i16 q4, q5, d6[2] :: Qd 0x0000a002 0x0000a002 0x0000a002 0x0000a002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmul.i32 q4, q8, d15[1] :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmul.i16 q4, q5, d6[0] :: Qd 0xdffe8866 0xdffe8866 0xdffe8866 0xdffe8866  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmul.i32 q7, q8, d1[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmul.i16 q4, q5, d6[0] :: Qd 0x2000c1fc 0x2000c1fc 0x2000c1fc 0x2000c1fc  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmul.i32 q7, q8, d1[1] :: Qd 0x80000002 0x80000002 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VMLA (by scalar) ----
+vmla.i32 q0, q1, d4[0] :: Qd 0x55556095 0x55556095 0x55556095 0x55556095  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmla.i32 q15, q8, d7[1] :: Qd 0x555513b5 0x555513b5 0x555513b5 0x555513b5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmla.i16 q10, q9, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmla.i16 q4, q5, d6[2] :: Qd 0x5555f557 0x5555f557 0x5555f557 0x5555f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmla.i32 q4, q8, d15[1] :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.i16 q4, q5, d6[0] :: Qd 0x3553ddbb 0x3553ddbb 0x3553ddbb 0x3553ddbb  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmla.i32 q7, q8, d1[1] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmla.i16 q4, q5, d6[0] :: Qd 0x75551751 0x75551751 0x75551751 0x75551751  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmla.i32 q7, q8, d1[1] :: Qd 0xd5555557 0xd5555557 0xd5555557 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VMLS (by scalar) ----
+vmls.i32 q0, q1, d4[0] :: Qd 0x55554a15 0x55554a15 0x55554a15 0x55554a15  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmls.i32 q15, q8, d7[1] :: Qd 0x555596f5 0x555596f5 0x555596f5 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmls.i16 q10, q9, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmls.i16 q4, q5, d6[2] :: Qd 0x5555b553 0x5555b553 0x5555b553 0x5555b553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmls.i32 q4, q8, d15[1] :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.i16 q4, q5, d6[0] :: Qd 0x7557ccef 0x7557ccef 0x7557ccef 0x7557ccef  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmls.i32 q7, q8, d1[1] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmls.i16 q4, q5, d6[0] :: Qd 0x35559359 0x35559359 0x35559359 0x35559359  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmls.i32 q7, q8, d1[1] :: Qd 0xd5555553 0xd5555553 0xd5555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VMULL (by scalar) ----
+vmull.s32 q0, d2, d4[0] :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmull.s32 q15, d8, d7[1] :: Qd 0xffffffff 0xffffbe60 0xffffffff 0xffffbe60  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmull.s16 q10, d31, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmull.s16 q4, d5, d6[2] :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmull.s32 q4, d7, d15[1] :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmull.s16 q4, d5, d6[0] :: Qd 0xffffdffe 0xf2858866 0xffffdffe 0xf2858866  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmull.s32 q7, d7, d1[1] :: Qd 0xfff9fffa 0x00000000 0xfff9fffa 0x00000000  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmull.s16 q4, d5, d6[0] :: Qd 0x02002000 0x001fc1fc 0x02002000 0x001fc1fc  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmull.s32 q7, d7, d1[1] :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmull.u32 q0, d1, d4[0] :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmull.u32 q15, d8, d7[1] :: Qd 0x00000046 0x0000008c 0x00000046 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmull.u16 q10, d31, d7[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmull.u16 q4, d5, d6[2] :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmull.u32 q4, d7, d15[1] :: Qd 0x40000001 0x80000002 0x40000001 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmull.u16 q4, d5, d6[0] :: Qd 0x2001dffe 0x12878866 0x2001dffe 0x12878866  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmull.u32 q7, d7, d1[1] :: Qd 0x00060006 0x00000000 0x00060006 0x00000000  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmull.u16 q4, d5, d6[0] :: Qd 0x02002000 0x001fc1fc 0x02002000 0x001fc1fc  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmull.u32 q7, d7, d1[1] :: Qd 0x40000001 0x80000002 0x40000001 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VMLAL (by scalar) ----
+vmlal.s32 q0, d2, d4[0] :: Qd 0x55555555 0x55556095 0x55555555 0x55556095  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmlal.s32 q15, d8, d7[1] :: Qd 0x55555555 0x555513b5 0x55555555 0x555513b5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmlal.s16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlal.s16 q4, d5, d6[2] :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlal.s32 q4, d7, d15[1] :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlal.s16 q4, d5, d6[0] :: Qd 0x55553553 0x47daddbb 0x55553553 0x47daddbb  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmlal.s32 q7, d7, d1[1] :: Qd 0x554f554f 0x55555555 0x554f554f 0x55555555  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmlal.s16 q4, d5, d6[0] :: Qd 0x57557555 0x55751751 0x57557555 0x55751751  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmlal.s32 q7, d7, d1[1] :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlal.u32 q0, d1, d4[0] :: Qd 0x00000018 0x00000b58 0x55555555 0x55556095  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmlal.u32 q15, d8, d7[1] :: Qd 0x5555559b 0x555555e1 0x5555559b 0x555555e1  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmlal.u16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlal.u16 q4, d5, d6[2] :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlal.u32 q4, d7, d15[1] :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlal.u16 q4, d5, d6[0] :: Qd 0x75573553 0x67dcddbb 0x75573553 0x67dcddbb  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmlal.u32 q7, d7, d1[1] :: Qd 0x555b555b 0x55555555 0x555b555b 0x55555555  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmlal.u16 q4, d5, d6[0] :: Qd 0x57557555 0x55751751 0x57557555 0x55751751  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmlal.u32 q7, d7, d1[1] :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VMLSL (by scalar) ----
+vmlsl.s32 q0, d2, d4[0] :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmlsl.s32 q15, d8, d7[1] :: Qd 0x55555555 0x555596f5 0x55555555 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmlsl.s16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlsl.s16 q4, d5, d6[2] :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlsl.s32 q4, d7, d15[1] :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlsl.s16 q4, d5, d6[0] :: Qd 0x55557557 0x62cfccef 0x55557557 0x62cfccef  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmlsl.s32 q7, d7, d1[1] :: Qd 0x555b555b 0x55555555 0x555b555b 0x55555555  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmlsl.s16 q4, d5, d6[0] :: Qd 0x53553555 0x55359359 0x53553555 0x55359359  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmlsl.s32 q7, d7, d1[1] :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlsl.u32 q0, d1, d4[0] :: Qd 0x00000017 0xfffff4d8 0x55555555 0x55554a15  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmlsl.u32 q15, d8, d7[1] :: Qd 0x5555550f 0x555554c9 0x5555550f 0x555554c9  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmlsl.u16 q10, d31, d7[3] :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlsl.u16 q4, d5, d6[2] :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlsl.u32 q4, d7, d15[1] :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlsl.u16 q4, d5, d6[0] :: Qd 0x35537557 0x42cdccef 0x35537557 0x42cdccef  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmlsl.u32 q7, d7, d1[1] :: Qd 0x554f554f 0x55555555 0x554f554f 0x55555555  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmlsl.u16 q4, d5, d6[0] :: Qd 0x53553555 0x55359359 0x53553555 0x55359359  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmlsl.u32 q7, d7, d1[1] :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VRSHR ----
+vrshr.s8 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vrshr.s8 q0, q1, #1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff
+vrshr.s16 q3, q4, #2 :: Qd 0x0000ffe1 0x0000ffe1 0x0000ffe1 0x0000ffe1  Qm (i32)0xffffff84
+vrshr.s32 q2, q5, #31 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xffffffff
+vrshr.s8 q6, q7, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000ffff
+vrshr.s16 q8, q9, #12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xfffffff6
+vrshr.s32 q10, q11, #5 :: Qd 0x00000140 0x00000140 0x00000140 0x00000140  Qm (i32)0x000027fa
+vrshr.u8 q12, q13, #1 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080  Qm (i32)0xffffffff
+vrshr.u16 q14, q15, #11 :: Qd 0x00200020 0x00200020 0x00200020 0x00200020  Qm (i32)0xffffffff
+vrshr.u32 q10, q11, #9 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x000003e8
+vrshr.u8 q7, q13, #7 :: Qd 0x02020202 0x02020202 0x02020202 0x02020202  Qm (i32)0xffffffff
+vrshr.u16 q8, q1, #5 :: Qd 0x0000055e 0x0000055e 0x0000055e 0x0000055e  Qm (i32)0x0000abcf
+vrshr.u32 q12, q3, #15 :: Qd 0x00020000 0x00020000 0x00020000 0x00020000  Qm (i32)0xfffffe50
+vrshr.u64 q0, q1, #42 :: Qd 0x00000000 0x00400000 0x00000000 0x00400000  Qm (i32)0xffffffff
+vrshr.s64 q6, q7, #12 :: Qd 0x00000000 0xfac00001 0x00000000 0xfac00001  Qm (i32)0x00000fac
+vrshr.u64 q8, q4, #9 :: Qd 0x0000001a 0x7c00001a 0x0000001a 0x7c00001a  Qm (i32)0x000034f8
+vrshr.s64 q9, q12, #11 :: Qd 0x00000030 0x32c00030 0x00000030 0x32c00030  Qm (i32)0x00018196
+---- VRSRA ----
+vrsra.s8 q0, q1, #1 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0xffffffff
+vrsra.s16 q3, q4, #2 :: Qd 0x55555536 0x55555536 0x55555536 0x55555536  Qm (i32)0xffffff84
+vrsra.s32 q2, q5, #31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0xffffffff
+vrsra.s8 q6, q7, #7 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x0000ffff
+vrsra.s16 q8, q9, #12 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0xfffffff6
+vrsra.s32 q10, q11, #5 :: Qd 0x55555695 0x55555695 0x55555695 0x55555695  Qm (i32)0x000027fa
+vrsra.u8 q12, q13, #1 :: Qd 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5  Qm (i32)0xffffffff
+vrsra.u16 q14, q15, #11 :: Qd 0x55755575 0x55755575 0x55755575 0x55755575  Qm (i32)0xffffffff
+vrsra.u32 q10, q11, #9 :: Qd 0x55555557 0x55555557 0x55555557 0x55555557  Qm (i32)0x000003e8
+vrsra.u8 q7, q13, #7 :: Qd 0x57575757 0x57575757 0x57575757 0x57575757  Qm (i32)0xffffffff
+vrsra.u16 q8, q1, #5 :: Qd 0x55555ab3 0x55555ab3 0x55555ab3 0x55555ab3  Qm (i32)0x0000abcf
+vrsra.u32 q12, q3, #15 :: Qd 0x55575555 0x55575555 0x55575555 0x55575555  Qm (i32)0xfffffe50
+vrsra.u64 q0, q1, #42 :: Qd 0x55555555 0x55955555 0x55555555 0x55955555  Qm (i32)0xffffffff
+vrsra.s64 q6, q7, #12 :: Qd 0x55555556 0x50155556 0x55555556 0x50155556  Qm (i32)0x00000fac
+vrsra.u64 q8, q4, #9 :: Qd 0x5555556f 0xd155556f 0x5555556f 0xd155556f  Qm (i32)0x000034f8
+vrsra.s64 q9, q12, #11 :: Qd 0x55555585 0x88155585 0x55555585 0x88155585  Qm (i32)0x00018196
+---- VSHR ----
+vshr.s8 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshr.s8 q0, q1, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshr.s16 q3, q4, #2 :: Qd 0xffffffe1 0xffffffe1 0xffffffe1 0xffffffe1  Qm (i32)0xffffff84
+vshr.s32 q2, q5, #31 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshr.s8 q6, q7, #7 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x0000ffff
+vshr.s16 q8, q9, #12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xfffffff6
+vshr.s32 q10, q11, #5 :: Qd 0x0000013f 0x0000013f 0x0000013f 0x0000013f  Qm (i32)0x000027fa
+vshr.u8 q12, q13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f  Qm (i32)0xffffffff
+vshr.u16 q14, q15, #11 :: Qd 0x001f001f 0x001f001f 0x001f001f 0x001f001f  Qm (i32)0xffffffff
+vshr.u32 q10, q11, #9 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x000003e8
+vshr.u8 q7, q13, #7 :: Qd 0x01010101 0x01010101 0x01010101 0x01010101  Qm (i32)0xffffffff
+vshr.u16 q8, q1, #5 :: Qd 0x0000055e 0x0000055e 0x0000055e 0x0000055e  Qm (i32)0x0000abcf
+vshr.u32 q12, q3, #15 :: Qd 0x0001ffff 0x0001ffff 0x0001ffff 0x0001ffff  Qm (i32)0xfffffe50
+vshr.u64 q0, q1, #42 :: Qd 0x00000000 0x003fffff 0x00000000 0x003fffff  Qm (i32)0xffffffff
+vshr.s64 q6, q7, #12 :: Qd 0x00000000 0xfac00000 0x00000000 0xfac00000  Qm (i32)0x00000fac
+vshr.u64 q8, q4, #9 :: Qd 0x0000001a 0x7c00001a 0x0000001a 0x7c00001a  Qm (i32)0x000034f8
+vshr.s64 q9, q12, #11 :: Qd 0x00000030 0x32c00030 0x00000030 0x32c00030  Qm (i32)0x00018196
+---- VSRA ----
+vsra.s8 q0, q1, #1 :: Qd 0x54545454 0x54545454 0x54545454 0x54545454  Qm (i32)0xffffffff
+vsra.s16 q3, q4, #2 :: Qd 0x55545536 0x55545536 0x55545536 0x55545536  Qm (i32)0xffffff84
+vsra.s32 q2, q5, #31 :: Qd 0x55555554 0x55555554 0x55555554 0x55555554  Qm (i32)0xffffffff
+vsra.s8 q6, q7, #7 :: Qd 0x55555454 0x55555454 0x55555454 0x55555454  Qm (i32)0x0000ffff
+vsra.s16 q8, q9, #12 :: Qd 0x55545554 0x55545554 0x55545554 0x55545554  Qm (i32)0xfffffff6
+vsra.s32 q10, q11, #5 :: Qd 0x55555694 0x55555694 0x55555694 0x55555694  Qm (i32)0x000027fa
+vsra.u8 q12, q13, #1 :: Qd 0xd4d4d4d4 0xd4d4d4d4 0xd4d4d4d4 0xd4d4d4d4  Qm (i32)0xffffffff
+vsra.u16 q14, q15, #11 :: Qd 0x55745574 0x55745574 0x55745574 0x55745574  Qm (i32)0xffffffff
+vsra.u32 q10, q11, #9 :: Qd 0x55555556 0x55555556 0x55555556 0x55555556  Qm (i32)0x000003e8
+vsra.u8 q7, q13, #7 :: Qd 0x56565656 0x56565656 0x56565656 0x56565656  Qm (i32)0xffffffff
+vsra.u16 q8, q1, #5 :: Qd 0x55555ab3 0x55555ab3 0x55555ab3 0x55555ab3  Qm (i32)0x0000abcf
+vsra.u32 q12, q3, #15 :: Qd 0x55575554 0x55575554 0x55575554 0x55575554  Qm (i32)0xfffffe50
+vsra.u64 q0, q1, #42 :: Qd 0x55555555 0x55955554 0x55555555 0x55955554  Qm (i32)0xffffffff
+vsra.s64 q6, q7, #12 :: Qd 0x55555556 0x50155555 0x55555556 0x50155555  Qm (i32)0x00000fac
+vsra.u64 q8, q4, #9 :: Qd 0x5555556f 0xd155556f 0x5555556f 0xd155556f  Qm (i32)0x000034f8
+vsra.s64 q9, q12, #11 :: Qd 0x55555585 0x88155585 0x55555585 0x88155585  Qm (i32)0x00018196
+---- VSRI ----
+vsri.16 q0, q1, #1 :: Qd 0x7fff7fff 0x7fff7fff 0x7fff7fff 0x7fff7fff  Qm (i32)0xffffffff
+vsri.16 q3, q4, #2 :: Qd 0x7fff7fe1 0x7fff7fe1 0x7fff7fe1 0x7fff7fe1  Qm (i32)0xffffff84
+vsri.32 q2, q5, #31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0xffffffff
+vsri.8 q6, q7, #7 :: Qd 0x54545555 0x54545555 0x54545555 0x54545555  Qm (i32)0x0000ffff
+vsri.16 q8, q9, #12 :: Qd 0x555f555f 0x555f555f 0x555f555f 0x555f555f  Qm (i32)0xfffffff6
+vsri.32 q10, q11, #5 :: Qd 0x5000013f 0x5000013f 0x5000013f 0x5000013f  Qm (i32)0x000027fa
+vsri.8 q12, q13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f 0x7f7f7f7f  Qm (i32)0xffffffff
+vsri.16 q14, q15, #11 :: Qd 0x555f555f 0x555f555f 0x555f555f 0x555f555f  Qm (i32)0xffffffff
+vsri.32 q10, q11, #9 :: Qd 0x55000001 0x55000001 0x55000001 0x55000001  Qm (i32)0x000003e8
+vsri.8 q7, q13, #7 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0xffffffff
+vsri.16 q8, q1, #5 :: Qd 0x5000555e 0x5000555e 0x5000555e 0x5000555e  Qm (i32)0x0000abcf
+vsri.32 q12, q3, #15 :: Qd 0x5555ffff 0x5555ffff 0x5555ffff 0x5555ffff  Qm (i32)0xfffffe50
+vsri.64 q0, q1, #42 :: Qd 0x55555555 0x557fffff 0x55555555 0x557fffff  Qm (i32)0xffffffff
+vsri.64 q6, q7, #12 :: Qd 0x55500000 0xfac00000 0x55500000 0xfac00000  Qm (i32)0x00000fac
+vsri.64 q8, q4, #9 :: Qd 0x5500001a 0x7c00001a 0x5500001a 0x7c00001a  Qm (i32)0x000034f8
+vsri.64 q9, q12, #11 :: Qd 0x55400030 0x32c00030 0x55400030 0x32c00030  Qm (i32)0x00018196
+---- VMOVL ----
+vmovl.u32 q0, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042  Qm (i32)0x00000042
+vmovl.u16 q15, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042  Qm (i32)0x00000042
+vmovl.u8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x00000042
+vmovl.s32 q0, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042  Qm (i32)0x00000042
+vmovl.s16 q15, d2 :: Qd 0x00000000 0x00000042 0x00000000 0x00000042  Qm (i32)0x00000042
+vmovl.s8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i32)0x00000042
+vmovl.u32 q0, d2 :: Qd 0x00000000 0xedededed 0x00000000 0xedededed  Qm (i8)0x000000ed
+vmovl.u16 q15, d2 :: Qd 0x0000eded 0x0000eded 0x0000eded 0x0000eded  Qm (i8)0x000000ed
+vmovl.u8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i8)0x000000ed
+vmovl.s32 q0, d2 :: Qd 0xffffffff 0xedededed 0xffffffff 0xedededed  Qm (i8)0x000000ed
+vmovl.s16 q15, d2 :: Qd 0xffffeded 0xffffeded 0xffffeded 0xffffeded  Qm (i8)0x000000ed
+vmovl.s8 q3, d31 :: Qd 0x55555555 0x55555555 0x55555555 0x55555555  Qm (i8)0x000000ed
+---- VABS ----
+vabs.s32 q0, q1 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073  Qm (i32)0x00000073
+vabs.s16 q15, q4 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073  Qm (i32)0x00000073
+vabs.s8 q8, q7 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073  Qm (i32)0x00000073
+vabs.s32 q0, q1 :: Qd 0x000000fe 0x000000fe 0x000000fe 0x000000fe  Qm (i32)0x000000fe
+vabs.s16 q15, q4 :: Qd 0x000000ef 0x000000ef 0x000000ef 0x000000ef  Qm (i32)0x000000ef
+vabs.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022  Qm (i32)0x000000de
+vabs.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6  Qm (i16)0x0000fe0a
+vabs.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5  Qm (i16)0x0000ef0b
+vabs.s8 q8, q7 :: Qd 0x220c220c 0x220c220c 0x220c220c 0x220c220c  Qm (i16)0x0000de0c
+---- VQABS ----
+vqabs.s32 q0, q1 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073  Qm (i32)0x00000073  fpscr: 00000000
+vqabs.s32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  fpscr: 08000000
+vqabs.s16 q0, q1 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  fpscr: 08000000
+vqabs.s8 q0, q1 :: Qd 0x7f000000 0x7f000000 0x7f000000 0x7f000000  Qm (i32)0x80000000  fpscr: 08000000
+vqabs.s16 q15, q4 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073  Qm (i32)0x00000073  fpscr: 00000000
+vqabs.s8 q8, q7 :: Qd 0x00000073 0x00000073 0x00000073 0x00000073  Qm (i32)0x00000073  fpscr: 00000000
+vqabs.s32 q0, q1 :: Qd 0x000000fe 0x000000fe 0x000000fe 0x000000fe  Qm (i32)0x000000fe  fpscr: 00000000
+vqabs.s16 q15, q4 :: Qd 0x000000ef 0x000000ef 0x000000ef 0x000000ef  Qm (i32)0x000000ef  fpscr: 00000000
+vqabs.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022  Qm (i32)0x000000de  fpscr: 00000000
+vqabs.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6  Qm (i16)0x0000fe0a  fpscr: 00000000
+vqabs.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5  Qm (i16)0x0000ef0b  fpscr: 00000000
+vqabs.s8 q8, q7 :: Qd 0x220c220c 0x220c220c 0x220c220c 0x220c220c  Qm (i16)0x0000de0c  fpscr: 00000000
+---- VADDW ----
+vaddw.s32 q0, q1, d4 :: Qd 0x00000073 0x12121285 0x00000073 0x12121285  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddw.s16 q15, q14, d4 :: Qd 0x00001285 0x00001285 0x00001285 0x00001285  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddw.s8 q0, q1, d31 :: Qd 0x00120085 0x00120085 0x00120085 0x00120085  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddw.u32 q0, q1, d4 :: Qd 0x00000073 0x12121285 0x00000073 0x12121285  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddw.u16 q0, q1, d4 :: Qd 0x00001285 0x00001285 0x00001285 0x00001285  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddw.u8 q0, q1, d4 :: Qd 0x00120085 0x00120085 0x00120085 0x00120085  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddw.s32 q0, q1, d4 :: Qd 0x00000072 0xe2e2e355 0x00000072 0xe2e2e355  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddw.s16 q15, q14, d4 :: Qd 0xffffe355 0xffffe355 0xffffe355 0xffffe355  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddw.s8 q0, q1, d31 :: Qd 0xffe20055 0xffe20055 0xffe20055 0xffe20055  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddw.u32 q0, q1, d4 :: Qd 0x00000073 0xe2e2e355 0x00000073 0xe2e2e355  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddw.u16 q0, q1, d4 :: Qd 0x0000e355 0x0000e355 0x0000e355 0x0000e355  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddw.u8 q0, q1, d4 :: Qd 0x00e20155 0x00e20155 0x00e20155 0x00e20155  Qm (i32)0x00000073  Qn (i8)0x000000e2
+---- VADDL ----
+vaddl.s32 q0, d2, d4 :: Qd 0x00000000 0x12121285 0x00000000 0x12121285  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddl.s16 q15, d14, d4 :: Qd 0x00001212 0x00001285 0x00001212 0x00001285  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddl.s8 q0, d2, d31 :: Qd 0x00120012 0x00120085 0x00120012 0x00120085  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0x12121285 0x00000000 0x12121285  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddl.u16 q0, d2, d4 :: Qd 0x00001212 0x00001285 0x00001212 0x00001285  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddl.u8 q0, d2, d4 :: Qd 0x00120012 0x00120085 0x00120012 0x00120085  Qm (i32)0x00000073  Qn (i8)0x00000012
+vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0xe2e2e355 0xffffffff 0xe2e2e355  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddl.s16 q15, d14, d4 :: Qd 0xffffe2e2 0xffffe355 0xffffe2e2 0xffffe355  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddl.s8 q0, d2, d31 :: Qd 0xffe2ffe2 0xffe20055 0xffe2ffe2 0xffe20055  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0xe2e2e355 0x00000000 0xe2e2e355  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddl.u16 q0, d2, d4 :: Qd 0x0000e2e2 0x0000e355 0x0000e2e2 0x0000e355  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddl.u8 q0, d2, d4 :: Qd 0x00e200e2 0x00e20155 0x00e200e2 0x00e20155  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0xa5a5a5a5 0xffffffff 0xa5a5a5a5  Qm (i8)0x00000093  Qn (i8)0x00000012
+vaddl.s16 q15, d14, d4 :: Qd 0xffffa5a5 0xffffa5a5 0xffffa5a5 0xffffa5a5  Qm (i8)0x00000093  Qn (i8)0x00000012
+vaddl.s8 q0, d2, d31 :: Qd 0xffabffab 0xffabffab 0xffabffab 0xffabffab  Qm (i8)0x00000099  Qn (i8)0x00000012
+vaddl.u32 q0, d2, d4 :: Qd 0x00000000 0xa5a5a5a5 0x00000000 0xa5a5a5a5  Qm (i8)0x00000093  Qn (i8)0x00000012
+vaddl.u16 q0, d2, d4 :: Qd 0x0000a5a5 0x0000a5a5 0x0000a5a5 0x0000a5a5  Qm (i8)0x00000093  Qn (i8)0x00000012
+vaddl.u8 q0, d2, d4 :: Qd 0x00a500a5 0x00a500a5 0x00a500a5 0x00a500a5  Qm (i8)0x00000093  Qn (i8)0x00000012
+vaddl.s32 q0, d2, d4 :: Qd 0xffffffff 0x76767675 0xffffffff 0x76767675  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vaddl.s16 q15, d14, d4 :: Qd 0xffff7675 0xffff7675 0xffff7675 0xffff7675  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vaddl.s8 q0, d2, d31 :: Qd 0xff75ff75 0xff75ff75 0xff75ff75 0xff75ff75  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vaddl.u32 q0, d2, d4 :: Qd 0x00000001 0x76767675 0x00000001 0x76767675  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vaddl.u16 q0, d2, d4 :: Qd 0x00017675 0x00017675 0x00017675 0x00017675  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vaddl.u8 q0, d2, d4 :: Qd 0x01750175 0x01750175 0x01750175 0x01750175  Qm (i8)0x00000093  Qn (i8)0x000000e2
+---- VSUBW ----
+vsubw.s32 q0, q1, d4 :: Qd 0x00000072 0xededee61 0x00000072 0xededee61  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubw.s16 q15, q14, d4 :: Qd 0xffffee61 0xffffee61 0xffffee61 0xffffee61  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubw.s8 q0, q1, d31 :: Qd 0xffee0061 0xffee0061 0xffee0061 0xffee0061  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubw.u32 q0, q1, d4 :: Qd 0x00000072 0xededee61 0x00000072 0xededee61  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubw.u16 q0, q1, d4 :: Qd 0xffffee61 0xffffee61 0xffffee61 0xffffee61  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubw.u8 q0, q1, d4 :: Qd 0xffee0061 0xffee0061 0xffee0061 0xffee0061  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubw.s32 q0, q1, d4 :: Qd 0x00000073 0x1d1d1d91 0x00000073 0x1d1d1d91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubw.s16 q15, q14, d4 :: Qd 0x00001d91 0x00001d91 0x00001d91 0x00001d91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubw.s8 q0, q1, d31 :: Qd 0x001e0091 0x001e0091 0x001e0091 0x001e0091  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubw.u32 q0, q1, d4 :: Qd 0x00000072 0x1d1d1d91 0x00000072 0x1d1d1d91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubw.u16 q0, q1, d4 :: Qd 0xffff1d91 0xffff1d91 0xffff1d91 0xffff1d91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubw.u8 q0, q1, d4 :: Qd 0xff1eff91 0xff1eff91 0xff1eff91 0xff1eff91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+---- VSUBL ----
+vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0xededee61 0xffffffff 0xededee61  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubl.s16 q15, d14, d4 :: Qd 0xffffedee 0xffffee61 0xffffedee 0xffffee61  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubl.s8 q0, d2, d31 :: Qd 0xffeeffee 0xffee0061 0xffeeffee 0xffee0061  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0xededee61 0xffffffff 0xededee61  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubl.u16 q0, d2, d4 :: Qd 0xffffedee 0xffffee61 0xffffedee 0xffffee61  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubl.u8 q0, d2, d4 :: Qd 0xffeeffee 0xffee0061 0xffeeffee 0xffee0061  Qm (i32)0x00000073  Qn (i8)0x00000012
+vsubl.s32 q0, d2, d4 :: Qd 0x00000000 0x1d1d1d91 0x00000000 0x1d1d1d91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubl.s16 q15, d14, d4 :: Qd 0x00001d1e 0x00001d91 0x00001d1e 0x00001d91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubl.s8 q0, d2, d31 :: Qd 0x001e001e 0x001e0091 0x001e001e 0x001e0091  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0x1d1d1d91 0xffffffff 0x1d1d1d91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubl.u16 q0, d2, d4 :: Qd 0xffff1d1e 0xffff1d91 0xffff1d1e 0xffff1d91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubl.u8 q0, d2, d4 :: Qd 0xff1eff1e 0xff1eff91 0xff1eff1e 0xff1eff91  Qm (i32)0x00000073  Qn (i8)0x000000e2
+vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0x81818181 0xffffffff 0x81818181  Qm (i8)0x00000093  Qn (i8)0x00000012
+vsubl.s16 q15, d14, d4 :: Qd 0xffff8181 0xffff8181 0xffff8181 0xffff8181  Qm (i8)0x00000093  Qn (i8)0x00000012
+vsubl.s8 q0, d2, d31 :: Qd 0xff87ff87 0xff87ff87 0xff87ff87 0xff87ff87  Qm (i8)0x00000099  Qn (i8)0x00000012
+vsubl.u32 q0, d2, d4 :: Qd 0x00000000 0x81818181 0x00000000 0x81818181  Qm (i8)0x00000093  Qn (i8)0x00000012
+vsubl.u16 q0, d2, d4 :: Qd 0x00008181 0x00008181 0x00008181 0x00008181  Qm (i8)0x00000093  Qn (i8)0x00000012
+vsubl.u8 q0, d2, d4 :: Qd 0x00810081 0x00810081 0x00810081 0x00810081  Qm (i8)0x00000093  Qn (i8)0x00000012
+vsubl.s32 q0, d2, d4 :: Qd 0xffffffff 0xb0b0b0b1 0xffffffff 0xb0b0b0b1  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vsubl.s16 q15, d14, d4 :: Qd 0xffffb0b1 0xffffb0b1 0xffffb0b1 0xffffb0b1  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vsubl.s8 q0, d2, d31 :: Qd 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vsubl.u32 q0, d2, d4 :: Qd 0xffffffff 0xb0b0b0b1 0xffffffff 0xb0b0b0b1  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vsubl.u16 q0, d2, d4 :: Qd 0xffffb0b1 0xffffb0b1 0xffffb0b1 0xffffb0b1  Qm (i8)0x00000093  Qn (i8)0x000000e2
+vsubl.u8 q0, d2, d4 :: Qd 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1 0xffb1ffb1  Qm (i8)0x00000093  Qn (i8)0x000000e2
+---- VCEQ #0 ----
+vceq.i32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000021
+vceq.i16 q2, q1, #0 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000  Qm (i32)0x00000021
+vceq.i8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0x00000021
+vceq.i32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vceq.i16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vceq.i8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+---- VCGT #0 ----
+vcgt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000021
+vcgt.s16 q2, q1, #0 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff  Qm (i32)0x00000021
+vcgt.s8 q10, q11, #0 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x00000021
+vcgt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ef
+vcgt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ed
+vcgt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ae
+---- VCGE #0 ----
+vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000021
+vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000021
+vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000021
+vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcge.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcge.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ef
+vcge.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ed
+vcge.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ae
+vcge.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x000000ef
+vcge.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x000000ed
+vcge.s8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0x000000ae
+---- VCLE #0 ----
+vcle.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000021
+vcle.s16 q2, q1, #0 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000  Qm (i32)0x00000021
+vcle.s8 q10, q11, #0 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00  Qm (i32)0x00000021
+vcle.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ef
+vcle.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ed
+vcle.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ae
+---- VCLT #0 ----
+vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000021
+vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000021
+vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000021
+vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.s8 q10, q11, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.s32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ef
+vclt.s16 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ed
+vclt.s8 q10, q11, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i8)0x000000ae
+vclt.s32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x000000ef
+vclt.s16 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x000000ed
+vclt.s8 q10, q11, #0 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff  Qm (i32)0x000000ae
+---- VCNT ----
+vcnt.8 q0, q1 :: Qd 0x04050306 0x04050306 0x04050306 0x04050306  Qm (i32)0xac3d25eb
+vcnt.8 q11, q14 :: Qd 0x04050306 0x04050306 0x04050306 0x04050306  Qm (i32)0xac3d25eb
+vcnt.8 q6, q2 :: Qd 0x00020306 0x00020306 0x00020306 0x00020306  Qm (i32)0x000ad0eb
+---- VCLS ----
+vcls.s8 q0, q1 :: Qd 0x07070701 0x07070701 0x07070701 0x07070701  Qm (i32)0x00000021
+vcls.s8 q10, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x00000082
+vcls.s16 q0, q1 :: Qd 0x000f0009 0x000f0009 0x000f0009 0x000f0009  Qm (i32)0x00000021
+vcls.s16 q15, q10 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x00000082
+vcls.s32 q6, q1 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019  Qm (i32)0x00000021
+vcls.s32 q10, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x00000082
+vcls.s8 q2, q4 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707  Qm (i8)0x000000ff
+vcls.s16 q2, q4 :: Qd 0x000f000f 0x000f000f 0x000f000f 0x000f000f  Qm (i8)0x000000ff
+vcls.s32 q2, q4 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f  Qm (i8)0x000000ff
+vcls.s8 q2, q4 :: Qd 0x07020702 0x07020702 0x07020702 0x07020702  Qm (i16)0x0000ffef
+vcls.s16 q2, q4 :: Qd 0x000a000a 0x000a000a 0x000a000a 0x000a000a  Qm (i16)0x0000ffef
+vcls.s32 q2, q4 :: Qd 0x0000000a 0x0000000a 0x0000000a 0x0000000a  Qm (i16)0x0000ffef
+vcls.s8 q2, q4 :: Qd 0x07070707 0x07070707 0x07070707 0x07070707  Qm (i8)0x00000000
+vcls.s16 q2, q4 :: Qd 0x000f000f 0x000f000f 0x000f000f 0x000f000f  Qm (i8)0x00000000
+vcls.s32 q2, q4 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f  Qm (i8)0x00000000
+vcls.s8 q2, q4 :: Qd 0x07020702 0x07020702 0x07020702 0x07020702  Qm (i16)0x000000ef
+vcls.s16 q2, q4 :: Qd 0x00070007 0x00070007 0x00070007 0x00070007  Qm (i16)0x000000ef
+vcls.s32 q2, q4 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007  Qm (i16)0x000000ef
+---- VCLZ ----
+vclz.i8 q0, q1 :: Qd 0x08080802 0x08080802 0x08080802 0x08080802  Qm (i32)0x00000021
+vclz.i8 q10, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x00000082
+vclz.i16 q0, q1 :: Qd 0x0010000a 0x0010000a 0x0010000a 0x0010000a  Qm (i32)0x00000021
+vclz.i16 q15, q10 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x00000082
+vclz.i32 q6, q1 :: Qd 0x0000001a 0x0000001a 0x0000001a 0x0000001a  Qm (i32)0x00000021
+vclz.i32 q10, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x00000082
+vclz.i8 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ff
+vclz.i16 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ff
+vclz.i32 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i8)0x000000ff
+vclz.i8 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i16)0x0000ffef
+vclz.i16 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i16)0x0000ffef
+vclz.i32 q2, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i16)0x0000ffef
+vclz.i8 q2, q4 :: Qd 0x08080808 0x08080808 0x08080808 0x08080808  Qm (i8)0x00000000
+vclz.i16 q2, q4 :: Qd 0x00100010 0x00100010 0x00100010 0x00100010  Qm (i8)0x00000000
+vclz.i32 q2, q4 :: Qd 0x00000020 0x00000020 0x00000020 0x00000020  Qm (i8)0x00000000
+vclz.i8 q2, q4 :: Qd 0x08000800 0x08000800 0x08000800 0x08000800  Qm (i16)0x000000ef
+vclz.i16 q2, q4 :: Qd 0x00080008 0x00080008 0x00080008 0x00080008  Qm (i16)0x000000ef
+vclz.i32 q2, q4 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i16)0x000000ef
+---- VSLI ----
+vsli.16 q0, q1, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vsli.16 q3, q4, #2 :: Qd 0xfffdfe11 0xfffdfe11 0xfffdfe11 0xfffdfe11  Qm (i32)0xffffff84
+vsli.32 q2, q5, #31 :: Qd 0xd5555555 0xd5555555 0xd5555555 0xd5555555  Qm (i32)0xffffffff
+vsli.8 q6, q7, #7 :: Qd 0x5555d5d5 0x5555d5d5 0x5555d5d5 0x5555d5d5  Qm (i32)0x0000ffff
+vsli.16 q8, q9, #12 :: Qd 0xf5556555 0xf5556555 0xf5556555 0xf5556555  Qm (i32)0xfffffff6
+vsli.32 q10, q11, #5 :: Qd 0x0004ff55 0x0004ff55 0x0004ff55 0x0004ff55  Qm (i32)0x000027fa
+vsli.8 q12, q13, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vsli.16 q14, q15, #11 :: Qd 0xfd55fd55 0xfd55fd55 0xfd55fd55 0xfd55fd55  Qm (i32)0xffffffff
+vsli.32 q10, q11, #9 :: Qd 0x0007d155 0x0007d155 0x0007d155 0x0007d155  Qm (i32)0x000003e8
+vsli.8 q7, q13, #7 :: Qd 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5 0xd5d5d5d5  Qm (i32)0xffffffff
+vsli.16 q8, q1, #1 :: Qd 0x0001579f 0x0001579f 0x0001579f 0x0001579f  Qm (i32)0x0000abcf
+vsli.32 q12, q3, #15 :: Qd 0xff285555 0xff285555 0xff285555 0xff285555  Qm (i32)0xfffffe50
+vsli.64 q0, q1, #42 :: Qd 0xfffffd55 0x55555555 0xfffffd55 0x55555555  Qm (i32)0xffffffff
+vsli.64 q6, q7, #12 :: Qd 0x00fac000 0x00fac555 0x00fac000 0x00fac555  Qm (i32)0x00000fac
+vsli.64 q8, q4, #9 :: Qd 0x0069f000 0x0069f155 0x0069f000 0x0069f155  Qm (i32)0x000034f8
+vsli.64 q9, q12, #11 :: Qd 0x0c0cb000 0x0c0cb555 0x0c0cb000 0x0c0cb555  Qm (i32)0x00018196
+---- VPADDL ----
+vpaddl.u32 q0, q1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030  Qm (i32)0x00000018
+vpaddl.u32 q0, q1 :: Qd 0x00000000 0x00000118 0x00000000 0x00000118  Qm (i32)0x0000008c
+vpaddl.u16 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c
+vpaddl.u8 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c
+vpaddl.u8 q0, q1 :: Qd 0x00800001 0x00800001 0x00800001 0x00800001  Qm (i32)0x80000001
+vpaddl.u16 q0, q1 :: Qd 0x00008001 0x00008001 0x00008001 0x00008001  Qm (i32)0x80000001
+vpaddl.u32 q0, q1 :: Qd 0x00000001 0x00000002 0x00000001 0x00000002  Qm (i32)0x80000001
+vpaddl.u32 q10, q11 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030  Qm (i32)0x00000018
+vpaddl.s32 q0, q1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030  Qm (i32)0x00000018
+vpaddl.s32 q0, q1 :: Qd 0x00000000 0x00000118 0x00000000 0x00000118  Qm (i32)0x0000008c
+vpaddl.s16 q0, q1 :: Qd 0x0000008c 0x0000008c 0x0000008c 0x0000008c  Qm (i32)0x0000008c
+vpaddl.s8 q0, q1 :: Qd 0x0000ff8c 0x0000ff8c 0x0000ff8c 0x0000ff8c  Qm (i32)0x0000008c
+vpaddl.s8 q0, q1 :: Qd 0xff800001 0xff800001 0xff800001 0xff800001  Qm (i32)0x80000001
+vpaddl.s16 q0, q1 :: Qd 0xffff8001 0xffff8001 0xffff8001 0xffff8001  Qm (i32)0x80000001
+vpaddl.s32 q0, q1 :: Qd 0xffffffff 0x00000002 0xffffffff 0x00000002  Qm (i32)0x80000001
+vpaddl.s32 q10, q11 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030  Qm (i32)0x00000018
+---- VPADAL ----
+vpadal.u32 q0, q1 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585  Qm (i32)0x00000018
+vpadal.u32 q0, q1 :: Qd 0x55555555 0x5555566d 0x55555555 0x5555566d  Qm (i32)0x0000008c
+vpadal.u16 q0, q1 :: Qd 0x555555e1 0x555555e1 0x555555e1 0x555555e1  Qm (i32)0x0000008c
+vpadal.u8 q0, q1 :: Qd 0x566d566d 0x566d566d 0x566d566d 0x566d566d  Qm (i8)0x0000008c
+vpadal.u8 q0, q1 :: Qd 0x55d55556 0x55d55556 0x55d55556 0x55d55556  Qm (i32)0x80000001
+vpadal.u16 q0, q1 :: Qd 0x5555d556 0x5555d556 0x5555d556 0x5555d556  Qm (i32)0x80000001
+vpadal.u32 q0, q1 :: Qd 0x55555556 0x55555557 0x55555556 0x55555557  Qm (i32)0x80000001
+vpadal.u32 q10, q11 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585  Qm (i32)0x00000018
+vpadal.s32 q0, q1 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585  Qm (i32)0x00000018
+vpadal.s32 q0, q1 :: Qd 0x55555555 0x5555566d 0x55555555 0x5555566d  Qm (i32)0x0000008c
+vpadal.s16 q0, q1 :: Qd 0x555555e1 0x555555e1 0x555555e1 0x555555e1  Qm (i32)0x0000008c
+vpadal.s8 q0, q1 :: Qd 0x546d546d 0x546d546d 0x546d546d 0x546d546d  Qm (i8)0x0000008c
+vpadal.s8 q0, q1 :: Qd 0x54d55556 0x54d55556 0x54d55556 0x54d55556  Qm (i32)0x80000001
+vpadal.s16 q0, q1 :: Qd 0x5554d556 0x5554d556 0x5554d556 0x5554d556  Qm (i32)0x80000001
+vpadal.s32 q0, q1 :: Qd 0x55555554 0x55555557 0x55555554 0x55555557  Qm (i32)0x80000001
+vpadal.s32 q10, q11 :: Qd 0x55555555 0x55555585 0x55555555 0x55555585  Qm (i32)0x00000018
+---- VZIP ----
+vzip.32 q0, q1 :: Qm 0x34343434 0x12121212 0x34343434 0x12121212  Qn 0x34343434 0x12121212 0x34343434 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vzip.16 q1, q0 :: Qm 0x12123434 0x12123434 0x12123434 0x12123434  Qn 0x12123434 0x12123434 0x12123434 0x12123434  Qm (i8)0x00000012  Qn (i8)0x00000034
+vzip.8 q10, q11 :: Qm 0x34123412 0x34123412 0x34123412 0x34123412  Qn 0x34123412 0x34123412 0x34123412 0x34123412  Qm (i8)0x00000012  Qn (i8)0x00000034
+vzip.32 q0, q1 :: Qm 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678  Qn 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vzip.16 q1, q0 :: Qm 0x12340a0b 0x56780c0d 0x12340a0b 0x56780c0d  Qn 0x12340a0b 0x56780c0d 0x12340a0b 0x56780c0d  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vzip.8 q10, q11 :: Qm 0x0a120b34 0x0c560d78 0x0a120b34 0x0c560d78  Qn 0x0a120b34 0x0c560d78 0x0a120b34 0x0c560d78  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+---- VUZP ----
+vuzp.32 q0, q1 :: Qm 0x34343434 0x34343434 0x12121212 0x12121212  Qn 0x34343434 0x34343434 0x12121212 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vuzp.16 q1, q0 :: Qm 0x12121212 0x12121212 0x34343434 0x34343434  Qn 0x12121212 0x12121212 0x34343434 0x34343434  Qm (i8)0x00000012  Qn (i8)0x00000034
+vuzp.8 q10, q11 :: Qm 0x34343434 0x34343434 0x12121212 0x12121212  Qn 0x34343434 0x34343434 0x12121212 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vuzp.32 q0, q1 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x12345678 0x12345678  Qn 0x0a0b0c0d 0x0a0b0c0d 0x12345678 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vuzp.16 q1, q0 :: Qm 0x12341234 0x12341234 0x0a0b0a0b 0x0a0b0a0b  Qn 0x56785678 0x56785678 0x0c0d0c0d 0x0c0d0c0d  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vuzp.8 q10, q11 :: Qm 0x0b0d0b0d 0x0b0d0b0d 0x34783478 0x34783478  Qn 0x0a0c0a0c 0x0a0c0a0c 0x12561256 0x12561256  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+---- VTRN ----
+vtrn.32 q0, q1 :: Qm 0x34343434 0x12121212 0x34343434 0x12121212  Qn 0x34343434 0x12121212 0x34343434 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vtrn.16 q1, q0 :: Qm 0x12123434 0x12123434 0x12123434 0x12123434  Qn 0x12123434 0x12123434 0x12123434 0x12123434  Qm (i8)0x00000012  Qn (i8)0x00000034
+vtrn.8 q10, q11 :: Qm 0x34123412 0x34123412 0x34123412 0x34123412  Qn 0x34123412 0x34123412 0x34123412 0x34123412  Qm (i8)0x00000012  Qn (i8)0x00000034
+vtrn.32 q0, q1 :: Qm 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678  Qn 0x0a0b0c0d 0x12345678 0x0a0b0c0d 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vtrn.16 q1, q0 :: Qm 0x12340a0b 0x12340a0b 0x12340a0b 0x12340a0b  Qn 0x56780c0d 0x56780c0d 0x56780c0d 0x56780c0d  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vtrn.8 q10, q11 :: Qm 0x0b340d78 0x0b340d78 0x0b340d78 0x0b340d78  Qn 0x0a120c56 0x0a120c56 0x0a120c56 0x0a120c56  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+---- VSWP ----
+vswp q0, q1 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434  Qn 0x12121212 0x12121212 0x12121212 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vswp q1, q0 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434  Qn 0x12121212 0x12121212 0x12121212 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vswp q10, q11 :: Qm 0x34343434 0x34343434 0x34343434 0x34343434  Qn 0x12121212 0x12121212 0x12121212 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vswp q0, q1 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d  Qn 0x12345678 0x12345678 0x12345678 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vswp q1, q0 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d  Qn 0x12345678 0x12345678 0x12345678 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vswp q10, q11 :: Qm 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d 0x0a0b0c0d  Qn 0x12345678 0x12345678 0x12345678 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+---- VDUP ----
+vdup.8 q2, d2[0] :: Qd 0x57575757 0x57575757 0x57575757 0x57575757  Qm (i32)0x0abc4657
+vdup.8 q3, d3[2] :: Qd 0x07070707 0x07070707 0x07070707 0x07070707  Qm (i32)0x0007a1b3
+vdup.8 q1, d0[7] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00713aaa
+vdup.8 q0, d4[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x000aa713
+vdup.8 q4, d28[4] :: Qd 0xc3c3c3c3 0xc3c3c3c3 0xc3c3c3c3 0xc3c3c3c3  Qm (i32)0x0007b1c3
+vdup.16 q7, d19[3] :: Qd 0x07130713 0x07130713 0x07130713 0x07130713  Qm (i32)0x0713ffff
+vdup.16 q15, d31[0] :: Qd 0x00fa00fa 0x00fa00fa 0x00fa00fa 0x00fa00fa  Qm (i32)0x007f00fa
+vdup.16 q6, d2[0] :: Qd 0xbcdebcde 0xbcdebcde 0xbcdebcde 0xbcdebcde  Qm (i32)0x0ffabcde
+vdup.16 q8, d22[3] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000713
+vdup.16 q9, d2[0] :: Qd 0x07130713 0x07130713 0x07130713 0x07130713  Qm (i32)0x00000713
+vdup.32 q10, d17[1] :: Qd 0x00000713 0x00000713 0x00000713 0x00000713  Qm (i32)0x00000713
+vdup.32 q15, d11[0] :: Qd 0x00000003 0x00000003 0x00000003 0x00000003  Qm (i32)0x00000003
+vdup.32 q10, d29[1] :: Qd 0xf00000aa 0xf00000aa 0xf00000aa 0xf00000aa  Qm (i32)0xf00000aa
+vdup.32 q12, d0[1] :: Qd 0x0000000f 0x0000000f 0x0000000f 0x0000000f  Qm (i32)0x0000000f
+vdup.32 q13, d13[0] :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+---- VQDMULL ----
+vqdmull.s32 q0, d1, d2 :: Qd 0x00000000 0x00001680 0x00000000 0x00001680  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmull.s32 q6, d7, d8 :: Qd 0xffffffff 0xffff7cc0 0xffffffff 0xffff7cc0  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmull.s16 q9, d11, d12 :: Qd 0x00000000 0x0002d000 0x00000000 0x0002d000  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x10014004 0x00000000 0x10014004  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmull.s32 q7, d8, d9 :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0xe50b10cc 0x00000000 0xe50b10cc  Qm (i32)0xffff9433  Qn (i32)0x00002002  fpscr: 00000000
+vqdmull.s32 q7, d8, d9 :: Qd 0xfffffff4 0x00000000 0xfffffff4 0x00000000  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmull.s16 q4, d5, d6 :: Qd 0x00000000 0x003f83f8 0x00000000 0x003f83f8  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmull.s32 q7, d8, d9 :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmull.s32 q10, d11, d15 :: Qd 0x00000000 0x00001680 0x00000000 0x00001680  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmull.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmull.s16 q10, d30, d31 :: Qd 0x7fffffff 0x00000000 0x7fffffff 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmull.s32 q10, d30, d31 :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmull.s16 q10, d30, d31 :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VQDMULL (by scalar) ----
+vqdmull.s32 q0, d1, d7[0] :: Qd 0x00000000 0x00001680 0x00000000 0x00001680  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmull.s32 q6, d7, d6[0] :: Qd 0xffffffff 0xffff7cc0 0xffffffff 0xffff7cc0  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmull.s16 q9, d11, d7[2] :: Qd 0x00000000 0x0002d000 0x00000000 0x0002d000  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmull.s16 q4, d5, d6[2] :: Qd 0x00000000 0x10014004 0x00000000 0x10014004  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmull.s32 q7, d8, d3[1] :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmull.s16 q4, d5, d6[1] :: Qd 0xffffbffc 0xe50b10cc 0xffffbffc 0xe50b10cc  Qm (i32)0xffff9433  Qn (i16)0x00002002  fpscr: 00000000
+vqdmull.s32 q7, d8, d3[0] :: Qd 0xfffffff4 0x00000000 0xfffffff4 0x00000000  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmull.s16 q4, d5, d6[2] :: Qd 0x04004000 0x003f83f8 0x04004000 0x003f83f8  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmull.s32 q7, d8, d3[1] :: Qd 0x7ffffffd 0x00000004 0x7ffffffd 0x00000004  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmull.s32 q10, d11, d15[1] :: Qd 0x00000000 0x00001680 0x00000000 0x00001680  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmull.s32 q10, d30, d1[0] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmull.s16 q10, d30, d1[1] :: Qd 0x7fffffff 0x00000000 0x7fffffff 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmull.s32 q10, d30, d1[1] :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmull.s16 q10, d30, d1[3] :: Qd 0xc0000000 0x00000000 0xc0000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VQDMLSL ----
+vqdmlsl.s32 q0, d1, d2 :: Qd 0x00000017 0xffffe998 0x55555555 0x55553ed5  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmlsl.s32 q6, d7, d8 :: Qd 0x55555555 0x5555d895 0x55555555 0x5555d895  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmlsl.s16 q9, d11, d12 :: Qd 0x55555555 0x55528555 0x55555555 0x55528555  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x45541551 0x55555555 0x45541551  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlsl.s32 q7, d8, d9 :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x704a4489 0x55555555 0x704a4489  Qm (i32)0xffff9433  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlsl.s32 q7, d8, d9 :: Qd 0x55555561 0x55555555 0x55555561 0x55555555  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x5515d15d 0x55555555 0x5515d15d  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlsl.s32 q7, d8, d9 :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmlsl.s32 q10, d11, d15 :: Qd 0x55555555 0x55553ed5 0x55555555 0x55553ed5  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmlsl.s32 q10, d30, d31 :: Qd 0xd5555555 0x55555556 0xd5555555 0x55555556  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlsl.s16 q10, d30, d31 :: Qd 0xd5555556 0x55555555 0xd5555556 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlsl.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlsl.s16 q10, d30, d31 :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 08000000
+---- VQDMLSL (by scalar) ----
+vqdmlsl.s32 q0, d1, d7[0] :: Qd 0x00000017 0xffffe998 0x55555555 0x55553ed5  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmlsl.s32 q6, d7, d6[0] :: Qd 0x55555555 0x5555d895 0x55555555 0x5555d895  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmlsl.s16 q9, d11, d7[2] :: Qd 0x55555555 0x55528555 0x55555555 0x55528555  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x55555555 0x45541551 0x55555555 0x45541551  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlsl.s32 q7, d8, d3[1] :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmlsl.s16 q4, d5, d6[1] :: Qd 0x55559559 0x704a4489 0x55559559 0x704a4489  Qm (i32)0xffff9433  Qn (i16)0x00002002  fpscr: 00000000
+vqdmlsl.s32 q7, d8, d3[0] :: Qd 0x55555561 0x55555555 0x55555561 0x55555555  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmlsl.s16 q4, d5, d6[2] :: Qd 0x51551555 0x5515d15d 0x51551555 0x5515d15d  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlsl.s32 q7, d8, d3[1] :: Qd 0xd5555558 0x55555551 0xd5555558 0x55555551  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmlsl.s32 q10, d11, d15[1] :: Qd 0x55555555 0x55553ed5 0x55555555 0x55553ed5  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmlsl.s32 q10, d30, d1[0] :: Qd 0xd5555555 0x55555556 0xd5555555 0x55555556  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlsl.s16 q10, d30, d1[1] :: Qd 0xd5555556 0x55555555 0xd5555556 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlsl.s32 q10, d30, d1[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlsl.s16 q10, d30, d1[3] :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 08000000
+---- VQDMLAL ----
+vqdmlal.s32 q0, d1, d2 :: Qd 0x00000018 0x00001698 0x55555555 0x55556bd5  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmlal.s32 q6, d7, d8 :: Qd 0x55555555 0x5554d215 0x55555555 0x5554d215  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmlal.s16 q9, d11, d12 :: Qd 0x55555555 0x55582555 0x55555555 0x55582555  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x65569559 0x55555555 0x65569559  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlal.s32 q7, d8, d9 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x3a606621 0x55555555 0x3a606621  Qm (i32)0xffff9433  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlal.s32 q7, d8, d9 :: Qd 0x55555549 0x55555555 0x55555549 0x55555555  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5594d94d 0x55555555 0x5594d94d  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlal.s32 q7, d8, d9 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqdmlal.s32 q10, d11, d15 :: Qd 0x55555555 0x55556bd5 0x55555555 0x55556bd5  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmlal.s32 q10, d30, d31 :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlal.s16 q10, d30, d31 :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlal.s32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmlal.s16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VQDMLAL (by scalar) ----
+vqdmlal.s32 q0, d1, d7[0] :: Qd 0x00000018 0x00001698 0x55555555 0x55556bd5  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmlal.s32 q6, d7, d6[0] :: Qd 0x55555555 0x5554d215 0x55555555 0x5554d215  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmlal.s16 q9, d11, d7[2] :: Qd 0x55555555 0x55582555 0x55555555 0x55582555  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmlal.s16 q4, d5, d6[2] :: Qd 0x55555555 0x65569559 0x55555555 0x65569559  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlal.s32 q7, d8, d3[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqdmlal.s16 q4, d5, d6[1] :: Qd 0x55551551 0x3a606621 0x55551551 0x3a606621  Qm (i32)0xffff9433  Qn (i16)0x00002002  fpscr: 00000000
+vqdmlal.s32 q7, d8, d3[0] :: Qd 0x55555549 0x55555555 0x55555549 0x55555555  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmlal.s16 q4, d5, d6[2] :: Qd 0x59559555 0x5594d94d 0x59559555 0x5594d94d  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmlal.s32 q7, d8, d3[1] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqdmlal.s32 q10, d11, d15[1] :: Qd 0x55555555 0x55556bd5 0x55555555 0x55556bd5  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmlal.s32 q10, d30, d1[0] :: Qd 0x7fffffff 0xffffffff 0x7fffffff 0xffffffff  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlal.s16 q10, d30, d1[1] :: Qd 0x7fffffff 0x55555555 0x7fffffff 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmlal.s32 q10, d30, d1[1] :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmlal.s16 q10, d30, d1[3] :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VQDMULH ----
+vqdmulh.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmulh.s32 q6, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmulh.s16 q9, q11, q12 :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmulh.s16 q4, q5, q6 :: Qd 0x00001001 0x00001001 0x00001001 0x00001001  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmulh.s16 q4, q5, q6 :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b  Qm (i32)0xffff9433  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 q7, q8, q9 :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmulh.s16 q4, q5, q6 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmulh.s32 q10, q11, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmulh.s16 q10, q14, q15 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmulh.s32 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmulh.s16 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VQDMULH (by scalar) ----
+vqdmulh.s32 q0, q1, d6[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmulh.s32 q6, q7, d1[1] :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmulh.s16 q9, q11, d7[0] :: Qd 0x00000002 0x00000002 0x00000002 0x00000002  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmulh.s16 q4, q5, d6[0] :: Qd 0x00001001 0x00001001 0x00001001 0x00001001  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 q7, q8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmulh.s16 q4, q5, d6[1] :: Qd 0xffffe50b 0xffffe50b 0xffffe50b 0xffffe50b  Qm (i32)0xffff9433  Qn (i16)0x00002002  fpscr: 00000000
+vqdmulh.s32 q7, q8, d9[0] :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmulh.s16 q4, q5, d6[2] :: Qd 0x0400003f 0x0400003f 0x0400003f 0x0400003f  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 q7, q8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmulh.s32 q10, q11, d15[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmulh.s32 q10, q14, d15[1] :: Qd 0xffffff88 0xffffff88 0xffffff88 0xffffff88  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmulh.s16 q10, q14, d7[3] :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmulh.s32 q10, q14, d15[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmulh.s16 q10, q14, d7[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VSHL (immediate) ----
+vshl.i64 q0, q1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030  Qm (i32)0x00000018
+vshl.i64 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x40000000
+vshl.i64 q9, q12, #2 :: Qd 0x0000000a 0x00000008 0x0000000a 0x00000008  Qm (i32)0x80000002
+vshl.i64 q11, q2, #12 :: Qd 0xffffffff 0xfffff000 0xffffffff 0xfffff000  Qm (i32)0xffffffff
+vshl.i64 q15, q12, #63 :: Qd 0x80000000 0x00000000 0x80000000 0x00000000  Qm (i32)0x00000005
+vshl.i64 q5, q12, #62 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x80000001
+vshl.i32 q0, q1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030  Qm (i32)0x00000018
+vshl.i32 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x40000000
+vshl.i32 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x80000002
+vshl.i32 q11, q2, #12 :: Qd 0xfffff000 0xfffff000 0xfffff000 0xfffff000  Qm (i32)0xffffffff
+vshl.i32 q15, q12, #20 :: Qd 0x00500000 0x00500000 0x00500000 0x00500000  Qm (i32)0x00000005
+vshl.i32 q5, q12, #30 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x80000001
+vshl.i16 q0, q1, #1 :: Qd 0x00300030 0x00300030 0x00300030 0x00300030  Qm (i16)0x00000018
+vshl.i16 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x40000000
+vshl.i16 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x80000002
+vshl.i16 q11, q2, #12 :: Qd 0xf000f000 0xf000f000 0xf000f000 0xf000f000  Qm (i16)0xffffffff
+vshl.i16 q15, q12, #3 :: Qd 0x00280028 0x00280028 0x00280028 0x00280028  Qm (i16)0x00000005
+vshl.i16 q5, q12, #14 :: Qd 0x00004000 0x00004000 0x00004000 0x00004000  Qm (i32)0x80000001
+vshl.i8 q0, q1, #1 :: Qd 0x30303030 0x30303030 0x30303030 0x30303030  Qm (i8)0x00000018
+vshl.i8 q5, q2, #1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x40000000
+vshl.i8 q9, q12, #2 :: Qd 0x00000008 0x00000008 0x00000008 0x00000008  Qm (i32)0x80000002
+vshl.i8 q11, q2, #7 :: Qd 0x80808080 0x80808080 0x80808080 0x80808080  Qm (i8)0xffffffff
+vshl.i8 q15, q12, #3 :: Qd 0x28282828 0x28282828 0x28282828 0x28282828  Qm (i8)0x00000005
+vshl.i8 q5, q12, #6 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040  Qm (i32)0x80000001
+---- VNEG ----
+vneg.s32 q0, q1 :: Qd 0xffffff8d 0xffffff8d 0xffffff8d 0xffffff8d  Qm (i32)0x00000073
+vneg.s16 q15, q4 :: Qd 0x0000ff8d 0x0000ff8d 0x0000ff8d 0x0000ff8d  Qm (i32)0x00000073
+vneg.s8 q8, q7 :: Qd 0x0000008d 0x0000008d 0x0000008d 0x0000008d  Qm (i32)0x00000073
+vneg.s32 q0, q1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02  Qm (i32)0x000000fe
+vneg.s16 q15, q4 :: Qd 0x0000ff11 0x0000ff11 0x0000ff11 0x0000ff11  Qm (i32)0x000000ef
+vneg.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022  Qm (i32)0x000000de
+vneg.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6  Qm (i16)0x0000fe0a
+vneg.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5  Qm (i16)0x0000ef0b
+vneg.s8 q8, q7 :: Qd 0x22f422f4 0x22f422f4 0x22f422f4 0x22f422f4  Qm (i16)0x0000de0c
+---- VQNEG ----
+vqneg.s32 q0, q1 :: Qd 0xffffff8d 0xffffff8d 0xffffff8d 0xffffff8d  Qm (i32)0x00000073  fpscr: 00000000
+vqneg.s32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  fpscr: 08000000
+vqneg.s16 q0, q1 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  fpscr: 08000000
+vqneg.s8 q0, q1 :: Qd 0x7f000000 0x7f000000 0x7f000000 0x7f000000  Qm (i32)0x80000000  fpscr: 08000000
+vqneg.s16 q15, q4 :: Qd 0x0000ff8d 0x0000ff8d 0x0000ff8d 0x0000ff8d  Qm (i32)0x00000073  fpscr: 00000000
+vqneg.s8 q8, q7 :: Qd 0x0000008d 0x0000008d 0x0000008d 0x0000008d  Qm (i32)0x00000073  fpscr: 00000000
+vqneg.s32 q0, q1 :: Qd 0xffffff02 0xffffff02 0xffffff02 0xffffff02  Qm (i32)0x000000fe  fpscr: 00000000
+vqneg.s16 q15, q4 :: Qd 0x0000ff11 0x0000ff11 0x0000ff11 0x0000ff11  Qm (i32)0x000000ef  fpscr: 00000000
+vqneg.s8 q8, q7 :: Qd 0x00000022 0x00000022 0x00000022 0x00000022  Qm (i32)0x000000de  fpscr: 00000000
+vqneg.s32 q0, q1 :: Qd 0x01f501f6 0x01f501f6 0x01f501f6 0x01f501f6  Qm (i16)0x0000fe0a  fpscr: 00000000
+vqneg.s16 q15, q4 :: Qd 0x10f510f5 0x10f510f5 0x10f510f5 0x10f510f5  Qm (i16)0x0000ef0b  fpscr: 00000000
+vqneg.s8 q8, q7 :: Qd 0x22f422f4 0x22f422f4 0x22f422f4 0x22f422f4  Qm (i16)0x0000de0c  fpscr: 00000000
+---- VREV ----
+vrev64.8 q0, q1 :: Qd 0xddccbbaa 0xddccbbaa 0xddccbbaa 0xddccbbaa  Qm (i32)0xaabbccdd
+vrev64.16 q10, q15 :: Qd 0xccddaabb 0xccddaabb 0xccddaabb 0xccddaabb  Qm (i32)0xaabbccdd
+vrev64.32 q1, q14 :: Qd 0xaabbccdd 0xaabbccdd 0xaabbccdd 0xaabbccdd  Qm (i32)0xaabbccdd
+vrev32.8 q0, q1 :: Qd 0xddccbbaa 0xddccbbaa 0xddccbbaa 0xddccbbaa  Qm (i32)0xaabbccdd
+vrev32.16 q10, q15 :: Qd 0xccddaabb 0xccddaabb 0xccddaabb 0xccddaabb  Qm (i32)0xaabbccdd
+vrev16.8 q0, q1 :: Qd 0xbbaaddcc 0xbbaaddcc 0xbbaaddcc 0xbbaaddcc  Qm (i32)0xaabbccdd
+---- VSHLL ----
+vshll.s32 q0, d1, #1 :: Qd 0x00000000 0x00000030 0x00000000 0x00000030  Qm (i32)0x00000018
+vshll.s32 q5, d2, #1 :: Qd 0x00000000 0x80000000 0x00000000 0x80000000  Qm (i32)0x40000000
+vshll.s32 q9, d12, #2 :: Qd 0xfffffffe 0x00000008 0xfffffffe 0x00000008  Qm (i32)0x80000002
+vshll.u32 q11, d2, #12 :: Qd 0x00000fff 0xfffff000 0x00000fff 0xfffff000  Qm (i32)0xffffffff
+vshll.u32 q15, d12, #20 :: Qd 0x00000000 0x00500000 0x00000000 0x00500000  Qm (i32)0x00000005
+vshll.u32 q5, d22, #30 :: Qd 0x20000000 0x40000000 0x20000000 0x40000000  Qm (i32)0x80000001
+vshll.s16 q0, d1, #1 :: Qd 0x00000030 0x00000030 0x00000030 0x00000030  Qm (i16)0x00000018
+vshll.s16 q5, d2, #1 :: Qd 0x00008000 0x00000000 0x00008000 0x00000000  Qm (i32)0x40000000
+vshll.s16 q9, d12, #2 :: Qd 0xfffe0000 0x00000008 0xfffe0000 0x00000008  Qm (i32)0x80000002
+vshll.u16 q11, d2, #12 :: Qd 0x0ffff000 0x0ffff000 0x0ffff000 0x0ffff000  Qm (i16)0xffffffff
+vshll.u16 q15, d22, #3 :: Qd 0x00000028 0x00000028 0x00000028 0x00000028  Qm (i16)0x00000005
+vshll.u16 q5, d12, #14 :: Qd 0x20000000 0x00004000 0x20000000 0x00004000  Qm (i32)0x80000001
+vshll.s8 q0, d1, #1 :: Qd 0x00300030 0x00300030 0x00300030 0x00300030  Qm (i8)0x00000018
+vshll.s8 q5, d2, #1 :: Qd 0x00800000 0x00000000 0x00800000 0x00000000  Qm (i32)0x40000000
+vshll.s8 q9, d12, #2 :: Qd 0xfe000000 0x00000008 0xfe000000 0x00000008  Qm (i32)0x80000002
+vshll.u8 q11, d2, #7 :: Qd 0x7f807f80 0x7f807f80 0x7f807f80 0x7f807f80  Qm (i8)0xffffffff
+vshll.u8 q15, d19, #3 :: Qd 0x00280028 0x00280028 0x00280028 0x00280028  Qm (i8)0x00000005
+vshll.u8 q5, d12, #6 :: Qd 0x20000000 0x00000040 0x20000000 0x00000040  Qm (i32)0x80000001
+---- VSHLL (max shift) ----
+vshll.i32 q0, d1, #32 :: Qd 0x00000018 0x00000000 0x00000018 0x00000000  Qm (i32)0x00000018
+vshll.i32 q5, d2, #32 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x40000000
+vshll.i32 q11, d2, #32 :: Qd 0xffffffff 0x00000000 0xffffffff 0x00000000  Qm (i32)0xffffffff
+vshll.i32 q15, d12, #32 :: Qd 0x00000005 0x00000000 0x00000005 0x00000000  Qm (i32)0x00000005
+vshll.i16 q0, d1, #16 :: Qd 0x00180000 0x00180000 0x00180000 0x00180000  Qm (i16)0x00000018
+vshll.i16 q5, d2, #16 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x40000000
+vshll.i16 q11, d2, #16 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000  Qm (i16)0xffffffff
+vshll.i16 q15, d22, #16 :: Qd 0x00050000 0x00050000 0x00050000 0x00050000  Qm (i16)0x00000005
+vshll.i8 q0, d1, #8 :: Qd 0x18001800 0x18001800 0x18001800 0x18001800  Qm (i8)0x00000018
+vshll.i8 q5, d2, #8 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x40000000
+vshll.i8 q11, d2, #8 :: Qd 0xff00ff00 0xff00ff00 0xff00ff00 0xff00ff00  Qm (i8)0xffffffff
+vshll.i8 q15, d19, #8 :: Qd 0x05000500 0x05000500 0x05000500 0x05000500  Qm (i8)0x00000005
+---- VMULL ----
+vmull.s8 q0, d1, d12 :: Qd 0x0000fe0c 0x01980d94 0x0000fe0c 0x01980d94  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmull.s8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmull.s8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmull.s8 q4, d5, d6 :: Qd 0x00000000 0xee48ed46 0x00000000 0xee48ed46  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmull.s8 q4, d5, d6 :: Qd 0x00000000 0x0000ffa6 0x00000000 0x0000ffa6  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmull.s8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmull.s8 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmull.u8 q0, d1, d12 :: Qd 0x0000080c 0xb7989294 0x0000080c 0xb7989294  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmull.u8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x18482046 0x00000000 0x18482046  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmull.u8 q4, d5, d6 :: Qd 0x00000000 0x00002ca6 0x00000000 0x00002ca6  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmull.u8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmull.u8 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmull.s16 q0, d1, d12 :: Qd 0x0000080c 0x01649694 0x0000080c 0x01649694  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmull.s16 q9, d11, d12 :: Qd 0x00000000 0x00016800 0x00000000 0x00016800  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmull.s16 q4, d5, d6 :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmull.s16 q4, d5, d6 :: Qd 0x00000000 0xee0c2646 0x00000000 0xee0c2646  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmull.s16 q4, d5, d6 :: Qd 0x0002b000 0xffdc74a6 0x0002b000 0xffdc74a6  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmull.s16 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmull.s16 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmull.u16 q0, d1, d12 :: Qd 0x0000080c 0xb8e99694 0x0000080c 0xb8e99694  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmull.u16 q9, d11, d12 :: Qd 0x00000000 0x00016800 0x00000000 0x00016800  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmull.u16 q4, d5, d6 :: Qd 0x00000000 0x0800a002 0x00000000 0x0800a002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmull.u16 q4, d5, d6 :: Qd 0x00000000 0x18ae2646 0x00000000 0x18ae2646  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmull.u16 q4, d5, d6 :: Qd 0x0002b000 0x00da74a6 0x0002b000 0x00da74a6  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmull.u16 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmull.u16 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmull.s32 q0, d1, d2 :: Qd 0x000121f2 0xd7d30fa8 0x000121f2 0xd7d30fa8  Qm (i32)0x0aabbcc4  Qn (i32)0x001b2c0a
+vmull.s32 q6, d7, d8 :: Qd 0xffffffff 0xffffbe60 0xffffffff 0xffffbe60  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmull.s32 q7, d8, d9 :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmull.s32 q7, d8, d9 :: Qd 0xfffffffa 0x00000000 0xfffffffa 0x00000000  Qm (i32)0x80000000  Qn (i32)0x0000000c
+vmull.s32 q7, d8, d9 :: Qd 0x3ffffffe 0x80000002 0x3ffffffe 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmull.s32 q10, d11, d15 :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmull.s32 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmull.s32 q10, d30, d31 :: Qd 0xe0000000 0x00000000 0xe0000000 0x00000000  Qm (i32)0x40000000  Qn (i32)0x80000000
+vmull.u32 q0, d1, d2 :: Qd 0x000121f2 0xd7d30fa8 0x000121f2 0xd7d30fa8  Qm (i32)0x0aabbcc4  Qn (i32)0x001b2c0a
+vmull.u32 q6, d7, d8 :: Qd 0x0000008b 0xffffbe60 0x0000008b 0xffffbe60  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmull.u32 q7, d8, d9 :: Qd 0x40000001 0x80000002 0x40000001 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmull.u32 q7, d8, d9 :: Qd 0x00000006 0x00000000 0x00000006 0x00000000  Qm (i32)0x80000000  Qn (i32)0x0000000c
+vmull.u32 q7, d8, d9 :: Qd 0x40000001 0x80000002 0x40000001 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmull.u32 q10, d11, d15 :: Qd 0x00000000 0x00000b40 0x00000000 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmull.u32 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmull.u32 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000  Qm (i32)0x40000000  Qn (i32)0x80000000
+vmull.p8 q9, d11, d12 :: Qd 0x00000a3a 0x3eb60440 0x00000a3a 0x3eb60440  Qm (i32)0x001a4b0c  Qn (i32)0x00d1e2f0
+vmull.p8 q4, d5, d6 :: Qd 0x00000000 0x08000002 0x00000000 0x08000002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmull.p8 q4, d15, d26 :: Qd 0x00000000 0x17081f86 0x00000000 0x17081f86  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmull.p8 q14, d5, d6 :: Qd 0x00000000 0x04281b36 0x00000000 0x04281b36  Qm (i32)0x10000efe  Qn (i32)0x002bdc2d
+vmull.p8 q10, d30, d31 :: Qd 0x40000000 0x00000000 0x40000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmull.p8 q10, d27, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmull.p8 q9, d11, d12 :: Qd 0x00000000 0x00010800 0x00000000 0x00010800  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmull.p8 q4, d5, d6 :: Qd 0x00000000 0x00001b36 0x00000000 0x00001b36  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmull.p8 q10, d30, d31 :: Qd 0x20000000 0x00000000 0x20000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x40000000
+---- VMLAL ----
+vmlal.s8 q0, d1, d12 :: Qd 0x000abae0 0x01a2ca68 0x55555361 0x56ed62e9  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmlal.s8 q9, d11, d12 :: Qd 0x55555555 0x55565d55 0x55555555 0x55565d55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x5d555557 0x55555555 0x5d555557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x439d429b 0x55555555 0x439d429b  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmlal.s8 q4, d5, d6 :: Qd 0x55555555 0x555554fb 0x55555555 0x555554fb  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmlal.s8 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlal.s8 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmlal.u8 q0, d1, d12 :: Qd 0x000ac4e0 0xb7a24f68 0x55555d61 0x0cede7e9  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmlal.u8 q9, d11, d12 :: Qd 0x55555555 0x55565d55 0x55555555 0x55565d55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x5d555557 0x55555555 0x5d555557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x6d9d759b 0x55555555 0x6d9d759b  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmlal.u8 q4, d5, d6 :: Qd 0x55555555 0x555581fb 0x55555555 0x555581fb  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmlal.u8 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlal.u8 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmlal.s16 q0, d1, d12 :: Qd 0x000ac4e0 0x016f5368 0x55555d61 0x56b9ebe9  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmlal.s16 q9, d11, d12 :: Qd 0x55555555 0x5556bd55 0x55555555 0x5556bd55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlal.s16 q4, d5, d6 :: Qd 0x55555555 0x43617b9b 0x55555555 0x43617b9b  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmlal.s16 q4, d5, d6 :: Qd 0x55580555 0x5531c9fb 0x55580555 0x5531c9fb  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmlal.s16 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlal.s16 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmlal.u16 q0, d1, d12 :: Qd 0x000ac4e0 0xb8f45368 0x55555d61 0x0e3eebe9  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmlal.u16 q9, d11, d12 :: Qd 0x55555555 0x5556bd55 0x55555555 0x5556bd55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlal.u16 q4, d5, d6 :: Qd 0x55555555 0x5d55f557 0x55555555 0x5d55f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlal.u16 q4, d5, d6 :: Qd 0x55555555 0x6e037b9b 0x55555555 0x6e037b9b  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmlal.u16 q4, d5, d6 :: Qd 0x55580555 0x562fc9fb 0x55580555 0x562fc9fb  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmlal.u16 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlal.u16 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmlal.s32 q0, d1, d2 :: Qd 0x0aacdeb6 0xe27ecc6c 0x55567748 0x2d2864fd  Qm (i32)0x0aabbcc4  Qn (i32)0x001b2c0a
+vmlal.s32 q6, d7, d8 :: Qd 0x55555555 0x555513b5 0x55555555 0x555513b5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmlal.s32 q7, d8, d9 :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlal.s32 q7, d8, d9 :: Qd 0x5555554f 0x55555555 0x5555554f 0x55555555  Qm (i32)0x80000000  Qn (i32)0x0000000c
+vmlal.s32 q7, d8, d9 :: Qd 0x95555553 0xd5555557 0x95555553 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlal.s32 q10, d11, d15 :: Qd 0x55555555 0x55556095 0x55555555 0x55556095  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmlal.s32 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlal.s32 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555  Qm (i32)0x40000000  Qn (i32)0x80000000
+vmlal.u32 q0, d1, d2 :: Qd 0x0aacdeb6 0xe27ecc6c 0x55567748 0x2d2864fd  Qm (i32)0x0aabbcc4  Qn (i32)0x001b2c0a
+vmlal.u32 q6, d7, d8 :: Qd 0x555555e1 0x555513b5 0x555555e1 0x555513b5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmlal.u32 q7, d8, d9 :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlal.u32 q7, d8, d9 :: Qd 0x5555555b 0x55555555 0x5555555b 0x55555555  Qm (i32)0x80000000  Qn (i32)0x0000000c
+vmlal.u32 q7, d8, d9 :: Qd 0x95555556 0xd5555557 0x95555556 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlal.u32 q10, d11, d15 :: Qd 0x55555555 0x55556095 0x55555555 0x55556095  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmlal.u32 q10, d30, d31 :: Qd 0x95555555 0x55555555 0x95555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlal.u32 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555  Qm (i32)0x40000000  Qn (i32)0x80000000
+---- VMLSL ----
+vmlsl.s8 q0, d1, d12 :: Qd 0x000abec8 0xfe72af40 0x55555749 0x53bd47c1  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmlsl.s8 q9, d11, d12 :: Qd 0x55555555 0x55544d55 0x55555555 0x55544d55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x4d555553 0x55555555 0x4d555553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x670d680f 0x55555555 0x670d680f  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmlsl.s8 q4, d5, d6 :: Qd 0x55555555 0x555555af 0x55555555 0x555555af  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmlsl.s8 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlsl.s8 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmlsl.u8 q0, d1, d12 :: Qd 0x000ab4c8 0x48722a40 0x55554d49 0x9dbdc2c1  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmlsl.u8 q9, d11, d12 :: Qd 0x55555555 0x55544d55 0x55555555 0x55544d55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x4d555553 0x55555555 0x4d555553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x3d0d350f 0x55555555 0x3d0d350f  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmlsl.u8 q4, d5, d6 :: Qd 0x55555555 0x555528af 0x55555555 0x555528af  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmlsl.u8 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlsl.u8 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmlsl.s16 q0, d1, d12 :: Qd 0x000ab4c8 0xfea62640 0x55554d49 0x53f0bec1  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmlsl.s16 q9, d11, d12 :: Qd 0x55555555 0x5553ed55 0x55555555 0x5553ed55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlsl.s16 q4, d5, d6 :: Qd 0x55555555 0x67492f0f 0x55555555 0x67492f0f  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmlsl.s16 q4, d5, d6 :: Qd 0x5552a555 0x5578e0af 0x5552a555 0x5578e0af  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmlsl.s16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlsl.s16 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmlsl.u16 q0, d1, d12 :: Qd 0x000ab4c8 0x47212640 0x55554d49 0x9c6bbec1  Qm (i32)0x000abcd4  Qn (i32)0x00cefab1
+vmlsl.u16 q9, d11, d12 :: Qd 0x55555555 0x5553ed55 0x55555555 0x5553ed55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmlsl.u16 q4, d5, d6 :: Qd 0x55555555 0x4d54b553 0x55555555 0x4d54b553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmlsl.u16 q4, d5, d6 :: Qd 0x55555555 0x3ca72f0f 0x55555555 0x3ca72f0f  Qm (i32)0xffff9433  Qn (i32)0x00002aa2
+vmlsl.u16 q4, d5, d6 :: Qd 0x5552a555 0x547ae0af 0x5552a555 0x547ae0af  Qm (i32)0x100000fe  Qn (i32)0x002bdc2d
+vmlsl.u16 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlsl.u16 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x40000000
+vmlsl.s32 q0, d1, d2 :: Qd 0x0aaa9ad1 0x32d8ad1c 0x55543362 0x7d8245ad  Qm (i32)0x0aabbcc4  Qn (i32)0x001b2c0a
+vmlsl.s32 q6, d7, d8 :: Qd 0x55555555 0x555596f5 0x55555555 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmlsl.s32 q7, d8, d9 :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlsl.s32 q7, d8, d9 :: Qd 0x5555555b 0x55555555 0x5555555b 0x55555555  Qm (i32)0x80000000  Qn (i32)0x0000000c
+vmlsl.s32 q7, d8, d9 :: Qd 0x15555556 0xd5555553 0x15555556 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlsl.s32 q10, d11, d15 :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmlsl.s32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlsl.s32 q10, d30, d31 :: Qd 0x75555555 0x55555555 0x75555555 0x55555555  Qm (i32)0x40000000  Qn (i32)0x80000000
+vmlsl.u32 q0, d1, d2 :: Qd 0x0aaa9ad1 0x32d8ad1c 0x55543362 0x7d8245ad  Qm (i32)0x0aabbcc4  Qn (i32)0x001b2c0a
+vmlsl.u32 q6, d7, d8 :: Qd 0x555554c9 0x555596f5 0x555554c9 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmlsl.u32 q7, d8, d9 :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlsl.u32 q7, d8, d9 :: Qd 0x5555554f 0x55555555 0x5555554f 0x55555555  Qm (i32)0x80000000  Qn (i32)0x0000000c
+vmlsl.u32 q7, d8, d9 :: Qd 0x15555553 0xd5555553 0x15555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmlsl.u32 q10, d11, d15 :: Qd 0x55555555 0x55554a15 0x55555555 0x55554a15  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmlsl.u32 q10, d30, d31 :: Qd 0x15555555 0x55555555 0x15555555 0x55555555  Qm (i32)0x80000000  Qn (i32)0x80000000
+vmlsl.u32 q10, d30, d31 :: Qd 0x35555555 0x55555555 0x35555555 0x55555555  Qm (i32)0x40000000  Qn (i32)0x80000000
+---- VQRDMULH ----
+vqrdmulh.s32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqrdmulh.s32 q6, q7, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqrdmulh.s16 q9, q11, q12 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqrdmulh.s16 q4, q5, q6 :: Qd 0x00001001 0x00001001 0x00001001 0x00001001  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqrdmulh.s16 q4, q5, q6 :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b  Qm (i32)0xffff9433  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 q7, q8, q9 :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqrdmulh.s16 q4, q5, q6 :: Qd 0x00000040 0x00000040 0x00000040 0x00000040  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 q7, q8, q9 :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqrdmulh.s32 q10, q11, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqrdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqrdmulh.s32 q10, q14, q15 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  Qn (i32)0x80000001  fpscr: 00000000
+vqrdmulh.s16 q10, q14, q15 :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqrdmulh.s32 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqrdmulh.s16 q10, q14, q15 :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VQRDMULH (by scalar) ----
+vqrdmulh.s32 q0, q1, d6[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqrdmulh.s32 q6, q7, d1[1] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqrdmulh.s16 q9, q11, d7[0] :: Qd 0x00000003 0x00000003 0x00000003 0x00000003  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqrdmulh.s16 q4, q5, d6[0] :: Qd 0x00001001 0x00001001 0x00001001 0x00001001  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 q7, q8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqrdmulh.s16 q4, q5, d6[1] :: Qd 0x0000e50b 0x0000e50b 0x0000e50b 0x0000e50b  Qm (i32)0xffff9433  Qn (i16)0x00002002  fpscr: 00000000
+vqrdmulh.s32 q7, q8, d9[0] :: Qd 0xfffffff4 0xfffffff4 0xfffffff4 0xfffffff4  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqrdmulh.s16 q4, q5, d6[2] :: Qd 0x04000040 0x04000040 0x04000040 0x04000040  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 q7, q8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqrdmulh.s32 q10, q11, d15[0] :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqrdmulh.s32 q10, q14, d15[1] :: Qd 0xffffff88 0xffffff88 0xffffff88 0xffffff88  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 00000000
+vqrdmulh.s16 q10, q14, d7[3] :: Qd 0x7fff0000 0x7fff0000 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  Qn (i32)0x80000001  fpscr: 08000000
+vqrdmulh.s32 q10, q14, d15[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqrdmulh.s16 q10, q14, d7[1] :: Qd 0xc0000000 0xc0000000 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VADD (fp) ----
+vadd.f32 q0, q5, q2 :: Qd 0xc1b43ac6 0xc1b43ac6 0xc1b43ac6 0xc1b43ac6  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vadd.f32 q3, q4, q5 :: Qd 0xc8a931cf 0xc8a931cf 0xc8a931cf 0xc8a931cf  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vadd.f32 q10, q11, q2 :: Qd 0x45398860 0x45398860 0x45398860 0x45398860  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vadd.f32 q9, q5, q7 :: Qd 0x47dc9261 0x47dc9261 0x47dc9261 0x47dc9261  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vadd.f32 q0, q5, q2 :: Qd 0xc88faac0 0xc88faac0 0xc88faac0 0xc88faac0  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vadd.f32 q3, q4, q5 :: Qd 0x44ab4000 0x44ab4000 0x44ab4000 0x44ab4000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vadd.f32 q10, q11, q2 :: Qd 0x4742b400 0x4742b400 0x4742b400 0x4742b400  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vadd.f32 q9, q5, q7 :: Qd 0x49d5e6b8 0x49d5e6b8 0x49d5e6b8 0x49d5e6b8  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vadd.f32 q0, q11, q12 :: Qd 0x48b0b752 0x48b0b752 0x48b0b752 0x48b0b752  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vadd.f32 q7, q1, q6 :: Qd 0x420802fd 0x420802fd 0x420802fd 0x420802fd  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vadd.f32 q0, q1, q2 :: Qd 0x4532d000 0x4532d000 0x4532d000 0x4532d000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vadd.f32 q3, q4, q5 :: Qd 0x450d299a 0x450d299a 0x450d299a 0x450d299a  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vadd.f32 q10, q11, q2 :: Qd 0x44152592 0x44152592 0x44152592 0x44152592  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vadd.f32 q9, q5, q7 :: Qd 0x4573a000 0x4573a000 0x4573a000 0x4573a000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vadd.f32 q0, q11, q12 :: Qd 0xc5b695c3 0xc5b695c3 0xc5b695c3 0xc5b695c3  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vadd.f32 q7, q1, q6 :: Qd 0x43e07a2a 0x43e07a2a 0x43e07a2a 0x43e07a2a  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vadd.f32 q0, q5, q2 :: Qd 0x44053ee0 0x44053ee0 0x44053ee0 0x44053ee0  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vadd.f32 q10, q13, q15 :: Qd 0xc4838fb4 0xc4838fb4 0xc4838fb4 0xc4838fb4  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vadd.f32 q10, q13, q15 :: Qd 0x488c3d8e 0x488c3d8e 0x488c3d8e 0x488c3d8e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vadd.f32 q0, q1, q2 :: Qd 0x4efa8dc5 0x4efa8dc5 0x4efa8dc5 0x4efa8dc5  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vadd.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vadd.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vadd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vadd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vadd.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VSUB (fp) ----
+vsub.f32 q0, q5, q2 :: Qd 0x428937a8 0x428937a8 0x428937a8 0x428937a8  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vsub.f32 q3, q4, q5 :: Qd 0xc8aa824f 0xc8aa824f 0xc8aa824f 0xc8aa824f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vsub.f32 q10, q11, q2 :: Qd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vsub.f32 q9, q5, q7 :: Qd 0x4799e961 0x4799e961 0x4799e961 0x4799e961  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vsub.f32 q0, q5, q2 :: Qd 0x484623e2 0x484623e2 0x484623e2 0x484623e2  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vsub.f32 q3, q4, q5 :: Qd 0xc4a52385 0xc4a52385 0xc4a52385 0xc4a52385  Qm (i32)0x41c71eb8  Qn (i32)0x44a84000
+vsub.f32 q10, q11, q2 :: Qd 0x473a3200 0x473a3200 0x473a3200 0x473a3200  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vsub.f32 q9, q5, q7 :: Qd 0xc9d5d958 0xc9d5d958 0xc9d5d958 0xc9d5d958  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vsub.f32 q0, q11, q12 :: Qd 0x48aafc92 0x48aafc92 0x48aafc92 0x48aafc92  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vsub.f32 q7, q1, q6 :: Qd 0x4207fdf5 0x4207fdf5 0x4207fdf5 0x4207fdf5  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vsub.f32 q0, q1, q2 :: Qd 0x45257000 0x45257000 0x45257000 0x45257000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vsub.f32 q3, q4, q5 :: Qd 0xc3ff4ccc 0xc3ff4ccc 0xc3ff4ccc 0xc3ff4ccc  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vsub.f32 q10, q11, q2 :: Qd 0x43bd4b23 0x43bd4b23 0x43bd4b23 0x43bd4b23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vsub.f32 q9, q5, q7 :: Qd 0x43c50000 0x43c50000 0x43c50000 0x43c50000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vsub.f32 q0, q11, q12 :: Qd 0x45b311c3 0x45b311c3 0x45b311c3 0x45b311c3  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vsub.f32 q7, q1, q6 :: Qd 0x43e7c592 0x43e7c592 0x43e7c592 0x43e7c592  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vsub.f32 q0, q5, q2 :: Qd 0x44053f76 0x44053f76 0x44053f76 0x44053f76  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vsub.f32 q10, q13, q15 :: Qd 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vsub.f32 q10, q13, q15 :: Qd 0x4883b08e 0x4883b08e 0x4883b08e 0x4883b08e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vsub.f32 q0, q1, q2 :: Qd 0xcda5da84 0xcda5da84 0xcda5da84 0xcda5da84  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vsub.f32 q0, q1, q2 :: Qd 0xbf800000 0xbf800000 0xbf800000 0xbf800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vsub.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vsub.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vsub.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vsub.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VABD (fp) ----
+vabd.f32 q0, q5, q2 :: Qd 0x428937a8 0x428937a8 0x428937a8 0x428937a8  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vabd.f32 q3, q4, q5 :: Qd 0x48aa824f 0x48aa824f 0x48aa824f 0x48aa824f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vabd.f32 q10, q11, q2 :: Qd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd 0x47b8a6bd  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vabd.f32 q9, q5, q7 :: Qd 0x4799e961 0x4799e961 0x4799e961 0x4799e961  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vabd.f32 q0, q5, q2 :: Qd 0x484623e2 0x484623e2 0x484623e2 0x484623e2  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vabd.f32 q3, q4, q5 :: Qd 0x44a54000 0x44a54000 0x44a54000 0x44a54000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vabd.f32 q10, q11, q2 :: Qd 0x473a3200 0x473a3200 0x473a3200 0x473a3200  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vabd.f32 q9, q5, q7 :: Qd 0x49d5d958 0x49d5d958 0x49d5d958 0x49d5d958  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vabd.f32 q0, q11, q12 :: Qd 0x48aafc92 0x48aafc92 0x48aafc92 0x48aafc92  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vabd.f32 q7, q1, q6 :: Qd 0x4207fdf5 0x4207fdf5 0x4207fdf5 0x4207fdf5  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vabd.f32 q0, q1, q2 :: Qd 0x45257000 0x45257000 0x45257000 0x45257000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vabd.f32 q3, q4, q5 :: Qd 0x43ff4ccc 0x43ff4ccc 0x43ff4ccc 0x43ff4ccc  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vabd.f32 q10, q11, q2 :: Qd 0x43bd4b23 0x43bd4b23 0x43bd4b23 0x43bd4b23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vabd.f32 q9, q5, q7 :: Qd 0x43c50000 0x43c50000 0x43c50000 0x43c50000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vabd.f32 q0, q11, q12 :: Qd 0x45b311c3 0x45b311c3 0x45b311c3 0x45b311c3  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vabd.f32 q7, q1, q6 :: Qd 0x43e7c592 0x43e7c592 0x43e7c592 0x43e7c592  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vabd.f32 q0, q5, q2 :: Qd 0x44053f76 0x44053f76 0x44053f76 0x44053f76  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vabd.f32 q10, q13, q15 :: Qd 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4 0x42a3ffa4  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vabd.f32 q10, q13, q15 :: Qd 0x4883b08e 0x4883b08e 0x4883b08e 0x4883b08e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vabd.f32 q0, q1, q2 :: Qd 0x4da5da84 0x4da5da84 0x4da5da84 0x4da5da84  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vabd.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vabd.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vabd.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vabd.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMUL (fp) ----
+vmul.f32 q0, q5, q2 :: Qd 0xc4833ce4 0xc4833ce4 0xc4833ce4 0xc4833ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmul.f32 q3, q4, q5 :: Qd 0xcddf4321 0xcddf4321 0xcddf4321 0xcddf4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmul.f32 q10, q11, q2 :: Qd 0xcf050e7f 0xcf050e7f 0xcf050e7f 0xcf050e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmul.f32 q9, q5, q7 :: Qd 0x4ec3063f 0x4ec3063f 0x4ec3063f 0x4ec3063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmul.f32 q0, q5, q2 :: Qd 0x5029254c 0x5029254c 0x5029254c 0x5029254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmul.f32 q3, q4, q5 :: Qd 0x46fc6000 0x46fc6000 0x46fc6000 0x46fc6000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vmul.f32 q10, q11, q2 :: Qd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vmul.f32 q9, q5, q7 :: Qd 0x4db2c947 0x4db2c947 0x4db2c947 0x4db2c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmul.f32 q0, q11, q12 :: Qd 0x4ef90536 0x4ef90536 0x4ef90536 0x4ef90536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmul.f32 q7, q1, q6 :: Qd 0x3dab1f7a 0x3dab1f7a 0x3dab1f7a 0x3dab1f7a  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmul.f32 q0, q1, q2 :: Qd 0x488fe2c0 0x488fe2c0 0x488fe2c0 0x488fe2c0  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmul.f32 q3, q4, q5 :: Qd 0x4993b8e3 0x4993b8e3 0x4993b8e3 0x4993b8e3  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmul.f32 q10, q11, q2 :: Qd 0x474f9afc 0x474f9afc 0x474f9afc 0x474f9afc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmul.f32 q9, q5, q7 :: Qd 0x4a657ac0 0x4a657ac0 0x4a657ac0 0x4a657ac0  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmul.f32 q0, q11, q12 :: Qd 0x489eee1e 0x489eee1e 0x489eee1e 0x489eee1e  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmul.f32 q7, q1, q6 :: Qd 0xc5500239 0xc5500239 0xc5500239 0xc5500239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmul.f32 q0, q5, q2 :: Qd 0xc01c7d07 0xc01c7d07 0xc01c7d07 0xc01c7d07  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmul.f32 q10, q13, q15 :: Qd 0x488666a6 0x488666a6 0x488666a6 0x488666a6  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmul.f32 q10, q13, q15 :: Qd 0x4f115379 0x4f115379 0x4f115379 0x4f115379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmul.f32 q0, q1, q2 :: Qd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmul.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmul.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmul.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmul.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmul.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMLA (fp) ----
+vmla.f32 q0, q5, q2 :: Qd 0xc4831ce4 0xc4831ce4 0xc4831ce4 0xc4831ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmla.f32 q3, q4, q5 :: Qd 0xcddf4321 0xcddf4321 0xcddf4321 0xcddf4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmla.f32 q10, q11, q2 :: Qd 0xcf050e7f 0xcf050e7f 0xcf050e7f 0xcf050e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmla.f32 q9, q5, q7 :: Qd 0x4ec3063f 0x4ec3063f 0x4ec3063f 0x4ec3063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmla.f32 q0, q5, q2 :: Qd 0x5029254c 0x5029254c 0x5029254c 0x5029254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmla.f32 q3, q4, q5 :: Qd 0x46fc6200 0x46fc6200 0x46fc6200 0x46fc6200  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vmla.f32 q10, q11, q2 :: Qd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd 0x4c4a89cd  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vmla.f32 q9, q5, q7 :: Qd 0x4db2c947 0x4db2c947 0x4db2c947 0x4db2c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmla.f32 q0, q11, q12 :: Qd 0x4ef90536 0x4ef90536 0x4ef90536 0x4ef90536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmla.f32 q7, q1, q6 :: Qd 0x3f8ab1f8 0x3f8ab1f8 0x3f8ab1f8 0x3f8ab1f8  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmla.f32 q0, q1, q2 :: Qd 0x488fe2e0 0x488fe2e0 0x488fe2e0 0x488fe2e0  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmla.f32 q3, q4, q5 :: Qd 0x4993b8eb 0x4993b8eb 0x4993b8eb 0x4993b8eb  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmla.f32 q10, q11, q2 :: Qd 0x474f9bfc 0x474f9bfc 0x474f9bfc 0x474f9bfc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmla.f32 q9, q5, q7 :: Qd 0x4a657ac4 0x4a657ac4 0x4a657ac4 0x4a657ac4  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmla.f32 q0, q11, q12 :: Qd 0x489eee3e 0x489eee3e 0x489eee3e 0x489eee3e  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmla.f32 q7, q1, q6 :: Qd 0xc54ff239 0xc54ff239 0xc54ff239 0xc54ff239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmla.f32 q0, q5, q2 :: Qd 0xbfb8fa0e 0xbfb8fa0e 0xbfb8fa0e 0xbfb8fa0e  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmla.f32 q10, q13, q15 :: Qd 0x488666c6 0x488666c6 0x488666c6 0x488666c6  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmla.f32 q10, q13, q15 :: Qd 0x4f115379 0x4f115379 0x4f115379 0x4f115379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmla.f32 q0, q1, q2 :: Qd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd 0x5d6e81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmla.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmla.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmla.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmla.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMLA (fp by scalar) ----
+vmla.f32 q0, q1, d4[0] :: Qd 0x45341000 0x45341000 0x45341000 0x45341000  Qm (i32)0x41c00000  Qn (i32)0x42f00000
+vmla.f32 q15, q8, d7[1] :: Qd 0xc6833e00 0xc6833e00 0xc6833e00 0xc6833e00  Qm (i32)0x430c0000  Qn (i32)0xc2f00000
+vmla.f32 q4, q8, d15[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmla.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.f32 q7, q8, d1[0] :: Qd 0x447a3fff 0x447a3fff 0x447a3fff 0x447a3fff  Qm (i32)0x64078678  Qn (i32)0x1fec1e4a
+vmla.f32 q7, q8, d1[0] :: Qd 0x65a96816 0x65a96816 0x65a96816 0x65a96816  Qm (i32)0x5368d4a5  Qn (i32)0x51ba43b7
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x40000000 0x40000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x40000000 0x40000000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x40000000 0x40000000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmla.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmla.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMLS (fp) ----
+vmls.f32 q0, q5, q2 :: Qd 0x44835ce4 0x44835ce4 0x44835ce4 0x44835ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmls.f32 q3, q4, q5 :: Qd 0x4ddf4321 0x4ddf4321 0x4ddf4321 0x4ddf4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmls.f32 q10, q11, q2 :: Qd 0x4f050e7f 0x4f050e7f 0x4f050e7f 0x4f050e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmls.f32 q9, q5, q7 :: Qd 0xcec3063f 0xcec3063f 0xcec3063f 0xcec3063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmls.f32 q0, q5, q2 :: Qd 0xd029254c 0xd029254c 0xd029254c 0xd029254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmls.f32 q3, q4, q5 :: Qd 0xc6fc5e00 0xc6fc5e00 0xc6fc5e00 0xc6fc5e00  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vmls.f32 q10, q11, q2 :: Qd 0xcc4a89cd 0xcc4a89cd 0xcc4a89cd 0xcc4a89cd  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vmls.f32 q9, q5, q7 :: Qd 0xcdb2c947 0xcdb2c947 0xcdb2c947 0xcdb2c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmls.f32 q0, q11, q12 :: Qd 0xcef90536 0xcef90536 0xcef90536 0xcef90536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmls.f32 q7, q1, q6 :: Qd 0x3f6a9c11 0x3f6a9c11 0x3f6a9c11 0x3f6a9c11  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmls.f32 q0, q1, q2 :: Qd 0xc88fe2a0 0xc88fe2a0 0xc88fe2a0 0xc88fe2a0  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmls.f32 q3, q4, q5 :: Qd 0xc993b8db 0xc993b8db 0xc993b8db 0xc993b8db  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmls.f32 q10, q11, q2 :: Qd 0xc74f99fc 0xc74f99fc 0xc74f99fc 0xc74f99fc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmls.f32 q9, q5, q7 :: Qd 0xca657abc 0xca657abc 0xca657abc 0xca657abc  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmls.f32 q0, q11, q12 :: Qd 0xc89eedfe 0xc89eedfe 0xc89eedfe 0xc89eedfe  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmls.f32 q7, q1, q6 :: Qd 0x45501239 0x45501239 0x45501239 0x45501239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmls.f32 q0, q5, q2 :: Qd 0x405c7d07 0x405c7d07 0x405c7d07 0x405c7d07  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmls.f32 q10, q13, q15 :: Qd 0xc8866686 0xc8866686 0xc8866686 0xc8866686  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmls.f32 q10, q13, q15 :: Qd 0xcf115379 0xcf115379 0xcf115379 0xcf115379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmls.f32 q0, q1, q2 :: Qd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmls.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmls.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmls.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmls.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMLS (fp by scalar) ----
+vmls.f32 q0, q1, d4[0] :: Qd 0xc533f000 0xc533f000 0xc533f000 0xc533f000  Qm (i32)0x41c00000  Qn (i32)0x42f00000
+vmls.f32 q15, q8, d7[1] :: Qd 0x46834200 0x46834200 0x46834200 0x46834200  Qm (i32)0x430c0000  Qn (i32)0xc2f00000
+vmls.f32 q4, q8, d15[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmls.f32 q7, q8, d1[1] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.f32 q7, q8, d1[0] :: Qd 0xc479bfff 0xc479bfff 0xc479bfff 0xc479bfff  Qm (i32)0x64078678  Qn (i32)0x1fec1e4a
+vmls.f32 q7, q8, d1[0] :: Qd 0xe5a96816 0xe5a96816 0xe5a96816 0xe5a96816  Qm (i32)0x5368d4a5  Qn (i32)0x51ba43b7
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0xff800000 0xff800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7fc00000 0x7fc00000 0x3f800000 0x3f800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmls.f32 q0, q1, d2[0] :: Qd 0x7f800000 0x7f800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmls.f32 q0, q1, d2[0] :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VCVT (integer <-> fp) ----
+vcvt.u32.f32 q0, q1 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003  Qm (i32)0x404ccccd
+vcvt.u32.f32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x64cb49b4
+vcvt.u32.f32 q15, q4 :: Qd 0xb2d05e00 0xb2d05e00 0xb2d05e00 0xb2d05e00  Qm (i32)0x4f32d05e
+vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xbf000000
+vcvt.u32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc0e33333
+vcvt.u32.f32 q12, q8 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007  Qm (i32)0x40fff800
+vcvt.u32.f32 q12, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc0fff800
+vcvt.s32.f32 q0, q1 :: Qd 0x00000003 0x00000003 0x00000003 0x00000003  Qm (i32)0x404ccccd
+vcvt.s32.f32 q10, q11 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x64cb49b4
+vcvt.s32.f32 q15, q4 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x4f32d05e
+vcvt.s32.f32 q15, q4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xbf000000
+vcvt.s32.f32 q15, q4 :: Qd 0xfffffff9 0xfffffff9 0xfffffff9 0xfffffff9  Qm (i32)0xc0e33333
+vcvt.s32.f32 q12, q8 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007  Qm (i32)0x40fff800
+vcvt.s32.f32 q12, q8 :: Qd 0xfffffff9 0xfffffff9 0xfffffff9 0xfffffff9  Qm (i32)0xc0fff800
+vcvt.f32.u32 q0, q1 :: Qd 0x40e00000 0x40e00000 0x40e00000 0x40e00000  Qm (i32)0x00000007
+vcvt.f32.u32 q10, q11 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000  Qm (i32)0x80000000
+vcvt.f32.u32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000  Qm (i32)0x80000001
+vcvt.f32.u32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000  Qm (i32)0x7fffffff
+vcvt.f32.u32 q0, q14 :: Qd 0x4e4282f4 0x4e4282f4 0x4e4282f4 0x4e4282f4  Qm (i32)0x30a0bcef
+vcvt.f32.s32 q0, q1 :: Qd 0x40e00000 0x40e00000 0x40e00000 0x40e00000  Qm (i32)0x00000007
+vcvt.f32.s32 q10, q11 :: Qd 0xcf000000 0xcf000000 0xcf000000 0xcf000000  Qm (i32)0x80000000
+vcvt.f32.s32 q0, q1 :: Qd 0xcf000000 0xcf000000 0xcf000000 0xcf000000  Qm (i32)0x80000001
+vcvt.f32.s32 q0, q1 :: Qd 0x4f000000 0x4f000000 0x4f000000 0x4f000000  Qm (i32)0x7fffffff
+vcvt.f32.s32 q0, q14 :: Qd 0x4e4282f4 0x4e4282f4 0x4e4282f4 0x4e4282f4  Qm (i32)0x30a0bcef
+vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcvt.u32.f32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000
+vcvt.u32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000
+vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcvt.s32.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcvt.s32.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x7f800000
+vcvt.s32.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0xff800000
+---- VCVT (fixed <-> fp) ----
+vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000019 0x00000019 0x00000019 0x00000019  Qm (i32)0x404ccccd
+vcvt.u32.f32 q10, q11, #1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x64cb49b4
+vcvt.u32.f32 q15, q4, #32 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x4f32d05e
+vcvt.u32.f32 q15, q4, #7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xbf000000
+vcvt.u32.f32 q15, q4, #4 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc0e33333
+vcvt.u32.f32 q12, q8, #3 :: Qd 0x0000003f 0x0000003f 0x0000003f 0x0000003f  Qm (i32)0x40fff800
+vcvt.u32.f32 q12, q8, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc0fff800
+vcvt.s32.f32 q0, q1, #5 :: Qd 0x00000066 0x00000066 0x00000066 0x00000066  Qm (i32)0x404ccccd
+vcvt.s32.f32 q10, q11, #1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x64cb49b4
+vcvt.s32.f32 q15, q4, #8 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x4f32d05e
+vcvt.s32.f32 q15, q4, #2 :: Qd 0xfffffffe 0xfffffffe 0xfffffffe 0xfffffffe  Qm (i32)0xbf000000
+vcvt.s32.f32 q15, q4, #1 :: Qd 0xfffffff2 0xfffffff2 0xfffffff2 0xfffffff2  Qm (i32)0xc0e33333
+vcvt.s32.f32 q12, q8, #2 :: Qd 0x0000001f 0x0000001f 0x0000001f 0x0000001f  Qm (i32)0x40fff800
+vcvt.s32.f32 q12, q8, #2 :: Qd 0xffffffe1 0xffffffe1 0xffffffe1 0xffffffe1  Qm (i32)0xc0fff800
+vcvt.f32.u32 q0, q1, #5 :: Qd 0x3e600000 0x3e600000 0x3e600000 0x3e600000  Qm (i32)0x00000007
+vcvt.f32.u32 q10, q11, #9 :: Qd 0x4a800000 0x4a800000 0x4a800000 0x4a800000  Qm (i32)0x80000000
+vcvt.f32.u32 q0, q1, #4 :: Qd 0x4d000000 0x4d000000 0x4d000000 0x4d000000  Qm (i32)0x80000001
+vcvt.f32.u32 q0, q1, #6 :: Qd 0x4c000000 0x4c000000 0x4c000000 0x4c000000  Qm (i32)0x7fffffff
+vcvt.f32.u32 q0, q14, #5 :: Qd 0x4bc282f4 0x4bc282f4 0x4bc282f4 0x4bc282f4  Qm (i32)0x30a0bcef
+vcvt.f32.s32 q0, q1, #12 :: Qd 0x3ae00000 0x3ae00000 0x3ae00000 0x3ae00000  Qm (i32)0x00000007
+vcvt.f32.s32 q10, q11, #8 :: Qd 0xcb000000 0xcb000000 0xcb000000 0xcb000000  Qm (i32)0x80000000
+vcvt.f32.s32 q0, q1, #2 :: Qd 0xce000000 0xce000000 0xce000000 0xce000000  Qm (i32)0x80000001
+vcvt.f32.s32 q0, q1, #1 :: Qd 0x4e800000 0x4e800000 0x4e800000 0x4e800000  Qm (i32)0x7fffffff
+vcvt.f32.s32 q0, q14, #6 :: Qd 0x4b4282f4 0x4b4282f4 0x4b4282f4 0x4b4282f4  Qm (i32)0x30a0bcef
+vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcvt.u32.f32 q0, q1, #3 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000
+vcvt.u32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000
+vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcvt.s32.f32 q0, q1, #3 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcvt.s32.f32 q0, q1, #3 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x7f800000
+vcvt.s32.f32 q0, q1, #3 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0xff800000
+---- VMAX (fp) ----
+vmax.f32 q0, q5, q2 :: Qd 0x41b851ec 0x41b851ec 0x41b851ec 0x41b851ec  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmax.f32 q3, q4, q5 :: Qd 0x44a84000 0x44a84000 0x44a84000 0x44a84000  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmax.f32 q10, q11, q2 :: Qd 0x473e7300 0x473e7300 0x473e7300 0x473e7300  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmax.f32 q9, q5, q7 :: Qd 0x47bb3de1 0x47bb3de1 0x47bb3de1 0x47bb3de1  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmax.f32 q0, q5, q2 :: Qd 0xc732633d 0xc732633d 0xc732633d 0xc732633d  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmax.f32 q3, q4, q5 :: Qd 0x44a84000 0x44a84000 0x44a84000 0x44a84000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vmax.f32 q10, q11, q2 :: Qd 0x473e7300 0x473e7300 0x473e7300 0x473e7300  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vmax.f32 q9, q5, q7 :: Qd 0x49d5e008 0x49d5e008 0x49d5e008 0x49d5e008  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmax.f32 q0, q11, q12 :: Qd 0x48add9f2 0x48add9f2 0x48add9f2 0x48add9f2  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmax.f32 q7, q1, q6 :: Qd 0x42080079 0x42080079 0x42080079 0x42080079  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmax.f32 q0, q1, q2 :: Qd 0x452c2000 0x452c2000 0x452c2000 0x452c2000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmax.f32 q3, q4, q5 :: Qd 0x44ad1333 0x44ad1333 0x44ad1333 0x44ad1333  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmax.f32 q10, q11, q2 :: Qd 0x43f3cb23 0x43f3cb23 0x43f3cb23 0x43f3cb23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmax.f32 q9, q5, q7 :: Qd 0x45062000 0x45062000 0x45062000 0x45062000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmax.f32 q0, q11, q12 :: Qd 0xc2610000 0xc2610000 0xc2610000 0xc2610000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmax.f32 q7, q1, q6 :: Qd 0x43e41fde 0x43e41fde 0x43e41fde 0x43e41fde  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmax.f32 q0, q5, q2 :: Qd 0x44053f2b 0x44053f2b 0x44053f2b 0x44053f2b  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmax.f32 q10, q13, q15 :: Qd 0xc3f29f73 0xc3f29f73 0xc3f29f73 0xc3f29f73  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmax.f32 q10, q13, q15 :: Qd 0x4887f70e 0x4887f70e 0x4887f70e 0x4887f70e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmax.f32 q0, q1, q2 :: Qd 0x4e920233 0x4e920233 0x4e920233 0x4e920233  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmax.f32 q0, q1, q2 :: Qd 0x3a800000 0x3a800000 0x3a800000 0x3a800000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vmax.f32 q0, q1, q2 :: Qd 0x3a800000 0x3a800000 0x3a800000 0x3a800000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vmax.f32 q0, q1, q2 :: Qd 0x45126004 0x45126004 0x45126004 0x45126004  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vmax.f32 q0, q1, q2 :: Qd 0xc5125ffc 0xc5125ffc 0xc5125ffc 0xc5125ffc  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vmax.f32 q0, q1, q2 :: Qd 0x47ae5e00 0x47ae5e00 0x47ae5e00 0x47ae5e00  Qm (i32)0x47ae5e00  Qn (i32)0x47ae5e00
+vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmax.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmax.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmax.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmax.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmax.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmax.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMIN (fp) ----
+vmin.f32 q0, q5, q2 :: Qd 0xc2364659 0xc2364659 0xc2364659 0xc2364659  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmin.f32 q3, q4, q5 :: Qd 0xc8a9da0f 0xc8a9da0f 0xc8a9da0f 0xc8a9da0f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmin.f32 q10, q11, q2 :: Qd 0xc732da7a 0xc732da7a 0xc732da7a 0xc732da7a  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmin.f32 q9, q5, q7 :: Qd 0x46855200 0x46855200 0x46855200 0x46855200  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmin.f32 q0, q5, q2 :: Qd 0xc872bcb1 0xc872bcb1 0xc872bcb1 0xc872bcb1  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmin.f32 q3, q4, q5 :: Qd 0x41c00000 0x41c00000 0x41c00000 0x41c00000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vmin.f32 q10, q11, q2 :: Qd 0x44882000 0x44882000 0x44882000 0x44882000  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vmin.f32 q9, q5, q7 :: Qd 0x43560000 0x43560000 0x43560000 0x43560000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmin.f32 q0, q11, q12 :: Qd 0x45b75812 0x45b75812 0x45b75812 0x45b75812  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmin.f32 q7, q1, q6 :: Qd 0x3b210e02 0x3b210e02 0x3b210e02 0x3b210e02  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmin.f32 q0, q1, q2 :: Qd 0x42d60000 0x42d60000 0x42d60000 0x42d60000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmin.f32 q3, q4, q5 :: Qd 0x445a8000 0x445a8000 0x445a8000 0x445a8000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmin.f32 q10, q11, q2 :: Qd 0x42da0000 0x42da0000 0x42da0000 0x42da0000  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmin.f32 q9, q5, q7 :: Qd 0x44db0000 0x44db0000 0x44db0000 0x44db0000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmin.f32 q0, q11, q12 :: Qd 0xc5b4d3c3 0xc5b4d3c3 0xc5b4d3c3 0xc5b4d3c3  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmin.f32 q7, q1, q6 :: Qd 0xc0e96d19 0xc0e96d19 0xc0e96d19 0xc0e96d19  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmin.f32 q0, q5, q2 :: Qd 0xbb965394 0xbb965394 0xbb965394 0xbb965394  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmin.f32 q10, q13, q15 :: Qd 0xc40dcfae 0xc40dcfae 0xc40dcfae 0xc40dcfae  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmin.f32 q10, q13, q15 :: Qd 0x4608d008 0x4608d008 0x4608d008 0x4608d008  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmin.f32 q0, q1, q2 :: Qd 0x4e511724 0x4e511724 0x4e511724 0x4e511724  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmin.f32 q0, q1, q2 :: Qd 0xba800000 0xba800000 0xba800000 0xba800000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vmin.f32 q0, q1, q2 :: Qd 0xba800000 0xba800000 0xba800000 0xba800000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vmin.f32 q0, q1, q2 :: Qd 0x45125ffc 0x45125ffc 0x45125ffc 0x45125ffc  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vmin.f32 q0, q1, q2 :: Qd 0xc5126004 0xc5126004 0xc5126004 0xc5126004  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vmin.f32 q0, q1, q2 :: Qd 0x47ae5e00 0x47ae5e00 0x47ae5e00 0x47ae5e00  Qm (i32)0x47ae5e00  Qn (i32)0x47ae5e00
+vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmin.f32 q0, q1, q2 :: Qd 0x3f800000 0x3f800000 0x3f800000 0x3f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmin.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmin.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmin.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmin.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VRECPE ----
+vrecpe.u32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x404ccccd
+vrecpe.u32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x64cb49b4
+vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x4f32d05e
+vrecpe.u32 q15, q4 :: Qd 0xab800000 0xab800000 0xab800000 0xab800000  Qm (i32)0xbf000000
+vrecpe.u32 q15, q4 :: Qd 0xaa000000 0xaa000000 0xaa000000 0xaa000000  Qm (i32)0xc0e33333
+vrecpe.u32 q12, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x40fff800
+vrecpe.u32 q12, q8 :: Qd 0xaa000000 0xaa000000 0xaa000000 0xaa000000  Qm (i32)0xc0fff800
+vrecpe.u32 q0, q1 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x404ccccd
+vrecpe.u32 q10, q11 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x64cb49b4
+vrecpe.u32 q15, q4 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x4f32d05e
+vrecpe.f32 q15, q4 :: Qd 0xbfff8000 0xbfff8000 0xbfff8000 0xbfff8000  Qm (i32)0xbf000000
+vrecpe.f32 q15, q4 :: Qd 0xbe100000 0xbe100000 0xbe100000 0xbe100000  Qm (i32)0xc0e33333
+vrecpe.f32 q12, q8 :: Qd 0x3e000000 0x3e000000 0x3e000000 0x3e000000  Qm (i32)0x40fff800
+vrecpe.f32 q12, q8 :: Qd 0xbe000000 0xbe000000 0xbe000000 0xbe000000  Qm (i32)0xc0fff800
+vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000007
+vrecpe.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x80000000
+vrecpe.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x80000001
+vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fffffff
+vrecpe.f32 q0, q14 :: Qd 0x4e4c0000 0x4e4c0000 0x4e4c0000 0x4e4c0000  Qm (i32)0x30a0bcef
+vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000007
+vrecpe.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x80000000
+vrecpe.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x80000001
+vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fffffff
+vrecpe.f32 q0, q14 :: Qd 0x4e4c0000 0x4e4c0000 0x4e4c0000 0x4e4c0000  Qm (i32)0x30a0bcef
+vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000
+vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000000
+vrecpe.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000
+vrecpe.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0xff800000
+vrecpe.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000
+vrecpe.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000000
+vrecpe.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000
+vrecpe.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0xff800000
+---- VRECPS ----
+vrecps.f32 q0, q5, q2 :: Qd 0x44837ce4 0x44837ce4 0x44837ce4 0x44837ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vrecps.f32 q3, q4, q5 :: Qd 0x4ddf4321 0x4ddf4321 0x4ddf4321 0x4ddf4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vrecps.f32 q10, q11, q2 :: Qd 0x4f050e7f 0x4f050e7f 0x4f050e7f 0x4f050e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vrecps.f32 q9, q5, q7 :: Qd 0xcec3063f 0xcec3063f 0xcec3063f 0xcec3063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vrecps.f32 q0, q5, q2 :: Qd 0xd029254c 0xd029254c 0xd029254c 0xd029254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vrecps.f32 q3, q4, q5 :: Qd 0xc6fc5c00 0xc6fc5c00 0xc6fc5c00 0xc6fc5c00  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vrecps.f32 q10, q11, q2 :: Qd 0xcc4a89cc 0xcc4a89cc 0xcc4a89cc 0xcc4a89cc  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vrecps.f32 q9, q5, q7 :: Qd 0xcdb2c947 0xcdb2c947 0xcdb2c947 0xcdb2c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vrecps.f32 q0, q11, q12 :: Qd 0xcef90536 0xcef90536 0xcef90536 0xcef90536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vrecps.f32 q7, q1, q6 :: Qd 0x3ff54e08 0x3ff54e08 0x3ff54e08 0x3ff54e08  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vrecps.f32 q0, q1, q2 :: Qd 0xc88fe280 0xc88fe280 0xc88fe280 0xc88fe280  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vrecps.f32 q3, q4, q5 :: Qd 0xc993b8d3 0xc993b8d3 0xc993b8d3 0xc993b8d3  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vrecps.f32 q10, q11, q2 :: Qd 0xc74f98fc 0xc74f98fc 0xc74f98fc 0xc74f98fc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vrecps.f32 q9, q5, q7 :: Qd 0xca657ab8 0xca657ab8 0xca657ab8 0xca657ab8  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vrecps.f32 q0, q11, q12 :: Qd 0xc89eedde 0xc89eedde 0xc89eedde 0xc89eedde  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vrecps.f32 q7, q1, q6 :: Qd 0x45502239 0x45502239 0x45502239 0x45502239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vrecps.f32 q0, q5, q2 :: Qd 0x408e3e84 0x408e3e84 0x408e3e84 0x408e3e84  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vrecps.f32 q10, q13, q15 :: Qd 0xc8866666 0xc8866666 0xc8866666 0xc8866666  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vrecps.f32 q10, q13, q15 :: Qd 0xcf115379 0xcf115379 0xcf115379 0xcf115379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vrecps.f32 q0, q1, q2 :: Qd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd 0xdd6e81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vrecps.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vrecps.f32 q0, q1, q2 :: Qd 0x40000000 0x40000000 0x40000000 0x40000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vrecps.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vrecps.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VABS (fp) ----
+vabs.f32 q0, q1 :: Qd 0x404ccccd 0x404ccccd 0x404ccccd 0x404ccccd  Qm (i32)0x404ccccd
+vabs.f32 q10, q11 :: Qd 0x64cb49b4 0x64cb49b4 0x64cb49b4 0x64cb49b4  Qm (i32)0x64cb49b4
+vabs.f32 q15, q4 :: Qd 0x4f32d05e 0x4f32d05e 0x4f32d05e 0x4f32d05e  Qm (i32)0x4f32d05e
+vabs.f32 q15, q4 :: Qd 0x3f000000 0x3f000000 0x3f000000 0x3f000000  Qm (i32)0xbf000000
+vabs.f32 q15, q4 :: Qd 0x40e33333 0x40e33333 0x40e33333 0x40e33333  Qm (i32)0xc0e33333
+vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800  Qm (i32)0x40fff800
+vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800  Qm (i32)0xc0fff800
+vabs.f32 q0, q1 :: Qd 0x404ccccd 0x404ccccd 0x404ccccd 0x404ccccd  Qm (i32)0x404ccccd
+vabs.f32 q10, q11 :: Qd 0x64cb49b4 0x64cb49b4 0x64cb49b4 0x64cb49b4  Qm (i32)0x64cb49b4
+vabs.f32 q15, q4 :: Qd 0x4f32d05e 0x4f32d05e 0x4f32d05e 0x4f32d05e  Qm (i32)0x4f32d05e
+vabs.f32 q15, q4 :: Qd 0x3f000000 0x3f000000 0x3f000000 0x3f000000  Qm (i32)0xbf000000
+vabs.f32 q15, q4 :: Qd 0x40e33333 0x40e33333 0x40e33333 0x40e33333  Qm (i32)0xc0e33333
+vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800  Qm (i32)0x40fff800
+vabs.f32 q12, q8 :: Qd 0x40fff800 0x40fff800 0x40fff800 0x40fff800  Qm (i32)0xc0fff800
+vabs.f32 q0, q1 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007  Qm (i32)0x00000007
+vabs.f32 q10, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000000
+vabs.f32 q0, q1 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x80000001
+vabs.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x7fffffff
+vabs.f32 q0, q14 :: Qd 0x30a0bcef 0x30a0bcef 0x30a0bcef 0x30a0bcef  Qm (i32)0x30a0bcef
+vabs.f32 q0, q1 :: Qd 0x00000007 0x00000007 0x00000007 0x00000007  Qm (i32)0x00000007
+vabs.f32 q10, q11 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000000
+vabs.f32 q0, q1 :: Qd 0x00000001 0x00000001 0x00000001 0x00000001  Qm (i32)0x80000001
+vabs.f32 q0, q1 :: Qd 0x7fffffff 0x7fffffff 0x7fffffff 0x7fffffff  Qm (i32)0x7fffffff
+vabs.f32 q0, q14 :: Qd 0x30a0bcef 0x30a0bcef 0x30a0bcef 0x30a0bcef  Qm (i32)0x30a0bcef
+vabs.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000
+vabs.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000
+vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000
+vabs.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000
+vabs.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000
+vabs.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000
+---- VCGT (fp) ----
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vcgt.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vcgt.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43677333  Qn (i32)0x43677333
+vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vcgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vcgt.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vcgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vcgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vcgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vcgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vcgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vcgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vcgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vcgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vcgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vcgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x47ae5e00  Qn (i32)0x47ae5e00
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0xff800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vcgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vcgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VCGE (fp) ----
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vcge.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vcge.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43677333  Qn (i32)0x43677333
+vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vcge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vcge.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vcge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vcge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vcge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vcge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vcge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vcge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vcge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vcge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vcge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vcge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x47ae5e00  Qn (i32)0x47ae5e00
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0xff800000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vcge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vcge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VACGT (fp) ----
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vacgt.f32 q2, q15, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vacgt.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43677333  Qn (i32)0x43677333
+vacgt.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vacgt.f32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vacgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vacgt.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vacgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vacgt.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vacgt.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vacgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vacgt.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vacgt.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vacgt.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vacgt.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vacgt.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vacgt.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vacgt.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vacgt.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x47ae5e00  Qn (i32)0x47ae5e00
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vacgt.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x00000000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vacgt.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VACGE (fp) ----
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vacge.f32 q2, q15, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vacge.f32 q15, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43677333  Qn (i32)0x43677333
+vacge.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vacge.f32 q3, q4, q5 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vacge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vacge.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vacge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vacge.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vacge.f32 q0, q11, q12 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vacge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vacge.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vacge.f32 q10, q11, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vacge.f32 q9, q5, q7 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vacge.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vacge.f32 q7, q1, q6 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vacge.f32 q0, q5, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vacge.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vacge.f32 q10, q13, q15 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x47ae5e00  Qn (i32)0x47ae5e00
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vacge.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x00000000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vacge.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VCEQ (fp) ----
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vceq.f32 q2, q15, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vceq.f32 q15, q7, q8 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x43677333  Qn (i32)0x43677333
+vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vceq.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vceq.f32 q7, q1, q6 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vceq.f32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vceq.f32 q10, q11, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vceq.f32 q9, q5, q7 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vceq.f32 q0, q11, q12 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vceq.f32 q7, q1, q6 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vceq.f32 q0, q5, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vceq.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vceq.f32 q10, q13, q15 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x47ae5e00  Qn (i32)0x47ae5e00
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vceq.f32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vceq.f32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VCEQ (fp) #0 ----
+vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x01000000
+vceq.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000001
+vceq.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000000
+vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41b851ec
+vceq.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc1b851ec
+vceq.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vceq.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000
+vceq.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000
+---- VCGT (fp) #0 ----
+vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x01000000
+vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000001
+vcgt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000000
+vcgt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x41b851ec
+vcgt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc1b851ec
+vcgt.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000
+vcgt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000
+---- VCLT (fp) #0 ----
+vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x01000000
+vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000001
+vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000000
+vclt.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41b851ec
+vclt.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc1b851ec
+vclt.f32 q10, q15, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000
+vclt.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000
+---- VCGE (fp) #0 ----
+vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x01000000
+vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000001
+vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000000
+vcge.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x41b851ec
+vcge.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xc1b851ec
+vcge.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcge.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcge.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x7f800000
+vcge.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0xff800000
+---- VCLE (fp) #0 ----
+vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x01000000
+vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000001
+vcle.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x80000000
+vcle.f32 q2, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x41b851ec
+vcle.f32 q2, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xc1b851ec
+vcle.f32 q10, q15, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.f32 q0, q1, #0 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000
+vcle.f32 q0, q1, #0 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff  Qm (i32)0xff800000
+---- VNEG (fp) ----
+vneg.f32 q0, q1 :: Qd 0x81000000 0x81000000 0x81000000 0x81000000  Qm (i32)0x01000000
+vneg.f32 q0, q1 :: Qd 0x80000001 0x80000001 0x80000001 0x80000001  Qm (i32)0x00000001
+vneg.f32 q2, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x80000000
+vneg.f32 q2, q1 :: Qd 0xc1b851ec 0xc1b851ec 0xc1b851ec 0xc1b851ec  Qm (i32)0x41b851ec
+vneg.f32 q2, q1 :: Qd 0x41b851ec 0x41b851ec 0x41b851ec 0x41b851ec  Qm (i32)0xc1b851ec
+vneg.f32 q10, q15 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x00000000
+vneg.f32 q0, q1 :: Qd 0xffc00000 0xffc00000 0xffc00000 0xffc00000  Qm (i32)0x7fc00000
+vneg.f32 q0, q1 :: Qd 0x80000000 0x80000000 0x80000000 0x80000000  Qm (i32)0x00000000
+vneg.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000
+vneg.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000
+---- VRSQRTS ----
+vrsqrts.f32 q0, q5, q2 :: Qd 0x44039ce4 0x44039ce4 0x44039ce4 0x44039ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vrsqrts.f32 q3, q4, q5 :: Qd 0x4d5f4321 0x4d5f4321 0x4d5f4321 0x4d5f4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vrsqrts.f32 q10, q11, q2 :: Qd 0x4e850e7f 0x4e850e7f 0x4e850e7f 0x4e850e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vrsqrts.f32 q9, q5, q7 :: Qd 0xce43063f 0xce43063f 0xce43063f 0xce43063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vrsqrts.f32 q0, q5, q2 :: Qd 0xcfa9254c 0xcfa9254c 0xcfa9254c 0xcfa9254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vrsqrts.f32 q3, q4, q5 :: Qd 0xc67c5a00 0xc67c5a00 0xc67c5a00 0xc67c5a00  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vrsqrts.f32 q10, q11, q2 :: Qd 0xcbca89cc 0xcbca89cc 0xcbca89cc 0xcbca89cc  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vrsqrts.f32 q9, q5, q7 :: Qd 0xcd32c947 0xcd32c947 0xcd32c947 0xcd32c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vrsqrts.f32 q0, q11, q12 :: Qd 0xce790536 0xce790536 0xce790536 0xce790536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vrsqrts.f32 q7, q1, q6 :: Qd 0x3fbaa704 0x3fbaa704 0x3fbaa704 0x3fbaa704  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vrsqrts.f32 q0, q1, q2 :: Qd 0xc80fe260 0xc80fe260 0xc80fe260 0xc80fe260  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vrsqrts.f32 q3, q4, q5 :: Qd 0xc913b8cb 0xc913b8cb 0xc913b8cb 0xc913b8cb  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vrsqrts.f32 q10, q11, q2 :: Qd 0xc6cf97fc 0xc6cf97fc 0xc6cf97fc 0xc6cf97fc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vrsqrts.f32 q9, q5, q7 :: Qd 0xc9e57ab4 0xc9e57ab4 0xc9e57ab4 0xc9e57ab4  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vrsqrts.f32 q0, q11, q12 :: Qd 0xc81eedbe 0xc81eedbe 0xc81eedbe 0xc81eedbe  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vrsqrts.f32 q7, q1, q6 :: Qd 0x44d03239 0x44d03239 0x44d03239 0x44d03239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vrsqrts.f32 q0, q5, q2 :: Qd 0x402e3e84 0x402e3e84 0x402e3e84 0x402e3e84  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vrsqrts.f32 q10, q13, q15 :: Qd 0xc8066646 0xc8066646 0xc8066646 0xc8066646  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vrsqrts.f32 q10, q13, q15 :: Qd 0xce915379 0xce915379 0xce915379 0xce915379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vrsqrts.f32 q0, q1, q2 :: Qd 0xdcee81fd 0xdcee81fd 0xdcee81fd 0xdcee81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x3fc00000 0x3fc00000 0x3fc00000 0x3fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vrsqrts.f32 q0, q1, q2 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vrsqrts.f32 q0, q1, q2 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VRSQRTE (fp) ----
+vrsqrte.f32 q0, q1 :: Qd 0x3f0f0000 0x3f0f0000 0x3f0f0000 0x3f0f0000  Qm (i32)0x404ccccd
+vrsqrte.f32 q10, q11 :: Qd 0x2ccb0000 0x2ccb0000 0x2ccb0000 0x2ccb0000  Qm (i32)0x64cb49b4
+vrsqrte.f32 q15, q4 :: Qd 0x37998000 0x37998000 0x37998000 0x37998000  Qm (i32)0x4f32d05e
+vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xbf000000
+vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xc0e33333
+vrsqrte.f32 q12, q8 :: Qd 0x3eb50000 0x3eb50000 0x3eb50000 0x3eb50000  Qm (i32)0x40fff800
+vrsqrte.f32 q12, q8 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xc0fff800
+vrsqrte.f32 q0, q1 :: Qd 0x3f0f0000 0x3f0f0000 0x3f0f0000 0x3f0f0000  Qm (i32)0x404ccccd
+vrsqrte.f32 q10, q11 :: Qd 0x2ccb0000 0x2ccb0000 0x2ccb0000 0x2ccb0000  Qm (i32)0x64cb49b4
+vrsqrte.f32 q15, q4 :: Qd 0x37998000 0x37998000 0x37998000 0x37998000  Qm (i32)0x4f32d05e
+vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xbf000000
+vrsqrte.f32 q15, q4 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xc0e33333
+vrsqrte.f32 q12, q8 :: Qd 0x3eb50000 0x3eb50000 0x3eb50000 0x3eb50000  Qm (i32)0x40fff800
+vrsqrte.f32 q12, q8 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xc0fff800
+vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000007
+vrsqrte.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x80000000
+vrsqrte.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x80000001
+vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fffffff
+vrsqrte.f32 q0, q14 :: Qd 0x46e48000 0x46e48000 0x46e48000 0x46e48000  Qm (i32)0x30a0bcef
+vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000007
+vrsqrte.f32 q10, q11 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x80000000
+vrsqrte.f32 q0, q1 :: Qd 0xff800000 0xff800000 0xff800000 0xff800000  Qm (i32)0x80000001
+vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fffffff
+vrsqrte.f32 q0, q14 :: Qd 0x46e48000 0x46e48000 0x46e48000 0x46e48000  Qm (i32)0x30a0bcef
+vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000
+vrsqrte.f32 q0, q1 :: Qd 0x7f800000 0x7f800000 0x7f800000 0x7f800000  Qm (i32)0x00000000
+vrsqrte.f32 q0, q1 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000  Qm (i32)0x7f800000
+vrsqrte.f32 q0, q1 :: Qd 0x7fc00000 0x7fc00000 0x7fc00000 0x7fc00000  Qm (i32)0xff800000

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.vgtest
new file mode 100644 (file)
index 0000000..d73f24b
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon128.vgtest
@@ -0,0 +1,2 @@
+prog: neon128
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.c
new file mode 100644 (file)
index 0000000..e826c16
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.c
@@ -0,0 +1,3634 @@
+
+/* How to compile:
+
+   gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \
+       -marm -o neon64-a neon64.c
+
+   or
+
+   gcc -O -g -Wall -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp \
+       -mthumb -o neon64-t neon64.c
+
+*/
+
+#include <stdio.h>
+#include <string.h>
+#include <math.h>
+
+#ifndef __thumb__
+// ARM
+#define MOVE_to_FPSCR_from_R4 \
+      ".word 0xEEE14A10 @ vmsr FPSCR, r4\n\t"
+#define MOVE_to_R4_from_FPSCR \
+      ".word 0xEEF14A10 @ vmrs r4, FPSCR\n\t"
+#endif
+
+#ifdef __thumb__
+// Thumb
+#define MOVE_to_FPSCR_from_R4 \
+      ".word 0x4A10EEE1 @ vmsr FPSCR, r4\n\t"
+#define MOVE_to_R4_from_FPSCR \
+      ".word 0x4A10EEF1 @ vmrs r4, FPSCR\n\t"
+#endif
+
+static inline unsigned int f2u(float x) {
+    union {
+        float f;
+        unsigned int u;
+    } cvt;
+    cvt.f = x;
+    return cvt.u;
+}
+
+/* test macros to generate and output the result of a single instruction */
+
+const unsigned int mem[] = {
+    0x121f1e1f, 0x131b1a1b, 0x141c1f1c, 0x151d191d,
+    0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a,
+    0x3f343f3e, 0x3e353d3c, 0x363a3c3b, 0x3b373b3a,
+    0x454f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
+};
+
+#define TESTINSN_imm(instruction, QD, imm) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      instruction ", #" #imm "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out) \
+      : #QD, "memory" \
+      ); \
+  printf("%s, #" #imm " :: Qd 0x%08x 0x%08x\n", \
+      instruction, out[1], out[0]); \
+}
+
+#define TESTINSN_un(instruction, QD, QM, QMtype, QMval) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval) \
+      : #QD, #QM, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x\n", \
+      instruction, out[1], out[0], QMval); \
+}
+
+#define TESTINSN_un_q(instruction, QD, QM, QMtype, QMval) \
+{ \
+  unsigned int out[2]; \
+  unsigned int fpscr; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "mov r4, #0\n\t" \
+      MOVE_to_FPSCR_from_R4 \
+      "vdup." #QMtype " " #QM ", %2\n\t" \
+      instruction "\n\t" \
+      "vstmia %1, {" #QD "}\n\t" \
+      MOVE_to_R4_from_FPSCR \
+      "mov %0, r4" \
+      : "=r" (fpscr) \
+      : "r" (out), "r" (QMval) \
+      : #QD, #QM, "memory", "r4" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x  fpscr %08x\n", \
+      instruction, out[1], out[0], QMval, fpscr); \
+}
+
+#define TESTINSN_core_to_scalar(instruction, QD, QM, QMval) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "mov " #QM ", %1\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval) \
+      : #QD, #QM, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x  Qm 0x%08x\n", \
+      instruction, out[1], out[0], QMval); \
+}
+
+#define TESTINSN_scalar_to_core(instruction, QD, QM, QMtype, QMval) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "mov " #QD ", #0x55" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      instruction "\n\t" \
+      "str " #QD ", [%0]\n\t" \
+      : \
+      : "r" (out), "r" (QMval) \
+      : #QD, #QM, "memory" \
+      ); \
+  printf("%s :: Rd 0x%08x  Qm (" #QMtype ")0x%08x\n", \
+      instruction, out[0], QMval); \
+}
+
+#define TESTINSN_VLDn(instruction, QD1, QD2, QD3, QD4) \
+{ \
+  unsigned int out[8]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD1 ", #0x55" "\n\t" \
+      "vmov.i8 " #QD2 ", #0x55" "\n\t" \
+      "vmov.i8 " #QD3 ", #0x55" "\n\t" \
+      "vmov.i8 " #QD4 ", #0x55" "\n\t" \
+      instruction ", [%1]\n\t" \
+      "mov r4, %0\n\t" \
+      "vstmia %0!, {" #QD1 "}\n\t" \
+      "vstmia %0!, {" #QD2 "}\n\t" \
+      "vstmia %0!, {" #QD3 "}\n\t" \
+      "vstmia %0!, {" #QD4 "}\n\t" \
+      "mov %0, r4\n\t" \
+      : \
+      : "r" (out), "r" (mem) \
+      : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \
+      ); \
+  printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\
+          "0x%08x 0x%08x 0x%08x 0x%08x\n", \
+      instruction, out[0], out[1], out[2], out[3], out[4],\
+          out[5], out[6], out[7]); \
+}
+
+#define TESTINSN_VSTn(instruction, QD1, QD2, QD3, QD4) \
+{ \
+  unsigned int out[8]; \
+\
+  memset(out, 0x55, 8 * (sizeof(unsigned int)));\
+  __asm__ volatile( \
+      "mov r4, %1\n\t" \
+      "vldmia %1!, {" #QD1 "}\n\t" \
+      "vldmia %1!, {" #QD2 "}\n\t" \
+      "vldmia %1!, {" #QD3 "}\n\t" \
+      "vldmia %1!, {" #QD4 "}\n\t" \
+      "mov %1, r4\n\t" \
+      instruction ", [%0]\n\t" \
+      : \
+      : "r" (out), "r" (mem) \
+      : #QD1, #QD2, #QD3, #QD4, "memory", "r4" \
+      ); \
+  printf("%s :: Result 0x%08x 0x%08x 0x%08x 0x%08x "\
+          "0x%08x 0x%08x 0x%08x 0x%08x\n", \
+      instruction, out[0], out[1], out[2], out[3], out[4],\
+          out[5], out[6], out[7]); \
+}
+
+#define TESTINSN_bin(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      "vdup." #QNtype " " #QN ", %2\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval), "r" (QNval) \
+      : #QD, #QM, #QN, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x\n", \
+      instruction, out[1], out[0], QMval, QNval); \
+}
+
+#define TESTINSN_bin_f(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "vdup.i32 " #QD ", %3\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      "vdup." #QNtype " " #QN ", %2\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval), "r" (QNval), "r"(0x3f800000) \
+      : #QD, #QM, #QN, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x\n", \
+      instruction, out[1], out[0], QMval, QNval); \
+}
+
+#define TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
+        QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      "vdup." #QN1type " " #QN1 ", %2\n\t" \
+      "vdup." #QN2type " " #QN2 ", %3\n\t" \
+      "vdup." #QN3type " " #QN3 ", %4\n\t" \
+      "vdup." #QN4type " " #QN4 ", %5\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval), "r" (QN1val), "r" (QN2val), "r" (QN3val), \
+        "r" (QN4val) \
+      : #QD, #QM, #QN1, #QN2, #QN3, #QN4, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn1 (" #QN1type ")0x%08x" \
+      "  Qn2 (" #QN2type ")0x%08x" \
+      "  Qn3 (" #QN3type ")0x%08x" \
+      "  Qn4 (" #QN4type ")0x%08x\n", \
+      instruction, out[1], out[0], QMval, QN1val, QN2val, QN3val, QN4val); \
+}
+#define TESTINSN_tbl_1(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val) \
+    TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
+            QN1, QN1type, QN1val, QN1, QN1type, QN1val, QN1, QN1type, QN1val)
+#define TESTINSN_tbl_2(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
+        QN2, QN2type, QN2val) \
+    TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
+            QN2, QN2type, QN2val, QN1, QN1type, QN1val, QN2, QN2type, QN2val)
+#define TESTINSN_tbl_3(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
+        QN2, QN2type, QN2val, QN3, QN3type, QN3val) \
+    TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
+            QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN2, QN2type, QN2val)
+#define TESTINSN_tbl_4(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
+        QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val) \
+    TESTINSN_tbl(instruction, QD, QM, QMtype, QMval, QN1, QN1type, QN1val, \
+            QN2, QN2type, QN2val, QN3, QN3type, QN3val, QN4, QN4type, QN4val)
+
+#define TESTINSN_bin_q(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out[2]; \
+  unsigned int fpscr; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "mov r4, #0\n\t" \
+      MOVE_to_FPSCR_from_R4 \
+      "vdup." #QMtype " " #QM ", %2\n\t" \
+      "vdup." #QNtype " " #QN ", %3\n\t" \
+      instruction "\n\t" \
+      "vstmia %1, {" #QD "}\n\t" \
+      MOVE_to_R4_from_FPSCR \
+      "mov %0, r4" \
+      : "=r" (fpscr) \
+      : "r" (out), "r" (QMval), "r" (QNval) \
+      : #QD, #QM, #QN, "memory", "r4" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x  fpscr: %08x\n", \
+      instruction, out[1], out[0], QMval, QNval, fpscr); \
+}
+
+#define TESTINSN_dual(instruction, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out1[2]; \
+  unsigned int out2[2]; \
+\
+  __asm__ volatile( \
+      "vdup." #QMtype " " #QM ", %2\n\t" \
+      "vdup." #QNtype " " #QN ", %3\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QM "}\n\t" \
+      "vstmia %1, {" #QN "}\n\t" \
+      : \
+      : "r" (out1), "r" (out2), "r" (QMval), "r" (QNval) \
+      : #QM, #QN, "memory" \
+      ); \
+  printf("%s :: Qm 0x%08x 0x%08x  Qn 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x\n", \
+      instruction, out1[1], out1[0], out2[1], out2[0], QMval, QNval); \
+}
+
+// Ditto TESTING_bin(), but in QD all zeros
+#define TESTINSN_bin_0s(instruction, QD, QM, QMtype, QMval, QN, QNtype, QNval) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x00" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      "vdup." #QNtype " " #QN ", %2\n\t" \
+      instruction "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval), "r" (QNval) \
+      : #QD, #QM, #QN, "memory" \
+      ); \
+  printf("%s :: Qd 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x" \
+      "  Qn (" #QNtype ")0x%08x\n", \
+      instruction, out[1], out[0], QMval, QNval); \
+}
+
+#if 0
+#define TESTINSN_2reg_shift(instruction, QD, QM, QMtype, QMval, imm) \
+{ \
+  unsigned int out[2]; \
+\
+  __asm__ volatile( \
+      "vmov.i8 " #QD ", #0x55" "\n\t" \
+      "vdup." #QMtype " " #QM ", %1\n\t" \
+      instruction ", #" #imm "\n\t" \
+      "vstmia %0, {" #QD "}\n\t" \
+      : \
+      : "r" (out), "r" (QMval) \
+      : #QD, #QM, "memory" \
+      ); \
+  printf("%s, #" #imm " :: Qd 0x%08x 0x%08x  Qm (" #QMtype ")0x%08x", \
+      instruction, out[1], out[0], QMval); \
+}
+#endif
+
+int main(int argc, char **argv)
+{
+    printf("----- VMOV (immediate) -----\n");
+    TESTINSN_imm("vmov.i32 d0", d0, 0x7);
+    TESTINSN_imm("vmov.i16 d1", d1, 0x7);
+    TESTINSN_imm("vmov.i8 d2", d2, 0x7);
+    TESTINSN_imm("vmov.i32 d5", d5, 0x700);
+    TESTINSN_imm("vmov.i16 d7", d7, 0x700);
+    TESTINSN_imm("vmov.i32 d10", d10, 0x70000);
+    TESTINSN_imm("vmov.i32 d12", d12, 0x7000000);
+    TESTINSN_imm("vmov.i32 d13", d13, 0x7FF);
+    TESTINSN_imm("vmov.i32 d14", d14, 0x7FFFF);
+    TESTINSN_imm("vmov.i64 d15", d15, 0xFF0000FF00FFFF00);
+
+    printf("----- VMVN (immediate) -----\n");
+    TESTINSN_imm("vmvn.i32 d0", d0, 0x7);
+    TESTINSN_imm("vmvn.i16 d1", d1, 0x7);
+    TESTINSN_imm("vmvn.i8 d2", d2, 0x7);
+    TESTINSN_imm("vmvn.i32 d5", d5, 0x700);
+    TESTINSN_imm("vmvn.i16 d7", d7, 0x700);
+    TESTINSN_imm("vmvn.i32 d10", d10, 0x70000);
+    TESTINSN_imm("vmvn.i32 d13", d13, 0x7000000);
+    TESTINSN_imm("vmvn.i32 d11", d11, 0x7FF);
+    TESTINSN_imm("vmvn.i32 d14", d14, 0x7FFFF);
+    TESTINSN_imm("vmvn.i64 d15", d15, 0xFF0000FF00FFFF00);
+
+    printf("----- VORR (immediate) -----\n");
+    TESTINSN_imm("vorr.i32 d0", d0, 0x7);
+    TESTINSN_imm("vorr.i16 d2", d2, 0x7);
+    TESTINSN_imm("vorr.i32 d8", d8, 0x700);
+    TESTINSN_imm("vorr.i16 d6", d6, 0x700);
+    TESTINSN_imm("vorr.i32 d14", d14, 0x70000);
+    TESTINSN_imm("vorr.i32 d15", d15, 0x7000000);
+
+    printf("----- VBIC (immediate) -----\n");
+    TESTINSN_imm("vbic.i32 d0", d0, 0x7);
+    TESTINSN_imm("vbic.i16 d3", d3, 0x7);
+    TESTINSN_imm("vbic.i32 d5", d5, 0x700);
+    TESTINSN_imm("vbic.i16 d8", d8, 0x700);
+    TESTINSN_imm("vbic.i32 d10", d10, 0x70000);
+    TESTINSN_imm("vbic.i32 d15", d15, 0x7000000);
+
+    printf("---- VMVN (register) ----\n");
+    TESTINSN_un("vmvn d0, d1", d0, d1, i32, 24);
+    TESTINSN_un("vmvn d10, d15", d10, d15, i32, 24);
+    TESTINSN_un("vmvn d0, d14", d0, d14, i32, 24);
+
+    printf("---- VMOV (register) ----\n");
+    TESTINSN_un("vmov d0, d1", d0, d1, i32, 24);
+    TESTINSN_un("vmov d10, d15", d10, d15, i32, 24);
+    TESTINSN_un("vmov d0, d14", d0, d14, i32, 24);
+
+    printf("---- VDUP (ARM core register) (tested indirectly) ----\n");
+    TESTINSN_un("vmov d0, d1", d0, d1, i8, 7);
+    TESTINSN_un("vmov d10, d11", d10, d11, i16, 7);
+    TESTINSN_un("vmov d0, d15", d0, d15, i32, 7);
+
+    printf("---- VADD ----\n");
+    TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vadd.i64 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vadd.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vadd.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vadd.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vadd.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vadd.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vadd.i64 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vadd.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vadd.i64 d13, d14, d15", d13, d14, i32, 140, d15, i32, 120);
+
+    printf("---- VSUB ----\n");
+    TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vsub.i64 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vsub.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vsub.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vsub.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vsub.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vsub.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vsub.i64 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vsub.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vsub.i64 d13, d14, d15", d13, d14, i32, 140, d15, i32, 120);
+
+    printf("---- VAND ----\n");
+    TESTINSN_bin("vand d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
+    TESTINSN_bin("vand d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
+    TESTINSN_bin("vand d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
+    TESTINSN_bin("vand d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
+
+    printf("---- VBIC ----\n");
+    TESTINSN_bin("vbic d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
+    TESTINSN_bin("vbic d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
+    TESTINSN_bin("vbic d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
+    TESTINSN_bin("vbic d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
+
+    printf("---- VORR ----\n");
+    TESTINSN_bin("vorr d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
+    TESTINSN_bin("vorr d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
+    TESTINSN_bin("vorr d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
+    TESTINSN_bin("vorr d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
+
+    printf("---- VORN ----\n");
+    TESTINSN_bin("vorn d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
+    TESTINSN_bin("vorn d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
+    TESTINSN_bin("vorn d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
+    TESTINSN_bin("vorn d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
+
+    printf("---- VEOR ----\n");
+    TESTINSN_bin("veor d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
+    TESTINSN_bin("veor d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
+    TESTINSN_bin("veor d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
+    TESTINSN_bin("veor d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
+    TESTINSN_bin("veor d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
+    TESTINSN_bin("veor d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
+    TESTINSN_bin("veor d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
+    TESTINSN_bin("veor d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
+
+    printf("---- VBSL ----\n");
+    TESTINSN_bin("vbsl d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
+    TESTINSN_bin("vbsl d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
+    TESTINSN_bin("vbsl d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
+    TESTINSN_bin("vbsl d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
+    TESTINSN_bin("vbsl d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
+    TESTINSN_bin("vbsl d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
+    TESTINSN_bin("vbsl d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
+    TESTINSN_bin("vbsl d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
+
+    printf("---- VBIT ----\n");
+    TESTINSN_bin("vbit d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
+    TESTINSN_bin("vbit d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
+    TESTINSN_bin("vbit d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
+    TESTINSN_bin("vbit d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
+    TESTINSN_bin("vbit d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
+    TESTINSN_bin("vbit d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
+    TESTINSN_bin("vbit d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
+    TESTINSN_bin("vbit d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
+
+    printf("---- VBIF ----\n");
+    TESTINSN_bin("vbif d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x77);
+    TESTINSN_bin("vbif d4, d6, d5", d4, d6, i8, 0xff, d5, i16, 0x57);
+    TESTINSN_bin("vbif d10, d11, d12", d10, d11, i8, 0xfe, d12, i8, 0xed);
+    TESTINSN_bin("vbif d15, d15, d15", d15, d15, i8, 0xff, d15, i8, 0xff);
+    TESTINSN_bin("vbif d0, d1, d2", d0, d1, i8, 0x24, d2, i16, 0x73);
+    TESTINSN_bin("vbif d7, d3, d0", d7, d3, i8, 0x24, d0, i16, 0xff);
+    TESTINSN_bin("vbif d4, d4, d4", d4, d4, i16, 0xff, d4, i16, 0xff);
+    TESTINSN_bin("vbif d2, d3, d15", d2, d3, i32, 0x24, d15, i32, 0x1f);
+
+    printf("---- VEXT ----\n");
+    TESTINSN_bin("vext.8 d0, d1, d2, #0", d0, d1, i8, 0x77, d2, i8, 0xff);
+    TESTINSN_bin("vext.8 d0, d1, d2, #1", d0, d1, i8, 0x77, d2, i8, 0xff);
+    TESTINSN_bin("vext.8 d0, d1, d2, #7", d0, d1, i8, 0x77, d2, i8, 0xff);
+    TESTINSN_bin("vext.8 d0, d1, d2, #6", d0, d1, i8, 0x77, d2, i8, 0xff);
+    TESTINSN_bin("vext.8 d10, d11, d12, #4", d10, d11, i8, 0x77, d12, i8, 0xff);
+    TESTINSN_bin("vext.8 d0, d5, d15, #5", d0, d5, i8, 0x77, d15, i8, 0xff);
+
+    printf("---- VHADD ----\n");
+    TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i8, 141, d2, i8, 121);
+    TESTINSN_bin("vhadd.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i8, 141, d2, i8, 121);
+    TESTINSN_bin("vhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VHSUB ----\n");
+    TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhsub.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhsub.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhsub.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhsub.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhsub.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vhsub.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vhsub.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VQADD ----\n");
+    TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqadd.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VQSUB ----\n");
+    TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqsub.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqsub.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqsub.s8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqsub.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqsub.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin_q("vqsub.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqsub.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VRHADD ----\n");
+    TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vrhadd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vrhadd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vrhadd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VCGT ----\n");
+    TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
+    TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
+    TESTINSN_bin("vcgt.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
+    TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 3, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 2, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcgt.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcgt.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VCGE ----\n");
+    TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
+    TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
+    TESTINSN_bin("vcge.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 140);
+    TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 3, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 2, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 3, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vcge.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 2, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vcge.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VSHL (register) ----\n");
+    TESTINSN_bin("vshl.s8 d0, d1, d2", d0, d1, i32, 24, d2, i32, 1);
+    TESTINSN_bin("vshl.s8 d8, d1, d12", d8, d1, i32, 24, d12, i32, 8);
+    TESTINSN_bin("vshl.s8 d10, d31, d7", d10, d31, i32, 24, d7, i32, 4);
+    TESTINSN_bin("vshl.s16 d3, d8, d11", d3, d8, i32, 14, d11, i32, 2);
+    TESTINSN_bin("vshl.s16 d5, d12, d14", d5, d12, i32, (1 << 30), d14, i32, 1);
+    TESTINSN_bin("vshl.s16 d15, d2, d1", d15, d2, i32, (1 << 30), d1, i32, 11); 
+    TESTINSN_bin("vshl.s32 d9, d12, d19", d9, d12, i32, (1 << 31) + 2, d19, i32, 2);
+    TESTINSN_bin("vshl.s32 d11, d22, d0", d11, d22, i32, -1, d0, i32, 12); 
+    TESTINSN_bin("vshl.s32 d5, d2, d3", d5, d2, i32, (1 << 30), d3, i32, 21); 
+    TESTINSN_bin("vshl.s64 d15, d12, d4", d15, d12, i32, 5, d4, i32, 20); 
+    TESTINSN_bin("vshl.s64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 4);
+    TESTINSN_bin("vshl.s64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 30); 
+    TESTINSN_bin("vshl.s64 d15, d2, d4", d15, d2, i32, 0xffabcd59, d4, i32, 0xabcdefab); 
+    TESTINSN_bin("vshl.s64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 0x400bb5);
+    TESTINSN_bin("vshl.s64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 0x30abcff); 
+    TESTINSN_bin("vshl.u8 d0, d1, d2", d0, d1, i32, 24, d2, i32, 1);
+    TESTINSN_bin("vshl.u8 d8, d1, d12", d8, d1, i32, 24, d12, i32, 8);
+    TESTINSN_bin("vshl.u8 d10, d11, d7", d10, d11, i32, 24, d7, i32, 4);
+    TESTINSN_bin("vshl.u16 d3, d8, d11", d3, d8, i32, 14, d11, i32, 2);
+    TESTINSN_bin("vshl.u16 d5, d12, d14", d5, d12, i32, (1 << 30), d14, i32, 1);
+    TESTINSN_bin("vshl.u16 d15, d2, d1", d15, d2, i32, (1 << 30), d1, i32, 11);
+    TESTINSN_bin("vshl.u32 d9, d12, d15", d9, d12, i32, (1 << 31) + 2, d15, i32, 2);
+    TESTINSN_bin("vshl.u32 d11, d2, d0", d11, d2, i32, -1, d0, i32, 12);
+    TESTINSN_bin("vshl.u32 d5, d2, d3", d5, d2, i32, (1 << 30), d3, i32, 21);
+    TESTINSN_bin("vshl.u64 d15, d12, d4", d15, d12, i32, 5, d4, i32, 20);
+    TESTINSN_bin("vshl.u64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 4);
+    TESTINSN_bin("vshl.u64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 30);
+    TESTINSN_bin("vshl.u64 d15, d2, d4", d15, d2, i32, 0xffabcd59, d4, i32, 0xabcdefab); 
+    TESTINSN_bin("vshl.u64 d8, d2, d4", d8, d2, i32, 15, d4, i32, 0x400bb5);
+    TESTINSN_bin("vshl.u64 d5, d12, d4", d5, d12, i32, (1 << 31) + 1, d4, i32, 0x30abcff); 
+
+    printf("---- VQSHL (register) ----\n");
+    TESTINSN_bin_q("vqshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
+    TESTINSN_bin_q("vqshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
+    TESTINSN_bin_q("vqshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
+    TESTINSN_bin_q("vqshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
+    TESTINSN_bin_q("vqshl.s64 d13, d14, d31", d13, d14, i32, -17, d31, i32, -26);
+    TESTINSN_bin_q("vqshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
+    TESTINSN_bin_q("vqshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
+    TESTINSN_bin_q("vqshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
+    TESTINSN_bin_q("vqshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
+    TESTINSN_bin_q("vqshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
+    TESTINSN_bin_q("vqshl.s32 d9, d30, d11", d9, d30, i32, (1 << 31) + 8, d11, i32, -1);
+    TESTINSN_bin_q("vqshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
+    TESTINSN_bin_q("vqshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
+    TESTINSN_bin_q("vqshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
+    TESTINSN_bin_q("vqshl.s16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1);
+    TESTINSN_bin_q("vqshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
+    TESTINSN_bin_q("vqshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
+    TESTINSN_bin_q("vqshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
+    TESTINSN_bin_q("vqshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
+    TESTINSN_bin_q("vqshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
+    TESTINSN_bin_q("vqshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
+    TESTINSN_bin_q("vqshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
+    TESTINSN_bin_q("vqshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
+    TESTINSN_bin_q("vqshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin_q("vqshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
+    TESTINSN_bin_q("vqshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
+    TESTINSN_bin_q("vqshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
+    TESTINSN_bin_q("vqshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
+    TESTINSN_bin_q("vqshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
+    TESTINSN_bin_q("vqshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
+    TESTINSN_bin_q("vqshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
+    TESTINSN_bin_q("vqshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
+    TESTINSN_bin_q("vqshl.u32 d12, d31, d13", d12, d31, i32, -120, d13, i32, -9);
+    TESTINSN_bin_q("vqshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
+    TESTINSN_bin_q("vqshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
+    TESTINSN_bin_q("vqshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
+    TESTINSN_bin_q("vqshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
+    TESTINSN_bin_q("vqshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
+    TESTINSN_bin_q("vqshl.u16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1);
+    TESTINSN_bin_q("vqshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
+    TESTINSN_bin_q("vqshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
+    TESTINSN_bin_q("vqshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
+    TESTINSN_bin_q("vqshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
+    TESTINSN_bin_q("vqshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
+    TESTINSN_bin_q("vqshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
+    TESTINSN_bin_q("vqshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
+    TESTINSN_bin_q("vqshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
+    TESTINSN_bin_q("vqshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VQSHL / VQSHLU (immediate) ----\n");
+    TESTINSN_un_q("vqshl.s64 d0, d1, #1", d0, d1, i32, 1);
+    TESTINSN_un_q("vqshl.s64 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #63", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #60", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #59", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #58", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #17", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #63", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #60", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.s64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.s32 d10, d11, #1", d10, d11, i32, 1);
+    TESTINSN_un_q("vqshl.s32 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #31", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #28", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #27", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #26", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #17", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #31", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #29", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.s32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.s16 d9, d8, #1", d9, d8, i32, 1);
+    TESTINSN_un_q("vqshl.s16 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshl.s16 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshl.s16 d9, d8, #15", d9, d8, i32, 16);
+    TESTINSN_un_q("vqshl.s16 d5, d4, #12", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s16 d5, d4, #11", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s16 d5, d4, #10", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s16 d5, d4, #4", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s16 d5, d4, #15", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.s16 d5, d4, #12", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.s16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.s8 d0, d1, #1", d0, d1, i32, 1);
+    TESTINSN_un_q("vqshl.s8 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshl.s8 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshl.s8 d5, d4, #7", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 d25, d4, #4", d25, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 d5, d4, #3", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 d5, d4, #2", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 d5, d4, #1", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.s8 d5, d4, #7", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.s8 d5, d4, #5", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.s8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.u64 d0, d1, #1", d0, d1, i32, 1);
+    TESTINSN_un_q("vqshl.u64 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #63", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #60", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #59", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #58", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #17", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #63", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #60", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.u64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.u32 d10, d11, #1", d10, d11, i32, 1);
+    TESTINSN_un_q("vqshl.u32 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #31", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #28", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #27", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #26", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #17", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #31", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #29", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.u32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.u16 d9, d8, #1", d9, d8, i32, 1);
+    TESTINSN_un_q("vqshl.u16 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshl.u16 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshl.u16 d9, d8, #15", d9, d8, i32, 16);
+    TESTINSN_un_q("vqshl.u16 d5, d4, #12", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u16 d5, d4, #11", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u16 d5, d4, #10", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u16 d5, d4, #4", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u16 d5, d4, #15", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.u16 d5, d4, #12", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.u16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshl.u8 d0, d1, #1", d0, d1, i32, 1);
+    TESTINSN_un_q("vqshl.u8 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #7", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #4", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #3", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #2", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #1", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #7", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #5", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshl.u8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshlu.s64 d0, d1, #1", d0, d1, i32, 1);
+    TESTINSN_un_q("vqshlu.s64 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #63", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #60", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #59", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #58", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #17", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #63", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #60", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshlu.s64 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshlu.s32 d10, d11, #1", d10, d11, i32, 1);
+    TESTINSN_un_q("vqshlu.s32 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshlu.s32 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshlu.s32 d5, d4, #31", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 d25, d24, #28", d25, d24, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 d5, d4, #27", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 d5, d4, #26", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 d5, d4, #17", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s32 d5, d24, #31", d5, d24, i32, -1);
+    TESTINSN_un_q("vqshlu.s32 d5, d4, #29", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshlu.s32 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshlu.s16 d9, d8, #1", d9, d8, i32, 1);
+    TESTINSN_un_q("vqshlu.s16 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshlu.s16 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshlu.s16 d9, d8, #15", d9, d8, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 d5, d4, #12", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 d5, d4, #11", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 d5, d4, #10", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 d5, d4, #4", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s16 d15, d14, #15", d15, d14, i32, -1);
+    TESTINSN_un_q("vqshlu.s16 d5, d4, #12", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshlu.s16 d5, d4, #7", d5, d4, i32, (1 << 31) + 2);
+    TESTINSN_un_q("vqshlu.s8 d0, d1, #1", d0, d1, i32, 1);
+    TESTINSN_un_q("vqshlu.s8 d31, d30, #1", d31, d30, i32, -127);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #0", d5, d4, i32, -127);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #7", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #4", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #3", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #2", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #1", d5, d4, i32, 16);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #7", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #5", d5, d4, i32, -1);
+    TESTINSN_un_q("vqshlu.s8 d5, d4, #2", d5, d4, i32, (1 << 31) + 2);
+
+    printf("---- VQRSHL (register) ----\n");
+    TESTINSN_bin_q("vqrshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
+    TESTINSN_bin_q("vqrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
+    TESTINSN_bin_q("vqrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
+    TESTINSN_bin_q("vqrshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
+    TESTINSN_bin_q("vqrshl.s64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
+    TESTINSN_bin_q("vqrshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
+    TESTINSN_bin_q("vqrshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
+    TESTINSN_bin_q("vqrshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
+    TESTINSN_bin_q("vqrshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
+    TESTINSN_bin_q("vqrshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
+    TESTINSN_bin_q("vqrshl.s32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
+    TESTINSN_bin_q("vqrshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
+    TESTINSN_bin_q("vqrshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
+    TESTINSN_bin_q("vqrshl.s16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1);
+    TESTINSN_bin_q("vqrshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
+    TESTINSN_bin_q("vqrshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
+    TESTINSN_bin_q("vqrshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
+    TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
+    TESTINSN_bin_q("vqrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
+    TESTINSN_bin_q("vqrshl.s32 d2, d7, d31", d2, d7, i32, -1, d31, i32, 0);
+    TESTINSN_bin_q("vqrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
+    TESTINSN_bin_q("vqrshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
+    TESTINSN_bin_q("vqrshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
+    TESTINSN_bin_q("vqrshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
+    TESTINSN_bin_q("vqrshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
+    TESTINSN_bin_q("vqrshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin_q("vqrshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
+    TESTINSN_bin_q("vqrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
+    TESTINSN_bin_q("vqrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
+    TESTINSN_bin_q("vqrshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
+    TESTINSN_bin_q("vqrshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
+    TESTINSN_bin_q("vqrshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
+    TESTINSN_bin_q("vqrshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
+    TESTINSN_bin_q("vqrshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
+    TESTINSN_bin_q("vqrshl.u32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
+    TESTINSN_bin_q("vqrshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
+    TESTINSN_bin_q("vqrshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
+    TESTINSN_bin_q("vqrshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
+    TESTINSN_bin_q("vqrshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
+    TESTINSN_bin_q("vqrshl.u16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1);
+    TESTINSN_bin_q("vqrshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
+    TESTINSN_bin_q("vqrshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
+    TESTINSN_bin_q("vqrshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
+    TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
+    TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin_q("vqrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
+    TESTINSN_bin_q("vqrshl.u16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
+    TESTINSN_bin_q("vqrshl.u32 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
+    TESTINSN_bin_q("vqrshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
+    TESTINSN_bin_q("vqrshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
+    TESTINSN_bin_q("vqrshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
+    TESTINSN_bin_q("vqrshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
+    TESTINSN_bin_q("vqrshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VRSHL (register) ----\n");
+    TESTINSN_bin("vrshl.s64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
+    TESTINSN_bin("vrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
+    TESTINSN_bin("vrshl.s64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
+    TESTINSN_bin("vrshl.s64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
+    TESTINSN_bin("vrshl.s64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
+    TESTINSN_bin("vrshl.s64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
+    TESTINSN_bin("vrshl.s32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
+    TESTINSN_bin("vrshl.s32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
+    TESTINSN_bin("vrshl.s32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
+    TESTINSN_bin("vrshl.s32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
+    TESTINSN_bin("vrshl.s32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
+    TESTINSN_bin("vrshl.s32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
+    TESTINSN_bin("vrshl.s16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
+    TESTINSN_bin("vrshl.s16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
+    TESTINSN_bin("vrshl.s16 d0, d11, d2", d0, d11, i32, (1 << 31) + 256, d2, i32, -1);
+    TESTINSN_bin("vrshl.s16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
+    TESTINSN_bin("vrshl.s16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
+    TESTINSN_bin("vrshl.s16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
+    TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin("vrshl.s8 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1);
+    TESTINSN_bin("vrshl.s16 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1);
+    TESTINSN_bin("vrshl.s32 d2, d7, d31", d2, d7, i32, -1, d31, i32, -1);
+    TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, -2, d11, i32, -1);
+    TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
+    TESTINSN_bin("vrshl.s16 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
+    TESTINSN_bin("vrshl.s32 d2, d7, d11", d2, d7, i32, -1, d11, i32, 0);
+    TESTINSN_bin("vrshl.s8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
+    TESTINSN_bin("vrshl.s8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
+    TESTINSN_bin("vrshl.s8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
+    TESTINSN_bin("vrshl.s8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
+    TESTINSN_bin("vrshl.s8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
+    TESTINSN_bin("vrshl.s8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vrshl.u64 d0, d1, d2", d0, d1, i32, 1, d2, i32, 1);
+    TESTINSN_bin("vrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, 1);
+    TESTINSN_bin("vrshl.u64 d3, d4, d5", d3, d4, i32, -127, d5, i32, -3);
+    TESTINSN_bin("vrshl.u64 d0, d1, d2", d0, d1, i32, 16, d2, i32, 14);
+    TESTINSN_bin("vrshl.u64 d13, d14, d15", d13, d14, i32, -17, d15, i32, -26);
+    TESTINSN_bin("vrshl.u64 d7, d8, d2", d7, d8, i32, 24, d2, i32, -60);
+    TESTINSN_bin("vrshl.u32 d3, d4, d15", d3, d4, i32, 127, d15, i32, -30);
+    TESTINSN_bin("vrshl.u32 d2, d8, d4", d2, d8, i32, -11, d4, i32, -4);
+    TESTINSN_bin("vrshl.u32 d12, d11, d13", d12, d11, i32, -120, d13, i32, -9);
+    TESTINSN_bin("vrshl.u32 d0, d1, d2", d0, d1, i32, 34, d2, i32, -7);
+    TESTINSN_bin("vrshl.u32 d9, d10, d11", d9, d10, i32, (1 << 31) + 8, d11, i32, -1);
+    TESTINSN_bin("vrshl.u32 d13, d3, d5", d13, d3, i32, (1 << 27), d5, i32, 3);
+    TESTINSN_bin("vrshl.u16 d11, d10, d2", d11, d10, i32, (1 << 31), d2, i32, -31);
+    TESTINSN_bin("vrshl.u16 d3, d14, d7", d3, d14, i32, (1 << 31), d7, i32, -3);
+    TESTINSN_bin("vrshl.u16 d0, d31, d2", d0, d31, i32, (1 << 31) + 256, d2, i32, -1);
+    TESTINSN_bin("vrshl.u16 d1, d2, d3", d1, d2, i32, (1 << 31) + 256, d3, i32, -31);
+    TESTINSN_bin("vrshl.u16 d3, d4, d5", d3, d4, i32, (1 << 31) + (1 << 29), d5, i32, -13);
+    TESTINSN_bin("vrshl.u16 d0, d15, d2", d0, d15, i32, 1, d2, i32, 30);
+    TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, 40);
+    TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
+    TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin("vrshl.u16 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin("vrshl.u32 d2, d7, d11", d2, d7, i32, 0xf, d11, i32, -1);
+    TESTINSN_bin("vrshl.u8 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
+    TESTINSN_bin("vrshl.u16 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
+    TESTINSN_bin("vrshl.u32 d2, d7, d11", d2, d7, i32, -1, d11, i32, -1);
+    TESTINSN_bin("vrshl.u8 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1);
+    TESTINSN_bin("vrshl.u16 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1);
+    TESTINSN_bin("vrshl.u32 d2, d7, d31", d2, d7, i32, -2, d31, i32, -1);
+    TESTINSN_bin("vrshl.u8 d13, d1, d2", d13, d1, i32, -4, d2, i32, 30);
+    TESTINSN_bin("vrshl.u8 d3, d7, d5", d3, d7, i32, (1 << 31) + 11, d5, i32, 3);
+    TESTINSN_bin("vrshl.u8 d10, d11, d12", d10, d11, i32, (1 << 16), d12, i32, 16);
+    TESTINSN_bin("vrshl.u8 d6, d7, d8", d6, d7, i32, (1 << 30), d8, i32, 2);
+    TESTINSN_bin("vrshl.u8 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VMAX (integer) ----\n");
+    TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121);
+    TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vmax.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120);
+    TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmax.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);  
+
+    printf("---- VMIN (integer) ----\n");
+    TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121);
+    TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vmin.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120);
+    TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3); 
+    TESTINSN_bin("vmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmin.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VABD ----\n");
+    TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, -120);
+    TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabd.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200);
+    TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, -140, d2, i32, 120);
+    TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vabd.u8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200);
+    TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vabd.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vabd.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VABA ----\n");
+    TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vaba.s8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200);
+    TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vaba.u8 d5, d7, d5", d5, d7, i32, -255, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, -200);
+    TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vaba.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vaba.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VTST ----\n");
+    TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vtst.32 d3, d4, d5", d3, d4, i32, 140, d5, i32, 120);
+    TESTINSN_bin("vtst.16 d6, d7, d8", d6, d7, i32, 120, d8, i32, 120);
+    TESTINSN_bin("vtst.8 d9, d10, d12", d9, d10, i32, 140, d12, i32, 120);
+    TESTINSN_bin("vtst.8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vtst.16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1); 
+    TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vtst.8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, 2); 
+    TESTINSN_bin("vtst.16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1); 
+    TESTINSN_bin("vtst.32 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vtst.32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VCEQ ----\n");
+    TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vceq.i32 d3, d4, d5", d3, d4, i32, 140, d5, i32, 120);
+    TESTINSN_bin("vceq.i16 d6, d7, d8", d6, d7, i32, 120, d8, i32, 120);
+    TESTINSN_bin("vceq.i8 d9, d10, d12", d9, d10, i32, 140, d12, i32, 120);
+    TESTINSN_bin("vceq.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vceq.i16 d0, d1, d2", d0, d1, i32, (1 << 14) + 1, d2, i32, (1 << 14) + 1); 
+    TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vceq.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, 2); 
+    TESTINSN_bin("vceq.i16 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 14) + 1); 
+    TESTINSN_bin("vceq.i32 d0, d1, d2", d0, d1, i32, 1, d2, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vceq.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VMLA ----\n");
+    TESTINSN_bin("vmla.i32 d0, d1, d2", d0, d1, i32, -24, d2, i32, 120);
+    TESTINSN_bin("vmla.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, 120);
+    TESTINSN_bin("vmla.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmla.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, -120);
+    TESTINSN_bin("vmla.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); 
+    TESTINSN_bin("vmla.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); 
+    TESTINSN_bin("vmla.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmla.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); 
+    TESTINSN_bin("vmla.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); 
+    TESTINSN_bin("vmla.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmla.i32 d10, d11, d15", d10, d11, i32, 24, d15, i32, -120);
+
+    printf("---- VMLS ----\n");
+    TESTINSN_bin("vmls.i32 d0, d1, d2", d0, d1, i32, -24, d2, i32, 120);
+    TESTINSN_bin("vmls.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin("vmls.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmls.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vmls.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); 
+    TESTINSN_bin("vmls.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2); 
+    TESTINSN_bin("vmls.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmls.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2); 
+    TESTINSN_bin("vmls.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2); 
+    TESTINSN_bin("vmls.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2); 
+    TESTINSN_bin("vmls.i32 d10, d11, d15", d10, d11, i32, -24, d15, i32, 120);
+
+    printf("---- VMUL ----\n");
+    TESTINSN_bin("vmul.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vmul.i32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin("vmul.i16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin("vmul.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vmul.i8 d10, d11, d12", d10, d11, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2);
+    TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmul.i8 d10, d11, d12", d10, d11, i32, (1 << 25) + 0xfeb2, d12, i32, (1 << 13) + 0xdf);
+    TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin("vmul.i8 d10, d13, d12", d10, d13, i32, (1 << 5) + 1, d12, i32, (1 << 3) + 2);
+    TESTINSN_bin("vmul.i16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmul.i32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 3, q2, i32, 3);
+    TESTINSN_bin("vmul.p8 q0, q1, q2", q0, q1, i32, 12, q2, i8, 0x0f);
+
+    printf("---- VMUL (by scalar) ----\n");
+    TESTINSN_bin("vmul.i32 d0, d1, d4[0]", d0, d1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmul.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120);
+    TESTINSN_bin("vmul.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmul.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmul.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmul.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmul.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VMLA (by scalar) ----\n");
+    TESTINSN_bin("vmla.i32 d0, d1, d4[0]", d0, d1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmla.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120);
+    TESTINSN_bin("vmla.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmla.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmla.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmla.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmla.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VMLS (by scalar) ----\n");
+    TESTINSN_bin("vmls.i32 d0, d1, d4[0]", q0, q1, i32, 24, d4, i32, 120);
+    TESTINSN_bin("vmls.i32 d31, d8, d7[1]", d31, d8, i32, 140, d7, i32, -120);
+    TESTINSN_bin("vmls.i16 d30, d9, d7[3]", d30, d9, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin("vmls.i16 d4, d5, d6[2]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmls.i32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin("vmls.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmls.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin("vmls.i16 d4, d5, d6[0]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin("vmls.i32 d7, d8, d1[1]", d7, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+
+    printf("---- VRSHR ----\n");
+    TESTINSN_un("vrshr.s8 d0, d1, #0", d0, d1, i32, -1);
+    TESTINSN_un("vrshr.s8 d0, d1, #1", d0, d1, i32, -1);
+    TESTINSN_un("vrshr.s16 d3, d4, #2", d3, d4, i32, -0x7c);
+    TESTINSN_un("vrshr.s32 d2, d5, #31", d2, d5, i32, -1);
+    TESTINSN_un("vrshr.s8 d6, d7, #7", d6, d7, i32, 0xffff);
+    TESTINSN_un("vrshr.s16 d8, d9, #12", d8, d9, i32, -10);
+    TESTINSN_un("vrshr.s32 d10, d11, #5", d10, d11, i32, 10234);
+    TESTINSN_un("vrshr.u8 d12, d13, #1", d12, d13, i32, -1);
+    TESTINSN_un("vrshr.u16 d14, d15, #11", d14, d15, i32, -1);
+    TESTINSN_un("vrshr.u32 d10, d11, #9", d10, d11, i32, 1000);
+    TESTINSN_un("vrshr.u8 d7, d13, #7", d7, d13, i32, -1);
+    TESTINSN_un("vrshr.u16 d8, d1, #5", d8, d1, i32, 0xabcf);
+    TESTINSN_un("vrshr.u32 d12, d3, #15", d12, d3, i32, -0x1b0);
+    TESTINSN_un("vrshr.u64 d0, d1, #42", d0, d1, i32, -1);
+    TESTINSN_un("vrshr.s64 d6, d7, #12", d6, d7, i32, 0xfac);
+    TESTINSN_un("vrshr.u64 d8, d4, #9", d8, d4, i32, 13560);
+    TESTINSN_un("vrshr.s64 d9, d12, #11", d9, d12, i32, 98710);
+
+    printf("---- VRSRA ----\n");
+    TESTINSN_un("vrsra.s8 d0, d1, #1", d0, d1, i32, -1);
+    TESTINSN_un("vrsra.s16 d3, d4, #2", d3, d4, i32, -0x7c);
+    TESTINSN_un("vrsra.s32 d2, d5, #31", d2, d5, i32, -1);
+    TESTINSN_un("vrsra.s8 d6, d7, #7", d6, d7, i32, 0xffff);
+    TESTINSN_un("vrsra.s16 d8, d9, #12", d8, d9, i32, -10);
+    TESTINSN_un("vrsra.s32 d10, d11, #5", d10, d11, i32, 10234);
+    TESTINSN_un("vrsra.u8 d12, d13, #1", d12, d13, i32, -1);
+    TESTINSN_un("vrsra.u16 d14, d15, #11", d14, d15, i32, -1);
+    TESTINSN_un("vrsra.u32 d10, d11, #9", d10, d11, i32, 1000);
+    TESTINSN_un("vrsra.u8 d7, d13, #7", d7, d13, i32, -1);
+    TESTINSN_un("vrsra.u16 d8, d1, #5", d8, d1, i32, 0xabcf);
+    TESTINSN_un("vrsra.u32 d12, d3, #15", d12, d3, i32, -0x1b0);
+    TESTINSN_un("vrsra.u64 d0, d1, #42", d0, d1, i32, -1);
+    TESTINSN_un("vrsra.s64 d6, d7, #12", d6, d7, i32, 0xfac);
+    TESTINSN_un("vrsra.u64 d8, d4, #9", d8, d4, i32, 13560);
+    TESTINSN_un("vrsra.s64 d9, d12, #11", d9, d12, i32, 98710);
+
+    printf("---- VSHR ----\n");
+    TESTINSN_un("vshr.s8 d0, d1, #0", d0, d1, i32, -1);
+    TESTINSN_un("vshr.s8 d0, d1, #1", d0, d1, i32, -1);
+    TESTINSN_un("vshr.s16 d3, d4, #2", d3, d4, i32, -0x7c);
+    TESTINSN_un("vshr.s32 d2, d5, #31", d2, d5, i32, -1);
+    TESTINSN_un("vshr.s8 d6, d7, #7", d6, d7, i32, 0xffff);
+    TESTINSN_un("vshr.s16 d8, d9, #12", d8, d9, i32, -10);
+    TESTINSN_un("vshr.s32 d10, d11, #5", d10, d11, i32, 10234);
+    TESTINSN_un("vshr.u8 d12, d13, #1", d12, d13, i32, -1);
+    TESTINSN_un("vshr.u16 d14, d15, #11", d14, d15, i32, -1);
+    TESTINSN_un("vshr.u32 d10, d11, #9", d10, d11, i32, 1000);
+    TESTINSN_un("vshr.u8 d7, d13, #7", d7, d13, i32, -1);
+    TESTINSN_un("vshr.u16 d8, d1, #5", d8, d1, i32, 0xabcf);
+    TESTINSN_un("vshr.u32 d12, d3, #15", d12, d3, i32, -0x1b0);
+    TESTINSN_un("vshr.u64 d0, d1, #42", d0, d1, i32, -1);
+    TESTINSN_un("vshr.s64 d6, d7, #12", d6, d7, i32, 0xfac);
+    TESTINSN_un("vshr.u64 d8, d4, #9", d8, d4, i32, 13560);
+    TESTINSN_un("vshr.s64 d9, d12, #11", d9, d12, i32, 98710);
+
+    printf("---- VSRA ----\n");
+    TESTINSN_un("vsra.s8 d0, d1, #1", d0, d1, i32, -1);
+    TESTINSN_un("vsra.s16 d3, d4, #2", d3, d4, i32, -0x7c);
+    TESTINSN_un("vsra.s32 d2, d5, #31", d2, d5, i32, -1);
+    TESTINSN_un("vsra.s8 d6, d7, #7", d6, d7, i32, 0xffff);
+    TESTINSN_un("vsra.s16 d8, d9, #12", d8, d9, i32, -10);
+    TESTINSN_un("vsra.s32 d10, d11, #5", d10, d11, i32, 10234);
+    TESTINSN_un("vsra.u8 d12, d13, #1", d12, d13, i32, -1);
+    TESTINSN_un("vsra.u16 d14, d15, #11", d14, d15, i32, -1);
+    TESTINSN_un("vsra.u32 d10, d11, #9", d10, d11, i32, 1000);
+    TESTINSN_un("vsra.u8 d7, d13, #7", d7, d13, i32, -1);
+    TESTINSN_un("vsra.u16 d8, d1, #5", d8, d1, i32, 0xabcf);
+    TESTINSN_un("vsra.u32 d12, d3, #15", d12, d3, i32, -0x1b0);
+    TESTINSN_un("vsra.u64 d0, d1, #42", d0, d1, i32, -1);
+    TESTINSN_un("vsra.s64 d6, d7, #12", d6, d7, i32, 0xfac);
+    TESTINSN_un("vsra.u64 d8, d4, #9", d8, d4, i32, 13560);
+    TESTINSN_un("vsra.s64 d9, d12, #11", d9, d12, i32, 98710);
+
+    printf("---- VSRI ----\n");
+    TESTINSN_un("vsri.16 d0, d1, #1", d0, d1, i32, -1);
+    TESTINSN_un("vsri.16 d3, d4, #2", d3, d4, i32, -0x7c);
+    TESTINSN_un("vsri.32 d2, d5, #31", d2, d5, i32, -1);
+    TESTINSN_un("vsri.8 d6, d7, #7", d6, d7, i32, 0xffff);
+    TESTINSN_un("vsri.16 d8, d9, #12", d8, d9, i32, -10);
+    TESTINSN_un("vsri.32 d10, d11, #5", d10, d11, i32, 10234);
+    TESTINSN_un("vsri.8 d12, d13, #1", d12, d13, i32, -1);
+    TESTINSN_un("vsri.16 d14, d15, #11", d14, d15, i32, -1);
+    TESTINSN_un("vsri.32 d10, d11, #9", d10, d11, i32, 1000);
+    TESTINSN_un("vsri.8 d7, d13, #7", d7, d13, i32, -1);
+    TESTINSN_un("vsri.16 d8, d1, #5", d8, d1, i32, 0xabcf);
+    TESTINSN_un("vsri.32 d12, d3, #15", d12, d3, i32, -0x1b0);
+    TESTINSN_un("vsri.64 d0, d1, #42", d0, d1, i32, -1);
+    TESTINSN_un("vsri.64 d6, d7, #12", d6, d7, i32, 0xfac);
+    TESTINSN_un("vsri.64 d8, d4, #9", d8, d4, i32, 13560);
+    TESTINSN_un("vsri.64 d9, d12, #11", d9, d12, i32, 98710);
+
+    printf("---- VMOV (ARM core register to scalar) ----\n");
+    TESTINSN_core_to_scalar("vmov.32 d0[0], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.32 d1[1], r3", d1, r3, 12);
+    TESTINSN_core_to_scalar("vmov.16 d0[0], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.16 d2[2], r6", d2, r6, 14);
+    TESTINSN_core_to_scalar("vmov.16 d3[3], r1", d3, r1, 17);
+    TESTINSN_core_to_scalar("vmov.8 d0[0], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.8 d0[1], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.8 d0[2], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.8 d0[3], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.8 d0[4], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.8 d0[5], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.8 d0[6], r5", d0, r5, 13);
+    TESTINSN_core_to_scalar("vmov.8 d31[7], r5", d31, r5, 13);
+
+    printf("---- VMOV (scalar toARM core register) ----\n");
+    TESTINSN_scalar_to_core("vmov.32 r5, d0[0]", r5, d0, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.32 r6, d5[1]", r6, d5, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u16 r5, d31[0]", r5, d31, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u16 r5, d30[1]", r5, d30, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u16 r5, d31[2]", r5, d31, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u16 r5, d31[3]", r5, d31, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u8 r2, d4[0]", r2, d4, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u8 r2, d4[1]", r2, d4, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u8 r2, d4[2]", r2, d4, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u8 r2, d4[3]", r2, d4, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u8 r2, d4[4]", r2, d4, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u8 r2, d4[5]", r2, d4, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u8 r2, d4[6]", r2, d4, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.u8 r2, d4[7]", r2, d4, i32, 0x11223344);
+    TESTINSN_scalar_to_core("vmov.s16 r5, d31[0]", r5, d31, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s16 r5, d30[1]", r5, d30, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s16 r5, d31[2]", r5, d31, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s16 r5, d31[3]", r5, d31, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s8 r2, d4[0]", r2, d4, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s8 r2, d4[1]", r2, d4, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s8 r2, d4[2]", r2, d4, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s8 r2, d4[3]", r2, d4, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s8 r2, d4[4]", r2, d4, i8, 128);
+    TESTINSN_scalar_to_core("vmov.s8 r2, d4[5]", r2, d4, i8, 130);
+    TESTINSN_scalar_to_core("vmov.s8 r2, d4[6]", r2, d4, i8, 129);
+    TESTINSN_scalar_to_core("vmov.s8 r2, d4[7]", r2, d4, i8, 131);
+
+    printf("---- VLD1 (multiple single elements) ----\n");
+    TESTINSN_VLDn("vld1.8 {d0}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.16 {d0}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.32 {d0}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.64 {d0}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.8 {d9}", d9, d9, d9, d9);
+    TESTINSN_VLDn("vld1.16 {d17}", d17, d17, d17, d17);
+    TESTINSN_VLDn("vld1.32 {d31}", d31, d31, d31, d31);
+    TESTINSN_VLDn("vld1.64 {d14}", d14, d14, d14, d14);
+    TESTINSN_VLDn("vld1.8 {d0-d1}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld1.16 {d0-d1}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld1.32 {d5-d6}", d5, d6, d5, d6);
+    TESTINSN_VLDn("vld1.64 {d30-d31}", d30, d31, d30, d31);
+    TESTINSN_VLDn("vld1.8 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VLDn("vld1.16 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VLDn("vld1.32 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VLDn("vld1.64 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VLDn("vld1.8 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld1.16 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld1.32 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld1.64 {d0-d3}", d0, d1, d2, d3);
+
+    printf("---- VLD1 (single element to one lane) ----\n");
+    TESTINSN_VLDn("vld1.32 {d0[0]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.32 {d0[1]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.16 {d1[0]}", d1, d1, d1, d1);
+    TESTINSN_VLDn("vld1.16 {d1[1]}", d1, d1, d1, d1);
+    TESTINSN_VLDn("vld1.16 {d1[2]}", d1, d1, d1, d1);
+    TESTINSN_VLDn("vld1.16 {d1[3]}", d1, d1, d1, d1);
+    TESTINSN_VLDn("vld1.8 {d0[7]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.8 {d1[6]}", d1, d1, d1, d1);
+    TESTINSN_VLDn("vld1.8 {d0[5]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.8 {d0[4]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.8 {d20[3]}", d20, d20, d20, d20);
+    TESTINSN_VLDn("vld1.8 {d0[2]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.8 {d17[1]}", d17, d17, d17, d17);
+    TESTINSN_VLDn("vld1.8 {d30[0]}", d30, d30, d30, d30);
+
+    printf("---- VLD1 (single element to all lanes) ----\n");
+    TESTINSN_VLDn("vld1.8 {d0[]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.16 {d0[]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.32 {d0[]}", d0, d0, d0, d0);
+    TESTINSN_VLDn("vld1.8 {d9[]}", d9, d9, d9, d9);
+    TESTINSN_VLDn("vld1.16 {d17[]}", d17, d17, d17, d17);
+    TESTINSN_VLDn("vld1.32 {d31[]}", d31, d31, d31, d31);
+    TESTINSN_VLDn("vld1.8 {d0[],d1[]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld1.16 {d0[],d1[]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld1.32 {d5[],d6[]}", d5, d6, d5, d6);
+
+    printf("---- VLD2 (multiple 2-elements) ----\n");
+    TESTINSN_VLDn("vld2.8 {d30-d31}", d30, d31, d30, d31);
+    TESTINSN_VLDn("vld2.16 {d0-d1}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.32 {d0-d1}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.8 {d10,d12}", d10, d12, d10, d12);
+    TESTINSN_VLDn("vld2.16 {d20,d22}", d20, d22, d20, d22);
+    TESTINSN_VLDn("vld2.32 {d0,d2}", d0, d2, d0, d2);
+    TESTINSN_VLDn("vld2.8 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld2.16 {d20-d23}", d20, d21, d22, d23);
+    TESTINSN_VLDn("vld2.32 {d0-d3}", d0, d1, d2, d3);
+
+    printf("---- VLD2 (single 2-element structure to one lane) ----\n");
+    TESTINSN_VLDn("vld2.32 {d0[0],d1[0]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.32 {d0[1],d1[1]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.32 {d0[0],d2[0]}", d0, d2, d0, d2);
+    TESTINSN_VLDn("vld2.32 {d0[1],d2[1]}", d0, d2, d0, d2);
+    TESTINSN_VLDn("vld2.16 {d1[0],d2[0]}", d1, d2, d1, d2);
+    TESTINSN_VLDn("vld2.16 {d1[1],d2[1]}", d1, d2, d1, d2);
+    TESTINSN_VLDn("vld2.16 {d1[2],d2[2]}", d1, d2, d1, d2);
+    TESTINSN_VLDn("vld2.16 {d1[3],d2[3]}", d1, d2, d1, d2);
+    TESTINSN_VLDn("vld2.16 {d1[0],d3[0]}", d1, d3, d1, d3);
+    TESTINSN_VLDn("vld2.16 {d1[1],d3[1]}", d1, d3, d1, d3);
+    TESTINSN_VLDn("vld2.16 {d1[2],d3[2]}", d1, d3, d1, d3);
+    TESTINSN_VLDn("vld2.16 {d1[3],d3[3]}", d1, d3, d1, d3);
+    TESTINSN_VLDn("vld2.8 {d0[7],d1[7]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.8 {d1[6],d2[6]}", d1, d2, d1, d2);
+    TESTINSN_VLDn("vld2.8 {d0[5],d1[5]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.8 {d0[4],d1[4]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.8 {d20[3],d21[3]}", d20, d21, d20, d21);
+    TESTINSN_VLDn("vld2.8 {d0[2],d1[2]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.8 {d17[1],d18[1]}", d17, d18, d17, d18);
+    TESTINSN_VLDn("vld2.8 {d30[0],d31[0]}", d30, d31, d30, d31);
+
+    printf("---- VLD2 (2-elements to all lanes) ----\n");
+    TESTINSN_VLDn("vld2.8 {d0[],d1[]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.16 {d0[],d1[]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.32 {d0[],d1[]}", d0, d1, d0, d1);
+    TESTINSN_VLDn("vld2.8 {d9[],d11[]}", d9, d11, d9, d11);
+    TESTINSN_VLDn("vld2.16 {d17[],d18[]}", d17, d18, d17, d18);
+    TESTINSN_VLDn("vld2.32 {d30[],d31[]}", d30, d31, d30, d31);
+    TESTINSN_VLDn("vld2.8 {d0[],d2[]}", d0, d2, d0, d2);
+    TESTINSN_VLDn("vld2.16 {d0[],d2[]}", d0, d2, d0, d2);
+    TESTINSN_VLDn("vld2.32 {d5[],d7[]}", d5, d7, d5, d7);
+
+    printf("---- VLD3 (multiple 3-elements) ----\n");
+    TESTINSN_VLDn("vld3.8 {d20-d22}", d20, d21, d22, d20);
+    TESTINSN_VLDn("vld3.16 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VLDn("vld3.32 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VLDn("vld3.8 {d0,d2,d4}", d0, d2, d4, d0);
+    TESTINSN_VLDn("vld3.16 {d20,d22,d24}", d20, d22, d24, d20);
+    TESTINSN_VLDn("vld3.32 {d0,d2,d4}", d0, d2, d4, d0);
+
+    printf("---- VLD3 (single 3-element structure to one lane) ----\n");
+    TESTINSN_VLDn("vld3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2);
+    TESTINSN_VLDn("vld3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2);
+    TESTINSN_VLDn("vld3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2);
+    TESTINSN_VLDn("vld3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2);
+    TESTINSN_VLDn("vld3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2);
+    TESTINSN_VLDn("vld3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2);
+    TESTINSN_VLDn("vld3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5);
+    TESTINSN_VLDn("vld3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5);
+    TESTINSN_VLDn("vld3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5);
+    TESTINSN_VLDn("vld3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5);
+    TESTINSN_VLDn("vld3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2);
+    TESTINSN_VLDn("vld3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21);
+    TESTINSN_VLDn("vld3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18);
+    TESTINSN_VLDn("vld3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31);
+
+    printf("---- VLD3 (3-elements to all lanes) ----\n");
+    TESTINSN_VLDn("vld3.8 {d0[],d1[],d2[]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.16 {d0[],d1[],d2[]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.32 {d0[],d1[],d2[]}", d0, d1, d2, d1);
+    TESTINSN_VLDn("vld3.8 {d9[],d11[],d13[]}", d9, d11, d13, d11);
+    TESTINSN_VLDn("vld3.16 {d17[],d18[],d19[]}", d17, d18, d19, d18);
+    TESTINSN_VLDn("vld3.32 {d29[],d30[],d31[]}", d29, d30, d30, d31);
+    TESTINSN_VLDn("vld3.8 {d0[],d2[],d4[]}", d0, d2, d4, d2);
+    TESTINSN_VLDn("vld3.16 {d0[],d2[],d4[]}", d0, d2, d4, d2);
+    TESTINSN_VLDn("vld3.32 {d5[],d7[],d9[]}", d5, d7, d9, d7);
+
+    printf("---- VLD4 (multiple 3-elements) ----\n");
+    TESTINSN_VLDn("vld4.8 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.16 {d20-d23}", d20, d21, d22, d23);
+    TESTINSN_VLDn("vld4.32 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.8 {d0,d2,d4,d6}", d0, d2, d4, d6);
+    TESTINSN_VLDn("vld4.16 {d1,d3,d5,d7}", d1, d3, d5, d7);
+    TESTINSN_VLDn("vld4.32 {d20,d22,d24,d26}", d20, d22, d24, d26);
+
+    printf("---- VLD4 (single 4-element structure to one lane) ----\n");
+    TESTINSN_VLDn("vld4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4);
+    TESTINSN_VLDn("vld4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6);
+    TESTINSN_VLDn("vld4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6);
+    TESTINSN_VLDn("vld4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4);
+    TESTINSN_VLDn("vld4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4);
+    TESTINSN_VLDn("vld4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4);
+    TESTINSN_VLDn("vld4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4);
+    TESTINSN_VLDn("vld4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7);
+    TESTINSN_VLDn("vld4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7);
+    TESTINSN_VLDn("vld4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7);
+    TESTINSN_VLDn("vld4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7);
+    TESTINSN_VLDn("vld4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4);
+    TESTINSN_VLDn("vld4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23);
+    TESTINSN_VLDn("vld4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20);
+    TESTINSN_VLDn("vld4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31);
+
+    printf("---- VLD4 (4-elements to all lanes) ----\n");
+    TESTINSN_VLDn("vld4.8 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.16 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.32 {d0[],d1[],d2[],d3[]}", d0, d1, d2, d3);
+    TESTINSN_VLDn("vld4.8 {d9[],d11[],d13[],d15[]}", d9, d11, d13, d15);
+    TESTINSN_VLDn("vld4.16 {d17[],d18[],d19[],d20[]}", d17, d18, d19, d20);
+    TESTINSN_VLDn("vld4.32 {d28[],d29[],d30[],d31[]}", d28, d29, d30, d31);
+    TESTINSN_VLDn("vld4.8 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6);
+    TESTINSN_VLDn("vld4.16 {d0[],d2[],d4[],d6[]}", d0, d2, d4, d6);
+    TESTINSN_VLDn("vld4.32 {d5[],d7[],d9[],d11[]}", d5, d7, d9, d11);
+
+    printf("---- VST1 (multiple single elements) ----\n");
+    TESTINSN_VSTn("vst1.8 {d0}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.16 {d0}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.32 {d0}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.64 {d0}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.8 {d9}", d9, d9, d9, d9);
+    TESTINSN_VSTn("vst1.16 {d17}", d17, d17, d17, d17);
+    TESTINSN_VSTn("vst1.32 {d31}", d31, d31, d31, d31);
+    TESTINSN_VSTn("vst1.64 {d14}", d14, d14, d14, d14);
+    TESTINSN_VSTn("vst1.8 {d0-d1}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst1.16 {d0-d1}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst1.32 {d5-d6}", d5, d6, d5, d6);
+    TESTINSN_VSTn("vst1.64 {d30-d31}", d30, d31, d30, d31);
+    TESTINSN_VSTn("vst1.8 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VSTn("vst1.16 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VSTn("vst1.32 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VSTn("vst1.64 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VSTn("vst1.8 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst1.16 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst1.32 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst1.64 {d0-d3}", d0, d1, d2, d3);
+
+    printf("---- VST1 (single element from one lane) ----\n");
+    TESTINSN_VSTn("vst1.32 {d0[0]}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.32 {d0[1]}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.16 {d1[0]}", d1, d1, d1, d1);
+    TESTINSN_VSTn("vst1.16 {d1[1]}", d1, d1, d1, d1);
+    TESTINSN_VSTn("vst1.16 {d1[2]}", d1, d1, d1, d1);
+    TESTINSN_VSTn("vst1.16 {d1[3]}", d1, d1, d1, d1);
+    TESTINSN_VSTn("vst1.8 {d0[7]}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.8 {d1[6]}", d1, d1, d1, d1);
+    TESTINSN_VSTn("vst1.8 {d0[5]}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.8 {d0[4]}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.8 {d20[3]}", d20, d20, d20, d20);
+    TESTINSN_VSTn("vst1.8 {d0[2]}", d0, d0, d0, d0);
+    TESTINSN_VSTn("vst1.8 {d17[1]}", d17, d17, d17, d17);
+    TESTINSN_VSTn("vst1.8 {d30[0]}", d30, d30, d30, d30);
+
+    printf("---- VST2 (multiple 2-elements) ----\n");
+    TESTINSN_VSTn("vst2.8 {d30-d31}", d30, d31, d30, d31);
+    TESTINSN_VSTn("vst2.16 {d0-d1}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst2.32 {d0-d1}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst2.8 {d10,d12}", d10, d12, d10, d12);
+    TESTINSN_VSTn("vst2.16 {d20,d22}", d20, d22, d20, d22);
+    TESTINSN_VSTn("vst2.32 {d0,d2}", d0, d2, d0, d2);
+    TESTINSN_VSTn("vst2.8 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst2.16 {d20-d23}", d20, d21, d22, d23);
+    TESTINSN_VSTn("vst2.32 {d0-d3}", d0, d1, d2, d3);
+
+    printf("---- VST2 (single 2-element structure from one lane) ----\n");
+    TESTINSN_VSTn("vst2.32 {d0[0],d1[0]}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst2.32 {d0[1],d1[1]}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst2.32 {d0[0],d2[0]}", d0, d2, d0, d2);
+    TESTINSN_VSTn("vst2.32 {d0[1],d2[1]}", d0, d2, d0, d2);
+    TESTINSN_VSTn("vst2.16 {d1[0],d2[0]}", d1, d2, d1, d2);
+    TESTINSN_VSTn("vst2.16 {d1[1],d2[1]}", d1, d2, d1, d2);
+    TESTINSN_VSTn("vst2.16 {d1[2],d2[2]}", d1, d2, d1, d2);
+    TESTINSN_VSTn("vst2.16 {d1[3],d2[3]}", d1, d2, d1, d2);
+    TESTINSN_VSTn("vst2.16 {d1[0],d3[0]}", d1, d3, d1, d3);
+    TESTINSN_VSTn("vst2.16 {d1[1],d3[1]}", d1, d3, d1, d3);
+    TESTINSN_VSTn("vst2.16 {d1[2],d3[2]}", d1, d3, d1, d3);
+    TESTINSN_VSTn("vst2.16 {d1[3],d3[3]}", d1, d3, d1, d3);
+    TESTINSN_VSTn("vst2.8 {d0[7],d1[7]}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst2.8 {d1[6],d2[6]}", d1, d2, d1, d2);
+    TESTINSN_VSTn("vst2.8 {d0[5],d1[5]}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst2.8 {d0[4],d1[4]}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst2.8 {d20[3],d21[3]}", d20, d21, d20, d21);
+    TESTINSN_VSTn("vst2.8 {d0[2],d1[2]}", d0, d1, d0, d1);
+    TESTINSN_VSTn("vst2.8 {d17[1],d18[1]}", d17, d18, d17, d18);
+    TESTINSN_VSTn("vst2.8 {d30[0],d31[0]}", d30, d31, d30, d31);
+
+    printf("---- VST3 (multiple 3-elements) ----\n");
+    TESTINSN_VSTn("vst3.8 {d20-d22}", d20, d21, d22, d20);
+    TESTINSN_VSTn("vst3.16 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VSTn("vst3.32 {d0-d2}", d0, d1, d2, d0);
+    TESTINSN_VSTn("vst3.8 {d0,d2,d4}", d0, d2, d4, d0);
+    TESTINSN_VSTn("vst3.16 {d20,d22,d24}", d20, d22, d24, d20);
+    TESTINSN_VSTn("vst3.32 {d0,d2,d4}", d0, d2, d4, d0);
+
+    printf("---- VST3 (single 3-element structure from one lane) ----\n");
+    TESTINSN_VSTn("vst3.32 {d0[0],d1[0],d2[0]}", d0, d1, d2, d1);
+    TESTINSN_VSTn("vst3.32 {d0[1],d1[1],d2[1]}", d0, d1, d2, d1);
+    TESTINSN_VSTn("vst3.32 {d0[0],d2[0],d4[0]}", d0, d2, d4, d2);
+    TESTINSN_VSTn("vst3.32 {d0[1],d2[1],d4[1]}", d0, d2, d4, d2);
+    TESTINSN_VSTn("vst3.16 {d1[0],d2[0],d3[0]}", d1, d2, d3, d2);
+    TESTINSN_VSTn("vst3.16 {d1[1],d2[1],d3[1]}", d1, d2, d3, d2);
+    TESTINSN_VSTn("vst3.16 {d1[2],d2[2],d3[2]}", d1, d2, d3, d2);
+    TESTINSN_VSTn("vst3.16 {d1[3],d2[3],d3[3]}", d1, d2, d3, d2);
+    TESTINSN_VSTn("vst3.16 {d1[0],d3[0],d5[0]}", d1, d3, d3, d5);
+    TESTINSN_VSTn("vst3.16 {d1[1],d3[1],d5[1]}", d1, d3, d3, d5);
+    TESTINSN_VSTn("vst3.16 {d1[2],d3[2],d5[2]}", d1, d3, d3, d5);
+    TESTINSN_VSTn("vst3.16 {d1[3],d3[3],d5[3]}", d1, d3, d3, d5);
+    TESTINSN_VSTn("vst3.8 {d0[7],d1[7],d2[7]}", d0, d1, d2, d1);
+    TESTINSN_VSTn("vst3.8 {d1[6],d2[6],d3[6]}", d1, d2, d3, d2);
+    TESTINSN_VSTn("vst3.8 {d0[5],d1[5],d2[5]}", d0, d1, d2, d1);
+    TESTINSN_VSTn("vst3.8 {d0[4],d1[4],d2[4]}", d0, d1, d2, d1);
+    TESTINSN_VSTn("vst3.8 {d20[3],d21[3],d22[3]}", d20, d21, d22, d21);
+    TESTINSN_VSTn("vst3.8 {d0[2],d1[2],d2[2]}", d0, d1, d2, d1);
+    TESTINSN_VSTn("vst3.8 {d17[1],d18[1],d19[1]}", d17, d18, d19, d18);
+    TESTINSN_VSTn("vst3.8 {d29[0],d30[0],d31[0]}", d30, d31, d29, d31);
+
+    printf("---- VST4 (multiple 4-elements) ----\n");
+    TESTINSN_VSTn("vst4.8 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst4.16 {d20-d23}", d20, d21, d22, d23);
+    TESTINSN_VSTn("vst4.32 {d0-d3}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst4.8 {d0,d2,d4,d6}", d0, d2, d4, d6);
+    TESTINSN_VSTn("vst4.16 {d1,d3,d5,d7}", d1, d3, d5, d7);
+    TESTINSN_VSTn("vst4.32 {d20,d22,d24,d26}", d20, d22, d24, d26);
+
+    printf("---- VST4 (single 4-element structure from one lane) ----\n");
+    TESTINSN_VSTn("vst4.32 {d0[0],d1[0],d2[0],d3[0]}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst4.32 {d0[1],d1[1],d2[1],d3[1]}", d0, d1, d2, d4);
+    TESTINSN_VSTn("vst4.32 {d0[0],d2[0],d4[0],d6[0]}", d0, d2, d4, d6);
+    TESTINSN_VSTn("vst4.32 {d0[1],d2[1],d4[1],d6[1]}", d0, d2, d4, d6);
+    TESTINSN_VSTn("vst4.16 {d1[0],d2[0],d3[0],d4[0]}", d1, d2, d3, d4);
+    TESTINSN_VSTn("vst4.16 {d1[1],d2[1],d3[1],d4[1]}", d1, d2, d3, d4);
+    TESTINSN_VSTn("vst4.16 {d1[2],d2[2],d3[2],d4[2]}", d1, d2, d3, d4);
+    TESTINSN_VSTn("vst4.16 {d1[3],d2[3],d3[3],d4[3]}", d1, d2, d3, d4);
+    TESTINSN_VSTn("vst4.16 {d1[0],d3[0],d5[0],d7[0]}", d1, d3, d5, d7);
+    TESTINSN_VSTn("vst4.16 {d1[1],d3[1],d5[1],d7[1]}", d1, d3, d5, d7);
+    TESTINSN_VSTn("vst4.16 {d1[2],d3[2],d5[2],d7[2]}", d1, d3, d5, d7);
+    TESTINSN_VSTn("vst4.16 {d1[3],d3[3],d5[3],d7[3]}", d1, d3, d5, d7);
+    TESTINSN_VSTn("vst4.8 {d0[7],d1[7],d2[7],d3[7]}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst4.8 {d1[6],d2[6],d3[6],d4[6]}", d1, d2, d3, d4);
+    TESTINSN_VSTn("vst4.8 {d0[5],d1[5],d2[5],d3[5]}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst4.8 {d0[4],d1[4],d2[4],d3[4]}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst4.8 {d20[3],d21[3],d22[3],d23[3]}", d20, d21, d22, d23);
+    TESTINSN_VSTn("vst4.8 {d0[2],d1[2],d2[2],d3[2]}", d0, d1, d2, d3);
+    TESTINSN_VSTn("vst4.8 {d17[1],d18[1],d19[1],d20[1]}", d17, d18, d19, d20);
+    TESTINSN_VSTn("vst4.8 {d28[0],d29[0],d30[0],d31[0]}", d28, d29, d30, d31);
+
+    printf("---- VMOVN ----\n");
+    TESTINSN_bin("vmovn.i32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24);
+    TESTINSN_bin("vmovn.i16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24);
+    TESTINSN_bin("vmovn.i64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24);
+    TESTINSN_bin("vmovn.i32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0);
+    TESTINSN_bin("vmovn.i16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef);
+    TESTINSN_bin("vmovn.i64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24);
+
+    printf("---- VQMOVN ----\n");
+    TESTINSN_bin_q("vqmovn.u32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24);
+    TESTINSN_bin_q("vqmovn.u16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24);
+    TESTINSN_bin_q("vqmovn.u64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24);
+    TESTINSN_bin_q("vqmovn.u32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0);
+    TESTINSN_bin_q("vqmovn.u16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef);
+    TESTINSN_bin_q("vqmovn.u64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24);
+    TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24);
+    TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24);
+    TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24);
+    TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0);
+    TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef);
+    TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24);
+    TESTINSN_bin_q("vqmovn.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xff);
+    TESTINSN_bin_q("vqmovn.s16 d7, q5", d7, d10, i8, 0xff, d11, i16, 0xff);
+    TESTINSN_bin_q("vqmovn.s64 d31, q0", d31, d0, i8, 0xff, d1, i8, 0xff);
+
+    printf("---- VQMOVN ----\n");
+    TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i32, 0x32, d1, i32, 0x24);
+    TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i32, 0x32, d11, i32, 0x24);
+    TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i32, 0x32, d1, i32, 0x24);
+    TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xf0);
+    TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i16, 0xdead, d11, i16, 0xbeef);
+    TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i32, 0xff00fe0f, d1, i8, 0x24);
+    TESTINSN_bin_q("vqmovun.s32 d0, q0", d0, d0, i8, 0xff, d1, i8, 0xff);
+    TESTINSN_bin_q("vqmovun.s16 d7, q5", d7, d10, i8, 0xff, d11, i16, 0xff);
+    TESTINSN_bin_q("vqmovun.s64 d31, q0", d31, d0, i8, 0xff, d1, i8, 0xff);
+
+    printf("---- VABS ----\n");
+    TESTINSN_un("vabs.s32 d0, d1", d0, d1, i32, 0x73);
+    TESTINSN_un("vabs.s16 d15, d4", d15, d4, i32, 0x73);
+    TESTINSN_un("vabs.s8 d8, d7", d8, d7, i32, 0x73);
+    TESTINSN_un("vabs.s32 d0, d1", d0, d1, i32, 0xfe);
+    TESTINSN_un("vabs.s16 d31, d4", d31, d4, i32, 0xef);
+    TESTINSN_un("vabs.s8 d8, d7", d8, d7, i32, 0xde);
+    TESTINSN_un("vabs.s32 d0, d1", d0, d1, i16, 0xfe0a);
+    TESTINSN_un("vabs.s16 d15, d4", d15, d4, i16, 0xef0b);
+    TESTINSN_un("vabs.s8 d8, d7", d8, d7, i16, 0xde0c);
+
+    printf("---- VQABS ----\n");
+    TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 0x73);
+    TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 1 << 31);
+    TESTINSN_un_q("vqabs.s16 d0, d1", d0, d1, i32, 1 << 31);
+    TESTINSN_un_q("vqabs.s8 d0, d1", d0, d1, i32, 1 << 31);
+    TESTINSN_un_q("vqabs.s16 d15, d4", d15, d4, i32, 0x73);
+    TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i32, 0x73);
+    TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i32, 0xfe);
+    TESTINSN_un_q("vqabs.s16 d31, d4", d31, d4, i32, 0xef);
+    TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i32, 0xde);
+    TESTINSN_un_q("vqabs.s32 d0, d1", d0, d1, i16, 0xfe0a);
+    TESTINSN_un_q("vqabs.s16 d15, d4", d15, d4, i16, 0xef0b);
+    TESTINSN_un_q("vqabs.s8 d8, d7", d8, d7, i16, 0xde0c);
+
+    printf("---- VADDHN ----\n");
+    TESTINSN_bin("vaddhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72);
+    TESTINSN_bin("vaddhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vaddhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vaddhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vaddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172);
+    TESTINSN_bin("vaddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172);
+    TESTINSN_bin("vaddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172);
+    TESTINSN_bin("vaddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72);
+    TESTINSN_bin("vaddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vaddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vaddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+
+    printf("---- VRADDHN ----\n");
+    TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72);
+    TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vraddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172);
+    TESTINSN_bin("vraddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172);
+    TESTINSN_bin("vraddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172);
+    TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72);
+    TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vraddhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0102);
+    TESTINSN_bin("vraddhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0102);
+    TESTINSN_bin("vraddhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0102);
+    TESTINSN_bin("vraddhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x02);
+    TESTINSN_bin("vraddhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02);
+    TESTINSN_bin("vraddhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02);
+    TESTINSN_bin("vraddhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x02);
+
+    printf("---- VSUBHN ----\n");
+    TESTINSN_bin("vsubhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72);
+    TESTINSN_bin("vsubhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vsubhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vsubhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172);
+    TESTINSN_bin("vsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172);
+    TESTINSN_bin("vsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172);
+    TESTINSN_bin("vsubhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72);
+    TESTINSN_bin("vsubhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vsubhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vsubhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+
+    printf("---- VRSUBHN ----\n");
+    TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i32, 0x73, q1, i32, 0x72);
+    TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i32, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vrsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef73, q2, i32, 0x0172);
+    TESTINSN_bin("vrsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef73, q2, i32, 0x0172);
+    TESTINSN_bin("vrsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef73, q8, i32, 0x0172);
+    TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i8, 0x73, q1, i32, 0x72);
+    TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i8, 0x73, q2, i32, 0x72);
+    TESTINSN_bin("vrsubhn.i16 d0, q15, q2", d0, q15, i16, 0xef93, q2, i32, 0x0102);
+    TESTINSN_bin("vrsubhn.i32 d31, q1, q2", d31, q1, i16, 0xef93, q2, i32, 0x0102);
+    TESTINSN_bin("vrsubhn.i64 d0, q1, q8", d0, q1, i16, 0xef93, q8, i32, 0x0102);
+    TESTINSN_bin("vrsubhn.i32 d0, q1, q1", d0, q1, i8, 0x93, q1, i32, 0x02);
+    TESTINSN_bin("vrsubhn.i16 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02);
+    TESTINSN_bin("vrsubhn.i32 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02);
+    TESTINSN_bin("vrsubhn.i64 d0, q1, q2", d0, q1, i8, 0x93, q2, i32, 0x02);
+
+    printf("---- VCEQ #0 ----\n");
+    TESTINSN_un("vceq.i32 d0, d1, #0", d0, d1, i32, 0x21);
+    TESTINSN_un("vceq.i16 d2, d1, #0", d2, d1, i32, 0x21);
+    TESTINSN_un("vceq.i8 d10, d11, #0", d10, d11, i32, 0x21);
+    TESTINSN_un("vceq.i32 d0, d1, #0", d0, d1, i32, 0x0);
+    TESTINSN_un("vceq.i16 d2, d1, #0", d2, d1, i32, 0x0);
+    TESTINSN_un("vceq.i8 d10, d31, #0", d10, d31, i32, 0x0);
+
+    printf("---- VCGT #0 ----\n");
+    TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i32, 0x21);
+    TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i32, 0x21);
+    TESTINSN_un("vcgt.s8 d10, d31, #0", d10, d31, i32, 0x21);
+    TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i32, 0x0);
+    TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i32, 0x0);
+    TESTINSN_un("vcgt.s8 d10, d11, #0", d10, d11, i32, 0x0);
+    TESTINSN_un("vcgt.s32 d0, d1, #0", d0, d1, i8, 0xef);
+    TESTINSN_un("vcgt.s16 d2, d1, #0", d2, d1, i8, 0xed);
+    TESTINSN_un("vcgt.s8 d10, d11, #0", d10, d11, i8, 0xae);
+
+    printf("---- VCGE #0 ----\n");
+    TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0x21);
+    TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0x21);
+    TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i32, 0x21);
+    TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0x0);
+    TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0x0);
+    TESTINSN_un("vcge.s8 d10, d31, #0", d10, d31, i32, 0x0);
+    TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i8, 0xef);
+    TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i8, 0xed);
+    TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i8, 0xae);
+    TESTINSN_un("vcge.s32 d0, d1, #0", d0, d1, i32, 0xef);
+    TESTINSN_un("vcge.s16 d2, d1, #0", d2, d1, i32, 0xed);
+    TESTINSN_un("vcge.s8 d10, d11, #0", d10, d11, i32, 0xae);
+
+    printf("---- VCLE #0 ----\n");
+    TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i32, 0x21);
+    TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i32, 0x21);
+    TESTINSN_un("vcle.s8 d10, d11, #0", d10, d11, i32, 0x21);
+    TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i32, 0x0);
+    TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i32, 0x0);
+    TESTINSN_un("vcle.s8 d10, d31, #0", d10, d31, i32, 0x0);
+    TESTINSN_un("vcle.s32 d0, d1, #0", d0, d1, i8, 0xef);
+    TESTINSN_un("vcle.s16 d2, d1, #0", d2, d1, i8, 0xed);
+    TESTINSN_un("vcle.s8 d10, d11, #0", d10, d11, i8, 0xae);
+
+    printf("---- VCLT #0 ----\n");
+    TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0x21);
+    TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0x21);
+    TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0x21);
+    TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0x0);
+    TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0x0);
+    TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0x0);
+    TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i8, 0xef);
+    TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i8, 0xed);
+    TESTINSN_un("vclt.s8 d10, d31, #0", d10, d31, i8, 0xae);
+    TESTINSN_un("vclt.s32 d0, d1, #0", d0, d1, i32, 0xef);
+    TESTINSN_un("vclt.s16 d2, d1, #0", d2, d1, i32, 0xed);
+    TESTINSN_un("vclt.s8 d10, d11, #0", d10, d11, i32, 0xae);
+
+    printf("---- VCNT ----\n");
+    TESTINSN_un("vcnt.8 d0, d1", d0, d1, i32, 0xac3d25eb);
+    TESTINSN_un("vcnt.8 d11, d14", d11, d14, i32, 0xac3d25eb);
+    TESTINSN_un("vcnt.8 d6, d2", d6, d2, i32, 0xad0eb);
+
+    printf("---- VCLS ----\n");
+    TESTINSN_un("vcls.s8 d0, d1", d0, d1, i32, 0x21);
+    TESTINSN_un("vcls.s8 d30, d31", d30, d31, i8, 0x82);
+    TESTINSN_un("vcls.s16 d0, d1", d0, d1, i32, 0x21);
+    TESTINSN_un("vcls.s16 d31, d30", d31, d30, i8, 0x82);
+    TESTINSN_un("vcls.s32 d6, d1", d6, d1, i32, 0x21);
+    TESTINSN_un("vcls.s32 d30, d5", d30, d5, i8, 0x82);
+    TESTINSN_un("vcls.s8 d2, d4", d2, d4, i8, 0xff);
+    TESTINSN_un("vcls.s16 d2, d4", d2, d4, i8, 0xff);
+    TESTINSN_un("vcls.s32 d2, d4", d2, d4, i8, 0xff);
+    TESTINSN_un("vcls.s8 d2, d4", d2, d4, i16, 0xffef);
+    TESTINSN_un("vcls.s16 d2, d4", d2, d4, i16, 0xffef);
+    TESTINSN_un("vcls.s32 d2, d4", d2, d4, i16, 0xffef);
+    TESTINSN_un("vcls.s8 d2, d4", d2, d4, i8, 0x00);
+    TESTINSN_un("vcls.s16 d2, d4", d2, d4, i8, 0x00);
+    TESTINSN_un("vcls.s32 d2, d4", d2, d4, i8, 0x00);
+    TESTINSN_un("vcls.s8 d2, d4", d2, d4, i16, 0x00ef);
+    TESTINSN_un("vcls.s16 d2, d4", d2, d4, i16, 0x00ef);
+    TESTINSN_un("vcls.s32 d2, d4", d2, d4, i16, 0x00ef);
+
+    printf("---- VCLZ ----\n");
+    TESTINSN_un("vclz.i8 d0, d1", d0, d1, i32, 0x21);
+    TESTINSN_un("vclz.i8 d30, d31", d30, d31, i8, 0x82);
+    TESTINSN_un("vclz.i16 d0, d1", d0, d1, i32, 0x21);
+    TESTINSN_un("vclz.i16 d31, d30", d31, d30, i8, 0x82);
+    TESTINSN_un("vclz.i32 d6, d1", d6, d1, i32, 0x21);
+    TESTINSN_un("vclz.i32 d30, d5", d30, d5, i8, 0x82);
+    TESTINSN_un("vclz.i8 d2, d4", d2, d4, i8, 0xff);
+    TESTINSN_un("vclz.i16 d2, d4", d2, d4, i8, 0xff);
+    TESTINSN_un("vclz.i32 d2, d4", d2, d4, i8, 0xff);
+    TESTINSN_un("vclz.i8 d2, d4", d2, d4, i16, 0xffef);
+    TESTINSN_un("vclz.i16 d2, d4", d2, d4, i16, 0xffef);
+    TESTINSN_un("vclz.i32 d2, d4", d2, d4, i16, 0xffef);
+    TESTINSN_un("vclz.i8 d2, d4", d2, d4, i8, 0x00);
+    TESTINSN_un("vclz.i16 d2, d4", d2, d4, i8, 0x00);
+    TESTINSN_un("vclz.i32 d2, d4", d2, d4, i8, 0x00);
+    TESTINSN_un("vclz.i8 d2, d4", d2, d4, i16, 0x00ef);
+    TESTINSN_un("vclz.i16 d2, d4", d2, d4, i16, 0x00ef);
+    TESTINSN_un("vclz.i32 d2, d4", d2, d4, i16, 0x00ef);
+
+    printf("---- VSLI ----\n");
+    TESTINSN_un("vsli.16 d0, d1, #1", d0, d1, i32, 7);
+    TESTINSN_un("vsli.16 d3, d4, #2", d3, d4, i32, -0x7c);
+    TESTINSN_un("vsli.32 d2, d5, #31", d2, d5, i32, -1);
+    TESTINSN_un("vsli.8 d6, d7, #7", d6, d7, i32, 0xffff);
+    TESTINSN_un("vsli.16 d8, d9, #12", d8, d9, i32, -10);
+    TESTINSN_un("vsli.32 d10, d11, #5", d10, d11, i32, 10234);
+    TESTINSN_un("vsli.8 d12, d13, #1", d12, d13, i32, -1);
+    TESTINSN_un("vsli.16 d14, d15, #11", d14, d15, i32, -1);
+    TESTINSN_un("vsli.32 d10, d11, #9", d10, d11, i32, 1000);
+    TESTINSN_un("vsli.8 d7, d13, #7", d7, d13, i32, -1);
+    TESTINSN_un("vsli.16 d8, d1, #1", d8, d1, i32, 0xabcf);
+    TESTINSN_un("vsli.32 d12, d3, #15", d12, d3, i32, -0x1b0);
+    TESTINSN_un("vsli.64 d0, d1, #42", d0, d1, i32, -1);
+    TESTINSN_un("vsli.64 d6, d7, #12", d6, d7, i32, 0xfac);
+    TESTINSN_un("vsli.64 d8, d4, #9", d8, d4, i32, 13560);
+    TESTINSN_un("vsli.64 d9, d12, #11", d9, d12, i32, 98710);
+
+    printf("---- VPADD ----\n");
+    TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vpadd.i16 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vpadd.i8 d0, d1, d2", d0, d1, i32, 140, d2, i32, 120);
+    TESTINSN_bin("vpadd.i8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpadd.i16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpadd.i32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpadd.i32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VPADDL ----\n");
+    TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, 24);
+    TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpaddl.u16 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpaddl.u8 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpaddl.u8 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.u16 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.u32 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.u32 d10, d11", d10, d11, i32, 24);
+    TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, 24);
+    TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpaddl.s16 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpaddl.s8 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpaddl.s8 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.s16 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.s32 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpaddl.s32 d10, d11", d10, d11, i32, 24);
+
+    printf("---- VPADAL ----\n");
+    TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, 24);
+    TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpadal.u16 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpadal.u8 d0, d1", d0, d1, i8, 140);
+    TESTINSN_un("vpadal.u8 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.u16 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.u32 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.u32 d10, d11", d10, d11, i32, 24);
+    TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, 24);
+    TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpadal.s16 d0, d1", d0, d1, i32, 140);
+    TESTINSN_un("vpadal.s8 d0, d1", d0, d1, i8, 140);
+    TESTINSN_un("vpadal.s8 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.s16 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.s32 d0, d1", d0, d1, i32, (1 << 31) + 1);
+    TESTINSN_un("vpadal.s32 d10, d11", d10, d11, i32, 24);
+
+    printf("---- VZIP ----\n");
+    TESTINSN_dual("vzip.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34);
+    TESTINSN_dual("vzip.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34);
+    TESTINSN_dual("vzip.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34);
+    TESTINSN_dual("vzip.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vzip.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vzip.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d);
+
+    printf("---- VUZP ----\n");
+    TESTINSN_dual("vuzp.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34);
+    TESTINSN_dual("vuzp.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34);
+    TESTINSN_dual("vuzp.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34);
+    TESTINSN_dual("vuzp.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vuzp.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vuzp.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d);
+
+    printf("---- VTRN ----\n");
+    TESTINSN_dual("vtrn.32 d0, d1", d0, i8, 0x12, d1, i8, 0x34);
+    TESTINSN_dual("vtrn.16 d1, d0", d0, i8, 0x12, d1, i8, 0x34);
+    TESTINSN_dual("vtrn.8 d10, d11", d10, i8, 0x12, d11, i8, 0x34);
+    TESTINSN_dual("vtrn.32 d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vtrn.16 d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vtrn.8 d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d);
+
+    printf("---- VSWP ----\n");
+    TESTINSN_dual("vswp d0, d1", d0, i8, 0x12, d1, i8, 0x34);
+    TESTINSN_dual("vswp d1, d0", d0, i8, 0x12, d1, i8, 0x34);
+    TESTINSN_dual("vswp d10, d11", d10, i8, 0x12, d11, i8, 0x34);
+    TESTINSN_dual("vswp d0, d1", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vswp d1, d0", d0, i32, 0x12345678, d1, i32, 0x0a0b0c0d);
+    TESTINSN_dual("vswp d30, d31", d30, i32, 0x12345678, d31, i32, 0x0a0b0c0d);
+
+    printf("---- VSHRN ----\n");
+    TESTINSN_un("vshrn.i16 d0, q1, #1", d0, q1, i32, -1);
+    TESTINSN_un("vshrn.i16 d3, q4, #2", d3, q4, i32, -0x7c);
+    TESTINSN_un("vshrn.i32 d2, q5, #10", d2, q5, i32, -1);
+    TESTINSN_un("vshrn.i32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
+    TESTINSN_un("vshrn.i64 d6, q7, #7", d6, q7, i32, 0xffff);
+    TESTINSN_un("vshrn.i16 d8, q9, #8", d8, q9, i32, -10);
+    TESTINSN_un("vshrn.i32 d10, q11, #5", d10, q11, i32, 10234);
+    TESTINSN_un("vshrn.i64 d12, q13, #1", d12, q13, i32, -1);
+    TESTINSN_un("vshrn.i16 d14, q15, #6", d14, q15, i32, -1);
+    TESTINSN_un("vshrn.i32 d10, q11, #9", d10, q11, i32, 1000);
+    TESTINSN_un("vshrn.i64 d7, q13, #7", d7, q13, i32, -1);
+    TESTINSN_un("vshrn.i16 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un("vshrn.i32 d12, q3, #15", d12, q3, i32, -0x1b0);
+    TESTINSN_un("vshrn.i64 d0, q1, #22", d0, q1, i32, -1);
+    TESTINSN_un("vshrn.i64 d6, q7, #12", d6, q7, i32, 0xfac);
+    TESTINSN_un("vshrn.i64 d8, q4, #9", d8, q4, i32, 13560);
+    TESTINSN_un("vshrn.i64 d9, q12, #11", d9, q12, i32, 98710);
+
+    printf("---- VDUP ----\n");
+    TESTINSN_un("vdup.8 d12, d2[0]", d12, d2, i32, 0xabc4657);
+    TESTINSN_un("vdup.8 d0, d3[2]", d0, d3, i32, 0x7a1b3);
+    TESTINSN_un("vdup.8 d1, d0[7]", d1, d0, i32, 0x713aaa);
+    TESTINSN_un("vdup.8 d10, d4[3]", d10, d4, i32, 0xaa713);
+    TESTINSN_un("vdup.8 d4, d28[4]", d4, d28, i32, 0x7b1c3);
+    TESTINSN_un("vdup.16 d17, d19[1]", d17, d19, i32, 0x713ffff);
+    TESTINSN_un("vdup.16 d15, d31[2]", d15, d31, i32, 0x7f00fa);
+    TESTINSN_un("vdup.16 d6, d2[0]", d6, d2, i32, 0xffabcde);
+    TESTINSN_un("vdup.16 d8, d22[3]", d8, d22, i32, 0x713);
+    TESTINSN_un("vdup.16 d9, d2[0]", d9, d2, i32, 0x713);
+    TESTINSN_un("vdup.32 d10, d17[1]", d10, d17, i32, 0x713);
+    TESTINSN_un("vdup.32 d15, d11[0]", d15, d11, i32, 0x3);
+    TESTINSN_un("vdup.32 d30, d29[1]", d30, d29, i32, 0xf00000aa);
+    TESTINSN_un("vdup.32 d22, d0[1]", d22, d0, i32, 0xf);
+    TESTINSN_un("vdup.32 d13, d13[0]", d13, d13, i32, -1);
+
+    printf("---- VQDMULH ----\n");
+    TESTINSN_bin_q("vqdmulh.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqdmulh.s32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin_q("vqdmulh.s16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 30, d31, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+
+    printf("---- VQDMULH (by scalar) ----\n");
+    TESTINSN_bin_q("vqdmulh.s32 d0, d1, d6[0]", d0, d1, i32, 24, d6, i32, 120);
+    TESTINSN_bin_q("vqdmulh.s32 d6, d7, d1[1]", d6, d7, i32, 140, d1, i32, -120);
+    TESTINSN_bin_q("vqdmulh.s16 d9, d11, d7[0]", d9, d11, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[1]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[1]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin_q("vqdmulh.s16 d4, d5, d6[2]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqdmulh.s32 d10, d31, d15[0]", d10, d31, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 31, d7, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s16 d10, d14, d7[3]", d10, d14, i32, 1 << 31, q15, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 30, d15, i32, 1 << 31);
+    TESTINSN_bin_q("vqdmulh.s16 d31, d14, d7[1]", d31, d14, i32, 1 << 31, d7, i32, 1 << 30);
+
+    printf("---- VSHRN ----\n");
+    TESTINSN_un("vshrn.i64 d2, q2, #1", d2, q2, i32, 0xabc4657);
+    TESTINSN_un("vshrn.i64 d3, q3, #0", d3, q3, i32, 0x7a1b3);
+    TESTINSN_un("vshrn.i64 d1, q0, #3", d1, q0, i32, 0x713aaa);
+    TESTINSN_un("vshrn.i64 d0, q4, #5", d0, q4, i32, 0xaa713);
+    TESTINSN_un("vshrn.i64 d4, q8, #11", d4, q8, i32, 0x7b1c3);
+    TESTINSN_un("vshrn.i16 d7, q12, #6", d7, q12, i32, 0x713ffff);
+    TESTINSN_un("vshrn.i16 d15, q11, #2", d15, q11, i32, 0x7f00fa);
+    TESTINSN_un("vshrn.i16 d6, q2, #4", d6, q2, i32, 0xffabc);
+    TESTINSN_un("vshrn.i16 d8, q12, #3", d8, q12, i32, 0x713);
+    TESTINSN_un("vshrn.i16 d9, q2, #7", d9, q2, i32, 0x713);
+    TESTINSN_un("vshrn.i32 d10, q13, #2", d10, q13, i32, 0x713);
+    TESTINSN_un("vshrn.i32 d15, q11, #1", d15, q11, i32, 0x3);
+    TESTINSN_un("vshrn.i32 d10, q9, #5", d10, q9, i32, 0xf00000aa);
+    TESTINSN_un("vshrn.i32 d12, q0, #6", d12, q0, i32, 0xf);
+    TESTINSN_un("vshrn.i32 d13, q13, #2", d13, q13, i32, -1);
+
+    printf("---- VQSHRN ----\n");
+    TESTINSN_un_q("vqshrn.s16 d0, q1, #1", d0, q1, i32, -1);
+    TESTINSN_un_q("vqshrn.s16 d3, q4, #2", d3, q4, i32, -0x7c);
+    TESTINSN_un_q("vqshrn.s32 d2, q5, #10", d2, q5, i32, -1);
+    TESTINSN_un_q("vqshrn.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
+    TESTINSN_un_q("vqshrn.s16 d2, q5, #1", d2, q5, i16, 0x7fff);
+    TESTINSN_un_q("vqshrn.s64 d6, q7, #7", d6, q7, i32, 0xffff);
+    TESTINSN_un_q("vqshrn.s16 d8, q9, #8", d8, q9, i32, -10);
+    TESTINSN_un_q("vqshrn.s32 d10, q11, #5", d10, q11, i32, 10234);
+    TESTINSN_un_q("vqshrn.s64 d12, q13, #1", d12, q13, i32, -1);
+    TESTINSN_un_q("vqshrn.s16 d14, q15, #6", d14, q15, i32, -1);
+    TESTINSN_un_q("vqshrn.s32 d10, q11, #9", d10, q11, i32, 1000);
+    TESTINSN_un_q("vqshrn.s64 d7, q13, #7", d7, q13, i32, -1);
+    TESTINSN_un_q("vqshrn.s16 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqshrn.s32 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqshrn.s32 d12, q3, #15", d12, q3, i32, -0x1b0);
+    TESTINSN_un_q("vqshrn.s64 d0, q1, #22", d0, q1, i32, -1);
+    TESTINSN_un_q("vqshrn.s64 d6, q7, #12", d6, q7, i32, 0xfac);
+    TESTINSN_un_q("vqshrn.s64 d8, q4, #9", d8, q4, i32, 13560);
+    TESTINSN_un_q("vqshrn.s64 d9, q12, #11", d9, q12, i32, 98710);
+    TESTINSN_un_q("vqshrn.u16 d0, q1, #1", d0, q1, i32, -1);
+    TESTINSN_un_q("vqshrn.u16 d3, q4, #2", d3, q4, i32, -0x7c);
+    TESTINSN_un_q("vqshrn.u32 d2, q5, #10", d2, q5, i32, -1);
+    TESTINSN_un_q("vqshrn.u32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
+    TESTINSN_un_q("vqshrn.u16 d2, q5, #1", d2, q5, i16, 0x7fff);
+    TESTINSN_un_q("vqshrn.u64 d6, q7, #7", d6, q7, i32, 0xffff);
+    TESTINSN_un_q("vqshrn.u16 d8, q9, #8", d8, q9, i32, -10);
+    TESTINSN_un_q("vqshrn.u32 d10, q11, #5", d10, q11, i32, 10234);
+    TESTINSN_un_q("vqshrn.u64 d12, q13, #1", d12, q13, i32, -1);
+    TESTINSN_un_q("vqshrn.u16 d14, q15, #6", d14, q15, i32, -1);
+    TESTINSN_un_q("vqshrn.u32 d10, q11, #9", d10, q11, i32, 1000);
+    TESTINSN_un_q("vqshrn.u64 d7, q13, #7", d7, q13, i32, -1);
+    TESTINSN_un_q("vqshrn.u16 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqshrn.u32 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqshrn.u32 d12, q3, #15", d12, q3, i32, -0x1b0);
+    TESTINSN_un_q("vqshrn.u64 d0, q1, #22", d0, q1, i32, -1);
+    TESTINSN_un_q("vqshrn.u64 d6, q7, #12", d6, q7, i32, 0xfac);
+    TESTINSN_un_q("vqshrn.u64 d8, q4, #9", d8, q4, i32, 13560);
+    TESTINSN_un_q("vqshrn.u64 d9, q12, #11", d9, q12, i32, 98710);
+
+    printf("---- VQSHRUN ----\n");
+    TESTINSN_un_q("vqshrun.s16 d0, q1, #1", d0, q1, i32, -1);
+    TESTINSN_un_q("vqshrun.s16 d3, q4, #2", d3, q4, i32, -0x7c);
+    TESTINSN_un_q("vqshrun.s32 d2, q5, #10", d2, q5, i32, -1);
+    TESTINSN_un_q("vqshrun.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
+    TESTINSN_un_q("vqshrun.s16 d2, q5, #1", d2, q5, i16, 0x7fff);
+    TESTINSN_un_q("vqshrun.s64 d6, q7, #7", d6, q7, i32, 0xffff);
+    TESTINSN_un_q("vqshrun.s16 d8, q9, #8", d8, q9, i32, -10);
+    TESTINSN_un_q("vqshrun.s32 d10, q11, #5", d10, q11, i32, 10234);
+    TESTINSN_un_q("vqshrun.s64 d12, q13, #1", d12, q13, i32, -1);
+    TESTINSN_un_q("vqshrun.s16 d14, q15, #6", d14, q15, i32, -1);
+    TESTINSN_un_q("vqshrun.s32 d10, q11, #9", d10, q11, i32, 1000);
+    TESTINSN_un_q("vqshrun.s64 d7, q13, #7", d7, q13, i32, -1);
+    TESTINSN_un_q("vqshrun.s16 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqshrun.s32 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqshrun.s32 d12, q3, #15", d12, q3, i32, -0x1b0);
+    TESTINSN_un_q("vqshrun.s64 d0, q1, #22", d0, q1, i32, -1);
+    TESTINSN_un_q("vqshrun.s64 d6, q7, #12", d6, q7, i32, 0xfac);
+    TESTINSN_un_q("vqshrun.s64 d8, q4, #9", d8, q4, i32, 13560);
+    TESTINSN_un_q("vqshrun.s64 d9, q12, #11", d9, q12, i32, 98710);
+
+    printf("---- VQRSHRN ----\n");
+    TESTINSN_un_q("vqrshrn.s16 d0, q1, #1", d0, q1, i32, -1);
+    TESTINSN_un_q("vqrshrn.s16 d3, q4, #2", d3, q4, i32, -0x7c);
+    TESTINSN_un_q("vqrshrn.s32 d2, q5, #10", d2, q5, i32, -1);
+    TESTINSN_un_q("vqrshrn.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
+    TESTINSN_un_q("vqrshrn.s16 d2, q5, #1", d2, q5, i16, 0x7fff);
+    TESTINSN_un_q("vqrshrn.s64 d6, q7, #7", d6, q7, i32, 0xffff);
+    TESTINSN_un_q("vqrshrn.s16 d8, q9, #8", d8, q9, i32, -10);
+    TESTINSN_un_q("vqrshrn.s32 d10, q11, #5", d10, q11, i32, 10234);
+    TESTINSN_un_q("vqrshrn.s64 d12, q13, #1", d12, q13, i32, -1);
+    TESTINSN_un_q("vqrshrn.s16 d14, q15, #6", d14, q15, i32, -1);
+    TESTINSN_un_q("vqrshrn.s32 d10, q11, #9", d10, q11, i32, 1000);
+    TESTINSN_un_q("vqrshrn.s64 d7, q13, #7", d7, q13, i32, -1);
+    TESTINSN_un_q("vqrshrn.s16 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqrshrn.s32 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqrshrn.s32 d12, q3, #15", d12, q3, i32, -0x1b0);
+    TESTINSN_un_q("vqrshrn.s64 d0, q1, #22", d0, q1, i32, -1);
+    TESTINSN_un_q("vqrshrn.s64 d6, q7, #12", d6, q7, i32, 0xfac);
+    TESTINSN_un_q("vqrshrn.s64 d8, q4, #9", d8, q4, i32, 13560);
+    TESTINSN_un_q("vqrshrn.s64 d9, q12, #11", d9, q12, i32, 98710);
+    TESTINSN_un_q("vqrshrn.u16 d0, q1, #1", d0, q1, i32, -1);
+    TESTINSN_un_q("vqrshrn.u16 d3, q4, #2", d3, q4, i32, -0x7c);
+    TESTINSN_un_q("vqrshrn.u32 d2, q5, #10", d2, q5, i32, -1);
+    TESTINSN_un_q("vqrshrn.u32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
+    TESTINSN_un_q("vqrshrn.u16 d2, q5, #1", d2, q5, i16, 0x7fff);
+    TESTINSN_un_q("vqrshrn.u64 d6, q7, #7", d6, q7, i32, 0xffff);
+    TESTINSN_un_q("vqrshrn.u16 d8, q9, #8", d8, q9, i32, -10);
+    TESTINSN_un_q("vqrshrn.u32 d10, q11, #5", d10, q11, i32, 10234);
+    TESTINSN_un_q("vqrshrn.u64 d12, q13, #1", d12, q13, i32, -1);
+    TESTINSN_un_q("vqrshrn.u16 d14, q15, #6", d14, q15, i32, -1);
+    TESTINSN_un_q("vqrshrn.u32 d10, q11, #9", d10, q11, i32, 1000);
+    TESTINSN_un_q("vqrshrn.u64 d7, q13, #7", d7, q13, i32, -1);
+    TESTINSN_un_q("vqrshrn.u16 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqrshrn.u32 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqrshrn.u32 d12, q3, #15", d12, q3, i32, -0x1b0);
+    TESTINSN_un_q("vqrshrn.u64 d0, q1, #22", d0, q1, i32, -1);
+    TESTINSN_un_q("vqrshrn.u64 d6, q7, #12", d6, q7, i32, 0xfac);
+    TESTINSN_un_q("vqrshrn.u64 d8, q4, #9", d8, q4, i32, 13560);
+    TESTINSN_un_q("vqrshrn.u64 d9, q12, #11", d9, q12, i32, 98710);
+
+    printf("---- VQRSHRUN ----\n");
+    TESTINSN_un_q("vqrshrun.s16 d0, q1, #1", d0, q1, i32, -1);
+    TESTINSN_un_q("vqrshrun.s16 d3, q4, #2", d3, q4, i32, -0x7c);
+    TESTINSN_un_q("vqrshrun.s32 d2, q5, #10", d2, q5, i32, -1);
+    TESTINSN_un_q("vqrshrun.s32 d2, q5, #1", d2, q5, i32, 0x7fffffff);
+    TESTINSN_un_q("vqrshrun.s16 d2, q5, #1", d2, q5, i16, 0x7fff);
+    TESTINSN_un_q("vqrshrun.s64 d6, q7, #7", d6, q7, i32, 0xffff);
+    TESTINSN_un_q("vqrshrun.s16 d8, q9, #8", d8, q9, i32, -10);
+    TESTINSN_un_q("vqrshrun.s32 d10, q11, #5", d10, q11, i32, 10234);
+    TESTINSN_un_q("vqrshrun.s64 d12, q13, #1", d12, q13, i32, -1);
+    TESTINSN_un_q("vqrshrun.s16 d14, q15, #6", d14, q15, i32, -1);
+    TESTINSN_un_q("vqrshrun.s32 d10, q11, #9", d10, q11, i32, 1000);
+    TESTINSN_un_q("vqrshrun.s64 d7, q13, #7", d7, q13, i32, -1);
+    TESTINSN_un_q("vqrshrun.s16 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqrshrun.s32 d8, q1, #1", d8, q1, i32, 0xabcf);
+    TESTINSN_un_q("vqrshrun.s32 d12, q3, #15", d12, q3, i32, -0x1b0);
+    TESTINSN_un_q("vqrshrun.s64 d0, q1, #22", d0, q1, i32, -1);
+    TESTINSN_un_q("vqrshrun.s64 d6, q7, #12", d6, q7, i32, 0xfac);
+    TESTINSN_un_q("vqrshrun.s64 d8, q4, #9", d8, q4, i32, 13560);
+    TESTINSN_un_q("vqrshrun.s64 d9, q12, #11", d9, q12, i32, 98710);
+
+    printf("---- VRSHRN ----\n");
+    TESTINSN_un("vrshrn.i64 d2, q2, #1", d2, q2, i32, 0xabc4657);
+    TESTINSN_un("vrshrn.i64 d3, q3, #0", d3, q3, i32, 0x7a1b3);
+    TESTINSN_un("vrshrn.i64 d1, q0, #3", d1, q0, i32, 0x713aaa);
+    TESTINSN_un("vrshrn.i64 d0, q4, #5", d0, q4, i32, 0xaa713);
+    TESTINSN_un("vrshrn.i64 d4, q8, #11", d4, q8, i32, 0x7b1c3);
+    TESTINSN_un("vrshrn.i16 d7, q12, #6", d7, q12, i32, 0x713ffff);
+    TESTINSN_un("vrshrn.i16 d15, q11, #2", d15, q11, i32, 0x7f00fa);
+    TESTINSN_un("vrshrn.i16 d6, q2, #4", d6, q2, i32, 0xffabc);
+    TESTINSN_un("vrshrn.i16 d8, q12, #3", d8, q12, i32, 0x713);
+    TESTINSN_un("vrshrn.i16 d9, q2, #7", d9, q2, i32, 0x713);
+    TESTINSN_un("vrshrn.i32 d10, q13, #2", d10, q13, i32, 0x713);
+    TESTINSN_un("vrshrn.i32 d15, q11, #1", d15, q11, i32, 0x3);
+    TESTINSN_un("vrshrn.i32 d10, q9, #5", d10, q9, i32, 0xf00000aa);
+    TESTINSN_un("vrshrn.i32 d12, q0, #6", d12, q0, i32, 0xf);
+    TESTINSN_un("vrshrn.i32 d13, q13, #2", d13, q13, i32, -1);
+
+    printf("---- VSHL (immediate) ----\n");
+    TESTINSN_un("vshl.i64 d0, d1, #1", d0, d1, i32, 24);
+    TESTINSN_un("vshl.i64 d5, d2, #1", d5, d2, i32, (1 << 30));
+    TESTINSN_un("vshl.i64 d9, d12, #2", d9, d12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshl.i64 d11, d2, #12", d11, d2, i32, -1);
+    TESTINSN_un("vshl.i64 d15, d12, #63", d15, d12, i32, 5);
+    TESTINSN_un("vshl.i64 d5, d12, #62", d5, d12, i32, (1 << 31) + 1);
+    TESTINSN_un("vshl.i32 d0, d1, #1", d0, d1, i32, 24);
+    TESTINSN_un("vshl.i32 d5, d2, #1", d5, d2, i32, (1 << 30));
+    TESTINSN_un("vshl.i32 d9, d12, #2", d9, d12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshl.i32 d11, d2, #12", d11, d2, i32, -1);
+    TESTINSN_un("vshl.i32 d15, d12, #20", d15, d12, i32, 5);
+    TESTINSN_un("vshl.i32 d5, d12, #30", d5, d12, i32, (1 << 31) + 1);
+    TESTINSN_un("vshl.i16 d0, d1, #1", d0, d1, i16, 24);
+    TESTINSN_un("vshl.i16 d5, d2, #1", d5, d2, i32, (1 << 30));
+    TESTINSN_un("vshl.i16 d9, d12, #2", d9, d12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshl.i16 d11, d2, #12", d11, d2, i16, -1);
+    TESTINSN_un("vshl.i16 d15, d12, #3", d15, d12, i16, 5);
+    TESTINSN_un("vshl.i16 d5, d12, #14", d5, d12, i32, (1 << 31) + 1);
+    TESTINSN_un("vshl.i8 d0, d1, #1", d0, d1, i8, 24);
+    TESTINSN_un("vshl.i8 d5, d2, #1", d5, d2, i32, (1 << 30));
+    TESTINSN_un("vshl.i8 d9, d12, #2", d9, d12, i32, (1 << 31) + 2);
+    TESTINSN_un("vshl.i8 d11, d2, #7", d11, d2, i8, -1);
+    TESTINSN_un("vshl.i8 d15, d12, #3", d15, d12, i8, 5);
+    TESTINSN_un("vshl.i8 d5, d12, #6", d5, d12, i32, (1 << 31) + 1);
+
+    printf("---- VNEG ----\n");
+    TESTINSN_un("vneg.s32 d0, d1", d0, d1, i32, 0x73);
+    TESTINSN_un("vneg.s16 d15, d4", d15, d4, i32, 0x73);
+    TESTINSN_un("vneg.s8 d8, d7", d8, d7, i32, 0x73);
+    TESTINSN_un("vneg.s32 d0, d1", d0, d1, i32, 0xfe);
+    TESTINSN_un("vneg.s16 d31, d4", d31, d4, i32, 0xef);
+    TESTINSN_un("vneg.s8 d8, d7", d8, d7, i32, 0xde);
+    TESTINSN_un("vneg.s32 d0, d1", d0, d1, i16, 0xfe0a);
+    TESTINSN_un("vneg.s16 d15, d4", d15, d4, i16, 0xef0b);
+    TESTINSN_un("vneg.s8 d8, d7", d8, d7, i16, 0xde0c);
+
+    printf("---- VQNEG ----\n");
+    TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 0x73);
+    TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 1 << 31);
+    TESTINSN_un_q("vqneg.s16 d0, d1", d0, d1, i32, 1 << 31);
+    TESTINSN_un_q("vqneg.s8 d0, d1", d0, d1, i32, 1 << 31);
+    TESTINSN_un_q("vqneg.s16 d15, d4", d15, d4, i32, 0x73);
+    TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i32, 0x73);
+    TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i32, 0xfe);
+    TESTINSN_un_q("vqneg.s16 d31, d4", d31, d4, i32, 0xef);
+    TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i32, 0xde);
+    TESTINSN_un_q("vqneg.s32 d0, d1", d0, d1, i16, 0xfe0a);
+    TESTINSN_un_q("vqneg.s16 d15, d4", d15, d4, i16, 0xef0b);
+    TESTINSN_un_q("vqneg.s8 d8, d7", d8, d7, i16, 0xde0c);
+
+    printf("---- VREV ----\n");
+    TESTINSN_un("vrev64.8 d0, d1", d0, d1, i32, 0xaabbccdd);
+    TESTINSN_un("vrev64.16 d10, d31", d10, d31, i32, 0xaabbccdd);
+    TESTINSN_un("vrev64.32 d1, d14", d1, d14, i32, 0xaabbccdd);
+    TESTINSN_un("vrev32.8 d0, d1", d0, d1, i32, 0xaabbccdd);
+    TESTINSN_un("vrev32.16 d30, d15", d30, d15, i32, 0xaabbccdd);
+    TESTINSN_un("vrev16.8 d0, d1", d0, d1, i32, 0xaabbccdd);
+
+    printf("---- VTBL ----\n");
+    TESTINSN_tbl_1("vtbl.8 d0, {d2}, d1", d0, d1, i8, 0, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbl.8 d0, {d31}, d1", d0, d1, i8, 0x07, d31, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbl.8 d0, {d20}, d1", d0, d1, i8, 1, d20, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbl.8 d0, {d2}, d31", d0, d31, i8, 2, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07030501, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbl.8 d31, {d2}, d1", d31, d1, i16, 0x0104, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07080501, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbl.8 d30, {d2}, d1", d30, d1, i32, 0x07ed05ee, d2, i32, 0x12345678);
+    TESTINSN_tbl_2("vtbl.8 d0, {d2-d3}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d0, {d1-d2}, d3", d0, d3, i8, 0xa, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d0, {d30-d31}, d1", d0, d1, i8, 0xf, d30, i32, 0x12345678, d31, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 14, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x070e0e01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0d130f01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbl.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_3("vtbl.8 d0, {d2-d4}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d0, {d1-d3}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d0, {d29-d31}, d1", d0, d1, i8, 0x17, d29, i32, 0x12345678, d30, i32, 0xa1a2a3a4, d31, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d0, {d22-d24}, d1", d0, d1, i8, 17, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0a031504, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x170efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0d130f11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbl.8 d30, {d2-d4}, d31", d30, d31, i32, 0x070f1511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_4("vtbl.8 d0, {d2-d5}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d0, {d1-d4}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd, d4, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d0, {d28-d31}, d1", d0, d1, i8, 0x17, d28, i32, 0x12345678, d29, i32, 0xa1a2a3a4, d30, i32, 0xcacbcccd, d31, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1a, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1f, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1a0315ff, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x171efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1d130f1a, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbl.8 d30, {d2-d5}, d31", d30, d31, i32, 0x17101c11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+
+    printf("---- VTBX ----\n");
+    TESTINSN_tbl_1("vtbx.8 d0, {d2}, d1", d0, d1, i8, 0, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbx.8 d0, {d31}, d1", d0, d1, i8, 0x07, d31, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbx.8 d0, {d20}, d1", d0, d1, i8, 1, d20, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbx.8 d0, {d2}, d31", d0, d31, i8, 2, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07030501, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbx.8 d31, {d2}, d1", d31, d1, i16, 0x0104, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07080501, d2, i32, 0x12345678);
+    TESTINSN_tbl_1("vtbx.8 d30, {d2}, d1", d30, d1, i32, 0x07ed05ee, d2, i32, 0x12345678);
+    TESTINSN_tbl_2("vtbx.8 d0, {d2-d3}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d0, {d1-d2}, d3", d0, d3, i8, 0xa, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d0, {d30-d31}, d1", d0, d1, i8, 0xf, d30, i32, 0x12345678, d31, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 14, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d0, {d22-d23}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x070e0e01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x0d130f01, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_2("vtbx.8 d30, {d2-d3}, d31", d30, d31, i32, 0x07030511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4);
+    TESTINSN_tbl_3("vtbx.8 d0, {d2-d4}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d0, {d1-d3}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d0, {d29-d31}, d1", d0, d1, i8, 0x17, d29, i32, 0x12345678, d30, i32, 0xa1a2a3a4, d31, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 15, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d0, {d22-d24}, d1", d0, d1, i8, 17, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0a031504, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x170efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x0d130f11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_3("vtbx.8 d30, {d2-d4}, d31", d30, d31, i32, 0x070f1511, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd);
+    TESTINSN_tbl_4("vtbx.8 d0, {d2-d5}, d1", d0, d1, i8, 0, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d0, {d1-d4}, d10", d0, d10, i8, 0x11, d1, i32, 0x12345678, d2, i32, 0xa1a2a3a4, d3, i32, 0xcacbcccd, d4, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d0, {d28-d31}, d1", d0, d1, i8, 0x17, d28, i32, 0x12345678, d29, i32, 0xa1a2a3a4, d30, i32, 0xcacbcccd, d31, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 9, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1a, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 4, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x16, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d0, {d22-d25}, d1", d0, d1, i8, 0x1f, d22, i32, 0x12345678, d23, i32, 0xa1a2a3a4, d24, i32, 0xcacbcccd, d25, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1a0315ff, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x0c0a0501, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x171efe0f, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x1d130f1a, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+    TESTINSN_tbl_4("vtbx.8 d30, {d2-d5}, d31", d30, d31, i32, 0x17101c11, d2, i32, 0x12345678, d3, i32, 0xa1a2a3a4, d4, i32, 0xcacbcccd, d5, i32, 0xfefdfcfb);
+
+    printf("---- VPMAX (integer) ----\n");
+    TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121);
+    TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120);
+    TESTINSN_bin("vpmax.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmax.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120);
+    TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120);
+    TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, 0x01202120, d2, i32, 120);
+    TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmax.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmax.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VPMIN (integer) ----\n");
+    TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 121);
+    TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 121);
+    TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120);
+    TESTINSN_bin("vpmin.s8 d0, d1, d2", d0, d1, i32, 120, d2, i32, 120);
+    TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 1, d5, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmin.s8 d5, d7, d5", d5, d7, i32, (1 << 31) + 4, d5, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.s16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.s32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.s32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+    TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 25, d2, i32, 120);
+    TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 250, d2, i32, 120);
+    TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, 140, d2, i32, 140);
+    TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, 0x01200140, d2, i32, 120);
+    TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, 0x01202120, d2, i32, 120);
+    TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 1, d2, i32, (1 << 31) + 3);
+    TESTINSN_bin("vpmin.u8 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.u16 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.u32 d0, d1, d2", d0, d1, i32, (1 << 31) + 4, d2, i32, (1 << 31) + 2);
+    TESTINSN_bin("vpmin.u32 d10, d11, d12", d10, d11, i32, 24, d12, i32, 120);
+
+    printf("---- VQRDMULH ----\n");
+    TESTINSN_bin_q("vqrdmulh.s32 d0, d1, d2", d0, d1, i32, 24, d2, i32, 120);
+    TESTINSN_bin_q("vqrdmulh.s32 d6, d7, d8", d6, d7, i32, 140, d8, i32, -120);
+    TESTINSN_bin_q("vqrdmulh.s16 d9, d11, d12", d9, d11, i32, 0x140, d12, i32, 0x120);
+    TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 14) - 0xabcd, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31), d9, i32, 12); 
+    TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 d10, d11, d15", d10, d11, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqrdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 31); 
+    TESTINSN_bin_q("vqrdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, (1 << 31) + 1); 
+    TESTINSN_bin_q("vqrdmulh.s32 d10, d30, d31", d10, d30, i32, 1 << 30, d31, i32, 1 << 31); 
+    TESTINSN_bin_q("vqrdmulh.s16 d10, d30, d31", d10, d30, i32, 1 << 31, d31, i32, 1 << 30);
+
+    printf("---- VQRDMULH (by scalar) ----\n");
+    TESTINSN_bin_q("vqrdmulh.s32 d0, d1, d6[0]", d0, d1, i32, 24, d6, i32, 120);
+    TESTINSN_bin_q("vqrdmulh.s32 d6, d7, d1[1]", d6, d7, i32, 140, d1, i32, -120);
+    TESTINSN_bin_q("vqrdmulh.s16 d9, d11, d7[0]", d9, d11, i32, 0x140, d7, i32, 0x120);
+    TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[0]", d4, d5, i32, (1 << 14) + 1, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[1]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[1]", d4, d5, i32, (1 << 14) - 0xabcd, d6, i16, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31), d9, i32, 12);
+    TESTINSN_bin_q("vqrdmulh.s16 d4, d5, d6[2]", d4, d5, i32, (1 << 28) + 0xfe, d6, i32, (1 << 13) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 d7, d8, d9[0]", d7, d8, i32, (1 << 31) + 1, d9, i32, (1 << 31) + 2);
+    TESTINSN_bin_q("vqrdmulh.s32 d10, d31, d15[0]", d10, d31, i32, 24, d15, i32, 120);
+    TESTINSN_bin_q("vqrdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 31, d7, i32, 1 << 31);
+    TESTINSN_bin_q("vqrdmulh.s16 d10, d14, d7[3]", d10, d14, i32, 1 << 31, q15, i32, (1 << 31) + 1);
+    TESTINSN_bin_q("vqrdmulh.s32 d10, d14, d15[1]", d10, d14, i32, 1 << 30, d15, i32, 1 << 31);
+    TESTINSN_bin_q("vqrdmulh.s16 d31, d14, d7[1]", d31, d14, i32, 1 << 31, d7, i32, 1 << 30);
+
+    printf("---- VADD (fp) ----\n");
+    TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vadd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vadd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vadd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vadd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vadd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vadd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vadd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vadd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vadd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vadd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VSUB (fp) ----\n");
+    TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
+    TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
+    TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vsub.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vsub.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vsub.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vsub.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vsub.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vsub.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vsub.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vsub.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vsub.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vsub.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vsub.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VMUL (fp) ----\n");
+    TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
+    TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
+    TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vmul.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vmul.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vmul.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vmul.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vmul.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vmul.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vmul.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vmul.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vmul.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vmul.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmul.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VMLA (fp) ----\n");
+    TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
+    TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
+    TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin_f("vmla.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin_f("vmla.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin_f("vmla.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin_f("vmla.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin_f("vmla.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin_f("vmla.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin_f("vmla.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin_f("vmla.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin_f("vmla.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin_f("vmla.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VMLA (fp by scalar) ----\n");
+    TESTINSN_bin_f("vmla.f32 d0, d1, d4[0]", d0, d1, i32, f2u(24), d4, i32, f2u(120));
+    TESTINSN_bin_f("vmla.f32 d31, d8, d7[1]", d31, d8, i32, f2u(140), d7, i32, f2u(-120));
+    TESTINSN_bin_f("vmla.f32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin_f("vmla.f32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin_f("vmla.f32 d17, d8, d1[1]", d17, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+    TESTINSN_bin_f("vmla.f32 d7, d8, d1[0]", d7, d8, i32, f2u(1e22), d1, i32, f2u(1e-19));
+    TESTINSN_bin_f("vmla.f32 d7, d24, d1[0]", d7, d24, i32, f2u(1e12), d1, i32, f2u(1e11));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmla.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VMLS (fp) ----\n");
+    TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
+    TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
+    TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin_f("vmls.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin_f("vmls.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin_f("vmls.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin_f("vmls.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin_f("vmls.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin_f("vmls.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin_f("vmls.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin_f("vmls.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin_f("vmls.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin_f("vmls.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VMLS (fp by scalar) ----\n");
+    TESTINSN_bin_f("vmls.f32 d0, d1, d4[0]", d0, d1, i32, f2u(24), d4, i32, f2u(120));
+    TESTINSN_bin_f("vmls.f32 d31, d8, d7[1]", d31, d8, i32, f2u(140), d7, i32, f2u(-120));
+    TESTINSN_bin_f("vmls.f32 d4, d8, d15[1]", d4, d8, i32, (1 << 31) + 1, d15, i32, (1 << 31) + 2);
+    TESTINSN_bin_f("vmls.f32 d7, d8, d1[1]", d7, d8, i32, (1 << 31), d1, i16, 12);
+    TESTINSN_bin_f("vmls.f32 d17, d8, d1[1]", d17, d8, i32, (1 << 31) + 1, d1, i32, (1 << 31) + 2);
+    TESTINSN_bin_f("vmls.f32 d7, d8, d1[0]", d7, d8, i32, f2u(1e22), d1, i32, f2u(1e-19));
+    TESTINSN_bin_f("vmls.f32 d7, d24, d1[0]", d7, d24, i32, f2u(1e12), d1, i32, f2u(1e11));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin_f("vmls.f32 d0, d1, d2[0]", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VABD (fp) ----\n");
+    TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
+    TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
+    TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vabd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vabd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vabd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vabd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vabd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vabd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vabd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vabd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vabd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vabd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vabd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vabd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+
+    printf("---- VPADD (fp) ----\n");
+    TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
+    TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
+    TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vpadd.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vpadd.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vpadd.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vpadd.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vpadd.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vpadd.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vpadd.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vpadd.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vpadd.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vpadd.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpadd.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VCVT (integer <-> fp) ----\n");
+    TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vcvt.u32.f32 d10, d11", d10, d11, i32, f2u(3e22));
+    TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vcvt.u32.f32 d15, d4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vcvt.u32.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vcvt.u32.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vcvt.s32.f32 d20, d21", d20, d21, i32, f2u(3e22));
+    TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vcvt.s32.f32 d15, d4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vcvt.s32.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vcvt.s32.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vcvt.f32.u32 d0, d1", d0, d1, i32, 7);
+    TESTINSN_un("vcvt.f32.u32 d10, d11", d10, d11, i32, 1 << 31);
+    TESTINSN_un("vcvt.f32.u32 d0, d1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vcvt.f32.u32 d24, d26", d24, d26, i32, (1U << 31) - 1);
+    TESTINSN_un("vcvt.f32.u32 d0, d14", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, 7);
+    TESTINSN_un("vcvt.f32.s32 d30, d31", d30, d31, i32, 1 << 31);
+    TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vcvt.f32.s32 d0, d1", d0, d1, i32, (1U << 31) - 1);
+    TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vcvt.u32.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
+    TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vcvt.s32.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VCVT (fixed <-> fp) ----\n");
+    TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vcvt.u32.f32 d10, d11, #1", d10, d11, i32, f2u(3e22));
+    TESTINSN_un("vcvt.u32.f32 d15, d4, #32", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vcvt.u32.f32 d15, d4, #7", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vcvt.u32.f32 d15, d4, #4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vcvt.u32.f32 d12, d8, #3", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vcvt.u32.f32 d12, d8, #3", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vcvt.s32.f32 d0, d1, #5", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vcvt.s32.f32 d20, d21, #1", d20, d21, i32, f2u(3e22));
+    TESTINSN_un("vcvt.s32.f32 d15, d4, #8", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vcvt.s32.f32 d15, d4, #2", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vcvt.s32.f32 d15, d4, #1", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vcvt.s32.f32 d12, d8, #2", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vcvt.s32.f32 d12, d8, #2", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vcvt.f32.u32 d0, d1, #5", d0, d1, i32, 7);
+    TESTINSN_un("vcvt.f32.u32 d10, d11, #9", d10, d11, i32, 1 << 31);
+    TESTINSN_un("vcvt.f32.u32 d0, d1, #4", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vcvt.f32.u32 d24, d26, #6", d24, d26, i32, (1U << 31) - 1);
+    TESTINSN_un("vcvt.f32.u32 d0, d14, #5", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vcvt.f32.s32 d0, d1, #12", d0, d1, i32, 7);
+    TESTINSN_un("vcvt.f32.s32 d30, d31, #8", d30, d31, i32, 1 << 31);
+    TESTINSN_un("vcvt.f32.s32 d0, d1, #1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vcvt.f32.s32 d0, d1, #6", d0, d1, i32, (1U << 31) - 1);
+    TESTINSN_un("vcvt.f32.s32 d0, d14, #2", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vcvt.u32.f32 d0, d1, #3", d0, d1, i32, f2u(-INFINITY));
+    TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vcvt.s32.f32 d0, d1, #3", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VMAX (fp) ----\n");
+    TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vmax.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vmax.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vmax.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vmax.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vmax.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vmax.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vmax.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vmax.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vmax.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vmax.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VMIN (fp) ----\n");
+    TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vmin.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vmin.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vmin.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vmin.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vmin.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vmin.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vmin.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vmin.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vmin.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vmin.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VPMAX (fp) ----\n");
+    TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vpmax.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vpmax.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vpmax.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vpmax.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vpmax.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vpmax.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vpmax.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vpmax.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vpmax.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vpmax.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpmax.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VPMIN (fp) ----\n");
+    TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vpmin.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vpmin.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vpmin.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vpmin.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vpmin.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vpmin.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vpmin.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vpmin.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vpmin.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vpmin.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vpmin.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VRECPE ----\n");
+    TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(-653.2));
+    TESTINSN_un("vrecpe.u32 d10, d11", d10, d11, i32, f2u(3e22));
+    TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vrecpe.u32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vrecpe.u32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vrecpe.u32 d0, d1", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vrecpe.u32 d10, d11", d10, d11, i32, f2u(3e22));
+    TESTINSN_un("vrecpe.u32 d15, d4", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vrecpe.f32 d15, d4", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vrecpe.f32 d15, d4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vrecpe.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vrecpe.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, 7);
+    TESTINSN_un("vrecpe.f32 d10, d11", d10, d11, i32, 1 << 31);
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
+    TESTINSN_un("vrecpe.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, 7);
+    TESTINSN_un("vrecpe.f32 d10, d11", d10, d11, i32, 1 << 31);
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
+    TESTINSN_un("vrecpe.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vrecpe.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VRECPS ----\n");
+    TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346)); 
+    TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
+    TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vrecps.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vrecps.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vrecps.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vrecps.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vrecps.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); 
+    TESTINSN_bin("vrecps.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vrecps.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vrecps.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vrecps.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vrecps.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrecps.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VABS (fp) ----\n");
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, f2u(3e22));
+    TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, f2u(3e22));
+    TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vabs.f32 d15, d4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vabs.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, 7);
+    TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, 1 << 31); 
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
+    TESTINSN_un("vabs.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, 7);
+    TESTINSN_un("vabs.f32 d10, d11", d10, d11, i32, 1 << 31); 
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
+    TESTINSN_un("vabs.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vabs.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VCGT (fp) ----\n");
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
+    TESTINSN_bin("vcgt.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
+    TESTINSN_bin("vcgt.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
+    TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vcgt.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vcgt.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vcgt.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vcgt.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vcgt.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vcgt.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vcgt.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vcgt.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vcgt.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vcgt.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vcgt.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vcgt.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VCGE (fp) ----\n");
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
+    TESTINSN_bin("vcge.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
+    TESTINSN_bin("vcge.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
+    TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vcge.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vcge.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vcge.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vcge.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vcge.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vcge.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vcge.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vcge.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vcge.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vcge.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vcge.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vcge.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vcge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VACGT (fp) ----\n");
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
+    TESTINSN_bin("vacgt.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
+    TESTINSN_bin("vacgt.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
+    TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vacgt.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vacgt.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vacgt.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vacgt.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vacgt.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vacgt.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vacgt.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vacgt.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vacgt.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vacgt.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vacgt.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vacgt.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacgt.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VACGE (fp) ----\n");
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
+    TESTINSN_bin("vacge.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
+    TESTINSN_bin("vacge.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
+    TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vacge.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vacge.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vacge.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vacge.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vacge.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vacge.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vacge.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vacge.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vacge.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vacge.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vacge.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vacge.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vacge.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VCEQ (fp) ----\n");
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.5), d2, i32, f2u(-0.5));
+    TESTINSN_bin("vceq.f32 d2, d15, d12", d2, d15, i32, f2u(-0.53), d12, i32, f2u(0.52));
+    TESTINSN_bin("vceq.f32 d15, d7, d8", d15, d7, i32, f2u(231.45), d7, i32, f2u(231.45));
+    TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vceq.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(24.87556), d5, i32, f2u(1346.0004));
+    TESTINSN_bin("vceq.f32 d10, d31, d2", d10, d31, i32, f2u(48755.7), d2, i32, f2u(1089.2));
+    TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vceq.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vceq.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vceq.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vceq.f32 d20, d21, d2", d20, d21, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vceq.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752));
+    TESTINSN_bin("vceq.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vceq.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vceq.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vceq.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vceq.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0), d2, i32, f2u(0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(1.0/1024.0), d2, i32, f2u(-1.0/1024.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-1.0/1024.0), d2, i32, f2u(1.0/1024.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(2342+1.0/1024.0), d2, i32, f2u(2342-1.0/1024.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-2342+1.0/1024.0), d2, i32, f2u(-2342-1.0/1024.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(89276+1.0/1024.0), d2, i32, f2u(98276+1.0/1024.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vceq.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VCEQ (fp) #0 ----\n");
+    TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
+    TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, 0x1);
+    TESTINSN_un("vceq.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
+    TESTINSN_un("vceq.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
+    TESTINSN_un("vceq.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
+    TESTINSN_un("vceq.f32 d30, d15, #0", d30, d15, i32, 0x0);
+    TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vceq.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VCGT (fp) #0 ----\n");
+    TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
+    TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, 0x1);
+    TESTINSN_un("vcgt.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
+    TESTINSN_un("vcgt.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
+    TESTINSN_un("vcgt.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
+    TESTINSN_un("vcgt.f32 d30, d15, #0", d30, d15, i32, 0x0);
+    TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vcgt.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VCLT (fp) #0 ----\n");
+    TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
+    TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, 0x1);
+    TESTINSN_un("vclt.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
+    TESTINSN_un("vclt.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
+    TESTINSN_un("vclt.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
+    TESTINSN_un("vclt.f32 d30, d15, #0", d30, d15, i32, 0x0);
+    TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vclt.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VCGE (fp) #0 ----\n");
+    TESTINSN_un("vcge.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
+    TESTINSN_un("vcge.f32 d0, d1, #0", d0, d1, i32, 0x1);
+    TESTINSN_un("vcge.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
+    TESTINSN_un("vcge.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
+    TESTINSN_un("vcge.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
+    TESTINSN_un("vcge.f32 d30, d15, #0", d30, d15, i32, 0x0);
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VCLE (fp) #0 ----\n");
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, 0x01000000);
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, 0x1);
+    TESTINSN_un("vcle.f32 d2, d1, #0", d2, d1, i32, 1 << 31);
+    TESTINSN_un("vcle.f32 d2, d1, #0", d2, d1, i32, f2u(23.04));
+    TESTINSN_un("vcle.f32 d2, d31, #0", d2, d31, i32, f2u(-23.04));
+    TESTINSN_un("vcle.f32 d30, d15, #0", d30, d15, i32, 0x0);
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vcle.f32 d0, d1, #0", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VNEG (fp) ----\n");
+    TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, 0x01000000);
+    TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, 0x1);
+    TESTINSN_un("vneg.f32 d2, d1", d2, d1, i32, 1 << 31);
+    TESTINSN_un("vneg.f32 d2, d1", d2, d1, i32, f2u(23.04));
+    TESTINSN_un("vneg.f32 d2, d31", d2, d31, i32, f2u(-23.04));
+    TESTINSN_un("vneg.f32 d30, d15", d30, d15, i32, 0x0);
+    TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vneg.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
+
+    printf("---- VRSQRTS ----\n");
+    TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(23.04), d2, i32, f2u(-45.5687));
+    TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(-347856.475), d5, i32, f2u(1346));
+    TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(-45786.476));
+    TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(95867.76), d7, i32, f2u(17065));
+    TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(-45667.24), d2, i32, f2u(-248562.76));
+    TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(24), d5, i32, f2u(1346));
+    TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(48755), d2, i32, f2u(1089));
+    TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(214), d7, i32, f2u(1752065));
+    TESTINSN_bin("vrsqrts.f32 d0, d11, d12", d0, d11, i32, f2u(356047.56), d12, i32, f2u(5867.009));
+    TESTINSN_bin("vrsqrts.f32 d7, d1, d6", d7, d1, i32, f2u(34.00046), d6, i32, f2u(0.0024575));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(2754), d2, i32, f2u(107));
+    TESTINSN_bin("vrsqrts.f32 d3, d4, d5", d3, d4, i32, f2u(874), d5, i32, f2u(1384.6));
+    TESTINSN_bin("vrsqrts.f32 d10, d11, d2", d10, d11, i32, f2u(487.587), d2, i32, f2u(109));
+    TESTINSN_bin("vrsqrts.f32 d9, d5, d7", d9, d5, i32, f2u(2146), d7, i32, f2u(1752)); 
+    TESTINSN_bin("vrsqrts.f32 d0, d11, d12", d0, d11, i32, f2u(-56.25), d12, i32, f2u(-5786.47));
+    TESTINSN_bin("vrsqrts.f32 d7, d1, d6", d7, d1, i32, f2u(456.2489562), d6, i32, f2u(-7.2945676));
+    TESTINSN_bin("vrsqrts.f32 d0, d5, d2", d0, d5, i32, f2u(532.987), d2, i32, f2u(-0.0045876));
+    TESTINSN_bin("vrsqrts.f32 d10, d13, d15", d10, d13, i32, f2u(-485.2457), d15, i32, f2u(-567.245));
+    TESTINSN_bin("vrsqrts.f32 d10, d13, d15", d10, d13, i32, f2u(278456.45), d15, i32, f2u(8756.0076));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(876988654), d2, i32, f2u(1224808797));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(NAN));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(1.0));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(0.0));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(NAN), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(NAN));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(1.0));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(0.0));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(0.0), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(INFINITY), d2, i32, f2u(-INFINITY));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(NAN));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(1.0));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(0.0));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(INFINITY));
+    TESTINSN_bin("vrsqrts.f32 d0, d1, d2", d0, d1, i32, f2u(-INFINITY), d2, i32, f2u(-INFINITY));
+
+    printf("---- VRSQRTE (fp) ----\n");
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, f2u(3e22));
+    TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(3.2));
+    TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, f2u(3e22));
+    TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(3e9));
+    TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-0.5));
+    TESTINSN_un("vrsqrte.f32 d15, d4", d15, d4, i32, f2u(-7.1));
+    TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(8.0 - 1.0/1024.0));
+    TESTINSN_un("vrsqrte.f32 d12, d8", d12, d8, i32, f2u(-8.0 + 1.0/1024.0));
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, 7);
+    TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, 1 << 31); 
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
+    TESTINSN_un("vrsqrte.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, 7);
+    TESTINSN_un("vrsqrte.f32 d10, d11", d10, d11, i32, 1 << 31); 
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) + 1);
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, (1U << 31) - 1);
+    TESTINSN_un("vrsqrte.f32 d0, d14", d0, d14, i32, 0x30a0bcef);
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(NAN));
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(0.0));
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(INFINITY));
+    TESTINSN_un("vrsqrte.f32 d0, d1", d0, d1, i32, f2u(-INFINITY));
+
+    return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.stdout.exp
new file mode 100644 (file)
index 0000000..6ec95e4
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.stdout.exp
@@ -0,0 +1,3133 @@
+----- VMOV (immediate) -----
+vmov.i32 d0, #0x7 :: Qd 0x00000007 0x00000007
+vmov.i16 d1, #0x7 :: Qd 0x00070007 0x00070007
+vmov.i8 d2, #0x7 :: Qd 0x07070707 0x07070707
+vmov.i32 d5, #0x700 :: Qd 0x00000700 0x00000700
+vmov.i16 d7, #0x700 :: Qd 0x07000700 0x07000700
+vmov.i32 d10, #0x70000 :: Qd 0x00070000 0x00070000
+vmov.i32 d12, #0x7000000 :: Qd 0x07000000 0x07000000
+vmov.i32 d13, #0x7FF :: Qd 0x000007ff 0x000007ff
+vmov.i32 d14, #0x7FFFF :: Qd 0x0007ffff 0x0007ffff
+vmov.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0xff0000ff 0x00ffff00
+----- VMVN (immediate) -----
+vmvn.i32 d0, #0x7 :: Qd 0xfffffff8 0xfffffff8
+vmvn.i16 d1, #0x7 :: Qd 0xfff8fff8 0xfff8fff8
+vmvn.i8 d2, #0x7 :: Qd 0xf8f8f8f8 0xf8f8f8f8
+vmvn.i32 d5, #0x700 :: Qd 0xfffff8ff 0xfffff8ff
+vmvn.i16 d7, #0x700 :: Qd 0xf8fff8ff 0xf8fff8ff
+vmvn.i32 d10, #0x70000 :: Qd 0xfff8ffff 0xfff8ffff
+vmvn.i32 d13, #0x7000000 :: Qd 0xf8ffffff 0xf8ffffff
+vmvn.i32 d11, #0x7FF :: Qd 0xfffff800 0xfffff800
+vmvn.i32 d14, #0x7FFFF :: Qd 0xfff80000 0xfff80000
+vmvn.i64 d15, #0xFF0000FF00FFFF00 :: Qd 0x00ffff00 0xff0000ff
+----- VORR (immediate) -----
+vorr.i32 d0, #0x7 :: Qd 0x55555557 0x55555557
+vorr.i16 d2, #0x7 :: Qd 0x55575557 0x55575557
+vorr.i32 d8, #0x700 :: Qd 0x55555755 0x55555755
+vorr.i16 d6, #0x700 :: Qd 0x57555755 0x57555755
+vorr.i32 d14, #0x70000 :: Qd 0x55575555 0x55575555
+vorr.i32 d15, #0x7000000 :: Qd 0x57555555 0x57555555
+----- VBIC (immediate) -----
+vbic.i32 d0, #0x7 :: Qd 0x55555550 0x55555550
+vbic.i16 d3, #0x7 :: Qd 0x55505550 0x55505550
+vbic.i32 d5, #0x700 :: Qd 0x55555055 0x55555055
+vbic.i16 d8, #0x700 :: Qd 0x50555055 0x50555055
+vbic.i32 d10, #0x70000 :: Qd 0x55505555 0x55505555
+vbic.i32 d15, #0x7000000 :: Qd 0x50555555 0x50555555
+---- VMVN (register) ----
+vmvn d0, d1 :: Qd 0xffffffe7 0xffffffe7  Qm (i32)0x00000018
+vmvn d10, d15 :: Qd 0xffffffe7 0xffffffe7  Qm (i32)0x00000018
+vmvn d0, d14 :: Qd 0xffffffe7 0xffffffe7  Qm (i32)0x00000018
+---- VMOV (register) ----
+vmov d0, d1 :: Qd 0x00000018 0x00000018  Qm (i32)0x00000018
+vmov d10, d15 :: Qd 0x00000018 0x00000018  Qm (i32)0x00000018
+vmov d0, d14 :: Qd 0x00000018 0x00000018  Qm (i32)0x00000018
+---- VDUP (ARM core register) (tested indirectly) ----
+vmov d0, d1 :: Qd 0x07070707 0x07070707  Qm (i8)0x00000007
+vmov d10, d11 :: Qd 0x00070007 0x00070007  Qm (i16)0x00000007
+vmov d0, d15 :: Qd 0x00000007 0x00000007  Qm (i32)0x00000007
+---- VADD ----
+vadd.i32 d0, d1, d2 :: Qd 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078
+vadd.i64 d0, d1, d2 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vadd.i32 d0, d1, d2 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vadd.i16 d0, d1, d2 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vadd.i8 d0, d1, d2 :: Qd 0x00000004 0x00000004  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vadd.i8 d0, d1, d2 :: Qd 0x00000003 0x00000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vadd.i16 d0, d1, d2 :: Qd 0x00000003 0x00000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vadd.i32 d0, d1, d2 :: Qd 0x00000003 0x00000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vadd.i64 d0, d1, d2 :: Qd 0x00000004 0x00000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vadd.i32 d10, d11, d12 :: Qd 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078
+vadd.i64 d13, d14, d15 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078
+---- VSUB ----
+vsub.i32 d0, d1, d2 :: Qd 0xffffffa0 0xffffffa0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vsub.i64 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vsub.i32 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vsub.i16 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vsub.i8 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vsub.i8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vsub.i16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vsub.i32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vsub.i64 d0, d1, d2 :: Qd 0xfffffffe 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vsub.i32 d10, d11, d12 :: Qd 0xffffffa0 0xffffffa0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vsub.i64 d13, d14, d15 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+---- VAND ----
+vand d0, d1, d2 :: Qd 0x00240024 0x00240024  Qm (i8)0x00000024  Qn (i16)0x00000077
+vand d4, d6, d5 :: Qd 0x00570057 0x00570057  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vand d10, d11, d12 :: Qd 0xecececec 0xecececec  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vand d15, d15, d15 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+---- VBIC ----
+vbic d0, d1, d2 :: Qd 0x24002400 0x24002400  Qm (i8)0x00000024  Qn (i16)0x00000077
+vbic d4, d6, d5 :: Qd 0xffa8ffa8 0xffa8ffa8  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vbic d10, d11, d12 :: Qd 0x12121212 0x12121212  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vbic d15, d15, d15 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+---- VORR ----
+vorr d0, d1, d2 :: Qd 0x24772477 0x24772477  Qm (i8)0x00000024  Qn (i16)0x00000073
+vorr d7, d3, d0 :: Qd 0x24ff24ff 0x24ff24ff  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vorr d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vorr d2, d3, d15 :: Qd 0x0000003f 0x0000003f  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VORN ----
+vorn d0, d1, d2 :: Qd 0xffacffac 0xffacffac  Qm (i8)0x00000024  Qn (i16)0x00000073
+vorn d7, d3, d0 :: Qd 0xff24ff24 0xff24ff24  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vorn d4, d4, d4 :: Qd 0xffffffff 0xffffffff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vorn d2, d3, d15 :: Qd 0xffffffe4 0xffffffe4  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VEOR ----
+veor d0, d1, d2 :: Qd 0x24532453 0x24532453  Qm (i8)0x00000024  Qn (i16)0x00000077
+veor d4, d6, d5 :: Qd 0xffa8ffa8 0xffa8ffa8  Qm (i8)0x000000ff  Qn (i16)0x00000057
+veor d10, d11, d12 :: Qd 0x13131313 0x13131313  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+veor d15, d15, d15 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+veor d0, d1, d2 :: Qd 0x24572457 0x24572457  Qm (i8)0x00000024  Qn (i16)0x00000073
+veor d7, d3, d0 :: Qd 0x24db24db 0x24db24db  Qm (i8)0x00000024  Qn (i16)0x000000ff
+veor d4, d4, d4 :: Qd 0x00000000 0x00000000  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+veor d2, d3, d15 :: Qd 0x0000003b 0x0000003b  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VBSL ----
+vbsl d0, d1, d2 :: Qd 0x04260426 0x04260426  Qm (i8)0x00000024  Qn (i16)0x00000077
+vbsl d4, d6, d5 :: Qd 0x55575557 0x55575557  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vbsl d10, d11, d12 :: Qd 0xfcfcfcfc 0xfcfcfcfc  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vbsl d15, d15, d15 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+vbsl d0, d1, d2 :: Qd 0x04260426 0x04260426  Qm (i8)0x00000024  Qn (i16)0x00000073
+vbsl d7, d3, d0 :: Qd 0x04ae04ae 0x04ae04ae  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vbsl d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vbsl d2, d3, d15 :: Qd 0x0000000e 0x0000000e  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VBIT ----
+vbit d0, d1, d2 :: Qd 0x55245524 0x55245524  Qm (i8)0x00000024  Qn (i16)0x00000077
+vbit d4, d6, d5 :: Qd 0x55575557 0x55575557  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vbit d10, d11, d12 :: Qd 0xfcfcfcfc 0xfcfcfcfc  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vbit d15, d15, d15 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+vbit d0, d1, d2 :: Qd 0x55245524 0x55245524  Qm (i8)0x00000024  Qn (i16)0x00000073
+vbit d7, d3, d0 :: Qd 0x55245524 0x55245524  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vbit d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vbit d2, d3, d15 :: Qd 0x55555544 0x55555544  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VBIF ----
+vbif d0, d1, d2 :: Qd 0x24552455 0x24552455  Qm (i8)0x00000024  Qn (i16)0x00000077
+vbif d4, d6, d5 :: Qd 0xfffdfffd 0xfffdfffd  Qm (i8)0x000000ff  Qn (i16)0x00000057
+vbif d10, d11, d12 :: Qd 0x57575757 0x57575757  Qm (i8)0x000000fe  Qn (i8)0x000000ed
+vbif d15, d15, d15 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff
+vbif d0, d1, d2 :: Qd 0x24552455 0x24552455  Qm (i8)0x00000024  Qn (i16)0x00000073
+vbif d7, d3, d0 :: Qd 0x24552455 0x24552455  Qm (i8)0x00000024  Qn (i16)0x000000ff
+vbif d4, d4, d4 :: Qd 0x00ff00ff 0x00ff00ff  Qm (i16)0x000000ff  Qn (i16)0x000000ff
+vbif d2, d3, d15 :: Qd 0x00000035 0x00000035  Qm (i32)0x00000024  Qn (i32)0x0000001f
+---- VEXT ----
+vext.8 d0, d1, d2, #0 :: Qd 0x77777777 0x77777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 d0, d1, d2, #1 :: Qd 0xff777777 0x77777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 d0, d1, d2, #7 :: Qd 0xffffffff 0xffffff77  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 d0, d1, d2, #6 :: Qd 0xffffffff 0xffff7777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 d10, d11, d12, #4 :: Qd 0xffffffff 0x77777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+vext.8 d0, d5, d15, #5 :: Qd 0xffffffff 0xff777777  Qm (i8)0x00000077  Qn (i8)0x000000ff
+---- VHADD ----
+vhadd.s32 d0, d1, d2 :: Qd 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhadd.s32 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.s16 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.s8 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.s8 d0, d1, d2 :: Qd 0x03030303 0x03030303  Qm (i8)0x0000008d  Qn (i8)0x00000079
+vhadd.s8 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.s16 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.s32 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.s32 d10, d11, d12 :: Qd 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhadd.u32 d0, d1, d2 :: Qd 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhadd.u32 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.u16 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.u8 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhadd.u8 d0, d1, d2 :: Qd 0x83838383 0x83838383  Qm (i8)0x0000008d  Qn (i8)0x00000079
+vhadd.u8 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.u16 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.u32 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhadd.u32 d10, d11, d12 :: Qd 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VHSUB ----
+vhsub.s32 d0, d1, d2 :: Qd 0xffffffd0 0xffffffd0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhsub.s32 d0, d1, d2 :: Qd 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.s16 d0, d1, d2 :: Qd 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.s8 d0, d1, d2 :: Qd 0x0000008a 0x0000008a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.s8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.s16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.s32 d10, d11, d12 :: Qd 0xffffffd0 0xffffffd0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhsub.u32 d0, d1, d2 :: Qd 0xffffffd0 0xffffffd0  Qm (i32)0x00000018  Qn (i32)0x00000078
+vhsub.u32 d0, d1, d2 :: Qd 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.u16 d0, d1, d2 :: Qd 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.u8 d0, d1, d2 :: Qd 0x0000000a 0x0000000a  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vhsub.u8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vhsub.u32 d10, d11, d12 :: Qd 0xffffffd0 0xffffffd0  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VQADD ----
+vqadd.s32 d0, d1, d2 :: Qd 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.s32 d0, d1, d2 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.s16 d0, d1, d2 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.s8 d0, d1, d2 :: Qd 0x00000004 0x00000004  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.s8 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.s16 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.s32 d0, d1, d2 :: Qd 0x80000000 0x80000000  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.s32 d10, d11, d12 :: Qd 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.u32 d0, d1, d2 :: Qd 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.u32 d0, d1, d2 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.u16 d0, d1, d2 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqadd.u8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 08000000
+vqadd.u8 d0, d1, d2 :: Qd 0xff000003 0xff000003  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.u16 d0, d1, d2 :: Qd 0xffff0003 0xffff0003  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqadd.u32 d10, d11, d12 :: Qd 0x00000090 0x00000090  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+---- VQSUB ----
+vqsub.s32 d0, d1, d2 :: Qd 0xffffffa0 0xffffffa0  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.s32 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.s16 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.s8 d0, d1, d2 :: Qd 0x00000080 0x00000080  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 08000000
+vqsub.s8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqsub.s16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqsub.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqsub.s32 d10, d11, d12 :: Qd 0xffffffa0 0xffffffa0  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+vqsub.u32 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.u16 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.u8 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078  fpscr: 00000000
+vqsub.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqsub.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqsub.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 08000000
+vqsub.u32 d10, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+---- VRHADD ----
+vrhadd.s32 d0, d1, d2 :: Qd 0x00000049 0x00000049  Qm (i32)0x00000019  Qn (i32)0x00000078
+vrhadd.s32 d0, d1, d2 :: Qd 0x00000049 0x00000049  Qm (i32)0x00000019  Qn (i32)0x00000079
+vrhadd.s32 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.s16 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.s8 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.s8 d5, d7, d5 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.s16 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.s32 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.s32 d10, d11, d12 :: Qd 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+vrhadd.u32 d0, d1, d2 :: Qd 0x00000049 0x00000049  Qm (i32)0x00000019  Qn (i32)0x00000078
+vrhadd.u32 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.u16 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.u8 d0, d1, d2 :: Qd 0x00000082 0x00000082  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vrhadd.u8 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.u16 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vrhadd.u8 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.u16 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vrhadd.u8 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.u16 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.u32 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000004  Qn (i32)0x80000002
+vrhadd.u32 d10, d11, d12 :: Qd 0x00000048 0x00000048  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VCGT ----
+vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000078
+vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000079
+vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.s16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.s8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.s16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.s8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcgt.s16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcgt.s8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcgt.s8 d5, d7, d5 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.s16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.s8 d5, d7, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.s16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.s8 d5, d7, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.s16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.s32 d10, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000078
+vcgt.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.u8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcgt.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcgt.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcgt.u8 d0, d1, d2 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.u16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcgt.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcgt.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.u16 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcgt.u32 d10, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VCGE ----
+vcge.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000078
+vcge.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000079
+vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.s8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.s8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcge.s16 d0, d1, d2 :: Qd 0xffff0000 0xffff0000  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcge.s8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x0000008c
+vcge.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.s8 d5, d7, d5 :: Qd 0xffffff00 0xffffff00  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.s16 d0, d1, d2 :: Qd 0xffff0000 0xffff0000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.s8 d5, d7, d5 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.s16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.s32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.s32 d10, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+vcge.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000019  Qn (i32)0x00000078
+vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000003  Qn (i32)0x80000002
+vcge.u8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.u16 d0, d1, d2 :: Qd 0xffff0000 0xffff0000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vcge.u8 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.u16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.u32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000002  Qn (i32)0x80000002
+vcge.u32 d10, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VSHL (register) ----
+vshl.s8 d0, d1, d2 :: Qd 0x00000030 0x00000030  Qm (i32)0x00000018  Qn (i32)0x00000001
+vshl.s8 d8, d1, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000008
+vshl.s8 d10, d31, d7 :: Qd 0x00000080 0x00000080  Qm (i32)0x00000018  Qn (i32)0x00000004
+vshl.s16 d3, d8, d11 :: Qd 0x00000038 0x00000038  Qm (i32)0x0000000e  Qn (i32)0x00000002
+vshl.s16 d5, d12, d14 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000001
+vshl.s16 d15, d2, d1 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x0000000b
+vshl.s32 d9, d12, d19 :: Qd 0x00000008 0x00000008  Qm (i32)0x80000002  Qn (i32)0x00000002
+vshl.s32 d11, d22, d0 :: Qd 0xfffff000 0xfffff000  Qm (i32)0xffffffff  Qn (i32)0x0000000c
+vshl.s32 d5, d2, d3 :: Qd 0x00000000 0x00000000  Qm (i32)0x40000000  Qn (i32)0x00000015
+vshl.s64 d15, d12, d4 :: Qd 0x00500000 0x00500000  Qm (i32)0x00000005  Qn (i32)0x00000014
+vshl.s64 d8, d2, d4 :: Qd 0x000000f0 0x000000f0  Qm (i32)0x0000000f  Qn (i32)0x00000004
+vshl.s64 d5, d12, d4 :: Qd 0x60000000 0x40000000  Qm (i32)0x80000001  Qn (i32)0x0000001e
+vshl.s64 d15, d2, d4 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffabcd59  Qn (i32)0xabcdefab
+vshl.s64 d8, d2, d4 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000000f  Qn (i32)0x00400bb5
+vshl.s64 d5, d12, d4 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000001  Qn (i32)0x030abcff
+vshl.u8 d0, d1, d2 :: Qd 0x00000030 0x00000030  Qm (i32)0x00000018  Qn (i32)0x00000001
+vshl.u8 d8, d1, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000008
+vshl.u8 d10, d11, d7 :: Qd 0x00000080 0x00000080  Qm (i32)0x00000018  Qn (i32)0x00000004
+vshl.u16 d3, d8, d11 :: Qd 0x00000038 0x00000038  Qm (i32)0x0000000e  Qn (i32)0x00000002
+vshl.u16 d5, d12, d14 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000001
+vshl.u16 d15, d2, d1 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x0000000b
+vshl.u32 d9, d12, d15 :: Qd 0x00000008 0x00000008  Qm (i32)0x80000002  Qn (i32)0x00000002
+vshl.u32 d11, d2, d0 :: Qd 0xfffff000 0xfffff000  Qm (i32)0xffffffff  Qn (i32)0x0000000c
+vshl.u32 d5, d2, d3 :: Qd 0x00000000 0x00000000  Qm (i32)0x40000000  Qn (i32)0x00000015
+vshl.u64 d15, d12, d4 :: Qd 0x00500000 0x00500000  Qm (i32)0x00000005  Qn (i32)0x00000014
+vshl.u64 d8, d2, d4 :: Qd 0x000000f0 0x000000f0  Qm (i32)0x0000000f  Qn (i32)0x00000004
+vshl.u64 d5, d12, d4 :: Qd 0x60000000 0x40000000  Qm (i32)0x80000001  Qn (i32)0x0000001e
+vshl.u64 d15, d2, d4 :: Qd 0x00000000 0x00000000  Qm (i32)0xffabcd59  Qn (i32)0xabcdefab
+vshl.u64 d8, d2, d4 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000000f  Qn (i32)0x00400bb5
+vshl.u64 d5, d12, d4 :: Qd 0x40000000 0xc0000000  Qm (i32)0x80000001  Qn (i32)0x030abcff
+---- VQSHL (register) ----
+vqshl.s64 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001  fpscr: 00000000
+vqshl.s64 d3, d4, d5 :: Qd 0xffffff03 0xffffff02  Qm (i32)0xffffff81  Qn (i32)0x00000001  fpscr: 00000000
+vqshl.s64 d3, d4, d5 :: Qd 0xfffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd  fpscr: 00000000
+vqshl.s64 d0, d1, d2 :: Qd 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e  fpscr: 00000000
+vqshl.s64 d13, d14, d31 :: Qd 0xffffffff 0xfffffbff  Qm (i32)0xffffffef  Qn (i32)0xffffffe6  fpscr: 00000000
+vqshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4  fpscr: 00000000
+vqshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2  fpscr: 00000000
+vqshl.s32 d2, d8, d4 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc  fpscr: 00000000
+vqshl.s32 d12, d11, d13 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff88  Qn (i32)0xfffffff7  fpscr: 00000000
+vqshl.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9  fpscr: 00000000
+vqshl.s32 d9, d30, d11 :: Qd 0xc0000004 0xc0000004  Qm (i32)0x80000008  Qn (i32)0xffffffff  fpscr: 00000000
+vqshl.s32 d13, d3, d5 :: Qd 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003  fpscr: 00000000
+vqshl.s16 d11, d10, d2 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1  fpscr: 00000000
+vqshl.s16 d3, d14, d7 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd  fpscr: 00000000
+vqshl.s16 d0, d11, d2 :: Qd 0xc0000080 0xc0000080  Qm (i32)0x80000100  Qn (i32)0xffffffff  fpscr: 00000000
+vqshl.s16 d1, d2, d3 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1  fpscr: 00000000
+vqshl.s16 d3, d4, d5 :: Qd 0xd0000000 0xd0000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3  fpscr: 00000000
+vqshl.s16 d0, d15, d2 :: Qd 0x00007fff 0x00007fff  Qm (i32)0x00000001  Qn (i32)0x0000001e  fpscr: 08000000
+vqshl.s8 d2, d7, d11 :: Qd 0xffffff80 0xffffff80  Qm (i32)0xffffffff  Qn (i32)0x00000028  fpscr: 08000000
+vqshl.s8 d13, d1, d2 :: Qd 0xffffff80 0xffffff80  Qm (i32)0xfffffffc  Qn (i32)0x0000001e  fpscr: 08000000
+vqshl.s8 d3, d7, d5 :: Qd 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003  fpscr: 00000000
+vqshl.s8 d10, d11, d12 :: Qd 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010  fpscr: 00000000
+vqshl.s8 d6, d7, d8 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002  fpscr: 00000000
+vqshl.s8 d10, d11, d12 :: Qd 0x0000007f 0x0000007f  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+vqshl.u64 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001  fpscr: 00000000
+vqshl.u64 d3, d4, d5 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff81  Qn (i32)0x00000001  fpscr: 08000000
+vqshl.u64 d3, d4, d5 :: Qd 0x1ffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd  fpscr: 00000000
+vqshl.u64 d0, d1, d2 :: Qd 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e  fpscr: 00000000
+vqshl.u64 d13, d14, d15 :: Qd 0x0000003f 0xfffffbff  Qm (i32)0xffffffef  Qn (i32)0xffffffe6  fpscr: 00000000
+vqshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4  fpscr: 00000000
+vqshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2  fpscr: 00000000
+vqshl.u32 d2, d8, d4 :: Qd 0x0fffffff 0x0fffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc  fpscr: 00000000
+vqshl.u32 d12, d31, d13 :: Qd 0x007fffff 0x007fffff  Qm (i32)0xffffff88  Qn (i32)0xfffffff7  fpscr: 00000000
+vqshl.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9  fpscr: 00000000
+vqshl.u32 d9, d10, d11 :: Qd 0x40000004 0x40000004  Qm (i32)0x80000008  Qn (i32)0xffffffff  fpscr: 00000000
+vqshl.u32 d13, d3, d5 :: Qd 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003  fpscr: 00000000
+vqshl.u16 d11, d10, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1  fpscr: 00000000
+vqshl.u16 d3, d14, d7 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd  fpscr: 00000000
+vqshl.u16 d0, d11, d2 :: Qd 0x40000080 0x40000080  Qm (i32)0x80000100  Qn (i32)0xffffffff  fpscr: 00000000
+vqshl.u16 d1, d2, d3 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1  fpscr: 00000000
+vqshl.u16 d3, d4, d5 :: Qd 0x50000000 0x50000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3  fpscr: 00000000
+vqshl.u16 d0, d15, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00000001  Qn (i32)0x0000001e  fpscr: 08000000
+vqshl.u8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000028  fpscr: 08000000
+vqshl.u8 d13, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffffc  Qn (i32)0x0000001e  fpscr: 08000000
+vqshl.u8 d3, d7, d5 :: Qd 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003  fpscr: 00000000
+vqshl.u8 d10, d11, d12 :: Qd 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010  fpscr: 00000000
+vqshl.u8 d6, d7, d8 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002  fpscr: 00000000
+vqshl.u8 d10, d11, d12 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+---- VQSHL / VQSHLU (immediate) ----
+vqshl.s64 d0, d1, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshl.s64 d31, d30, #1 :: Qd 0xffffff03 0xffffff02  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.s64 d5, d4, #0 :: Qd 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.s64 d5, d4, #63 :: Qd 0x7fffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s64 d5, d4, #60 :: Qd 0x7fffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s64 d5, d4, #59 :: Qd 0x7fffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s64 d5, d4, #58 :: Qd 0x7fffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s64 d5, d4, #17 :: Qd 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.s64 d5, d4, #63 :: Qd 0x80000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqshl.s64 d5, d4, #60 :: Qd 0xf0000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqshl.s64 d5, d4, #7 :: Qd 0x80000000 0x00000000  Qm (i32)0x80000002  fpscr 08000000
+vqshl.s32 d10, d11, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshl.s32 d31, d30, #1 :: Qd 0xffffff02 0xffffff02  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.s32 d5, d4, #0 :: Qd 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.s32 d5, d4, #31 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s32 d5, d4, #28 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s32 d5, d4, #27 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s32 d5, d4, #26 :: Qd 0x40000000 0x40000000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.s32 d5, d4, #17 :: Qd 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.s32 d5, d4, #31 :: Qd 0x80000000 0x80000000  Qm (i32)0xffffffff  fpscr 00000000
+vqshl.s32 d5, d4, #29 :: Qd 0xe0000000 0xe0000000  Qm (i32)0xffffffff  fpscr 00000000
+vqshl.s32 d5, d4, #7 :: Qd 0x80000000 0x80000000  Qm (i32)0x80000002  fpscr 08000000
+vqshl.s16 d9, d8, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshl.s16 d31, d30, #1 :: Qd 0xfffeff02 0xfffeff02  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.s16 d5, d4, #0 :: Qd 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.s16 d9, d8, #15 :: Qd 0x00007fff 0x00007fff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s16 d5, d4, #12 :: Qd 0x00007fff 0x00007fff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s16 d5, d4, #11 :: Qd 0x00007fff 0x00007fff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s16 d5, d4, #10 :: Qd 0x00004000 0x00004000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.s16 d5, d4, #4 :: Qd 0x00000100 0x00000100  Qm (i32)0x00000010  fpscr 00000000
+vqshl.s16 d5, d4, #15 :: Qd 0x80008000 0x80008000  Qm (i32)0xffffffff  fpscr 00000000
+vqshl.s16 d5, d4, #12 :: Qd 0xf000f000 0xf000f000  Qm (i32)0xffffffff  fpscr 00000000
+vqshl.s16 d5, d4, #7 :: Qd 0x80000100 0x80000100  Qm (i32)0x80000002  fpscr 08000000
+vqshl.s8 d0, d1, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshl.s8 d31, d30, #1 :: Qd 0xfefefe80 0xfefefe80  Qm (i32)0xffffff81  fpscr 08000000
+vqshl.s8 d5, d4, #0 :: Qd 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.s8 d5, d4, #7 :: Qd 0x0000007f 0x0000007f  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s8 d25, d4, #4 :: Qd 0x0000007f 0x0000007f  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s8 d5, d4, #3 :: Qd 0x0000007f 0x0000007f  Qm (i32)0x00000010  fpscr 08000000
+vqshl.s8 d5, d4, #2 :: Qd 0x00000040 0x00000040  Qm (i32)0x00000010  fpscr 00000000
+vqshl.s8 d5, d4, #1 :: Qd 0x00000020 0x00000020  Qm (i32)0x00000010  fpscr 00000000
+vqshl.s8 d5, d4, #7 :: Qd 0x80808080 0x80808080  Qm (i32)0xffffffff  fpscr 00000000
+vqshl.s8 d5, d4, #5 :: Qd 0xe0e0e0e0 0xe0e0e0e0  Qm (i32)0xffffffff  fpscr 00000000
+vqshl.s8 d5, d4, #2 :: Qd 0x80000008 0x80000008  Qm (i32)0x80000002  fpscr 08000000
+vqshl.u64 d0, d1, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshl.u64 d31, d30, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff81  fpscr 08000000
+vqshl.u64 d5, d4, #0 :: Qd 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.u64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u64 d5, d4, #59 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u64 d5, d4, #58 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u64 d5, d4, #17 :: Qd 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshl.u64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshl.u64 d5, d4, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000002  fpscr 08000000
+vqshl.u32 d10, d11, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshl.u32 d31, d30, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff81  fpscr 08000000
+vqshl.u32 d5, d4, #0 :: Qd 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.u32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u32 d5, d4, #28 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u32 d5, d4, #27 :: Qd 0x80000000 0x80000000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u32 d5, d4, #26 :: Qd 0x40000000 0x40000000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u32 d5, d4, #17 :: Qd 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshl.u32 d5, d4, #29 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshl.u32 d5, d4, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000002  fpscr 08000000
+vqshl.u16 d9, d8, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshl.u16 d31, d30, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff81  fpscr 08000000
+vqshl.u16 d5, d4, #0 :: Qd 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.u16 d9, d8, #15 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u16 d5, d4, #12 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u16 d5, d4, #11 :: Qd 0x00008000 0x00008000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u16 d5, d4, #10 :: Qd 0x00004000 0x00004000  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u16 d5, d4, #4 :: Qd 0x00000100 0x00000100  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u16 d5, d4, #15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshl.u16 d5, d4, #12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshl.u16 d5, d4, #7 :: Qd 0xffff0100 0xffff0100  Qm (i32)0x80000002  fpscr 08000000
+vqshl.u8 d0, d1, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshl.u8 d31, d30, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff81  fpscr 08000000
+vqshl.u8 d5, d4, #0 :: Qd 0xffffff81 0xffffff81  Qm (i32)0xffffff81  fpscr 00000000
+vqshl.u8 d5, d4, #7 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u8 d5, d4, #4 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x00000010  fpscr 08000000
+vqshl.u8 d5, d4, #3 :: Qd 0x00000080 0x00000080  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u8 d5, d4, #2 :: Qd 0x00000040 0x00000040  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u8 d5, d4, #1 :: Qd 0x00000020 0x00000020  Qm (i32)0x00000010  fpscr 00000000
+vqshl.u8 d5, d4, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshl.u8 d5, d4, #5 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshl.u8 d5, d4, #2 :: Qd 0xff000008 0xff000008  Qm (i32)0x80000002  fpscr 08000000
+vqshlu.s64 d0, d1, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshlu.s64 d31, d30, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr 08000000
+vqshlu.s64 d5, d4, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr 08000000
+vqshlu.s64 d5, d4, #63 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s64 d5, d4, #60 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s64 d5, d4, #59 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s64 d5, d4, #58 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s64 d5, d4, #17 :: Qd 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s64 d5, d4, #63 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshlu.s64 d5, d4, #60 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshlu.s64 d5, d4, #7 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000002  fpscr 08000000
+vqshlu.s32 d10, d11, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshlu.s32 d31, d30, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr 08000000
+vqshlu.s32 d5, d4, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr 08000000
+vqshlu.s32 d5, d4, #31 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s32 d25, d24, #28 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s32 d5, d4, #27 :: Qd 0x80000000 0x80000000  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s32 d5, d4, #26 :: Qd 0x40000000 0x40000000  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s32 d5, d4, #17 :: Qd 0x00200000 0x00200000  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s32 d5, d24, #31 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshlu.s32 d5, d4, #29 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshlu.s32 d5, d4, #7 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000002  fpscr 08000000
+vqshlu.s16 d9, d8, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshlu.s16 d31, d30, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr 08000000
+vqshlu.s16 d5, d4, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr 08000000
+vqshlu.s16 d9, d8, #15 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s16 d5, d4, #12 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s16 d5, d4, #11 :: Qd 0x00008000 0x00008000  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s16 d5, d4, #10 :: Qd 0x00004000 0x00004000  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s16 d5, d4, #4 :: Qd 0x00000100 0x00000100  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s16 d15, d14, #15 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshlu.s16 d5, d4, #12 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshlu.s16 d5, d4, #7 :: Qd 0x00000100 0x00000100  Qm (i32)0x80000002  fpscr 08000000
+vqshlu.s8 d0, d1, #1 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  fpscr 00000000
+vqshlu.s8 d31, d30, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr 08000000
+vqshlu.s8 d5, d4, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff81  fpscr 08000000
+vqshlu.s8 d5, d4, #7 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s8 d5, d4, #4 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x00000010  fpscr 08000000
+vqshlu.s8 d5, d4, #3 :: Qd 0x00000080 0x00000080  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s8 d5, d4, #2 :: Qd 0x00000040 0x00000040  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s8 d5, d4, #1 :: Qd 0x00000020 0x00000020  Qm (i32)0x00000010  fpscr 00000000
+vqshlu.s8 d5, d4, #7 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshlu.s8 d5, d4, #5 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshlu.s8 d5, d4, #2 :: Qd 0x00000008 0x00000008  Qm (i32)0x80000002  fpscr 08000000
+---- VQRSHL (register) ----
+vqrshl.s64 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001  fpscr: 00000000
+vqrshl.s64 d3, d4, d5 :: Qd 0xffffff03 0xffffff02  Qm (i32)0xffffff81  Qn (i32)0x00000001  fpscr: 00000000
+vqrshl.s64 d3, d4, d5 :: Qd 0xfffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd  fpscr: 00000000
+vqrshl.s64 d0, d1, d2 :: Qd 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e  fpscr: 00000000
+vqrshl.s64 d13, d14, d15 :: Qd 0xffffffff 0xfffffc00  Qm (i32)0xffffffef  Qn (i32)0xffffffe6  fpscr: 00000000
+vqrshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4  fpscr: 00000000
+vqrshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2  fpscr: 00000000
+vqrshl.s32 d2, d8, d4 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc  fpscr: 00000000
+vqrshl.s32 d12, d11, d13 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff88  Qn (i32)0xfffffff7  fpscr: 00000000
+vqrshl.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9  fpscr: 00000000
+vqrshl.s32 d9, d10, d11 :: Qd 0xc0000004 0xc0000004  Qm (i32)0x80000008  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s32 d13, d3, d5 :: Qd 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003  fpscr: 00000000
+vqrshl.s16 d11, d10, d2 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1  fpscr: 00000000
+vqrshl.s16 d3, d14, d7 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd  fpscr: 00000000
+vqrshl.s16 d0, d31, d2 :: Qd 0xc0000080 0xc0000080  Qm (i32)0x80000100  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s16 d1, d2, d3 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1  fpscr: 00000000
+vqrshl.s16 d3, d4, d5 :: Qd 0xd0000000 0xd0000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3  fpscr: 00000000
+vqrshl.s16 d0, d15, d2 :: Qd 0x00007fff 0x00007fff  Qm (i32)0x00000001  Qn (i32)0x0000001e  fpscr: 08000000
+vqrshl.s8 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s16 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s32 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s8 d2, d7, d11 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s16 d2, d7, d11 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s32 d2, d7, d11 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s8 d2, d7, d11 :: Qd 0x000000ff 0x000000ff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s16 d2, d7, d11 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s32 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.s8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.s16 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.s32 d2, d7, d31 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.s8 d2, d7, d11 :: Qd 0xffffff80 0xffffff80  Qm (i32)0xffffffff  Qn (i32)0x00000028  fpscr: 08000000
+vqrshl.s8 d13, d1, d2 :: Qd 0xffffff80 0xffffff80  Qm (i32)0xfffffffc  Qn (i32)0x0000001e  fpscr: 08000000
+vqrshl.s8 d3, d7, d5 :: Qd 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003  fpscr: 00000000
+vqrshl.s8 d10, d11, d12 :: Qd 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010  fpscr: 00000000
+vqrshl.s8 d6, d7, d8 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002  fpscr: 00000000
+vqrshl.s8 d10, d11, d12 :: Qd 0x0000007f 0x0000007f  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+vqrshl.u64 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001  fpscr: 00000000
+vqrshl.u64 d3, d4, d5 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff81  Qn (i32)0x00000001  fpscr: 08000000
+vqrshl.u64 d3, d4, d5 :: Qd 0x1ffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd  fpscr: 00000000
+vqrshl.u64 d0, d1, d2 :: Qd 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e  fpscr: 00000000
+vqrshl.u64 d13, d14, d15 :: Qd 0x0000003f 0xfffffc00  Qm (i32)0xffffffef  Qn (i32)0xffffffe6  fpscr: 00000000
+vqrshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4  fpscr: 00000000
+vqrshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2  fpscr: 00000000
+vqrshl.u32 d2, d8, d4 :: Qd 0x0fffffff 0x0fffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc  fpscr: 00000000
+vqrshl.u32 d12, d11, d13 :: Qd 0x00800000 0x00800000  Qm (i32)0xffffff88  Qn (i32)0xfffffff7  fpscr: 00000000
+vqrshl.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9  fpscr: 00000000
+vqrshl.u32 d9, d10, d11 :: Qd 0x40000004 0x40000004  Qm (i32)0x80000008  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u32 d13, d3, d5 :: Qd 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003  fpscr: 00000000
+vqrshl.u16 d11, d10, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1  fpscr: 00000000
+vqrshl.u16 d3, d14, d7 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd  fpscr: 00000000
+vqrshl.u16 d0, d31, d2 :: Qd 0x40000080 0x40000080  Qm (i32)0x80000100  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u16 d1, d2, d3 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1  fpscr: 00000000
+vqrshl.u16 d3, d4, d5 :: Qd 0x50000000 0x50000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3  fpscr: 00000000
+vqrshl.u16 d0, d15, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00000001  Qn (i32)0x0000001e  fpscr: 08000000
+vqrshl.u8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000028  fpscr: 08000000
+vqrshl.u8 d2, d7, d11 :: Qd 0x80808080 0x80808080  Qm (i32)0xffffffff  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u8 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u16 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u32 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u8 d2, d7, d11 :: Qd 0x8080807f 0x8080807f  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u16 d2, d7, d11 :: Qd 0x80007fff 0x80007fff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u32 d2, d7, d11 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff  fpscr: 00000000
+vqrshl.u8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.u16 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.u32 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000  fpscr: 00000000
+vqrshl.u8 d13, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffffc  Qn (i32)0x0000001e  fpscr: 08000000
+vqrshl.u8 d3, d7, d5 :: Qd 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003  fpscr: 00000000
+vqrshl.u8 d10, d11, d12 :: Qd 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010  fpscr: 00000000
+vqrshl.u8 d6, d7, d8 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002  fpscr: 00000000
+vqrshl.u8 d10, d11, d12 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 08000000
+---- VRSHL (register) ----
+vrshl.s64 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001
+vrshl.s64 d3, d4, d5 :: Qd 0xffffff03 0xffffff02  Qm (i32)0xffffff81  Qn (i32)0x00000001
+vrshl.s64 d3, d4, d5 :: Qd 0xfffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd
+vrshl.s64 d0, d1, d2 :: Qd 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e
+vrshl.s64 d13, d14, d15 :: Qd 0xffffffff 0xfffffc00  Qm (i32)0xffffffef  Qn (i32)0xffffffe6
+vrshl.s64 d7, d8, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4
+vrshl.s32 d3, d4, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2
+vrshl.s32 d2, d8, d4 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc
+vrshl.s32 d12, d11, d13 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff88  Qn (i32)0xfffffff7
+vrshl.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9
+vrshl.s32 d9, d10, d11 :: Qd 0xc0000004 0xc0000004  Qm (i32)0x80000008  Qn (i32)0xffffffff
+vrshl.s32 d13, d3, d5 :: Qd 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003
+vrshl.s16 d11, d10, d2 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1
+vrshl.s16 d3, d14, d7 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd
+vrshl.s16 d0, d11, d2 :: Qd 0xc0000080 0xc0000080  Qm (i32)0x80000100  Qn (i32)0xffffffff
+vrshl.s16 d1, d2, d3 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1
+vrshl.s16 d3, d4, d5 :: Qd 0xd0000000 0xd0000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3
+vrshl.s16 d0, d15, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000001  Qn (i32)0x0000001e
+vrshl.s8 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.s16 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.s32 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.s8 d2, d7, d31 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.s16 d2, d7, d31 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.s32 d2, d7, d31 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.s8 d2, d7, d11 :: Qd 0x000000ff 0x000000ff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.s16 d2, d7, d11 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.s32 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.s8 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000
+vrshl.s16 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000
+vrshl.s32 d2, d7, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  Qn (i32)0x00000000
+vrshl.s8 d2, d7, d11 :: Qd 0xffffff00 0xffffff00  Qm (i32)0xffffffff  Qn (i32)0x00000028
+vrshl.s8 d13, d1, d2 :: Qd 0xffffff00 0xffffff00  Qm (i32)0xfffffffc  Qn (i32)0x0000001e
+vrshl.s8 d3, d7, d5 :: Qd 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003
+vrshl.s8 d10, d11, d12 :: Qd 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010
+vrshl.s8 d6, d7, d8 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002
+vrshl.s8 d10, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+vrshl.u64 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000001  Qn (i32)0x00000001
+vrshl.u64 d3, d4, d5 :: Qd 0xffffff03 0xffffff02  Qm (i32)0xffffff81  Qn (i32)0x00000001
+vrshl.u64 d3, d4, d5 :: Qd 0x1ffffff0 0x3ffffff0  Qm (i32)0xffffff81  Qn (i32)0xfffffffd
+vrshl.u64 d0, d1, d2 :: Qd 0x00040000 0x00040000  Qm (i32)0x00000010  Qn (i32)0x0000000e
+vrshl.u64 d13, d14, d15 :: Qd 0x0000003f 0xfffffc00  Qm (i32)0xffffffef  Qn (i32)0xffffffe6
+vrshl.u64 d7, d8, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0xffffffc4
+vrshl.u32 d3, d4, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000007f  Qn (i32)0xffffffe2
+vrshl.u32 d2, d8, d4 :: Qd 0x0fffffff 0x0fffffff  Qm (i32)0xfffffff5  Qn (i32)0xfffffffc
+vrshl.u32 d12, d11, d13 :: Qd 0x00800000 0x00800000  Qm (i32)0xffffff88  Qn (i32)0xfffffff7
+vrshl.u32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000022  Qn (i32)0xfffffff9
+vrshl.u32 d9, d10, d11 :: Qd 0x40000004 0x40000004  Qm (i32)0x80000008  Qn (i32)0xffffffff
+vrshl.u32 d13, d3, d5 :: Qd 0x40000000 0x40000000  Qm (i32)0x08000000  Qn (i32)0x00000003
+vrshl.u16 d11, d10, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xffffffe1
+vrshl.u16 d3, d14, d7 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000000  Qn (i32)0xfffffffd
+vrshl.u16 d0, d31, d2 :: Qd 0x40000080 0x40000080  Qm (i32)0x80000100  Qn (i32)0xffffffff
+vrshl.u16 d1, d2, d3 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000100  Qn (i32)0xffffffe1
+vrshl.u16 d3, d4, d5 :: Qd 0x50000000 0x50000000  Qm (i32)0xa0000000  Qn (i32)0xfffffff3
+vrshl.u16 d0, d15, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000001  Qn (i32)0x0000001e
+vrshl.u8 d2, d7, d11 :: Qd 0xffffff00 0xffffff00  Qm (i32)0xffffffff  Qn (i32)0x00000028
+vrshl.u8 d2, d7, d11 :: Qd 0x80808080 0x80808080  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.u8 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.u16 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.u32 d2, d7, d11 :: Qd 0x00000008 0x00000008  Qm (i32)0x0000000f  Qn (i32)0xffffffff
+vrshl.u8 d2, d7, d11 :: Qd 0x80808080 0x80808080  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.u16 d2, d7, d11 :: Qd 0x80008000 0x80008000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.u32 d2, d7, d11 :: Qd 0x80000000 0x80000000  Qm (i32)0xffffffff  Qn (i32)0xffffffff
+vrshl.u8 d2, d7, d31 :: Qd 0x8080807f 0x8080807f  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.u16 d2, d7, d31 :: Qd 0x80007fff 0x80007fff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.u32 d2, d7, d31 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0xfffffffe  Qn (i32)0xffffffff
+vrshl.u8 d13, d1, d2 :: Qd 0xffffff00 0xffffff00  Qm (i32)0xfffffffc  Qn (i32)0x0000001e
+vrshl.u8 d3, d7, d5 :: Qd 0x80000058 0x80000058  Qm (i32)0x8000000b  Qn (i32)0x00000003
+vrshl.u8 d10, d11, d12 :: Qd 0x00010000 0x00010000  Qm (i32)0x00010000  Qn (i32)0x00000010
+vrshl.u8 d6, d7, d8 :: Qd 0x40000000 0x40000000  Qm (i32)0x40000000  Qn (i32)0x00000002
+vrshl.u8 d10, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VMAX (integer) ----
+vmax.s32 d0, d1, d2 :: Qd 0x00000079 0x00000079  Qm (i32)0x00000019  Qn (i32)0x00000079
+vmax.s32 d0, d1, d2 :: Qd 0x000000fa 0x000000fa  Qm (i32)0x000000fa  Qn (i32)0x00000079
+vmax.s32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vmax.s16 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmax.s8 d0, d1, d2 :: Qd 0x00000078 0x00000078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vmax.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.s8 d5, d7, d5 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.s16 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.s32 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.s8 d5, d7, d5 :: Qd 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.s16 d0, d1, d2 :: Qd 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.s32 d0, d1, d2 :: Qd 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.s32 d10, d11, d12 :: Qd 0x00000078 0x00000078  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmax.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078  Qm (i32)0x00000019  Qn (i32)0x00000078
+vmax.u32 d0, d1, d2 :: Qd 0x000000fa 0x000000fa  Qm (i32)0x000000fa  Qn (i32)0x00000078
+vmax.u32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vmax.u16 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmax.u8 d0, d1, d2 :: Qd 0x00000078 0x00000078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vmax.u8 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.u16 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmax.u8 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.u16 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.u32 d0, d1, d2 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmax.u8 d0, d1, d2 :: Qd 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.u16 d0, d1, d2 :: Qd 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.u32 d0, d1, d2 :: Qd 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmax.u32 d10, d11, d12 :: Qd 0x00000078 0x00000078  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VMIN (integer) ----
+vmin.s32 d0, d1, d2 :: Qd 0x00000019 0x00000019  Qm (i32)0x00000019  Qn (i32)0x00000079
+vmin.s32 d0, d1, d2 :: Qd 0x00000079 0x00000079  Qm (i32)0x000000fa  Qn (i32)0x00000079
+vmin.s32 d0, d1, d2 :: Qd 0x00000078 0x00000078  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmin.s16 d0, d1, d2 :: Qd 0x00000078 0x00000078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vmin.s8 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vmin.s8 d5, d7, d5 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.s16 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.s32 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.s8 d5, d7, d5 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.s16 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.s32 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.s8 d5, d7, d5 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.s16 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.s32 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.s32 d10, d11, d12 :: Qd 0x00000018 0x00000018  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmin.u32 d0, d1, d2 :: Qd 0x00000019 0x00000019  Qm (i32)0x00000019  Qn (i32)0x00000078
+vmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078  Qm (i32)0x000000fa  Qn (i32)0x00000078
+vmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000078  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmin.u16 d0, d1, d2 :: Qd 0x00000078 0x00000078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vmin.u8 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vmin.u8 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.u16 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.u32 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmin.u8 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.u16 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.u32 d0, d1, d2 :: Qd 0x80000001 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vmin.u8 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.u16 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.u32 d0, d1, d2 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vmin.u32 d10, d11, d12 :: Qd 0x00000018 0x00000018  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VABD ----
+vabd.s32 d0, d1, d2 :: Qd 0x0000005f 0x0000005f  Qm (i32)0x00000019  Qn (i32)0x00000078
+vabd.s32 d0, d1, d2 :: Qd 0x00000060 0x00000060  Qm (i32)0x00000019  Qn (i32)0x00000079
+vabd.s32 d0, d1, d2 :: Qd 0x00000104 0x00000104  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vabd.s16 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabd.s8 d0, d1, d2 :: Qd 0x000000ec 0x000000ec  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabd.s8 d5, d7, d5 :: Qd 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.s8 d5, d7, d5 :: Qd 0x7f010101 0x7f010101  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vabd.s8 d5, d7, d5 :: Qd 0x7f010137 0x7f010137  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vabd.s16 d0, d1, d2 :: Qd 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.s32 d0, d1, d2 :: Qd 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.s8 d5, d7, d5 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.s16 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.s32 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.s8 d5, d7, d5 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.s16 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.s32 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.s32 d10, d11, d12 :: Qd 0x00000060 0x00000060  Qm (i32)0x00000018  Qn (i32)0x00000078
+vabd.u32 d0, d1, d2 :: Qd 0x0000005f 0x0000005f  Qm (i32)0x00000019  Qn (i32)0x00000078
+vabd.u32 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabd.u16 d0, d1, d2 :: Qd 0xfffffefc 0xfffffefc  Qm (i32)0xffffff74  Qn (i32)0x00000078
+vabd.u8 d0, d1, d2 :: Qd 0x00000014 0x00000014  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vabd.u8 d5, d7, d5 :: Qd 0x7fffff01 0x7fffff01  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vabd.u8 d5, d7, d5 :: Qd 0x7fffff37 0x7fffff37  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vabd.u8 d0, d1, d2 :: Qd 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.u16 d0, d1, d2 :: Qd 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.u32 d0, d1, d2 :: Qd 0x00000001 0x00000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vabd.u8 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.u16 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.u32 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000003
+vabd.u8 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.u16 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.u32 d0, d1, d2 :: Qd 0x00000002 0x00000002  Qm (i32)0x80000004  Qn (i32)0x80000002
+vabd.u32 d10, d11, d12 :: Qd 0x00000060 0x00000060  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VABA ----
+vaba.s32 d0, d1, d2 :: Qd 0x555555b4 0x555555b4  Qm (i32)0x00000019  Qn (i32)0x00000078
+vaba.s32 d0, d1, d2 :: Qd 0x555555b5 0x555555b5  Qm (i32)0x00000019  Qn (i32)0x00000079
+vaba.s32 d0, d1, d2 :: Qd 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.s16 d0, d1, d2 :: Qd 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.s8 d0, d1, d2 :: Qd 0x55555541 0x55555541  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.s8 d5, d7, d5 :: Qd 0x80000003 0x80000003  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.s8 d5, d7, d5 :: Qd 0xff010103 0xff010103  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vaba.s8 d5, d7, d5 :: Qd 0x7e00006f 0x7e00006f  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vaba.s16 d0, d1, d2 :: Qd 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.s32 d0, d1, d2 :: Qd 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.s8 d5, d7, d5 :: Qd 0x80000005 0x80000005  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.s16 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.s32 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.s8 d5, d7, d5 :: Qd 0x80000004 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.s16 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.s32 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.s32 d10, d11, d12 :: Qd 0x555555b5 0x555555b5  Qm (i32)0x00000018  Qn (i32)0x00000078
+vaba.u32 d0, d1, d2 :: Qd 0x555555b4 0x555555b4  Qm (i32)0x00000019  Qn (i32)0x00000078
+vaba.u32 d0, d1, d2 :: Qd 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.u16 d0, d1, d2 :: Qd 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.u8 d0, d1, d2 :: Qd 0x55555569 0x55555569  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vaba.u8 d5, d7, d5 :: Qd 0xffffff03 0xffffff03  Qm (i32)0xffffff01  Qn (i32)0x80000002
+vaba.u8 d5, d7, d5 :: Qd 0x7efefe6f 0x7efefe6f  Qm (i32)0x80000001  Qn (i32)0xffffff38
+vaba.u8 d0, d1, d2 :: Qd 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.u16 d0, d1, d2 :: Qd 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.u32 d0, d1, d2 :: Qd 0x55555556 0x55555556  Qm (i32)0x80000001  Qn (i32)0x80000002
+vaba.u8 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.u16 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.u32 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000001  Qn (i32)0x80000003
+vaba.u8 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.u16 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.u32 d0, d1, d2 :: Qd 0x55555557 0x55555557  Qm (i32)0x80000004  Qn (i32)0x80000002
+vaba.u32 d10, d11, d12 :: Qd 0x555555b5 0x555555b5  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VTST ----
+vtst.32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000018  Qn (i32)0x00000078
+vtst.32 d3, d4, d5 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vtst.16 d6, d7, d8 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vtst.8 d9, d10, d12 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vtst.8 d0, d1, d2 :: Qd 0xff000000 0xff000000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vtst.16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00004001  Qn (i32)0x00004001
+vtst.32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000001  Qn (i32)0x80000002
+vtst.8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x00000002
+vtst.16 d0, d1, d2 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00004001  Qn (i32)0x00004001
+vtst.32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000001  Qn (i32)0x80000002
+vtst.32 d10, d11, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VCEQ ----
+vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+vceq.i32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vceq.i16 d6, d7, d8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000078  Qn (i32)0x00000078
+vceq.i8 d9, d10, d12 :: Qd 0xffffff00 0xffffff00  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vceq.i8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00  Qm (i32)0x80000001  Qn (i32)0x80000002
+vceq.i16 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00004001  Qn (i32)0x00004001
+vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vceq.i8 d0, d1, d2 :: Qd 0x00ffff00 0x00ffff00  Qm (i32)0x80000001  Qn (i32)0x00000002
+vceq.i16 d0, d1, d2 :: Qd 0xffff0000 0xffff0000  Qm (i32)0x00000001  Qn (i32)0x00004001
+vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000001  Qn (i32)0x80000002
+vceq.i32 d10, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VMLA ----
+vmla.i32 d0, d1, d2 :: Qd 0x55554a15 0x55554a15  Qm (i32)0xffffffe8  Qn (i32)0x00000078
+vmla.i32 d6, d7, d8 :: Qd 0x555596f5 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmla.i16 d9, d11, d12 :: Qd 0x5555bd55 0x5555bd55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmla.i8 d0, d1, d2 :: Qd 0x555555b5 0x555555b5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmla.i8 d10, d11, d12 :: Qd 0x5555559f 0x5555559f  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmla.i16 d4, d5, d6 :: Qd 0x5555f557 0x5555f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmla.i32 d7, d8, d9 :: Qd 0xd5555557 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.i8 d10, d13, d12 :: Qd 0x5555559f 0x5555559f  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmla.i16 d4, d5, d6 :: Qd 0x55551751 0x55551751  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmla.i32 d7, d8, d9 :: Qd 0xd5555557 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.i32 d10, d11, d15 :: Qd 0x55554a15 0x55554a15  Qm (i32)0x00000018  Qn (i32)0xffffff88
+---- VMLS ----
+vmls.i32 d0, d1, d2 :: Qd 0x55556095 0x55556095  Qm (i32)0xffffffe8  Qn (i32)0x00000078
+vmls.i32 d6, d7, d8 :: Qd 0x555596f5 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmls.i16 d9, d11, d12 :: Qd 0x5555ed55 0x5555ed55  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmls.i8 d0, d1, d2 :: Qd 0x555555b5 0x555555b5  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmls.i8 d10, d11, d12 :: Qd 0x5555550b 0x5555550b  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmls.i16 d4, d5, d6 :: Qd 0x5555b553 0x5555b553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmls.i32 d7, d8, d9 :: Qd 0xd5555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.i8 d10, d13, d12 :: Qd 0x5555550b 0x5555550b  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmls.i16 d4, d5, d6 :: Qd 0x55559359 0x55559359  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmls.i32 d7, d8, d9 :: Qd 0xd5555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.i32 d10, d11, d15 :: Qd 0x55556095 0x55556095  Qm (i32)0xffffffe8  Qn (i32)0x00000078
+---- VMUL ----
+vmul.i32 d0, d1, d2 :: Qd 0x00000b40 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmul.i32 d6, d7, d8 :: Qd 0xffffbe60 0xffffbe60  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmul.i16 d9, d11, d12 :: Qd 0x00006800 0x00006800  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmul.i8 d0, d1, d2 :: Qd 0x000000a0 0x000000a0  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vmul.i8 d10, d11, d12 :: Qd 0x0000004a 0x0000004a  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmul.i16 d4, d5, d6 :: Qd 0x0000a002 0x0000a002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmul.i32 d7, d8, d9 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmul.i8 d10, d11, d12 :: Qd 0x0000c00e 0x0000c00e  Qm (i32)0x0200feb2  Qn (i32)0x000020df
+vmul.i16 d4, d5, d6 :: Qd 0x00008866 0x00008866  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmul.i32 d7, d8, d9 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000000  Qn (i32)0x0000000c
+vmul.i8 d10, d13, d12 :: Qd 0x0000004a 0x0000004a  Qm (i32)0x00000021  Qn (i32)0x0000000a
+vmul.i16 d4, d5, d6 :: Qd 0x0000c1fc 0x0000c1fc  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmul.i32 d7, d8, d9 :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmul.i32 d10, d11, d15 :: Qd 0x00000b40 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmul.p8 q0, q1, q2 :: Qd 0x00000005 0x00000005  Qm (i32)0x00000003  Qn (i32)0x00000003
+vmul.p8 q0, q1, q2 :: Qd 0x00000044 0x00000044  Qm (i32)0x0000000c  Qn (i8)0x0000000f
+---- VMUL (by scalar) ----
+vmul.i32 d0, d1, d4[0] :: Qd 0x00000b40 0x00000b40  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmul.i32 d31, d8, d7[1] :: Qd 0xffffbe60 0xffffbe60  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmul.i16 d30, d9, d7[3] :: Qd 0x00000000 0x00000000  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmul.i16 d4, d5, d6[2] :: Qd 0x0000a002 0x0000a002  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmul.i32 d4, d8, d15[1] :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmul.i16 d4, d5, d6[0] :: Qd 0xdffe8866 0xdffe8866  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmul.i32 d7, d8, d1[1] :: Qd 0x00000000 0x00000000  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmul.i16 d4, d5, d6[0] :: Qd 0x2000c1fc 0x2000c1fc  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmul.i32 d7, d8, d1[1] :: Qd 0x80000002 0x80000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VMLA (by scalar) ----
+vmla.i32 d0, d1, d4[0] :: Qd 0x55556095 0x55556095  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmla.i32 d31, d8, d7[1] :: Qd 0x555513b5 0x555513b5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmla.i16 d30, d9, d7[3] :: Qd 0x55555555 0x55555555  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmla.i16 d4, d5, d6[2] :: Qd 0x5555f557 0x5555f557  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmla.i32 d4, d8, d15[1] :: Qd 0xd5555557 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.i16 d4, d5, d6[0] :: Qd 0x3553ddbb 0x3553ddbb  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmla.i32 d7, d8, d1[1] :: Qd 0x55555555 0x55555555  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmla.i16 d4, d5, d6[0] :: Qd 0x75551751 0x75551751  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmla.i32 d7, d8, d1[1] :: Qd 0xd5555557 0xd5555557  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VMLS (by scalar) ----
+vmls.i32 d0, d1, d4[0] :: Qd 0x5555557d 0x5555557d  Qm (i32)0x00000018  Qn (i32)0x00000078
+vmls.i32 d31, d8, d7[1] :: Qd 0x555596f5 0x555596f5  Qm (i32)0x0000008c  Qn (i32)0xffffff88
+vmls.i16 d30, d9, d7[3] :: Qd 0x55555555 0x55555555  Qm (i32)0x00000140  Qn (i32)0x00000120
+vmls.i16 d4, d5, d6[2] :: Qd 0x5555b553 0x5555b553  Qm (i32)0x00004001  Qn (i32)0x00002002
+vmls.i32 d4, d8, d15[1] :: Qd 0xd5555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.i16 d4, d5, d6[0] :: Qd 0x7557ccef 0x7557ccef  Qm (i32)0xffff9433  Qn (i32)0x00002002
+vmls.i32 d7, d8, d1[1] :: Qd 0x55555555 0x55555555  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmls.i16 d4, d5, d6[0] :: Qd 0x35559359 0x35559359  Qm (i32)0x100000fe  Qn (i32)0x00002002
+vmls.i32 d7, d8, d1[1] :: Qd 0xd5555553 0xd5555553  Qm (i32)0x80000001  Qn (i32)0x80000002
+---- VRSHR ----
+vrshr.s8 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vrshr.s8 d0, d1, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff
+vrshr.s16 d3, d4, #2 :: Qd 0x0000ffe1 0x0000ffe1  Qm (i32)0xffffff84
+vrshr.s32 d2, d5, #31 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff
+vrshr.s8 d6, d7, #7 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000ffff
+vrshr.s16 d8, d9, #12 :: Qd 0x00000000 0x00000000  Qm (i32)0xfffffff6
+vrshr.s32 d10, d11, #5 :: Qd 0x00000140 0x00000140  Qm (i32)0x000027fa
+vrshr.u8 d12, d13, #1 :: Qd 0x80808080 0x80808080  Qm (i32)0xffffffff
+vrshr.u16 d14, d15, #11 :: Qd 0x00200020 0x00200020  Qm (i32)0xffffffff
+vrshr.u32 d10, d11, #9 :: Qd 0x00000002 0x00000002  Qm (i32)0x000003e8
+vrshr.u8 d7, d13, #7 :: Qd 0x02020202 0x02020202  Qm (i32)0xffffffff
+vrshr.u16 d8, d1, #5 :: Qd 0x0000055e 0x0000055e  Qm (i32)0x0000abcf
+vrshr.u32 d12, d3, #15 :: Qd 0x00020000 0x00020000  Qm (i32)0xfffffe50
+vrshr.u64 d0, d1, #42 :: Qd 0x00000000 0x00400000  Qm (i32)0xffffffff
+vrshr.s64 d6, d7, #12 :: Qd 0x00000000 0xfac00001  Qm (i32)0x00000fac
+vrshr.u64 d8, d4, #9 :: Qd 0x0000001a 0x7c00001a  Qm (i32)0x000034f8
+vrshr.s64 d9, d12, #11 :: Qd 0x00000030 0x32c00030  Qm (i32)0x00018196
+---- VRSRA ----
+vrsra.s8 d0, d1, #1 :: Qd 0x55555555 0x55555555  Qm (i32)0xffffffff
+vrsra.s16 d3, d4, #2 :: Qd 0x55555536 0x55555536  Qm (i32)0xffffff84
+vrsra.s32 d2, d5, #31 :: Qd 0x55555555 0x55555555  Qm (i32)0xffffffff
+vrsra.s8 d6, d7, #7 :: Qd 0x55555555 0x55555555  Qm (i32)0x0000ffff
+vrsra.s16 d8, d9, #12 :: Qd 0x55555555 0x55555555  Qm (i32)0xfffffff6
+vrsra.s32 d10, d11, #5 :: Qd 0x55555695 0x55555695  Qm (i32)0x000027fa
+vrsra.u8 d12, d13, #1 :: Qd 0xd5d5d5d5 0xd5d5d5d5  Qm (i32)0xffffffff
+vrsra.u16 d14, d15, #11 :: Qd 0x55755575 0x55755575  Qm (i32)0xffffffff
+vrsra.u32 d10, d11, #9 :: Qd 0x55555557 0x55555557  Qm (i32)0x000003e8
+vrsra.u8 d7, d13, #7 :: Qd 0x57575757 0x57575757  Qm (i32)0xffffffff
+vrsra.u16 d8, d1, #5 :: Qd 0x55555ab3 0x55555ab3  Qm (i32)0x0000abcf
+vrsra.u32 d12, d3, #15 :: Qd 0x55575555 0x55575555  Qm (i32)0xfffffe50
+vrsra.u64 d0, d1, #42 :: Qd 0x55555555 0x55955555  Qm (i32)0xffffffff
+vrsra.s64 d6, d7, #12 :: Qd 0x55555556 0x50155556  Qm (i32)0x00000fac
+vrsra.u64 d8, d4, #9 :: Qd 0x5555556f 0xd155556f  Qm (i32)0x000034f8
+vrsra.s64 d9, d12, #11 :: Qd 0x55555585 0x88155585  Qm (i32)0x00018196
+---- VSHR ----
+vshr.s8 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshr.s8 d0, d1, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshr.s16 d3, d4, #2 :: Qd 0xffffffe1 0xffffffe1  Qm (i32)0xffffff84
+vshr.s32 d2, d5, #31 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshr.s8 d6, d7, #7 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x0000ffff
+vshr.s16 d8, d9, #12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffff6
+vshr.s32 d10, d11, #5 :: Qd 0x0000013f 0x0000013f  Qm (i32)0x000027fa
+vshr.u8 d12, d13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f  Qm (i32)0xffffffff
+vshr.u16 d14, d15, #11 :: Qd 0x001f001f 0x001f001f  Qm (i32)0xffffffff
+vshr.u32 d10, d11, #9 :: Qd 0x00000001 0x00000001  Qm (i32)0x000003e8
+vshr.u8 d7, d13, #7 :: Qd 0x01010101 0x01010101  Qm (i32)0xffffffff
+vshr.u16 d8, d1, #5 :: Qd 0x0000055e 0x0000055e  Qm (i32)0x0000abcf
+vshr.u32 d12, d3, #15 :: Qd 0x0001ffff 0x0001ffff  Qm (i32)0xfffffe50
+vshr.u64 d0, d1, #42 :: Qd 0x00000000 0x003fffff  Qm (i32)0xffffffff
+vshr.s64 d6, d7, #12 :: Qd 0x00000000 0xfac00000  Qm (i32)0x00000fac
+vshr.u64 d8, d4, #9 :: Qd 0x0000001a 0x7c00001a  Qm (i32)0x000034f8
+vshr.s64 d9, d12, #11 :: Qd 0x00000030 0x32c00030  Qm (i32)0x00018196
+---- VSRA ----
+vsra.s8 d0, d1, #1 :: Qd 0x54545454 0x54545454  Qm (i32)0xffffffff
+vsra.s16 d3, d4, #2 :: Qd 0x55545536 0x55545536  Qm (i32)0xffffff84
+vsra.s32 d2, d5, #31 :: Qd 0x55555554 0x55555554  Qm (i32)0xffffffff
+vsra.s8 d6, d7, #7 :: Qd 0x55555454 0x55555454  Qm (i32)0x0000ffff
+vsra.s16 d8, d9, #12 :: Qd 0x55545554 0x55545554  Qm (i32)0xfffffff6
+vsra.s32 d10, d11, #5 :: Qd 0x55555694 0x55555694  Qm (i32)0x000027fa
+vsra.u8 d12, d13, #1 :: Qd 0xd4d4d4d4 0xd4d4d4d4  Qm (i32)0xffffffff
+vsra.u16 d14, d15, #11 :: Qd 0x55745574 0x55745574  Qm (i32)0xffffffff
+vsra.u32 d10, d11, #9 :: Qd 0x55555556 0x55555556  Qm (i32)0x000003e8
+vsra.u8 d7, d13, #7 :: Qd 0x56565656 0x56565656  Qm (i32)0xffffffff
+vsra.u16 d8, d1, #5 :: Qd 0x55555ab3 0x55555ab3  Qm (i32)0x0000abcf
+vsra.u32 d12, d3, #15 :: Qd 0x55575554 0x55575554  Qm (i32)0xfffffe50
+vsra.u64 d0, d1, #42 :: Qd 0x55555555 0x55955554  Qm (i32)0xffffffff
+vsra.s64 d6, d7, #12 :: Qd 0x55555556 0x50155555  Qm (i32)0x00000fac
+vsra.u64 d8, d4, #9 :: Qd 0x5555556f 0xd155556f  Qm (i32)0x000034f8
+vsra.s64 d9, d12, #11 :: Qd 0x55555585 0x88155585  Qm (i32)0x00018196
+---- VSRI ----
+vsri.16 d0, d1, #1 :: Qd 0x7fff7fff 0x7fff7fff  Qm (i32)0xffffffff
+vsri.16 d3, d4, #2 :: Qd 0x7fff7fe1 0x7fff7fe1  Qm (i32)0xffffff84
+vsri.32 d2, d5, #31 :: Qd 0x55555555 0x55555555  Qm (i32)0xffffffff
+vsri.8 d6, d7, #7 :: Qd 0x54545555 0x54545555  Qm (i32)0x0000ffff
+vsri.16 d8, d9, #12 :: Qd 0x555f555f 0x555f555f  Qm (i32)0xfffffff6
+vsri.32 d10, d11, #5 :: Qd 0x5000013f 0x5000013f  Qm (i32)0x000027fa
+vsri.8 d12, d13, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f  Qm (i32)0xffffffff
+vsri.16 d14, d15, #11 :: Qd 0x555f555f 0x555f555f  Qm (i32)0xffffffff
+vsri.32 d10, d11, #9 :: Qd 0x55000001 0x55000001  Qm (i32)0x000003e8
+vsri.8 d7, d13, #7 :: Qd 0x55555555 0x55555555  Qm (i32)0xffffffff
+vsri.16 d8, d1, #5 :: Qd 0x5000555e 0x5000555e  Qm (i32)0x0000abcf
+vsri.32 d12, d3, #15 :: Qd 0x5555ffff 0x5555ffff  Qm (i32)0xfffffe50
+vsri.64 d0, d1, #42 :: Qd 0x55555555 0x557fffff  Qm (i32)0xffffffff
+vsri.64 d6, d7, #12 :: Qd 0x55500000 0xfac00000  Qm (i32)0x00000fac
+vsri.64 d8, d4, #9 :: Qd 0x5500001a 0x7c00001a  Qm (i32)0x000034f8
+vsri.64 d9, d12, #11 :: Qd 0x55400030 0x32c00030  Qm (i32)0x00018196
+---- VMOV (ARM core register to scalar) ----
+vmov.32 d0[0], r5 :: Qd 0x55555555 0x0000000d  Qm 0x0000000d
+vmov.32 d1[1], r3 :: Qd 0x0000000c 0x55555555  Qm 0x0000000c
+vmov.16 d0[0], r5 :: Qd 0x55555555 0x5555000d  Qm 0x0000000d
+vmov.16 d2[2], r6 :: Qd 0x5555000e 0x55555555  Qm 0x0000000e
+vmov.16 d3[3], r1 :: Qd 0x00115555 0x55555555  Qm 0x00000011
+vmov.8 d0[0], r5 :: Qd 0x55555555 0x5555550d  Qm 0x0000000d
+vmov.8 d0[1], r5 :: Qd 0x55555555 0x55550d55  Qm 0x0000000d
+vmov.8 d0[2], r5 :: Qd 0x55555555 0x550d5555  Qm 0x0000000d
+vmov.8 d0[3], r5 :: Qd 0x55555555 0x0d555555  Qm 0x0000000d
+vmov.8 d0[4], r5 :: Qd 0x5555550d 0x55555555  Qm 0x0000000d
+vmov.8 d0[5], r5 :: Qd 0x55550d55 0x55555555  Qm 0x0000000d
+vmov.8 d0[6], r5 :: Qd 0x550d5555 0x55555555  Qm 0x0000000d
+vmov.8 d31[7], r5 :: Qd 0x0d555555 0x55555555  Qm 0x0000000d
+---- VMOV (scalar toARM core register) ----
+vmov.32 r5, d0[0] :: Rd 0x11223344  Qm (i32)0x11223344
+vmov.32 r6, d5[1] :: Rd 0x11223344  Qm (i32)0x11223344
+vmov.u16 r5, d31[0] :: Rd 0x00003344  Qm (i32)0x11223344
+vmov.u16 r5, d30[1] :: Rd 0x00001122  Qm (i32)0x11223344
+vmov.u16 r5, d31[2] :: Rd 0x00003344  Qm (i32)0x11223344
+vmov.u16 r5, d31[3] :: Rd 0x00001122  Qm (i32)0x11223344
+vmov.u8 r2, d4[0] :: Rd 0x00000044  Qm (i32)0x11223344
+vmov.u8 r2, d4[1] :: Rd 0x00000033  Qm (i32)0x11223344
+vmov.u8 r2, d4[2] :: Rd 0x00000022  Qm (i32)0x11223344
+vmov.u8 r2, d4[3] :: Rd 0x00000011  Qm (i32)0x11223344
+vmov.u8 r2, d4[4] :: Rd 0x00000044  Qm (i32)0x11223344
+vmov.u8 r2, d4[5] :: Rd 0x00000033  Qm (i32)0x11223344
+vmov.u8 r2, d4[6] :: Rd 0x00000022  Qm (i32)0x11223344
+vmov.u8 r2, d4[7] :: Rd 0x00000011  Qm (i32)0x11223344
+vmov.s16 r5, d31[0] :: Rd 0xffff8080  Qm (i8)0x00000080
+vmov.s16 r5, d30[1] :: Rd 0xffff8080  Qm (i8)0x00000080
+vmov.s16 r5, d31[2] :: Rd 0xffff8080  Qm (i8)0x00000080
+vmov.s16 r5, d31[3] :: Rd 0xffff8080  Qm (i8)0x00000080
+vmov.s8 r2, d4[0] :: Rd 0xffffff80  Qm (i8)0x00000080
+vmov.s8 r2, d4[1] :: Rd 0xffffff80  Qm (i8)0x00000080
+vmov.s8 r2, d4[2] :: Rd 0xffffff80  Qm (i8)0x00000080
+vmov.s8 r2, d4[3] :: Rd 0xffffff80  Qm (i8)0x00000080
+vmov.s8 r2, d4[4] :: Rd 0xffffff80  Qm (i8)0x00000080
+vmov.s8 r2, d4[5] :: Rd 0xffffff82  Qm (i8)0x00000082
+vmov.s8 r2, d4[6] :: Rd 0xffffff81  Qm (i8)0x00000081
+vmov.s8 r2, d4[7] :: Rd 0xffffff83  Qm (i8)0x00000083
+---- VLD1 (multiple single elements) ----
+vld1.8 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b
+vld1.16 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b
+vld1.32 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b
+vld1.64 {d0} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b
+vld1.8 {d9} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b
+vld1.16 {d17} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b
+vld1.32 {d31} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b
+vld1.64 {d14} :: Result 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b 0x121f1e1f 0x131b1a1b
+vld1.8 {d0-d1} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d
+vld1.16 {d0-d1} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d
+vld1.32 {d5-d6} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d
+vld1.64 {d30-d31} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d
+vld1.8 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b
+vld1.16 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b
+vld1.32 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b
+vld1.64 {d0-d2} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x121f1e1f 0x131b1a1b
+vld1.8 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a
+vld1.16 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a
+vld1.32 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a
+vld1.64 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a
+---- VLD1 (single element to one lane) ----
+vld1.32 {d0[0]} :: Result 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555
+vld1.32 {d0[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f 0x55555555 0x121f1e1f
+vld1.16 {d1[0]} :: Result 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555
+vld1.16 {d1[1]} :: Result 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555
+vld1.16 {d1[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f 0x55555555 0x55551e1f
+vld1.16 {d1[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555 0x55555555 0x1e1f5555
+vld1.8 {d0[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555
+vld1.8 {d1[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555
+vld1.8 {d0[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55
+vld1.8 {d0[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f
+vld1.8 {d20[3]} :: Result 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555 0x1f555555 0x55555555
+vld1.8 {d0[2]} :: Result 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555 0x551f5555 0x55555555
+vld1.8 {d17[1]} :: Result 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555 0x55551f55 0x55555555
+vld1.8 {d30[0]} :: Result 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555
+---- VLD1 (single element to all lanes) ----
+vld1.8 {d0[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f
+vld1.16 {d0[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f
+vld1.32 {d0[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f
+vld1.8 {d9[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f
+vld1.16 {d17[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f
+vld1.32 {d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f
+vld1.8 {d0[],d1[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f 0x1f1f1f1f
+vld1.16 {d0[],d1[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f 0x1e1f1e1f
+vld1.32 {d5[],d6[]} :: Result 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f 0x121f1e1f
+---- VLD2 (multiple 2-elements) ----
+vld2.8 {d30-d31} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f
+vld2.16 {d0-d1} :: Result 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c
+vld2.32 {d0-d1} :: Result 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d
+vld2.8 {d10,d12} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f 0x1b1b1f1f 0x1d1d1c1c 0x131a121e 0x1519141f
+vld2.16 {d20,d22} :: Result 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c 0x1a1b1e1f 0x191d1f1c 0x131b121f 0x151d141c
+vld2.32 {d0,d2} :: Result 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d 0x121f1e1f 0x141c1f1c 0x131b1a1b 0x151d191d
+vld2.8 {d0-d3} :: Result 0x1b1b1f1f 0x1d1d1c1c 0x2c2b2f2f 0x2d2a2a2b 0x131a121e 0x1519141f 0x242b232e 0x262d252e
+vld2.16 {d20-d23} :: Result 0x1a1b1e1f 0x191d1f1c 0x2b2b2e2f 0x2d2a2e2b 0x131b121f 0x151d141c 0x242c232f 0x262d252a
+vld2.32 {d0-d3} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a
+---- VLD2 (single 2-element structure to one lane) ----
+vld2.32 {d0[0],d1[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555
+vld2.32 {d0[1],d1[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b
+vld2.32 {d0[0],d2[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555
+vld2.32 {d0[1],d2[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b
+vld2.16 {d1[0],d2[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555
+vld2.16 {d1[1],d2[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555
+vld2.16 {d1[2],d2[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f
+vld2.16 {d1[3],d2[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555
+vld2.16 {d1[0],d3[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555
+vld2.16 {d1[1],d3[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555
+vld2.16 {d1[2],d3[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551e1f 0x55555555 0x5555121f
+vld2.16 {d1[3],d3[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1e1f5555 0x55555555 0x121f5555
+vld2.8 {d0[7],d1[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555
+vld2.8 {d1[6],d2[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555
+vld2.8 {d0[5],d1[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55
+vld2.8 {d0[4],d1[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e
+vld2.8 {d20[3],d21[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555
+vld2.8 {d0[2],d1[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555
+vld2.8 {d17[1],d18[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555
+vld2.8 {d30[0],d31[0]} :: Result 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555
+---- VLD2 (2-elements to all lanes) ----
+vld2.8 {d0[],d1[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e
+vld2.16 {d0[],d1[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f
+vld2.32 {d0[],d1[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b
+vld2.8 {d9[],d11[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e
+vld2.16 {d17[],d18[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f
+vld2.32 {d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b
+vld2.8 {d0[],d2[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e
+vld2.16 {d0[],d2[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f
+vld2.32 {d5[],d7[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b
+---- VLD3 (multiple 3-elements) ----
+vld3.8 {d20-d22} :: Result 0x1f1b121f 0x2b2f151d 0x1c131b1e 0x2c232f19 0x141c1a1f 0x242b2e1d 0x1f1b121f 0x2b2f151d
+vld3.16 {d0-d2} :: Result 0x131b1e1f 0x232f191d 0x1f1c121f 0x2b2b151d 0x141c1a1b 0x242c2e2f 0x131b1e1f 0x232f191d
+vld3.32 {d0-d2} :: Result 0x121f1e1f 0x151d191d 0x131b1a1b 0x232f2e2f 0x141c1f1c 0x242c2b2b 0x121f1e1f 0x151d191d
+vld3.8 {d0,d2,d4} :: Result 0x1f1b121f 0x2b2f151d 0x1c131b1e 0x2c232f19 0x141c1a1f 0x242b2e1d 0x1f1b121f 0x2b2f151d
+vld3.16 {d20,d22,d24} :: Result 0x131b1e1f 0x232f191d 0x1f1c121f 0x2b2b151d 0x141c1a1b 0x242c2e2f 0x131b1e1f 0x232f191d
+vld3.32 {d0,d2,d4} :: Result 0x121f1e1f 0x151d191d 0x131b1a1b 0x232f2e2f 0x141c1f1c 0x242c2b2b 0x121f1e1f 0x151d191d
+---- VLD3 (single 3-element structure to one lane) ----
+vld3.32 {d0[0],d1[0],d2[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b 0x55555555
+vld3.32 {d0[1],d1[1],d2[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b
+vld3.32 {d0[0],d2[0],d4[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b 0x55555555
+vld3.32 {d0[1],d2[1],d4[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x131b1a1b
+vld3.16 {d1[0],d2[0],d3[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555121f 0x55555555
+vld3.16 {d1[1],d2[1],d3[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x121f5555 0x55555555
+vld3.16 {d1[2],d2[2],d3[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555121f
+vld3.16 {d1[3],d2[3],d3[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x121f5555
+vld3.16 {d1[0],d3[0],d5[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555
+vld3.16 {d1[1],d3[1],d5[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555
+vld3.16 {d1[2],d3[2],d5[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x5555121f 0x55555555 0x55551a1b
+vld3.16 {d1[3],d3[3],d5[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555
+vld3.8 {d0[7],d1[7],d2[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555
+vld3.8 {d1[6],d2[6],d3[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555
+vld3.8 {d0[5],d1[5],d2[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55
+vld3.8 {d0[4],d1[4],d2[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551e
+vld3.8 {d20[3],d21[3],d22[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555
+vld3.8 {d0[2],d1[2],d2[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555
+vld3.8 {d17[1],d18[1],d19[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555
+vld3.8 {d29[0],d30[0],d31[0]} :: Result 0x5555551e 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555 0x5555551f 0x55555555
+---- VLD3 (3-elements to all lanes) ----
+vld3.8 {d0[],d1[],d2[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e
+vld3.16 {d0[],d1[],d2[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f
+vld3.32 {d0[],d1[],d2[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x131b1a1b 0x131b1a1b
+vld3.8 {d9[],d11[],d13[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e
+vld3.16 {d17[],d18[],d19[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f
+vld3.32 {d29[],d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c
+vld3.8 {d0[],d2[],d4[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e
+vld3.16 {d0[],d2[],d4[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x121f121f 0x121f121f
+vld3.32 {d5[],d7[],d9[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x131b1a1b 0x131b1a1b
+---- VLD4 (multiple 3-elements) ----
+vld4.8 {d0-d3} :: Result 0x1d1c1b1f 0x2a2b2b2f 0x191f1a1e 0x2d2e2b2e 0x1d1c1b1f 0x2d2a2c2f 0x15141312 0x26252423
+vld4.16 {d20-d23} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c
+vld4.32 {d0-d3} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a
+vld4.8 {d0,d2,d4,d6} :: Result 0x1d1c1b1f 0x2a2b2b2f 0x191f1a1e 0x2d2e2b2e 0x1d1c1b1f 0x2d2a2c2f 0x15141312 0x26252423
+vld4.16 {d1,d3,d5,d7} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c
+vld4.32 {d20,d22,d24,d26} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a
+---- VLD4 (single 4-element structure to one lane) ----
+vld4.32 {d0[0],d1[0],d2[0],d3[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d 0x55555555
+vld4.32 {d0[1],d1[1],d2[1],d3[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x55555555
+vld4.32 {d0[0],d2[0],d4[0],d6[0]} :: Result 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d 0x55555555
+vld4.32 {d0[1],d2[1],d4[1],d6[1]} :: Result 0x55555555 0x121f1e1f 0x55555555 0x131b1a1b 0x55555555 0x141c1f1c 0x55555555 0x151d191d
+vld4.16 {d1[0],d2[0],d3[0],d4[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b 0x55555555
+vld4.16 {d1[1],d2[1],d3[1],d4[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 0x55555555
+vld4.16 {d1[2],d2[2],d3[2],d4[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b
+vld4.16 {d1[3],d2[3],d3[3],d4[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555
+vld4.16 {d1[0],d3[0],d5[0],d7[0]} :: Result 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b 0x55555555
+vld4.16 {d1[1],d3[1],d5[1],d7[1]} :: Result 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555 0x55555555
+vld4.16 {d1[2],d3[2],d5[2],d7[2]} :: Result 0x55555555 0x55551e1f 0x55555555 0x5555121f 0x55555555 0x55551a1b 0x55555555 0x5555131b
+vld4.16 {d1[3],d3[3],d5[3],d7[3]} :: Result 0x55555555 0x1e1f5555 0x55555555 0x121f5555 0x55555555 0x1a1b5555 0x55555555 0x131b5555
+vld4.8 {d0[7],d1[7],d2[7],d3[7]} :: Result 0x55555555 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x12555555
+vld4.8 {d1[6],d2[6],d3[6],d4[6]} :: Result 0x55555555 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x55125555
+vld4.8 {d0[5],d1[5],d2[5],d3[5]} :: Result 0x55555555 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551255
+vld4.8 {d0[4],d1[4],d2[4],d3[4]} :: Result 0x55555555 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x55555512
+vld4.8 {d20[3],d21[3],d22[3],d23[3]} :: Result 0x1f555555 0x55555555 0x1e555555 0x55555555 0x1f555555 0x55555555 0x12555555 0x55555555
+vld4.8 {d0[2],d1[2],d2[2],d3[2]} :: Result 0x551f5555 0x55555555 0x551e5555 0x55555555 0x551f5555 0x55555555 0x55125555 0x55555555
+vld4.8 {d17[1],d18[1],d19[1],d20[1]} :: Result 0x55551f55 0x55555555 0x55551e55 0x55555555 0x55551f55 0x55555555 0x55551255 0x55555555
+vld4.8 {d28[0],d29[0],d30[0],d31[0]} :: Result 0x5555551f 0x55555555 0x5555551e 0x55555555 0x5555551f 0x55555555 0x55555512 0x55555555
+---- VLD4 (4-elements to all lanes) ----
+vld4.8 {d0[],d1[],d2[],d3[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212
+vld4.16 {d0[],d1[],d2[],d3[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b
+vld4.32 {d0[],d1[],d2[],d3[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d
+vld4.8 {d9[],d11[],d13[],d15[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212
+vld4.16 {d17[],d18[],d19[],d20[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b
+vld4.32 {d28[],d29[],d30[],d31[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d
+vld4.8 {d0[],d2[],d4[],d6[]} :: Result 0x1f1f1f1f 0x1f1f1f1f 0x1e1e1e1e 0x1e1e1e1e 0x1f1f1f1f 0x1f1f1f1f 0x12121212 0x12121212
+vld4.16 {d0[],d2[],d4[],d6[]} :: Result 0x1e1f1e1f 0x1e1f1e1f 0x121f121f 0x121f121f 0x1a1b1a1b 0x1a1b1a1b 0x131b131b 0x131b131b
+vld4.32 {d5[],d7[],d9[],d11[]} :: Result 0x121f1e1f 0x121f1e1f 0x131b1a1b 0x131b1a1b 0x141c1f1c 0x141c1f1c 0x151d191d 0x151d191d
+---- VST1 (multiple single elements) ----
+vst1.8 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.16 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.32 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.64 {d0} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d9} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.16 {d17} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.32 {d31} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.64 {d14} :: Result 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d0-d1} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.16 {d0-d1} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.32 {d5-d6} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.64 {d30-d31} :: Result 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555
+vst1.16 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555
+vst1.32 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555
+vst1.64 {d0-d2} :: Result 0x252a2e2b 0x262d2d2a 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x55555555 0x55555555
+vst1.8 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a
+vst1.16 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a
+vst1.32 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a
+vst1.64 {d0-d3} :: Result 0x121f1e1f 0x131b1a1b 0x141c1f1c 0x151d191d 0x232f2e2f 0x242c2b2b 0x252a2e2b 0x262d2d2a
+---- VST1 (single element from one lane) ----
+vst1.32 {d0[0]} :: Result 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.32 {d0[1]} :: Result 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.16 {d1[0]} :: Result 0x55552e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.16 {d1[1]} :: Result 0x5555252a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.16 {d1[2]} :: Result 0x55552d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.16 {d1[3]} :: Result 0x5555262d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d0[7]} :: Result 0x55555526 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d1[6]} :: Result 0x5555552d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d0[5]} :: Result 0x5555552d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d0[4]} :: Result 0x5555552a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d20[3]} :: Result 0x55555525 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d0[2]} :: Result 0x5555552a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d17[1]} :: Result 0x5555552e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst1.8 {d30[0]} :: Result 0x5555552b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+---- VST2 (multiple 2-elements) ----
+vst2.8 {d30-d31} :: Result 0x2e2e2b2f 0x25232a2f 0x2d2b2a2b 0x26242d2c 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d0-d1} :: Result 0x2e2b2e2f 0x252a232f 0x2d2a2b2b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.32 {d0-d1} :: Result 0x232f2e2f 0x252a2e2b 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d10,d12} :: Result 0x2e2e2b2f 0x25232a2f 0x2d2b2a2b 0x26242d2c 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d20,d22} :: Result 0x2e2b2e2f 0x252a232f 0x2d2a2b2b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.32 {d0,d2} :: Result 0x232f2e2f 0x252a2e2b 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d0-d3} :: Result 0x2e1e2f1f 0x23122f1f 0x2b1a2b1b 0x24132c1b 0x2e1f2b1c 0x25142a1c 0x2d192a1d 0x26152d1d
+vst2.16 {d20-d23} :: Result 0x2e2f1e1f 0x232f121f 0x2b2b1a1b 0x242c131b 0x2e2b1f1c 0x252a141c 0x2d2a191d 0x262d151d
+vst2.32 {d0-d3} :: Result 0x121f1e1f 0x232f2e2f 0x131b1a1b 0x242c2b2b 0x141c1f1c 0x252a2e2b 0x151d191d 0x262d2d2a
+---- VST2 (single 2-element structure from one lane) ----
+vst2.32 {d0[0],d1[0]} :: Result 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.32 {d0[1],d1[1]} :: Result 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.32 {d0[0],d2[0]} :: Result 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.32 {d0[1],d2[1]} :: Result 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d1[0],d2[0]} :: Result 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d1[1],d2[1]} :: Result 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d1[2],d2[2]} :: Result 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d1[3],d2[3]} :: Result 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d1[0],d3[0]} :: Result 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d1[1],d3[1]} :: Result 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d1[2],d3[2]} :: Result 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.16 {d1[3],d3[3]} :: Result 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d0[7],d1[7]} :: Result 0x55552624 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d1[6],d2[6]} :: Result 0x55552d2c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d0[5],d1[5]} :: Result 0x55552d2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d0[4],d1[4]} :: Result 0x55552a2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d20[3],d21[3]} :: Result 0x55552523 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d0[2],d1[2]} :: Result 0x55552a2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d17[1],d18[1]} :: Result 0x55552e2e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst2.8 {d30[0],d31[0]} :: Result 0x55552b2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+---- VST3 (multiple 3-elements) ----
+vst3.8 {d20-d22} :: Result 0x2e2f1c2b 0x1c2a2e1f 0x2314252f 0x2d2b1d2a 0x1d2d2b19 0x2415262c 0x55555555 0x55555555
+vst3.16 {d0-d2} :: Result 0x1f1c2e2b 0x252a2e2f 0x232f141c 0x191d2d2a 0x262d2b2b 0x242c151d 0x55555555 0x55555555
+vst3.32 {d0-d2} :: Result 0x252a2e2b 0x141c1f1c 0x232f2e2f 0x262d2d2a 0x151d191d 0x242c2b2b 0x55555555 0x55555555
+vst3.8 {d0,d2,d4} :: Result 0x2e2f1c2b 0x1c2a2e1f 0x2314252f 0x2d2b1d2a 0x1d2d2b19 0x2415262c 0x55555555 0x55555555
+vst3.16 {d20,d22,d24} :: Result 0x1f1c2e2b 0x252a2e2f 0x232f141c 0x191d2d2a 0x262d2b2b 0x242c151d 0x55555555 0x55555555
+vst3.32 {d0,d2,d4} :: Result 0x252a2e2b 0x141c1f1c 0x232f2e2f 0x262d2d2a 0x151d191d 0x242c2b2b 0x55555555 0x55555555
+---- VST3 (single 3-element structure from one lane) ----
+vst3.32 {d0[0],d1[0],d2[0]} :: Result 0x121f1e1f 0x252a2e2b 0x232f2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.32 {d0[1],d1[1],d2[1]} :: Result 0x131b1a1b 0x262d2d2a 0x242c2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.32 {d0[0],d2[0],d4[0]} :: Result 0x121f1e1f 0x252a2e2b 0x232f2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.32 {d0[1],d2[1],d4[1]} :: Result 0x131b1a1b 0x262d2d2a 0x242c2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.16 {d1[0],d2[0],d3[0]} :: Result 0x2e2b1e1f 0x55552e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.16 {d1[1],d2[1],d3[1]} :: Result 0x252a121f 0x5555232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.16 {d1[2],d2[2],d3[2]} :: Result 0x2d2a1a1b 0x55552b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.16 {d1[3],d2[3],d3[3]} :: Result 0x262d131b 0x5555242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.16 {d1[0],d3[0],d5[0]} :: Result 0x2e2f1e1f 0x55552e2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.16 {d1[1],d3[1],d5[1]} :: Result 0x232f121f 0x5555252a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.16 {d1[2],d3[2],d5[2]} :: Result 0x2b2b1a1b 0x55552d2a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.16 {d1[3],d3[3],d5[3]} :: Result 0x242c131b 0x5555262d 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.8 {d0[7],d1[7],d2[7]} :: Result 0x55242613 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.8 {d1[6],d2[6],d3[6]} :: Result 0x552c2d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.8 {d0[5],d1[5],d2[5]} :: Result 0x552b2d1a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.8 {d0[4],d1[4],d2[4]} :: Result 0x552b2a1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.8 {d20[3],d21[3],d22[3]} :: Result 0x55232512 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.8 {d0[2],d1[2],d2[2]} :: Result 0x552f2a1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.8 {d17[1],d18[1],d19[1]} :: Result 0x552e2e1e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst3.8 {d29[0],d30[0],d31[0]} :: Result 0x552b1f2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+---- VST4 (multiple 4-elements) ----
+vst4.8 {d0-d3} :: Result 0x2b2f1c1f 0x2e2e1f1e 0x2a2f1c1f 0x25231412 0x2a2b1d1b 0x2d2b191a 0x2d2c1d1b 0x26241513
+vst4.16 {d20-d23} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c
+vst4.32 {d0-d3} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a
+vst4.8 {d0,d2,d4,d6} :: Result 0x2b2f1c1f 0x2e2e1f1e 0x2a2f1c1f 0x25231412 0x2a2b1d1b 0x2d2b191a 0x2d2c1d1b 0x26241513
+vst4.16 {d1,d3,d5,d7} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x141c121f 0x252a232f 0x191d1a1b 0x2d2a2b2b 0x151d131b 0x262d242c
+vst4.32 {d20,d22,d24,d26} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a
+---- VST4 (single 4-element structure from one lane) ----
+vst4.32 {d0[0],d1[0],d2[0],d3[0]} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.32 {d0[1],d1[1],d2[1],d3[1]} :: Result 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.32 {d0[0],d2[0],d4[0],d6[0]} :: Result 0x121f1e1f 0x141c1f1c 0x232f2e2f 0x252a2e2b 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.32 {d0[1],d2[1],d4[1],d6[1]} :: Result 0x131b1a1b 0x151d191d 0x242c2b2b 0x262d2d2a 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.16 {d1[0],d2[0],d3[0],d4[0]} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.16 {d1[1],d2[1],d3[1],d4[1]} :: Result 0x141c121f 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.16 {d1[2],d2[2],d3[2],d4[2]} :: Result 0x191d1a1b 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.16 {d1[3],d2[3],d3[3],d4[3]} :: Result 0x151d131b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.16 {d1[0],d3[0],d5[0],d7[0]} :: Result 0x1f1c1e1f 0x2e2b2e2f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.16 {d1[1],d3[1],d5[1],d7[1]} :: Result 0x141c121f 0x252a232f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.16 {d1[2],d3[2],d5[2],d7[2]} :: Result 0x191d1a1b 0x2d2a2b2b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.16 {d1[3],d3[3],d5[3],d7[3]} :: Result 0x151d131b 0x262d242c 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.8 {d0[7],d1[7],d2[7],d3[7]} :: Result 0x26241513 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.8 {d1[6],d2[6],d3[6],d4[6]} :: Result 0x2d2c1d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.8 {d0[5],d1[5],d2[5],d3[5]} :: Result 0x2d2b191a 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.8 {d0[4],d1[4],d2[4],d3[4]} :: Result 0x2a2b1d1b 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.8 {d20[3],d21[3],d22[3],d23[3]} :: Result 0x25231412 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.8 {d0[2],d1[2],d2[2],d3[2]} :: Result 0x2a2f1c1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.8 {d17[1],d18[1],d19[1],d20[1]} :: Result 0x2e2e1f1e 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+vst4.8 {d28[0],d29[0],d30[0],d31[0]} :: Result 0x2b2f1c1f 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555 0x55555555
+---- VMOVN ----
+vmovn.i32 d0, q0 :: Qd 0x00240024 0x00320032  Qm (i32)0x00000032  Qn (i32)0x00000024
+vmovn.i16 d7, q5 :: Qd 0x00240024 0x00320032  Qm (i32)0x00000032  Qn (i32)0x00000024
+vmovn.i64 d31, q0 :: Qd 0x00000024 0x00000032  Qm (i32)0x00000032  Qn (i32)0x00000024
+vmovn.i32 d0, q0 :: Qd 0xf0f0f0f0 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000f0
+vmovn.i16 d7, q5 :: Qd 0xefefefef 0xadadadad  Qm (i16)0x0000dead  Qn (i16)0x0000beef
+vmovn.i64 d31, q0 :: Qd 0x24242424 0xff00fe0f  Qm (i32)0xff00fe0f  Qn (i8)0x00000024
+---- VQMOVN ----
+vqmovn.u32 d0, q0 :: Qd 0x00240024 0x00320032  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 00000000
+vqmovn.u16 d7, q5 :: Qd 0x00240024 0x00320032  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 00000000
+vqmovn.u64 d31, q0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 08000000
+vqmovn.u32 d0, q0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000f0  fpscr: 08000000
+vqmovn.u16 d7, q5 :: Qd 0xffffffff 0xffffffff  Qm (i16)0x0000dead  Qn (i16)0x0000beef  fpscr: 08000000
+vqmovn.u64 d31, q0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff00fe0f  Qn (i8)0x00000024  fpscr: 08000000
+vqmovn.s32 d0, q0 :: Qd 0x00240024 0x00320032  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 00000000
+vqmovn.s16 d7, q5 :: Qd 0x00240024 0x00320032  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 00000000
+vqmovn.s64 d31, q0 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 08000000
+vqmovn.s32 d0, q0 :: Qd 0x80008000 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000f0  fpscr: 08000000
+vqmovn.s16 d7, q5 :: Qd 0x80808080 0x80808080  Qm (i16)0x0000dead  Qn (i16)0x0000beef  fpscr: 08000000
+vqmovn.s64 d31, q0 :: Qd 0x7fffffff 0x80000000  Qm (i32)0xff00fe0f  Qn (i8)0x00000024  fpscr: 08000000
+vqmovn.s32 d0, q0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff  fpscr: 00000000
+vqmovn.s16 d7, q5 :: Qd 0x7f7f7f7f 0xffffffff  Qm (i8)0x000000ff  Qn (i16)0x000000ff  fpscr: 08000000
+vqmovn.s64 d31, q0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ff  Qn (i8)0x000000ff  fpscr: 00000000
+---- VQMOVN ----
+vqmovun.s32 d0, q0 :: Qd 0x00240024 0x00320032  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 00000000
+vqmovun.s16 d7, q5 :: Qd 0x00240024 0x00320032  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 00000000
+vqmovun.s64 d31, q0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000032  Qn (i32)0x00000024  fpscr: 08000000
+vqmovun.s32 d0, q0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ff  Qn (i8)0x000000f0  fpscr: 08000000
+vqmovun.s16 d7, q5 :: Qd 0x00000000 0x00000000  Qm (i16)0x0000dead  Qn (i16)0x0000beef  fpscr: 08000000
+vqmovun.s64 d31, q0 :: Qd 0xffffffff 0x00000000  Qm (i32)0xff00fe0f  Qn (i8)0x00000024  fpscr: 08000000
+vqmovun.s32 d0, q0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ff  Qn (i8)0x000000ff  fpscr: 08000000
+vqmovun.s16 d7, q5 :: Qd 0xffffffff 0x00000000  Qm (i8)0x000000ff  Qn (i16)0x000000ff  fpscr: 08000000
+vqmovun.s64 d31, q0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ff  Qn (i8)0x000000ff  fpscr: 08000000
+---- VABS ----
+vabs.s32 d0, d1 :: Qd 0x00000073 0x00000073  Qm (i32)0x00000073
+vabs.s16 d15, d4 :: Qd 0x00000073 0x00000073  Qm (i32)0x00000073
+vabs.s8 d8, d7 :: Qd 0x00000073 0x00000073  Qm (i32)0x00000073
+vabs.s32 d0, d1 :: Qd 0x000000fe 0x000000fe  Qm (i32)0x000000fe
+vabs.s16 d31, d4 :: Qd 0x000000ef 0x000000ef  Qm (i32)0x000000ef
+vabs.s8 d8, d7 :: Qd 0x00000022 0x00000022  Qm (i32)0x000000de
+vabs.s32 d0, d1 :: Qd 0x01f501f6 0x01f501f6  Qm (i16)0x0000fe0a
+vabs.s16 d15, d4 :: Qd 0x10f510f5 0x10f510f5  Qm (i16)0x0000ef0b
+vabs.s8 d8, d7 :: Qd 0x220c220c 0x220c220c  Qm (i16)0x0000de0c
+---- VQABS ----
+vqabs.s32 d0, d1 :: Qd 0x00000073 0x00000073  Qm (i32)0x00000073  fpscr 00000000
+vqabs.s32 d0, d1 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  fpscr 08000000
+vqabs.s16 d0, d1 :: Qd 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  fpscr 08000000
+vqabs.s8 d0, d1 :: Qd 0x7f000000 0x7f000000  Qm (i32)0x80000000  fpscr 08000000
+vqabs.s16 d15, d4 :: Qd 0x00000073 0x00000073  Qm (i32)0x00000073  fpscr 00000000
+vqabs.s8 d8, d7 :: Qd 0x00000073 0x00000073  Qm (i32)0x00000073  fpscr 00000000
+vqabs.s32 d0, d1 :: Qd 0x000000fe 0x000000fe  Qm (i32)0x000000fe  fpscr 00000000
+vqabs.s16 d31, d4 :: Qd 0x000000ef 0x000000ef  Qm (i32)0x000000ef  fpscr 00000000
+vqabs.s8 d8, d7 :: Qd 0x00000022 0x00000022  Qm (i32)0x000000de  fpscr 00000000
+vqabs.s32 d0, d1 :: Qd 0x01f501f6 0x01f501f6  Qm (i16)0x0000fe0a  fpscr 00000000
+vqabs.s16 d15, d4 :: Qd 0x10f510f5 0x10f510f5  Qm (i16)0x0000ef0b  fpscr 00000000
+vqabs.s8 d8, d7 :: Qd 0x220c220c 0x220c220c  Qm (i16)0x0000de0c  fpscr 00000000
+---- VADDHN ----
+vaddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vaddhn.i16 d0, q1, q2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vaddhn.i32 d0, q1, q2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vaddhn.i64 d0, q1, q2 :: Qd 0x000000e5 0x000000e5  Qm (i32)0x00000073  Qn (i32)0x00000072
+vaddhn.i16 d0, q15, q2 :: Qd 0xeff0eff0 0xeff0eff0  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vaddhn.i32 d31, q1, q2 :: Qd 0xef73ef73 0xef73ef73  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vaddhn.i64 d0, q1, q8 :: Qd 0xef73f0e5 0xef73f0e5  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vaddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000073  Qn (i32)0x00000072
+vaddhn.i16 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000072
+vaddhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000072
+vaddhn.i64 d0, q1, q2 :: Qd 0x737373e5 0x737373e5  Qm (i8)0x00000073  Qn (i32)0x00000072
+---- VRADDHN ----
+vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vraddhn.i16 d0, q1, q2 :: Qd 0x00010001 0x00010001  Qm (i32)0x00000073  Qn (i32)0x00000072
+vraddhn.i32 d0, q1, q2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vraddhn.i64 d0, q1, q2 :: Qd 0x000000e5 0x000000e5  Qm (i32)0x00000073  Qn (i32)0x00000072
+vraddhn.i16 d0, q15, q2 :: Qd 0xeff1eff1 0xeff1eff1  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vraddhn.i32 d31, q1, q2 :: Qd 0xef74ef74 0xef74ef74  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vraddhn.i64 d0, q1, q8 :: Qd 0xef73f0e6 0xef73f0e6  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000073  Qn (i32)0x00000072
+vraddhn.i16 d0, q1, q2 :: Qd 0x73747374 0x73747374  Qm (i8)0x00000073  Qn (i32)0x00000072
+vraddhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000072
+vraddhn.i64 d0, q1, q2 :: Qd 0x737373e5 0x737373e5  Qm (i8)0x00000073  Qn (i32)0x00000072
+vraddhn.i16 d0, q15, q2 :: Qd 0xeff0eff0 0xeff0eff0  Qm (i16)0x0000ef73  Qn (i32)0x00000102
+vraddhn.i32 d31, q1, q2 :: Qd 0xef74ef74 0xef74ef74  Qm (i16)0x0000ef73  Qn (i32)0x00000102
+vraddhn.i64 d0, q1, q8 :: Qd 0xef73f076 0xef73f076  Qm (i16)0x0000ef73  Qn (i32)0x00000102
+vraddhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000073  Qn (i32)0x00000002
+vraddhn.i16 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000002
+vraddhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000002
+vraddhn.i64 d0, q1, q2 :: Qd 0x73737375 0x73737375  Qm (i8)0x00000073  Qn (i32)0x00000002
+---- VSUBHN ----
+vsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vsubhn.i16 d0, q1, q2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vsubhn.i32 d0, q1, q2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vsubhn.i64 d0, q1, q2 :: Qd 0x00000001 0x00000001  Qm (i32)0x00000073  Qn (i32)0x00000072
+vsubhn.i16 d0, q15, q2 :: Qd 0xefeeefee 0xefeeefee  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vsubhn.i32 d31, q1, q2 :: Qd 0xef73ef73 0xef73ef73  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vsubhn.i64 d0, q1, q8 :: Qd 0xef73ee01 0xef73ee01  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000073  Qn (i32)0x00000072
+vsubhn.i16 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000072
+vsubhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000072
+vsubhn.i64 d0, q1, q2 :: Qd 0x73737301 0x73737301  Qm (i8)0x00000073  Qn (i32)0x00000072
+---- VRSUBHN ----
+vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vrsubhn.i16 d0, q1, q2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vrsubhn.i32 d0, q1, q2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000073  Qn (i32)0x00000072
+vrsubhn.i64 d0, q1, q2 :: Qd 0x00000001 0x00000001  Qm (i32)0x00000073  Qn (i32)0x00000072
+vrsubhn.i16 d0, q15, q2 :: Qd 0xefeeefee 0xefeeefee  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vrsubhn.i32 d31, q1, q2 :: Qd 0xef74ef74 0xef74ef74  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vrsubhn.i64 d0, q1, q8 :: Qd 0xef73ee02 0xef73ee02  Qm (i16)0x0000ef73  Qn (i32)0x00000172
+vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000073  Qn (i32)0x00000072
+vrsubhn.i16 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000072
+vrsubhn.i32 d0, q1, q2 :: Qd 0x73737373 0x73737373  Qm (i8)0x00000073  Qn (i32)0x00000072
+vrsubhn.i64 d0, q1, q2 :: Qd 0x73737301 0x73737301  Qm (i8)0x00000073  Qn (i32)0x00000072
+vrsubhn.i16 d0, q15, q2 :: Qd 0xf0eff0ef 0xf0eff0ef  Qm (i16)0x0000ef93  Qn (i32)0x00000102
+vrsubhn.i32 d31, q1, q2 :: Qd 0xef94ef94 0xef94ef94  Qm (i16)0x0000ef93  Qn (i32)0x00000102
+vrsubhn.i64 d0, q1, q8 :: Qd 0xef93ee92 0xef93ee92  Qm (i16)0x0000ef93  Qn (i32)0x00000102
+vrsubhn.i32 d0, q1, q1 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000093  Qn (i32)0x00000002
+vrsubhn.i16 d0, q1, q2 :: Qd 0x94949494 0x94949494  Qm (i8)0x00000093  Qn (i32)0x00000002
+vrsubhn.i32 d0, q1, q2 :: Qd 0x93949394 0x93949394  Qm (i8)0x00000093  Qn (i32)0x00000002
+vrsubhn.i64 d0, q1, q2 :: Qd 0x93939392 0x93939392  Qm (i8)0x00000093  Qn (i32)0x00000002
+---- VCEQ #0 ----
+vceq.i32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000021
+vceq.i16 d2, d1, #0 :: Qd 0xffff0000 0xffff0000  Qm (i32)0x00000021
+vceq.i8 d10, d11, #0 :: Qd 0xffffff00 0xffffff00  Qm (i32)0x00000021
+vceq.i32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vceq.i16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vceq.i8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+---- VCGT #0 ----
+vcgt.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000021
+vcgt.s16 d2, d1, #0 :: Qd 0x0000ffff 0x0000ffff  Qm (i32)0x00000021
+vcgt.s8 d10, d31, #0 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x00000021
+vcgt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ef
+vcgt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ed
+vcgt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ae
+---- VCGE #0 ----
+vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000021
+vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000021
+vcge.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000021
+vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcge.s8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcge.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ef
+vcge.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ed
+vcge.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ae
+vcge.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x000000ef
+vcge.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x000000ed
+vcge.s8 d10, d11, #0 :: Qd 0xffffff00 0xffffff00  Qm (i32)0x000000ae
+---- VCLE #0 ----
+vcle.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000021
+vcle.s16 d2, d1, #0 :: Qd 0xffff0000 0xffff0000  Qm (i32)0x00000021
+vcle.s8 d10, d11, #0 :: Qd 0xffffff00 0xffffff00  Qm (i32)0x00000021
+vcle.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.s8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ef
+vcle.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ed
+vcle.s8 d10, d11, #0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ae
+---- VCLT #0 ----
+vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000021
+vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000021
+vclt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000021
+vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.s8 d10, d11, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.s32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ef
+vclt.s16 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ed
+vclt.s8 d10, d31, #0 :: Qd 0xffffffff 0xffffffff  Qm (i8)0x000000ae
+vclt.s32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x000000ef
+vclt.s16 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x000000ed
+vclt.s8 d10, d11, #0 :: Qd 0x000000ff 0x000000ff  Qm (i32)0x000000ae
+---- VCNT ----
+vcnt.8 d0, d1 :: Qd 0x04050306 0x04050306  Qm (i32)0xac3d25eb
+vcnt.8 d11, d14 :: Qd 0x04050306 0x04050306  Qm (i32)0xac3d25eb
+vcnt.8 d6, d2 :: Qd 0x00020306 0x00020306  Qm (i32)0x000ad0eb
+---- VCLS ----
+vcls.s8 d0, d1 :: Qd 0x07070701 0x07070701  Qm (i32)0x00000021
+vcls.s8 d30, d31 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000082
+vcls.s16 d0, d1 :: Qd 0x000f0009 0x000f0009  Qm (i32)0x00000021
+vcls.s16 d31, d30 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000082
+vcls.s32 d6, d1 :: Qd 0x00000019 0x00000019  Qm (i32)0x00000021
+vcls.s32 d30, d5 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000082
+vcls.s8 d2, d4 :: Qd 0x07070707 0x07070707  Qm (i8)0x000000ff
+vcls.s16 d2, d4 :: Qd 0x000f000f 0x000f000f  Qm (i8)0x000000ff
+vcls.s32 d2, d4 :: Qd 0x0000001f 0x0000001f  Qm (i8)0x000000ff
+vcls.s8 d2, d4 :: Qd 0x07020702 0x07020702  Qm (i16)0x0000ffef
+vcls.s16 d2, d4 :: Qd 0x000a000a 0x000a000a  Qm (i16)0x0000ffef
+vcls.s32 d2, d4 :: Qd 0x0000000a 0x0000000a  Qm (i16)0x0000ffef
+vcls.s8 d2, d4 :: Qd 0x07070707 0x07070707  Qm (i8)0x00000000
+vcls.s16 d2, d4 :: Qd 0x000f000f 0x000f000f  Qm (i8)0x00000000
+vcls.s32 d2, d4 :: Qd 0x0000001f 0x0000001f  Qm (i8)0x00000000
+vcls.s8 d2, d4 :: Qd 0x07020702 0x07020702  Qm (i16)0x000000ef
+vcls.s16 d2, d4 :: Qd 0x00070007 0x00070007  Qm (i16)0x000000ef
+vcls.s32 d2, d4 :: Qd 0x00000007 0x00000007  Qm (i16)0x000000ef
+---- VCLZ ----
+vclz.i8 d0, d1 :: Qd 0x08080802 0x08080802  Qm (i32)0x00000021
+vclz.i8 d30, d31 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000082
+vclz.i16 d0, d1 :: Qd 0x0010000a 0x0010000a  Qm (i32)0x00000021
+vclz.i16 d31, d30 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000082
+vclz.i32 d6, d1 :: Qd 0x0000001a 0x0000001a  Qm (i32)0x00000021
+vclz.i32 d30, d5 :: Qd 0x00000000 0x00000000  Qm (i8)0x00000082
+vclz.i8 d2, d4 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ff
+vclz.i16 d2, d4 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ff
+vclz.i32 d2, d4 :: Qd 0x00000000 0x00000000  Qm (i8)0x000000ff
+vclz.i8 d2, d4 :: Qd 0x00000000 0x00000000  Qm (i16)0x0000ffef
+vclz.i16 d2, d4 :: Qd 0x00000000 0x00000000  Qm (i16)0x0000ffef
+vclz.i32 d2, d4 :: Qd 0x00000000 0x00000000  Qm (i16)0x0000ffef
+vclz.i8 d2, d4 :: Qd 0x08080808 0x08080808  Qm (i8)0x00000000
+vclz.i16 d2, d4 :: Qd 0x00100010 0x00100010  Qm (i8)0x00000000
+vclz.i32 d2, d4 :: Qd 0x00000020 0x00000020  Qm (i8)0x00000000
+vclz.i8 d2, d4 :: Qd 0x08000800 0x08000800  Qm (i16)0x000000ef
+vclz.i16 d2, d4 :: Qd 0x00080008 0x00080008  Qm (i16)0x000000ef
+vclz.i32 d2, d4 :: Qd 0x00000008 0x00000008  Qm (i16)0x000000ef
+---- VSLI ----
+vsli.16 d0, d1, #1 :: Qd 0x0001000f 0x0001000f  Qm (i32)0x00000007
+vsli.16 d3, d4, #2 :: Qd 0xfffdfe11 0xfffdfe11  Qm (i32)0xffffff84
+vsli.32 d2, d5, #31 :: Qd 0xd5555555 0xd5555555  Qm (i32)0xffffffff
+vsli.8 d6, d7, #7 :: Qd 0x5555d5d5 0x5555d5d5  Qm (i32)0x0000ffff
+vsli.16 d8, d9, #12 :: Qd 0xf5556555 0xf5556555  Qm (i32)0xfffffff6
+vsli.32 d10, d11, #5 :: Qd 0x0004ff55 0x0004ff55  Qm (i32)0x000027fa
+vsli.8 d12, d13, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vsli.16 d14, d15, #11 :: Qd 0xfd55fd55 0xfd55fd55  Qm (i32)0xffffffff
+vsli.32 d10, d11, #9 :: Qd 0x0007d155 0x0007d155  Qm (i32)0x000003e8
+vsli.8 d7, d13, #7 :: Qd 0xd5d5d5d5 0xd5d5d5d5  Qm (i32)0xffffffff
+vsli.16 d8, d1, #1 :: Qd 0x0001579f 0x0001579f  Qm (i32)0x0000abcf
+vsli.32 d12, d3, #15 :: Qd 0xff285555 0xff285555  Qm (i32)0xfffffe50
+vsli.64 d0, d1, #42 :: Qd 0xfffffd55 0x55555555  Qm (i32)0xffffffff
+vsli.64 d6, d7, #12 :: Qd 0x00fac000 0x00fac555  Qm (i32)0x00000fac
+vsli.64 d8, d4, #9 :: Qd 0x0069f000 0x0069f155  Qm (i32)0x000034f8
+vsli.64 d9, d12, #11 :: Qd 0x0c0cb000 0x0c0cb555  Qm (i32)0x00018196
+---- VPADD ----
+vpadd.i32 d0, d1, d2 :: Qd 0x000000f0 0x00000030  Qm (i32)0x00000018  Qn (i32)0x00000078
+vpadd.i32 d0, d1, d2 :: Qd 0x000000f0 0x00000118  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vpadd.i16 d0, d1, d2 :: Qd 0x00780078 0x008c008c  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vpadd.i8 d0, d1, d2 :: Qd 0x00780078 0x008c008c  Qm (i32)0x0000008c  Qn (i32)0x00000078
+vpadd.i8 d0, d1, d2 :: Qd 0x80028002 0x80018001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpadd.i16 d0, d1, d2 :: Qd 0x80028002 0x80018001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpadd.i32 d0, d1, d2 :: Qd 0x00000004 0x00000002  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpadd.i32 d10, d11, d12 :: Qd 0x000000f0 0x00000030  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VPADDL ----
+vpaddl.u32 d0, d1 :: Qd 0x00000000 0x00000030  Qm (i32)0x00000018
+vpaddl.u32 d0, d1 :: Qd 0x00000000 0x00000118  Qm (i32)0x0000008c
+vpaddl.u16 d0, d1 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c
+vpaddl.u8 d0, d1 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c
+vpaddl.u8 d0, d1 :: Qd 0x00800001 0x00800001  Qm (i32)0x80000001
+vpaddl.u16 d0, d1 :: Qd 0x00008001 0x00008001  Qm (i32)0x80000001
+vpaddl.u32 d0, d1 :: Qd 0x00000001 0x00000002  Qm (i32)0x80000001
+vpaddl.u32 d10, d11 :: Qd 0x00000000 0x00000030  Qm (i32)0x00000018
+vpaddl.s32 d0, d1 :: Qd 0x00000000 0x00000030  Qm (i32)0x00000018
+vpaddl.s32 d0, d1 :: Qd 0x00000000 0x00000118  Qm (i32)0x0000008c
+vpaddl.s16 d0, d1 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c
+vpaddl.s8 d0, d1 :: Qd 0x0000ff8c 0x0000ff8c  Qm (i32)0x0000008c
+vpaddl.s8 d0, d1 :: Qd 0xff800001 0xff800001  Qm (i32)0x80000001
+vpaddl.s16 d0, d1 :: Qd 0xffff8001 0xffff8001  Qm (i32)0x80000001
+vpaddl.s32 d0, d1 :: Qd 0xffffffff 0x00000002  Qm (i32)0x80000001
+vpaddl.s32 d10, d11 :: Qd 0x00000000 0x00000030  Qm (i32)0x00000018
+---- VPADAL ----
+vpadal.u32 d0, d1 :: Qd 0x55555555 0x55555585  Qm (i32)0x00000018
+vpadal.u32 d0, d1 :: Qd 0x55555555 0x5555566d  Qm (i32)0x0000008c
+vpadal.u16 d0, d1 :: Qd 0x555555e1 0x555555e1  Qm (i32)0x0000008c
+vpadal.u8 d0, d1 :: Qd 0x566d566d 0x566d566d  Qm (i8)0x0000008c
+vpadal.u8 d0, d1 :: Qd 0x55d55556 0x55d55556  Qm (i32)0x80000001
+vpadal.u16 d0, d1 :: Qd 0x5555d556 0x5555d556  Qm (i32)0x80000001
+vpadal.u32 d0, d1 :: Qd 0x55555556 0x55555557  Qm (i32)0x80000001
+vpadal.u32 d10, d11 :: Qd 0x55555555 0x55555585  Qm (i32)0x00000018
+vpadal.s32 d0, d1 :: Qd 0x55555555 0x55555585  Qm (i32)0x00000018
+vpadal.s32 d0, d1 :: Qd 0x55555555 0x5555566d  Qm (i32)0x0000008c
+vpadal.s16 d0, d1 :: Qd 0x555555e1 0x555555e1  Qm (i32)0x0000008c
+vpadal.s8 d0, d1 :: Qd 0x546d546d 0x546d546d  Qm (i8)0x0000008c
+vpadal.s8 d0, d1 :: Qd 0x54d55556 0x54d55556  Qm (i32)0x80000001
+vpadal.s16 d0, d1 :: Qd 0x5554d556 0x5554d556  Qm (i32)0x80000001
+vpadal.s32 d0, d1 :: Qd 0x55555554 0x55555557  Qm (i32)0x80000001
+vpadal.s32 d10, d11 :: Qd 0x55555555 0x55555585  Qm (i32)0x00000018
+---- VZIP ----
+vzip.32 d0, d1 :: Qm 0x34343434 0x12121212  Qn 0x34343434 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vzip.16 d1, d0 :: Qm 0x12123434 0x12123434  Qn 0x12123434 0x12123434  Qm (i8)0x00000012  Qn (i8)0x00000034
+vzip.8 d10, d11 :: Qm 0x34123412 0x34123412  Qn 0x34123412 0x34123412  Qm (i8)0x00000012  Qn (i8)0x00000034
+vzip.32 d0, d1 :: Qm 0x0a0b0c0d 0x12345678  Qn 0x0a0b0c0d 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vzip.16 d1, d0 :: Qm 0x12340a0b 0x56780c0d  Qn 0x12340a0b 0x56780c0d  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vzip.8 d30, d31 :: Qm 0x0a120b34 0x0c560d78  Qn 0x0a120b34 0x0c560d78  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+---- VUZP ----
+vuzp.32 d0, d1 :: Qm 0x34343434 0x12121212  Qn 0x34343434 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vuzp.16 d1, d0 :: Qm 0x12121212 0x34343434  Qn 0x12121212 0x34343434  Qm (i8)0x00000012  Qn (i8)0x00000034
+vuzp.8 d10, d11 :: Qm 0x34343434 0x12121212  Qn 0x34343434 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vuzp.32 d0, d1 :: Qm 0x0a0b0c0d 0x12345678  Qn 0x0a0b0c0d 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vuzp.16 d1, d0 :: Qm 0x12341234 0x0a0b0a0b  Qn 0x56785678 0x0c0d0c0d  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vuzp.8 d30, d31 :: Qm 0x0b0d0b0d 0x34783478  Qn 0x0a0c0a0c 0x12561256  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+---- VTRN ----
+vtrn.32 d0, d1 :: Qm 0x34343434 0x12121212  Qn 0x34343434 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vtrn.16 d1, d0 :: Qm 0x12123434 0x12123434  Qn 0x12123434 0x12123434  Qm (i8)0x00000012  Qn (i8)0x00000034
+vtrn.8 d10, d11 :: Qm 0x34123412 0x34123412  Qn 0x34123412 0x34123412  Qm (i8)0x00000012  Qn (i8)0x00000034
+vtrn.32 d0, d1 :: Qm 0x0a0b0c0d 0x12345678  Qn 0x0a0b0c0d 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vtrn.16 d1, d0 :: Qm 0x12340a0b 0x12340a0b  Qn 0x56780c0d 0x56780c0d  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vtrn.8 d30, d31 :: Qm 0x0b340d78 0x0b340d78  Qn 0x0a120c56 0x0a120c56  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+---- VSWP ----
+vswp d0, d1 :: Qm 0x34343434 0x34343434  Qn 0x12121212 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vswp d1, d0 :: Qm 0x34343434 0x34343434  Qn 0x12121212 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vswp d10, d11 :: Qm 0x34343434 0x34343434  Qn 0x12121212 0x12121212  Qm (i8)0x00000012  Qn (i8)0x00000034
+vswp d0, d1 :: Qm 0x0a0b0c0d 0x0a0b0c0d  Qn 0x12345678 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vswp d1, d0 :: Qm 0x0a0b0c0d 0x0a0b0c0d  Qn 0x12345678 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+vswp d30, d31 :: Qm 0x0a0b0c0d 0x0a0b0c0d  Qn 0x12345678 0x12345678  Qm (i32)0x12345678  Qn (i32)0x0a0b0c0d
+---- VSHRN ----
+vshrn.i16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshrn.i16 d3, q4, #2 :: Qd 0xffe1ffe1 0xffe1ffe1  Qm (i32)0xffffff84
+vshrn.i32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshrn.i32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7fffffff
+vshrn.i64 d6, q7, #7 :: Qd 0xfe0001ff 0xfe0001ff  Qm (i32)0x0000ffff
+vshrn.i16 d8, q9, #8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffff6
+vshrn.i32 d10, q11, #5 :: Qd 0x013f013f 0x013f013f  Qm (i32)0x000027fa
+vshrn.i64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshrn.i16 d14, q15, #6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshrn.i32 d10, q11, #9 :: Qd 0x00010001 0x00010001  Qm (i32)0x000003e8
+vshrn.i64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshrn.i16 d8, q1, #1 :: Qd 0x00e700e7 0x00e700e7  Qm (i32)0x0000abcf
+vshrn.i32 d12, q3, #15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffe50
+vshrn.i64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+vshrn.i64 d6, q7, #12 :: Qd 0xfac00000 0xfac00000  Qm (i32)0x00000fac
+vshrn.i64 d8, q4, #9 :: Qd 0x7c00001a 0x7c00001a  Qm (i32)0x000034f8
+vshrn.i64 d9, q12, #11 :: Qd 0x32c00030 0x32c00030  Qm (i32)0x00018196
+---- VDUP ----
+vdup.8 d12, d2[0] :: Qd 0x57575757 0x57575757  Qm (i32)0x0abc4657
+vdup.8 d0, d3[2] :: Qd 0x07070707 0x07070707  Qm (i32)0x0007a1b3
+vdup.8 d1, d0[7] :: Qd 0x00000000 0x00000000  Qm (i32)0x00713aaa
+vdup.8 d10, d4[3] :: Qd 0x00000000 0x00000000  Qm (i32)0x000aa713
+vdup.8 d4, d28[4] :: Qd 0xc3c3c3c3 0xc3c3c3c3  Qm (i32)0x0007b1c3
+vdup.16 d17, d19[1] :: Qd 0x07130713 0x07130713  Qm (i32)0x0713ffff
+vdup.16 d15, d31[2] :: Qd 0x00fa00fa 0x00fa00fa  Qm (i32)0x007f00fa
+vdup.16 d6, d2[0] :: Qd 0xbcdebcde 0xbcdebcde  Qm (i32)0x0ffabcde
+vdup.16 d8, d22[3] :: Qd 0x00000000 0x00000000  Qm (i32)0x00000713
+vdup.16 d9, d2[0] :: Qd 0x07130713 0x07130713  Qm (i32)0x00000713
+vdup.32 d10, d17[1] :: Qd 0x00000713 0x00000713  Qm (i32)0x00000713
+vdup.32 d15, d11[0] :: Qd 0x00000003 0x00000003  Qm (i32)0x00000003
+vdup.32 d30, d29[1] :: Qd 0xf00000aa 0xf00000aa  Qm (i32)0xf00000aa
+vdup.32 d22, d0[1] :: Qd 0x0000000f 0x0000000f  Qm (i32)0x0000000f
+vdup.32 d13, d13[0] :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+---- VQDMULH ----
+vqdmulh.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmulh.s32 d6, d7, d8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmulh.s16 d9, d11, d12 :: Qd 0x00000002 0x00000002  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmulh.s16 d4, d5, d6 :: Qd 0x00001001 0x00001001  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmulh.s16 d4, d5, d6 :: Qd 0x0000e50b 0x0000e50b  Qm (i32)0xffff9433  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 d7, d8, d9 :: Qd 0xfffffff4 0xfffffff4  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmulh.s16 d4, d5, d6 :: Qd 0x0000003f 0x0000003f  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmulh.s32 d10, d11, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmulh.s32 d10, d30, d31 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmulh.s16 d10, d30, d31 :: Qd 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmulh.s32 d10, d30, d31 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmulh.s16 d10, d30, d31 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VQDMULH (by scalar) ----
+vqdmulh.s32 d0, d1, d6[0] :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmulh.s32 d6, d7, d1[1] :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqdmulh.s16 d9, d11, d7[0] :: Qd 0x00000002 0x00000002  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqdmulh.s16 d4, d5, d6[0] :: Qd 0x00001001 0x00001001  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 d7, d8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmulh.s16 d4, d5, d6[1] :: Qd 0xffffe50b 0xffffe50b  Qm (i32)0xffff9433  Qn (i16)0x00002002  fpscr: 00000000
+vqdmulh.s32 d7, d8, d9[0] :: Qd 0xfffffff4 0xfffffff4  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqdmulh.s16 d4, d5, d6[2] :: Qd 0x0400003f 0x0400003f  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqdmulh.s32 d7, d8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqdmulh.s32 d10, d31, d15[0] :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqdmulh.s32 d10, d14, d15[1] :: Qd 0xffffff88 0xffffff88  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmulh.s16 d10, d14, d7[3] :: Qd 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqdmulh.s32 d10, d14, d15[1] :: Qd 0xc0000000 0xc0000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqdmulh.s16 d31, d14, d7[1] :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VSHRN ----
+vshrn.i64 d2, q2, #1 :: Qd 0x855e232b 0x855e232b  Qm (i32)0x0abc4657
+vshrn.i64 d3, q3, #0 :: Qd 0x0007a1b3 0x0007a1b3  Qm (i32)0x0007a1b3
+vshrn.i64 d1, q0, #3 :: Qd 0x400e2755 0x400e2755  Qm (i32)0x00713aaa
+vshrn.i64 d0, q4, #5 :: Qd 0x98005538 0x98005538  Qm (i32)0x000aa713
+vshrn.i64 d4, q8, #11 :: Qd 0x386000f6 0x386000f6  Qm (i32)0x0007b1c3
+vshrn.i16 d7, q12, #6 :: Qd 0x1cff1cff 0x1cff1cff  Qm (i32)0x0713ffff
+vshrn.i16 d15, q11, #2 :: Qd 0x1f3e1f3e 0x1f3e1f3e  Qm (i32)0x007f00fa
+vshrn.i16 d6, q2, #4 :: Qd 0x00ab00ab 0x00ab00ab  Qm (i32)0x000ffabc
+vshrn.i16 d8, q12, #3 :: Qd 0x00e200e2 0x00e200e2  Qm (i32)0x00000713
+vshrn.i16 d9, q2, #7 :: Qd 0x000e000e 0x000e000e  Qm (i32)0x00000713
+vshrn.i32 d10, q13, #2 :: Qd 0x01c401c4 0x01c401c4  Qm (i32)0x00000713
+vshrn.i32 d15, q11, #1 :: Qd 0x00010001 0x00010001  Qm (i32)0x00000003
+vshrn.i32 d10, q9, #5 :: Qd 0x00050005 0x00050005  Qm (i32)0xf00000aa
+vshrn.i32 d12, q0, #6 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000000f
+vshrn.i32 d13, q13, #2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff
+---- VQSHRN ----
+vqshrn.s16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 00000000
+vqshrn.s16 d3, q4, #2 :: Qd 0xffe1ffe1 0xffe1ffe1  Qm (i32)0xffffff84  fpscr 00000000
+vqshrn.s32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 00000000
+vqshrn.s32 d2, q5, #1 :: Qd 0x7fff7fff 0x7fff7fff  Qm (i32)0x7fffffff  fpscr 08000000
+vqshrn.s16 d2, q5, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f  Qm (i16)0x00007fff  fpscr 08000000
+vqshrn.s64 d6, q7, #7 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x0000ffff  fpscr 08000000
+vqshrn.s16 d8, q9, #8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffff6  fpscr 00000000
+vqshrn.s32 d10, q11, #5 :: Qd 0x013f013f 0x013f013f  Qm (i32)0x000027fa  fpscr 00000000
+vqshrn.s64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 00000000
+vqshrn.s16 d14, q15, #6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 00000000
+vqshrn.s32 d10, q11, #9 :: Qd 0x00010001 0x00010001  Qm (i32)0x000003e8  fpscr 00000000
+vqshrn.s64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 00000000
+vqshrn.s16 d8, q1, #1 :: Qd 0x00800080 0x00800080  Qm (i32)0x0000abcf  fpscr 08000000
+vqshrn.s32 d8, q1, #1 :: Qd 0x55e755e7 0x55e755e7  Qm (i32)0x0000abcf  fpscr 00000000
+vqshrn.s32 d12, q3, #15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffe50  fpscr 00000000
+vqshrn.s64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 00000000
+vqshrn.s64 d6, q7, #12 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x00000fac  fpscr 08000000
+vqshrn.s64 d8, q4, #9 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x000034f8  fpscr 08000000
+vqshrn.s64 d9, q12, #11 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x00018196  fpscr 08000000
+vqshrn.u16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshrn.u16 d3, q4, #2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff84  fpscr 08000000
+vqshrn.u32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshrn.u32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7fffffff  fpscr 08000000
+vqshrn.u16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i16)0x00007fff  fpscr 08000000
+vqshrn.u64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000ffff  fpscr 08000000
+vqshrn.u16 d8, q9, #8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffff6  fpscr 00000000
+vqshrn.u32 d10, q11, #5 :: Qd 0x013f013f 0x013f013f  Qm (i32)0x000027fa  fpscr 00000000
+vqshrn.u64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshrn.u16 d14, q15, #6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshrn.u32 d10, q11, #9 :: Qd 0x00010001 0x00010001  Qm (i32)0x000003e8  fpscr 00000000
+vqshrn.u64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshrn.u16 d8, q1, #1 :: Qd 0x00ff00ff 0x00ff00ff  Qm (i32)0x0000abcf  fpscr 08000000
+vqshrn.u32 d8, q1, #1 :: Qd 0x55e755e7 0x55e755e7  Qm (i32)0x0000abcf  fpscr 00000000
+vqshrn.u32 d12, q3, #15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffe50  fpscr 08000000
+vqshrn.u64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqshrn.u64 d6, q7, #12 :: Qd 0xfac00000 0xfac00000  Qm (i32)0x00000fac  fpscr 00000000
+vqshrn.u64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x000034f8  fpscr 08000000
+vqshrn.u64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00018196  fpscr 08000000
+---- VQSHRUN ----
+vqshrun.s16 d0, q1, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshrun.s16 d3, q4, #2 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff84  fpscr 08000000
+vqshrun.s32 d2, q5, #10 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshrun.s32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7fffffff  fpscr 08000000
+vqshrun.s16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i16)0x00007fff  fpscr 08000000
+vqshrun.s64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000ffff  fpscr 08000000
+vqshrun.s16 d8, q9, #8 :: Qd 0x00000000 0x00000000  Qm (i32)0xfffffff6  fpscr 08000000
+vqshrun.s32 d10, q11, #5 :: Qd 0x013f013f 0x013f013f  Qm (i32)0x000027fa  fpscr 00000000
+vqshrun.s64 d12, q13, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshrun.s16 d14, q15, #6 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshrun.s32 d10, q11, #9 :: Qd 0x00010001 0x00010001  Qm (i32)0x000003e8  fpscr 00000000
+vqshrun.s64 d7, q13, #7 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshrun.s16 d8, q1, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000abcf  fpscr 08000000
+vqshrun.s32 d8, q1, #1 :: Qd 0x55e755e7 0x55e755e7  Qm (i32)0x0000abcf  fpscr 00000000
+vqshrun.s32 d12, q3, #15 :: Qd 0x00000000 0x00000000  Qm (i32)0xfffffe50  fpscr 08000000
+vqshrun.s64 d0, q1, #22 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 08000000
+vqshrun.s64 d6, q7, #12 :: Qd 0xfac00000 0xfac00000  Qm (i32)0x00000fac  fpscr 00000000
+vqshrun.s64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x000034f8  fpscr 08000000
+vqshrun.s64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00018196  fpscr 08000000
+---- VQRSHRN ----
+vqrshrn.s16 d0, q1, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrn.s16 d3, q4, #2 :: Qd 0x00e100e1 0x00e100e1  Qm (i32)0xffffff84  fpscr 00000000
+vqrshrn.s32 d2, q5, #10 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrn.s32 d2, q5, #1 :: Qd 0x7fff7fff 0x7fff7fff  Qm (i32)0x7fffffff  fpscr 08000000
+vqrshrn.s16 d2, q5, #1 :: Qd 0x7f7f7f7f 0x7f7f7f7f  Qm (i16)0x00007fff  fpscr 08000000
+vqrshrn.s64 d6, q7, #7 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x0000ffff  fpscr 08000000
+vqrshrn.s16 d8, q9, #8 :: Qd 0x00000000 0x00000000  Qm (i32)0xfffffff6  fpscr 00000000
+vqrshrn.s32 d10, q11, #5 :: Qd 0x01400140 0x01400140  Qm (i32)0x000027fa  fpscr 00000000
+vqrshrn.s64 d12, q13, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrn.s16 d14, q15, #6 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrn.s32 d10, q11, #9 :: Qd 0x00020002 0x00020002  Qm (i32)0x000003e8  fpscr 00000000
+vqrshrn.s64 d7, q13, #7 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrn.s16 d8, q1, #1 :: Qd 0x00800080 0x00800080  Qm (i32)0x0000abcf  fpscr 08000000
+vqrshrn.s32 d8, q1, #1 :: Qd 0x55e855e8 0x55e855e8  Qm (i32)0x0000abcf  fpscr 00000000
+vqrshrn.s32 d12, q3, #15 :: Qd 0x00000000 0x00000000  Qm (i32)0xfffffe50  fpscr 00000000
+vqrshrn.s64 d0, q1, #22 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrn.s64 d6, q7, #12 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x00000fac  fpscr 08000000
+vqrshrn.s64 d8, q4, #9 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x000034f8  fpscr 08000000
+vqrshrn.s64 d9, q12, #11 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x00018196  fpscr 08000000
+vqrshrn.u16 d0, q1, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqrshrn.u16 d3, q4, #2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffff84  fpscr 08000000
+vqrshrn.u32 d2, q5, #10 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqrshrn.u32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7fffffff  fpscr 08000000
+vqrshrn.u16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i16)0x00007fff  fpscr 08000000
+vqrshrn.u64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000ffff  fpscr 08000000
+vqrshrn.u16 d8, q9, #8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffff6  fpscr 08000000
+vqrshrn.u32 d10, q11, #5 :: Qd 0x01400140 0x01400140  Qm (i32)0x000027fa  fpscr 00000000
+vqrshrn.u64 d12, q13, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqrshrn.u16 d14, q15, #6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqrshrn.u32 d10, q11, #9 :: Qd 0x00020002 0x00020002  Qm (i32)0x000003e8  fpscr 00000000
+vqrshrn.u64 d7, q13, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqrshrn.u16 d8, q1, #1 :: Qd 0x00ff00ff 0x00ff00ff  Qm (i32)0x0000abcf  fpscr 08000000
+vqrshrn.u32 d8, q1, #1 :: Qd 0x55e855e8 0x55e855e8  Qm (i32)0x0000abcf  fpscr 00000000
+vqrshrn.u32 d12, q3, #15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xfffffe50  fpscr 08000000
+vqrshrn.u64 d0, q1, #22 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xffffffff  fpscr 08000000
+vqrshrn.u64 d6, q7, #12 :: Qd 0xfac00001 0xfac00001  Qm (i32)0x00000fac  fpscr 00000000
+vqrshrn.u64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x000034f8  fpscr 08000000
+vqrshrn.u64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00018196  fpscr 08000000
+---- VQRSHRUN ----
+vqrshrun.s16 d0, q1, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrun.s16 d3, q4, #2 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffff84  fpscr 08000000
+vqrshrun.s32 d2, q5, #10 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrun.s32 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7fffffff  fpscr 08000000
+vqrshrun.s16 d2, q5, #1 :: Qd 0xffffffff 0xffffffff  Qm (i16)0x00007fff  fpscr 08000000
+vqrshrun.s64 d6, q7, #7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x0000ffff  fpscr 08000000
+vqrshrun.s16 d8, q9, #8 :: Qd 0x00000000 0x00000000  Qm (i32)0xfffffff6  fpscr 00000000
+vqrshrun.s32 d10, q11, #5 :: Qd 0x01400140 0x01400140  Qm (i32)0x000027fa  fpscr 00000000
+vqrshrun.s64 d12, q13, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrun.s16 d14, q15, #6 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrun.s32 d10, q11, #9 :: Qd 0x00020002 0x00020002  Qm (i32)0x000003e8  fpscr 00000000
+vqrshrun.s64 d7, q13, #7 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrun.s16 d8, q1, #1 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000abcf  fpscr 08000000
+vqrshrun.s32 d8, q1, #1 :: Qd 0x55e855e8 0x55e855e8  Qm (i32)0x0000abcf  fpscr 00000000
+vqrshrun.s32 d12, q3, #15 :: Qd 0x00000000 0x00000000  Qm (i32)0xfffffe50  fpscr 00000000
+vqrshrun.s64 d0, q1, #22 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff  fpscr 00000000
+vqrshrun.s64 d6, q7, #12 :: Qd 0xfac00001 0xfac00001  Qm (i32)0x00000fac  fpscr 00000000
+vqrshrun.s64 d8, q4, #9 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x000034f8  fpscr 08000000
+vqrshrun.s64 d9, q12, #11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00018196  fpscr 08000000
+---- VRSHRN ----
+vrshrn.i64 d2, q2, #1 :: Qd 0x855e232c 0x855e232c  Qm (i32)0x0abc4657
+vrshrn.i64 d3, q3, #0 :: Qd 0x0007a1b3 0x0007a1b3  Qm (i32)0x0007a1b3
+vrshrn.i64 d1, q0, #3 :: Qd 0x400e2755 0x400e2755  Qm (i32)0x00713aaa
+vrshrn.i64 d0, q4, #5 :: Qd 0x98005539 0x98005539  Qm (i32)0x000aa713
+vrshrn.i64 d4, q8, #11 :: Qd 0x386000f6 0x386000f6  Qm (i32)0x0007b1c3
+vrshrn.i16 d7, q12, #6 :: Qd 0x1c001c00 0x1c001c00  Qm (i32)0x0713ffff
+vrshrn.i16 d15, q11, #2 :: Qd 0x203f203f 0x203f203f  Qm (i32)0x007f00fa
+vrshrn.i16 d6, q2, #4 :: Qd 0x01ac01ac 0x01ac01ac  Qm (i32)0x000ffabc
+vrshrn.i16 d8, q12, #3 :: Qd 0x00e200e2 0x00e200e2  Qm (i32)0x00000713
+vrshrn.i16 d9, q2, #7 :: Qd 0x000e000e 0x000e000e  Qm (i32)0x00000713
+vrshrn.i32 d10, q13, #2 :: Qd 0x01c501c5 0x01c501c5  Qm (i32)0x00000713
+vrshrn.i32 d15, q11, #1 :: Qd 0x00020002 0x00020002  Qm (i32)0x00000003
+vrshrn.i32 d10, q9, #5 :: Qd 0x00050005 0x00050005  Qm (i32)0xf00000aa
+vrshrn.i32 d12, q0, #6 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000000f
+vrshrn.i32 d13, q13, #2 :: Qd 0x00000000 0x00000000  Qm (i32)0xffffffff
+---- VSHL (immediate) ----
+vshl.i64 d0, d1, #1 :: Qd 0x00000030 0x00000030  Qm (i32)0x00000018
+vshl.i64 d5, d2, #1 :: Qd 0x80000000 0x80000000  Qm (i32)0x40000000
+vshl.i64 d9, d12, #2 :: Qd 0x0000000a 0x00000008  Qm (i32)0x80000002
+vshl.i64 d11, d2, #12 :: Qd 0xffffffff 0xfffff000  Qm (i32)0xffffffff
+vshl.i64 d15, d12, #63 :: Qd 0x80000000 0x00000000  Qm (i32)0x00000005
+vshl.i64 d5, d12, #62 :: Qd 0x40000000 0x00000000  Qm (i32)0x80000001
+vshl.i32 d0, d1, #1 :: Qd 0x00000030 0x00000030  Qm (i32)0x00000018
+vshl.i32 d5, d2, #1 :: Qd 0x80000000 0x80000000  Qm (i32)0x40000000
+vshl.i32 d9, d12, #2 :: Qd 0x00000008 0x00000008  Qm (i32)0x80000002
+vshl.i32 d11, d2, #12 :: Qd 0xfffff000 0xfffff000  Qm (i32)0xffffffff
+vshl.i32 d15, d12, #20 :: Qd 0x00500000 0x00500000  Qm (i32)0x00000005
+vshl.i32 d5, d12, #30 :: Qd 0x40000000 0x40000000  Qm (i32)0x80000001
+vshl.i16 d0, d1, #1 :: Qd 0x00300030 0x00300030  Qm (i16)0x00000018
+vshl.i16 d5, d2, #1 :: Qd 0x80000000 0x80000000  Qm (i32)0x40000000
+vshl.i16 d9, d12, #2 :: Qd 0x00000008 0x00000008  Qm (i32)0x80000002
+vshl.i16 d11, d2, #12 :: Qd 0xf000f000 0xf000f000  Qm (i16)0xffffffff
+vshl.i16 d15, d12, #3 :: Qd 0x00280028 0x00280028  Qm (i16)0x00000005
+vshl.i16 d5, d12, #14 :: Qd 0x00004000 0x00004000  Qm (i32)0x80000001
+vshl.i8 d0, d1, #1 :: Qd 0x30303030 0x30303030  Qm (i8)0x00000018
+vshl.i8 d5, d2, #1 :: Qd 0x80000000 0x80000000  Qm (i32)0x40000000
+vshl.i8 d9, d12, #2 :: Qd 0x00000008 0x00000008  Qm (i32)0x80000002
+vshl.i8 d11, d2, #7 :: Qd 0x80808080 0x80808080  Qm (i8)0xffffffff
+vshl.i8 d15, d12, #3 :: Qd 0x28282828 0x28282828  Qm (i8)0x00000005
+vshl.i8 d5, d12, #6 :: Qd 0x00000040 0x00000040  Qm (i32)0x80000001
+---- VNEG ----
+vneg.s32 d0, d1 :: Qd 0xffffff8d 0xffffff8d  Qm (i32)0x00000073
+vneg.s16 d15, d4 :: Qd 0x0000ff8d 0x0000ff8d  Qm (i32)0x00000073
+vneg.s8 d8, d7 :: Qd 0x0000008d 0x0000008d  Qm (i32)0x00000073
+vneg.s32 d0, d1 :: Qd 0xffffff02 0xffffff02  Qm (i32)0x000000fe
+vneg.s16 d31, d4 :: Qd 0x0000ff11 0x0000ff11  Qm (i32)0x000000ef
+vneg.s8 d8, d7 :: Qd 0x00000022 0x00000022  Qm (i32)0x000000de
+vneg.s32 d0, d1 :: Qd 0x01f501f6 0x01f501f6  Qm (i16)0x0000fe0a
+vneg.s16 d15, d4 :: Qd 0x10f510f5 0x10f510f5  Qm (i16)0x0000ef0b
+vneg.s8 d8, d7 :: Qd 0x22f422f4 0x22f422f4  Qm (i16)0x0000de0c
+---- VQNEG ----
+vqneg.s32 d0, d1 :: Qd 0xffffff8d 0xffffff8d  Qm (i32)0x00000073  fpscr 00000000
+vqneg.s32 d0, d1 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  fpscr 08000000
+vqneg.s16 d0, d1 :: Qd 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  fpscr 08000000
+vqneg.s8 d0, d1 :: Qd 0x7f000000 0x7f000000  Qm (i32)0x80000000  fpscr 08000000
+vqneg.s16 d15, d4 :: Qd 0x0000ff8d 0x0000ff8d  Qm (i32)0x00000073  fpscr 00000000
+vqneg.s8 d8, d7 :: Qd 0x0000008d 0x0000008d  Qm (i32)0x00000073  fpscr 00000000
+vqneg.s32 d0, d1 :: Qd 0xffffff02 0xffffff02  Qm (i32)0x000000fe  fpscr 00000000
+vqneg.s16 d31, d4 :: Qd 0x0000ff11 0x0000ff11  Qm (i32)0x000000ef  fpscr 00000000
+vqneg.s8 d8, d7 :: Qd 0x00000022 0x00000022  Qm (i32)0x000000de  fpscr 00000000
+vqneg.s32 d0, d1 :: Qd 0x01f501f6 0x01f501f6  Qm (i16)0x0000fe0a  fpscr 00000000
+vqneg.s16 d15, d4 :: Qd 0x10f510f5 0x10f510f5  Qm (i16)0x0000ef0b  fpscr 00000000
+vqneg.s8 d8, d7 :: Qd 0x22f422f4 0x22f422f4  Qm (i16)0x0000de0c  fpscr 00000000
+---- VREV ----
+vrev64.8 d0, d1 :: Qd 0xddccbbaa 0xddccbbaa  Qm (i32)0xaabbccdd
+vrev64.16 d10, d31 :: Qd 0xccddaabb 0xccddaabb  Qm (i32)0xaabbccdd
+vrev64.32 d1, d14 :: Qd 0xaabbccdd 0xaabbccdd  Qm (i32)0xaabbccdd
+vrev32.8 d0, d1 :: Qd 0xddccbbaa 0xddccbbaa  Qm (i32)0xaabbccdd
+vrev32.16 d30, d15 :: Qd 0xccddaabb 0xccddaabb  Qm (i32)0xaabbccdd
+vrev16.8 d0, d1 :: Qd 0xbbaaddcc 0xbbaaddcc  Qm (i32)0xaabbccdd
+---- VTBL ----
+vtbl.8 d0, {d2}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000000  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbl.8 d0, {d31}, d1 :: Qd 0x12121212 0x12121212  Qm (i8)0x00000007  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbl.8 d0, {d20}, d1 :: Qd 0x56565656 0x56565656  Qm (i8)0x00000001  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbl.8 d0, {d2}, d31 :: Qd 0x34343434 0x34343434  Qm (i8)0x00000002  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbl.8 d30, {d2}, d1 :: Qd 0x12125656 0x12125656  Qm (i32)0x07030501  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbl.8 d31, {d2}, d1 :: Qd 0x56785678 0x56785678  Qm (i16)0x00000104  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbl.8 d30, {d2}, d1 :: Qd 0x12005656 0x12005656  Qm (i32)0x07080501  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbl.8 d30, {d2}, d1 :: Qd 0x12005600 0x12005600  Qm (i32)0x07ed05ee  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbl.8 d0, {d2-d3}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000000  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d1-d2}, d3 :: Qd 0xa2a2a2a2 0xa2a2a2a2  Qm (i8)0x0000000a  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d30-d31}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1  Qm (i8)0x0000000f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3  Qm (i8)0x00000009  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1  Qm (i8)0x0000000f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d23}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000004  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa2a2a2a2 0xa2a2a2a2  Qm (i8)0x0000000e  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1  Qm (i8)0x0000000f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d3}, d31 :: Qd 0x12125656 0x12125656  Qm (i32)0x07030501  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d3}, d31 :: Qd 0xa4a25656 0xa4a25656  Qm (i32)0x0c0a0501  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d3}, d31 :: Qd 0x12a2a256 0x12a2a256  Qm (i32)0x070e0e01  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d3}, d31 :: Qd 0xa300a156 0xa300a156  Qm (i32)0x0d130f01  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d3}, d31 :: Qd 0x12125600 0x12125600  Qm (i32)0x07030511  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d2-d4}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000000  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d1-d3}, d10 :: Qd 0xcccccccc 0xcccccccc  Qm (i8)0x00000011  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d29-d31}, d1 :: Qd 0xcacacaca 0xcacacaca  Qm (i8)0x00000017  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d24}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3  Qm (i8)0x00000009  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d24}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1  Qm (i8)0x0000000f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d24}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000004  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d24}, d1 :: Qd 0xcdcdcdcd 0xcdcdcdcd  Qm (i8)0x00000010  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d22-d24}, d1 :: Qd 0xcccccccc 0xcccccccc  Qm (i8)0x00000011  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa212cc78 0xa212cc78  Qm (i32)0x0a031504  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa4a25656 0xa4a25656  Qm (i32)0x0c0a0501  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d4}, d31 :: Qd 0xcaa200a1 0xcaa200a1  Qm (i32)0x170efe0f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d4}, d31 :: Qd 0xa3caa1cc 0xa3caa1cc  Qm (i32)0x0d130f11  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d30, {d2-d4}, d31 :: Qd 0x12a1cccc 0x12a1cccc  Qm (i32)0x070f1511  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbl.8 d0, {d2-d5}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000000  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d0, {d1-d4}, d10 :: Qd 0xcccccccc 0xcccccccc  Qm (i8)0x00000011  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d0, {d28-d31}, d1 :: Qd 0xcacacaca 0xcacacaca  Qm (i8)0x00000017  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d0, {d22-d25}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3  Qm (i8)0x00000009  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d0, {d22-d25}, d1 :: Qd 0xfdfdfdfd 0xfdfdfdfd  Qm (i8)0x0000001a  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d0, {d22-d25}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000004  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d0, {d22-d25}, d1 :: Qd 0xcbcbcbcb 0xcbcbcbcb  Qm (i8)0x00000016  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d0, {d22-d25}, d1 :: Qd 0xfefefefe 0xfefefefe  Qm (i8)0x0000001f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d30, {d2-d5}, d31 :: Qd 0xfd12cc00 0xfd12cc00  Qm (i32)0x1a0315ff  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d30, {d2-d5}, d31 :: Qd 0xa4a25656 0xa4a25656  Qm (i32)0x0c0a0501  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d30, {d2-d5}, d31 :: Qd 0xcafd00a1 0xcafd00a1  Qm (i32)0x171efe0f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d30, {d2-d5}, d31 :: Qd 0xfccaa1fd 0xfccaa1fd  Qm (i32)0x1d130f1a  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbl.8 d30, {d2-d5}, d31 :: Qd 0xcacdfbcc 0xcacdfbcc  Qm (i32)0x17101c11  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+---- VTBX ----
+vtbx.8 d0, {d2}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000000  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbx.8 d0, {d31}, d1 :: Qd 0x12121212 0x12121212  Qm (i8)0x00000007  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbx.8 d0, {d20}, d1 :: Qd 0x56565656 0x56565656  Qm (i8)0x00000001  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbx.8 d0, {d2}, d31 :: Qd 0x34343434 0x34343434  Qm (i8)0x00000002  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbx.8 d30, {d2}, d1 :: Qd 0x12125656 0x12125656  Qm (i32)0x07030501  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbx.8 d31, {d2}, d1 :: Qd 0x56785678 0x56785678  Qm (i16)0x00000104  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbx.8 d30, {d2}, d1 :: Qd 0x12555656 0x12555656  Qm (i32)0x07080501  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbx.8 d30, {d2}, d1 :: Qd 0x12555655 0x12555655  Qm (i32)0x07ed05ee  Qn1 (i32)0x12345678  Qn2 (i32)0x12345678  Qn3 (i32)0x12345678  Qn4 (i32)0x12345678
+vtbx.8 d0, {d2-d3}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000000  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d1-d2}, d3 :: Qd 0xa2a2a2a2 0xa2a2a2a2  Qm (i8)0x0000000a  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d30-d31}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1  Qm (i8)0x0000000f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3  Qm (i8)0x00000009  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1  Qm (i8)0x0000000f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d23}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000004  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa2a2a2a2 0xa2a2a2a2  Qm (i8)0x0000000e  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d23}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1  Qm (i8)0x0000000f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d3}, d31 :: Qd 0x12125656 0x12125656  Qm (i32)0x07030501  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d3}, d31 :: Qd 0xa4a25656 0xa4a25656  Qm (i32)0x0c0a0501  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d3}, d31 :: Qd 0x12a2a256 0x12a2a256  Qm (i32)0x070e0e01  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d3}, d31 :: Qd 0xa355a156 0xa355a156  Qm (i32)0x0d130f01  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d3}, d31 :: Qd 0x12125655 0x12125655  Qm (i32)0x07030511  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0x12345678  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d2-d4}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000000  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d1-d3}, d10 :: Qd 0xcccccccc 0xcccccccc  Qm (i8)0x00000011  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d29-d31}, d1 :: Qd 0xcacacaca 0xcacacaca  Qm (i8)0x00000017  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d24}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3  Qm (i8)0x00000009  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d24}, d1 :: Qd 0xa1a1a1a1 0xa1a1a1a1  Qm (i8)0x0000000f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d24}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000004  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d24}, d1 :: Qd 0xcdcdcdcd 0xcdcdcdcd  Qm (i8)0x00000010  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d22-d24}, d1 :: Qd 0xcccccccc 0xcccccccc  Qm (i8)0x00000011  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa212cc78 0xa212cc78  Qm (i32)0x0a031504  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa4a25656 0xa4a25656  Qm (i32)0x0c0a0501  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d4}, d31 :: Qd 0xcaa255a1 0xcaa255a1  Qm (i32)0x170efe0f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d4}, d31 :: Qd 0xa3caa1cc 0xa3caa1cc  Qm (i32)0x0d130f11  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d30, {d2-d4}, d31 :: Qd 0x12a1cccc 0x12a1cccc  Qm (i32)0x070f1511  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xa1a2a3a4
+vtbx.8 d0, {d2-d5}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000000  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d0, {d1-d4}, d10 :: Qd 0xcccccccc 0xcccccccc  Qm (i8)0x00000011  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d0, {d28-d31}, d1 :: Qd 0xcacacaca 0xcacacaca  Qm (i8)0x00000017  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d0, {d22-d25}, d1 :: Qd 0xa3a3a3a3 0xa3a3a3a3  Qm (i8)0x00000009  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d0, {d22-d25}, d1 :: Qd 0xfdfdfdfd 0xfdfdfdfd  Qm (i8)0x0000001a  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d0, {d22-d25}, d1 :: Qd 0x78787878 0x78787878  Qm (i8)0x00000004  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d0, {d22-d25}, d1 :: Qd 0xcbcbcbcb 0xcbcbcbcb  Qm (i8)0x00000016  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d0, {d22-d25}, d1 :: Qd 0xfefefefe 0xfefefefe  Qm (i8)0x0000001f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d30, {d2-d5}, d31 :: Qd 0xfd12cc55 0xfd12cc55  Qm (i32)0x1a0315ff  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d30, {d2-d5}, d31 :: Qd 0xa4a25656 0xa4a25656  Qm (i32)0x0c0a0501  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d30, {d2-d5}, d31 :: Qd 0xcafd55a1 0xcafd55a1  Qm (i32)0x171efe0f  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d30, {d2-d5}, d31 :: Qd 0xfccaa1fd 0xfccaa1fd  Qm (i32)0x1d130f1a  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+vtbx.8 d30, {d2-d5}, d31 :: Qd 0xcacdfbcc 0xcacdfbcc  Qm (i32)0x17101c11  Qn1 (i32)0x12345678  Qn2 (i32)0xa1a2a3a4  Qn3 (i32)0xcacbcccd  Qn4 (i32)0xfefdfcfb
+---- VPMAX (integer) ----
+vpmax.s32 d0, d1, d2 :: Qd 0x00000079 0x00000019  Qm (i32)0x00000019  Qn (i32)0x00000079
+vpmax.s32 d0, d1, d2 :: Qd 0x00000079 0x000000fa  Qm (i32)0x000000fa  Qn (i32)0x00000079
+vpmax.s32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vpmax.s16 d0, d1, d2 :: Qd 0x00780078 0x01400140  Qm (i32)0x01200140  Qn (i32)0x00000078
+vpmax.s8 d0, d1, d2 :: Qd 0x00780078 0x00780078  Qm (i32)0x00000078  Qn (i32)0x00000078
+vpmax.s8 d5, d7, d5 :: Qd 0x00020002 0x00010001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmax.s16 d0, d1, d2 :: Qd 0x00020002 0x00010001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmax.s32 d0, d1, d2 :: Qd 0x80000002 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmax.s8 d5, d7, d5 :: Qd 0x00030003 0x00010001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmax.s16 d0, d1, d2 :: Qd 0x00030003 0x00010001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmax.s32 d0, d1, d2 :: Qd 0x80000003 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmax.s8 d5, d7, d5 :: Qd 0x00020002 0x00040004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmax.s16 d0, d1, d2 :: Qd 0x00020002 0x00040004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmax.s32 d0, d1, d2 :: Qd 0x80000002 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmax.s32 d10, d11, d12 :: Qd 0x00000078 0x00000018  Qm (i32)0x00000018  Qn (i32)0x00000078
+vpmax.u32 d0, d1, d2 :: Qd 0x00000078 0x00000019  Qm (i32)0x00000019  Qn (i32)0x00000078
+vpmax.u32 d0, d1, d2 :: Qd 0x00000078 0x000000fa  Qm (i32)0x000000fa  Qn (i32)0x00000078
+vpmax.u32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vpmax.u16 d0, d1, d2 :: Qd 0x00780078 0x01400140  Qm (i32)0x01200140  Qn (i32)0x00000078
+vpmax.u8 d0, d1, d2 :: Qd 0x00780078 0x20212021  Qm (i32)0x01202120  Qn (i32)0x00000078
+vpmax.u8 d0, d1, d2 :: Qd 0x80028002 0x80018001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmax.u32 d0, d1, d2 :: Qd 0x80000002 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmax.u8 d0, d1, d2 :: Qd 0x80038003 0x80018001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmax.u32 d0, d1, d2 :: Qd 0x80000003 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmax.u8 d0, d1, d2 :: Qd 0x80028002 0x80048004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmax.u16 d0, d1, d2 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmax.u32 d0, d1, d2 :: Qd 0x80000002 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmax.u32 d10, d11, d12 :: Qd 0x00000078 0x00000018  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VPMIN (integer) ----
+vpmin.s32 d0, d1, d2 :: Qd 0x00000079 0x00000019  Qm (i32)0x00000019  Qn (i32)0x00000079
+vpmin.s32 d0, d1, d2 :: Qd 0x00000079 0x000000fa  Qm (i32)0x000000fa  Qn (i32)0x00000079
+vpmin.s32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vpmin.s16 d0, d1, d2 :: Qd 0x00000000 0x01200120  Qm (i32)0x01200140  Qn (i32)0x00000078
+vpmin.s8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000078  Qn (i32)0x00000078
+vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmin.s32 d0, d1, d2 :: Qd 0x80000002 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmin.s32 d0, d1, d2 :: Qd 0x80000003 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmin.s8 d5, d7, d5 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmin.s16 d0, d1, d2 :: Qd 0x80008000 0x80008000  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmin.s32 d0, d1, d2 :: Qd 0x80000002 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmin.s32 d10, d11, d12 :: Qd 0x00000078 0x00000018  Qm (i32)0x00000018  Qn (i32)0x00000078
+vpmin.u32 d0, d1, d2 :: Qd 0x00000078 0x00000019  Qm (i32)0x00000019  Qn (i32)0x00000078
+vpmin.u32 d0, d1, d2 :: Qd 0x00000078 0x000000fa  Qm (i32)0x000000fa  Qn (i32)0x00000078
+vpmin.u32 d0, d1, d2 :: Qd 0x0000008c 0x0000008c  Qm (i32)0x0000008c  Qn (i32)0x0000008c
+vpmin.u16 d0, d1, d2 :: Qd 0x00000000 0x01200120  Qm (i32)0x01200140  Qn (i32)0x00000078
+vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x01200120  Qm (i32)0x01202120  Qn (i32)0x00000078
+vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmin.u16 d0, d1, d2 :: Qd 0x00020002 0x00010001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmin.u32 d0, d1, d2 :: Qd 0x80000002 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000002
+vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmin.u16 d0, d1, d2 :: Qd 0x00030003 0x00010001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmin.u32 d0, d1, d2 :: Qd 0x80000003 0x80000001  Qm (i32)0x80000001  Qn (i32)0x80000003
+vpmin.u8 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmin.u16 d0, d1, d2 :: Qd 0x00020002 0x00040004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmin.u32 d0, d1, d2 :: Qd 0x80000002 0x80000004  Qm (i32)0x80000004  Qn (i32)0x80000002
+vpmin.u32 d10, d11, d12 :: Qd 0x00000078 0x00000018  Qm (i32)0x00000018  Qn (i32)0x00000078
+---- VQRDMULH ----
+vqrdmulh.s32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqrdmulh.s32 d6, d7, d8 :: Qd 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqrdmulh.s16 d9, d11, d12 :: Qd 0x00000003 0x00000003  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqrdmulh.s16 d4, d5, d6 :: Qd 0x00001001 0x00001001  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqrdmulh.s16 d4, d5, d6 :: Qd 0x0000e50b 0x0000e50b  Qm (i32)0xffff9433  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 d7, d8, d9 :: Qd 0xfffffff4 0xfffffff4  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqrdmulh.s16 d4, d5, d6 :: Qd 0x00000040 0x00000040  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 d7, d8, d9 :: Qd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqrdmulh.s32 d10, d11, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqrdmulh.s32 d10, d30, d31 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 08000000
+vqrdmulh.s16 d10, d30, d31 :: Qd 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  Qn (i32)0x80000001  fpscr: 08000000
+vqrdmulh.s32 d10, d30, d31 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqrdmulh.s16 d10, d30, d31 :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VQRDMULH (by scalar) ----
+vqrdmulh.s32 d0, d1, d6[0] :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqrdmulh.s32 d6, d7, d1[1] :: Qd 0x00000000 0x00000000  Qm (i32)0x0000008c  Qn (i32)0xffffff88  fpscr: 00000000
+vqrdmulh.s16 d9, d11, d7[0] :: Qd 0x00000003 0x00000003  Qm (i32)0x00000140  Qn (i32)0x00000120  fpscr: 00000000
+vqrdmulh.s16 d4, d5, d6[0] :: Qd 0x00001001 0x00001001  Qm (i32)0x00004001  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 d7, d8, d9[1] :: Qd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqrdmulh.s16 d4, d5, d6[1] :: Qd 0x0000e50b 0x0000e50b  Qm (i32)0xffff9433  Qn (i16)0x00002002  fpscr: 00000000
+vqrdmulh.s32 d7, d8, d9[0] :: Qd 0xfffffff4 0xfffffff4  Qm (i32)0x80000000  Qn (i32)0x0000000c  fpscr: 00000000
+vqrdmulh.s16 d4, d5, d6[2] :: Qd 0x04000040 0x04000040  Qm (i32)0x100000fe  Qn (i32)0x00002002  fpscr: 00000000
+vqrdmulh.s32 d7, d8, d9[0] :: Qd 0x7ffffffd 0x7ffffffd  Qm (i32)0x80000001  Qn (i32)0x80000002  fpscr: 00000000
+vqrdmulh.s32 d10, d31, d15[0] :: Qd 0x00000000 0x00000000  Qm (i32)0x00000018  Qn (i32)0x00000078  fpscr: 00000000
+vqrdmulh.s32 d10, d14, d15[1] :: Qd 0xffffff88 0xffffff88  Qm (i32)0x80000000  Qn (i32)0x80000000  fpscr: 00000000
+vqrdmulh.s16 d10, d14, d7[3] :: Qd 0x7fff0000 0x7fff0000  Qm (i32)0x80000000  Qn (i32)0x80000001  fpscr: 08000000
+vqrdmulh.s32 d10, d14, d15[1] :: Qd 0xc0000000 0xc0000000  Qm (i32)0x40000000  Qn (i32)0x80000000  fpscr: 00000000
+vqrdmulh.s16 d31, d14, d7[1] :: Qd 0xc0000000 0xc0000000  Qm (i32)0x80000000  Qn (i32)0x40000000  fpscr: 00000000
+---- VADD (fp) ----
+vadd.f32 d0, d5, d2 :: Qd 0xc1b43ac6 0xc1b43ac6  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vadd.f32 d3, d4, d5 :: Qd 0xc8a931cf 0xc8a931cf  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vadd.f32 d10, d11, d2 :: Qd 0x45398860 0x45398860  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vadd.f32 d9, d5, d7 :: Qd 0x47dc9261 0x47dc9261  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vadd.f32 d0, d5, d2 :: Qd 0xc88faac0 0xc88faac0  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vadd.f32 d3, d4, d5 :: Qd 0x44ab5c08 0x44ab5c08  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vadd.f32 d10, d11, d2 :: Qd 0x4742b4e6 0x4742b4e6  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vadd.f32 d9, d5, d7 :: Qd 0x49d5e6b8 0x49d5e6b8  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vadd.f32 d0, d11, d12 :: Qd 0x48b0b752 0x48b0b752  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vadd.f32 d7, d1, d6 :: Qd 0x420802fd 0x420802fd  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vadd.f32 d0, d1, d2 :: Qd 0x4532d000 0x4532d000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vadd.f32 d3, d4, d5 :: Qd 0x450d299a 0x450d299a  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vadd.f32 d10, d11, d2 :: Qd 0x44152592 0x44152592  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vadd.f32 d9, d5, d7 :: Qd 0x4573a000 0x4573a000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vadd.f32 d0, d11, d12 :: Qd 0xc5b695c3 0xc5b695c3  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vadd.f32 d7, d1, d6 :: Qd 0x43e07a2a 0x43e07a2a  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vadd.f32 d0, d5, d2 :: Qd 0x44053ee0 0x44053ee0  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vadd.f32 d10, d13, d15 :: Qd 0xc4838fb4 0xc4838fb4  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vadd.f32 d10, d13, d15 :: Qd 0x488c3d8e 0x488c3d8e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vadd.f32 d0, d1, d2 :: Qd 0x4efa8dc5 0x4efa8dc5  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vadd.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vadd.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VSUB (fp) ----
+vsub.f32 d0, d5, d2 :: Qd 0x428937a8 0x428937a8  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vsub.f32 d3, d4, d5 :: Qd 0xc8aa824f 0xc8aa824f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vsub.f32 d10, d11, d2 :: Qd 0x47b8a6bd 0x47b8a6bd  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vsub.f32 d9, d5, d7 :: Qd 0x4799e961 0x4799e961  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vsub.f32 d0, d5, d2 :: Qd 0x484623e2 0x484623e2  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vsub.f32 d3, d4, d5 :: Qd 0xc4a54000 0xc4a54000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vsub.f32 d10, d11, d2 :: Qd 0x473a3200 0x473a3200  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vsub.f32 d9, d5, d7 :: Qd 0xc9d5d958 0xc9d5d958  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vsub.f32 d0, d11, d12 :: Qd 0x48aafc92 0x48aafc92  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vsub.f32 d7, d1, d6 :: Qd 0x4207fdf5 0x4207fdf5  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vsub.f32 d0, d1, d2 :: Qd 0x45257000 0x45257000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vsub.f32 d3, d4, d5 :: Qd 0xc3ff4ccc 0xc3ff4ccc  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vsub.f32 d10, d11, d2 :: Qd 0x43bd4b23 0x43bd4b23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vsub.f32 d9, d5, d7 :: Qd 0x43c50000 0x43c50000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vsub.f32 d0, d11, d12 :: Qd 0x45b311c3 0x45b311c3  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vsub.f32 d7, d1, d6 :: Qd 0x43e7c592 0x43e7c592  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vsub.f32 d0, d5, d2 :: Qd 0x44053f76 0x44053f76  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vsub.f32 d10, d13, d15 :: Qd 0x42a3ffa4 0x42a3ffa4  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vsub.f32 d10, d13, d15 :: Qd 0x4883b08e 0x4883b08e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vsub.f32 d0, d1, d2 :: Qd 0xcda5da84 0xcda5da84  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vsub.f32 d0, d1, d2 :: Qd 0xbf800000 0xbf800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vsub.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vsub.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vsub.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vsub.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMUL (fp) ----
+vmul.f32 d0, d5, d2 :: Qd 0xc4833ce4 0xc4833ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmul.f32 d3, d4, d5 :: Qd 0xcddf4321 0xcddf4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmul.f32 d10, d11, d2 :: Qd 0xcf050e7f 0xcf050e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmul.f32 d9, d5, d7 :: Qd 0x4ec3063f 0x4ec3063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmul.f32 d0, d5, d2 :: Qd 0x5029254c 0x5029254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmul.f32 d3, d4, d5 :: Qd 0x46fc6000 0x46fc6000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vmul.f32 d10, d11, d2 :: Qd 0x4c4a89cd 0x4c4a89cd  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vmul.f32 d9, d5, d7 :: Qd 0x4db2c947 0x4db2c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmul.f32 d0, d11, d12 :: Qd 0x4ef90536 0x4ef90536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmul.f32 d7, d1, d6 :: Qd 0x3dab1f7a 0x3dab1f7a  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmul.f32 d0, d1, d2 :: Qd 0x488fe2c0 0x488fe2c0  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmul.f32 d3, d4, d5 :: Qd 0x4993b8e3 0x4993b8e3  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmul.f32 d10, d11, d2 :: Qd 0x474f9afc 0x474f9afc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmul.f32 d9, d5, d7 :: Qd 0x4a657ac0 0x4a657ac0  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmul.f32 d0, d11, d12 :: Qd 0x489eee1e 0x489eee1e  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmul.f32 d7, d1, d6 :: Qd 0xc5500239 0xc5500239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmul.f32 d0, d5, d2 :: Qd 0xc01c7d07 0xc01c7d07  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmul.f32 d10, d13, d15 :: Qd 0x488666a6 0x488666a6  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmul.f32 d10, d13, d15 :: Qd 0x4f115379 0x4f115379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmul.f32 d0, d1, d2 :: Qd 0x5d6e81fd 0x5d6e81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmul.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmul.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmul.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmul.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmul.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMLA (fp) ----
+vmla.f32 d0, d5, d2 :: Qd 0xc4831ce4 0xc4831ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmla.f32 d3, d4, d5 :: Qd 0xcddf4321 0xcddf4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmla.f32 d10, d11, d2 :: Qd 0xcf050e7f 0xcf050e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmla.f32 d9, d5, d7 :: Qd 0x4ec3063f 0x4ec3063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmla.f32 d0, d5, d2 :: Qd 0x5029254c 0x5029254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmla.f32 d3, d4, d5 :: Qd 0x46fc6200 0x46fc6200  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vmla.f32 d10, d11, d2 :: Qd 0x4c4a89cd 0x4c4a89cd  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vmla.f32 d9, d5, d7 :: Qd 0x4db2c947 0x4db2c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmla.f32 d0, d11, d12 :: Qd 0x4ef90536 0x4ef90536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmla.f32 d7, d1, d6 :: Qd 0x3f8ab1f8 0x3f8ab1f8  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmla.f32 d0, d1, d2 :: Qd 0x488fe2e0 0x488fe2e0  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmla.f32 d3, d4, d5 :: Qd 0x4993b8eb 0x4993b8eb  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmla.f32 d10, d11, d2 :: Qd 0x474f9bfc 0x474f9bfc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmla.f32 d9, d5, d7 :: Qd 0x4a657ac4 0x4a657ac4  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmla.f32 d0, d11, d12 :: Qd 0x489eee3e 0x489eee3e  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmla.f32 d7, d1, d6 :: Qd 0xc54ff239 0xc54ff239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmla.f32 d0, d5, d2 :: Qd 0xbfb8fa0e 0xbfb8fa0e  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmla.f32 d10, d13, d15 :: Qd 0x488666c6 0x488666c6  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmla.f32 d10, d13, d15 :: Qd 0x4f115379 0x4f115379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmla.f32 d0, d1, d2 :: Qd 0x5d6e81fd 0x5d6e81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmla.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmla.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmla.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmla.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMLA (fp by scalar) ----
+vmla.f32 d0, d1, d4[0] :: Qd 0x45341000 0x45341000  Qm (i32)0x41c00000  Qn (i32)0x42f00000
+vmla.f32 d31, d8, d7[1] :: Qd 0xc6833e00 0xc6833e00  Qm (i32)0x430c0000  Qn (i32)0xc2f00000
+vmla.f32 d4, d8, d15[1] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.f32 d7, d8, d1[1] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmla.f32 d17, d8, d1[1] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmla.f32 d7, d8, d1[0] :: Qd 0x447a3fff 0x447a3fff  Qm (i32)0x64078678  Qn (i32)0x1fec1e4a
+vmla.f32 d7, d24, d1[0] :: Qd 0x65a96816 0x65a96816  Qm (i32)0x5368d4a5  Qn (i32)0x51ba43b7
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmla.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmla.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMLS (fp) ----
+vmls.f32 d0, d5, d2 :: Qd 0x44835ce4 0x44835ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmls.f32 d3, d4, d5 :: Qd 0x4ddf4321 0x4ddf4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmls.f32 d10, d11, d2 :: Qd 0x4f050e7f 0x4f050e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmls.f32 d9, d5, d7 :: Qd 0xcec3063f 0xcec3063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmls.f32 d0, d5, d2 :: Qd 0xd029254c 0xd029254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmls.f32 d3, d4, d5 :: Qd 0xc6fc5e00 0xc6fc5e00  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vmls.f32 d10, d11, d2 :: Qd 0xcc4a89cd 0xcc4a89cd  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vmls.f32 d9, d5, d7 :: Qd 0xcdb2c947 0xcdb2c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmls.f32 d0, d11, d12 :: Qd 0xcef90536 0xcef90536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmls.f32 d7, d1, d6 :: Qd 0x3f6a9c11 0x3f6a9c11  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmls.f32 d0, d1, d2 :: Qd 0xc88fe2a0 0xc88fe2a0  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmls.f32 d3, d4, d5 :: Qd 0xc993b8db 0xc993b8db  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmls.f32 d10, d11, d2 :: Qd 0xc74f99fc 0xc74f99fc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmls.f32 d9, d5, d7 :: Qd 0xca657abc 0xca657abc  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmls.f32 d0, d11, d12 :: Qd 0xc89eedfe 0xc89eedfe  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmls.f32 d7, d1, d6 :: Qd 0x45501239 0x45501239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmls.f32 d0, d5, d2 :: Qd 0x405c7d07 0x405c7d07  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmls.f32 d10, d13, d15 :: Qd 0xc8866686 0xc8866686  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmls.f32 d10, d13, d15 :: Qd 0xcf115379 0xcf115379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmls.f32 d0, d1, d2 :: Qd 0xdd6e81fd 0xdd6e81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmls.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmls.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmls.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmls.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMLS (fp by scalar) ----
+vmls.f32 d0, d1, d4[0] :: Qd 0xc533f000 0xc533f000  Qm (i32)0x41c00000  Qn (i32)0x42f00000
+vmls.f32 d31, d8, d7[1] :: Qd 0x46834200 0x46834200  Qm (i32)0x430c0000  Qn (i32)0xc2f00000
+vmls.f32 d4, d8, d15[1] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.f32 d7, d8, d1[1] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x80000000  Qn (i16)0x0000000c
+vmls.f32 d17, d8, d1[1] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x80000001  Qn (i32)0x80000002
+vmls.f32 d7, d8, d1[0] :: Qd 0xc479bfff 0xc479bfff  Qm (i32)0x64078678  Qn (i32)0x1fec1e4a
+vmls.f32 d7, d24, d1[0] :: Qd 0xe5a96816 0xe5a96816  Qm (i32)0x5368d4a5  Qn (i32)0x51ba43b7
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmls.f32 d0, d1, d2[0] :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmls.f32 d0, d1, d2[0] :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VABD (fp) ----
+vabd.f32 d0, d5, d2 :: Qd 0x428937a8 0x428937a8  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vabd.f32 d3, d4, d5 :: Qd 0x48aa824f 0x48aa824f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vabd.f32 d10, d11, d2 :: Qd 0x47b8a6bd 0x47b8a6bd  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vabd.f32 d9, d5, d7 :: Qd 0x4799e961 0x4799e961  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vabd.f32 d0, d5, d2 :: Qd 0x484623e2 0x484623e2  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vabd.f32 d3, d4, d5 :: Qd 0x44a54000 0x44a54000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vabd.f32 d10, d11, d2 :: Qd 0x473a3200 0x473a3200  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vabd.f32 d9, d5, d7 :: Qd 0x49d5d958 0x49d5d958  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vabd.f32 d0, d11, d12 :: Qd 0x48aafc92 0x48aafc92  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vabd.f32 d7, d1, d6 :: Qd 0x4207fdf5 0x4207fdf5  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vabd.f32 d0, d1, d2 :: Qd 0x45257000 0x45257000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vabd.f32 d3, d4, d5 :: Qd 0x43ff4ccc 0x43ff4ccc  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vabd.f32 d10, d11, d2 :: Qd 0x43bd4b23 0x43bd4b23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vabd.f32 d9, d5, d7 :: Qd 0x43c50000 0x43c50000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vabd.f32 d0, d11, d12 :: Qd 0x45b311c3 0x45b311c3  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vabd.f32 d7, d1, d6 :: Qd 0x43e7c592 0x43e7c592  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vabd.f32 d0, d5, d2 :: Qd 0x44053f76 0x44053f76  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vabd.f32 d10, d13, d15 :: Qd 0x42a3ffa4 0x42a3ffa4  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vabd.f32 d10, d13, d15 :: Qd 0x4883b08e 0x4883b08e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vabd.f32 d0, d1, d2 :: Qd 0x4da5da84 0x4da5da84  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+---- VPADD (fp) ----
+vpadd.f32 d0, d5, d2 :: Qd 0xc2b64659 0x423851ec  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vpadd.f32 d3, d4, d5 :: Qd 0x45284000 0xc929da0f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vpadd.f32 d10, d11, d2 :: Qd 0xc7b2da7a 0x47be7300  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vpadd.f32 d9, d5, d7 :: Qd 0x47055200 0x483b3de1  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vpadd.f32 d0, d5, d2 :: Qd 0xc8f2bcb1 0xc7b2633d  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vpadd.f32 d3, d4, d5 :: Qd 0x45284000 0x42400000  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vpadd.f32 d10, d11, d2 :: Qd 0x45082000 0x47be7300  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vpadd.f32 d9, d5, d7 :: Qd 0x4a55e008 0x43d60000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vpadd.f32 d0, d11, d12 :: Qd 0x46375812 0x492dd9f2  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vpadd.f32 d7, d1, d6 :: Qd 0x3ba10e02 0x42880079  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vpadd.f32 d0, d1, d2 :: Qd 0x43560000 0x45ac2000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vpadd.f32 d3, d4, d5 :: Qd 0x452d1333 0x44da8000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vpadd.f32 d10, d11, d2 :: Qd 0x435a0000 0x4473cb23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vpadd.f32 d9, d5, d7 :: Qd 0x455b0000 0x45862000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vpadd.f32 d0, d11, d12 :: Qd 0xc634d3c3 0xc2e10000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vpadd.f32 d7, d1, d6 :: Qd 0xc1696d19 0x44641fde  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vpadd.f32 d0, d5, d2 :: Qd 0xbc165394 0x44853f2b  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vpadd.f32 d10, d13, d15 :: Qd 0xc48dcfae 0xc4729f73  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vpadd.f32 d10, d13, d15 :: Qd 0x4688d008 0x4907f70e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vpadd.f32 d0, d1, d2 :: Qd 0x4f120233 0x4ed11724  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vpadd.f32 d0, d1, d2 :: Qd 0x7fc00000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vpadd.f32 d0, d1, d2 :: Qd 0x40000000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vpadd.f32 d0, d1, d2 :: Qd 0x00000000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vpadd.f32 d0, d1, d2 :: Qd 0x7f800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vpadd.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VCVT (integer <-> fp) ----
+vcvt.u32.f32 d0, d1 :: Qd 0x00000003 0x00000003  Qm (i32)0x404ccccd
+vcvt.u32.f32 d10, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x64cb49b4
+vcvt.u32.f32 d15, d4 :: Qd 0xb2d05e00 0xb2d05e00  Qm (i32)0x4f32d05e
+vcvt.u32.f32 d15, d4 :: Qd 0x00000000 0x00000000  Qm (i32)0xbf000000
+vcvt.u32.f32 d15, d4 :: Qd 0x00000000 0x00000000  Qm (i32)0xc0e33333
+vcvt.u32.f32 d12, d8 :: Qd 0x00000007 0x00000007  Qm (i32)0x40fff800
+vcvt.u32.f32 d12, d8 :: Qd 0x00000000 0x00000000  Qm (i32)0xc0fff800
+vcvt.s32.f32 d0, d1 :: Qd 0x00000003 0x00000003  Qm (i32)0x404ccccd
+vcvt.s32.f32 d20, d21 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x64cb49b4
+vcvt.s32.f32 d15, d4 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x4f32d05e
+vcvt.s32.f32 d15, d4 :: Qd 0x00000000 0x00000000  Qm (i32)0xbf000000
+vcvt.s32.f32 d15, d4 :: Qd 0xfffffff9 0xfffffff9  Qm (i32)0xc0e33333
+vcvt.s32.f32 d12, d8 :: Qd 0x00000007 0x00000007  Qm (i32)0x40fff800
+vcvt.s32.f32 d12, d8 :: Qd 0xfffffff9 0xfffffff9  Qm (i32)0xc0fff800
+vcvt.f32.u32 d0, d1 :: Qd 0x40e00000 0x40e00000  Qm (i32)0x00000007
+vcvt.f32.u32 d10, d11 :: Qd 0x4f000000 0x4f000000  Qm (i32)0x80000000
+vcvt.f32.u32 d0, d1 :: Qd 0x4f000000 0x4f000000  Qm (i32)0x80000001
+vcvt.f32.u32 d24, d26 :: Qd 0x4f000000 0x4f000000  Qm (i32)0x7fffffff
+vcvt.f32.u32 d0, d14 :: Qd 0x4e4282f4 0x4e4282f4  Qm (i32)0x30a0bcef
+vcvt.f32.s32 d0, d1 :: Qd 0x40e00000 0x40e00000  Qm (i32)0x00000007
+vcvt.f32.s32 d30, d31 :: Qd 0xcf000000 0xcf000000  Qm (i32)0x80000000
+vcvt.f32.s32 d0, d1 :: Qd 0xcf000000 0xcf000000  Qm (i32)0x80000001
+vcvt.f32.s32 d0, d1 :: Qd 0x4f000000 0x4f000000  Qm (i32)0x7fffffff
+vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcvt.u32.f32 d0, d1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000
+vcvt.u32.f32 d0, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000
+vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcvt.s32.f32 d0, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcvt.s32.f32 d0, d1 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x7f800000
+vcvt.s32.f32 d0, d1 :: Qd 0x80000000 0x80000000  Qm (i32)0xff800000
+---- VCVT (fixed <-> fp) ----
+vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000019 0x00000019  Qm (i32)0x404ccccd
+vcvt.u32.f32 d10, d11, #1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x64cb49b4
+vcvt.u32.f32 d15, d4, #32 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x4f32d05e
+vcvt.u32.f32 d15, d4, #7 :: Qd 0x00000000 0x00000000  Qm (i32)0xbf000000
+vcvt.u32.f32 d15, d4, #4 :: Qd 0x00000000 0x00000000  Qm (i32)0xc0e33333
+vcvt.u32.f32 d12, d8, #3 :: Qd 0x0000003f 0x0000003f  Qm (i32)0x40fff800
+vcvt.u32.f32 d12, d8, #3 :: Qd 0x00000000 0x00000000  Qm (i32)0xc0fff800
+vcvt.s32.f32 d0, d1, #5 :: Qd 0x00000066 0x00000066  Qm (i32)0x404ccccd
+vcvt.s32.f32 d20, d21, #1 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x64cb49b4
+vcvt.s32.f32 d15, d4, #8 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x4f32d05e
+vcvt.s32.f32 d15, d4, #2 :: Qd 0xfffffffe 0xfffffffe  Qm (i32)0xbf000000
+vcvt.s32.f32 d15, d4, #1 :: Qd 0xfffffff2 0xfffffff2  Qm (i32)0xc0e33333
+vcvt.s32.f32 d12, d8, #2 :: Qd 0x0000001f 0x0000001f  Qm (i32)0x40fff800
+vcvt.s32.f32 d12, d8, #2 :: Qd 0xffffffe1 0xffffffe1  Qm (i32)0xc0fff800
+vcvt.f32.u32 d0, d1, #5 :: Qd 0x3e600000 0x3e600000  Qm (i32)0x00000007
+vcvt.f32.u32 d10, d11, #9 :: Qd 0x4a800000 0x4a800000  Qm (i32)0x80000000
+vcvt.f32.u32 d0, d1, #4 :: Qd 0x4d000000 0x4d000000  Qm (i32)0x80000001
+vcvt.f32.u32 d24, d26, #6 :: Qd 0x4c000000 0x4c000000  Qm (i32)0x7fffffff
+vcvt.f32.u32 d0, d14, #5 :: Qd 0x4bc282f4 0x4bc282f4  Qm (i32)0x30a0bcef
+vcvt.f32.s32 d0, d1, #12 :: Qd 0x3ae00000 0x3ae00000  Qm (i32)0x00000007
+vcvt.f32.s32 d30, d31, #8 :: Qd 0xcb000000 0xcb000000  Qm (i32)0x80000000
+vcvt.f32.s32 d0, d1, #1 :: Qd 0xce800000 0xce800000  Qm (i32)0x80000001
+vcvt.f32.s32 d0, d1, #6 :: Qd 0x4c000000 0x4c000000  Qm (i32)0x7fffffff
+vcvt.f32.s32 d0, d14, #2 :: Qd 0x4d4282f4 0x4d4282f4  Qm (i32)0x30a0bcef
+vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcvt.u32.f32 d0, d1, #3 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000
+vcvt.u32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000
+vcvt.s32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcvt.s32.f32 d0, d1, #3 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcvt.s32.f32 d0, d1, #3 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x7f800000
+vcvt.s32.f32 d0, d1, #3 :: Qd 0x80000000 0x80000000  Qm (i32)0xff800000
+---- VMAX (fp) ----
+vmax.f32 d0, d5, d2 :: Qd 0x41b851ec 0x41b851ec  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmax.f32 d3, d4, d5 :: Qd 0x44a84000 0x44a84000  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmax.f32 d10, d11, d2 :: Qd 0x473e7300 0x473e7300  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmax.f32 d9, d5, d7 :: Qd 0x47bb3de1 0x47bb3de1  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmax.f32 d0, d5, d2 :: Qd 0xc732633d 0xc732633d  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmax.f32 d3, d4, d5 :: Qd 0x44a84003 0x44a84003  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vmax.f32 d10, d11, d2 :: Qd 0x473e73b3 0x473e73b3  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vmax.f32 d9, d5, d7 :: Qd 0x49d5e008 0x49d5e008  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmax.f32 d0, d11, d12 :: Qd 0x48add9f2 0x48add9f2  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmax.f32 d7, d1, d6 :: Qd 0x42080079 0x42080079  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmax.f32 d0, d1, d2 :: Qd 0x452c2000 0x452c2000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmax.f32 d3, d4, d5 :: Qd 0x44ad1333 0x44ad1333  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmax.f32 d10, d11, d2 :: Qd 0x43f3cb23 0x43f3cb23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmax.f32 d9, d5, d7 :: Qd 0x45062000 0x45062000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmax.f32 d0, d11, d12 :: Qd 0xc2610000 0xc2610000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmax.f32 d7, d1, d6 :: Qd 0x43e41fde 0x43e41fde  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmax.f32 d0, d5, d2 :: Qd 0x44053f2b 0x44053f2b  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmax.f32 d10, d13, d15 :: Qd 0xc3f29f73 0xc3f29f73  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmax.f32 d10, d13, d15 :: Qd 0x4887f70e 0x4887f70e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmax.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e920233  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmax.f32 d0, d1, d2 :: Qd 0x3a800000 0x3a800000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vmax.f32 d0, d1, d2 :: Qd 0x3a800000 0x3a800000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vmax.f32 d0, d1, d2 :: Qd 0x45126004 0x45126004  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vmax.f32 d0, d1, d2 :: Qd 0xc5125ffc 0xc5125ffc  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vmax.f32 d0, d1, d2 :: Qd 0x47bff200 0x47bff200  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmax.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VMIN (fp) ----
+vmin.f32 d0, d5, d2 :: Qd 0xc2364659 0xc2364659  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vmin.f32 d3, d4, d5 :: Qd 0xc8a9da0f 0xc8a9da0f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vmin.f32 d10, d11, d2 :: Qd 0xc732da7a 0xc732da7a  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vmin.f32 d9, d5, d7 :: Qd 0x46855200 0x46855200  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vmin.f32 d0, d5, d2 :: Qd 0xc872bcb1 0xc872bcb1  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vmin.f32 d3, d4, d5 :: Qd 0x41c70126 0x41c70126  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vmin.f32 d10, d11, d2 :: Qd 0x44882666 0x44882666  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vmin.f32 d9, d5, d7 :: Qd 0x43560000 0x43560000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vmin.f32 d0, d11, d12 :: Qd 0x45b75812 0x45b75812  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vmin.f32 d7, d1, d6 :: Qd 0x3b210e02 0x3b210e02  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vmin.f32 d0, d1, d2 :: Qd 0x42d60000 0x42d60000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vmin.f32 d3, d4, d5 :: Qd 0x445a8000 0x445a8000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vmin.f32 d10, d11, d2 :: Qd 0x42da0000 0x42da0000  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vmin.f32 d9, d5, d7 :: Qd 0x44db0000 0x44db0000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vmin.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0xc5b4d3c3  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vmin.f32 d7, d1, d6 :: Qd 0xc0e96d19 0xc0e96d19  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vmin.f32 d0, d5, d2 :: Qd 0xbb965394 0xbb965394  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vmin.f32 d10, d13, d15 :: Qd 0xc40dcfae 0xc40dcfae  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vmin.f32 d10, d13, d15 :: Qd 0x4608d008 0x4608d008  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vmin.f32 d0, d1, d2 :: Qd 0x4e511724 0x4e511724  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmin.f32 d0, d1, d2 :: Qd 0xba800000 0xba800000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vmin.f32 d0, d1, d2 :: Qd 0xba800000 0xba800000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vmin.f32 d0, d1, d2 :: Qd 0x45125ffc 0x45125ffc  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vmin.f32 d0, d1, d2 :: Qd 0xc5126004 0xc5126004  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vmin.f32 d0, d1, d2 :: Qd 0x47ae5e00 0x47ae5e00  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x3f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VPMAX (fp) ----
+vpmax.f32 d0, d5, d2 :: Qd 0xc2364659 0x41b851ec  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vpmax.f32 d3, d4, d5 :: Qd 0x44a84000 0xc8a9da0f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vpmax.f32 d10, d11, d2 :: Qd 0xc732da7a 0x473e7300  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vpmax.f32 d9, d5, d7 :: Qd 0x46855200 0x47bb3de1  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vpmax.f32 d0, d5, d2 :: Qd 0xc872bcb1 0xc732633d  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vpmax.f32 d3, d4, d5 :: Qd 0x44a84003 0x41c70126  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vpmax.f32 d10, d11, d2 :: Qd 0x44882666 0x473e73b3  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vpmax.f32 d9, d5, d7 :: Qd 0x49d5e008 0x43560000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vpmax.f32 d0, d11, d12 :: Qd 0x45b75812 0x48add9f2  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vpmax.f32 d7, d1, d6 :: Qd 0x3b210e02 0x42080079  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vpmax.f32 d0, d1, d2 :: Qd 0x42d60000 0x452c2000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vpmax.f32 d3, d4, d5 :: Qd 0x44ad1333 0x445a8000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vpmax.f32 d10, d11, d2 :: Qd 0x42da0000 0x43f3cb23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vpmax.f32 d9, d5, d7 :: Qd 0x44db0000 0x45062000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vpmax.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0xc2610000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vpmax.f32 d7, d1, d6 :: Qd 0xc0e96d19 0x43e41fde  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vpmax.f32 d0, d5, d2 :: Qd 0xbb965394 0x44053f2b  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vpmax.f32 d10, d13, d15 :: Qd 0xc40dcfae 0xc3f29f73  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vpmax.f32 d10, d13, d15 :: Qd 0x4608d008 0x4887f70e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vpmax.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e511724  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vpmax.f32 d0, d1, d2 :: Qd 0xba800000 0x3a800000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vpmax.f32 d0, d1, d2 :: Qd 0x3a800000 0xba800000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vpmax.f32 d0, d1, d2 :: Qd 0x45125ffc 0x45126004  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vpmax.f32 d0, d1, d2 :: Qd 0xc5126004 0xc5125ffc  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vpmax.f32 d0, d1, d2 :: Qd 0x47bff200 0x47ae5e00  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vpmax.f32 d0, d1, d2 :: Qd 0x7fc00000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vpmax.f32 d0, d1, d2 :: Qd 0x3f800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vpmax.f32 d0, d1, d2 :: Qd 0x00000000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vpmax.f32 d0, d1, d2 :: Qd 0x7f800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vpmax.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VPMIN (fp) ----
+vpmin.f32 d0, d5, d2 :: Qd 0xc2364659 0x41b851ec  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vpmin.f32 d3, d4, d5 :: Qd 0x44a84000 0xc8a9da0f  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vpmin.f32 d10, d11, d2 :: Qd 0xc732da7a 0x473e7300  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vpmin.f32 d9, d5, d7 :: Qd 0x46855200 0x47bb3de1  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vpmin.f32 d0, d5, d2 :: Qd 0xc872bcb1 0xc732633d  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vpmin.f32 d3, d4, d5 :: Qd 0x44a84003 0x41c70126  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vpmin.f32 d10, d11, d2 :: Qd 0x44882666 0x473e73b3  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vpmin.f32 d9, d5, d7 :: Qd 0x49d5e008 0x43560000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vpmin.f32 d0, d11, d12 :: Qd 0x45b75812 0x48add9f2  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vpmin.f32 d7, d1, d6 :: Qd 0x3b210e02 0x42080079  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vpmin.f32 d0, d1, d2 :: Qd 0x42d60000 0x452c2000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vpmin.f32 d3, d4, d5 :: Qd 0x44ad1333 0x445a8000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vpmin.f32 d10, d11, d2 :: Qd 0x42da0000 0x43f3cb23  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vpmin.f32 d9, d5, d7 :: Qd 0x44db0000 0x45062000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vpmin.f32 d0, d11, d12 :: Qd 0xc5b4d3c3 0xc2610000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vpmin.f32 d7, d1, d6 :: Qd 0xc0e96d19 0x43e41fde  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vpmin.f32 d0, d5, d2 :: Qd 0xbb965394 0x44053f2b  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vpmin.f32 d10, d13, d15 :: Qd 0xc40dcfae 0xc3f29f73  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vpmin.f32 d10, d13, d15 :: Qd 0x4608d008 0x4887f70e  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vpmin.f32 d0, d1, d2 :: Qd 0x4e920233 0x4e511724  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vpmin.f32 d0, d1, d2 :: Qd 0xba800000 0x3a800000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vpmin.f32 d0, d1, d2 :: Qd 0x3a800000 0xba800000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vpmin.f32 d0, d1, d2 :: Qd 0x45125ffc 0x45126004  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vpmin.f32 d0, d1, d2 :: Qd 0xc5126004 0xc5125ffc  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vpmin.f32 d0, d1, d2 :: Qd 0x47bff200 0x47ae5e00  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vpmin.f32 d0, d1, d2 :: Qd 0x7fc00000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vpmin.f32 d0, d1, d2 :: Qd 0x3f800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vpmin.f32 d0, d1, d2 :: Qd 0x00000000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vpmin.f32 d0, d1, d2 :: Qd 0x7f800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vpmin.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VRECPE ----
+vrecpe.u32 d0, d1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x404ccccd
+vrecpe.u32 d0, d1 :: Qd 0xa7000000 0xa7000000  Qm (i32)0xc4234ccd
+vrecpe.u32 d10, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x64cb49b4
+vrecpe.u32 d15, d4 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x4f32d05e
+vrecpe.u32 d15, d4 :: Qd 0xab800000 0xab800000  Qm (i32)0xbf000000
+vrecpe.u32 d15, d4 :: Qd 0xaa000000 0xaa000000  Qm (i32)0xc0e33333
+vrecpe.u32 d12, d8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x40fff800
+vrecpe.u32 d12, d8 :: Qd 0xaa000000 0xaa000000  Qm (i32)0xc0fff800
+vrecpe.u32 d0, d1 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x404ccccd
+vrecpe.u32 d10, d11 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x64cb49b4
+vrecpe.u32 d15, d4 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x4f32d05e
+vrecpe.f32 d15, d4 :: Qd 0xbfff8000 0xbfff8000  Qm (i32)0xbf000000
+vrecpe.f32 d15, d4 :: Qd 0xbe100000 0xbe100000  Qm (i32)0xc0e33333
+vrecpe.f32 d12, d8 :: Qd 0x3e000000 0x3e000000  Qm (i32)0x40fff800
+vrecpe.f32 d12, d8 :: Qd 0xbe000000 0xbe000000  Qm (i32)0xc0fff800
+vrecpe.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000007
+vrecpe.f32 d10, d11 :: Qd 0xff800000 0xff800000  Qm (i32)0x80000000
+vrecpe.f32 d0, d1 :: Qd 0xff800000 0xff800000  Qm (i32)0x80000001
+vrecpe.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fffffff
+vrecpe.f32 d0, d14 :: Qd 0x4e4c0000 0x4e4c0000  Qm (i32)0x30a0bcef
+vrecpe.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000007
+vrecpe.f32 d10, d11 :: Qd 0xff800000 0xff800000  Qm (i32)0x80000000
+vrecpe.f32 d0, d1 :: Qd 0xff800000 0xff800000  Qm (i32)0x80000001
+vrecpe.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fffffff
+vrecpe.f32 d0, d14 :: Qd 0x4e4c0000 0x4e4c0000  Qm (i32)0x30a0bcef
+vrecpe.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000
+vrecpe.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000000
+vrecpe.f32 d0, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000
+vrecpe.f32 d0, d1 :: Qd 0x80000000 0x80000000  Qm (i32)0xff800000
+---- VRECPS ----
+vrecps.f32 d0, d5, d2 :: Qd 0x44837ce4 0x44837ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vrecps.f32 d3, d4, d5 :: Qd 0x4ddf4321 0x4ddf4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vrecps.f32 d10, d11, d2 :: Qd 0x4f050e7f 0x4f050e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vrecps.f32 d9, d5, d7 :: Qd 0xcec3063f 0xcec3063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vrecps.f32 d0, d5, d2 :: Qd 0xd029254c 0xd029254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vrecps.f32 d3, d4, d5 :: Qd 0xc6fc5c00 0xc6fc5c00  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vrecps.f32 d10, d11, d2 :: Qd 0xcc4a89cc 0xcc4a89cc  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vrecps.f32 d9, d5, d7 :: Qd 0xcdb2c947 0xcdb2c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vrecps.f32 d0, d11, d12 :: Qd 0xcef90536 0xcef90536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vrecps.f32 d7, d1, d6 :: Qd 0x3ff54e08 0x3ff54e08  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vrecps.f32 d0, d1, d2 :: Qd 0xc88fe280 0xc88fe280  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vrecps.f32 d3, d4, d5 :: Qd 0xc993b8d3 0xc993b8d3  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vrecps.f32 d10, d11, d2 :: Qd 0xc74f98fc 0xc74f98fc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vrecps.f32 d9, d5, d7 :: Qd 0xca657ab8 0xca657ab8  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vrecps.f32 d0, d11, d12 :: Qd 0xc89eedde 0xc89eedde  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vrecps.f32 d7, d1, d6 :: Qd 0x45502239 0x45502239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vrecps.f32 d0, d5, d2 :: Qd 0x408e3e84 0x408e3e84  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vrecps.f32 d10, d13, d15 :: Qd 0xc8866666 0xc8866666  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vrecps.f32 d10, d13, d15 :: Qd 0xcf115379 0xcf115379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vrecps.f32 d0, d1, d2 :: Qd 0xdd6e81fd 0xdd6e81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vrecps.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vrecps.f32 d0, d1, d2 :: Qd 0x40000000 0x40000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vrecps.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vrecps.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VABS (fp) ----
+vabs.f32 d0, d1 :: Qd 0x404ccccd 0x404ccccd  Qm (i32)0x404ccccd
+vabs.f32 d10, d11 :: Qd 0x64cb49b4 0x64cb49b4  Qm (i32)0x64cb49b4
+vabs.f32 d15, d4 :: Qd 0x4f32d05e 0x4f32d05e  Qm (i32)0x4f32d05e
+vabs.f32 d15, d4 :: Qd 0x3f000000 0x3f000000  Qm (i32)0xbf000000
+vabs.f32 d15, d4 :: Qd 0x40e33333 0x40e33333  Qm (i32)0xc0e33333
+vabs.f32 d12, d8 :: Qd 0x40fff800 0x40fff800  Qm (i32)0x40fff800
+vabs.f32 d12, d8 :: Qd 0x40fff800 0x40fff800  Qm (i32)0xc0fff800
+vabs.f32 d0, d1 :: Qd 0x404ccccd 0x404ccccd  Qm (i32)0x404ccccd
+vabs.f32 d10, d11 :: Qd 0x64cb49b4 0x64cb49b4  Qm (i32)0x64cb49b4
+vabs.f32 d15, d4 :: Qd 0x4f32d05e 0x4f32d05e  Qm (i32)0x4f32d05e
+vabs.f32 d15, d4 :: Qd 0x3f000000 0x3f000000  Qm (i32)0xbf000000
+vabs.f32 d15, d4 :: Qd 0x40e33333 0x40e33333  Qm (i32)0xc0e33333
+vabs.f32 d12, d8 :: Qd 0x40fff800 0x40fff800  Qm (i32)0x40fff800
+vabs.f32 d12, d8 :: Qd 0x40fff800 0x40fff800  Qm (i32)0xc0fff800
+vabs.f32 d0, d1 :: Qd 0x00000007 0x00000007  Qm (i32)0x00000007
+vabs.f32 d10, d11 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000000
+vabs.f32 d0, d1 :: Qd 0x00000001 0x00000001  Qm (i32)0x80000001
+vabs.f32 d0, d1 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x7fffffff
+vabs.f32 d0, d14 :: Qd 0x30a0bcef 0x30a0bcef  Qm (i32)0x30a0bcef
+vabs.f32 d0, d1 :: Qd 0x00000007 0x00000007  Qm (i32)0x00000007
+vabs.f32 d10, d11 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000000
+vabs.f32 d0, d1 :: Qd 0x00000001 0x00000001  Qm (i32)0x80000001
+vabs.f32 d0, d1 :: Qd 0x7fffffff 0x7fffffff  Qm (i32)0x7fffffff
+vabs.f32 d0, d14 :: Qd 0x30a0bcef 0x30a0bcef  Qm (i32)0x30a0bcef
+vabs.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000
+vabs.f32 d0, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vabs.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000
+vabs.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000
+---- VCGT (fp) ----
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vcgt.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vcgt.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43677333  Qn (i32)0x43677333
+vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vcgt.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vcgt.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vcgt.f32 d10, d31, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vcgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vcgt.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vcgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vcgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vcgt.f32 d20, d21, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vcgt.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vcgt.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vcgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vcgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vcgt.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vcgt.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0xff800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vcgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vcgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VCGE (fp) ----
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vcge.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vcge.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43677333  Qn (i32)0x43677333
+vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vcge.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vcge.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vcge.f32 d10, d31, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vcge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vcge.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vcge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vcge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vcge.f32 d20, d21, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vcge.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vcge.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vcge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vcge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vcge.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vcge.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0xff800000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vcge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vcge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VACGT (fp) ----
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vacgt.f32 d2, d15, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vacgt.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43677333  Qn (i32)0x43677333
+vacgt.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vacgt.f32 d3, d4, d5 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vacgt.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vacgt.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vacgt.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vacgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vacgt.f32 d10, d31, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vacgt.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vacgt.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vacgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vacgt.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vacgt.f32 d20, d21, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vacgt.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vacgt.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vacgt.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vacgt.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vacgt.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vacgt.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vacgt.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x00000000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vacgt.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VACGE (fp) ----
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vacge.f32 d2, d15, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vacge.f32 d15, d7, d8 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43677333  Qn (i32)0x43677333
+vacge.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vacge.f32 d3, d4, d5 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vacge.f32 d10, d11, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vacge.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vacge.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vacge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vacge.f32 d10, d31, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vacge.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vacge.f32 d0, d11, d12 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vacge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vacge.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vacge.f32 d20, d21, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vacge.f32 d9, d5, d7 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vacge.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vacge.f32 d7, d1, d6 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vacge.f32 d0, d5, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vacge.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vacge.f32 d10, d13, d15 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vacge.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x00000000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vacge.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VCEQ (fp) ----
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x3f000000  Qn (i32)0xbf000000
+vceq.f32 d2, d15, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0xbf07ae14  Qn (i32)0x3f051eb8
+vceq.f32 d15, d7, d8 :: Qd 0x00000000 0x00000000  Qm (i32)0x43677333  Qn (i32)0x43677333
+vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vceq.f32 d10, d11, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x41c70126  Qn (i32)0x44a84003
+vceq.f32 d10, d31, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x473e73b3  Qn (i32)0x44882666
+vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vceq.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vceq.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vceq.f32 d3, d4, d5 :: Qd 0x00000000 0x00000000  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vceq.f32 d20, d21, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vceq.f32 d9, d5, d7 :: Qd 0x00000000 0x00000000  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vceq.f32 d0, d11, d12 :: Qd 0x00000000 0x00000000  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vceq.f32 d7, d1, d6 :: Qd 0x00000000 0x00000000  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vceq.f32 d0, d5, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vceq.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vceq.f32 d10, d13, d15 :: Qd 0x00000000 0x00000000  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vceq.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x3a800000  Qn (i32)0xba800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xba800000  Qn (i32)0x3a800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x45126004  Qn (i32)0x45125ffc
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xc5125ffc  Qn (i32)0xc5126004
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x47ae5e00  Qn (i32)0x47bff200
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vceq.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000  Qn (i32)0x00000000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vceq.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vceq.f32 d0, d1, d2 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vceq.f32 d0, d1, d2 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VCEQ (fp) #0 ----
+vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x01000000
+vceq.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000001
+vceq.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000000
+vceq.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x41b851ec
+vceq.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xc1b851ec
+vceq.f32 d30, d15, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vceq.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000
+vceq.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000
+---- VCGT (fp) #0 ----
+vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x01000000
+vcgt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000001
+vcgt.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000000
+vcgt.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x41b851ec
+vcgt.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xc1b851ec
+vcgt.f32 d30, d15, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcgt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vcgt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x7f800000
+vcgt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xff800000
+---- VCLT (fp) #0 ----
+vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x01000000
+vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000001
+vclt.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000000
+vclt.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x41b851ec
+vclt.f32 d2, d31, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc1b851ec
+vclt.f32 d30, d15, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x00000000
+vclt.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000
+vclt.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000
+---- VCGE (fp) #0 ----
+vcge.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x01000000
+vcge.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000001
+vcge.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000000
+vcge.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x41b851ec
+vcge.f32 d2, d31, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0xc1b851ec
+vcge.f32 d30, d15, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000
+vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000
+---- VCLE (fp) #0 ----
+vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x01000000
+vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000001
+vcle.f32 d2, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x80000000
+vcle.f32 d2, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x41b851ec
+vcle.f32 d2, d31, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xc1b851ec
+vcle.f32 d30, d15, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7fc00000
+vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0x00000000
+vcle.f32 d0, d1, #0 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000
+vcle.f32 d0, d1, #0 :: Qd 0xffffffff 0xffffffff  Qm (i32)0xff800000
+---- VNEG (fp) ----
+vneg.f32 d0, d1 :: Qd 0x81000000 0x81000000  Qm (i32)0x01000000
+vneg.f32 d0, d1 :: Qd 0x80000001 0x80000001  Qm (i32)0x00000001
+vneg.f32 d2, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0x80000000
+vneg.f32 d2, d1 :: Qd 0xc1b851ec 0xc1b851ec  Qm (i32)0x41b851ec
+vneg.f32 d2, d31 :: Qd 0x41b851ec 0x41b851ec  Qm (i32)0xc1b851ec
+vneg.f32 d30, d15 :: Qd 0x80000000 0x80000000  Qm (i32)0x00000000
+vneg.f32 d0, d1 :: Qd 0xffc00000 0xffc00000  Qm (i32)0x7fc00000
+vneg.f32 d0, d1 :: Qd 0x80000000 0x80000000  Qm (i32)0x00000000
+vneg.f32 d0, d1 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000
+vneg.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000
+---- VRSQRTS ----
+vrsqrts.f32 d0, d5, d2 :: Qd 0x44039ce4 0x44039ce4  Qm (i32)0x41b851ec  Qn (i32)0xc2364659
+vrsqrts.f32 d3, d4, d5 :: Qd 0x4d5f4321 0x4d5f4321  Qm (i32)0xc8a9da0f  Qn (i32)0x44a84000
+vrsqrts.f32 d10, d11, d2 :: Qd 0x4e850e7f 0x4e850e7f  Qm (i32)0x473e7300  Qn (i32)0xc732da7a
+vrsqrts.f32 d9, d5, d7 :: Qd 0xce43063f 0xce43063f  Qm (i32)0x47bb3de1  Qn (i32)0x46855200
+vrsqrts.f32 d0, d5, d2 :: Qd 0xcfa9254c 0xcfa9254c  Qm (i32)0xc732633d  Qn (i32)0xc872bcb1
+vrsqrts.f32 d3, d4, d5 :: Qd 0xc67c5a00 0xc67c5a00  Qm (i32)0x41c00000  Qn (i32)0x44a84000
+vrsqrts.f32 d10, d11, d2 :: Qd 0xcbca89cc 0xcbca89cc  Qm (i32)0x473e7300  Qn (i32)0x44882000
+vrsqrts.f32 d9, d5, d7 :: Qd 0xcd32c947 0xcd32c947  Qm (i32)0x43560000  Qn (i32)0x49d5e008
+vrsqrts.f32 d0, d11, d12 :: Qd 0xce790536 0xce790536  Qm (i32)0x48add9f2  Qn (i32)0x45b75812
+vrsqrts.f32 d7, d1, d6 :: Qd 0x3fbaa704 0x3fbaa704  Qm (i32)0x42080079  Qn (i32)0x3b210e02
+vrsqrts.f32 d0, d1, d2 :: Qd 0xc80fe260 0xc80fe260  Qm (i32)0x452c2000  Qn (i32)0x42d60000
+vrsqrts.f32 d3, d4, d5 :: Qd 0xc913b8cb 0xc913b8cb  Qm (i32)0x445a8000  Qn (i32)0x44ad1333
+vrsqrts.f32 d10, d11, d2 :: Qd 0xc6cf97fc 0xc6cf97fc  Qm (i32)0x43f3cb23  Qn (i32)0x42da0000
+vrsqrts.f32 d9, d5, d7 :: Qd 0xc9e57ab4 0xc9e57ab4  Qm (i32)0x45062000  Qn (i32)0x44db0000
+vrsqrts.f32 d0, d11, d12 :: Qd 0xc81eedbe 0xc81eedbe  Qm (i32)0xc2610000  Qn (i32)0xc5b4d3c3
+vrsqrts.f32 d7, d1, d6 :: Qd 0x44d03239 0x44d03239  Qm (i32)0x43e41fde  Qn (i32)0xc0e96d19
+vrsqrts.f32 d0, d5, d2 :: Qd 0x402e3e84 0x402e3e84  Qm (i32)0x44053f2b  Qn (i32)0xbb965394
+vrsqrts.f32 d10, d13, d15 :: Qd 0xc8066646 0xc8066646  Qm (i32)0xc3f29f73  Qn (i32)0xc40dcfae
+vrsqrts.f32 d10, d13, d15 :: Qd 0xce915379 0xce915379  Qm (i32)0x4887f70e  Qn (i32)0x4608d008
+vrsqrts.f32 d0, d1, d2 :: Qd 0xdcee81fd 0xdcee81fd  Qm (i32)0x4e511724  Qn (i32)0x4e920233
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7fc00000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x3f800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x00000000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0x7f800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000  Qn (i32)0xff800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x00000000  Qn (i32)0x7fc00000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000  Qm (i32)0x00000000  Qn (i32)0x3f800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000  Qm (i32)0x00000000  Qn (i32)0x00000000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000  Qm (i32)0x00000000  Qn (i32)0x7f800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000  Qm (i32)0x00000000  Qn (i32)0xff800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7f800000  Qn (i32)0x7fc00000
+vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x3f800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000  Qm (i32)0x7f800000  Qn (i32)0x00000000
+vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0x7f800000  Qn (i32)0x7f800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x7f800000  Qn (i32)0xff800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000  Qn (i32)0x7fc00000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x3f800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x3fc00000 0x3fc00000  Qm (i32)0xff800000  Qn (i32)0x00000000
+vrsqrts.f32 d0, d1, d2 :: Qd 0x7f800000 0x7f800000  Qm (i32)0xff800000  Qn (i32)0x7f800000
+vrsqrts.f32 d0, d1, d2 :: Qd 0xff800000 0xff800000  Qm (i32)0xff800000  Qn (i32)0xff800000
+---- VRSQRTE (fp) ----
+vrsqrte.f32 d0, d1 :: Qd 0x3f0f0000 0x3f0f0000  Qm (i32)0x404ccccd
+vrsqrte.f32 d10, d11 :: Qd 0x2ccb0000 0x2ccb0000  Qm (i32)0x64cb49b4
+vrsqrte.f32 d15, d4 :: Qd 0x37998000 0x37998000  Qm (i32)0x4f32d05e
+vrsqrte.f32 d15, d4 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xbf000000
+vrsqrte.f32 d15, d4 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xc0e33333
+vrsqrte.f32 d12, d8 :: Qd 0x3eb50000 0x3eb50000  Qm (i32)0x40fff800
+vrsqrte.f32 d12, d8 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xc0fff800
+vrsqrte.f32 d0, d1 :: Qd 0x3f0f0000 0x3f0f0000  Qm (i32)0x404ccccd
+vrsqrte.f32 d10, d11 :: Qd 0x2ccb0000 0x2ccb0000  Qm (i32)0x64cb49b4
+vrsqrte.f32 d15, d4 :: Qd 0x37998000 0x37998000  Qm (i32)0x4f32d05e
+vrsqrte.f32 d15, d4 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xbf000000
+vrsqrte.f32 d15, d4 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xc0e33333
+vrsqrte.f32 d12, d8 :: Qd 0x3eb50000 0x3eb50000  Qm (i32)0x40fff800
+vrsqrte.f32 d12, d8 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xc0fff800
+vrsqrte.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000007
+vrsqrte.f32 d10, d11 :: Qd 0xff800000 0xff800000  Qm (i32)0x80000000
+vrsqrte.f32 d0, d1 :: Qd 0xff800000 0xff800000  Qm (i32)0x80000001
+vrsqrte.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fffffff
+vrsqrte.f32 d0, d14 :: Qd 0x46e48000 0x46e48000  Qm (i32)0x30a0bcef
+vrsqrte.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000007
+vrsqrte.f32 d10, d11 :: Qd 0xff800000 0xff800000  Qm (i32)0x80000000
+vrsqrte.f32 d0, d1 :: Qd 0xff800000 0xff800000  Qm (i32)0x80000001
+vrsqrte.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fffffff
+vrsqrte.f32 d0, d14 :: Qd 0x46e48000 0x46e48000  Qm (i32)0x30a0bcef
+vrsqrte.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0x7fc00000
+vrsqrte.f32 d0, d1 :: Qd 0x7f800000 0x7f800000  Qm (i32)0x00000000
+vrsqrte.f32 d0, d1 :: Qd 0x00000000 0x00000000  Qm (i32)0x7f800000
+vrsqrte.f32 d0, d1 :: Qd 0x7fc00000 0x7fc00000  Qm (i32)0xff800000

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.vgtest
new file mode 100644 (file)
index 0000000..dffebc4
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/neon64.vgtest
@@ -0,0 +1,2 @@
+prog: neon64
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.c
index bc3254a1f5725f853a1d8fd1e4dc24f3eaeafedb..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.c
@@ -1,850 +0,0 @@
-
-/* How to compile:
-   gcc -O -g -Wall -mcpu=cortex-a8 -o testarmv6int testarmv6int.c
-*/
-
-#include <stdio.h>
-
-/* test macros to generate and output the result of a single instruction */
-#define TESTINST2(instruction, RMval, RD, RM, carryin) \
-{ \
-       unsigned int out; \
-       unsigned int cpsr; \
-\
-       __asm__ volatile( \
-               "movs %3,%3;" \
-               "msrne cpsr_f,#(1<<29);" \
-               "msreq cpsr_f,#0;" \
-               "mov " #RM ",%2;" \
-                /* set #RD to 0x55555555 so we can see which parts get overwritten */ \
-                "mov " #RD ", #0x55" "\n\t" \
-                "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \
-                "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \
-               instruction ";" \
-               "mov %0," #RD ";" \
-               "mrs %1,cpsr;" \
-               : "=&r" (out), "=&r" (cpsr) \
-               : "r" (RMval), "r" (carryin) \
-               : #RD, #RM, "cc", "memory" \
-       ); \
-       printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
-               instruction, out, RMval, \
-               carryin ? 1 : 0, \
-               cpsr & 0xffff0000, \
-               ((1<<31) & cpsr) ? 'N' : ' ', \
-               ((1<<30) & cpsr) ? 'Z' : ' ', \
-               ((1<<29) & cpsr) ? 'C' : ' ', \
-               ((1<<28) & cpsr) ? 'V' : ' ' \
-               ); \
-}
-
-#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \
-{ \
-       unsigned int out; \
-       unsigned int cpsr; \
-\
-       __asm__ volatile( \
-               "movs %4,%4;" \
-               "msrne cpsr_f,#(1<<29);" \
-               "msreq cpsr_f,#0;" \
-               "mov " #RM ",%2;" \
-               "mov " #RN ",%3;" \
-               instruction ";" \
-               "mov %0," #RD ";" \
-               "mrs %1,cpsr;" \
-               : "=&r" (out), "=&r" (cpsr) \
-               : "r" (RMval), "r" (RNval), "r" (carryin) \
-               : #RD, #RM, #RN, "cc", "memory" \
-       ); \
-       printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
-               instruction, out, RMval, RNval, \
-               carryin ? 1 : 0, \
-               cpsr & 0xffff0000, \
-               ((1<<31) & cpsr) ? 'N' : ' ', \
-               ((1<<30) & cpsr) ? 'Z' : ' ', \
-               ((1<<29) & cpsr) ? 'C' : ' ', \
-               ((1<<28) & cpsr) ? 'V' : ' ' \
-               ); \
-}
-
-#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \
-{ \
-       unsigned int out; \
-       unsigned int cpsr; \
-\
-       __asm__ volatile( \
-               "movs %5,%5;" \
-               "msrne cpsr_f,#(1<<29);" \
-               "msreq cpsr_f,#0;" \
-               "mov " #RM ",%2;" \
-               "mov " #RN ",%3;" \
-               "mov " #RS ",%4;" \
-               instruction ";" \
-               "mov %0," #RD ";" \
-               "mrs %1,cpsr;" \
-               : "=&r" (out), "=&r" (cpsr) \
-               : "r" (RMval), "r" (RNval), "r" (RSval), "r" (carryin) \
-               : #RD, #RM, #RN, #RS, "cc", "memory" \
-       ); \
-       printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
-               instruction, out, RMval, RNval, RSval, \
-               carryin ? 1 : 0, \
-               cpsr & 0xffff0000, \
-               ((1<<31) & cpsr) ? 'N' : ' ', \
-               ((1<<30) & cpsr) ? 'Z' : ' ', \
-               ((1<<29) & cpsr) ? 'C' : ' ', \
-               ((1<<28) & cpsr) ? 'V' : ' ' \
-               ); \
-}
-
-#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \
-{ \
-       unsigned int out; \
-       unsigned int out2; \
-       unsigned int cpsr; \
-\
-       __asm__ volatile( \
-               "movs %7,%7;" \
-               "msrne cpsr_f,#(1<<29);" \
-               "msreq cpsr_f,#0;" \
-               "mov " #RD ",%3;" \
-               "mov " #RD2 ",%4;" \
-               "mov " #RM ",%5;" \
-               "mov " #RS ",%6;" \
-               instruction ";" \
-               "mov %0," #RD ";" \
-               "mov %1," #RD2 ";" \
-               "mrs %2,cpsr;" \
-               : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \
-               : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (carryin) \
-               : #RD, #RD2, #RM, #RS, "cc", "memory" \
-       ); \
-       printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
-               instruction, out, out2, RMval, RSval, \
-               carryin ? 1 : 0, \
-               cpsr & 0xffff0000, \
-               ((1<<31) & cpsr) ? 'N' : ' ', \
-               ((1<<30) & cpsr) ? 'Z' : ' ', \
-               ((1<<29) & cpsr) ? 'C' : ' ', \
-               ((1<<28) & cpsr) ? 'V' : ' ' \
-               ); \
-}
-
-/* helpers */
-#define TESTCARRY { int c = 0; for (c = 0; c < 2; c++) {
-#define TESTCARRYEND }}
-
-
-
-
-int main(int argc, char **argv)
-{
-
-       printf("MOV\n");
-       TESTINST2("mov  r0, r1", 1, r0, r1, 0);
-       TESTINST2("cpy  r0, r1", 1, r0, r1, 0);
-       TESTINST2("mov  r0, #0", 0, r0, r1, 0);
-       TESTINST2("mov  r0, #1", 0, r0, r1, 0);
-       TESTCARRY
-       TESTINST2("movs r0, r1", 1, r0, r1, c);
-       TESTINST2("movs r0, r1", 0, r0, r1, c);
-       TESTINST2("movs r0, r1", 0x80000000, r0, r1, c);
-       TESTINST2("movs r0, #0", 0, r0, r1, c);
-       TESTINST2("movs r0, #1", 0, r0, r1, c);
-       TESTCARRYEND
-
-       printf("MVN\n");
-       TESTINST2("mvn  r0, r1", 1, r0, r1, 0);
-       TESTCARRY
-       TESTINST2("mvns r0, r1", 1, r0, r1, c);
-       TESTINST2("mvns r0, r1", 0, r0, r1, c);
-       TESTINST2("mvns r0, r1", 0x80000000, r0, r1, c);
-       TESTCARRYEND
-
-       printf("ADD\n");
-       TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0);
-       TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0);
-       TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0);
-       TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0);
-       TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0);
-       TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0);
-       TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0);
-       TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0);
-       TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0);
-
-       printf("ADC\n");
-       TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0);
-       TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1);
-
-       printf("LSL\n");
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
-
-       TESTINST3("lsl  r0, r1, r2", 0x1, 0, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0x1, 1, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0x1, 31, r0, r1, r2, 0);
-       TESTINST3("lsl  r0, r1, r2", 0x2, 31, r0, r1, r2, 0);
-
-       printf("LSLS\n");
-       TESTCARRY
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0x1, 0, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0x1, 1, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0x1, 31, r0, r1, r2, c);
-       TESTINST3("lsls r0, r1, r2", 0x2, 31, r0, r1, r2, c);
-       TESTCARRYEND
-
-       printf("LSL immediate\n");
-       TESTCARRY
-       TESTINST2("lsl  r0, r1, #0", 0xffffffff, r0, r1, c);
-       TESTINST2("lsl  r0, r1, #1", 0xffffffff, r0, r1, c);
-       TESTINST2("lsl  r0, r1, #31", 0xffffffff, r0, r1, c);
-       TESTINST2("lsl  r0, r1, #0", 0x1, r0, r1, c);
-       TESTINST2("lsl  r0, r1, #1", 0x1, r0, r1, c);
-       TESTINST2("lsl  r0, r1, #31", 0x1, r0, r1, c);
-       TESTINST2("lsl  r0, r1, #31", 0x2, r0, r1, c);
-       TESTCARRYEND
-
-       printf("LSLS immediate\n");
-       TESTCARRY
-       TESTINST2("lsls r0, r1, #0", 0xffffffff, r0, r1, c);
-       TESTINST2("lsls r0, r1, #1", 0xffffffff, r0, r1, c);
-       TESTINST2("lsls r0, r1, #31", 0xffffffff, r0, r1, c);
-       TESTINST2("lsls r0, r1, #0", 0x1, r0, r1, c);
-       TESTINST2("lsls r0, r1, #1", 0x1, r0, r1, c);
-       TESTINST2("lsls r0, r1, #31", 0x1, r0, r1, c);
-       TESTINST2("lsls r0, r1, #31", 0x2, r0, r1, c);
-       TESTCARRYEND
-
-       printf("LSR\n");
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
-       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
-
-       printf("LSRS\n");
-       TESTCARRY
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
-       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
-       TESTCARRYEND
-
-       printf("LSR immediate\n");
-       TESTINST2("lsr  r0, r1, #0", 0xffffffff, r0, r1, 0);
-       TESTINST2("lsr  r0, r1, #1", 0xffffffff, r0, r1, 0);
-       TESTINST2("lsr  r0, r1, #31", 0xffffffff, r0, r1, 0);
-       TESTINST2("lsr  r0, r1, #32", 0xffffffff, r0, r1, 0);
-       TESTINST2("lsr  r0, r1, #16", 0x00010000, r0, r1, 0);
-       TESTINST2("lsr  r0, r1, #17", 0x00010000, r0, r1, 0);
-       TESTINST2("lsr  r0, r1, #18", 0x00010000, r0, r1, 0);
-
-       printf("LSRS immediate\n");
-       TESTCARRY
-       TESTINST2("lsrs r0, r1, #0", 0xffffffff, r0, r1, c);
-       TESTINST2("lsrs r0, r1, #1", 0xffffffff, r0, r1, c);
-       TESTINST2("lsrs r0, r1, #31", 0xffffffff, r0, r1, c);
-       TESTINST2("lsrs r0, r1, #32", 0xffffffff, r0, r1, c);
-       TESTINST2("lsrs r0, r1, #16", 0x00010000, r0, r1, c);
-       TESTINST2("lsrs r0, r1, #17", 0x00010000, r0, r1, c);
-       TESTINST2("lsrs r0, r1, #18", 0x00010000, r0, r1, c);
-       TESTCARRYEND
-
-       printf("ASR\n");
-       TESTCARRY
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, c);
-       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, c);
-       TESTCARRYEND
-
-       printf("ASRS\n");
-       TESTCARRY
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, c);
-       TESTCARRYEND
-
-       TESTCARRY
-       TESTINST3("asrs r0, r1, r2", 0x8, 0, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x8, 1, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x8, 2, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x8, 3, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x8, 4, r0, r1, r2, c);
-       TESTINST3("asrs r0, r1, r2", 0x8, 5, r0, r1, r2, c);
-       TESTCARRYEND
-
-       TESTINST3("asrs r0, r1, r2", 0x80000001, 1, r0, r1, r2, 0);
-       TESTINST3("asrs r0, r1, r2", 0x80000001, 2, r0, r1, r2, 0);
-
-       printf("ASR immediate\n");
-       TESTINST2("asr  r0, r1, #0", 0xffffffff, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #1", 0xffffffff, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #31", 0xffffffff, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #32", 0xffffffff, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #0", 0x7fffffff, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #1", 0x7fffffff, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #31", 0x7fffffff, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #32", 0x7fffffff, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #16", 0x00010000, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #17", 0x00010000, r0, r1, 0);
-       TESTINST2("asr  r0, r1, #18", 0x00010000, r0, r1, 0);
-
-       printf("ASRS immediate\n");
-       TESTCARRY
-       TESTINST2("asrs r0, r1, #0", 0xffffffff, r0, r1, c);
-       TESTINST2("asrs r0, r1, #1", 0xffffffff, r0, r1, c);
-       TESTINST2("asrs r0, r1, #31", 0xffffffff, r0, r1, c);
-       TESTINST2("asrs r0, r1, #32", 0xffffffff, r0, r1, c);
-       TESTINST2("asrs r0, r1, #0", 0x7fffffff, r0, r1, c);
-       TESTINST2("asrs r0, r1, #1", 0x7fffffff, r0, r1, c);
-       TESTINST2("asrs r0, r1, #31", 0x7fffffff, r0, r1, c);
-       TESTINST2("asrs r0, r1, #32", 0x7fffffff, r0, r1, c);
-       TESTINST2("asrs r0, r1, #16", 0x00010000, r0, r1, c);
-       TESTINST2("asrs r0, r1, #17", 0x00010000, r0, r1, c);
-       TESTINST2("asrs r0, r1, #18", 0x00010000, r0, r1, c);
-       TESTCARRYEND
-
-       printf("ROR\n");
-       TESTCARRY
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 0, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x80088000, 1, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 1, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 2, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 31, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 32, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 33, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 63, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 64, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 255, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 256, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x80088000, 256, r0, r1, r2, c);
-       TESTINST3("ror  r0, r1, r2", 0x00088000, 257, r0, r1, r2, c);
-       TESTCARRYEND
-
-       printf("RORS\n");
-       TESTCARRY
-       TESTINST3("rors r0, r1, r2", 0x00088000, 0, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x80088000, 0, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 1, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 2, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 31, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 32, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 33, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 63, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 64, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 255, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 256, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x80088000, 256, r0, r1, r2, c);
-       TESTINST3("rors r0, r1, r2", 0x00088000, 257, r0, r1, r2, c);
-       TESTCARRYEND
-
-       printf("ROR immediate\n");
-       TESTCARRY
-       TESTINST2("ror  r0, r1, #0", 0x00088000, r0, r1, c);
-       TESTINST2("ror  r0, r1, #1", 0x00088000, r0, r1, c);
-       TESTINST2("ror  r0, r1, #31", 0x00088000, r0, r1, c);
-       TESTINST2("ror  r0, r1, #16", 0x00010000, r0, r1, c);
-       TESTINST2("ror  r0, r1, #17", 0x00010000, r0, r1, c);
-       TESTINST2("ror  r0, r1, #18", 0x00010000, r0, r1, c);
-       TESTCARRYEND
-
-       printf("RORS immediate\n");
-       TESTCARRY
-       TESTINST2("rors r0, r1, #0", 0x00088000, r0, r1, c);
-       TESTINST2("rors r0, r1, #1", 0x00088000, r0, r1, c);
-       TESTINST2("rors r0, r1, #31", 0x00088000, r0, r1, c);
-       TESTINST2("rors r0, r1, #16", 0x00010000, r0, r1, c);
-       TESTINST2("rors r0, r1, #17", 0x00010000, r0, r1, c);
-       TESTINST2("rors r0, r1, #18", 0x00010000, r0, r1, c);
-       TESTCARRYEND
-
-       printf("shift with barrel shifter\n");
-       TESTCARRY
-       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 0, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 1, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 31, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 32, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 255, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 256, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
-       TESTCARRYEND
-
-       TESTCARRY
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 0, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 1, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 2, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 3, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 4, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 5, r0, r1, r2, r3, c);
-       TESTCARRYEND
-
-       TESTCARRY
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, c);
-       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, c);
-       TESTCARRYEND
-
-       TESTCARRY
-       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
-
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, c);
-       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, c);
-       TESTCARRYEND
-
-       TESTCARRY
-       TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
-       TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
-       TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
-       TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
-       TESTCARRYEND
-
-       printf("MUL\n");
-       TESTINST3("mul  r0, r1, r2", 0, 0, r0, r1, r2, 0);
-       TESTINST3("mul  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
-       TESTINST3("mul  r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
-       TESTINST3("mul  r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
-       TESTINST3("mul  r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
-       TESTINST3("mul  r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
-
-       printf("MULS\n");
-       TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0);
-       TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
-       TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
-       TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
-       TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
-       TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
-
-       printf("MLA\n");
-       TESTINST4("mla  r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mla  r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mla  r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mla  r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mla  r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mla  r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
-       printf("MLAS\n");
-       TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
-       printf("MLS\n");
-       TESTINST4("mls  r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mls  r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mls  r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mls  r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mls  r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
-       TESTINST4("mls  r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
-
-       printf("UMULL\n");
-       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-
-       printf("SMULL\n");
-       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-
-       printf("UMLAL\n");
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-
-       printf("SMLAL\n");
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
-       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
-
-       printf("CLZ\n");
-       TESTCARRY
-       TESTINST2("clz  r0, r1", 0, r0, r1, c);
-       TESTINST2("clz  r0, r1", 1, r0, r1, c);
-       TESTINST2("clz  r0, r1", 0x10, r0, r1, c);
-       TESTINST2("clz  r0, r1", 0xffffffff, r0, r1, c);
-       TESTCARRYEND
-
-       printf("extend instructions\n");
-       TESTINST2("uxtb r0, r1", 0, r0, r1, 0);
-       TESTINST2("uxtb r0, r1", 1, r0, r1, 0);
-       TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0);
-       TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0);
-       TESTINST2("sxtb r0, r1", 0, r0, r1, 0);
-       TESTINST2("sxtb r0, r1", 1, r0, r1, 0);
-       TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0);
-       TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0);
-
-       TESTINST2("uxth r0, r1", 0, r0, r1, 0);
-       TESTINST2("uxth r0, r1", 1, r0, r1, 0);
-       TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0);
-       TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0);
-       TESTINST2("sxth r0, r1", 0, r0, r1, 0);
-       TESTINST2("sxth r0, r1", 1, r0, r1, 0);
-       TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0);
-       TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0);
-       TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0);
-       TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0);
-       TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0);
-
-       TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0);
-       TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0);
-       TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0);
-       TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0);
-       TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0);
-
-       TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0);
-       TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0);
-       TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0);
-       TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0);
-       TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0);
-
-       printf("------------ BFI ------------\n");
-
-        /* bfi  rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */
-       TESTINST2("bfi  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
-       TESTINST2("bfi  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
-       TESTINST2("bfi  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
-       TESTINST2("bfi  r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfi  r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfi  r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0);
-
-       TESTINST2("bfi  r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfi  r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0);
-
-       TESTINST2("bfi  r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfi  r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfi  r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0);
-
-       printf("------------ BFC ------------\n");
-
-        /* bfi  rDst, #lsb-in-dst, #number-of-bits-to-copy */
-       TESTINST2("bfc  r0, #0, #11", 0xAAAAAAAA, r0, r1, 0);
-       TESTINST2("bfc  r0, #1, #11", 0xAAAAAAAA, r0, r1, 0);
-       TESTINST2("bfc  r0, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
-       TESTINST2("bfc  r0, #19, #11", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfc  r0, #20, #11", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfc  r0, #21, #11", 0xFFFFFFFF, r0, r1, 0);
-
-       TESTINST2("bfc  r0, #0, #32", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfc  r0, #1, #31", 0xFFFFFFFF, r0, r1, 0);
-
-       TESTINST2("bfc  r0, #29, #3", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfc  r0, #30, #2", 0xFFFFFFFF, r0, r1, 0);
-       TESTINST2("bfc  r0, #31, #1", 0xFFFFFFFF, r0, r1, 0);
-
-       printf("------------ SBFX ------------\n");
-
-        /* sbfx rDst, rSrc, #lsb, #width */
-        TESTINST2("sbfx  r0, r1, #0, #1", 0x00000000, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #0, #1", 0x00000001, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000000, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000001, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000002, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000003, r0, r1, 0);
-
-        TESTINST2("sbfx  r0, r1, #0, #2", 0x00000000, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #0, #2", 0x00000001, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000000, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000001, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000002, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000003, r0, r1, 0);
-
-        TESTINST2("sbfx  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
-        TESTINST2("sbfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
-        TESTINST2("sbfx  r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
-        TESTINST2("sbfx  r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
-
-       printf("------------ UBFX ------------\n");
-
-        /* ubfx rDst, rSrc, #lsb, #width */
-        TESTINST2("ubfx  r0, r1, #0, #1", 0x00000000, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #0, #1", 0x00000001, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000000, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000001, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000002, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000003, r0, r1, 0);
-
-        TESTINST2("ubfx  r0, r1, #0, #2", 0x00000000, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #0, #2", 0x00000001, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000000, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000001, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000002, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000003, r0, r1, 0);
-
-        TESTINST2("ubfx  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
-        TESTINST2("ubfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
-
-        TESTINST2("ubfx  r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
-        TESTINST2("ubfx  r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
-
-       printf("------------ SMULL{B,T}{B,T} ------------\n");
-        /* SMULxx rD, rN, rM */
-
-       TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000,  r0, r1, r2, 0);
-       TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002,  r0, r1, r2, 0);
-       TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff,  r0, r1, r2, 0);
-       TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff,  r0, r1, r2, 0);
-       TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff,  r0, r1, r2, 0);
-
-       printf("------------ SXTAB ------------\n");
-        TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-
-        TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, 
-                  r0, r1, r2, 0);
-
-       printf("------------ UXTAB ------------\n");
-        TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-
-        TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, 
-                  r0, r1, r2, 0);
-
-       printf("------------ SXTAH ------------\n");
-        TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-
-        TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, 
-                  r0, r1, r2, 0);
-        TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, 
-                  r0, r1, r2, 0);
-
-       printf("------------ UXTAH ------------\n");
-        TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, 
-                  r0, r1, r2, 0);
-
-        TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, 
-                  r0, r1, r2, 0);
-        TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, 
-                  r0, r1, r2, 0);
-
-       printf("------------ PLD/PLDW (begin) ------------\n");
-        /* These don't have any effect on the architected state, so,
-           uh, there's no result values to check.  Just _do_ some of
-           them and check Valgrind's instruction decoder eats them up
-           without complaining. */
-        { int alocal;
-          printf("pld  reg +/- imm12  cases\n");
-          __asm__ __volatile__( "pld [%0, #128]" : :/*in*/"r"(&alocal) );
-          __asm__ __volatile__( "pld [%0, #-128]" : :/*in*/"r"(&alocal) );
-          __asm__ __volatile__( "pld [r15, #-128]" : :/*in*/"r"(&alocal) );
-
-          // apparently pldw is v7 only
-          //__asm__ __volatile__( "pldw [%0, #128]" : :/*in*/"r"(&alocal) );
-          //__asm__ __volatile__( "pldw [%0, #-128]" : :/*in*/"r"(&alocal) );
-          //__asm__ __volatile__( "pldw [r15, #128]" : :/*in*/"r"(&alocal) );
-
-          printf("pld  reg +/- shifted reg  cases\n");
-          __asm__ __volatile__( "pld [%0, %1]" : : /*in*/"r"(&alocal), "r"(0) );
-          __asm__ __volatile__( "pld [%0, %1, LSL #1]" : : /*in*/"r"(&alocal), "r"(0) );
-          __asm__ __volatile__( "pld [%0, %1, LSR #1]" : : /*in*/"r"(&alocal), "r"(0) );
-          __asm__ __volatile__( "pld [%0, %1, ASR #1]" : : /*in*/"r"(&alocal), "r"(0) );
-          __asm__ __volatile__( "pld [%0, %1, ROR #1]" : : /*in*/"r"(&alocal), "r"(0) );
-          __asm__ __volatile__( "pld [%0, %1, RRX]" : : /*in*/"r"(&alocal), "r"(0) );
-        }
-       printf("------------ PLD/PLDW (done) ------------\n");
-
-
-       return 0;
-}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.stdout.exp
index 064b52672fa50c700cc28f98aac34eb6d489ab06..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.stdout.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.stdout.exp
@@ -1,739 +0,0 @@
-MOV
-mov  r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-cpy  r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-mov  r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-mov  r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000     
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000  Z  
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 0, cpsr 0x80000000 N   
-movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000  Z  
-movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000     
-movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
-movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000  ZC 
-movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 1, cpsr 0xa0000000 N C 
-movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000  ZC 
-movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 1, cpsr 0x20000000   C 
-MVN
-mvn  r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x00000000     
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x80000000 N   
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 0, cpsr 0x80000000 N   
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 0, cpsr 0x00000000     
-mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 1, cpsr 0xa0000000 N C 
-mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 1, cpsr 0xa0000000 N C 
-mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 1, cpsr 0x20000000   C 
-ADD
-adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000  Z  
-adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, carryin 0, cpsr 0x60000000  ZC 
-adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x90000000 N  V
-adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, carryin 0, cpsr 0x30000000   CV
-adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
-ADC
-adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000  Z  
-adcs r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, carryin 1, cpsr 0x00000000     
-LSL
-lsl  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 0, cpsr 0x00000000     
-LSLS
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
-lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C 
-lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C 
-lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C 
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x60000000  ZC 
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x40000000  Z  
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000  Z  
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x40000000  Z  
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000  Z  
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x80000000 N   
-lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000     
-lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000     
-lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 0, cpsr 0x80000000 N   
-lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 0, cpsr 0x60000000  ZC 
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C 
-lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0xa0000000 N C 
-lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0xa0000000 N C 
-lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0xa0000000 N C 
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x60000000  ZC 
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x40000000  Z  
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000  Z  
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x40000000  Z  
-lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000  Z  
-lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C 
-lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
-lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 1, cpsr 0x00000000     
-lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 1, cpsr 0x80000000 N   
-lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 1, cpsr 0x60000000  ZC 
-LSL immediate
-lsl  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 0, cpsr 0x00000000     
-lsl  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
-lsl  r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
-lsl  r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
-lsl  r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
-lsl  r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
-lsl  r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
-lsl  r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 1, cpsr 0x20000000   C 
-LSLS immediate
-lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N   
-lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
-lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
-lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 0, cpsr 0x00000000     
-lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x80000000 N   
-lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 0, cpsr 0x60000000  ZC 
-lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
-lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
-lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
-lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
-lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 1, cpsr 0x00000000     
-lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 1, cpsr 0x80000000 N   
-lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 1, cpsr 0x60000000  ZC 
-LSR
-lsr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
-LSRS
-lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
-lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x20000000   C 
-lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x20000000   C 
-lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x20000000   C 
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x60000000  ZC 
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x40000000  Z  
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000  Z  
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x40000000  Z  
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000  Z  
-lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C 
-lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
-lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
-lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000   C 
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x60000000  ZC 
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x40000000  Z  
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000  Z  
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x40000000  Z  
-lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000  Z  
-LSR immediate
-lsr  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
-lsr  r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
-LSRS immediate
-lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N   
-lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 0, cpsr 0x20000000   C 
-lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x20000000   C 
-lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x60000000  ZC 
-lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
-lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x60000000  ZC 
-lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x40000000  Z  
-lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
-lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
-lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
-lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x60000000  ZC 
-lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000     
-lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x60000000  ZC 
-lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x40000000  Z  
-ASR
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 1, cpsr 0x20000000   C 
-asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
-ASRS
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x80000000 N   
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x20000000   C 
-asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 0, cpsr 0x20000000   C 
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 0, cpsr 0x60000000  ZC 
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 0, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 0, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 0, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
-asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
-asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 1, cpsr 0x60000000  ZC 
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 1, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 1, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 1, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
-asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, carryin 0, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, carryin 0, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, carryin 0, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, carryin 0, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, carryin 0, cpsr 0x60000000  ZC 
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, carryin 0, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
-asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, carryin 1, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, carryin 1, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, carryin 1, cpsr 0x00000000     
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, carryin 1, cpsr 0x60000000  ZC 
-asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, carryin 1, cpsr 0x40000000  Z  
-asrs r0, r1, r2 :: rd 0xc0000000 rm 0x80000001, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, r2 :: rd 0xe0000000 rm 0x80000001, rn 0x00000002, carryin 0, cpsr 0x80000000 N   
-ASR immediate
-asr  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
-asr  r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
-ASRS immediate
-asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N   
-asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
-asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000     
-asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 0, cpsr 0x20000000   C 
-asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x60000000  ZC 
-asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x40000000  Z  
-asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
-asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x60000000  ZC 
-asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x40000000  Z  
-asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
-asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 1, cpsr 0x20000000   C 
-asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 1, cpsr 0x20000000   C 
-asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 1, cpsr 0x60000000  ZC 
-asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 1, cpsr 0x40000000  Z  
-asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000     
-asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x60000000  ZC 
-asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x40000000  Z  
-ROR
-ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x40044000 rm 0x80088000, rn 0x00000001, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 0, cpsr 0x00000000     
-ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x40044000 rm 0x80088000, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 1, cpsr 0x20000000   C 
-RORS
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 0, cpsr 0x80000000 N   
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 0, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
-rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C 
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 1, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 1, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 1, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 1, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 1, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 1, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 1, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 1, cpsr 0x00000000     
-rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
-rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C 
-rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 1, cpsr 0x00000000     
-ROR immediate
-ror  r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 0, cpsr 0x00000000     
-ror  r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 0, cpsr 0x00000000     
-ror  r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 0, cpsr 0x00000000     
-ror  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
-ror  r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
-ror  r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
-ror  r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 1, cpsr 0x20000000   C 
-ror  r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 1, cpsr 0x20000000   C 
-RORS immediate
-rors r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 0, cpsr 0x00000000     
-rors r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 0, cpsr 0x00000000     
-rors r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 0, cpsr 0x00000000     
-rors r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
-rors r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 0, cpsr 0xa0000000 N C 
-rors r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
-rors r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 1, cpsr 0x20000000   C 
-rors r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 1, cpsr 0x00000000     
-rors r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 1, cpsr 0x00000000     
-rors r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000     
-rors r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 1, cpsr 0xa0000000 N C 
-rors r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 1, cpsr 0x00000000     
-shift with barrel shifter
-add  r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000000, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x3fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x0000001f, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x00000020, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x000000ff, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000100, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000000, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x3fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000001, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x0000001f, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x00000020, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x000000ff, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000100, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000008 rm 0x00000000, rn 0x00000008 rs 0x00000000, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000004 rm 0x00000000, rn 0x00000008 rs 0x00000001, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000002 rm 0x00000000, rn 0x00000008 rs 0x00000002, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000008 rs 0x00000003, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000004, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000005, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, asr r3 :: rd 0x00000008 rm 0x00000000, rn 0x00000008 rs 0x00000000, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000004 rm 0x00000000, rn 0x00000008 rs 0x00000001, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000002 rm 0x00000000, rn 0x00000008 rs 0x00000002, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000008 rs 0x00000003, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000004, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000005, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 0, cpsr 0x00000000     
-add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 1, cpsr 0x20000000   C 
-add  r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 1, cpsr 0x20000000   C 
-adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x40000000  Z  
-adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x40000000  Z  
-adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x40000000  Z  
-adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x40000000  Z  
-adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 0, cpsr 0x80000000 N   
-adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 0, cpsr 0x00000000     
-adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x80000000 N   
-adds r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x80000000 N   
-adds r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x80000000 N   
-adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x40000000  Z  
-adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x40000000  Z  
-adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x80000000 N   
-adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x80000000 N   
-adds r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x00000000     
-adds r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x00000000     
-adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x40000000  Z  
-adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x40000000  Z  
-adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x80000000 N   
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 1, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 1, cpsr 0x80000000 N   
-adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 1, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 1, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 1, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 1, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 1, cpsr 0x00000000     
-adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 1, cpsr 0x80000000 N   
-adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 1, cpsr 0x00000000     
-adcs r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N   
-adcs r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N   
-adcs r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x80000000 N   
-adcs r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-adcs r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x60000000  ZC 
-adcs r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x60000000  ZC 
-adcs r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x80000000 N   
-adcs r0, r1, r2, lsr r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x90000000 N  V
-MUL
-mul  r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000     
-mul  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
-mul  r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000     
-mul  r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000     
-mul  r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000     
-mul  r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000     
-MULS
-muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000  Z  
-muls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x40000000  Z  
-muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x40000000  Z  
-muls r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000     
-muls r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000     
-muls r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x80000000 N   
-MLA
-mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mla  r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mla  r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mla  r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-MLAS
-mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mlas r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mlas r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mlas r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x80000000 N   
-MLS
-mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mls  r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mls  r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-mls  r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000     
-UMULL
-umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000     
-umull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-umull  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
-umull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
-umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
-umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000  Z  
-umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
-umulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-umulls r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
-umulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x80000000 N   
-SMULL
-smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000     
-smull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-smull  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
-smull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
-smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
-smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000  Z  
-smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
-smulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-smulls r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
-smulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
-UMLAL
-umlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-umlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-umlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-umlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-umlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-umlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000     
-umlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-umlal  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
-umlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
-umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
-umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x80000000 N   
-umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000  Z  
-umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
-umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-umlals r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
-umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x80000000 N   
-SMLAL
-smlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-smlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-smlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-smlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-smlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
-smlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000     
-smlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-smlal  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
-smlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
-smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
-smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
-smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x80000000 N   
-smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000  Z  
-smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
-smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
-smlals r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
-smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
-CLZ
-clz  r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 0, cpsr 0x00000000     
-clz  r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 0, cpsr 0x00000000     
-clz  r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 0, cpsr 0x00000000     
-clz  r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-clz  r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 1, cpsr 0x20000000   C 
-clz  r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 1, cpsr 0x20000000   C 
-clz  r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 1, cpsr 0x20000000   C 
-clz  r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
-extend instructions
-uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000     
-uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, carryin 0, cpsr 0x00000000     
-sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-uxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-uxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, carryin 0, cpsr 0x00000000     
-uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-sxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-sxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, carryin 0, cpsr 0x00000000     
-sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, carryin 0, cpsr 0x00000000     
-sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, carryin 0, cpsr 0x00000000     
-sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, carryin 0, cpsr 0x00000000     
-sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000     
-uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, carryin 0, cpsr 0x00000000     
-uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, carryin 0, cpsr 0x00000000     
-uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, carryin 0, cpsr 0x00000000     
-uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, carryin 0, cpsr 0x00000000     
-uxtb16 r0, r1 :: rd 0x00ff00ff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-uxtb16 r0, r1, ror #16 :: rd 0x00ff0000 rm 0x0000ffff, carryin 0, cpsr 0x00000000     
-sxtb16 r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-sxtb16 r0, r1 :: rd 0xffffffff rm 0x00ff00ff, carryin 0, cpsr 0x00000000     
-sxtb16 r0, r1 :: rd 0x007f007f rm 0x007f007f, carryin 0, cpsr 0x00000000     
------------- BFI ------------
-bfi  r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfi  r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
------------- BFC ------------
-bfc  r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-bfc  r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-bfc  r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-bfc  r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfc  r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfc  r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfc  r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfc  r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfc  r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfc  r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
-bfc  r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
------------- SBFX ------------
-sbfx  r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-sbfx  r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
------------- UBFX ------------
-ubfx  r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
-ubfx  r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
------------- SMULL{B,T}{B,T} ------------
-smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, carryin 0, cpsr 0x00000000     
-smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, carryin 0, cpsr 0x00000000     
-smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, carryin 0, cpsr 0x00000000     
-smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, carryin 0, cpsr 0x00000000     
-smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, carryin 0, cpsr 0x00000000     
------------- SXTAB ------------
-sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
-sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
-sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
-sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
------------- UXTAB ------------
-uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
-uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
-uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
-uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
------------- SXTAH ------------
-sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-sxtah r0, r1, r2, ROR #8  :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-sxtah r0, r1, r2, ROR #0  :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
-sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
-sxtah r0, r1, r2, ROR #8  :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
-sxtah r0, r1, r2, ROR #0  :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
------------- UXTAH ------------
-uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-uxtah r0, r1, r2, ROR #8  :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-uxtah r0, r1, r2, ROR #0  :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
-uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
-uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
-uxtah r0, r1, r2, ROR #8  :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
-uxtah r0, r1, r2, ROR #0  :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
------------- PLD/PLDW (begin) ------------
-pld  reg +/- imm12  cases
-pld  reg +/- shifted reg  cases
------------- PLD/PLDW (done) ------------

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.vgtest
index 569572461d9387f0f18a7e0cbad46f569a446e6d..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.vgtest
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6int.vgtest
@@ -1,2 +0,0 @@
-prog: v6int
-vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.c
new file mode 100644 (file)
index 0000000..bc3254a
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.c
@@ -0,0 +1,850 @@
+
+/* How to compile:
+   gcc -O -g -Wall -mcpu=cortex-a8 -o testarmv6int testarmv6int.c
+*/
+
+#include <stdio.h>
+
+/* test macros to generate and output the result of a single instruction */
+#define TESTINST2(instruction, RMval, RD, RM, carryin) \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+               "movs %3,%3;" \
+               "msrne cpsr_f,#(1<<29);" \
+               "msreq cpsr_f,#0;" \
+               "mov " #RM ",%2;" \
+                /* set #RD to 0x55555555 so we can see which parts get overwritten */ \
+                "mov " #RD ", #0x55" "\n\t" \
+                "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \
+                "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (RMval), "r" (carryin) \
+               : #RD, #RM, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rm 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, RMval, \
+               carryin ? 1 : 0, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, carryin) \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+               "movs %4,%4;" \
+               "msrne cpsr_f,#(1<<29);" \
+               "msreq cpsr_f,#0;" \
+               "mov " #RM ",%2;" \
+               "mov " #RN ",%3;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (RMval), "r" (RNval), "r" (carryin) \
+               : #RD, #RM, #RN, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, RMval, RNval, \
+               carryin ? 1 : 0, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, carryin) \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+               "movs %5,%5;" \
+               "msrne cpsr_f,#(1<<29);" \
+               "msreq cpsr_f,#0;" \
+               "mov " #RM ",%2;" \
+               "mov " #RN ",%3;" \
+               "mov " #RS ",%4;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (RMval), "r" (RNval), "r" (RSval), "r" (carryin) \
+               : #RD, #RM, #RN, #RS, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, RMval, RNval, RSval, \
+               carryin ? 1 : 0, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, carryin) \
+{ \
+       unsigned int out; \
+       unsigned int out2; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+               "movs %7,%7;" \
+               "msrne cpsr_f,#(1<<29);" \
+               "msreq cpsr_f,#0;" \
+               "mov " #RD ",%3;" \
+               "mov " #RD2 ",%4;" \
+               "mov " #RM ",%5;" \
+               "mov " #RS ",%6;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mov %1," #RD2 ";" \
+               "mrs %2,cpsr;" \
+               : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \
+               : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (carryin) \
+               : #RD, #RD2, #RM, #RS, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, carryin %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, out2, RMval, RSval, \
+               carryin ? 1 : 0, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+/* helpers */
+#define TESTCARRY { int c = 0; for (c = 0; c < 2; c++) {
+#define TESTCARRYEND }}
+
+
+
+
+int main(int argc, char **argv)
+{
+
+       printf("MOV\n");
+       TESTINST2("mov  r0, r1", 1, r0, r1, 0);
+       TESTINST2("cpy  r0, r1", 1, r0, r1, 0);
+       TESTINST2("mov  r0, #0", 0, r0, r1, 0);
+       TESTINST2("mov  r0, #1", 0, r0, r1, 0);
+       TESTCARRY
+       TESTINST2("movs r0, r1", 1, r0, r1, c);
+       TESTINST2("movs r0, r1", 0, r0, r1, c);
+       TESTINST2("movs r0, r1", 0x80000000, r0, r1, c);
+       TESTINST2("movs r0, #0", 0, r0, r1, c);
+       TESTINST2("movs r0, #1", 0, r0, r1, c);
+       TESTCARRYEND
+
+       printf("MVN\n");
+       TESTINST2("mvn  r0, r1", 1, r0, r1, 0);
+       TESTCARRY
+       TESTINST2("mvns r0, r1", 1, r0, r1, c);
+       TESTINST2("mvns r0, r1", 0, r0, r1, c);
+       TESTINST2("mvns r0, r1", 0x80000000, r0, r1, c);
+       TESTCARRYEND
+
+       printf("ADD\n");
+       TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0);
+
+       printf("ADC\n");
+       TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0);
+       TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1);
+
+       printf("LSL\n");
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
+
+       TESTINST3("lsl  r0, r1, r2", 0x1, 0, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0x1, 1, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0x1, 31, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0x2, 31, r0, r1, r2, 0);
+
+       printf("LSLS\n");
+       TESTCARRY
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0x1, 0, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0x1, 1, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0x1, 31, r0, r1, r2, c);
+       TESTINST3("lsls r0, r1, r2", 0x2, 31, r0, r1, r2, c);
+       TESTCARRYEND
+
+       printf("LSL immediate\n");
+       TESTCARRY
+       TESTINST2("lsl  r0, r1, #0", 0xffffffff, r0, r1, c);
+       TESTINST2("lsl  r0, r1, #1", 0xffffffff, r0, r1, c);
+       TESTINST2("lsl  r0, r1, #31", 0xffffffff, r0, r1, c);
+       TESTINST2("lsl  r0, r1, #0", 0x1, r0, r1, c);
+       TESTINST2("lsl  r0, r1, #1", 0x1, r0, r1, c);
+       TESTINST2("lsl  r0, r1, #31", 0x1, r0, r1, c);
+       TESTINST2("lsl  r0, r1, #31", 0x2, r0, r1, c);
+       TESTCARRYEND
+
+       printf("LSLS immediate\n");
+       TESTCARRY
+       TESTINST2("lsls r0, r1, #0", 0xffffffff, r0, r1, c);
+       TESTINST2("lsls r0, r1, #1", 0xffffffff, r0, r1, c);
+       TESTINST2("lsls r0, r1, #31", 0xffffffff, r0, r1, c);
+       TESTINST2("lsls r0, r1, #0", 0x1, r0, r1, c);
+       TESTINST2("lsls r0, r1, #1", 0x1, r0, r1, c);
+       TESTINST2("lsls r0, r1, #31", 0x1, r0, r1, c);
+       TESTINST2("lsls r0, r1, #31", 0x2, r0, r1, c);
+       TESTCARRYEND
+
+       printf("LSR\n");
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
+
+       printf("LSRS\n");
+       TESTCARRY
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
+       TESTCARRYEND
+
+       printf("LSR immediate\n");
+       TESTINST2("lsr  r0, r1, #0", 0xffffffff, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #1", 0xffffffff, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #31", 0xffffffff, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #32", 0xffffffff, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #16", 0x00010000, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #17", 0x00010000, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #18", 0x00010000, r0, r1, 0);
+
+       printf("LSRS immediate\n");
+       TESTCARRY
+       TESTINST2("lsrs r0, r1, #0", 0xffffffff, r0, r1, c);
+       TESTINST2("lsrs r0, r1, #1", 0xffffffff, r0, r1, c);
+       TESTINST2("lsrs r0, r1, #31", 0xffffffff, r0, r1, c);
+       TESTINST2("lsrs r0, r1, #32", 0xffffffff, r0, r1, c);
+       TESTINST2("lsrs r0, r1, #16", 0x00010000, r0, r1, c);
+       TESTINST2("lsrs r0, r1, #17", 0x00010000, r0, r1, c);
+       TESTINST2("lsrs r0, r1, #18", 0x00010000, r0, r1, c);
+       TESTCARRYEND
+
+       printf("ASR\n");
+       TESTCARRY
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, c);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, c);
+       TESTCARRYEND
+
+       printf("ASRS\n");
+       TESTCARRY
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 256, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, c);
+       TESTCARRYEND
+
+       TESTCARRY
+       TESTINST3("asrs r0, r1, r2", 0x8, 0, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x8, 1, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x8, 2, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x8, 3, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x8, 4, r0, r1, r2, c);
+       TESTINST3("asrs r0, r1, r2", 0x8, 5, r0, r1, r2, c);
+       TESTCARRYEND
+
+       TESTINST3("asrs r0, r1, r2", 0x80000001, 1, r0, r1, r2, 0);
+       TESTINST3("asrs r0, r1, r2", 0x80000001, 2, r0, r1, r2, 0);
+
+       printf("ASR immediate\n");
+       TESTINST2("asr  r0, r1, #0", 0xffffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #1", 0xffffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #31", 0xffffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #32", 0xffffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #0", 0x7fffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #1", 0x7fffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #31", 0x7fffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #32", 0x7fffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #16", 0x00010000, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #17", 0x00010000, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #18", 0x00010000, r0, r1, 0);
+
+       printf("ASRS immediate\n");
+       TESTCARRY
+       TESTINST2("asrs r0, r1, #0", 0xffffffff, r0, r1, c);
+       TESTINST2("asrs r0, r1, #1", 0xffffffff, r0, r1, c);
+       TESTINST2("asrs r0, r1, #31", 0xffffffff, r0, r1, c);
+       TESTINST2("asrs r0, r1, #32", 0xffffffff, r0, r1, c);
+       TESTINST2("asrs r0, r1, #0", 0x7fffffff, r0, r1, c);
+       TESTINST2("asrs r0, r1, #1", 0x7fffffff, r0, r1, c);
+       TESTINST2("asrs r0, r1, #31", 0x7fffffff, r0, r1, c);
+       TESTINST2("asrs r0, r1, #32", 0x7fffffff, r0, r1, c);
+       TESTINST2("asrs r0, r1, #16", 0x00010000, r0, r1, c);
+       TESTINST2("asrs r0, r1, #17", 0x00010000, r0, r1, c);
+       TESTINST2("asrs r0, r1, #18", 0x00010000, r0, r1, c);
+       TESTCARRYEND
+
+       printf("ROR\n");
+       TESTCARRY
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 0, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x80088000, 1, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 1, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 2, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 31, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 32, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 33, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 63, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 64, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 255, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 256, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x80088000, 256, r0, r1, r2, c);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 257, r0, r1, r2, c);
+       TESTCARRYEND
+
+       printf("RORS\n");
+       TESTCARRY
+       TESTINST3("rors r0, r1, r2", 0x00088000, 0, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x80088000, 0, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 1, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 2, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 31, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 32, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 33, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 63, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 64, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 255, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 256, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x80088000, 256, r0, r1, r2, c);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 257, r0, r1, r2, c);
+       TESTCARRYEND
+
+       printf("ROR immediate\n");
+       TESTCARRY
+       TESTINST2("ror  r0, r1, #0", 0x00088000, r0, r1, c);
+       TESTINST2("ror  r0, r1, #1", 0x00088000, r0, r1, c);
+       TESTINST2("ror  r0, r1, #31", 0x00088000, r0, r1, c);
+       TESTINST2("ror  r0, r1, #16", 0x00010000, r0, r1, c);
+       TESTINST2("ror  r0, r1, #17", 0x00010000, r0, r1, c);
+       TESTINST2("ror  r0, r1, #18", 0x00010000, r0, r1, c);
+       TESTCARRYEND
+
+       printf("RORS immediate\n");
+       TESTCARRY
+       TESTINST2("rors r0, r1, #0", 0x00088000, r0, r1, c);
+       TESTINST2("rors r0, r1, #1", 0x00088000, r0, r1, c);
+       TESTINST2("rors r0, r1, #31", 0x00088000, r0, r1, c);
+       TESTINST2("rors r0, r1, #16", 0x00010000, r0, r1, c);
+       TESTINST2("rors r0, r1, #17", 0x00010000, r0, r1, c);
+       TESTINST2("rors r0, r1, #18", 0x00010000, r0, r1, c);
+       TESTCARRYEND
+
+       printf("shift with barrel shifter\n");
+       TESTCARRY
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 0, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 1, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 31, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 32, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 255, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 256, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
+       TESTCARRYEND
+
+       TESTCARRY
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 0, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 1, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 2, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 3, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 4, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 5, r0, r1, r2, r3, c);
+       TESTCARRYEND
+
+       TESTCARRY
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, c);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, c);
+       TESTCARRYEND
+
+       TESTCARRY
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, c);
+
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, c);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, c);
+       TESTCARRYEND
+
+       TESTCARRY
+       TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
+       TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, c);
+       TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
+       TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, c);
+       TESTCARRYEND
+
+       printf("MUL\n");
+       TESTINST3("mul  r0, r1, r2", 0, 0, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
+
+       printf("MULS\n");
+       TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
+
+       printf("MLA\n");
+       TESTINST4("mla  r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
+
+       printf("MLAS\n");
+       TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
+
+       printf("MLS\n");
+       TESTINST4("mls  r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
+
+       printf("UMULL\n");
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+
+       printf("SMULL\n");
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+
+       printf("UMLAL\n");
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+
+       printf("SMLAL\n");
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+
+       printf("CLZ\n");
+       TESTCARRY
+       TESTINST2("clz  r0, r1", 0, r0, r1, c);
+       TESTINST2("clz  r0, r1", 1, r0, r1, c);
+       TESTINST2("clz  r0, r1", 0x10, r0, r1, c);
+       TESTINST2("clz  r0, r1", 0xffffffff, r0, r1, c);
+       TESTCARRYEND
+
+       printf("extend instructions\n");
+       TESTINST2("uxtb r0, r1", 0, r0, r1, 0);
+       TESTINST2("uxtb r0, r1", 1, r0, r1, 0);
+       TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0);
+       TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0);
+       TESTINST2("sxtb r0, r1", 0, r0, r1, 0);
+       TESTINST2("sxtb r0, r1", 1, r0, r1, 0);
+       TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0);
+       TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0);
+
+       TESTINST2("uxth r0, r1", 0, r0, r1, 0);
+       TESTINST2("uxth r0, r1", 1, r0, r1, 0);
+       TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0);
+       TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 1, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0);
+
+       TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0);
+       TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0);
+       TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0);
+       TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0);
+       TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0);
+
+       TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0);
+       TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0);
+       TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0);
+       TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0);
+       TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0);
+
+       printf("------------ BFI ------------\n");
+
+        /* bfi  rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */
+       TESTINST2("bfi  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+       TESTINST2("bfi  r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0);
+
+       TESTINST2("bfi  r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0);
+
+       TESTINST2("bfi  r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0);
+
+       printf("------------ BFC ------------\n");
+
+        /* bfi  rDst, #lsb-in-dst, #number-of-bits-to-copy */
+       TESTINST2("bfc  r0, #0, #11", 0xAAAAAAAA, r0, r1, 0);
+       TESTINST2("bfc  r0, #1, #11", 0xAAAAAAAA, r0, r1, 0);
+       TESTINST2("bfc  r0, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+       TESTINST2("bfc  r0, #19, #11", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #20, #11", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #21, #11", 0xFFFFFFFF, r0, r1, 0);
+
+       TESTINST2("bfc  r0, #0, #32", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #1, #31", 0xFFFFFFFF, r0, r1, 0);
+
+       TESTINST2("bfc  r0, #29, #3", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #30, #2", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #31, #1", 0xFFFFFFFF, r0, r1, 0);
+
+       printf("------------ SBFX ------------\n");
+
+        /* sbfx rDst, rSrc, #lsb, #width */
+        TESTINST2("sbfx  r0, r1, #0, #1", 0x00000000, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #0, #1", 0x00000001, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000000, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000001, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000002, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000003, r0, r1, 0);
+
+        TESTINST2("sbfx  r0, r1, #0, #2", 0x00000000, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #0, #2", 0x00000001, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000000, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000001, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000002, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000003, r0, r1, 0);
+
+        TESTINST2("sbfx  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+        TESTINST2("sbfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+        TESTINST2("sbfx  r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
+
+       printf("------------ UBFX ------------\n");
+
+        /* ubfx rDst, rSrc, #lsb, #width */
+        TESTINST2("ubfx  r0, r1, #0, #1", 0x00000000, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #0, #1", 0x00000001, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000000, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000001, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000002, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000003, r0, r1, 0);
+
+        TESTINST2("ubfx  r0, r1, #0, #2", 0x00000000, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #0, #2", 0x00000001, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000000, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000001, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000002, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000003, r0, r1, 0);
+
+        TESTINST2("ubfx  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+        TESTINST2("ubfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+        TESTINST2("ubfx  r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
+
+       printf("------------ SMULL{B,T}{B,T} ------------\n");
+        /* SMULxx rD, rN, rM */
+
+       TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000,  r0, r1, r2, 0);
+       TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002,  r0, r1, r2, 0);
+       TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff,  r0, r1, r2, 0);
+       TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff,  r0, r1, r2, 0);
+       TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff,  r0, r1, r2, 0);
+
+       printf("------------ SXTAB ------------\n");
+        TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+
+       printf("------------ UXTAB ------------\n");
+        TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+
+       printf("------------ SXTAH ------------\n");
+        TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+
+       printf("------------ UXTAH ------------\n");
+        TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+
+       printf("------------ PLD/PLDW (begin) ------------\n");
+        /* These don't have any effect on the architected state, so,
+           uh, there's no result values to check.  Just _do_ some of
+           them and check Valgrind's instruction decoder eats them up
+           without complaining. */
+        { int alocal;
+          printf("pld  reg +/- imm12  cases\n");
+          __asm__ __volatile__( "pld [%0, #128]" : :/*in*/"r"(&alocal) );
+          __asm__ __volatile__( "pld [%0, #-128]" : :/*in*/"r"(&alocal) );
+          __asm__ __volatile__( "pld [r15, #-128]" : :/*in*/"r"(&alocal) );
+
+          // apparently pldw is v7 only
+          //__asm__ __volatile__( "pldw [%0, #128]" : :/*in*/"r"(&alocal) );
+          //__asm__ __volatile__( "pldw [%0, #-128]" : :/*in*/"r"(&alocal) );
+          //__asm__ __volatile__( "pldw [r15, #128]" : :/*in*/"r"(&alocal) );
+
+          printf("pld  reg +/- shifted reg  cases\n");
+          __asm__ __volatile__( "pld [%0, %1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, LSL #1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, LSR #1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, ASR #1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, ROR #1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, RRX]" : : /*in*/"r"(&alocal), "r"(0) );
+        }
+       printf("------------ PLD/PLDW (done) ------------\n");
+
+
+       return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.stdout.exp
new file mode 100644 (file)
index 0000000..064b526
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.stdout.exp
@@ -0,0 +1,739 @@
+MOV
+mov  r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+cpy  r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+mov  r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+mov  r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000     
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000  Z  
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 0, cpsr 0x80000000 N   
+movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000  Z  
+movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000     
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000  ZC 
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 1, cpsr 0xa0000000 N C 
+movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000  ZC 
+movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 1, cpsr 0x20000000   C 
+MVN
+mvn  r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x00000000     
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x80000000 N   
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 0, cpsr 0x80000000 N   
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 0, cpsr 0x00000000     
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 1, cpsr 0xa0000000 N C 
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, carryin 1, cpsr 0xa0000000 N C 
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, carryin 1, cpsr 0x20000000   C 
+ADD
+adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000  Z  
+adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, carryin 0, cpsr 0x60000000  ZC 
+adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x90000000 N  V
+adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, carryin 0, cpsr 0x30000000   CV
+adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
+ADC
+adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000  Z  
+adcs r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, carryin 1, cpsr 0x00000000     
+LSL
+lsl  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 0, cpsr 0x00000000     
+LSLS
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
+lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x60000000  ZC 
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x80000000 N   
+lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 0, cpsr 0x00000000     
+lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 0, cpsr 0x00000000     
+lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 0, cpsr 0x80000000 N   
+lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 0, cpsr 0x60000000  ZC 
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x60000000  ZC 
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
+lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, carryin 1, cpsr 0x00000000     
+lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, carryin 1, cpsr 0x80000000 N   
+lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, carryin 1, cpsr 0x60000000  ZC 
+LSL immediate
+lsl  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 0, cpsr 0x00000000     
+lsl  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
+lsl  r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
+lsl  r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
+lsl  r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
+lsl  r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 1, cpsr 0x20000000   C 
+LSLS immediate
+lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N   
+lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
+lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
+lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 0, cpsr 0x00000000     
+lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 0, cpsr 0x80000000 N   
+lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 0, cpsr 0x60000000  ZC 
+lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
+lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
+lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
+lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000   C 
+lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, carryin 1, cpsr 0x00000000     
+lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, carryin 1, cpsr 0x80000000 N   
+lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, carryin 1, cpsr 0x60000000  ZC 
+LSR
+lsr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
+LSRS
+lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
+lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x60000000  ZC 
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C 
+lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x60000000  ZC 
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000  Z  
+LSR immediate
+lsr  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
+lsr  r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
+LSRS immediate
+lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N   
+lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 0, cpsr 0x20000000   C 
+lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x20000000   C 
+lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x60000000  ZC 
+lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
+lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x60000000  ZC 
+lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x40000000  Z  
+lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
+lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
+lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
+lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x60000000  ZC 
+lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000     
+lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x60000000  ZC 
+lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x40000000  Z  
+ASR
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 1, cpsr 0x20000000   C 
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
+ASRS
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 0, cpsr 0x80000000 N   
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 0, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 0, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 0, cpsr 0x60000000  ZC 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, carryin 1, cpsr 0x60000000  ZC 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, carryin 1, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, carryin 1, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, carryin 1, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, carryin 1, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, carryin 1, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, carryin 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, carryin 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, carryin 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, carryin 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, carryin 0, cpsr 0x60000000  ZC 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, carryin 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, carryin 1, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, carryin 1, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, carryin 1, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, carryin 1, cpsr 0x60000000  ZC 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, carryin 1, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0xc0000000 rm 0x80000001, rn 0x00000001, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xe0000000 rm 0x80000001, rn 0x00000002, carryin 0, cpsr 0x80000000 N   
+ASR immediate
+asr  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
+asr  r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
+ASRS immediate
+asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x80000000 N   
+asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0xa0000000 N C 
+asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 0, cpsr 0x00000000     
+asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 0, cpsr 0x20000000   C 
+asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x60000000  ZC 
+asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 0, cpsr 0x40000000  Z  
+asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
+asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x60000000  ZC 
+asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 0, cpsr 0x40000000  Z  
+asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, carryin 1, cpsr 0xa0000000 N C 
+asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, carryin 1, cpsr 0x20000000   C 
+asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, carryin 1, cpsr 0x20000000   C 
+asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, carryin 1, cpsr 0x60000000  ZC 
+asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, carryin 1, cpsr 0x40000000  Z  
+asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000     
+asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x60000000  ZC 
+asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, carryin 1, cpsr 0x40000000  Z  
+ROR
+ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x40044000 rm 0x80088000, rn 0x00000001, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 0, cpsr 0x00000000     
+ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x40044000 rm 0x80088000, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 1, cpsr 0x20000000   C 
+RORS
+rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 0, cpsr 0x80000000 N   
+rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 0, cpsr 0x80000000 N   
+rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 0, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000000, carryin 1, cpsr 0x20000000   C 
+rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000000, carryin 1, cpsr 0xa0000000 N C 
+rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000001, carryin 1, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00022000 rm 0x00088000, rn 0x00000002, carryin 1, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000001f, carryin 1, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000020, carryin 1, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000021, carryin 1, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x0000003f, carryin 1, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000040, carryin 1, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00110000 rm 0x00088000, rn 0x000000ff, carryin 1, cpsr 0x00000000     
+rors r0, r1, r2 :: rd 0x00088000 rm 0x00088000, rn 0x00000100, carryin 1, cpsr 0x20000000   C 
+rors r0, r1, r2 :: rd 0x80088000 rm 0x80088000, rn 0x00000100, carryin 1, cpsr 0xa0000000 N C 
+rors r0, r1, r2 :: rd 0x00044000 rm 0x00088000, rn 0x00000101, carryin 1, cpsr 0x00000000     
+ROR immediate
+ror  r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 0, cpsr 0x00000000     
+ror  r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 0, cpsr 0x00000000     
+ror  r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 0, cpsr 0x00000000     
+ror  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
+ror  r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
+ror  r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
+ror  r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 1, cpsr 0x20000000   C 
+ror  r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 1, cpsr 0x20000000   C 
+RORS immediate
+rors r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 0, cpsr 0x00000000     
+rors r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 0, cpsr 0x00000000     
+rors r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 0, cpsr 0x00000000     
+rors r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 0, cpsr 0x00000000     
+rors r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 0, cpsr 0xa0000000 N C 
+rors r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 0, cpsr 0x00000000     
+rors r0, r1, #0 :: rd 0x00088000 rm 0x00088000, carryin 1, cpsr 0x20000000   C 
+rors r0, r1, #1 :: rd 0x00044000 rm 0x00088000, carryin 1, cpsr 0x00000000     
+rors r0, r1, #31 :: rd 0x00110000 rm 0x00088000, carryin 1, cpsr 0x00000000     
+rors r0, r1, #16 :: rd 0x00000001 rm 0x00010000, carryin 1, cpsr 0x00000000     
+rors r0, r1, #17 :: rd 0x80000000 rm 0x00010000, carryin 1, cpsr 0xa0000000 N C 
+rors r0, r1, #18 :: rd 0x40000000 rm 0x00010000, carryin 1, cpsr 0x00000000     
+shift with barrel shifter
+add  r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000000, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x3fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x0000001f, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x00000020, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x000000ff, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000100, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000000, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x3fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000001, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x0000001f, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x00000020, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x7fffffff rs 0x000000ff, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x7fffffff rm 0x00000000, rn 0x7fffffff rs 0x00000100, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000008 rm 0x00000000, rn 0x00000008 rs 0x00000000, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000004 rm 0x00000000, rn 0x00000008 rs 0x00000001, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000002 rm 0x00000000, rn 0x00000008 rs 0x00000002, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000008 rs 0x00000003, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000004, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000005, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, asr r3 :: rd 0x00000008 rm 0x00000000, rn 0x00000008 rs 0x00000000, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000004 rm 0x00000000, rn 0x00000008 rs 0x00000001, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000002 rm 0x00000000, rn 0x00000008 rs 0x00000002, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000008 rs 0x00000003, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000004, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, asr r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000008 rs 0x00000005, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 0, cpsr 0x00000000     
+add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 1, cpsr 0x20000000   C 
+add  r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 1, cpsr 0x20000000   C 
+adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x40000000  Z  
+adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x40000000  Z  
+adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 0, cpsr 0x40000000  Z  
+adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 0, cpsr 0x40000000  Z  
+adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 0, cpsr 0x80000000 N   
+adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 0, cpsr 0x00000000     
+adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x80000000 N   
+adds r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x80000000 N   
+adds r0, r1, r2, lsl r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x80000000 N   
+adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x40000000  Z  
+adds r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x40000000  Z  
+adds r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x80000000 N   
+adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x80000000 N   
+adds r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x00000000     
+adds r0, r1, r2, lsr r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x0000001f, carryin 1, cpsr 0x00000000     
+adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000020, carryin 1, cpsr 0x40000000  Z  
+adds r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x000000ff, carryin 1, cpsr 0x40000000  Z  
+adds r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000100, carryin 1, cpsr 0x80000000 N   
+adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000000, carryin 1, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000000, carryin 1, cpsr 0x80000000 N   
+adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000001, carryin 1, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x0000001f, carryin 1, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000020, carryin 1, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x00110000 rm 0x00000000, rn 0x00088000 rs 0x000000ff, carryin 1, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x00088000 rm 0x00000000, rn 0x00088000 rs 0x00000100, carryin 1, cpsr 0x00000000     
+adds r0, r1, r2, ror r3 :: rd 0x80088000 rm 0x00000000, rn 0x80088000 rs 0x00000100, carryin 1, cpsr 0x80000000 N   
+adds r0, r1, r2, ror r3 :: rd 0x00044000 rm 0x00000000, rn 0x00088000 rs 0x00000101, carryin 1, cpsr 0x00000000     
+adcs r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N   
+adcs r0, r1, r2, lsr r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 0, cpsr 0x80000000 N   
+adcs r0, r1, r2, lsl r3 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x80000000 N   
+adcs r0, r1, r2, lsr r3 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+adcs r0, r1, r2, lsl r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x60000000  ZC 
+adcs r0, r1, r2, lsr r3 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff rs 0x00000000, carryin 1, cpsr 0x60000000  ZC 
+adcs r0, r1, r2, lsl r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x80000000 N   
+adcs r0, r1, r2, lsr r3 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 1, cpsr 0x90000000 N  V
+MUL
+mul  r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000     
+mul  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000     
+mul  r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000     
+mul  r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000     
+mul  r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000     
+mul  r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000     
+MULS
+muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x40000000  Z  
+muls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x40000000  Z  
+muls r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x40000000  Z  
+muls r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000     
+muls r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000     
+muls r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x80000000 N   
+MLA
+mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mla  r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mla  r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mla  r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+MLAS
+mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+mlas r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mlas r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mlas r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mlas r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x80000000 N   
+MLS
+mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mls  r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mls  r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+mls  r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, carryin 0, cpsr 0x00000000     
+UMULL
+umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000     
+umull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+umull  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
+umull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
+umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
+umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000  Z  
+umulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
+umulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+umulls r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
+umulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x80000000 N   
+SMULL
+smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000     
+smull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+smull  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
+smull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
+smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
+smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000  Z  
+smulls r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
+smulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+smulls r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
+smulls r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
+UMLAL
+umlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+umlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+umlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+umlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+umlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+umlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000     
+umlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+umlal  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
+umlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
+umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
+umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x80000000 N   
+umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000  Z  
+umlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
+umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+umlals r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
+umlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x80000000 N   
+SMLAL
+smlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+smlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+smlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+smlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+smlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000     
+smlal  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x00000000     
+smlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+smlal  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
+smlal  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
+smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
+smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000001, rm 0x00000000 rs 0x00000000, carryin 0, cpsr 0x00000000     
+smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0xffffffff, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x80000000 N   
+smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, carryin 0, cpsr 0x40000000  Z  
+smlals r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, carryin 0, cpsr 0x40000000  Z  
+smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, carryin 0, cpsr 0x00000000     
+smlals r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, carryin 0, cpsr 0x00000000     
+smlals r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, carryin 0, cpsr 0x00000000     
+CLZ
+clz  r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 0, cpsr 0x00000000     
+clz  r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 0, cpsr 0x00000000     
+clz  r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 0, cpsr 0x00000000     
+clz  r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+clz  r0, r1 :: rd 0x00000020 rm 0x00000000, carryin 1, cpsr 0x20000000   C 
+clz  r0, r1 :: rd 0x0000001f rm 0x00000001, carryin 1, cpsr 0x20000000   C 
+clz  r0, r1 :: rd 0x0000001b rm 0x00000010, carryin 1, cpsr 0x20000000   C 
+clz  r0, r1 :: rd 0x00000000 rm 0xffffffff, carryin 1, cpsr 0x20000000   C 
+extend instructions
+uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000     
+uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, carryin 0, cpsr 0x00000000     
+sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+uxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+uxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, carryin 0, cpsr 0x00000000     
+uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+sxth r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+sxth r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, carryin 0, cpsr 0x00000000     
+sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, carryin 0, cpsr 0x00000000     
+sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, carryin 0, cpsr 0x00000000     
+sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, carryin 0, cpsr 0x00000000     
+sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, carryin 0, cpsr 0x00000000     
+uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, carryin 0, cpsr 0x00000000     
+uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, carryin 0, cpsr 0x00000000     
+uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, carryin 0, cpsr 0x00000000     
+uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, carryin 0, cpsr 0x00000000     
+uxtb16 r0, r1 :: rd 0x00ff00ff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+uxtb16 r0, r1, ror #16 :: rd 0x00ff0000 rm 0x0000ffff, carryin 0, cpsr 0x00000000     
+sxtb16 r0, r1 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+sxtb16 r0, r1 :: rd 0xffffffff rm 0x00ff00ff, carryin 0, cpsr 0x00000000     
+sxtb16 r0, r1 :: rd 0x007f007f rm 0x007f007f, carryin 0, cpsr 0x00000000     
+------------ BFI ------------
+bfi  r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfi  r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+------------ BFC ------------
+bfc  r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+bfc  r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+bfc  r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+bfc  r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfc  r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfc  r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfc  r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfc  r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfc  r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfc  r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+bfc  r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, carryin 0, cpsr 0x00000000     
+------------ SBFX ------------
+sbfx  r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+sbfx  r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+------------ UBFX ------------
+ubfx  r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+ubfx  r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, carryin 0, cpsr 0x00000000     
+------------ SMULL{B,T}{B,T} ------------
+smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, carryin 0, cpsr 0x00000000     
+smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, carryin 0, cpsr 0x00000000     
+smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, carryin 0, cpsr 0x00000000     
+smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, carryin 0, cpsr 0x00000000     
+smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, carryin 0, cpsr 0x00000000     
+------------ SXTAB ------------
+sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
+sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
+sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
+sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
+------------ UXTAB ------------
+uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
+uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
+uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
+uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, carryin 0, cpsr 0x00000000     
+------------ SXTAH ------------
+sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+sxtah r0, r1, r2, ROR #8  :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+sxtah r0, r1, r2, ROR #0  :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
+sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
+sxtah r0, r1, r2, ROR #8  :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
+sxtah r0, r1, r2, ROR #0  :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
+------------ UXTAH ------------
+uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+uxtah r0, r1, r2, ROR #8  :: rd 0x3141714f rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+uxtah r0, r1, r2, ROR #0  :: rd 0x31418140 rm 0x31415927, rn 0x27182819, carryin 0, cpsr 0x00000000     
+uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
+uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
+uxtah r0, r1, r2, ROR #8  :: rd 0x314171bf rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
+uxtah r0, r1, r2, ROR #0  :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, carryin 0, cpsr 0x00000000     
+------------ PLD/PLDW (begin) ------------
+pld  reg +/- imm12  cases
+pld  reg +/- shifted reg  cases
+------------ PLD/PLDW (done) ------------

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.vgtest
new file mode 100644 (file)
index 0000000..b2489f2
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intARM.vgtest
@@ -0,0 +1,2 @@
+prog: v6intARM
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.c
new file mode 100644 (file)
index 0000000..a1961e8
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.c
@@ -0,0 +1,5403 @@
+
+/* How to compile:
+   gcc -O -g -Wall -mcpu=cortex-a8 -o testarmv6int testarmv6int.c
+*/
+
+#include <stdio.h>
+
+static int gen_cvin(cvin)
+{
+  int r = ((cvin & 2) ? (1<<29) : 0) | ((cvin & 1) ? (1<<28) : 0);
+  r |= (1 << 31) | (1 << 30);
+  return r;
+}
+
+/* test macros to generate and output the result of a single instruction */
+
+
+// 1 registers in the insn, zero args: rD = op()
+#define TESTINST1(instruction, RD, cvin) \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+                "msr cpsr_f, %2;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (gen_cvin(cvin))        \
+               : #RD, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, \
+               cvin, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+
+
+// 1 registers in the insn, one args: rD = op(rD)
+#define TESTINST1x(instruction, RDval, RD, cvin)       \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+                "msr cpsr_f, %2;" \
+                "mov " #RD ",%3;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (gen_cvin(cvin)), "r"(RDval) \
+               : #RD, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, \
+               cvin, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+// 2 registers in the insn, one arg: rD = op(rM)
+#define TESTINST2(instruction, RMval, RD, RM, cvin) \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+                "msr cpsr_f, %3;" \
+               "mov " #RM ",%2;" \
+                /* set #RD to 0x55555555 so we can see which parts get overwritten */ \
+                "mov " #RD ", #0x55" "\n\t" \
+                "orr " #RD "," #RD "," #RD ", LSL #8" "\n\t" \
+                "orr " #RD "," #RD "," #RD ", LSL #16" "\n\t" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (RMval), "r" (gen_cvin(cvin))        \
+               : #RD, #RM, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, RMval, \
+               cvin, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+
+// 2 registers in the insn, two args: rD = op(rD, rM)
+#define TESTINST2x(instruction, RDval, RMval, RD, RM, cvin)       \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+                "msr cpsr_f, %3;" \
+               "mov " #RM ",%2;" \
+                "mov " #RD ",%4;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (RMval), "r" (gen_cvin(cvin)), "r"(RDval) \
+               : #RD, #RM, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rm 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, RMval, \
+               cvin, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+
+
+#define TESTINST3(instruction, RMval, RNval, RD, RM, RN, cvin) \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+                "msr cpsr_f, %4;" \
+               "mov " #RM ",%2;" \
+               "mov " #RN ",%3;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (RMval), "r" (RNval), "r" (gen_cvin(cvin))    \
+               : #RD, #RM, #RN, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, RMval, RNval, \
+               cvin, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+#define TESTINST4(instruction, RMval, RNval, RSval, RD, RM, RN, RS, cvin) \
+{ \
+       unsigned int out; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+                "msr cpsr_f, %5;" \
+               "mov " #RM ",%2;" \
+               "mov " #RN ",%3;" \
+               "mov " #RS ",%4;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mrs %1,cpsr;" \
+               : "=&r" (out), "=&r" (cpsr) \
+               : "r" (RMval), "r" (RNval), "r" (RSval), "r" (gen_cvin(cvin)) \
+               : #RD, #RM, #RN, #RS, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rm 0x%08x, rn 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, RMval, RNval, RSval, \
+               cvin, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+#define TESTINST4_2OUT(instruction, RDval, RD2val, RMval, RSval, RD, RD2, RM, RS, cvin) \
+{ \
+       unsigned int out; \
+       unsigned int out2; \
+       unsigned int cpsr; \
+\
+       __asm__ volatile( \
+                "msr cpsr_f, %7;" \
+               "mov " #RD ",%3;" \
+               "mov " #RD2 ",%4;" \
+               "mov " #RM ",%5;" \
+               "mov " #RS ",%6;" \
+               instruction ";" \
+               "mov %0," #RD ";" \
+               "mov %1," #RD2 ";" \
+               "mrs %2,cpsr;" \
+               : "=&r" (out), "=&r" (out2), "=&r" (cpsr) \
+               : "r" (RDval), "r" (RD2val), "r" (RMval), "r" (RSval), "r" (gen_cvin(cvin)) \
+               : #RD, #RD2, #RM, #RS, "cc", "memory" \
+       ); \
+       printf("%s :: rd 0x%08x rd2 0x%08x, rm 0x%08x rs 0x%08x, c:v-in %d, cpsr 0x%08x %c%c%c%c\n", \
+               instruction, out, out2, RMval, RSval, \
+               cvin, \
+               cpsr & 0xffff0000, \
+               ((1<<31) & cpsr) ? 'N' : ' ', \
+               ((1<<30) & cpsr) ? 'Z' : ' ', \
+               ((1<<29) & cpsr) ? 'C' : ' ', \
+               ((1<<28) & cpsr) ? 'V' : ' ' \
+               ); \
+}
+
+/* helpers */
+#define NOCARRY { int cv = 0; {
+#define TESTCARRY { int cv = 0; for (cv = 0; cv < 4; cv++) {
+#define TESTCARRYEND }}
+
+////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////
+
+static int old_main(void)
+{
+
+       printf("MOV\n");
+       TESTINST2("mov  r0, r1", 1, r0, r1, 0);
+       TESTINST2("cpy  r0, r1", 1, r0, r1, 0);
+       TESTINST2("mov  r0, #0", 0, r0, r1, 0);
+       TESTINST2("mov  r0, #1", 0, r0, r1, 0);
+       TESTCARRY
+       TESTINST2("movs r0, r1", 1, r0, r1, cv);
+       TESTINST2("movs r0, r1", 0, r0, r1, cv);
+       TESTINST2("movs r0, r1", 0x80000000, r0, r1, cv);
+       TESTINST2("movs r0, #0", 0, r0, r1, cv);
+       TESTINST2("movs r0, #1", 0, r0, r1, cv);
+       TESTCARRYEND
+
+       printf("MVN\n");
+       TESTINST2("mvn  r0, r1", 1, r0, r1, 0);
+       TESTCARRY
+       TESTINST2("mvns r0, r1", 1, r0, r1, cv);
+       TESTINST2("mvns r0, r1", 0, r0, r1, cv);
+       TESTINST2("mvns r0, r1", 0x80000000, r0, r1, cv);
+       TESTCARRYEND
+
+       printf("ADD\n");
+       TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 1, -1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0x80000000, -1, r0, r1, r2, 0);
+       TESTINST3("adds r0, r1, r2", 0x80000000, 0, r0, r1, r2, 0);
+
+       printf("ADC\n");
+       TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 0);
+       TESTINST3("adcs r0, r1, r2", 0, 0, r0, r1, r2, 1);
+
+       printf("LSL\n");
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
+
+       TESTINST3("lsl  r0, r1, r2", 0x1, 0, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0x1, 1, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0x1, 31, r0, r1, r2, 0);
+       TESTINST3("lsl  r0, r1, r2", 0x2, 31, r0, r1, r2, 0);
+
+       printf("LSLS\n");
+       TESTCARRY
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0x1, 0, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0x1, 1, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0x1, 31, r0, r1, r2, cv);
+       TESTINST3("lsls r0, r1, r2", 0x2, 31, r0, r1, r2, cv);
+       TESTCARRYEND
+
+       printf("LSL immediate\n");
+       TESTCARRY
+       TESTINST2("lsl  r0, r1, #0", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsl  r0, r1, #1", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsl  r0, r1, #31", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsl  r0, r1, #0", 0x1, r0, r1, cv);
+       TESTINST2("lsl  r0, r1, #1", 0x1, r0, r1, cv);
+       TESTINST2("lsl  r0, r1, #31", 0x1, r0, r1, cv);
+       TESTINST2("lsl  r0, r1, #31", 0x2, r0, r1, cv);
+       TESTCARRYEND
+
+       printf("LSLS immediate\n");
+       TESTCARRY
+       TESTINST2("lsls r0, r1, #0", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsls r0, r1, #1", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsls r0, r1, #31", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsls r0, r1, #0", 0x1, r0, r1, cv);
+       TESTINST2("lsls r0, r1, #1", 0x1, r0, r1, cv);
+       TESTINST2("lsls r0, r1, #31", 0x1, r0, r1, cv);
+       TESTINST2("lsls r0, r1, #31", 0x2, r0, r1, cv);
+       TESTCARRYEND
+
+       printf("LSR\n");
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, 0);
+       TESTINST3("lsr  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, 0);
+
+       printf("LSRS\n");
+       TESTCARRY
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv);
+       TESTINST3("lsrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv);
+       TESTCARRYEND
+
+       printf("LSR immediate\n");
+       TESTINST2("lsr  r0, r1, #0", 0xffffffff, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #1", 0xffffffff, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #31", 0xffffffff, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #32", 0xffffffff, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #16", 0x00010000, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #17", 0x00010000, r0, r1, 0);
+       TESTINST2("lsr  r0, r1, #18", 0x00010000, r0, r1, 0);
+
+       printf("LSRS immediate\n");
+       TESTCARRY
+       TESTINST2("lsrs r0, r1, #0", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsrs r0, r1, #1", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsrs r0, r1, #31", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsrs r0, r1, #32", 0xffffffff, r0, r1, cv);
+       TESTINST2("lsrs r0, r1, #16", 0x00010000, r0, r1, cv);
+       TESTINST2("lsrs r0, r1, #17", 0x00010000, r0, r1, cv);
+       TESTINST2("lsrs r0, r1, #18", 0x00010000, r0, r1, cv);
+       TESTCARRYEND
+
+       printf("ASR\n");
+       TESTCARRY
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, cv);
+       TESTINST3("asr  r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, cv);
+       TESTCARRYEND
+
+       printf("ASRS\n");
+       TESTCARRY
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 0, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 1, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 2, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 31, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 32, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 33, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 63, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 64, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 255, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0xffffffff, 256, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 0, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 1, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 2, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 31, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 32, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 33, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 63, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 64, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 255, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x7fffffff, 256, r0, r1, r2, cv);
+       TESTCARRYEND
+
+       TESTCARRY
+       TESTINST3("asrs r0, r1, r2", 0x8, 0, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x8, 1, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x8, 2, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x8, 3, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x8, 4, r0, r1, r2, cv);
+       TESTINST3("asrs r0, r1, r2", 0x8, 5, r0, r1, r2, cv);
+       TESTCARRYEND
+
+       TESTINST3("asrs r0, r1, r2", 0x80000001, 1, r0, r1, r2, 0);
+       TESTINST3("asrs r0, r1, r2", 0x80000001, 2, r0, r1, r2, 0);
+
+       printf("ASR immediate\n");
+       TESTINST2("asr  r0, r1, #0", 0xffffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #1", 0xffffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #31", 0xffffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #32", 0xffffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #0", 0x7fffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #1", 0x7fffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #31", 0x7fffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #32", 0x7fffffff, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #16", 0x00010000, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #17", 0x00010000, r0, r1, 0);
+       TESTINST2("asr  r0, r1, #18", 0x00010000, r0, r1, 0);
+
+       printf("ASRS immediate\n");
+       TESTCARRY
+       TESTINST2("asrs r0, r1, #0", 0xffffffff, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #1", 0xffffffff, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #31", 0xffffffff, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #32", 0xffffffff, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #0", 0x7fffffff, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #1", 0x7fffffff, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #31", 0x7fffffff, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #32", 0x7fffffff, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #16", 0x00010000, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #17", 0x00010000, r0, r1, cv);
+       TESTINST2("asrs r0, r1, #18", 0x00010000, r0, r1, cv);
+       TESTCARRYEND
+
+#if 0
+       printf("ROR\n");
+       TESTCARRY
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 0, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x80088000, 1, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 1, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 2, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 31, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 32, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 33, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 63, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 64, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 255, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 256, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x80088000, 256, r0, r1, r2, cv);
+       TESTINST3("ror  r0, r1, r2", 0x00088000, 257, r0, r1, r2, cv);
+       TESTCARRYEND
+
+       printf("RORS\n");
+       TESTCARRY
+       TESTINST3("rors r0, r1, r2", 0x00088000, 0, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x80088000, 0, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 1, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 2, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 31, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 32, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 33, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 63, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 64, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 255, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 256, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x80088000, 256, r0, r1, r2, cv);
+       TESTINST3("rors r0, r1, r2", 0x00088000, 257, r0, r1, r2, cv);
+       TESTCARRYEND
+
+       printf("ROR immediate\n");
+       TESTCARRY
+       TESTINST2("ror  r0, r1, #0", 0x00088000, r0, r1, cv);
+       TESTINST2("ror  r0, r1, #1", 0x00088000, r0, r1, cv);
+       TESTINST2("ror  r0, r1, #31", 0x00088000, r0, r1, cv);
+       TESTINST2("ror  r0, r1, #16", 0x00010000, r0, r1, cv);
+       TESTINST2("ror  r0, r1, #17", 0x00010000, r0, r1, cv);
+       TESTINST2("ror  r0, r1, #18", 0x00010000, r0, r1, cv);
+       TESTCARRYEND
+
+       printf("RORS immediate\n");
+       TESTCARRY
+       TESTINST2("rors r0, r1, #0", 0x00088000, r0, r1, cv);
+       TESTINST2("rors r0, r1, #1", 0x00088000, r0, r1, cv);
+       TESTINST2("rors r0, r1, #31", 0x00088000, r0, r1, cv);
+       TESTINST2("rors r0, r1, #16", 0x00010000, r0, r1, cv);
+       TESTINST2("rors r0, r1, #17", 0x00010000, r0, r1, cv);
+       TESTINST2("rors r0, r1, #18", 0x00010000, r0, r1, cv);
+       TESTCARRYEND
+#endif
+#if 0
+       printf("shift with barrel shifter\n");
+       TESTCARRY
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 0, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 1, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 31, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 32, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 255, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x7fffffff, 256, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
+       TESTCARRYEND
+
+       TESTCARRY
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 0, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 1, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 2, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 3, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 4, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, asr r3", 0, 0x8, 5, r0, r1, r2, r3, cv);
+       TESTCARRYEND
+
+       TESTCARRY
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, cv);
+       TESTINST4("add  r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, cv);
+       TESTCARRYEND
+#endif
+#if 0
+       TESTCARRY
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsl r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 31, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 32, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 255, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, lsr r3", 0, 0xffffffff, 256, r0, r1, r2, r3, cv);
+
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 0, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 0, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 1, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 31, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 32, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 255, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 256, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x80088000, 256, r0, r1, r2, r3, cv);
+       TESTINST4("adds r0, r1, r2, ror r3", 0, 0x00088000, 257, r0, r1, r2, r3, cv);
+       TESTCARRYEND
+#endif
+
+#if 0
+       TESTCARRY
+       TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
+       TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 0, r0, r1, r2, r3, cv);
+       TESTINST4("adcs r0, r1, r2, lsl r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
+       TESTINST4("adcs r0, r1, r2, lsr r3", 0, 0xffffffff, 1, r0, r1, r2, r3, cv);
+       TESTCARRYEND
+#endif
+
+       printf("MUL\n");
+       TESTINST3("mul  r0, r1, r2", 0, 0, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
+       TESTINST3("mul  r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
+
+#if 0
+       printf("MULS\n");
+       TESTINST3("muls r0, r1, r2", 0, 0, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0xffffffff, 0, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0, 0xffffffff, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0xffffffff, 0xffffffff, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0x7fffffff, 0x7fffffff, r0, r1, r2, 0);
+       TESTINST3("muls r0, r1, r2", 0x0000ffff, 0x0000ffff, r0, r1, r2, 0);
+#endif
+
+       printf("MLA\n");
+       TESTINST4("mla  r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mla  r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
+
+#if 0
+       printf("MLAS\n");
+       TESTINST4("mlas r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mlas r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
+#endif
+
+       printf("MLS\n");
+       TESTINST4("mls  r0, r1, r2, r3", 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0xffffffff, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0xffffffff, 0xffffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0x7fffffff, 0x7fffffff, 1, r0, r1, r2, r3, 0);
+       TESTINST4("mls  r0, r1, r2, r3", 0x0000ffff, 0x0000ffff, 1, r0, r1, r2, r3, 0);
+
+       printf("UMULL\n");
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umull  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+#if 0
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+#endif
+       printf("SMULL\n");
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smull  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+#if 0
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smulls r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+#endif
+
+#if 0
+       printf("UMLAL\n");
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlal  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+#endif
+#if 0
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("umlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+#endif
+#if 0
+       printf("SMLAL\n");
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlal  r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+#endif
+#if 0
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 1, 1, 0, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0xffffffff, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 0, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 1, 1, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffff, 0xffff, r0, r1, r2, r3, 0);
+       TESTINST4_2OUT("smlals r0, r1, r2, r3", 0, 0, 0xffffffff, 0xffffffff, r0, r1, r2, r3, 0);
+#endif
+       printf("CLZ\n");
+       TESTCARRY
+       TESTINST2("clz  r0, r1", 0, r0, r1, cv);
+       TESTINST2("clz  r0, r1", 1, r0, r1, cv);
+       TESTINST2("clz  r0, r1", 0x10, r0, r1, cv);
+       TESTINST2("clz  r0, r1", 0xffffffff, r0, r1, cv);
+       TESTCARRYEND
+
+       printf("extend instructions\n");
+       TESTINST2("uxtb r0, r1", 0, r0, r1, 0);
+       TESTINST2("uxtb r0, r1", 1, r0, r1, 0);
+       TESTINST2("uxtb r0, r1", 0xff, r0, r1, 0);
+       TESTINST2("uxtb r0, r1", 0xffffffff, r0, r1, 0);
+       TESTINST2("sxtb r0, r1", 0, r0, r1, 0);
+       TESTINST2("sxtb r0, r1", 1, r0, r1, 0);
+       TESTINST2("sxtb r0, r1", 0xff, r0, r1, 0);
+       TESTINST2("sxtb r0, r1", 0xffffffff, r0, r1, 0);
+
+       TESTINST2("uxth r0, r1", 0, r0, r1, 0);
+       TESTINST2("uxth r0, r1", 1, r0, r1, 0);
+       TESTINST2("uxth r0, r1", 0xffff, r0, r1, 0);
+       TESTINST2("uxth r0, r1", 0xffffffff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 1, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0x7fff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0xffff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0x10ffff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0x107fff, r0, r1, 0);
+       TESTINST2("sxth r0, r1", 0xffffffff, r0, r1, 0);
+
+       TESTINST2("uxtb r0, r1, ror #0", 0x000000ff, r0, r1, 0);
+       TESTINST2("uxtb r0, r1, ror #8", 0x000000ff, r0, r1, 0);
+       TESTINST2("uxtb r0, r1, ror #8", 0x0000ff00, r0, r1, 0);
+       TESTINST2("uxtb r0, r1, ror #16", 0x00ff0000, r0, r1, 0);
+       TESTINST2("uxtb r0, r1, ror #24", 0xff000000, r0, r1, 0);
+#if 0
+       TESTINST2("uxtb16 r0, r1", 0xffffffff, r0, r1, 0);
+       TESTINST2("uxtb16 r0, r1, ror #16", 0x0000ffff, r0, r1, 0);
+       TESTINST2("sxtb16 r0, r1", 0xffffffff, r0, r1, 0);
+       TESTINST2("sxtb16 r0, r1", 0x00ff00ff, r0, r1, 0);
+       TESTINST2("sxtb16 r0, r1", 0x007f007f, r0, r1, 0);
+#endif
+       printf("------------ BFI ------------\n");
+
+        /* bfi  rDst, rSrc, #lsb-in-dst, #number-of-bits-to-copy */
+       TESTINST2("bfi  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+       TESTINST2("bfi  r0, r1, #19, #11", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #20, #11", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #21, #11", 0xFFFFFFFF, r0, r1, 0);
+
+       TESTINST2("bfi  r0, r1, #0, #32", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #1, #31", 0xFFFFFFFF, r0, r1, 0);
+
+       TESTINST2("bfi  r0, r1, #29, #3", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #30, #2", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfi  r0, r1, #31, #1", 0xFFFFFFFF, r0, r1, 0);
+
+       printf("------------ BFC ------------\n");
+
+        /* bfi  rDst, #lsb-in-dst, #number-of-bits-to-copy */
+       TESTINST2("bfc  r0, #0, #11", 0xAAAAAAAA, r0, r1, 0);
+       TESTINST2("bfc  r0, #1, #11", 0xAAAAAAAA, r0, r1, 0);
+       TESTINST2("bfc  r0, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+       TESTINST2("bfc  r0, #19, #11", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #20, #11", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #21, #11", 0xFFFFFFFF, r0, r1, 0);
+
+       TESTINST2("bfc  r0, #0, #32", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #1, #31", 0xFFFFFFFF, r0, r1, 0);
+
+       TESTINST2("bfc  r0, #29, #3", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #30, #2", 0xFFFFFFFF, r0, r1, 0);
+       TESTINST2("bfc  r0, #31, #1", 0xFFFFFFFF, r0, r1, 0);
+
+       printf("------------ SBFX ------------\n");
+
+        /* sbfx rDst, rSrc, #lsb, #width */
+        TESTINST2("sbfx  r0, r1, #0, #1", 0x00000000, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #0, #1", 0x00000001, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000000, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000001, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000002, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #1", 0x00000003, r0, r1, 0);
+
+        TESTINST2("sbfx  r0, r1, #0, #2", 0x00000000, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #0, #2", 0x00000001, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000000, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000001, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000002, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #2", 0x00000003, r0, r1, 0);
+
+        TESTINST2("sbfx  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+        TESTINST2("sbfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+        TESTINST2("sbfx  r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("sbfx  r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
+
+       printf("------------ UBFX ------------\n");
+
+        /* ubfx rDst, rSrc, #lsb, #width */
+        TESTINST2("ubfx  r0, r1, #0, #1", 0x00000000, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #0, #1", 0x00000001, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000000, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000001, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000002, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #1", 0x00000003, r0, r1, 0);
+
+        TESTINST2("ubfx  r0, r1, #0, #2", 0x00000000, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #0, #2", 0x00000001, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000000, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000001, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000002, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #2", 0x00000003, r0, r1, 0);
+
+        TESTINST2("ubfx  r0, r1, #0, #11", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #1, #11", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+        TESTINST2("ubfx  r0, r1, #2, #11", 0xAAAAAAAA, r0, r1, 0);
+
+        TESTINST2("ubfx  r0, r1, #31, #1", 0xAAAAAAAA, r0, r1, 0);
+        TESTINST2("ubfx  r0, r1, #30, #2", 0xAAAAAAAA, r0, r1, 0);
+
+       printf("------------ SMULL{B,T}{B,T} ------------\n");
+        /* SMULxx rD, rN, rM */
+
+       TESTINST3("smulbb r0, r1, r2", 0x00030000, 0x00040000,  r0, r1, r2, 0);
+       TESTINST3("smulbb r0, r1, r2", 0x00030001, 0x00040002,  r0, r1, r2, 0);
+       TESTINST3("smulbb r0, r1, r2", 0x00038001, 0x00047fff,  r0, r1, r2, 0);
+       TESTINST3("smulbb r0, r1, r2", 0x00037fff, 0x00047fff,  r0, r1, r2, 0);
+       TESTINST3("smulbb r0, r1, r2", 0x0003ffff, 0x0004ffff,  r0, r1, r2, 0);
+
+       printf("------------ SXTAB ------------\n");
+        TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("sxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+#if 0
+       printf("------------ SXTAB16 ------------\n");
+        TESTINST3("sxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("sxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+#endif
+       printf("------------ UXTAB ------------\n");
+        TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("uxtab r0, r1, r2, ROR #24", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #16", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #8", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab r0, r1, r2, ROR #0", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+#if 0
+       printf("------------ UXTAB16 ------------\n");
+        TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("uxtab16 r0, r1, r2, ROR #24", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab16 r0, r1, r2, ROR #16", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab16 r0, r1, r2, ROR #8", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtab16 r0, r1, r2, ROR #0", 0x31415927, 0x27182899, 
+                  r0, r1, r2, 0);
+#endif
+       printf("------------ SXTAH ------------\n");
+        TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("sxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("sxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+
+       printf("------------ UXTAH ------------\n");
+        TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27182819, 
+                  r0, r1, r2, 0);
+
+        TESTINST3("uxtah r0, r1, r2, ROR #24", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #16", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #8 ", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+        TESTINST3("uxtah r0, r1, r2, ROR #0 ", 0x31415927, 0x27189819, 
+                  r0, r1, r2, 0);
+#if 0
+       printf("------------ PLD/PLDW (begin) ------------\n");
+        /* These don't have any effect on the architected state, so,
+           uh, there's no result values to check.  Just _do_ some of
+           them and check Valgrind's instruction decoder eats them up
+           without complaining. */
+        { int alocal;
+          printf("pld  reg +/- imm12  cases\n");
+          __asm__ __volatile__( "pld [%0, #128]" : :/*in*/"r"(&alocal) );
+          __asm__ __volatile__( "pld [%0, #-128]" : :/*in*/"r"(&alocal) );
+          __asm__ __volatile__( "pld [r15, #-128]" : :/*in*/"r"(&alocal) );
+
+          // apparently pldw is v7 only
+          //__asm__ __volatile__( "pldw [%0, #128]" : :/*in*/"r"(&alocal) );
+          //__asm__ __volatile__( "pldw [%0, #-128]" : :/*in*/"r"(&alocal) );
+          //__asm__ __volatile__( "pldw [r15, #128]" : :/*in*/"r"(&alocal) );
+
+          printf("pld  reg +/- shifted reg  cases\n");
+          __asm__ __volatile__( "pld [%0, %1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, LSL #1]" : : /*in*/"r"(&alocal), "r"(0) );
+#if 0
+          __asm__ __volatile__( "pld [%0, %1, LSR #1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, ASR #1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, ROR #1]" : : /*in*/"r"(&alocal), "r"(0) );
+          __asm__ __volatile__( "pld [%0, %1, RRX]" : : /*in*/"r"(&alocal), "r"(0) );
+#endif
+        }
+       printf("------------ PLD/PLDW (done) ------------\n");
+#endif
+
+       return 0;
+}
+
+
+////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////
+///////////////////////////////////////////////////////////
+
+
+int main ( void )
+{
+   // 16 bit instructions
+
+   printf("CMP-16 0x10a\n");
+   TESTCARRY
+   TESTINST3("cmp r3, r6", 0,          0,           r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmp r3, r6", 1,          0,           r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmp r3, r6", 0,          1,           r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmp r3, r6", -1,         0,           r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmp r3, r6", 0,          -1,          r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmp r3, r6", 0,          0x80000000,  r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmp r3, r6", 0x80000000, 0,           r6/*fake*/, r3, r6, 0);
+   TESTCARRYEND
+
+   printf("CMN-16 0x10a\n");
+   TESTCARRY
+   TESTINST3("cmn r3, r6", 0,          0,           r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmn r3, r6", 1,          0,           r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmn r3, r6", 0,          1,           r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmn r3, r6", -1,         0,           r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmn r3, r6", 0,          -1,          r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmn r3, r6", 0,          0x80000000,  r6/*fake*/, r3, r6, 0);
+   TESTINST3("cmn r3, r6", 0x80000000, 0,           r6/*fake*/, r3, r6, 0);
+   TESTCARRYEND
+
+   printf("TST-16 0x108\n");
+   TESTCARRY
+   TESTINST3("tst r3, r6", 0,          0,           r6/*fake*/, r3, r6, cv);
+   TESTINST3("tst r3, r6", 1,          0,           r6/*fake*/, r3, r6, cv);
+   TESTINST3("tst r3, r6", 0,          1,           r6/*fake*/, r3, r6, cv);
+   TESTINST3("tst r3, r6", 1,          1,           r6/*fake*/, r3, r6, cv);
+   TESTINST3("tst r3, r6", -1,         0,           r6/*fake*/, r3, r6, cv);
+   TESTINST3("tst r3, r6", 0,          -1,          r6/*fake*/, r3, r6, cv);
+   TESTINST3("tst r3, r6", -1,         -1,          r6/*fake*/, r3, r6, cv);
+   TESTCARRYEND
+
+   printf("NEGS-16 0x109\n");
+   TESTINST2("negs r0, r1", 1, r0, r1, 0);
+   TESTCARRY
+   TESTINST2("negs r0, r1", 1, r0, r1, cv);
+   TESTINST2("negs r0, r1", 0, r0, r1, cv);
+   TESTINST2("negs r0, r1", 0x80000000, r0, r1, cv);
+   TESTINST2("negs r0, r1", 0x80000001, r0, r1, cv);
+   TESTINST2("negs r0, r1", 0xFFFFFFFF, r0, r1, cv);
+   TESTINST2("negs r0, r1", 0x7FFFFFFF, r0, r1, cv);
+   TESTCARRYEND
+
+   printf("MVNS-16 0x10F\n");
+   TESTINST2("mvns r0, r1", 1, r0, r1, 0);
+   TESTCARRY
+   TESTINST2("mvns r0, r1", 1, r0, r1, cv);
+   TESTINST2("mvns r0, r1", 0, r0, r1, cv);
+   TESTINST2("mvns r0, r1", 0x80000000, r0, r1, cv);
+   TESTINST2("mvns r0, r1", 0x80000001, r0, r1, cv);
+   TESTINST2("mvns r0, r1", 0xFFFFFFFF, r0, r1, cv);
+   TESTINST2("mvns r0, r1", 0x7FFFFFFF, r0, r1, cv);
+   TESTCARRYEND
+
+   printf("ORRS-16 0x10C\n");
+   TESTCARRY
+   TESTINST2x("orrs r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
+   TESTINST2x("orrs r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("orrs r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
+   TESTINST2x("orrs r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
+   TESTINST2x("orrs r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("orrs r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
+   TESTINST2x("orrs r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("ANDS-16 0x100\n");
+   TESTCARRY
+   TESTINST2x("ands r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
+   TESTINST2x("ands r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("ands r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
+   TESTINST2x("ands r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
+   TESTINST2x("ands r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("ands r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
+   TESTINST2x("ands r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("EORS-16 0x101\n");
+   TESTCARRY
+   TESTINST2x("eors r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
+   TESTINST2x("eors r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("eors r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
+   TESTINST2x("eors r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
+   TESTINST2x("eors r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("eors r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
+   TESTINST2x("eors r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("MULS-16 0x10d\n");
+   TESTCARRY
+   TESTINST2x("muls r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
+   TESTINST2x("muls r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("muls r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
+   TESTINST2x("muls r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
+   TESTINST2x("muls r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("muls r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
+   TESTINST2x("muls r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("BICS-16 0x10E\n");
+   TESTCARRY
+   TESTINST2x("bics r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
+   TESTINST2x("bics r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("bics r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
+   TESTINST2x("bics r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
+   TESTINST2x("bics r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("bics r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
+   TESTINST2x("bics r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("ADCS-16 0x105\n");
+   TESTCARRY
+   TESTINST2x("adcs r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
+   TESTINST2x("adcs r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("adcs r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
+   TESTINST2x("adcs r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
+   TESTINST2x("adcs r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("adcs r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
+   TESTINST2x("adcs r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("SBCS-16 0x100\n");
+   TESTCARRY
+   TESTINST2x("sbcs r1, r2", 0x31415927, 0x27181728, r1, r2, cv);
+   TESTINST2x("sbcs r1, r2", 0x00000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("sbcs r1, r2", 0x00000001, 0x00000000, r1, r2, cv);
+   TESTINST2x("sbcs r1, r2", 0x00000000, 0x00000001, r1, r2, cv);
+   TESTINST2x("sbcs r1, r2", 0x80000000, 0x00000000, r1, r2, cv);
+   TESTINST2x("sbcs r1, r2", 0x00000000, 0x80000000, r1, r2, cv);
+   TESTINST2x("sbcs r1, r2", 0x80000000, 0x80000000, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("UXTB-16 0x2CB\n");
+   TESTCARRY
+   TESTINST2("uxtb r1, r2", 0x31415927, r1, r2, cv);
+   TESTINST2("uxtb r1, r2", 0x31415997, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("SXTB-16 0x2C9\n");
+   TESTCARRY
+   TESTINST2("sxtb r1, r2", 0x31415927, r1, r2, cv);
+   TESTINST2("sxtb r1, r2", 0x31415997, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("UXTH-16 0x2CA\n");
+   TESTCARRY
+   TESTINST2("uxth r1, r2", 0x31415927, r1, r2, cv);
+   TESTINST2("uxth r1, r2", 0x31419597, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("SXTH-16 0x2C8\n");
+   TESTCARRY
+   TESTINST2("sxth r1, r2", 0x31415927, r1, r2, cv);
+   TESTINST2("sxth r1, r2", 0x31419597, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("LSLS-16 0x102\n");
+   TESTCARRY
+   TESTINST2x("lsls r1, r2", 0x31415927, 0x00000000, r1, r2, cv);
+   TESTINST2x("lsls r1, r2", 0x31415927, 0x00000001, r1, r2, cv);
+   TESTINST2x("lsls r1, r2", 0x31415927, 0x00000002, r1, r2, cv);
+   TESTINST2x("lsls r1, r2", 0x31415927, 0x0000000F, r1, r2, cv);
+   TESTINST2x("lsls r1, r2", 0x31415927, 0x00000010, r1, r2, cv);
+   TESTINST2x("lsls r1, r2", 0x31415927, 0x0000001F, r1, r2, cv);
+   TESTINST2x("lsls r1, r2", 0x31415927, 0x00000020, r1, r2, cv);
+   TESTINST2x("lsls r1, r2", 0x31415927, 0x00000021, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("LSRS-16 0x103\n");
+   TESTCARRY
+   TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000000, r1, r2, cv);
+   TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000001, r1, r2, cv);
+   TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000002, r1, r2, cv);
+   TESTINST2x("lsrs r1, r2", 0x31415927, 0x0000000F, r1, r2, cv);
+   TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000010, r1, r2, cv);
+   TESTINST2x("lsrs r1, r2", 0x31415927, 0x0000001F, r1, r2, cv);
+   TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000020, r1, r2, cv);
+   TESTINST2x("lsrs r1, r2", 0x31415927, 0x00000021, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("ASRS-16 0x104\n");
+   TESTCARRY
+   TESTINST2x("asrs r1, r2", 0x31415927, 0x00000000, r1, r2, cv);
+   TESTINST2x("asrs r1, r2", 0x91415927, 0x00000001, r1, r2, cv);
+   TESTINST2x("asrs r1, r2", 0x31415927, 0x00000002, r1, r2, cv);
+   TESTINST2x("asrs r1, r2", 0x91415927, 0x0000000F, r1, r2, cv);
+   TESTINST2x("asrs r1, r2", 0x31415927, 0x00000010, r1, r2, cv);
+   TESTINST2x("asrs r1, r2", 0x91415927, 0x0000001F, r1, r2, cv);
+   TESTINST2x("asrs r1, r2", 0x31415927, 0x00000020, r1, r2, cv);
+   TESTINST2x("asrs r1, r2", 0x91415927, 0x00000021, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("RORS-16 0x107\n");
+   TESTCARRY
+   TESTINST2x("rors r1, r2", 0x31415927, 0x00000000, r1, r2, cv);
+   TESTINST2x("rors r1, r2", 0x31415927, 0x00000001, r1, r2, cv);
+   TESTINST2x("rors r1, r2", 0x31415927, 0x00000002, r1, r2, cv);
+   TESTINST2x("rors r1, r2", 0x31415927, 0x0000000F, r1, r2, cv);
+   TESTINST2x("rors r1, r2", 0x31415927, 0x00000010, r1, r2, cv);
+   TESTINST2x("rors r1, r2", 0x31415927, 0x0000001F, r1, r2, cv);
+   TESTINST2x("rors r1, r2", 0x31415927, 0x00000020, r1, r2, cv);
+   TESTINST2x("rors r1, r2", 0x31415927, 0x00000021, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("ADD(HI)-16\n");
+   TESTCARRY
+   TESTINST2x("add r5, r12", 0x31415927, 0x12345678, r5, r12, cv);
+   TESTINST2x("add r4, r9 ", 0x31415927, 0x12345678, r4, r9,  cv);
+   TESTCARRYEND
+
+   printf("CMP(HI)-16 0x10a\n");
+   TESTCARRY
+   TESTINST3("cmp r5, r12", 0,          0,           r12/*fake*/, r5, r12, 0);
+   TESTINST3("cmp r5, r12", 1,          0,           r12/*fake*/, r5, r12, 0);
+   TESTINST3("cmp r5, r12", 0,          1,           r12/*fake*/, r5, r12, 0);
+   TESTINST3("cmp r5, r12", -1,         0,           r12/*fake*/, r5, r12, 0);
+   TESTINST3("cmp r5, r12", 0,          -1,          r12/*fake*/, r5, r12, 0);
+   TESTINST3("cmp r5, r12", 0,          0x80000000,  r12/*fake*/, r5, r12, 0);
+   TESTINST3("cmp r5, r12", 0x80000000, 0,           r12/*fake*/, r5, r12, 0);
+   TESTCARRYEND
+
+   printf("MOV(HI)-16\n");
+   TESTCARRY
+   TESTINST2x("mov r5, r12", 0x31415927, 0x12345678, r5, r12, cv);
+   TESTINST2x("mov r4, r9 ", 0x31415927, 0x12345678, r4, r9,  cv);
+   TESTCARRYEND
+
+   printf("ADDS-16 Rd, Rn, #imm3\n");
+   TESTCARRY
+   TESTINST2x("adds r1, r2, #1", 0x31415927, 0x27181728, r1, r2, cv);
+   TESTINST2x("adds r1, r2, #7", 0x31415927, 0x97181728, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("ADDS-16 Rd, Rn, Rm\n");
+   TESTCARRY
+   TESTINST3("adds r1, r2, r3", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds r1, r2, r3", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("SUBS-16 Rd, Rn, Rm\n");
+   TESTCARRY
+   TESTINST3("subs r1, r2, r3", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs r1, r2, r3", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("ADDS-16 Rn, #uimm8\n");
+   TESTCARRY
+   TESTINST1x("adds r1, #0  ", 0x31415927, r1, cv);
+   TESTINST1x("adds r1, #255", 0x31415927, r1, cv);
+   TESTINST1x("adds r1, #0  ", 0x91415927, r1, cv);
+   TESTINST1x("adds r1, #255", 0x91415927, r1, cv);
+   TESTCARRYEND
+
+   printf("SUBS-16 Rn, #uimm8\n");
+   TESTCARRY
+   TESTINST1x("subs r1, #0  ", 0x31415927, r1, cv);
+   TESTINST1x("subs r1, #255", 0x31415927, r1, cv);
+   TESTINST1x("subs r1, #0  ", 0x91415927, r1, cv);
+   TESTINST1x("subs r1, #255", 0x91415927, r1, cv);
+   TESTCARRYEND
+
+   printf("CMP-16 Rn, #uimm8\n");
+   TESTCARRY
+   TESTINST1x("cmp r1, #0x80  ", 0x00000080, r1, cv);
+   TESTINST1x("cmp r1, #0x7f  ", 0x00000080, r1, cv);
+   TESTINST1x("cmp r1, #0x81  ", 0x00000080, r1, cv);
+   TESTINST1x("cmp r1, #0x80  ", 0xffffff80, r1, cv);
+   TESTINST1x("cmp r1, #0x7f  ", 0xffffff80, r1, cv);
+   TESTINST1x("cmp r1, #0x81  ", 0xffffff80, r1, cv);
+   TESTINST1x("cmp r1, #0x01  ", 0x80000000, r1, cv);
+   TESTCARRYEND
+
+   printf("MOVS-16 Rn, #uimm8\n");
+   TESTCARRY
+   TESTINST1x("movs r1, #0   ", 0x31415927, r1, cv);
+   TESTINST1x("movs r1, #0x7f", 0x31415927, r1, cv);
+   TESTINST1x("movs r1, #0x80", 0x31415927, r1, cv);
+   TESTINST1x("movs r1, #0x81", 0x31415927, r1, cv);
+   TESTINST1x("movs r1, #0xff", 0x31415927, r1, cv);
+   TESTCARRYEND
+
+   printf("LSLS-16 Rd, Rm, imm5\n");
+   TESTCARRY
+   TESTINST2("lsls r1, r2, #0   ", 0x31415927, r1, r2, cv);
+   TESTINST2("lsls r1, r2, #1   ", 0x31415927, r1, r2, cv);
+   TESTINST2("lsls r1, r2, #2   ", 0x31415927, r1, r2, cv);
+   TESTINST2("lsls r1, r2, #0xF ", 0x31415927, r1, r2, cv);
+   TESTINST2("lsls r1, r2, #0x10", 0x31415927, r1, r2, cv);
+   TESTINST2("lsls r1, r2, #0x1F", 0x31415927, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("LSRS-16 Rd, Rm, imm5\n");
+   TESTCARRY
+   TESTINST2("lsrs r1, r2, #0   ", 0x31415927, r1, r2, cv);
+   TESTINST2("lsrs r1, r2, #1   ", 0x31415927, r1, r2, cv);
+   TESTINST2("lsrs r1, r2, #2   ", 0x31415927, r1, r2, cv);
+   TESTINST2("lsrs r1, r2, #0xF ", 0x31415927, r1, r2, cv);
+   TESTINST2("lsrs r1, r2, #0x10", 0x31415927, r1, r2, cv);
+   TESTINST2("lsrs r1, r2, #0x1F", 0x31415927, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("ASRS-16 Rd, Rm, imm5\n");
+   TESTCARRY
+   TESTINST2("asrs r1, r2, #0   ", 0x31415927, r1, r2, cv);
+   TESTINST2("asrs r1, r2, #1   ", 0x91415927, r1, r2, cv);
+   TESTINST2("asrs r1, r2, #2   ", 0x31415927, r1, r2, cv);
+   TESTINST2("asrs r1, r2, #0xF ", 0x91415927, r1, r2, cv);
+   TESTINST2("asrs r1, r2, #0x10", 0x31415927, r1, r2, cv);
+   TESTINST2("asrs r1, r2, #0x1F", 0x91415927, r1, r2, cv);
+   TESTCARRYEND
+
+   // 32 bit instructions
+
+   printf("(T3) ADD{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("adds.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("adds.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("add.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T3) CMP.W Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST1x("cmp.w r1, #0xffffffff", 0x31415927, r1, cv);
+   TESTINST1x("cmp.w r1, #0xee00ee00", 0x31415927, r1, cv);
+   TESTINST1x("cmp.w r1, #255       ", 0,          r1, cv);
+   TESTINST1x("cmp.w r1, #0         ", 1,          r1, cv);
+   TESTINST1x("cmp.w r1, #1         ", 0,          r1, cv);
+   TESTINST1x("cmp.w r1, #0         ", -1,         r1, cv);
+   TESTINST1x("cmp.w r1, #-1        ", 0,          r1, cv);
+   TESTINST1x("cmp.w r1, #0x80000000", 0,          r1, cv);
+   TESTINST1x("cmp.w r1, #0         ", 0x80000000, r1, cv);
+   TESTINST1x("cmp.w r1, #0x80000000", 0x80000000, r1, cv);
+   TESTINST1x("cmp.w r1, #0x80000000", 0x7fffffff, r1, cv);
+   TESTINST1x("cmp.w r1, #0xff000000", 0x80000000, r1, cv);
+   TESTINST1x("cmp.w r1, #0x0dd00000", 0x7fffffff, r1, cv);
+   TESTCARRYEND
+
+   printf("(T3) CMN.W Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST1x("cmn.w r1, #0xffffffff", 0x31415927, r1, cv);
+   TESTINST1x("cmn.w r1, #0xee00ee00", 0x31415927, r1, cv);
+   TESTINST1x("cmn.w r1, #255       ", 0,          r1, cv);
+   TESTINST1x("cmn.w r1, #0         ", 1,          r1, cv);
+   TESTINST1x("cmn.w r1, #1         ", 0,          r1, cv);
+   TESTINST1x("cmn.w r1, #0         ", -1,         r1, cv);
+   TESTINST1x("cmn.w r1, #-1        ", 0,          r1, cv);
+   TESTINST1x("cmn.w r1, #0x80000000", 0,          r1, cv);
+   TESTINST1x("cmn.w r1, #0         ", 0x80000000, r1, cv);
+   TESTINST1x("cmn.w r1, #0x80000000", 0x80000000, r1, cv);
+   TESTINST1x("cmn.w r1, #0x80000000", 0x7fffffff, r1, cv);
+   TESTINST1x("cmn.w r1, #0xff000000", 0x80000000, r1, cv);
+   TESTINST1x("cmn.w r1, #0x0dd00000", 0x7fffffff, r1, cv);
+   TESTCARRYEND
+
+   printf("(T3) TST.W Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST1x("tst.w r1, #0xffffffff", 0x31415927, r1, cv);
+   TESTINST1x("tst.w r1, #0xee00ee00", 0x31415927, r1, cv);
+   TESTINST1x("tst.w r1, #255       ", 0,          r1, cv);
+   TESTINST1x("tst.w r1, #0         ", 1,          r1, cv);
+   TESTINST1x("tst.w r1, #1         ", 0,          r1, cv);
+   TESTINST1x("tst.w r1, #0         ", -1,         r1, cv);
+   TESTINST1x("tst.w r1, #-1        ", 0,          r1, cv);
+   TESTINST1x("tst.w r1, #0x80000000", 0,          r1, cv);
+   TESTINST1x("tst.w r1, #0         ", 0x80000000, r1, cv);
+   TESTINST1x("tst.w r1, #0x80000000", 0x80000000, r1, cv);
+   TESTINST1x("tst.w r1, #0x80000000", 0x7fffffff, r1, cv);
+   TESTINST1x("tst.w r1, #0xff000000", 0x80000000, r1, cv);
+   TESTINST1x("tst.w r1, #0x0dd00000", 0x7fffffff, r1, cv);
+   TESTCARRYEND
+
+   printf("(T3) TEQ.W Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST1x("teq.w r1, #0xffffffff", 0x31415927, r1, cv);
+   TESTINST1x("teq.w r1, #0xee00ee00", 0x31415927, r1, cv);
+   TESTINST1x("teq.w r1, #255       ", 0,          r1, cv);
+   TESTINST1x("teq.w r1, #0         ", 1,          r1, cv);
+   TESTINST1x("teq.w r1, #1         ", 0,          r1, cv);
+   TESTINST1x("teq.w r1, #0         ", -1,         r1, cv);
+   TESTINST1x("teq.w r1, #-1        ", 0,          r1, cv);
+   TESTINST1x("teq.w r1, #0x80000000", 0,          r1, cv);
+   TESTINST1x("teq.w r1, #0         ", 0x80000000, r1, cv);
+   TESTINST1x("teq.w r1, #0x80000000", 0x80000000, r1, cv);
+   TESTINST1x("teq.w r1, #0x80000000", 0x7fffffff, r1, cv);
+   TESTINST1x("teq.w r1, #0xff000000", 0x80000000, r1, cv);
+   TESTINST1x("teq.w r1, #0x0dd00000", 0x7fffffff, r1, cv);
+   TESTCARRYEND
+
+   printf("(T3) SUB{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("subs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("subs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("sub.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T3) RSB{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("rsbs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("rsbs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("rsb.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T3) ADC{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("adcs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("adcs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("adc.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T3) SBC{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("sbcs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("sbcs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("sbc.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T3) AND{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("ands.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("ands.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("and.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T3) ORR{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("orrs.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("orrs.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("orr.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T3) EOR{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("eors.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("eors.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("eor.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T3) BIC{S}.W Rd, Rn, #constT [allegedly]\n");
+   TESTCARRY
+   TESTINST2("bics.w r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("bics.w r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0xffffffff", 0x31415927, r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0xee00ee00", 0x31415927, r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #255       ", 0,          r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0         ", 1,          r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #1         ", 0,          r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0         ", -1,         r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #-1        ", 0,          r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0x80000000", 0,          r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0         ", 0x80000000, r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0x80000000", 0x80000000, r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0x80000000", 0x7fffffff, r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0xff000000", 0x80000000, r1, r2, cv);
+   TESTINST2("bic.w  r1, r2, #0x0dd00000", 0x7fffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("ADD{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adds.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("add.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("SUBB{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("subs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sub.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("RSB{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsbs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("rsb.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("ADC{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("adc.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("SBC{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbcs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("sbc.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+#if 0
+   printf("XXX{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxxs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("xxx.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+#endif
+
+   printf("AND{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("ands.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("and.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("ORR{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orrs.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("orr.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("EOR{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eors.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("eor.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("BIC{S}.W Rd, Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0x31415927, 0x27181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0x31415927, 0x97181728, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 1,          0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0,          1,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", -1,         0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0,          -1,         r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0,          0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0x80000000, 0,          r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0x80000000, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0x7fffffff, 0x80000000, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0x80000000, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bics.w r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsl #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, lsr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #0 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #1 ", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #15", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTINST3("bic.w  r1, r2, r3, asr #31", 0x7fffffff, 0x7fffffff, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("(T?) LSL{S}.W Rd, Rn, Rm\n");
+   TESTCARRY
+   TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
+   TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
+   TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
+   TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
+   TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
+   TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
+   TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
+   TESTINST3("lsls.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
+   TESTINST3("lsl.w  r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
+   TESTINST3("lsl.w  r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
+   TESTINST3("lsl.w  r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
+   TESTINST3("lsl.w  r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
+   TESTINST3("lsl.w  r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
+   TESTINST3("lsl.w  r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
+   TESTINST3("lsl.w  r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
+   TESTINST3("lsl.w  r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("(T?) LSR{S}.W Rd, Rn, Rm\n");
+   TESTCARRY
+   TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
+   TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
+   TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
+   TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
+   TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
+   TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
+   TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
+   TESTINST3("lsrs.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
+   TESTINST3("lsr.w  r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
+   TESTINST3("lsr.w  r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
+   TESTINST3("lsr.w  r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
+   TESTINST3("lsr.w  r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
+   TESTINST3("lsr.w  r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
+   TESTINST3("lsr.w  r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
+   TESTINST3("lsr.w  r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
+   TESTINST3("lsr.w  r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
+   TESTCARRYEND
+
+   printf("(T?) ASR{S}.W Rd, Rn, Rm\n");
+   TESTCARRY
+   TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
+   TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x00000001, r1, r2, r3, cv);
+   TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
+   TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x0000000F, r1, r2, r3, cv);
+   TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
+   TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x0000001F, r1, r2, r3, cv);
+   TESTINST3("asrs.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
+   TESTINST3("asrs.w r1, r2, r3", 0x91415927, 0x00000021, r1, r2, r3, cv);
+   TESTINST3("asr.w  r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
+   TESTINST3("asr.w  r1, r2, r3", 0x91415927, 0x00000001, r1, r2, r3, cv);
+   TESTINST3("asr.w  r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
+   TESTINST3("asr.w  r1, r2, r3", 0x91415927, 0x0000000F, r1, r2, r3, cv);
+   TESTINST3("asr.w  r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
+   TESTINST3("asr.w  r1, r2, r3", 0x91415927, 0x0000001F, r1, r2, r3, cv);
+   TESTINST3("asr.w  r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
+   TESTINST3("asr.w  r1, r2, r3", 0x91415927, 0x00000021, r1, r2, r3, cv);
+   TESTCARRYEND
+
+#if 0
+   // not handled by vex
+   printf("(T?) ROR{S}.W Rd, Rn, Rm\n");
+   TESTCARRY
+   TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
+   TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
+   TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
+   TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
+   TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
+   TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
+   TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
+   TESTINST3("rors.w r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
+   TESTINST3("ror.w  r1, r2, r3", 0x31415927, 0x00000000, r1, r2, r3, cv);
+   TESTINST3("ror.w  r1, r2, r3", 0x31415927, 0x00000001, r1, r2, r3, cv);
+   TESTINST3("ror.w  r1, r2, r3", 0x31415927, 0x00000002, r1, r2, r3, cv);
+   TESTINST3("ror.w  r1, r2, r3", 0x31415927, 0x0000000F, r1, r2, r3, cv);
+   TESTINST3("ror.w  r1, r2, r3", 0x31415927, 0x00000010, r1, r2, r3, cv);
+   TESTINST3("ror.w  r1, r2, r3", 0x31415927, 0x0000001F, r1, r2, r3, cv);
+   TESTINST3("ror.w  r1, r2, r3", 0x31415927, 0x00000020, r1, r2, r3, cv);
+   TESTINST3("ror.w  r1, r2, r3", 0x31415927, 0x00000021, r1, r2, r3, cv);
+   TESTCARRYEND
+#endif
+
+   printf("MVN{S}.W Rd, Rn, shift,   and MOV{S}.W ditto\n");
+   TESTCARRY
+   TESTINST2("lsls.w   r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #0 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #1 ", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #15", 0x7fffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #31", 0x7fffffff, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #15", 0x00000000, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #31", 0x00000000, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #15", 0x00000000, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #31", 0x00000000, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #15", 0x00000000, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #31", 0x00000000, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #15", 0x00000000, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #31", 0x00000000, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #15", 0x00000000, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #31", 0x00000000, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #15", 0x00000000, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #31", 0x00000000, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #15", 0x00000000, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #31", 0x00000000, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #15", 0x00000000, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #31", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #15", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #31", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #15", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #31", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #15", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #31", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #15", 0x00000000, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #31", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #15", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #31", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #15", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #31", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #15", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #31", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #0 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #1 ", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #15", 0x00000000, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #31", 0x00000000, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #15", 0x00000001, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #31", 0x00000001, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #15", 0x00000001, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #31", 0x00000001, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #15", 0x00000001, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #31", 0x00000001, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #15", 0x00000001, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #31", 0x00000001, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #15", 0x00000001, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #31", 0x00000001, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #15", 0x00000001, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #31", 0x00000001, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #15", 0x00000001, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #31", 0x00000001, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #15", 0x00000001, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #31", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #15", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #31", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #15", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #31", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #15", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #31", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #15", 0x00000001, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #31", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #15", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #31", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #15", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #31", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #15", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #31", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #0 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #1 ", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #15", 0x00000001, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #31", 0x00000001, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #0 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #1 ", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #15", 0x9218abcd, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #31", 0x9218abcd, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsls.w   r1, r2, #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsrs.w   r1, r2, #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("asrs.w   r1, r2, #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("rors.w   r1, r2, #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsl.w    r1, r2, #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("lsr.w    r1, r2, #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("asr.w    r1, r2, #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("ror.w    r1, r2, #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsl #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, lsr #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, asr #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvns.w   r1, r2, ror #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsl #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, lsr #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, asr #31", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #0 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #1 ", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #15", 0xffffffff, r1, r2, cv);
+   TESTINST2("mvn.w    r1, r2, ror #31", 0xffffffff, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T?) TST.W Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST2x("tst.w  r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv);
+   TESTINST2x("tst.w  r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T?) TEQ.W Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST2x("teq.w  r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv);
+   TESTINST2x("teq.w  r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T?) CMP.W Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST2x("cmp.w  r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, lsr #2", 0x15555555, 0x55555555, r1, r2, cv);
+   TESTINST2x("cmp.w  r1, r2, ror #1", 0x55555555, 0xaaaaaaaa, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T?) CMN.W Rn, Rm, {shift}\n");
+   TESTCARRY
+   TESTINST2x("cmn.w  r1, r2, lsl #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, lsr #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, asr #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, ror #1", 0x11223344, 0x99887766, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, lsl #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, lsr #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, asr #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, ror #1", 0x11223344, 0x00000000, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, lsl #1", 0x91223344, 0x40000000, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, lsr #1", 0x91223344, 0x40000000, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, asr #1", 0x91223344, 0x80000000, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, ror #1", 0x91223344, 0x00000001, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, lsr #2", 0x15555555, 0x55555555, r1, r2, cv);
+   TESTINST2x("cmn.w  r1, r2, ror #1", 0x55555555, 0xaaaaaaaa, r1, r2, cv);
+   TESTCARRYEND
+
+   printf("(T2) MOV{S}.W Rd, #constT\n");
+   TESTCARRY
+   TESTINST1("movs.w  r9, 0x00000000", r9, cv);
+   TESTINST1("movs.w  r9, 0x000000FF", r9, cv);
+   TESTINST1("movs.w  r9, 0x0000007F", r9, cv);
+   TESTINST1("movs.w  r9, 0x00FF00FF", r9, cv);
+   TESTINST1("movs.w  r9, 0x007F007F", r9, cv);
+   TESTINST1("movs.w  r9, 0x43434343", r9, cv);
+   TESTINST1("movs.w  r9, 0x93939393", r9, cv);
+   TESTINST1("movs.w  r9, 0x93000000", r9, cv);
+   TESTINST1("movs.w  r9, 0x43000000", r9, cv);
+   TESTINST1("movs.w  r9, 0x09300000", r9, cv);
+   TESTINST1("movs.w  r9, 0x04300000", r9, cv);
+   TESTINST1("movs.w  r9, 0x00930000", r9, cv);
+   TESTINST1("movs.w  r9, 0x00430000", r9, cv);
+   TESTINST1("movs.w  r9, 0x00000930", r9, cv);
+   TESTINST1("movs.w  r9, 0x00000430", r9, cv);
+   TESTINST1("movs.w  r9, 0x00000093", r9, cv);
+   TESTINST1("movs.w  r9, 0x00000043", r9, cv);
+   TESTINST1("mov.w   r9, 0x00000000", r9, cv);
+   TESTINST1("mov.w   r9, 0x000000FF", r9, cv);
+   TESTINST1("mov.w   r9, 0x0000007F", r9, cv);
+   TESTINST1("mov.w   r9, 0x00FF00FF", r9, cv);
+   TESTINST1("mov.w   r9, 0x007F007F", r9, cv);
+   TESTINST1("mov.w   r9, 0x43434343", r9, cv);
+   TESTINST1("mov.w   r9, 0x93939393", r9, cv);
+   TESTINST1("mov.w   r9, 0x93000000", r9, cv);
+   TESTINST1("mov.w   r9, 0x43000000", r9, cv);
+   TESTINST1("mov.w   r9, 0x09300000", r9, cv);
+   TESTINST1("mov.w   r9, 0x04300000", r9, cv);
+   TESTINST1("mov.w   r9, 0x00930000", r9, cv);
+   TESTINST1("mov.w   r9, 0x00430000", r9, cv);
+   TESTINST1("mov.w   r9, 0x00000930", r9, cv);
+   TESTINST1("mov.w   r9, 0x00000430", r9, cv);
+   TESTINST1("mov.w   r9, 0x00000093", r9, cv);
+   TESTINST1("mov.w   r9, 0x00000043", r9, cv);
+   TESTCARRYEND
+
+   printf("(T2) MVN{S}.W Rd, #constT\n");
+   TESTCARRY
+   TESTINST1("mvns.w  r9, 0x00000000", r9, cv);
+   TESTINST1("mvns.w  r9, 0x000000FF", r9, cv);
+   TESTINST1("mvns.w  r9, 0x0000007F", r9, cv);
+   TESTINST1("mvns.w  r9, 0x00FF00FF", r9, cv);
+   TESTINST1("mvns.w  r9, 0x007F007F", r9, cv);
+   TESTINST1("mvns.w  r9, 0x43434343", r9, cv);
+   TESTINST1("mvns.w  r9, 0x93939393", r9, cv);
+   TESTINST1("mvns.w  r9, 0x93000000", r9, cv);
+   TESTINST1("mvns.w  r9, 0x43000000", r9, cv);
+   TESTINST1("mvns.w  r9, 0x09300000", r9, cv);
+   TESTINST1("mvns.w  r9, 0x04300000", r9, cv);
+   TESTINST1("mvns.w  r9, 0x00930000", r9, cv);
+   TESTINST1("mvns.w  r9, 0x00430000", r9, cv);
+   TESTINST1("mvns.w  r9, 0x00000930", r9, cv);
+   TESTINST1("mvns.w  r9, 0x00000430", r9, cv);
+   TESTINST1("mvns.w  r9, 0x00000093", r9, cv);
+   TESTINST1("mvns.w  r9, 0x00000043", r9, cv);
+   TESTINST1("mvn.w   r9, 0x00000000", r9, cv);
+   TESTINST1("mvn.w   r9, 0x000000FF", r9, cv);
+   TESTINST1("mvn.w   r9, 0x0000007F", r9, cv);
+   TESTINST1("mvn.w   r9, 0x00FF00FF", r9, cv);
+   TESTINST1("mvn.w   r9, 0x007F007F", r9, cv);
+   TESTINST1("mvn.w   r9, 0x43434343", r9, cv);
+   TESTINST1("mvn.w   r9, 0x93939393", r9, cv);
+   TESTINST1("mvn.w   r9, 0x93000000", r9, cv);
+   TESTINST1("mvn.w   r9, 0x43000000", r9, cv);
+   TESTINST1("mvn.w   r9, 0x09300000", r9, cv);
+   TESTINST1("mvn.w   r9, 0x04300000", r9, cv);
+   TESTINST1("mvn.w   r9, 0x00930000", r9, cv);
+   TESTINST1("mvn.w   r9, 0x00430000", r9, cv);
+   TESTINST1("mvn.w   r9, 0x00000930", r9, cv);
+   TESTINST1("mvn.w   r9, 0x00000430", r9, cv);
+   TESTINST1("mvn.w   r9, 0x00000093", r9, cv);
+   TESTINST1("mvn.w   r9, 0x00000043", r9, cv);
+   TESTCARRYEND
+
+   // plus whatever stuff we can throw in from the old ARM test program
+   old_main();
+
+   return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.stdout.exp
new file mode 100644 (file)
index 0000000..7a4d4dc
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.stdout.exp
@@ -0,0 +1,15884 @@
+CMP-16 0x10a
+cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+CMN-16 0x10a
+cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+cmn r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+cmn r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+cmn r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+TST-16 0x108
+tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+tst r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+tst r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+tst r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+tst r3, r6 :: rd 0x00000001 rm 0x00000001, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+tst r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+tst r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+tst r3, r6 :: rd 0xffffffff rm 0xffffffff, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+NEGS-16 0x109
+negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 0, cpsr 0x00000000     
+negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x00000000     
+negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 1, cpsr 0x00000000     
+negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x00000000     
+negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 2, cpsr 0x00000000     
+negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x00000000     
+negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+negs r0, r1 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+negs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+negs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+negs r0, r1 :: rd 0x7fffffff rm 0x80000001, c:v-in 3, cpsr 0x00000000     
+negs r0, r1 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x00000000     
+negs r0, r1 :: rd 0x80000001 rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+MVNS-16 0x10F
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000     
+mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 0, cpsr 0x00000000     
+mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x10000000    V
+mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 1, cpsr 0x10000000    V
+mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 2, cpsr 0x20000000   C 
+mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+mvns r0, r1 :: rd 0x7ffffffe rm 0x80000001, c:v-in 3, cpsr 0x30000000   CV
+mvns r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns r0, r1 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+ORRS-16 0x10C
+orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+ANDS-16 0x100
+ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+ands r1, r2 :: rd 0x21001120 rm 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+ands r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+EORS-16 0x101
+eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors r1, r2 :: rd 0x16594e0f rm 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+eors r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+eors r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+eors r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+MULS-16 0x10d
+muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 1, cpsr 0x90000000 N  V
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 2, cpsr 0xa0000000 N C 
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+muls r1, r2 :: rd 0xdde06f18 rm 0x27181728, c:v-in 3, cpsr 0xb0000000 N CV
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+muls r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+muls r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+muls r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+BICS-16 0x10E
+bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics r1, r2 :: rd 0x10414807 rm 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+bics r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+bics r1, r2 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+bics r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ADCS-16 0x105
+adcs r1, r2 :: rd 0x5859704f rm 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adcs r1, r2 :: rd 0x5859704f rm 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adcs r1, r2 :: rd 0x58597050 rm 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs r1, r2 :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs r1, r2 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adcs r1, r2 :: rd 0x58597050 rm 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs r1, r2 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs r1, r2 :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs r1, r2 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+SBCS-16 0x100
+sbcs r1, r2 :: rd 0x0a2941fe rm 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs r1, r2 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs r1, r2 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs r1, r2 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs r1, r2 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000     
+sbcs r1, r2 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs r1, r2 :: rd 0x0a2941fe rm 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs r1, r2 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs r1, r2 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs r1, r2 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs r1, r2 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x00000000     
+sbcs r1, r2 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs r1, r2 :: rd 0x0a2941ff rm 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs r1, r2 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+sbcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs r1, r2 :: rd 0x0a2941ff rm 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs r1, r2 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+sbcs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs r1, r2 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+UXTB-16 0x2CB
+uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 1, cpsr 0xd0000000 NZ V
+uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 2, cpsr 0xe0000000 NZC 
+uxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+uxtb r1, r2 :: rd 0x00000097 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
+SXTB-16 0x2C9
+sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 1, cpsr 0xd0000000 NZ V
+sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 2, cpsr 0xe0000000 NZC 
+sxtb r1, r2 :: rd 0x00000027 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+sxtb r1, r2 :: rd 0xffffff97 rm 0x31415997, c:v-in 3, cpsr 0xf0000000 NZCV
+UXTH-16 0x2CA
+uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 0, cpsr 0xc0000000 NZ  
+uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 1, cpsr 0xd0000000 NZ V
+uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 2, cpsr 0xe0000000 NZC 
+uxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+uxth r1, r2 :: rd 0x00009597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
+SXTH-16 0x2C8
+sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 1, cpsr 0xd0000000 NZ V
+sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 2, cpsr 0xe0000000 NZC 
+sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
+LSLS-16 0x102
+lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 0, cpsr 0x80000000 N   
+lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 0, cpsr 0x80000000 N   
+lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 0, cpsr 0x20000000   C 
+lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C 
+lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x60000000  ZC 
+lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 0, cpsr 0x40000000  Z  
+lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 1, cpsr 0x90000000 N  V
+lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 1, cpsr 0x90000000 N  V
+lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 1, cpsr 0x30000000   CV
+lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV
+lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x70000000  ZCV
+lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 1, cpsr 0x50000000  Z V
+lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 2, cpsr 0x80000000 N   
+lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 2, cpsr 0x80000000 N   
+lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 2, cpsr 0x20000000   C 
+lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x60000000  ZC 
+lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 2, cpsr 0x40000000  Z  
+lsls r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+lsls r1, r2 :: rd 0x6282b24e rm 0x00000001, c:v-in 3, cpsr 0x10000000    V
+lsls r1, r2 :: rd 0xc505649c rm 0x00000002, c:v-in 3, cpsr 0x90000000 N  V
+lsls r1, r2 :: rd 0xac938000 rm 0x0000000f, c:v-in 3, cpsr 0x90000000 N  V
+lsls r1, r2 :: rd 0x59270000 rm 0x00000010, c:v-in 3, cpsr 0x30000000   CV
+lsls r1, r2 :: rd 0x80000000 rm 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x70000000  ZCV
+lsls r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 3, cpsr 0x50000000  Z V
+LSRS-16 0x103
+lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 0, cpsr 0x20000000   C 
+lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 0, cpsr 0x20000000   C 
+lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 0, cpsr 0x00000000     
+lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 1, cpsr 0x30000000   CV
+lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 1, cpsr 0x30000000   CV
+lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 1, cpsr 0x30000000   CV
+lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 1, cpsr 0x10000000    V
+lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 2, cpsr 0x20000000   C 
+lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 2, cpsr 0x20000000   C 
+lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 2, cpsr 0x00000000     
+lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+lsrs r1, r2 :: rd 0x18a0ac93 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+lsrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 3, cpsr 0x30000000   CV
+lsrs r1, r2 :: rd 0x00006282 rm 0x0000000f, c:v-in 3, cpsr 0x30000000   CV
+lsrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 3, cpsr 0x10000000    V
+lsrs r1, r2 :: rd 0x00000000 rm 0x0000001f, c:v-in 3, cpsr 0x50000000  Z V
+lsrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x50000000  Z V
+lsrs r1, r2 :: rd 0x00000000 rm 0x00000021, c:v-in 3, cpsr 0x50000000  Z V
+ASRS-16 0x104
+asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 0, cpsr 0x20000000   C 
+asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 0, cpsr 0x00000000     
+asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 0, cpsr 0x80000000 N   
+asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 0, cpsr 0x40000000  Z  
+asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 1, cpsr 0x30000000   CV
+asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 1, cpsr 0x10000000    V
+asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 1, cpsr 0x90000000 N  V
+asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 1, cpsr 0x50000000  Z V
+asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 2, cpsr 0x20000000   C 
+asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 2, cpsr 0x00000000     
+asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 2, cpsr 0x80000000 N   
+asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 2, cpsr 0x40000000  Z  
+asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+asrs r1, r2 :: rd 0xc8a0ac93 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r1, r2 :: rd 0x0c505649 rm 0x00000002, c:v-in 3, cpsr 0x30000000   CV
+asrs r1, r2 :: rd 0xffff2282 rm 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r1, r2 :: rd 0x00003141 rm 0x00000010, c:v-in 3, cpsr 0x10000000    V
+asrs r1, r2 :: rd 0xffffffff rm 0x0000001f, c:v-in 3, cpsr 0x90000000 N  V
+asrs r1, r2 :: rd 0x00000000 rm 0x00000020, c:v-in 3, cpsr 0x50000000  Z V
+asrs r1, r2 :: rd 0xffffffff rm 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV
+RORS-16 0x107
+rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 0, cpsr 0xa0000000 N C 
+rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C 
+rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 0, cpsr 0x00000000     
+rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 0, cpsr 0x00000000     
+rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 0, cpsr 0x00000000     
+rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 0, cpsr 0xa0000000 N C 
+rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV
+rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV
+rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 1, cpsr 0x10000000    V
+rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 1, cpsr 0x10000000    V
+rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 1, cpsr 0x10000000    V
+rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV
+rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 2, cpsr 0xa0000000 N C 
+rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C 
+rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 2, cpsr 0x00000000     
+rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 2, cpsr 0x00000000     
+rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 2, cpsr 0x00000000     
+rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 2, cpsr 0xa0000000 N C 
+rors r1, r2 :: rd 0x31415927 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+rors r1, r2 :: rd 0x98a0ac93 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+rors r1, r2 :: rd 0xcc505649 rm 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV
+rors r1, r2 :: rd 0xb24e6282 rm 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV
+rors r1, r2 :: rd 0x59273141 rm 0x00000010, c:v-in 3, cpsr 0x10000000    V
+rors r1, r2 :: rd 0x6282b24e rm 0x0000001f, c:v-in 3, cpsr 0x10000000    V
+rors r1, r2 :: rd 0x31415927 rm 0x00000020, c:v-in 3, cpsr 0x10000000    V
+rors r1, r2 :: rd 0x98a0ac93 rm 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV
+ADD(HI)-16
+add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ  
+add r4, r9  :: rd 0x4375af9f rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ  
+add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V
+add r4, r9  :: rd 0x4375af9f rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V
+add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC 
+add r4, r9  :: rd 0x4375af9f rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC 
+add r5, r12 :: rd 0x4375af9f rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV
+add r4, r9  :: rd 0x4375af9f rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV
+CMP(HI)-16 0x10a
+cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r5, r12 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r5, r12 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp r5, r12 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+cmp r5, r12 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r5, r12 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+cmp r5, r12 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp r5, r12 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+MOV(HI)-16
+mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ  
+mov r4, r9  :: rd 0x12345678 rm 0x12345678, c:v-in 0, cpsr 0xc0000000 NZ  
+mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V
+mov r4, r9  :: rd 0x12345678 rm 0x12345678, c:v-in 1, cpsr 0xd0000000 NZ V
+mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC 
+mov r4, r9  :: rd 0x12345678 rm 0x12345678, c:v-in 2, cpsr 0xe0000000 NZC 
+mov r5, r12 :: rd 0x12345678 rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV
+mov r4, r9  :: rd 0x12345678 rm 0x12345678, c:v-in 3, cpsr 0xf0000000 NZCV
+ADDS-16 Rd, Rn, #imm3
+adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adds r1, r2, #1 :: rd 0x27181729 rm 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds r1, r2, #7 :: rd 0x9718172f rm 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+ADDS-16 Rd, Rn, Rm
+adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000  ZCV
+adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adds r1, r2, r3 :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adds r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+adds r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds r1, r2, r3 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+SUBS-16 Rd, Rn, Rm
+subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs r1, r2, r3 :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs r1, r2, r3 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+subs r1, r2, r3 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+subs r1, r2, r3 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs r1, r2, r3 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs r1, r2, r3 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs r1, r2, r3 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+subs r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+ADDS-16 Rn, #uimm8
+adds r1, #0   :: rd 0x31415927, c:v-in 0, cpsr 0x00000000     
+adds r1, #255 :: rd 0x31415a26, c:v-in 0, cpsr 0x00000000     
+adds r1, #0   :: rd 0x91415927, c:v-in 0, cpsr 0x80000000 N   
+adds r1, #255 :: rd 0x91415a26, c:v-in 0, cpsr 0x80000000 N   
+adds r1, #0   :: rd 0x31415927, c:v-in 1, cpsr 0x00000000     
+adds r1, #255 :: rd 0x31415a26, c:v-in 1, cpsr 0x00000000     
+adds r1, #0   :: rd 0x91415927, c:v-in 1, cpsr 0x80000000 N   
+adds r1, #255 :: rd 0x91415a26, c:v-in 1, cpsr 0x80000000 N   
+adds r1, #0   :: rd 0x31415927, c:v-in 2, cpsr 0x00000000     
+adds r1, #255 :: rd 0x31415a26, c:v-in 2, cpsr 0x00000000     
+adds r1, #0   :: rd 0x91415927, c:v-in 2, cpsr 0x80000000 N   
+adds r1, #255 :: rd 0x91415a26, c:v-in 2, cpsr 0x80000000 N   
+adds r1, #0   :: rd 0x31415927, c:v-in 3, cpsr 0x00000000     
+adds r1, #255 :: rd 0x31415a26, c:v-in 3, cpsr 0x00000000     
+adds r1, #0   :: rd 0x91415927, c:v-in 3, cpsr 0x80000000 N   
+adds r1, #255 :: rd 0x91415a26, c:v-in 3, cpsr 0x80000000 N   
+SUBS-16 Rn, #uimm8
+subs r1, #0   :: rd 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+subs r1, #255 :: rd 0x31415828, c:v-in 0, cpsr 0x20000000   C 
+subs r1, #0   :: rd 0x91415927, c:v-in 0, cpsr 0xa0000000 N C 
+subs r1, #255 :: rd 0x91415828, c:v-in 0, cpsr 0xa0000000 N C 
+subs r1, #0   :: rd 0x31415927, c:v-in 1, cpsr 0x20000000   C 
+subs r1, #255 :: rd 0x31415828, c:v-in 1, cpsr 0x20000000   C 
+subs r1, #0   :: rd 0x91415927, c:v-in 1, cpsr 0xa0000000 N C 
+subs r1, #255 :: rd 0x91415828, c:v-in 1, cpsr 0xa0000000 N C 
+subs r1, #0   :: rd 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+subs r1, #255 :: rd 0x31415828, c:v-in 2, cpsr 0x20000000   C 
+subs r1, #0   :: rd 0x91415927, c:v-in 2, cpsr 0xa0000000 N C 
+subs r1, #255 :: rd 0x91415828, c:v-in 2, cpsr 0xa0000000 N C 
+subs r1, #0   :: rd 0x31415927, c:v-in 3, cpsr 0x20000000   C 
+subs r1, #255 :: rd 0x31415828, c:v-in 3, cpsr 0x20000000   C 
+subs r1, #0   :: rd 0x91415927, c:v-in 3, cpsr 0xa0000000 N C 
+subs r1, #255 :: rd 0x91415828, c:v-in 3, cpsr 0xa0000000 N C 
+CMP-16 Rn, #uimm8
+cmp r1, #0x80   :: rd 0x00000080, c:v-in 0, cpsr 0x60000000  ZC 
+cmp r1, #0x7f   :: rd 0x00000080, c:v-in 0, cpsr 0x20000000   C 
+cmp r1, #0x81   :: rd 0x00000080, c:v-in 0, cpsr 0x80000000 N   
+cmp r1, #0x80   :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r1, #0x7f   :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r1, #0x81   :: rd 0xffffff80, c:v-in 0, cpsr 0xa0000000 N C 
+cmp r1, #0x01   :: rd 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+cmp r1, #0x80   :: rd 0x00000080, c:v-in 1, cpsr 0x60000000  ZC 
+cmp r1, #0x7f   :: rd 0x00000080, c:v-in 1, cpsr 0x20000000   C 
+cmp r1, #0x81   :: rd 0x00000080, c:v-in 1, cpsr 0x80000000 N   
+cmp r1, #0x80   :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C 
+cmp r1, #0x7f   :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C 
+cmp r1, #0x81   :: rd 0xffffff80, c:v-in 1, cpsr 0xa0000000 N C 
+cmp r1, #0x01   :: rd 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+cmp r1, #0x80   :: rd 0x00000080, c:v-in 2, cpsr 0x60000000  ZC 
+cmp r1, #0x7f   :: rd 0x00000080, c:v-in 2, cpsr 0x20000000   C 
+cmp r1, #0x81   :: rd 0x00000080, c:v-in 2, cpsr 0x80000000 N   
+cmp r1, #0x80   :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C 
+cmp r1, #0x7f   :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C 
+cmp r1, #0x81   :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C 
+cmp r1, #0x01   :: rd 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+cmp r1, #0x80   :: rd 0x00000080, c:v-in 3, cpsr 0x60000000  ZC 
+cmp r1, #0x7f   :: rd 0x00000080, c:v-in 3, cpsr 0x20000000   C 
+cmp r1, #0x81   :: rd 0x00000080, c:v-in 3, cpsr 0x80000000 N   
+cmp r1, #0x80   :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C 
+cmp r1, #0x7f   :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C 
+cmp r1, #0x81   :: rd 0xffffff80, c:v-in 3, cpsr 0xa0000000 N C 
+cmp r1, #0x01   :: rd 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+MOVS-16 Rn, #uimm8
+movs r1, #0    :: rd 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+movs r1, #0x7f :: rd 0x0000007f, c:v-in 0, cpsr 0x00000000     
+movs r1, #0x80 :: rd 0x00000080, c:v-in 0, cpsr 0x00000000     
+movs r1, #0x81 :: rd 0x00000081, c:v-in 0, cpsr 0x00000000     
+movs r1, #0xff :: rd 0x000000ff, c:v-in 0, cpsr 0x00000000     
+movs r1, #0    :: rd 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+movs r1, #0x7f :: rd 0x0000007f, c:v-in 1, cpsr 0x10000000    V
+movs r1, #0x80 :: rd 0x00000080, c:v-in 1, cpsr 0x10000000    V
+movs r1, #0x81 :: rd 0x00000081, c:v-in 1, cpsr 0x10000000    V
+movs r1, #0xff :: rd 0x000000ff, c:v-in 1, cpsr 0x10000000    V
+movs r1, #0    :: rd 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+movs r1, #0x7f :: rd 0x0000007f, c:v-in 2, cpsr 0x20000000   C 
+movs r1, #0x80 :: rd 0x00000080, c:v-in 2, cpsr 0x20000000   C 
+movs r1, #0x81 :: rd 0x00000081, c:v-in 2, cpsr 0x20000000   C 
+movs r1, #0xff :: rd 0x000000ff, c:v-in 2, cpsr 0x20000000   C 
+movs r1, #0    :: rd 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+movs r1, #0x7f :: rd 0x0000007f, c:v-in 3, cpsr 0x30000000   CV
+movs r1, #0x80 :: rd 0x00000080, c:v-in 3, cpsr 0x30000000   CV
+movs r1, #0x81 :: rd 0x00000081, c:v-in 3, cpsr 0x30000000   CV
+movs r1, #0xff :: rd 0x000000ff, c:v-in 3, cpsr 0x30000000   CV
+LSLS-16 Rd, Rm, imm5
+lsls r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+lsls r1, r2, #1    :: rd 0x6282b24e rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+lsls r1, r2, #2    :: rd 0xc505649c rm 0x31415927, c:v-in 0, cpsr 0x80000000 N   
+lsls r1, r2, #0xF  :: rd 0xac938000 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N   
+lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C 
+lsls r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+lsls r1, r2, #1    :: rd 0x6282b24e rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+lsls r1, r2, #2    :: rd 0xc505649c rm 0x31415927, c:v-in 1, cpsr 0x90000000 N  V
+lsls r1, r2, #0xF  :: rd 0xac938000 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N  V
+lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 1, cpsr 0x30000000   CV
+lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 1, cpsr 0xb0000000 N CV
+lsls r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+lsls r1, r2, #1    :: rd 0x6282b24e rm 0x31415927, c:v-in 2, cpsr 0x00000000     
+lsls r1, r2, #2    :: rd 0xc505649c rm 0x31415927, c:v-in 2, cpsr 0x80000000 N   
+lsls r1, r2, #0xF  :: rd 0xac938000 rm 0x31415927, c:v-in 2, cpsr 0x80000000 N   
+lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+lsls r1, r2, #1    :: rd 0x6282b24e rm 0x31415927, c:v-in 3, cpsr 0x10000000    V
+lsls r1, r2, #2    :: rd 0xc505649c rm 0x31415927, c:v-in 3, cpsr 0x90000000 N  V
+lsls r1, r2, #0xF  :: rd 0xac938000 rm 0x31415927, c:v-in 3, cpsr 0x90000000 N  V
+lsls r1, r2, #0x10 :: rd 0x59270000 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+lsls r1, r2, #0x1F :: rd 0x80000000 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
+LSRS-16 Rd, Rm, imm5
+lsrs r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+lsrs r1, r2, #1    :: rd 0x18a0ac93 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+lsrs r1, r2, #2    :: rd 0x0c505649 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+lsrs r1, r2, #0xF  :: rd 0x00006282 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+lsrs r1, r2, #1    :: rd 0x18a0ac93 rm 0x31415927, c:v-in 1, cpsr 0x30000000   CV
+lsrs r1, r2, #2    :: rd 0x0c505649 rm 0x31415927, c:v-in 1, cpsr 0x30000000   CV
+lsrs r1, r2, #0xF  :: rd 0x00006282 rm 0x31415927, c:v-in 1, cpsr 0x30000000   CV
+lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+lsrs r1, r2, #1    :: rd 0x18a0ac93 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+lsrs r1, r2, #2    :: rd 0x0c505649 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+lsrs r1, r2, #0xF  :: rd 0x00006282 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 2, cpsr 0x00000000     
+lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+lsrs r1, r2, #1    :: rd 0x18a0ac93 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+lsrs r1, r2, #2    :: rd 0x0c505649 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+lsrs r1, r2, #0xF  :: rd 0x00006282 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+lsrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 3, cpsr 0x10000000    V
+lsrs r1, r2, #0x1F :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0x50000000  Z V
+ASRS-16 Rd, Rm, imm5
+asrs r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+asrs r1, r2, #1    :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r1, r2, #2    :: rd 0x0c505649 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+asrs r1, r2, #0xF  :: rd 0xffff2282 rm 0x91415927, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 0, cpsr 0x80000000 N   
+asrs r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+asrs r1, r2, #1    :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r1, r2, #2    :: rd 0x0c505649 rm 0x31415927, c:v-in 1, cpsr 0x30000000   CV
+asrs r1, r2, #0xF  :: rd 0xffff2282 rm 0x91415927, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 1, cpsr 0x90000000 N  V
+asrs r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+asrs r1, r2, #1    :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r1, r2, #2    :: rd 0x0c505649 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+asrs r1, r2, #0xF  :: rd 0xffff2282 rm 0x91415927, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 2, cpsr 0x00000000     
+asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 2, cpsr 0x80000000 N   
+asrs r1, r2, #0    :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+asrs r1, r2, #1    :: rd 0xc8a0ac93 rm 0x91415927, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r1, r2, #2    :: rd 0x0c505649 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+asrs r1, r2, #0xF  :: rd 0xffff2282 rm 0x91415927, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r1, r2, #0x10 :: rd 0x00003141 rm 0x31415927, c:v-in 3, cpsr 0x10000000    V
+asrs r1, r2, #0x1F :: rd 0xffffffff rm 0x91415927, c:v-in 3, cpsr 0x90000000 N  V
+(T3) ADD{S}.W Rd, Rn, #constT [allegedly]
+adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+adds.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+add.w  r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0x20000000   C 
+adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0x20000000   C 
+adds.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+add.w  r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+adds.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x70000000  ZCV
+adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+add.w  r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 3, cpsr 0x20000000   C 
+adds.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 3, cpsr 0x20000000   C 
+adds.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+adds.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adds.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+add.w  r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T3) CMP.W Rn, #constT [allegedly]
+cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x00000000     
+cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x00000000     
+cmp.w r1, #255        :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmp.w r1, #0          :: rd 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+cmp.w r1, #1          :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmp.w r1, #0          :: rd 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+cmp.w r1, #-1         :: rd 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+cmp.w r1, #0          :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x00000000     
+cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x00000000     
+cmp.w r1, #255        :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+cmp.w r1, #0          :: rd 0x00000001, c:v-in 1, cpsr 0x20000000   C 
+cmp.w r1, #1          :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+cmp.w r1, #0          :: rd 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+cmp.w r1, #-1         :: rd 0x00000000, c:v-in 1, cpsr 0x00000000     
+cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+cmp.w r1, #0          :: rd 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x00000000     
+cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x00000000     
+cmp.w r1, #255        :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+cmp.w r1, #0          :: rd 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+cmp.w r1, #1          :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+cmp.w r1, #0          :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+cmp.w r1, #-1         :: rd 0x00000000, c:v-in 2, cpsr 0x00000000     
+cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+cmp.w r1, #0          :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+cmp.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x00000000     
+cmp.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x00000000     
+cmp.w r1, #255        :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+cmp.w r1, #0          :: rd 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+cmp.w r1, #1          :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+cmp.w r1, #0          :: rd 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+cmp.w r1, #-1         :: rd 0x00000000, c:v-in 3, cpsr 0x00000000     
+cmp.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+cmp.w r1, #0          :: rd 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+cmp.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+cmp.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+cmp.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+cmp.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+(T3) CMN.W Rn, #constT [allegedly]
+cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+cmn.w r1, #255        :: rd 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn.w r1, #0          :: rd 0x00000001, c:v-in 0, cpsr 0x00000000     
+cmn.w r1, #1          :: rd 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn.w r1, #0          :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+cmn.w r1, #-1         :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+cmn.w r1, #0          :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x20000000   C 
+cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x20000000   C 
+cmn.w r1, #255        :: rd 0x00000000, c:v-in 1, cpsr 0x00000000     
+cmn.w r1, #0          :: rd 0x00000001, c:v-in 1, cpsr 0x00000000     
+cmn.w r1, #1          :: rd 0x00000000, c:v-in 1, cpsr 0x00000000     
+cmn.w r1, #0          :: rd 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+cmn.w r1, #-1         :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+cmn.w r1, #0          :: rd 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+cmn.w r1, #255        :: rd 0x00000000, c:v-in 2, cpsr 0x00000000     
+cmn.w r1, #0          :: rd 0x00000001, c:v-in 2, cpsr 0x00000000     
+cmn.w r1, #1          :: rd 0x00000000, c:v-in 2, cpsr 0x00000000     
+cmn.w r1, #0          :: rd 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+cmn.w r1, #-1         :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+cmn.w r1, #0          :: rd 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x70000000  ZCV
+cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+cmn.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x20000000   C 
+cmn.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x20000000   C 
+cmn.w r1, #255        :: rd 0x00000000, c:v-in 3, cpsr 0x00000000     
+cmn.w r1, #0          :: rd 0x00000001, c:v-in 3, cpsr 0x00000000     
+cmn.w r1, #1          :: rd 0x00000000, c:v-in 3, cpsr 0x00000000     
+cmn.w r1, #0          :: rd 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+cmn.w r1, #-1         :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+cmn.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+cmn.w r1, #0          :: rd 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+cmn.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+cmn.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+cmn.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+cmn.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+(T3) TST.W Rn, #constT [allegedly]
+tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x00000000     
+tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x00000000     
+tst.w r1, #255        :: rd 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w r1, #0          :: rd 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+tst.w r1, #1          :: rd 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w r1, #0          :: rd 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+tst.w r1, #-1         :: rd 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+tst.w r1, #0          :: rd 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x10000000    V
+tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x10000000    V
+tst.w r1, #255        :: rd 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w r1, #0          :: rd 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+tst.w r1, #1          :: rd 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w r1, #0          :: rd 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+tst.w r1, #-1         :: rd 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0x70000000  ZCV
+tst.w r1, #0          :: rd 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+tst.w r1, #255        :: rd 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+tst.w r1, #0          :: rd 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+tst.w r1, #1          :: rd 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+tst.w r1, #0          :: rd 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+tst.w r1, #-1         :: rd 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+tst.w r1, #0          :: rd 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+tst.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+tst.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+tst.w r1, #255        :: rd 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+tst.w r1, #0          :: rd 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+tst.w r1, #1          :: rd 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+tst.w r1, #0          :: rd 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+tst.w r1, #-1         :: rd 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+tst.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+tst.w r1, #0          :: rd 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+tst.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+tst.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+tst.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+tst.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+(T3) TEQ.W Rn, #constT [allegedly]
+teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 0, cpsr 0x80000000 N   
+teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 0, cpsr 0x80000000 N   
+teq.w r1, #255        :: rd 0x00000000, c:v-in 0, cpsr 0x00000000     
+teq.w r1, #0          :: rd 0x00000001, c:v-in 0, cpsr 0x00000000     
+teq.w r1, #1          :: rd 0x00000000, c:v-in 0, cpsr 0x00000000     
+teq.w r1, #0          :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+teq.w r1, #-1         :: rd 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+teq.w r1, #0          :: rd 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 1, cpsr 0x90000000 N  V
+teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 1, cpsr 0x90000000 N  V
+teq.w r1, #255        :: rd 0x00000000, c:v-in 1, cpsr 0x10000000    V
+teq.w r1, #0          :: rd 0x00000001, c:v-in 1, cpsr 0x10000000    V
+teq.w r1, #1          :: rd 0x00000000, c:v-in 1, cpsr 0x10000000    V
+teq.w r1, #0          :: rd 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+teq.w r1, #-1         :: rd 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV
+teq.w r1, #0          :: rd 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+teq.w r1, #255        :: rd 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+teq.w r1, #0          :: rd 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+teq.w r1, #1          :: rd 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+teq.w r1, #0          :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+teq.w r1, #-1         :: rd 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+teq.w r1, #0          :: rd 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+teq.w r1, #0xffffffff :: rd 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
+teq.w r1, #0xee00ee00 :: rd 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
+teq.w r1, #255        :: rd 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+teq.w r1, #0          :: rd 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+teq.w r1, #1          :: rd 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+teq.w r1, #0          :: rd 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+teq.w r1, #-1         :: rd 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+teq.w r1, #0x80000000 :: rd 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+teq.w r1, #0          :: rd 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+teq.w r1, #0x80000000 :: rd 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+teq.w r1, #0x80000000 :: rd 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+teq.w r1, #0xff000000 :: rd 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+teq.w r1, #0x0dd00000 :: rd 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+(T3) SUB{S}.W Rd, Rn, #constT [allegedly]
+subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sub.w  r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sub.w  r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sub.w  r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sub.w  r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T3) RSB{S}.W Rd, Rn, #constT [allegedly]
+rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0          :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0          :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+rsb.w  r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0          :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0          :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0          :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0          :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+rsb.w  r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0          :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0          :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0          :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0          :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+rsb.w  r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0          :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0          :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0          :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0          :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+rsb.w  r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0xee00ee00 :: rd 0xbcbf94d9 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0          :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0          :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0x80000000 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, #0x0dd00000 :: rd 0x8dd00001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T3) ADC{S}.W Rd, Rn, #constT [allegedly]
+adcs.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0x20000000   C 
+adcs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+adcs.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adc.w  r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0x20000000   C 
+adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0x20000000   C 
+adcs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+adcs.w r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adc.w  r1, r2, #0xffffffff :: rd 0x31415926 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0xee00ee00 :: rd 0x1f424727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, #0x0dd00000 :: rd 0x8dcfffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+adcs.w r1, r2, #255        :: rd 0x00000100 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, #0          :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, #1          :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, #0          :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adc.w  r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #255        :: rd 0x00000100 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0          :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #1          :: rd 0x00000002 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0          :: rd 0x80000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x20000000   C 
+adcs.w r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 3, cpsr 0x20000000   C 
+adcs.w r1, r2, #255        :: rd 0x00000100 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, #0          :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, #1          :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, #0          :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adc.w  r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0xee00ee00 :: rd 0x1f424728 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #255        :: rd 0x00000100 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0          :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #1          :: rd 0x00000002 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0x80000000 :: rd 0x80000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0          :: rd 0x80000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0x80000000 :: rd 0x00000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0xff000000 :: rd 0x7f000001 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, #0x0dd00000 :: rd 0x8dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T3) SBC{S}.W Rd, Rn, #constT [allegedly]
+sbcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, #255        :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, #1          :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0          :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+sbcs.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, #0          :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sbc.w  r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #255        :: rd 0xffffff00 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #1          :: rd 0xfffffffe rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0          :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0          :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, #255        :: rd 0xffffff00 rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, #1          :: rd 0xfffffffe rm 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0          :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+sbcs.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, #0          :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sbc.w  r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0xee00ee00 :: rd 0x43406b26 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #255        :: rd 0xffffff00 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #1          :: rd 0xfffffffe rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0          :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0          :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0x80000000 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0xff000000 :: rd 0x80ffffff rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, #0x0dd00000 :: rd 0x722ffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sbc.w  r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sbc.w  r1, r2, #0xffffffff :: rd 0x31415928 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0xee00ee00 :: rd 0x43406b27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #255        :: rd 0xffffff01 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #1          :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #-1         :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0xff000000 :: rd 0x81000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T3) AND{S}.W Rd, Rn, #constT [allegedly]
+ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+and.w  r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+and.w  r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+and.w  r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, #0          :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+ands.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+ands.w r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+and.w  r1, r2, #0xffffffff :: rd 0x31415927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0xee00ee00 :: rd 0x20004800 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0          :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0xff000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, #0x0dd00000 :: rd 0x0dd00000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T3) ORR{S}.W Rd, Rn, #constT [allegedly]
+orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+orr.w  r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+orr.w  r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+orr.w  r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+orr.w  r1, r2, #0xffffffff :: rd 0xffffffff rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0xee00ee00 :: rd 0xff41ff27 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0xff000000 :: rd 0xff000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, #0x0dd00000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T3) EOR{S}.W Rd, Rn, #constT [allegedly]
+eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+eor.w  r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+eor.w  r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+eor.w  r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+eor.w  r1, r2, #0xffffffff :: rd 0xcebea6d8 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0xee00ee00 :: rd 0xdf41b727 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #255        :: rd 0x000000ff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #1          :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #-1         :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0x80000000 :: rd 0x80000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0x80000000 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0xff000000 :: rd 0x7f000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T3) BIC{S}.W Rd, Rn, #constT [allegedly]
+bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+bic.w  r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+bic.w  r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+bic.w  r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+bic.w  r1, r2, #0xffffffff :: rd 0x00000000 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0xee00ee00 :: rd 0x11411127 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #255        :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0          :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #1          :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0          :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #-1         :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0          :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0x80000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0x80000000 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0xff000000 :: rd 0x00000000 rm 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, #0x0dd00000 :: rd 0x722fffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ADD{S}.W Rd, Rn, Rm, {shift}
+adds.w r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+add.w  r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+add.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adds.w r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+add.w  r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+add.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adds.w r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+add.w  r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+add.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adds.w r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+add.w  r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x40000000  Z  
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x40000000  Z  
+adds.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adds.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+add.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+adds.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+adds.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+adds.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+add.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adds.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+adds.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+adds.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adds.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x00000000     
+adds.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adds.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x00000000     
+add.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+add.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+SUBB{S}.W Rd, Rn, Rm, {shift}
+subs.w r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sub.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+subs.w r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sub.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+subs.w r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sub.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+subs.w r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+subs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+sub.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sub.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+subs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+subs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+subs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+subs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+subs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+subs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sub.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sub.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+RSB{S}.W Rd, Rn, Rm, {shift}
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #1  :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x90000000 N  V
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #1  :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x60000000  ZC 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #1  :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x90000000 N  V
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x1ceed529 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0xf5d6be01 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0xe24ab26d rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0xcebef509 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #1  :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xfceed529 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xda52a6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xcebea6d9 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x1a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xcebfd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xcebea6da rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x65d6be01 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0x9a4ab26d rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0xcebdd509 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsbs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+rsb.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsbs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+rsbs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+rsbs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+rsbs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+rsb.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+rsb.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ADC{S}.W Rd, Rn, Rm, {shift}
+adcs.w r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adcs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x70000000  ZCV
+adcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000  ZCV
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+adcs.w r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7f718777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0x5859704f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0x44cd64bb rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x3141a757 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x5f718777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x3cd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0x7ccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x31428757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0xc859704f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0xfccd64bb rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x31408757 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x40000000  Z  
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000  Z  
+adcs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adcs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+adcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffd rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fff7fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+adcs.w r1, r2, r3, lsl #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+adcs.w r1, r2, r3, lsl #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7f718778 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x58597050 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x44cd64bc rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x3141a758 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x5f718778 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x3cd55928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x7ccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x31428758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x31415929 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0xc8597050 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0xfccd64bc rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x31408758 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000002 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x00000000     
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000003 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00008001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0xffff8001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00020000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+adcs.w r1, r2, r3, asr #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x00010001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x00000002 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x80000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0xc0000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0xffff0001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0xc0000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80010001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000002 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+adcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+adc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fff8001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+adcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+adcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+adc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+adc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+SBC{S}.W Rd, Rn, Rm, {shift}
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x60000000  ZC 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x30000000   CV
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000  ZCV
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000  ZCV
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x70000000  ZCV
+sbcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x30000000   CV
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xe3112ad6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0x0a2941fe rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0x1db54d92 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x31410af6 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x31415926 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x03112ad6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x25ad5926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xe5b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x31402af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x31415925 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0x9a2941fe rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0x65b54d92 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x31422af6 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x80000000 N   
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x60000000  ZC 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x80000000 N   
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xfffffffd rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffff7fff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xa0000000 N C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000  Z  
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x40000000  Z  
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xfffe0000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x40000000  Z  
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xfffeffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xfffffffe rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x30000000   CV
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x3ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7ffefffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffd rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0xfffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0xbffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x8000fffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+sbcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80007ffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xfffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x90000000 N  V
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xe3112ad7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x0a2941ff rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x1db54d93 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x31410af7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x03112ad7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x25ad5927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xe5b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x31402af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x9a2941ff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x65b54d93 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x31422af7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x31415928 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x60000000  ZC 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x80000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xfffe0001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+sbcs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x00000000     
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+sbc.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x80000000 N   
+sbcs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+sbcs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xa0000000 N C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000002 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80008000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x40000001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7fff0001 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbcs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+sbcs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x60000000  ZC 
+sbcs.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sbcs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x20000000   C 
+sbc.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+sbc.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+AND{S}.W Rd, Rn, Rm, {shift}
+ands.w r1, r2, r3, lsl #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #1  :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+and.w  r1, r2, r3, lsl #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+ands.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+and.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+and.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ands.w r1, r2, r3, lsl #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #1  :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+and.w  r1, r2, r3, lsl #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+and.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+and.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ands.w r1, r2, r3, lsl #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, asr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsl #1  :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, asr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+and.w  r1, r2, r3, lsl #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+ands.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+and.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+ands.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+and.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ands.w r1, r2, r3, lsl #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, asr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000800 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x21001120 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x11000904 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00004820 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsl #1  :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, asr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+and.w  r1, r2, r3, lsl #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x20000800 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x01000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00010820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x11001120 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x01000904 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x31410820 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+ands.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+and.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+ands.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+ands.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+ands.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+and.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ands.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+ands.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+ands.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+ands.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+and.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+and.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ORR{S}.W Rd, Rn, Rm, {shift}
+orrs.w r1, r2, r3, lsl #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #1  :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+orr.w  r1, r2, r3, lsl #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #1  :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #1  :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+orr.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orr.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+orrs.w r1, r2, r3, lsl #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #1  :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+orr.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orr.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+orrs.w r1, r2, r3, lsl #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+orr.w  r1, r2, r3, lsl #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #1  :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+orrs.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+orr.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orr.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+orrs.w r1, r2, r3, lsl #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x7f717f77 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0x37595f2f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0x33cd5bb7 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0x31415f37 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #1  :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x3f717f77 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x3bd55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7bcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x31417f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0xb7595f2f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0xfbcd5bb7 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff7f37 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+orrs.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orr.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orrs.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+orrs.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+orrs.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orrs.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+orr.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+orr.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+EOR{S}.W Rd, Rn, Rm, {shift}
+eors.w r1, r2, r3, lsl #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #1  :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+eor.w  r1, r2, r3, lsl #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #1  :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #1  :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #1  :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eor.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+eors.w r1, r2, r3, lsl #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #1  :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #1  :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #1  :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #1  :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eor.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+eors.w r1, r2, r3, lsl #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #1  :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+eor.w  r1, r2, r3, lsl #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #1  :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #1  :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #1  :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+eors.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+eors.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eor.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+eors.w r1, r2, r3, lsl #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #1  :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7f717777 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0x16594e0f rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0x22cd52b3 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x31411717 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #1  :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #1  :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #1  :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x1f717777 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x3ad55927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x7acd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x31407717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0xa6594e0f rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0xfacd52b3 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0xcebe7717 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0xcebea6d8 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000002 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00008000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0xfffffffe rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0xffff8000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x7fffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x0001ffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+eors.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x00010000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0xc0000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0xffff0000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0xc0000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x80010000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000001 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+eors.w r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eor.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x7ffffffe rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x7fff8000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0xbfffffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x8000ffff rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eors.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+eors.w r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+eors.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+eors.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+eors.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+eor.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #1  :: rd 0x80000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #15 :: rd 0x80007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+eor.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+BIC{S}.W Rd, Rn, Rm, {shift}
+bics.w r1, r2, r3, lsl #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #1  :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0x00000000     
+bic.w  r1, r2, r3, lsl #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #1  :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bic.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+bic.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+bic.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bic.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bics.w r1, r2, r3, lsl #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #1  :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0x10000000    V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #1  :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bic.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+bic.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bic.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+bics.w r1, r2, r3, lsl #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #1  :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0x00000000     
+bic.w  r1, r2, r3, lsl #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #1  :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x00000000     
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bic.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+bic.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0x40000000  Z  
+bic.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x40000000  Z  
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+bic.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+bics.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bic.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+bics.w r1, r2, r3, lsl #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #1  :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0x10000000    V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x31415127 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x10414807 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x20415023 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x31411107 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x31415927 rm 0x31415927, rn 0x27181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #1  :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x11415127 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x30415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x31415927 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x31405107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x31415926 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x20414807 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x30415023 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x00005107 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x31415927, rn 0x97181728, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x10000000    V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bic.w  r1, r2, r3, lsl #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x00000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x80000000, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0x50000000  Z V
+bic.w  r1, r2, r3, lsl #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x7ffeffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x7ffffffe rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x7fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x3fffffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x0000ffff rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x00000000 rm 0x7fffffff, rn 0x80000000, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x50000000  Z V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bics.w r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+bic.w  r1, r2, r3, lsl #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x00000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x80000000 rm 0x80000000, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bics.w r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+bics.w r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+bics.w r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bics.w r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+bic.w  r1, r2, r3, lsl #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #1  :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #15 :: rd 0x00007fff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, lsr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #0  :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #1  :: rd 0x40000000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #15 :: rd 0x7fff0000 rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+bic.w  r1, r2, r3, asr #31 :: rd 0x7fffffff rm 0x7fffffff, rn 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T?) LSL{S}.W Rd, Rn, Rm
+lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x80000000 N   
+lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0x80000000 N   
+lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x20000000   C 
+lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C 
+lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x60000000  ZC 
+lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0x40000000  Z  
+lsl.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w  r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w  r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w  r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w  r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w  r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ  
+lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x90000000 N  V
+lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0x90000000 N  V
+lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x30000000   CV
+lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV
+lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x70000000  ZCV
+lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0x50000000  Z V
+lsl.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w  r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w  r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w  r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w  r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w  r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
+lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x80000000 N   
+lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0x80000000 N   
+lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x20000000   C 
+lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C 
+lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x60000000  ZC 
+lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0x40000000  Z  
+lsl.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w  r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w  r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w  r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w  r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w  r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC 
+lsls.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+lsls.w r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0x10000000    V
+lsls.w r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x90000000 N  V
+lsls.w r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0x90000000 N  V
+lsls.w r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x30000000   CV
+lsls.w r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV
+lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x70000000  ZCV
+lsls.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0x50000000  Z V
+lsl.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w  r1, r2, r3 :: rd 0x6282b24e rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w  r1, r2, r3 :: rd 0xc505649c rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w  r1, r2, r3 :: rd 0xac938000 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w  r1, r2, r3 :: rd 0x59270000 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w  r1, r2, r3 :: rd 0x80000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
+(T?) LSR{S}.W Rd, Rn, Rm
+lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x20000000   C 
+lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0x20000000   C 
+lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x00000000     
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0x40000000  Z  
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x40000000  Z  
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0x40000000  Z  
+lsr.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w  r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w  r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w  r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w  r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ  
+lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0x30000000   CV
+lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x30000000   CV
+lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0x30000000   CV
+lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x10000000    V
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0x50000000  Z V
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x50000000  Z V
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0x50000000  Z V
+lsr.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w  r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w  r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w  r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w  r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
+lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x00000000     
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0x40000000  Z  
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x40000000  Z  
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0x40000000  Z  
+lsr.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w  r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w  r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w  r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w  r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC 
+lsrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x10000000    V
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0x50000000  Z V
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x50000000  Z V
+lsrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0x50000000  Z V
+lsr.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w  r1, r2, r3 :: rd 0x18a0ac93 rm 0x31415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w  r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w  r1, r2, r3 :: rd 0x00006282 rm 0x31415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w  r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
+(T?) ASR{S}.W Rd, Rn, Rm
+asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0x20000000   C 
+asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 0, cpsr 0xa0000000 N C 
+asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0x00000000     
+asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 0, cpsr 0x80000000 N   
+asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0x40000000  Z  
+asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 0, cpsr 0xa0000000 N C 
+asr.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w  r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w  r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w  r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w  r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w  r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w  r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ  
+asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0x30000000   CV
+asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 1, cpsr 0xb0000000 N CV
+asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0x10000000    V
+asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 1, cpsr 0x90000000 N  V
+asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0x50000000  Z V
+asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV
+asr.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w  r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w  r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w  r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w  r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w  r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w  r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
+asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0x20000000   C 
+asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 2, cpsr 0xa0000000 N C 
+asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0x00000000     
+asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 2, cpsr 0x80000000 N   
+asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0x40000000  Z  
+asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 2, cpsr 0xa0000000 N C 
+asr.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w  r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w  r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w  r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w  r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w  r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w  r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC 
+asrs.w r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+asrs.w r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+asrs.w r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0x30000000   CV
+asrs.w r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 3, cpsr 0xb0000000 N CV
+asrs.w r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0x10000000    V
+asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 3, cpsr 0x90000000 N  V
+asrs.w r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0x50000000  Z V
+asrs.w r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV
+asr.w  r1, r2, r3 :: rd 0x31415927 rm 0x31415927, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w  r1, r2, r3 :: rd 0xc8a0ac93 rm 0x91415927, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w  r1, r2, r3 :: rd 0x0c505649 rm 0x31415927, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w  r1, r2, r3 :: rd 0xffff2282 rm 0x91415927, rn 0x0000000f, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w  r1, r2, r3 :: rd 0x00003141 rm 0x31415927, rn 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w  r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w  r1, r2, r3 :: rd 0x00000000 rm 0x31415927, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w  r1, r2, r3 :: rd 0xffffffff rm 0x91415927, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
+MVN{S}.W Rd, Rn, shift,   and MOV{S}.W ditto
+lsls.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+lsls.w   r1, r2, #1  :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+lsls.w   r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsrs.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+lsrs.w   r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+asrs.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+asrs.w   r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+asrs.w   r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+rors.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+rors.w   r1, r2, #1  :: rd 0xbfffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsl.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #1  :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #1  :: rd 0xbfffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvns.w   r1, r2, lsl #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #1  :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+mvns.w   r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, ror #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #1  :: rd 0x40000000 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+mvn.w    r1, r2, lsl #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #1  :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #1  :: rd 0x40000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsls.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+lsls.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+lsls.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+lsls.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+rors.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+rors.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+rors.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+rors.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+lsl.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvns.w   r1, r2, lsl #0  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #1  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #0  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #1  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvn.w    r1, r2, lsl #0  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #1  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #0  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #1  :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsls.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsls.w   r1, r2, #1  :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsls.w   r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+lsrs.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+lsrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+asrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x60000000  ZC 
+asrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0x40000000  Z  
+rors.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+rors.w   r1, r2, #1  :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+rors.w   r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsl.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #1  :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #1  :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvns.w   r1, r2, lsl #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #1  :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+mvns.w   r1, r2, lsr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #1  :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvn.w    r1, r2, lsl #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #1  :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #1  :: rd 0x7fffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsls.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+lsls.w   r1, r2, #1  :: rd 0x2431579a rm 0x9218abcd, c:v-in 0, cpsr 0x20000000   C 
+lsls.w   r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+lsrs.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+lsrs.w   r1, r2, #1  :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+lsrs.w   r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+asrs.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+asrs.w   r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C 
+asrs.w   r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+asrs.w   r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+rors.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+rors.w   r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+rors.w   r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+lsl.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #1  :: rd 0x2431579a rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #1  :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvns.w   r1, r2, lsl #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+mvns.w   r1, r2, lsl #1  :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+mvns.w   r1, r2, lsr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+mvns.w   r1, r2, lsr #1  :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+mvns.w   r1, r2, asr #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+mvns.w   r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 0, cpsr 0x40000000  Z  
+mvns.w   r1, r2, ror #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0x00000000     
+mvns.w   r1, r2, ror #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 0, cpsr 0x80000000 N   
+mvn.w    r1, r2, lsl #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #1  :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #1  :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 0, cpsr 0xc0000000 NZ  
+lsls.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+lsls.w   r1, r2, #1  :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsls.w   r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsrs.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+lsrs.w   r1, r2, #1  :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+asrs.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+asrs.w   r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+asrs.w   r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+asrs.w   r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+rors.w   r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsl.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #1  :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #1  :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr.w    r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr.w    r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+ror.w    r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvns.w   r1, r2, lsl #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+mvns.w   r1, r2, lsl #1  :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+mvns.w   r1, r2, lsr #1  :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+mvns.w   r1, r2, asr #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, ror #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x40000000  Z  
+mvns.w   r1, r2, ror #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+mvn.w    r1, r2, lsl #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #1  :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #1  :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w    r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsls.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+lsls.w   r1, r2, #1  :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+lsls.w   r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsrs.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+lsrs.w   r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+asrs.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+asrs.w   r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+asrs.w   r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+rors.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+rors.w   r1, r2, #1  :: rd 0xbfffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsl.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #1  :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #1  :: rd 0xbfffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvns.w   r1, r2, lsl #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #1  :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+mvns.w   r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, ror #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #1  :: rd 0x40000000 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+mvn.w    r1, r2, lsl #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #1  :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #1  :: rd 0x40000000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsls.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+lsls.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+lsls.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+lsls.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+rors.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+rors.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+rors.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+rors.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+lsl.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvns.w   r1, r2, lsl #0  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #1  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #0  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #1  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvn.w    r1, r2, lsl #0  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #1  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #0  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #1  :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+lsls.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsls.w   r1, r2, #1  :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsls.w   r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+lsrs.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+lsrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+asrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x70000000  ZCV
+asrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0x50000000  Z V
+rors.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+rors.w   r1, r2, #1  :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+rors.w   r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsl.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #1  :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #1  :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvns.w   r1, r2, lsl #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #1  :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+mvns.w   r1, r2, lsr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #1  :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvn.w    r1, r2, lsl #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #1  :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #1  :: rd 0x7fffffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsls.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+lsls.w   r1, r2, #1  :: rd 0x2431579a rm 0x9218abcd, c:v-in 1, cpsr 0x30000000   CV
+lsls.w   r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+lsrs.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+lsrs.w   r1, r2, #1  :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+lsrs.w   r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+asrs.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+asrs.w   r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV
+asrs.w   r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+asrs.w   r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+rors.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+rors.w   r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+rors.w   r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+lsl.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #1  :: rd 0x2431579a rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #1  :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvns.w   r1, r2, lsl #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+mvns.w   r1, r2, lsl #1  :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+mvns.w   r1, r2, lsr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+mvns.w   r1, r2, lsr #1  :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+mvns.w   r1, r2, asr #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+mvns.w   r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 1, cpsr 0x50000000  Z V
+mvns.w   r1, r2, ror #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0x10000000    V
+mvns.w   r1, r2, ror #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 1, cpsr 0x90000000 N  V
+mvn.w    r1, r2, lsl #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #1  :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #1  :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 1, cpsr 0xd0000000 NZ V
+lsls.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+lsls.w   r1, r2, #1  :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsls.w   r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsrs.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+lsrs.w   r1, r2, #1  :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+asrs.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+asrs.w   r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+asrs.w   r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+asrs.w   r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+rors.w   r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsl.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #1  :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #1  :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsr.w    r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr.w    r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+ror.w    r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvns.w   r1, r2, lsl #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+mvns.w   r1, r2, lsl #1  :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+mvns.w   r1, r2, lsr #1  :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+mvns.w   r1, r2, asr #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, ror #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x50000000  Z V
+mvns.w   r1, r2, ror #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+mvn.w    r1, r2, lsl #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #1  :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #1  :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w    r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsls.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+lsls.w   r1, r2, #1  :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0x80000000 N   
+lsls.w   r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsrs.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+asrs.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+asrs.w   r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+asrs.w   r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+rors.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+rors.w   r1, r2, #1  :: rd 0xbfffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsl.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #1  :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #1  :: rd 0xbfffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvns.w   r1, r2, lsl #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsl #1  :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x00000000     
+mvns.w   r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, ror #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, ror #1  :: rd 0x40000000 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+mvn.w    r1, r2, lsl #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #1  :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #1  :: rd 0x40000000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsls.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+lsls.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+lsls.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+lsls.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+lsrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+asrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+rors.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+rors.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+rors.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+rors.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+lsl.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvns.w   r1, r2, lsl #0  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsl #1  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #0  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, ror #1  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0x80000000 N   
+mvn.w    r1, r2, lsl #0  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #1  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #0  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #1  :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+lsls.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+lsls.w   r1, r2, #1  :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+lsls.w   r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+lsrs.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+lsrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+asrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x60000000  ZC 
+asrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0x40000000  Z  
+rors.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+rors.w   r1, r2, #1  :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+rors.w   r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+lsl.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #1  :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #1  :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvns.w   r1, r2, lsl #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsl #1  :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+mvns.w   r1, r2, lsr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, ror #1  :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+mvn.w    r1, r2, lsl #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #1  :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #1  :: rd 0x7fffffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsls.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C 
+lsls.w   r1, r2, #1  :: rd 0x2431579a rm 0x9218abcd, c:v-in 2, cpsr 0x20000000   C 
+lsls.w   r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000     
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N   
+lsrs.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C 
+lsrs.w   r1, r2, #1  :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000     
+lsrs.w   r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000     
+asrs.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C 
+asrs.w   r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C 
+asrs.w   r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N   
+asrs.w   r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N   
+rors.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 2, cpsr 0x00000000     
+rors.w   r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 2, cpsr 0x00000000     
+lsl.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #1  :: rd 0x2431579a rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #1  :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvns.w   r1, r2, lsl #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsl #1  :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 2, cpsr 0x00000000     
+mvns.w   r1, r2, lsr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsr #1  :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, asr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, asr #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 2, cpsr 0x00000000     
+mvns.w   r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 2, cpsr 0x40000000  Z  
+mvns.w   r1, r2, ror #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N   
+mvns.w   r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 2, cpsr 0x80000000 N   
+mvn.w    r1, r2, lsl #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #1  :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #1  :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 2, cpsr 0xe0000000 NZC 
+lsls.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsls.w   r1, r2, #1  :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsls.w   r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsrs.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsrs.w   r1, r2, #1  :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+lsrs.w   r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+asrs.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+asrs.w   r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+asrs.w   r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+asrs.w   r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+rors.w   r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsl.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #1  :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #1  :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsr.w    r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr.w    r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+ror.w    r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvns.w   r1, r2, lsl #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, lsl #1  :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+mvns.w   r1, r2, lsr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, lsr #1  :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w   r1, r2, asr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, asr #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, ror #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, ror #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvns.w   r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+mvn.w    r1, r2, lsl #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #1  :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #1  :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w    r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsls.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+lsls.w   r1, r2, #1  :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0x90000000 N  V
+lsls.w   r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsrs.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+asrs.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+asrs.w   r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+asrs.w   r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+rors.w   r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+rors.w   r1, r2, #1  :: rd 0xbfffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsl.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #1  :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #15 :: rd 0xffff8000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #1  :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #15 :: rd 0x0000ffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #0  :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #1  :: rd 0xbfffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #15 :: rd 0xfffeffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #31 :: rd 0xfffffffe rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvns.w   r1, r2, lsl #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsl #1  :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x10000000    V
+mvns.w   r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, ror #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, ror #1  :: rd 0x40000000 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+mvn.w    r1, r2, lsl #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #1  :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #15 :: rd 0x00007fff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #1  :: rd 0xc0000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #15 :: rd 0xffff0000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #0  :: rd 0x80000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #1  :: rd 0x40000000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #15 :: rd 0x00010000 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #31 :: rd 0x00000001 rm 0x7fffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsls.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+lsls.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+lsls.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+lsls.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+lsrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+asrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+rors.w   r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+rors.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+rors.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+rors.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+lsl.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #0  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvns.w   r1, r2, lsl #0  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsl #1  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #0  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, ror #1  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0x90000000 N  V
+mvn.w    r1, r2, lsl #0  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #1  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #0  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #1  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #0  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #1  :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #15 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #31 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+lsls.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+lsls.w   r1, r2, #1  :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000    V
+lsls.w   r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 3, cpsr 0x10000000    V
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+lsrs.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+lsrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+lsrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+asrs.w   r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x70000000  ZCV
+asrs.w   r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+asrs.w   r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0x50000000  Z V
+rors.w   r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+rors.w   r1, r2, #1  :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 3, cpsr 0x10000000    V
+rors.w   r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000    V
+lsl.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #1  :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #15 :: rd 0x00008000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #1  :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #15 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #31 :: rd 0x00000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #0  :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #1  :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #15 :: rd 0x00020000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #31 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvns.w   r1, r2, lsl #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsl #1  :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0x10000000    V
+mvns.w   r1, r2, lsr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, ror #1  :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+mvn.w    r1, r2, lsl #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #1  :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #15 :: rd 0xffff7fff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #1  :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #15 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #31 :: rd 0xffffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #0  :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #1  :: rd 0x7fffffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #15 :: rd 0xfffdffff rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #31 :: rd 0xfffffffd rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsls.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
+lsls.w   r1, r2, #1  :: rd 0x2431579a rm 0x9218abcd, c:v-in 3, cpsr 0x30000000   CV
+lsls.w   r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000    V
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N  V
+lsrs.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
+lsrs.w   r1, r2, #1  :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000    V
+lsrs.w   r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000    V
+asrs.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
+asrs.w   r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
+asrs.w   r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N  V
+asrs.w   r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N  V
+rors.w   r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 3, cpsr 0x10000000    V
+rors.w   r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 3, cpsr 0x10000000    V
+lsl.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #1  :: rd 0x2431579a rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #15 :: rd 0x55e68000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #1  :: rd 0x490c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #15 :: rd 0x00012431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #31 :: rd 0x00000001 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #15 :: rd 0xffff2431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #31 :: rd 0xffffffff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #0  :: rd 0x9218abcd rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #1  :: rd 0xc90c55e6 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #15 :: rd 0x579b2431 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #31 :: rd 0x2431579b rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvns.w   r1, r2, lsl #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsl #1  :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 3, cpsr 0x10000000    V
+mvns.w   r1, r2, lsr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsr #1  :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, asr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, asr #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 3, cpsr 0x10000000    V
+mvns.w   r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 3, cpsr 0x50000000  Z V
+mvns.w   r1, r2, ror #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w   r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 3, cpsr 0x90000000 N  V
+mvn.w    r1, r2, lsl #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #1  :: rd 0xdbcea865 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #15 :: rd 0xaa197fff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #1  :: rd 0xb6f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #15 :: rd 0xfffedbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #31 :: rd 0xfffffffe rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #15 :: rd 0x0000dbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #31 :: rd 0x00000000 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #0  :: rd 0x6de75432 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #1  :: rd 0x36f3aa19 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #15 :: rd 0xa864dbce rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #31 :: rd 0xdbcea864 rm 0x9218abcd, c:v-in 3, cpsr 0xf0000000 NZCV
+lsls.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsls.w   r1, r2, #1  :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsls.w   r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsls.w   r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsrs.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsrs.w   r1, r2, #1  :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+lsrs.w   r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+asrs.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+asrs.w   r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+asrs.w   r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+asrs.w   r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+rors.w   r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsl.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #1  :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #15 :: rd 0xffff8000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl.w    r1, r2, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #1  :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #15 :: rd 0x0001ffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsr.w    r1, r2, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr.w    r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #0  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #1  :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #15 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+ror.w    r1, r2, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvns.w   r1, r2, lsl #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, lsl #1  :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+mvns.w   r1, r2, lsr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, lsr #1  :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w   r1, r2, asr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, asr #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, ror #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, ror #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvns.w   r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+mvn.w    r1, r2, lsl #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #1  :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #15 :: rd 0x00007fff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsl #31 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #1  :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #15 :: rd 0xfffe0000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, lsr #31 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, asr #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #0  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #1  :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #15 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w    r1, r2, ror #31 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+(T?) TST.W Rn, Rm, {shift}
+tst.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x20000000   C 
+tst.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+tst.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+tst.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+tst.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N   
+tst.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x40000000  Z  
+tst.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+tst.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+tst.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x30000000   CV
+tst.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000    V
+tst.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000    V
+tst.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000    V
+tst.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x90000000 N  V
+tst.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x50000000  Z V
+tst.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x90000000 N  V
+tst.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+tst.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x20000000   C 
+tst.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+tst.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+tst.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+tst.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+tst.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+tst.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+tst.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+tst.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N   
+tst.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x40000000  Z  
+tst.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+tst.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+tst.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x30000000   CV
+tst.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000    V
+tst.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000    V
+tst.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000    V
+tst.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+tst.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+tst.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+tst.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x50000000  Z V
+tst.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x90000000 N  V
+tst.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x50000000  Z V
+tst.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x90000000 N  V
+tst.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+(T?) TEQ.W Rn, Rm, {shift}
+teq.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x20000000   C 
+teq.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+teq.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N   
+teq.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+teq.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+teq.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+teq.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+teq.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+teq.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x00000000     
+teq.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N   
+teq.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x00000000     
+teq.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+teq.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x30000000   CV
+teq.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000    V
+teq.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x90000000 N  V
+teq.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x10000000    V
+teq.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+teq.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+teq.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+teq.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+teq.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x10000000    V
+teq.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x90000000 N  V
+teq.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x10000000    V
+teq.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x30000000   CV
+teq.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x20000000   C 
+teq.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+teq.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N   
+teq.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+teq.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+teq.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+teq.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+teq.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+teq.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x00000000     
+teq.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N   
+teq.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x00000000     
+teq.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+teq.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x30000000   CV
+teq.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000    V
+teq.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x90000000 N  V
+teq.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x10000000    V
+teq.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000    V
+teq.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000    V
+teq.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000    V
+teq.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x10000000    V
+teq.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x10000000    V
+teq.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x90000000 N  V
+teq.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x10000000    V
+teq.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+(T?) CMP.W Rn, Rm, {shift}
+cmp.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N   
+cmp.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N   
+cmp.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+cmp.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N   
+cmp.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x30000000   CV
+cmp.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+cmp.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 0, cpsr 0x60000000  ZC 
+cmp.w  r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0x60000000  ZC 
+cmp.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N   
+cmp.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N   
+cmp.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000     
+cmp.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N   
+cmp.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+cmp.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+cmp.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x30000000   CV
+cmp.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+cmp.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 1, cpsr 0x60000000  ZC 
+cmp.w  r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 1, cpsr 0x60000000  ZC 
+cmp.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N   
+cmp.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N   
+cmp.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+cmp.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N   
+cmp.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+cmp.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+cmp.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x30000000   CV
+cmp.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+cmp.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 2, cpsr 0x60000000  ZC 
+cmp.w  r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 2, cpsr 0x60000000  ZC 
+cmp.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N   
+cmp.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N   
+cmp.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000     
+cmp.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N   
+cmp.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+cmp.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+cmp.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x30000000   CV
+cmp.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+cmp.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x20000000   C 
+cmp.w  r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 3, cpsr 0x60000000  ZC 
+cmp.w  r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 3, cpsr 0x60000000  ZC 
+(T?) CMN.W Rn, Rm, {shift}
+cmn.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+cmn.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+cmn.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x80000000 N   
+cmn.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 0, cpsr 0x00000000     
+cmn.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+cmn.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x30000000   CV
+cmn.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 0, cpsr 0x80000000 N   
+cmn.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 0, cpsr 0x30000000   CV
+cmn.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 0, cpsr 0x30000000   CV
+cmn.w  r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 0, cpsr 0x00000000     
+cmn.w  r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0x90000000 N  V
+cmn.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000     
+cmn.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000     
+cmn.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x80000000 N   
+cmn.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 1, cpsr 0x00000000     
+cmn.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+cmn.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+cmn.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+cmn.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 1, cpsr 0x00000000     
+cmn.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x30000000   CV
+cmn.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 1, cpsr 0x80000000 N   
+cmn.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 1, cpsr 0x30000000   CV
+cmn.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 1, cpsr 0x30000000   CV
+cmn.w  r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 1, cpsr 0x00000000     
+cmn.w  r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 1, cpsr 0x90000000 N  V
+cmn.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+cmn.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+cmn.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x80000000 N   
+cmn.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 2, cpsr 0x00000000     
+cmn.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+cmn.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+cmn.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+cmn.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 2, cpsr 0x00000000     
+cmn.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x30000000   CV
+cmn.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 2, cpsr 0x80000000 N   
+cmn.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 2, cpsr 0x30000000   CV
+cmn.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 2, cpsr 0x30000000   CV
+cmn.w  r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 2, cpsr 0x00000000     
+cmn.w  r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 2, cpsr 0x90000000 N  V
+cmn.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000     
+cmn.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000     
+cmn.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x80000000 N   
+cmn.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x99887766, c:v-in 3, cpsr 0x00000000     
+cmn.w  r1, r2, lsl #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+cmn.w  r1, r2, lsr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+cmn.w  r1, r2, asr #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+cmn.w  r1, r2, ror #1 :: rd 0x11223344 rm 0x00000000, c:v-in 3, cpsr 0x00000000     
+cmn.w  r1, r2, lsl #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x30000000   CV
+cmn.w  r1, r2, lsr #1 :: rd 0x91223344 rm 0x40000000, c:v-in 3, cpsr 0x80000000 N   
+cmn.w  r1, r2, asr #1 :: rd 0x91223344 rm 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+cmn.w  r1, r2, ror #1 :: rd 0x91223344 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+cmn.w  r1, r2, lsr #2 :: rd 0x15555555 rm 0x55555555, c:v-in 3, cpsr 0x00000000     
+cmn.w  r1, r2, ror #1 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 3, cpsr 0x90000000 N  V
+(T2) MOV{S}.W Rd, #constT
+movs.w  r9, 0x00000000 :: rd 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+movs.w  r9, 0x000000FF :: rd 0x000000ff, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x0000007F :: rd 0x0000007f, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x007F007F :: rd 0x007f007f, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x43434343 :: rd 0x43434343, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x93939393 :: rd 0x93939393, c:v-in 0, cpsr 0x80000000 N   
+movs.w  r9, 0x93000000 :: rd 0x93000000, c:v-in 0, cpsr 0xa0000000 N C 
+movs.w  r9, 0x43000000 :: rd 0x43000000, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x09300000 :: rd 0x09300000, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x04300000 :: rd 0x04300000, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x00930000 :: rd 0x00930000, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x00430000 :: rd 0x00430000, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x00000930 :: rd 0x00000930, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x00000430 :: rd 0x00000430, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x00000093 :: rd 0x00000093, c:v-in 0, cpsr 0x00000000     
+movs.w  r9, 0x00000043 :: rd 0x00000043, c:v-in 0, cpsr 0x00000000     
+mov.w   r9, 0x00000000 :: rd 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x000000FF :: rd 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x0000007F :: rd 0x0000007f, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x007F007F :: rd 0x007f007f, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x43434343 :: rd 0x43434343, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x93939393 :: rd 0x93939393, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x93000000 :: rd 0x93000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x43000000 :: rd 0x43000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x09300000 :: rd 0x09300000, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x04300000 :: rd 0x04300000, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x00930000 :: rd 0x00930000, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x00430000 :: rd 0x00430000, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x00000930 :: rd 0x00000930, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x00000430 :: rd 0x00000430, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x00000093 :: rd 0x00000093, c:v-in 0, cpsr 0xc0000000 NZ  
+mov.w   r9, 0x00000043 :: rd 0x00000043, c:v-in 0, cpsr 0xc0000000 NZ  
+movs.w  r9, 0x00000000 :: rd 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+movs.w  r9, 0x000000FF :: rd 0x000000ff, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x0000007F :: rd 0x0000007f, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x007F007F :: rd 0x007f007f, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x43434343 :: rd 0x43434343, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x93939393 :: rd 0x93939393, c:v-in 1, cpsr 0x90000000 N  V
+movs.w  r9, 0x93000000 :: rd 0x93000000, c:v-in 1, cpsr 0xb0000000 N CV
+movs.w  r9, 0x43000000 :: rd 0x43000000, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x09300000 :: rd 0x09300000, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x04300000 :: rd 0x04300000, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x00930000 :: rd 0x00930000, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x00430000 :: rd 0x00430000, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x00000930 :: rd 0x00000930, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x00000430 :: rd 0x00000430, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x00000093 :: rd 0x00000093, c:v-in 1, cpsr 0x10000000    V
+movs.w  r9, 0x00000043 :: rd 0x00000043, c:v-in 1, cpsr 0x10000000    V
+mov.w   r9, 0x00000000 :: rd 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x000000FF :: rd 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x0000007F :: rd 0x0000007f, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x007F007F :: rd 0x007f007f, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x43434343 :: rd 0x43434343, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x93939393 :: rd 0x93939393, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x93000000 :: rd 0x93000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x43000000 :: rd 0x43000000, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x09300000 :: rd 0x09300000, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x04300000 :: rd 0x04300000, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x00930000 :: rd 0x00930000, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x00430000 :: rd 0x00430000, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x00000930 :: rd 0x00000930, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x00000430 :: rd 0x00000430, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x00000093 :: rd 0x00000093, c:v-in 1, cpsr 0xd0000000 NZ V
+mov.w   r9, 0x00000043 :: rd 0x00000043, c:v-in 1, cpsr 0xd0000000 NZ V
+movs.w  r9, 0x00000000 :: rd 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+movs.w  r9, 0x000000FF :: rd 0x000000ff, c:v-in 2, cpsr 0x20000000   C 
+movs.w  r9, 0x0000007F :: rd 0x0000007f, c:v-in 2, cpsr 0x20000000   C 
+movs.w  r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 2, cpsr 0x20000000   C 
+movs.w  r9, 0x007F007F :: rd 0x007f007f, c:v-in 2, cpsr 0x20000000   C 
+movs.w  r9, 0x43434343 :: rd 0x43434343, c:v-in 2, cpsr 0x20000000   C 
+movs.w  r9, 0x93939393 :: rd 0x93939393, c:v-in 2, cpsr 0xa0000000 N C 
+movs.w  r9, 0x93000000 :: rd 0x93000000, c:v-in 2, cpsr 0xa0000000 N C 
+movs.w  r9, 0x43000000 :: rd 0x43000000, c:v-in 2, cpsr 0x00000000     
+movs.w  r9, 0x09300000 :: rd 0x09300000, c:v-in 2, cpsr 0x00000000     
+movs.w  r9, 0x04300000 :: rd 0x04300000, c:v-in 2, cpsr 0x00000000     
+movs.w  r9, 0x00930000 :: rd 0x00930000, c:v-in 2, cpsr 0x00000000     
+movs.w  r9, 0x00430000 :: rd 0x00430000, c:v-in 2, cpsr 0x00000000     
+movs.w  r9, 0x00000930 :: rd 0x00000930, c:v-in 2, cpsr 0x00000000     
+movs.w  r9, 0x00000430 :: rd 0x00000430, c:v-in 2, cpsr 0x00000000     
+movs.w  r9, 0x00000093 :: rd 0x00000093, c:v-in 2, cpsr 0x20000000   C 
+movs.w  r9, 0x00000043 :: rd 0x00000043, c:v-in 2, cpsr 0x20000000   C 
+mov.w   r9, 0x00000000 :: rd 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x000000FF :: rd 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x0000007F :: rd 0x0000007f, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x007F007F :: rd 0x007f007f, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x43434343 :: rd 0x43434343, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x93939393 :: rd 0x93939393, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x93000000 :: rd 0x93000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x43000000 :: rd 0x43000000, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x09300000 :: rd 0x09300000, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x04300000 :: rd 0x04300000, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x00930000 :: rd 0x00930000, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x00430000 :: rd 0x00430000, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x00000930 :: rd 0x00000930, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x00000430 :: rd 0x00000430, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x00000093 :: rd 0x00000093, c:v-in 2, cpsr 0xe0000000 NZC 
+mov.w   r9, 0x00000043 :: rd 0x00000043, c:v-in 2, cpsr 0xe0000000 NZC 
+movs.w  r9, 0x00000000 :: rd 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+movs.w  r9, 0x000000FF :: rd 0x000000ff, c:v-in 3, cpsr 0x30000000   CV
+movs.w  r9, 0x0000007F :: rd 0x0000007f, c:v-in 3, cpsr 0x30000000   CV
+movs.w  r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 3, cpsr 0x30000000   CV
+movs.w  r9, 0x007F007F :: rd 0x007f007f, c:v-in 3, cpsr 0x30000000   CV
+movs.w  r9, 0x43434343 :: rd 0x43434343, c:v-in 3, cpsr 0x30000000   CV
+movs.w  r9, 0x93939393 :: rd 0x93939393, c:v-in 3, cpsr 0xb0000000 N CV
+movs.w  r9, 0x93000000 :: rd 0x93000000, c:v-in 3, cpsr 0xb0000000 N CV
+movs.w  r9, 0x43000000 :: rd 0x43000000, c:v-in 3, cpsr 0x10000000    V
+movs.w  r9, 0x09300000 :: rd 0x09300000, c:v-in 3, cpsr 0x10000000    V
+movs.w  r9, 0x04300000 :: rd 0x04300000, c:v-in 3, cpsr 0x10000000    V
+movs.w  r9, 0x00930000 :: rd 0x00930000, c:v-in 3, cpsr 0x10000000    V
+movs.w  r9, 0x00430000 :: rd 0x00430000, c:v-in 3, cpsr 0x10000000    V
+movs.w  r9, 0x00000930 :: rd 0x00000930, c:v-in 3, cpsr 0x10000000    V
+movs.w  r9, 0x00000430 :: rd 0x00000430, c:v-in 3, cpsr 0x10000000    V
+movs.w  r9, 0x00000093 :: rd 0x00000093, c:v-in 3, cpsr 0x30000000   CV
+movs.w  r9, 0x00000043 :: rd 0x00000043, c:v-in 3, cpsr 0x30000000   CV
+mov.w   r9, 0x00000000 :: rd 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x000000FF :: rd 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x0000007F :: rd 0x0000007f, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x00FF00FF :: rd 0x00ff00ff, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x007F007F :: rd 0x007f007f, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x43434343 :: rd 0x43434343, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x93939393 :: rd 0x93939393, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x93000000 :: rd 0x93000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x43000000 :: rd 0x43000000, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x09300000 :: rd 0x09300000, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x04300000 :: rd 0x04300000, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x00930000 :: rd 0x00930000, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x00430000 :: rd 0x00430000, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x00000930 :: rd 0x00000930, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x00000430 :: rd 0x00000430, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x00000093 :: rd 0x00000093, c:v-in 3, cpsr 0xf0000000 NZCV
+mov.w   r9, 0x00000043 :: rd 0x00000043, c:v-in 3, cpsr 0xf0000000 NZCV
+(T2) MVN{S}.W Rd, #constT
+mvns.w  r9, 0x00000000 :: rd 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x000000FF :: rd 0xffffff00, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x0000007F :: rd 0xffffff80, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x007F007F :: rd 0xff80ff80, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 0, cpsr 0x00000000     
+mvns.w  r9, 0x93000000 :: rd 0x6cffffff, c:v-in 0, cpsr 0x20000000   C 
+mvns.w  r9, 0x43000000 :: rd 0xbcffffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x00930000 :: rd 0xff6cffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x00430000 :: rd 0xffbcffff, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x00000093 :: rd 0xffffff6c, c:v-in 0, cpsr 0x80000000 N   
+mvns.w  r9, 0x00000043 :: rd 0xffffffbc, c:v-in 0, cpsr 0x80000000 N   
+mvn.w   r9, 0x00000000 :: rd 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x000000FF :: rd 0xffffff00, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x0000007F :: rd 0xffffff80, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x007F007F :: rd 0xff80ff80, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x93000000 :: rd 0x6cffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x43000000 :: rd 0xbcffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x00930000 :: rd 0xff6cffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x00430000 :: rd 0xffbcffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x00000093 :: rd 0xffffff6c, c:v-in 0, cpsr 0xc0000000 NZ  
+mvn.w   r9, 0x00000043 :: rd 0xffffffbc, c:v-in 0, cpsr 0xc0000000 NZ  
+mvns.w  r9, 0x00000000 :: rd 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x000000FF :: rd 0xffffff00, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x0000007F :: rd 0xffffff80, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x007F007F :: rd 0xff80ff80, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 1, cpsr 0x10000000    V
+mvns.w  r9, 0x93000000 :: rd 0x6cffffff, c:v-in 1, cpsr 0x30000000   CV
+mvns.w  r9, 0x43000000 :: rd 0xbcffffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00930000 :: rd 0xff6cffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00430000 :: rd 0xffbcffff, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00000093 :: rd 0xffffff6c, c:v-in 1, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00000043 :: rd 0xffffffbc, c:v-in 1, cpsr 0x90000000 N  V
+mvn.w   r9, 0x00000000 :: rd 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x000000FF :: rd 0xffffff00, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x0000007F :: rd 0xffffff80, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x007F007F :: rd 0xff80ff80, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x93000000 :: rd 0x6cffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x43000000 :: rd 0xbcffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x00930000 :: rd 0xff6cffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x00430000 :: rd 0xffbcffff, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x00000093 :: rd 0xffffff6c, c:v-in 1, cpsr 0xd0000000 NZ V
+mvn.w   r9, 0x00000043 :: rd 0xffffffbc, c:v-in 1, cpsr 0xd0000000 NZ V
+mvns.w  r9, 0x00000000 :: rd 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w  r9, 0x000000FF :: rd 0xffffff00, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w  r9, 0x0000007F :: rd 0xffffff80, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w  r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w  r9, 0x007F007F :: rd 0xff80ff80, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w  r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w  r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 2, cpsr 0x20000000   C 
+mvns.w  r9, 0x93000000 :: rd 0x6cffffff, c:v-in 2, cpsr 0x20000000   C 
+mvns.w  r9, 0x43000000 :: rd 0xbcffffff, c:v-in 2, cpsr 0x80000000 N   
+mvns.w  r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 2, cpsr 0x80000000 N   
+mvns.w  r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 2, cpsr 0x80000000 N   
+mvns.w  r9, 0x00930000 :: rd 0xff6cffff, c:v-in 2, cpsr 0x80000000 N   
+mvns.w  r9, 0x00430000 :: rd 0xffbcffff, c:v-in 2, cpsr 0x80000000 N   
+mvns.w  r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 2, cpsr 0x80000000 N   
+mvns.w  r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 2, cpsr 0x80000000 N   
+mvns.w  r9, 0x00000093 :: rd 0xffffff6c, c:v-in 2, cpsr 0xa0000000 N C 
+mvns.w  r9, 0x00000043 :: rd 0xffffffbc, c:v-in 2, cpsr 0xa0000000 N C 
+mvn.w   r9, 0x00000000 :: rd 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x000000FF :: rd 0xffffff00, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x0000007F :: rd 0xffffff80, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x007F007F :: rd 0xff80ff80, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x93000000 :: rd 0x6cffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x43000000 :: rd 0xbcffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x00930000 :: rd 0xff6cffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x00430000 :: rd 0xffbcffff, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x00000093 :: rd 0xffffff6c, c:v-in 2, cpsr 0xe0000000 NZC 
+mvn.w   r9, 0x00000043 :: rd 0xffffffbc, c:v-in 2, cpsr 0xe0000000 NZC 
+mvns.w  r9, 0x00000000 :: rd 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w  r9, 0x000000FF :: rd 0xffffff00, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w  r9, 0x0000007F :: rd 0xffffff80, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w  r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w  r9, 0x007F007F :: rd 0xff80ff80, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w  r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w  r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 3, cpsr 0x30000000   CV
+mvns.w  r9, 0x93000000 :: rd 0x6cffffff, c:v-in 3, cpsr 0x30000000   CV
+mvns.w  r9, 0x43000000 :: rd 0xbcffffff, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w  r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w  r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00930000 :: rd 0xff6cffff, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00430000 :: rd 0xffbcffff, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 3, cpsr 0x90000000 N  V
+mvns.w  r9, 0x00000093 :: rd 0xffffff6c, c:v-in 3, cpsr 0xb0000000 N CV
+mvns.w  r9, 0x00000043 :: rd 0xffffffbc, c:v-in 3, cpsr 0xb0000000 N CV
+mvn.w   r9, 0x00000000 :: rd 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x000000FF :: rd 0xffffff00, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x0000007F :: rd 0xffffff80, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x00FF00FF :: rd 0xff00ff00, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x007F007F :: rd 0xff80ff80, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x43434343 :: rd 0xbcbcbcbc, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x93939393 :: rd 0x6c6c6c6c, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x93000000 :: rd 0x6cffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x43000000 :: rd 0xbcffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x09300000 :: rd 0xf6cfffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x04300000 :: rd 0xfbcfffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x00930000 :: rd 0xff6cffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x00430000 :: rd 0xffbcffff, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x00000930 :: rd 0xfffff6cf, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x00000430 :: rd 0xfffffbcf, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x00000093 :: rd 0xffffff6c, c:v-in 3, cpsr 0xf0000000 NZCV
+mvn.w   r9, 0x00000043 :: rd 0xffffffbc, c:v-in 3, cpsr 0xf0000000 NZCV
+MOV
+mov  r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+cpy  r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mov  r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mov  r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N   
+movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000     
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x00000000     
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 1, cpsr 0x80000000 N   
+movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000  Z V
+movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 1, cpsr 0x10000000    V
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x40000000  Z  
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 2, cpsr 0x80000000 N   
+movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 2, cpsr 0x60000000  ZC 
+movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+movs r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x00000000     
+movs r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x40000000  Z  
+movs r0, r1 :: rd 0x80000000 rm 0x80000000, c:v-in 3, cpsr 0x80000000 N   
+movs r0, #0 :: rd 0x00000000 rm 0x00000000, c:v-in 3, cpsr 0x70000000  ZCV
+movs r0, #1 :: rd 0x00000001 rm 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+MVN
+mvn  r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 0, cpsr 0x00000000     
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 1, cpsr 0x10000000    V
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 2, cpsr 0x20000000   C 
+mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+mvns r0, r1 :: rd 0xffffffff rm 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+mvns r0, r1 :: rd 0x7fffffff rm 0x80000000, c:v-in 3, cpsr 0x30000000   CV
+ADD
+adds r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adds r0, r1, r2 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+adds r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+adds r0, r1, r2 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+adds r0, r1, r2 :: rd 0x00000000 rm 0x00000001, rn 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+adds r0, r1, r2 :: rd 0x80000000 rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0x90000000 N  V
+adds r0, r1, r2 :: rd 0x7fffffff rm 0x80000000, rn 0xffffffff, c:v-in 0, cpsr 0x30000000   CV
+adds r0, r1, r2 :: rd 0x80000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+ADC
+adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x40000000  Z  
+adcs r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 1, cpsr 0x40000000  Z  
+LSL
+lsl  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+LSLS
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0x60000000  ZC 
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0x80000000 N   
+lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 0, cpsr 0x80000000 N   
+lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 0, cpsr 0x60000000  ZC 
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV
+lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0x70000000  ZCV
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000  Z V
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000  Z V
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000  Z V
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000  Z V
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0x90000000 N  V
+lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 1, cpsr 0x90000000 N  V
+lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 1, cpsr 0x70000000  ZCV
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0x60000000  ZC 
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000  Z  
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 2, cpsr 0x80000000 N   
+lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 2, cpsr 0x60000000  ZC 
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0x70000000  ZCV
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000  Z V
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000  Z V
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000  Z V
+lsls r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000  Z V
+lsls r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r0, r1, r2 :: rd 0x00000001 rm 0x00000001, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+lsls r0, r1, r2 :: rd 0x00000002 rm 0x00000001, rn 0x00000001, c:v-in 3, cpsr 0x10000000    V
+lsls r0, r1, r2 :: rd 0x80000000 rm 0x00000001, rn 0x0000001f, c:v-in 3, cpsr 0x90000000 N  V
+lsls r0, r1, r2 :: rd 0x00000000 rm 0x00000002, rn 0x0000001f, c:v-in 3, cpsr 0x70000000  ZCV
+LSL immediate
+lsl  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+lsl  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl  r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl  r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl  r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl  r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
+lsl  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl  r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl  r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl  r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl  r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC 
+lsl  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl  r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl  r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl  r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl  r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+lsl  r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
+LSLS immediate
+lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 0, cpsr 0x00000000     
+lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 0, cpsr 0x80000000 N   
+lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 0, cpsr 0x60000000  ZC 
+lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 1, cpsr 0x10000000    V
+lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 1, cpsr 0x90000000 N  V
+lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 1, cpsr 0x70000000  ZCV
+lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 2, cpsr 0x00000000     
+lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 2, cpsr 0x80000000 N   
+lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 2, cpsr 0x60000000  ZC 
+lsls r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r0, r1, #1 :: rd 0xfffffffe rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r0, r1, #31 :: rd 0x80000000 rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsls r0, r1, #0 :: rd 0x00000001 rm 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+lsls r0, r1, #1 :: rd 0x00000002 rm 0x00000001, c:v-in 3, cpsr 0x10000000    V
+lsls r0, r1, #31 :: rd 0x80000000 rm 0x00000001, c:v-in 3, cpsr 0x90000000 N  V
+lsls r0, r1, #31 :: rd 0x00000000 rm 0x00000002, c:v-in 3, cpsr 0x70000000  ZCV
+LSR
+lsr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ  
+LSRS
+lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0x60000000  ZC 
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0x30000000   CV
+lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0x30000000   CV
+lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0x30000000   CV
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0x70000000  ZCV
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0x20000000   C 
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0x60000000  ZC 
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+lsrs r0, r1, r2 :: rd 0x7fffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+lsrs r0, r1, r2 :: rd 0x3fffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0x30000000   CV
+lsrs r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0x30000000   CV
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0x70000000  ZCV
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000  Z V
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000  Z V
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000  Z V
+lsrs r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000  Z V
+LSR immediate
+lsr  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ  
+lsr  r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ  
+LSRS immediate
+lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0x20000000   C 
+lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0x60000000  ZC 
+lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0x00000000     
+lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x60000000  ZC 
+lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x40000000  Z  
+lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 1, cpsr 0x30000000   CV
+lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0x70000000  ZCV
+lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 1, cpsr 0x10000000    V
+lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x70000000  ZCV
+lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x50000000  Z V
+lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 2, cpsr 0x20000000   C 
+lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0x60000000  ZC 
+lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 2, cpsr 0x00000000     
+lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x60000000  ZC 
+lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x40000000  Z  
+lsrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+lsrs r0, r1, #1 :: rd 0x7fffffff rm 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+lsrs r0, r1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 3, cpsr 0x30000000   CV
+lsrs r0, r1, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0x70000000  ZCV
+lsrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 3, cpsr 0x10000000    V
+lsrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x70000000  ZCV
+lsrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x50000000  Z V
+ASR
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 1, cpsr 0xd0000000 NZ V
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 2, cpsr 0xe0000000 NZC 
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 3, cpsr 0xf0000000 NZCV
+asr  r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 3, cpsr 0xf0000000 NZCV
+ASRS
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0x80000000 N   
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 0, cpsr 0x80000000 N   
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 0, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 0, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 0, cpsr 0x60000000  ZC 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 1, cpsr 0x90000000 N  V
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 1, cpsr 0x90000000 N  V
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 1, cpsr 0x30000000   CV
+asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 1, cpsr 0x30000000   CV
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 1, cpsr 0x70000000  ZCV
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 1, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 1, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 1, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 1, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 1, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 1, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 2, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 2, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 2, cpsr 0x60000000  ZC 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 2, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 2, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 2, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 2, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 2, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 2, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000001, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000002, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000001f, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000020, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000021, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x0000003f, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000040, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x000000ff, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000100, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+asrs r0, r1, r2 :: rd 0x3fffffff rm 0x7fffffff, rn 0x00000001, c:v-in 3, cpsr 0x30000000   CV
+asrs r0, r1, r2 :: rd 0x1fffffff rm 0x7fffffff, rn 0x00000002, c:v-in 3, cpsr 0x30000000   CV
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000001f, c:v-in 3, cpsr 0x70000000  ZCV
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000020, c:v-in 3, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000021, c:v-in 3, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x0000003f, c:v-in 3, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x00000040, c:v-in 3, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x7fffffff, rn 0x000000ff, c:v-in 3, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x7fffffff rm 0x7fffffff, rn 0x00000100, c:v-in 3, cpsr 0x30000000   CV
+asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 0, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 0, cpsr 0x60000000  ZC 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 0, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 1, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 1, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 1, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 1, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 1, cpsr 0x70000000  ZCV
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 1, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 2, cpsr 0x20000000   C 
+asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 2, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 2, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 2, cpsr 0x00000000     
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 2, cpsr 0x60000000  ZC 
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 2, cpsr 0x40000000  Z  
+asrs r0, r1, r2 :: rd 0x00000008 rm 0x00000008, rn 0x00000000, c:v-in 3, cpsr 0x30000000   CV
+asrs r0, r1, r2 :: rd 0x00000004 rm 0x00000008, rn 0x00000001, c:v-in 3, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0x00000002 rm 0x00000008, rn 0x00000002, c:v-in 3, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0x00000001 rm 0x00000008, rn 0x00000003, c:v-in 3, cpsr 0x10000000    V
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000004, c:v-in 3, cpsr 0x70000000  ZCV
+asrs r0, r1, r2 :: rd 0x00000000 rm 0x00000008, rn 0x00000005, c:v-in 3, cpsr 0x50000000  Z V
+asrs r0, r1, r2 :: rd 0xc0000000 rm 0x80000001, rn 0x00000001, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, r2 :: rd 0xe0000000 rm 0x80000001, rn 0x00000002, c:v-in 0, cpsr 0x80000000 N   
+ASR immediate
+asr  r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ  
+asr  r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0xc0000000 NZ  
+ASRS immediate
+asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0x80000000 N   
+asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xa0000000 N C 
+asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x00000000     
+asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 0, cpsr 0x20000000   C 
+asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x60000000  ZC 
+asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 0, cpsr 0x40000000  Z  
+asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 0, cpsr 0x00000000     
+asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x60000000  ZC 
+asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 0, cpsr 0x40000000  Z  
+asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0x90000000 N  V
+asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 1, cpsr 0xb0000000 N CV
+asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x10000000    V
+asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 1, cpsr 0x30000000   CV
+asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x70000000  ZCV
+asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 1, cpsr 0x50000000  Z V
+asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 1, cpsr 0x10000000    V
+asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x70000000  ZCV
+asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 1, cpsr 0x50000000  Z V
+asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 2, cpsr 0xa0000000 N C 
+asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 2, cpsr 0x20000000   C 
+asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x60000000  ZC 
+asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 2, cpsr 0x40000000  Z  
+asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 2, cpsr 0x00000000     
+asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x60000000  ZC 
+asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 2, cpsr 0x40000000  Z  
+asrs r0, r1, #0 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, #1 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 3, cpsr 0xb0000000 N CV
+asrs r0, r1, #0 :: rd 0x7fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+asrs r0, r1, #1 :: rd 0x3fffffff rm 0x7fffffff, c:v-in 3, cpsr 0x30000000   CV
+asrs r0, r1, #31 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x70000000  ZCV
+asrs r0, r1, #32 :: rd 0x00000000 rm 0x7fffffff, c:v-in 3, cpsr 0x50000000  Z V
+asrs r0, r1, #16 :: rd 0x00000001 rm 0x00010000, c:v-in 3, cpsr 0x10000000    V
+asrs r0, r1, #17 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x70000000  ZCV
+asrs r0, r1, #18 :: rd 0x00000000 rm 0x00010000, c:v-in 3, cpsr 0x50000000  Z V
+MUL
+mul  r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mul  r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+mul  r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mul  r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mul  r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+mul  r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ  
+MLA
+mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mla  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mla  r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mla  r0, r1, r2, r3 :: rd 0x00000002 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mla  r0, r1, r2, r3 :: rd 0xfffe0002 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+MLS
+mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mls  r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mls  r0, r1, r2, r3 :: rd 0x00000000 rm 0xffffffff, rn 0xffffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mls  r0, r1, r2, r3 :: rd 0x00000000 rm 0x7fffffff, rn 0x7fffffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+mls  r0, r1, r2, r3 :: rd 0x00020000 rm 0x0000ffff, rn 0x0000ffff rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+UMULL
+umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+umull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+umull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+umull  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ  
+umull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0xfffffffe, rm 0xffffffff rs 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+SMULL
+smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000000 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+smull  r0, r1, r2, r3 :: rd 0x00000000 rd2 0x00000000, rm 0x00000001 rs 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+smull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0x00000001 rs 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+smull  r0, r1, r2, r3 :: rd 0xfffe0001 rd2 0x00000000, rm 0x0000ffff rs 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ  
+smull  r0, r1, r2, r3 :: rd 0x00000001 rd2 0x00000000, rm 0xffffffff rs 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+CLZ
+clz  r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+clz  r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+clz  r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 0, cpsr 0xc0000000 NZ  
+clz  r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+clz  r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 1, cpsr 0xd0000000 NZ V
+clz  r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 1, cpsr 0xd0000000 NZ V
+clz  r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 1, cpsr 0xd0000000 NZ V
+clz  r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 1, cpsr 0xd0000000 NZ V
+clz  r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 2, cpsr 0xe0000000 NZC 
+clz  r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 2, cpsr 0xe0000000 NZC 
+clz  r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 2, cpsr 0xe0000000 NZC 
+clz  r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 2, cpsr 0xe0000000 NZC 
+clz  r0, r1 :: rd 0x00000020 rm 0x00000000, c:v-in 3, cpsr 0xf0000000 NZCV
+clz  r0, r1 :: rd 0x0000001f rm 0x00000001, c:v-in 3, cpsr 0xf0000000 NZCV
+clz  r0, r1 :: rd 0x0000001b rm 0x00000010, c:v-in 3, cpsr 0xf0000000 NZCV
+clz  r0, r1 :: rd 0x00000000 rm 0xffffffff, c:v-in 3, cpsr 0xf0000000 NZCV
+extend instructions
+uxtb r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r0, r1 :: rd 0x000000ff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r0, r1 :: rd 0x000000ff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtb r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtb r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtb r0, r1 :: rd 0xffffffff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtb r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+uxth r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+uxth r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+uxth r0, r1 :: rd 0x0000ffff rm 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ  
+uxth r0, r1 :: rd 0x0000ffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r0, r1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r0, r1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r0, r1 :: rd 0x00007fff rm 0x00007fff, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r0, r1 :: rd 0xffffffff rm 0x0000ffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r0, r1 :: rd 0xffffffff rm 0x0010ffff, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r0, r1 :: rd 0x00007fff rm 0x00107fff, c:v-in 0, cpsr 0xc0000000 NZ  
+sxth r0, r1 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r0, r1, ror #0 :: rd 0x000000ff rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r0, r1, ror #8 :: rd 0x00000000 rm 0x000000ff, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r0, r1, ror #8 :: rd 0x000000ff rm 0x0000ff00, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r0, r1, ror #16 :: rd 0x000000ff rm 0x00ff0000, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtb r0, r1, ror #24 :: rd 0x000000ff rm 0xff000000, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ BFI ------------
+bfi  r0, r1, #0, #11 :: rd 0x555552aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #1, #11 :: rd 0x55555555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #2, #11 :: rd 0x55554aa9 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #19, #11 :: rd 0x7ffd5555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #20, #11 :: rd 0x7ff55555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #21, #11 :: rd 0xfff55555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #0, #32 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #1, #31 :: rd 0xffffffff rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #29, #3 :: rd 0xf5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #30, #2 :: rd 0xd5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfi  r0, r1, #31, #1 :: rd 0xd5555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ BFC ------------
+bfc  r0, #0, #11 :: rd 0x55555000 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #1, #11 :: rd 0x55555001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #2, #11 :: rd 0x55554001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #19, #11 :: rd 0x40055555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #20, #11 :: rd 0x00055555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #21, #11 :: rd 0x00155555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #0, #32 :: rd 0x00000000 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #1, #31 :: rd 0x00000001 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #29, #3 :: rd 0x15555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #30, #2 :: rd 0x15555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+bfc  r0, #31, #1 :: rd 0x55555555 rm 0xffffffff, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ SBFX ------------
+sbfx  r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #0, #1 :: rd 0xffffffff rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #1 :: rd 0xffffffff rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #1, #11 :: rd 0xfffffd55 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #31, #1 :: rd 0xffffffff rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+sbfx  r0, r1, #30, #2 :: rd 0xfffffffe rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ UBFX ------------
+ubfx  r0, r1, #0, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #0, #1 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #1 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #1 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #0, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #0, #2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #2 :: rd 0x00000000 rm 0x00000001, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000002, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #2 :: rd 0x00000001 rm 0x00000003, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #0, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #1, #11 :: rd 0x00000555 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #2, #11 :: rd 0x000002aa rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #31, #1 :: rd 0x00000001 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+ubfx  r0, r1, #30, #2 :: rd 0x00000002 rm 0xaaaaaaaa, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ SMULL{B,T}{B,T} ------------
+smulbb r0, r1, r2 :: rd 0x00000000 rm 0x00030000, rn 0x00040000, c:v-in 0, cpsr 0xc0000000 NZ  
+smulbb r0, r1, r2 :: rd 0x00000002 rm 0x00030001, rn 0x00040002, c:v-in 0, cpsr 0xc0000000 NZ  
+smulbb r0, r1, r2 :: rd 0xc000ffff rm 0x00038001, rn 0x00047fff, c:v-in 0, cpsr 0xc0000000 NZ  
+smulbb r0, r1, r2 :: rd 0x3fff0001 rm 0x00037fff, rn 0x00047fff, c:v-in 0, cpsr 0xc0000000 NZ  
+smulbb r0, r1, r2 :: rd 0x00000001 rm 0x0003ffff, rn 0x0004ffff, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ SXTAB ------------
+sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtab r0, r1, r2, ROR #0 :: rd 0x314158c0 rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ UXTAB ------------
+uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtab r0, r1, r2, ROR #0 :: rd 0x31415940 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtab r0, r1, r2, ROR #24 :: rd 0x3141594e rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtab r0, r1, r2, ROR #16 :: rd 0x3141593f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtab r0, r1, r2, ROR #8 :: rd 0x3141594f rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtab r0, r1, r2, ROR #0 :: rd 0x314159c0 rm 0x31415927, rn 0x27182899, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ SXTAH ------------
+sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtah r0, r1, r2, ROR #8  :: rd 0x3141714f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtah r0, r1, r2, ROR #0  :: rd 0x31418140 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtah r0, r1, r2, ROR #8  :: rd 0x314171bf rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ  
+sxtah r0, r1, r2, ROR #0  :: rd 0x3140f140 rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ  
+------------ UXTAH ------------
+uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtah r0, r1, r2, ROR #8  :: rd 0x3141714f rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtah r0, r1, r2, ROR #0  :: rd 0x31418140 rm 0x31415927, rn 0x27182819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtah r0, r1, r2, ROR #24 :: rd 0x3141724e rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtah r0, r1, r2, ROR #16 :: rd 0x3141803f rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtah r0, r1, r2, ROR #8  :: rd 0x314171bf rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ  
+uxtah r0, r1, r2, ROR #0  :: rd 0x3141f140 rm 0x31415927, rn 0x27189819, c:v-in 0, cpsr 0xc0000000 NZ  

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.vgtest
new file mode 100644 (file)
index 0000000..362326d
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/arm/v6intThumb.vgtest
@@ -0,0 +1,2 @@
+prog: v6intThumb
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/cmdline2.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/cmdline2.stdout.exp
index 60e0328f2832f8b72d55474606dd47075bd22bac..caa7eb0689a3c2c1752b643837a8fc0aa12f8aaa 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/cmdline2.stdout.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/cmdline2.stdout.exp
@@ -65,8 +65,8 @@ usage: valgrind [options] prog-and-args
     (none)
 
   debugging options for all Valgrind tools:
     (none)
 
   debugging options for all Valgrind tools:

-    --stats=no|yes            show tool and core statistics [no]

     -d                        show verbose debugging output
     -d                        show verbose debugging output

+    --stats=no|yes            show tool and core statistics [no]

     --sanity-level=<number>   level of sanity checking to do [1]
     --trace-flags=<XXXXXXXX>   show generated code? (X = 0|1) [00000000]
     --profile-flags=<XXXXXXXX> ditto, but for profiling (X = 0|1) [00000000]
     --sanity-level=<number>   level of sanity checking to do [1]
     --trace-flags=<XXXXXXXX>   show generated code? (X = 0|1) [00000000]
     --profile-flags=<XXXXXXXX> ditto, but for profiling (X = 0|1) [00000000]

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/cmdline4.stderr.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/cmdline4.stderr.exp
index 1f88235fdc0208d047f614235b8bee2f0346d488..f9b9ba65855aefffa37e6365eac78da467013d7b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/cmdline4.stderr.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/cmdline4.stderr.exp
@@ -1,2 +1,2 @@
-valgrind: Bad option '--bad-bad-option'; aborting.
-valgrind: Use --help for more information.
+valgrind: Bad option: --bad-bad-option
+valgrind: Use --help for more information or consult the user manual.

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/darwin/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/darwin/Makefile.in
index c6ecb58e1f669d2980d4e4c2abe1a9c0945f25cd..a6288512f72f5aee237eb9cb9376503efb25a210 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/darwin/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/darwin/Makefile.in
@@ -117,6 +117,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -151,14 +152,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -241,7 +246,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -300,7 +307,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -315,8 +322,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/linux/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/linux/Makefile.in
index 325a633faeaf34d9f346e8659f2f0f84a84a68d3..7c1df8fa5c1da3253a509a91f59bf9b3f0651ae6 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/linux/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/linux/Makefile.in
@@ -116,6 +116,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -150,14 +151,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -240,7 +245,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -299,7 +306,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -314,8 +321,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/ppc32/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/ppc32/Makefile.in
index 8ff8fe25ea57ac7205f5df063539a27ff20469b0..d53de596f3f75ba32b2db81a3fb05eb338eaf4f6 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/ppc32/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/ppc32/Makefile.in
@@ -161,6 +161,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -195,14 +196,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -285,7 +290,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -344,7 +351,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -359,8 +366,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/ppc64/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/ppc64/Makefile.in
index 6767333a1ae333bbab5fce754f9fc5ab8c3dce40..d3eef29a5d39679ffa5e1207aed5d4f4ecdd1161 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/ppc64/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/ppc64/Makefile.in
@@ -129,6 +129,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -163,14 +164,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -253,7 +258,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -312,7 +319,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -327,8 +334,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86-linux/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86-linux/Makefile.in
index 9f44936c73eadf1a3c25784ed47ad91e80d56ffd..1203e77c2b8988348e29421a483e9c1542d479b8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86-linux/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86-linux/Makefile.in
@@ -113,6 +113,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -147,14 +148,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -237,7 +242,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -296,7 +303,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -311,8 +318,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/Makefile.am b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/Makefile.am
index 47d6a3492a0370bc9ad34c861c29faaf6b7f839c..c0f0c08ae1fbb65a59ed454477279aa499f62c29 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/Makefile.am
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/Makefile.am
@@ -17,6 +17,9 @@ endif
 # Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS, 
 # to avoid packaging screwups if 'make dist' is run on a machine
 # which failed the BUILD_SSE3_TESTS test in configure.in.
 # Explicitly include insn_sse3 even if ! BUILD_SSE3_TESTS, 
 # to avoid packaging screwups if 'make dist' is run on a machine
 # which failed the BUILD_SSE3_TESTS test in configure.in.

+
+## FIXME: move lzcnt32 to SSE4 conditionalisation, when that happens.
+

 EXTRA_DIST = \
        badseg.stderr.exp badseg.stdout.exp badseg.vgtest \
        bt_everything.stderr.exp bt_everything.stdout.exp bt_everything.vgtest \
 EXTRA_DIST = \
        badseg.stderr.exp badseg.stdout.exp badseg.vgtest \
        bt_everything.stderr.exp bt_everything.stdout.exp bt_everything.vgtest \


@@ -46,6 +49,7 @@ EXTRA_DIST = \
        jcxz.stdout.exp jcxz.stderr.exp jcxz.vgtest \
        lahf.stdout.exp lahf.stderr.exp lahf.vgtest \
        looper.stderr.exp looper.stdout.exp looper.vgtest \
        jcxz.stdout.exp jcxz.stderr.exp jcxz.vgtest \
        lahf.stdout.exp lahf.stderr.exp lahf.vgtest \
        looper.stderr.exp looper.stdout.exp looper.vgtest \

+       lzcnt32.stderr.exp lzcnt32.stdout.exp lzcnt32.vgtest \

        movx.stderr.exp movx.stdout.exp movx.vgtest \
        pushpopseg.stderr.exp pushpopseg.stdout.exp pushpopseg.vgtest \
        sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \
        movx.stderr.exp movx.stdout.exp movx.vgtest \
        pushpopseg.stderr.exp pushpopseg.stdout.exp pushpopseg.vgtest \
        sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \


@@ -53,7 +57,8 @@ EXTRA_DIST = \
        ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
        ssse3_misaligned.vgtest ssse3_misaligned.c \
        x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \
        ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
        ssse3_misaligned.vgtest ssse3_misaligned.c \
        x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \

-       yield.stderr.exp yield.stdout.exp yield.disabled
+       yield.stderr.exp yield.stdout.exp yield.disabled \
+       xadd.stdout.exp xadd.stderr.exp xadd.vgtest

 
 check_PROGRAMS = \
        badseg \
 
 check_PROGRAMS = \
        badseg \


@@ -79,12 +84,14 @@ check_PROGRAMS = \
        jcxz \
        lahf \
        looper \
        jcxz \
        lahf \
        looper \

+       lzcnt32 \

        movx \
        pushpopseg \
        sbbmisc \
        smc1 \
        x86locked \
        movx \
        pushpopseg \
        sbbmisc \
        smc1 \
        x86locked \

-       yield
+       yield \
+       xadd

 if BUILD_SSSE3_TESTS
    check_PROGRAMS += ssse3_misaligned
 endif
 if BUILD_SSSE3_TESTS
    check_PROGRAMS += ssse3_misaligned
 endif

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/Makefile.in
index 94364f5b3747774218c2087a7fe3d68c07506ae2..720dd0d1d003cb69eee28ba5c9a3c250d08cb278 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/Makefile.in
@@ -56,9 +56,10 @@ check_PROGRAMS = badseg$(EXEEXT) bt_everything$(EXEEXT) \
        cse_fail$(EXEEXT) faultstatus$(EXEEXT) fcmovnu$(EXEEXT) \
        fpu_lazy_eflags$(EXEEXT) fxtract$(EXEEXT) getseg$(EXEEXT) \
        incdec_alt$(EXEEXT) $(am__EXEEXT_3) int$(EXEEXT) jcxz$(EXEEXT) \
        cse_fail$(EXEEXT) faultstatus$(EXEEXT) fcmovnu$(EXEEXT) \
        fpu_lazy_eflags$(EXEEXT) fxtract$(EXEEXT) getseg$(EXEEXT) \
        incdec_alt$(EXEEXT) $(am__EXEEXT_3) int$(EXEEXT) jcxz$(EXEEXT) \

-       lahf$(EXEEXT) looper$(EXEEXT) movx$(EXEEXT) \
+       lahf$(EXEEXT) looper$(EXEEXT) lzcnt32$(EXEEXT) movx$(EXEEXT) \

        pushpopseg$(EXEEXT) sbbmisc$(EXEEXT) smc1$(EXEEXT) \
        pushpopseg$(EXEEXT) sbbmisc$(EXEEXT) smc1$(EXEEXT) \

-       x86locked$(EXEEXT) yield$(EXEEXT) $(am__EXEEXT_4)
+       x86locked$(EXEEXT) yield$(EXEEXT) xadd$(EXEEXT) \
+       $(am__EXEEXT_4)

 @BUILD_SSSE3_TESTS_TRUE@am__append_3 = ssse3_misaligned
 
 # Some of the tests (bug125959_x86, bug152818_x86, insn_*) need
 @BUILD_SSSE3_TESTS_TRUE@am__append_3 = ssse3_misaligned
 
 # Some of the tests (bug125959_x86, bug152818_x86, insn_*) need


@@ -178,6 +179,9 @@ lahf_LDADD = $(LDADD)
 looper_SOURCES = looper.c
 looper_OBJECTS = looper.$(OBJEXT)
 looper_LDADD = $(LDADD)
 looper_SOURCES = looper.c
 looper_OBJECTS = looper.$(OBJEXT)
 looper_LDADD = $(LDADD)

+lzcnt32_SOURCES = lzcnt32.c
+lzcnt32_OBJECTS = lzcnt32.$(OBJEXT)
+lzcnt32_LDADD = $(LDADD)

 movx_SOURCES = movx.c
 movx_OBJECTS = movx.$(OBJEXT)
 movx_LDADD = $(LDADD)
 movx_SOURCES = movx.c
 movx_OBJECTS = movx.$(OBJEXT)
 movx_LDADD = $(LDADD)


@@ -198,6 +202,9 @@ x86locked_OBJECTS = x86locked-x86locked.$(OBJEXT)
 x86locked_LDADD = $(LDADD)
 x86locked_LINK = $(CCLD) $(x86locked_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
        $(LDFLAGS) -o $@
 x86locked_LDADD = $(LDADD)
 x86locked_LINK = $(CCLD) $(x86locked_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
        $(LDFLAGS) -o $@

+xadd_SOURCES = xadd.c
+xadd_OBJECTS = xadd.$(OBJEXT)
+xadd_LDADD = $(LDADD)

 yield_SOURCES = yield.c
 yield_OBJECTS = yield.$(OBJEXT)
 yield_DEPENDENCIES =
 yield_SOURCES = yield.c
 yield_OBJECTS = yield.$(OBJEXT)
 yield_DEPENDENCIES =


@@ -220,9 +227,9 @@ SOURCES = badseg.c bt_everything.c bt_literal.c bug125959-x86.c \
        $(insn_cmov_SOURCES) $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) \
        $(insn_mmxext_SOURCES) $(insn_sse_SOURCES) \
        $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
        $(insn_cmov_SOURCES) $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) \
        $(insn_mmxext_SOURCES) $(insn_sse_SOURCES) \
        $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \

-       $(insn_ssse3_SOURCES) int.c jcxz.c lahf.c looper.c movx.c \
-       pushpopseg.c sbbmisc.c smc1.c ssse3_misaligned.c x86locked.c \
-       yield.c
+       $(insn_ssse3_SOURCES) int.c jcxz.c lahf.c looper.c lzcnt32.c \
+       movx.c pushpopseg.c sbbmisc.c smc1.c ssse3_misaligned.c \
+       x86locked.c xadd.c yield.c

 DIST_SOURCES = badseg.c bt_everything.c bt_literal.c bug125959-x86.c \
        bug126147-x86.c bug132813-x86.c bug135421-x86.c \
        bug137714-x86.c bug152818-x86.c cmpxchg8b.c $(cpuid_SOURCES) \
 DIST_SOURCES = badseg.c bt_everything.c bt_literal.c bug125959-x86.c \
        bug126147-x86.c bug132813-x86.c bug135421-x86.c \
        bug137714-x86.c bug152818-x86.c cmpxchg8b.c $(cpuid_SOURCES) \


@@ -231,9 +238,9 @@ DIST_SOURCES = badseg.c bt_everything.c bt_literal.c bug125959-x86.c \
        $(insn_cmov_SOURCES) $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) \
        $(insn_mmxext_SOURCES) $(insn_sse_SOURCES) \
        $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \
        $(insn_cmov_SOURCES) $(insn_fpu_SOURCES) $(insn_mmx_SOURCES) \
        $(insn_mmxext_SOURCES) $(insn_sse_SOURCES) \
        $(insn_sse2_SOURCES) $(insn_sse3_SOURCES) \

-       $(insn_ssse3_SOURCES) int.c jcxz.c lahf.c looper.c movx.c \
-       pushpopseg.c sbbmisc.c smc1.c ssse3_misaligned.c x86locked.c \
-       yield.c
+       $(insn_ssse3_SOURCES) int.c jcxz.c lahf.c looper.c lzcnt32.c \
+       movx.c pushpopseg.c sbbmisc.c smc1.c ssse3_misaligned.c \
+       x86locked.c xadd.c yield.c

 ETAGS = etags
 CTAGS = ctags
 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
 ETAGS = etags
 CTAGS = ctags
 DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)


@@ -274,6 +281,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -308,14 +316,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -398,7 +410,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -457,7 +471,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -472,8 +486,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64


@@ -571,6 +585,7 @@ EXTRA_DIST = \
        jcxz.stdout.exp jcxz.stderr.exp jcxz.vgtest \
        lahf.stdout.exp lahf.stderr.exp lahf.vgtest \
        looper.stderr.exp looper.stdout.exp looper.vgtest \
        jcxz.stdout.exp jcxz.stderr.exp jcxz.vgtest \
        lahf.stdout.exp lahf.stderr.exp lahf.vgtest \
        looper.stderr.exp looper.stdout.exp looper.vgtest \

+       lzcnt32.stderr.exp lzcnt32.stdout.exp lzcnt32.vgtest \

        movx.stderr.exp movx.stdout.exp movx.vgtest \
        pushpopseg.stderr.exp pushpopseg.stdout.exp pushpopseg.vgtest \
        sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \
        movx.stderr.exp movx.stdout.exp movx.vgtest \
        pushpopseg.stderr.exp pushpopseg.stdout.exp pushpopseg.vgtest \
        sbbmisc.stderr.exp sbbmisc.stdout.exp sbbmisc.vgtest \


@@ -578,7 +593,8 @@ EXTRA_DIST = \
        ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
        ssse3_misaligned.vgtest ssse3_misaligned.c \
        x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \
        ssse3_misaligned.stderr.exp ssse3_misaligned.stdout.exp \
        ssse3_misaligned.vgtest ssse3_misaligned.c \
        x86locked.vgtest x86locked.stdout.exp x86locked.stderr.exp \

-       yield.stderr.exp yield.stdout.exp yield.disabled
+       yield.stderr.exp yield.stdout.exp yield.disabled \
+       xadd.stdout.exp xadd.stderr.exp xadd.vgtest

 
 cpuid_SOURCES = cpuid_c.c cpuid_s.S
 # fpu_lazy_eflags must use these flags -- the bug only occurred with them.
 
 cpuid_SOURCES = cpuid_c.c cpuid_s.S
 # fpu_lazy_eflags must use these flags -- the bug only occurred with them.


@@ -734,6 +750,9 @@ lahf$(EXEEXT): $(lahf_OBJECTS) $(lahf_DEPENDENCIES)
 looper$(EXEEXT): $(looper_OBJECTS) $(looper_DEPENDENCIES) 
        @rm -f looper$(EXEEXT)
        $(LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)
 looper$(EXEEXT): $(looper_OBJECTS) $(looper_DEPENDENCIES) 
        @rm -f looper$(EXEEXT)
        $(LINK) $(looper_OBJECTS) $(looper_LDADD) $(LIBS)

+lzcnt32$(EXEEXT): $(lzcnt32_OBJECTS) $(lzcnt32_DEPENDENCIES) 
+       @rm -f lzcnt32$(EXEEXT)
+       $(LINK) $(lzcnt32_OBJECTS) $(lzcnt32_LDADD) $(LIBS)

 movx$(EXEEXT): $(movx_OBJECTS) $(movx_DEPENDENCIES) 
        @rm -f movx$(EXEEXT)
        $(LINK) $(movx_OBJECTS) $(movx_LDADD) $(LIBS)
 movx$(EXEEXT): $(movx_OBJECTS) $(movx_DEPENDENCIES) 
        @rm -f movx$(EXEEXT)
        $(LINK) $(movx_OBJECTS) $(movx_LDADD) $(LIBS)


@@ -752,6 +771,9 @@ ssse3_misaligned$(EXEEXT): $(ssse3_misaligned_OBJECTS) $(ssse3_misaligned_DEPEND
 x86locked$(EXEEXT): $(x86locked_OBJECTS) $(x86locked_DEPENDENCIES) 
        @rm -f x86locked$(EXEEXT)
        $(x86locked_LINK) $(x86locked_OBJECTS) $(x86locked_LDADD) $(LIBS)
 x86locked$(EXEEXT): $(x86locked_OBJECTS) $(x86locked_DEPENDENCIES) 
        @rm -f x86locked$(EXEEXT)
        $(x86locked_LINK) $(x86locked_OBJECTS) $(x86locked_LDADD) $(LIBS)

+xadd$(EXEEXT): $(xadd_OBJECTS) $(xadd_DEPENDENCIES) 
+       @rm -f xadd$(EXEEXT)
+       $(LINK) $(xadd_OBJECTS) $(xadd_LDADD) $(LIBS)

 yield$(EXEEXT): $(yield_OBJECTS) $(yield_DEPENDENCIES) 
        @rm -f yield$(EXEEXT)
        $(LINK) $(yield_OBJECTS) $(yield_LDADD) $(LIBS)
 yield$(EXEEXT): $(yield_OBJECTS) $(yield_DEPENDENCIES) 
        @rm -f yield$(EXEEXT)
        $(LINK) $(yield_OBJECTS) $(yield_LDADD) $(LIBS)


@@ -794,12 +816,14 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jcxz.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lahf.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/looper.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/jcxz.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lahf.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/looper.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lzcnt32.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/movx.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pushpopseg.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sbbmisc.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/smc1.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ssse3_misaligned.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/x86locked-x86locked.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/movx.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pushpopseg.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sbbmisc.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/smc1.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ssse3_misaligned.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/x86locked-x86locked.Po@am__quote@

+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/xadd.Po@am__quote@

 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/yield.Po@am__quote@
 
 .S.o:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/yield.Po@am__quote@
 
 .S.o:

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/fxtract.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/fxtract.stdout.exp
index 4508fd6b69fd2eaaa3b7204620389f8f6deaed66..b82f306b04779dc4b503a5008288d6fd97bf38e6 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/fxtract.stdout.exp
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/fxtract.stdout.exp
@@ -40,7 +40,7 @@
  2.7049662808e+02  ->   1.0566274534   8.0000000000
  0.0000000000e+00  ->   0.0000000000           -inf
               inf  ->            inf            inf
  2.7049662808e+02  ->   1.0566274534   8.0000000000
  0.0000000000e+00  ->   0.0000000000           -inf
               inf  ->            inf            inf

-              nan  ->            nan            nan
+             -nan  ->           -nan           -nan

 7.2124891681e-308  ->   1.6207302828 -1021.0000000000
 5.7982756057e-308  ->   1.3029400313 -1021.0000000000
 4.3840620434e-308  ->   1.9702995595 -1022.0000000000
 7.2124891681e-308  ->   1.6207302828 -1021.0000000000
 5.7982756057e-308  ->   1.3029400313 -1021.0000000000
 4.3840620434e-308  ->   1.9702995595 -1022.0000000000

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.c
new file mode 100644 (file)
index 0000000..107a25d
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.c
@@ -0,0 +1,66 @@
+
+#include <stdio.h>
+
+typedef  unsigned long long int  ULong;
+typedef  unsigned int            UInt;
+
+__attribute__((noinline))
+void do_lzcnt32 ( /*OUT*/UInt* flags, /*OUT*/UInt* res, UInt arg )
+{
+  UInt block[3] = { arg, 0, 0 };
+  __asm__ __volatile__(
+    "movl $0x55555555, %%esi" "\n\t"
+    "lzcntl 0(%0), %%esi"     "\n\t"
+    "movl %%esi, 4(%0)"       "\n\t"
+    "pushfl"                  "\n\t"
+    "popl %%esi"              "\n\t"
+    "movl %%esi, 8(%0)"       "\n"
+    : : "r"(&block[0]) : "esi","cc","memory"
+  );
+  *res = block[1];
+  *flags = block[2] & 0x8d5;
+}
+
+__attribute__((noinline))
+void do_lzcnt16 ( /*OUT*/UInt* flags, /*OUT*/UInt* res, UInt arg )
+{
+  UInt block[3] = { arg, 0, 0 };
+  __asm__ __volatile__(
+    "movl $0x55555555, %%esi" "\n\t"
+    "lzcntw 0(%0), %%si"      "\n\t"
+    "movl %%esi, 4(%0)"       "\n\t"
+    "pushfl"                  "\n\t"
+    "popl %%esi"              "\n\t"
+    "movl %%esi, 8(%0)"       "\n"
+    : : "r"(&block[0]) : "esi","cc","memory"
+  );
+  *res = block[1];
+  *flags = block[2] & 0x8d5;
+}
+
+int main ( void )
+{
+   UInt w;
+
+   w = 0xFEDC1928;
+   while (1) {
+      UInt res;
+      UInt flags;
+      do_lzcnt32(&flags, &res, w);
+      printf("lzcntl %08x -> %08x %04x\n", w, res, flags);
+      if (w == 0) break;
+      w = ((w >> 2) | (w >> 1)) + (w / 17);
+   }
+
+   w = 0xFEDC1928;
+   while (1) {
+      UInt res;
+      UInt flags;
+      do_lzcnt16(&flags, &res, w);
+      printf("lzcntw %08x -> %08x %04x\n", w, res, flags);
+      if (w == 0) break;
+      w = ((w >> 2) | (w >> 1)) + (w / 17);
+   }
+
+   return 0;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.stdout.exp
new file mode 100644 (file)
index 0000000..41773d3
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.stdout.exp
@@ -0,0 +1,122 @@
+lzcntl fedc1928 -> 00000000 0040
+lzcntl 8efcf23a -> 00000000 0040
+lzcntl 7068b90b -> 00000001 0000
+lzcntl 42db3e5e -> 00000001 0000
+lzcntl 35eea72d -> 00000002 0000
+lzcntl 232c23d2 -> 00000002 0000
+lzcntl 1bf0c1be -> 00000003 0000
+lzcntl 11a13119 -> 00000003 0000
+lzcntl 0e025829 -> 00000004 0000
+lzcntl 0854b43e -> 00000004 0000
+lzcntl 06bcf322 -> 00000005 0000
+lzcntl 0464f58f -> 00000005 0000
+lzcntl 037dac76 -> 00000006 0000
+lzcntl 023490eb -> 00000006 0000
+lzcntl 01c0a232 -> 00000007 0000
+lzcntl 010add81 -> 00000007 0000
+lzcntl 00d7b28d -> 00000008 0000
+lzcntl 008cae0d -> 00000008 0000
+lzcntl 006fc600 -> 00000009 0000
+lzcntl 004686ad -> 00000009 0000
+lzcntl 00380a09 -> 0000000a 0000
+lzcntl 00215368 -> 0000000a 0000
+lzcntl 001af3d6 -> 0000000b 0000
+lzcntl 001193de -> 0000000b 0000
+lzcntl 000df6b1 -> 0000000c 0000
+lzcntl 0008d242 -> 0000000c 0000
+lzcntl 00070287 -> 0000000d 0000
+lzcntl 00042b72 -> 0000000d 0000
+lzcntl 00035ec7 -> 0000000e 0000
+lzcntl 000232b3 -> 0000000e 0000
+lzcntl 0001bf16 -> 0000000f 0000
+lzcntl 00011a1b -> 0000000f 0000
+lzcntl 0000e027 -> 00000010 0000
+lzcntl 0000854a -> 00000010 0000
+lzcntl 00006bce -> 00000011 0000
+lzcntl 0000464e -> 00000011 0000
+lzcntl 000037d9 -> 00000012 0000
+lzcntl 00002347 -> 00000012 0000
+lzcntl 00001c06 -> 00000013 0000
+lzcntl 000010a9 -> 00000013 0000
+lzcntl 00000d78 -> 00000014 0000
+lzcntl 000008c8 -> 00000014 0000
+lzcntl 000006fa -> 00000015 0000
+lzcntl 00000468 -> 00000015 0000
+lzcntl 00000380 -> 00000016 0000
+lzcntl 00000214 -> 00000016 0000
+lzcntl 000001ae -> 00000017 0000
+lzcntl 00000118 -> 00000017 0000
+lzcntl 000000de -> 00000018 0000
+lzcntl 0000008c -> 00000018 0000
+lzcntl 0000006f -> 00000019 0000
+lzcntl 00000045 -> 00000019 0000
+lzcntl 00000037 -> 0000001a 0000
+lzcntl 00000022 -> 0000001a 0000
+lzcntl 0000001b -> 0000001b 0000
+lzcntl 00000010 -> 0000001b 0000
+lzcntl 0000000c -> 0000001c 0000
+lzcntl 00000007 -> 0000001d 0000
+lzcntl 00000003 -> 0000001e 0000
+lzcntl 00000001 -> 0000001f 0000
+lzcntl 00000000 -> 00000020 0001
+lzcntw fedc1928 -> 55550003 0000
+lzcntw 8efcf23a -> 55550000 0040
+lzcntw 7068b90b -> 55550000 0040
+lzcntw 42db3e5e -> 55550002 0000
+lzcntw 35eea72d -> 55550000 0040
+lzcntw 232c23d2 -> 55550002 0000
+lzcntw 1bf0c1be -> 55550000 0040
+lzcntw 11a13119 -> 55550002 0000
+lzcntw 0e025829 -> 55550001 0000
+lzcntw 0854b43e -> 55550000 0040
+lzcntw 06bcf322 -> 55550000 0040
+lzcntw 0464f58f -> 55550000 0040
+lzcntw 037dac76 -> 55550000 0040
+lzcntw 023490eb -> 55550000 0040
+lzcntw 01c0a232 -> 55550000 0040
+lzcntw 010add81 -> 55550000 0040
+lzcntw 00d7b28d -> 55550000 0040
+lzcntw 008cae0d -> 55550000 0040
+lzcntw 006fc600 -> 55550000 0040
+lzcntw 004686ad -> 55550000 0040
+lzcntw 00380a09 -> 55550004 0000
+lzcntw 00215368 -> 55550001 0000
+lzcntw 001af3d6 -> 55550000 0040
+lzcntw 001193de -> 55550000 0040
+lzcntw 000df6b1 -> 55550000 0040
+lzcntw 0008d242 -> 55550000 0040
+lzcntw 00070287 -> 55550006 0000
+lzcntw 00042b72 -> 55550002 0000
+lzcntw 00035ec7 -> 55550001 0000
+lzcntw 000232b3 -> 55550002 0000
+lzcntw 0001bf16 -> 55550000 0040
+lzcntw 00011a1b -> 55550003 0000
+lzcntw 0000e027 -> 55550000 0040
+lzcntw 0000854a -> 55550000 0040
+lzcntw 00006bce -> 55550001 0000
+lzcntw 0000464e -> 55550001 0000
+lzcntw 000037d9 -> 55550002 0000
+lzcntw 00002347 -> 55550002 0000
+lzcntw 00001c06 -> 55550003 0000
+lzcntw 000010a9 -> 55550003 0000
+lzcntw 00000d78 -> 55550004 0000
+lzcntw 000008c8 -> 55550004 0000
+lzcntw 000006fa -> 55550005 0000
+lzcntw 00000468 -> 55550005 0000
+lzcntw 00000380 -> 55550006 0000
+lzcntw 00000214 -> 55550006 0000
+lzcntw 000001ae -> 55550007 0000
+lzcntw 00000118 -> 55550007 0000
+lzcntw 000000de -> 55550008 0000
+lzcntw 0000008c -> 55550008 0000
+lzcntw 0000006f -> 55550009 0000
+lzcntw 00000045 -> 55550009 0000
+lzcntw 00000037 -> 5555000a 0000
+lzcntw 00000022 -> 5555000a 0000
+lzcntw 0000001b -> 5555000b 0000
+lzcntw 00000010 -> 5555000b 0000
+lzcntw 0000000c -> 5555000c 0000
+lzcntw 00000007 -> 5555000d 0000
+lzcntw 00000003 -> 5555000e 0000
+lzcntw 00000001 -> 5555000f 0000
+lzcntw 00000000 -> 55550010 0001

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.vgtest
new file mode 100644 (file)
index 0000000..d1e95be
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/lzcnt32.vgtest
@@ -0,0 +1,3 @@
+prog: lzcnt32
+prereq: ../../../tests/x86_amd64_features x86-lzcnt
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.c
new file mode 100644 (file)
index 0000000..38d4f20
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.c
@@ -0,0 +1,51 @@
+
+#include "config.h"
+#include <stdio.h>
+#include <assert.h>
+
+/* Simple test program, no race.
+   Tests the 'xadd' exchange-and-add instruction with {r,r} operands, which is rarely generated by compilers. */
+
+#undef PLAT_x86_linux
+#undef PLAT_amd64_linux
+#undef PLAT_ppc32_linux
+#undef PLAT_ppc64_linux
+#undef PLAT_ppc32_aix5
+#undef PLAT_ppc64_aix5
+
+#if !defined(_AIX) && defined(__i386__)
+#  define PLAT_x86_linux 1
+#elif !defined(_AIX) && defined(__x86_64__)
+#  define PLAT_amd64_linux 1
+#endif
+
+
+#if defined(PLAT_amd64_linux) || defined(PLAT_x86_linux)
+#  define XADD_R_R(_addr,_lval) \
+       __asm__ __volatile__( \
+       "xadd %1, %0" \
+       : /*out*/ "=r"(_lval),"=r"(_addr) \
+       : /*in*/  "0"(_lval),"1"(_addr) \
+       : "flags" \
+       )
+#else
+#  error "Unsupported architecture"
+#endif
+
+int main ( void )
+{
+   long d = 20, s = 2;
+   long xadd_r_r_res;
+#define XADD_R_R_RES 42
+   
+   XADD_R_R(s, d);
+   xadd_r_r_res = s + d;
+   assert(xadd_r_r_res == XADD_R_R_RES);
+
+   if (xadd_r_r_res == XADD_R_R_RES)
+      printf("success\n");
+   else
+      printf("failure\n");
+
+   return xadd_r_r_res;
+}

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.stdout.exp b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.stdout.exp
new file mode 100644 (file)
index 0000000..2e9ba47
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.stdout.exp
@@ -0,0 +1 @@
+success

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.vgtest b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.vgtest
new file mode 100644 (file)
index 0000000..2cb1bee
--- /dev/null
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/none/tests/x86/xadd.vgtest
@@ -0,0 +1,2 @@
+prog: xadd
+vgopts: -q

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/perf/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/perf/Makefile.in
index cecc0699303983de2cb203cd1cf02fe50c384681..4a446300b5e7e7c1b306c70c3830d28beaca7348 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/perf/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/perf/Makefile.in
@@ -137,6 +137,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -171,14 +172,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -261,7 +266,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -320,7 +327,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -335,8 +342,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/Makefile.in b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/Makefile.in
index 19b5139b83c8425a3d831812bbfa27054168af6d..b3d67162c595117821a568c1ae647475eee6310a 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/Makefile.in
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/Makefile.in
@@ -126,6 +126,7 @@ FLAG_MAIX32 = @FLAG_MAIX32@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@
 FLAG_MAIX64 = @FLAG_MAIX64@
 FLAG_MMMX = @FLAG_MMMX@
 FLAG_MSSE = @FLAG_MSSE@

+FLAG_NO_BUILD_ID = @FLAG_NO_BUILD_ID@

 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@
 FLAG_UNLIMITED_INLINE_UNIT_GROWTH = @FLAG_UNLIMITED_INLINE_UNIT_GROWTH@
 FLAG_W_EXTRA = @FLAG_W_EXTRA@
 FLAG_W_NO_EMPTY_BODY = @FLAG_W_NO_EMPTY_BODY@


@@ -160,14 +161,18 @@ PACKAGE_VERSION = @PACKAGE_VERSION@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@
 PATH_SEPARATOR = @PATH_SEPARATOR@
 PERL = @PERL@
 PKG_CONFIG = @PKG_CONFIG@

+PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@
+PKG_CONFIG_PATH = @PKG_CONFIG_PATH@

 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@
 PREFERRED_STACK_BOUNDARY = @PREFERRED_STACK_BOUNDARY@
 QTCORE_CFLAGS = @QTCORE_CFLAGS@
 QTCORE_LIBS = @QTCORE_LIBS@
 RANLIB = @RANLIB@

+SED = @SED@

 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@
 SET_MAKE = @SET_MAKE@
 SHELL = @SHELL@
 STRIP = @STRIP@

-VALT_LOAD_ADDRESS = @VALT_LOAD_ADDRESS@
+VALT_LOAD_ADDRESS_PRI = @VALT_LOAD_ADDRESS_PRI@
+VALT_LOAD_ADDRESS_SEC = @VALT_LOAD_ADDRESS_SEC@

 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@
 VERSION = @VERSION@
 VGCONF_ARCH_PRI = @VGCONF_ARCH_PRI@
 VGCONF_ARCH_SEC = @VGCONF_ARCH_SEC@


@@ -250,7 +255,9 @@ AM_CFLAGS_BASE = \
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.
 # The aim is to give reasonable performance but also to have good
 # stack traces, since users often see stack traces extending 
 # into (and through) the preloads.

-@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing -mno-dynamic-no-pic
+@VGCONF_OS_IS_DARWIN_TRUE@AM_CFLAGS_PIC = -dynamic -O -g -fno-omit-frame-pointer -fno-strict-aliasing \
+@VGCONF_OS_IS_DARWIN_TRUE@             -mno-dynamic-no-pic -fpic -fPIC
+

 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \
 @VGCONF_OS_IS_L4RE_FALSE@AM_CPPFLAGS_@VGCONF_PLATFORM_PRI_CAPS@ = \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir) \
 @VGCONF_OS_IS_L4RE_FALSE@      -I$(top_srcdir)/include \


@@ -309,7 +316,7 @@ AM_CFLAGS_PPC64_LINUX = @FLAG_M64@ $(AM_CFLAGS_BASE)
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \
 AM_CCASFLAGS_PPC64_LINUX = $(AM_CPPFLAGS_PPC64_LINUX) @FLAG_M64@ -g
 AM_FLAG_M3264_ARM_LINUX = @FLAG_M32@
 AM_CFLAGS_ARM_LINUX = @FLAG_M32@ @PREFERRED_STACK_BOUNDARY@ \

-                               $(AM_CFLAGS_BASE)
+                               $(AM_CFLAGS_BASE) -marm

 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@
 
 AM_CCASFLAGS_ARM_LINUX = $(AM_CPPFLAGS_ARM_LINUX) @FLAG_M32@ -g
 AM_FLAG_M3264_PPC32_AIX5 = @FLAG_MAIX32@


@@ -324,8 +331,8 @@ AM_CCASFLAGS_PPC64_AIX5 = $(AM_CPPFLAGS_PPC64_AIX5) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \
 
 AM_FLAG_M3264_X86_DARWIN = -arch i386
 AM_CFLAGS_X86_DARWIN = $(WERROR) -arch i386 $(AM_CFLAGS_BASE) \

-                           -mmacosx-version-min=10.5 -fno-stack-protector \
-                           -mdynamic-no-pic
+                               -mmacosx-version-min=10.5 \
+                               -fno-stack-protector -fno-pic -fno-PIC

 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64
 
 AM_CCASFLAGS_X86_DARWIN = $(AM_CPPFLAGS_X86_DARWIN) -arch i386 -g
 AM_FLAG_M3264_AMD64_DARWIN = -arch x86_64

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/filter_stderr_basic b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/filter_stderr_basic
index 758695871328ad397bdad73021b3cc21d09b42fe..1537713eace47edb34644b68553a1866174bd4bb 100755 (executable)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/filter_stderr_basic
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/filter_stderr_basic
@@ -9,8 +9,8 @@
 
 dir=`dirname $0`
 
 
 dir=`dirname $0`
 

-# Remove ==pid== and --pid-- and ++pid++ and **pid** strings 
-perl -p -e 's/(==|--|\+\+|\*\*)[0-9]{1,7}\1 //' |
+# Remove ==pid== and --pid-- and **pid** strings 
+perl -p -e 's/(==|--|\*\*)[0-9]{1,7}\1 //' |

 
 # Remove any --pid:0: strings (debuglog level zero output)
 sed "/^--[0-9]\{1,7\}:0:*/d" |
 
 # Remove any --pid:0: strings (debuglog level zero output)
 sed "/^--[0-9]\{1,7\}:0:*/d" |

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/x86_amd64_features.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/x86_amd64_features.c
index aaa2a55cc42dfdbba392a0f022f28a9f2ca7115e..c497d22010ee2e82c1781e17bf40629b2f7c995b 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/x86_amd64_features.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/tests/x86_amd64_features.c
@@ -29,9 +29,23 @@ static void cpuid ( unsigned int n,
       : "0" (n)         /* input */
    );
 }
       : "0" (n)         /* input */
    );
 }

+
+static Bool vendorStringEquals ( char* str )
+{
+   char vstr[13];
+   unsigned int a, b, c, d;
+   cpuid(0, &a, &b, &c, &d);
+   memcpy(&vstr[0], &b, 4);
+   memcpy(&vstr[4], &d, 4);
+   memcpy(&vstr[8], &c, 4);
+   vstr[12] = 0;
+   return 0 == strcmp(vstr, str);
+}
+

 static Bool go(char* cpu)
 { 
    unsigned int level = 0, cmask = 0, dmask = 0, a, b, c, d;
 static Bool go(char* cpu)
 { 
    unsigned int level = 0, cmask = 0, dmask = 0, a, b, c, d;

+   Bool require_amd = False;

 
    if        ( strcmp( cpu, "x86-fpu" ) == 0 ) {
      level = 1;
 
    if        ( strcmp( cpu, "x86-fpu" ) == 0 ) {
      level = 1;


@@ -57,6 +71,10 @@ static Bool go(char* cpu)
    } else if ( strcmp( cpu, "x86-ssse3" ) == 0 ) {
      level = 1;
      cmask = 1 << 9;
    } else if ( strcmp( cpu, "x86-ssse3" ) == 0 ) {
      level = 1;
      cmask = 1 << 9;

+   } else if ( strcmp( cpu, "x86-lzcnt" ) == 0 ) {
+     level = 0x80000001;
+     cmask = 1 << 5;
+     require_amd = True;

 #if defined(VGA_amd64)
    } else if ( strcmp( cpu, "amd64-sse3" ) == 0 ) {
      level = 1;
 #if defined(VGA_amd64)
    } else if ( strcmp( cpu, "amd64-sse3" ) == 0 ) {
      level = 1;


@@ -67,6 +85,10 @@ static Bool go(char* cpu)
    } else if ( strcmp( cpu, "amd64-cx16" ) == 0 ) {
      level = 1;
      cmask = 1 << 13;
    } else if ( strcmp( cpu, "amd64-cx16" ) == 0 ) {
      level = 1;
      cmask = 1 << 13;

+   } else if ( strcmp( cpu, "amd64-lzcnt" ) == 0 ) {
+     level = 0x80000001;
+     cmask = 1 << 5;
+     require_amd = True;

 #endif
    } else {
      return 2;          // Unrecognised feature.
 #endif
    } else {
      return 2;          // Unrecognised feature.


@@ -75,6 +97,10 @@ static Bool go(char* cpu)
    assert( !(cmask != 0 && dmask != 0) );
    assert( !(cmask == 0 && dmask == 0) );
 
    assert( !(cmask != 0 && dmask != 0) );
    assert( !(cmask == 0 && dmask == 0) );
 

+   if (require_amd && !vendorStringEquals("AuthenticAMD"))
+      return 1; // Feature not present
+      // regardless of what that feature actually is
+

    cpuid( level & 0x80000000, &a, &b, &c, &d );
 
    if ( a >= level ) {
    cpuid( level & 0x80000000, &a, &b, &c, &d );
 
    if ( a >= level ) {