5 // Register and register bit definitions for ia32, amd64 and UX architectures.
8 #define CR0_PE 0x00000001 // Protection Enable
9 #define CR0_MP 0x00000002 // Monitor Coprocessor
10 #define CR0_EM 0x00000004 // Emulation Coprocessor
11 #define CR0_TS 0x00000008 // Task Switched
12 #define CR0_ET 0x00000010 // Extension Type
13 #define CR0_NE 0x00000020 // Numeric Error
14 #define CR0_WP 0x00010000 // Write Protect
15 #define CR0_AM 0x00040000 // Alignment Mask
16 #define CR0_NW 0x20000000 // Not Write-Through
17 #define CR0_CD 0x40000000 // Cache Disable
18 #define CR0_PG 0x80000000 // Paging
20 #define CR3_PWT 0x00000008 // Page-Level Write Transparent
21 #define CR3_PCD 0x00000010 // Page-Level Cache Disable
23 #define CR4_VME 0x00000001 // Virtual 8086 Mode Extensions
24 #define CR4_PVI 0x00000002 // Protected Mode Virtual Ints
25 #define CR4_TSD 0x00000004 // Time Stamp Disable
26 #define CR4_DE 0x00000008 // Debugging Extensions
27 #define CR4_PSE 0x00000010 // Page Size Extensions
28 #define CR4_PAE 0x00000020 // Physical Address Extensions
29 #define CR4_MCE 0x00000040 // Machine Check Exception
30 #define CR4_PGE 0x00000080 // Page Global Enable
31 #define CR4_PCE 0x00000100 // Perfmon Counter Enable
32 #define CR4_OSFXSR 0x00000200 // OS Supports FXSAVE/FXRSTOR
33 #define CR4_OSXMMEXCPT 0x00000400 // OS Supports SIMD Exceptions
34 #define CR4_VMXE 0x00002000 // VMX enable
36 #define EFLAGS_CF 0x00000001 // Carry Flag
37 #define EFLAGS_PF 0x00000004 // Parity Flag
38 #define EFLAGS_AF 0x00000010 // Adjust Flag
39 #define EFLAGS_ZF 0x00000040 // Zero Flag
40 #define EFLAGS_SF 0x00000080 // Sign Flag
41 #define EFLAGS_TF 0x00000100 // Trap Flag
42 #define EFLAGS_IF 0x00000200 // Interrupt Enable
43 #define EFLAGS_DF 0x00000400 // Direction Flag
44 #define EFLAGS_OF 0x00000800 // Overflow Flag
45 #define EFLAGS_IOPL 0x00003000 // I/O Privilege Level (12+13)
46 #define EFLAGS_IOPL_K 0x00000000 // kernel
47 #define EFLAGS_IOPL_U 0x00003000 // user
48 #define EFLAGS_NT 0x00004000 // Nested Task
49 #define EFLAGS_RF 0x00010000 // Resume
50 #define EFLAGS_VM 0x00020000 // Virtual 8086 Mode
51 #define EFLAGS_AC 0x00040000 // Alignment Check
52 #define EFLAGS_VIF 0x00080000 // Virtual Interrupt
53 #define EFLAGS_VIP 0x00100000 // Virtual Interrupt Pending
54 #define EFLAGS_ID 0x00200000 // Identification
57 #define FEAT_FPU 0x00000001 // FPU On Chip
58 #define FEAT_VME 0x00000002 // Virt. 8086 Mode Enhancements
59 #define FEAT_DE 0x00000004 // Debugging Extensions
60 #define FEAT_PSE 0x00000008 // Page Size Extension
61 #define FEAT_TSC 0x00000010 // Time Stamp Counter
62 #define FEAT_MSR 0x00000020 // Model Specific Registers
63 #define FEAT_PAE 0x00000040 // Physical Address Extension
64 #define FEAT_MCE 0x00000080 // Machine Check Exception
65 #define FEAT_CX8 0x00000100 // CMPXCHG8B Instruction
66 #define FEAT_APIC 0x00000200 // APIC On Chip
67 #define FEAT_SEP 0x00000800 // Sysenter/Sysexit Present
68 #define FEAT_MTRR 0x00001000 // Memory Type Range Registers
69 #define FEAT_PGE 0x00002000 // PTE Global Bit Extension
70 #define FEAT_MCA 0x00004000 // Machine Check Architecture
71 #define FEAT_CMOV 0x00008000 // Conditional Move Instruction
72 #define FEAT_PAT 0x00010000 // Page Attribute Table
73 #define FEAT_PSE36 0x00020000 // 32 bit Page Size Extension
74 #define FEAT_PSN 0x00040000 // Processor Serial Number
75 #define FEAT_CLFSH 0x00080000 // CLFLUSH Instruction
76 #define FEAT_DS 0x00200000 // Debug Store
77 #define FEAT_ACPI 0x00400000 // Thermal Monitor & Clock
78 #define FEAT_MMX 0x00800000 // MMX Technology
79 #define FEAT_FXSR 0x01000000 // FXSAVE/FXRSTOR Instructions
80 #define FEAT_SSE 0x02000000 // SSE
81 #define FEAT_SSE2 0x04000000 // SSE2
82 #define FEAT_SS 0x08000000 // Self Snoop
83 #define FEAT_HTT 0x10000000 // Hyper-Threading Technology
84 #define FEAT_TM 0x20000000 // Thermal Monitor
85 #define FEAT_PBE 0x80000000 // Pending Break Enable
87 // CPU Extended Feature Flags (Intel)
88 #define FEATX_SSE3 0x00000001 // SSE3
89 #define FEATX_MONITOR 0x00000008 // MONITOR/MWAIT Support
90 #define FEATX_DSCPL 0x00000010 // CPL Qualified Debug Store
91 #define FEATX_VMX 0x00000020 // Virtual Machine Extensions
92 #define FEATX_EST 0x00000080 // Enhanced SpeedStep Technology
93 #define FEATX_TM2 0x00000100 // Thermal Monitor 2
94 #define FEATX_CID 0x00000400 // L1 Context ID (adaptive/shared)
95 #define FEATX_CX16 0x00002000 // CMPXCHG16B Instruction
96 #define FEATX_XTPR 0x00004000 // Disable Task Priority Messages
98 // AMD: CPU Feature Flags, Fn80000001_ECX
99 #define FEATA_SVM 0x00000004
101 // AMD: CPU Feature Flags, Fn80000001_EDX
102 #define FEATA_SYSCALL 0x00000800 // Syscall/Sysret Present
103 #define FEATA_MP 0x00080000 // MP Capable
104 #define FEATA_NX 0x00100000 // No-Execute Page Protection
105 #define FEATA_MMXEXT 0x00400000 // AMD Extensions to MMX
106 #define FEATA_LM 0x20000000 // Long Mode
107 #define FEATA_3DNOWEXT 0x40000000 // AMD 3DNow! extensions
108 #define FEATA_3DNOW 0x80000000 // 3DNow!
110 // Page Fault Error Codes
111 // PF_ERR_REMTADDR and PF_ERR_USERADDR are UX-emulation only
112 #define PF_ERR_PRESENT 0x00000001 // PF: Page Is Present In PTE
113 #define PF_ERR_WRITE 0x00000002 // PF: Page Is Write Protected
114 #define PF_ERR_USERMODE 0x00000004 // PF: Caused By User Mode Code
115 #define PF_ERR_RESERVED 0x00000008 // PF: Reserved Bit Set in PDIR
116 #define PF_ERR_REMTADDR 0x40000000 // PF: In Remote Address Space
117 #define PF_ERR_USERADDR 0x80000000 // PF: In User Address Space
119 // Model Specific Registers
120 #define MSR_SYSENTER_CS 0x174 // Kernel Code Segment
121 #define MSR_SYSENTER_ESP 0x175 // Kernel Syscall Entry
122 #define MSR_SYSENTER_EIP 0x176 // Kernel Stack Pointer
123 #define MSR_LER_FROM_LIP 0x1d7 // Last Exception Record From Linear
124 #define MSR_LER_TO_LIP 0x1d8 // Last Exception Record To Linear
125 #define MSR_DEBUGCTLA 0x1d9 // Debug Control
126 #define MSR_LASTBRANCH_TOS 0x1da // (P4) Last Branch Record Stack TOS
127 #define MSR_LASTBRANCH_0 0x1db // (P4) Last Branch Record 0
128 #define MSR_LASTBRANCH_1 0x1dc // (P4) Last Branch Record 1
129 #define MSR_LASTBRANCH_2 0x1dd // (P4) Last Branch Record 2
130 #define MSR_LASTBRANCH_3 0x1de // (P4) Last Branch Record 3
131 #define MSR_LASTBRANCHFROMIP 0x1db // (P6)
132 #define MSR_LASTBRANCHTOIP 0x1dc // (P6)
133 #define MSR_LASTINTFROMIP 0x1dd // (P6)
134 #define MSR_LASTINTTOIP 0x1de // (P6)
136 // AMD64 Model Specific Registers
137 #define MSR_EFER 0xc0000080 // Extended Feature Enable Register
138 #define MSR_STAR 0xc0000081 // CS and SS for Syscall/Sysret
139 #define MSR_LSTAR 0xc0000082 // EIP for Syscall (64Bit-Mode)
140 #define MSR_CTAR 0xc0000083 // EIP for Syscall (Comp-Mode)
141 #define MSR_SFMASK 0xc0000084 // RFLAGS for Syscall
142 #define MSR_VM_CR 0xc0010114 // SVM
143 #define MSR_VM_HSAVE_PA 0xc0010117 // SVM host state-save area