2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
7 entity openMSP430_8_32_mul_dbus is
9 -- Clocks and reset (low active)
10 dco_clk : in std_logic;
11 lfxt_clk : in std_logic;
12 reset_n : in std_logic;
16 -- Periphery interface
17 per_addr : out std_logic_vector (7 downto 0);
18 per_din : out std_logic_vector (15 downto 0);
19 per_dout : in std_logic_vector (15 downto 0);
20 per_wen : out std_logic_vector (1 downto 0);
21 per_en : out std_logic;
23 irq : in std_logic_vector (13 downto 0);
24 irq_acc : out std_logic_vector (13 downto 0);
25 aclk_en : out std_logic;
26 smclk_en : out std_logic;
30 dmem_addr : out std_logic_vector (11 downto 0);
31 dmem_ce : out std_logic;
32 dmem_we : out std_logic;
33 dmem_din : out std_logic_vector (15 downto 0);
34 dmem_dout : in std_logic_vector (15 downto 0));
35 end entity openMSP430_8_32_mul_dbus;
37 --------------------------------------------------------------------------------
39 architecture rtl of openMSP430_8_32_mul_dbus is
41 component openMSP430 is
43 aclk_en : out std_logic; -- ACLK enable
44 dbg_freeze : out std_logic; -- Freeze peripherals
45 dbg_uart_txd : out std_logic; -- Debug interface: UART TXD
46 dmem_addr : out std_logic_vector; -- Data Memory address
47 dmem_cen : out std_logic; -- Data Memory chip enable (low active)
48 dmem_din : out std_logic_vector (15 downto 0); -- Data Memory data input
49 dmem_wen : out std_logic_vector (1 downto 0); -- Data Memory write enable (low active)
50 irq_acc : out std_logic_vector (13 downto 0); -- Interrupt request accepted (one-hot signal)
51 mclk : out std_logic; -- Main system clock
52 per_addr : out std_logic_vector (7 downto 0); -- Peripheral address
53 per_din : out std_logic_vector (15 downto 0); -- Peripheral data input
54 per_wen : out std_logic_vector (1 downto 0); -- Peripheral write enable (high active)
55 per_en : out std_logic; -- Peripheral enable (high active)
56 pmem_addr : out std_logic_vector; -- Program Memory address
57 pmem_cen : out std_logic; -- Program Memory chip enable (low active)
58 pmem_din : out std_logic_vector (15 downto 0); -- Program Memory data input (optional)
59 pmem_wen : out std_logic_vector (1 downto 0); -- Program Memory write enable (low active) (optional)
60 puc : out std_logic; -- Main system reset
61 smclk_en : out std_logic; -- SMCLK enable
63 dbg_uart_rxd : in std_logic; -- Debug interface: UART RXD
64 dco_clk : in std_logic; -- Fast oscillator (fast clock)
65 dmem_dout : in std_logic_vector (15 downto 0); -- Data Memory data output
66 irq : in std_logic_vector (13 downto 0); -- Maskable interrupts
67 lfxt_clk : in std_logic; -- Low frequency oscillator (typ 32kHz)
68 nmi : in std_logic; -- Non-maskable interrupt (asynchronous)
69 per_dout : in std_logic_vector (15 downto 0); -- Peripheral data output
70 pmem_dout : in std_logic_vector (15 downto 0); -- Program Memory data output
71 reset_n : in std_logic -- Reset Pin (low active)
76 signal inner_dmem_addr : std_logic_vector (12 downto 0);
77 signal inner_dmem_cen : std_logic;
78 signal inner_dmem_din : std_logic_vector (15 downto 0);
79 signal inner_dmem_dout : std_logic_vector (15 downto 0);
80 signal inner_dmem_wen : std_logic_vector (1 downto 0);
82 signal ram_dmem_cen : std_logic;
83 signal mcu_dmem_dout : std_logic_vector (15 downto 0);
85 signal dmem_mux : std_logic;
88 signal pmem_addr : std_logic_vector (13 downto 0);
89 signal pmem_cen : std_logic;
90 signal pmem_din : std_logic_vector (15 downto 0);
91 signal pmem_dout : std_logic_vector (15 downto 0);
92 signal pmem_wen : std_logic_vector (1 downto 0);
94 -- Inner signals used to connect built in components
95 signal inner_mclk : std_logic;
96 signal inner_puc : std_logic;
98 signal inner_per_addr : std_logic_vector (7 downto 0);
99 signal inner_per_din : std_logic_vector (15 downto 0);
100 signal inner_per_dout : std_logic_vector (15 downto 0);
101 signal inner_per_wen : std_logic_vector (1 downto 0);
102 signal inner_per_en : std_logic;
104 signal inner_irq_acc : std_logic_vector (13 downto 0);
105 signal inner_irq : std_logic_vector (13 downto 0);
108 signal uart_dout : std_logic_vector (15 downto 0);
109 signal uart_irq : std_logic;
111 --------------------------------------------------------------------------------
116 openMSP430_0 : openMSP430
120 dbg_uart_txd => open,
121 dmem_addr => inner_dmem_addr,
122 dmem_cen => inner_dmem_cen,
123 dmem_din => inner_dmem_din,
124 dmem_wen => inner_dmem_wen,
125 irq_acc => inner_irq_acc,
127 per_addr => inner_per_addr,
128 per_din => inner_per_din,
129 per_wen => inner_per_wen,
130 per_en => inner_per_en,
131 pmem_addr => pmem_addr,
132 pmem_cen => pmem_cen,
136 smclk_en => smclk_en,
140 dmem_dout => mcu_dmem_dout,
142 lfxt_clk => lfxt_clk,
144 per_dout => inner_per_dout,
145 pmem_dout => pmem_dout,
150 d_ram_hi : entity work.ram_generic
152 BRAM_TYPE => "RAMB16_S4",
160 addr => inner_dmem_addr (11 downto 0),
162 we => inner_dmem_wen (1),
163 din => inner_dmem_din (15 downto 8),
164 dout => inner_dmem_dout (15 downto 8));
166 d_ram_lo : entity work.ram_generic
168 BRAM_TYPE => "RAMB16_S4",
176 addr => inner_dmem_addr (11 downto 0),
178 we => inner_dmem_wen (0),
179 din => inner_dmem_din (7 downto 0),
180 dout => inner_dmem_dout (7 downto 0));
183 p_ram_hi : entity work.ram_generic
185 BRAM_TYPE => "RAMB16_S2",
195 din => pmem_din (15 downto 8),
196 dout => pmem_dout (15 downto 8));
198 p_ram_lo : entity work.ram_generic
200 BRAM_TYPE => "RAMB16_S2",
209 din => pmem_din (7 downto 0),
210 dout => pmem_dout (7 downto 0));
214 uart_o : entity work.uart
217 per_addr => inner_per_addr,
218 per_din => inner_per_din,
219 per_en => inner_per_en,
220 per_wen => inner_per_wen,
224 per_dout => uart_dout,
228 --------------------------------------------------------------------------------
230 process (inner_mclk) is
232 if rising_edge(inner_mclk) then
233 dmem_mux <= inner_dmem_addr (12);
238 mcu_dmem_dout <= inner_dmem_dout when dmem_mux = '0' else
241 ram_dmem_cen <= inner_dmem_cen or inner_dmem_addr (12);
243 dmem_addr <= inner_dmem_addr (11 downto 0);
244 dmem_ce <= (not inner_dmem_cen) and inner_dmem_addr (12);
245 dmem_we <= '1' when inner_dmem_wen = "00" else '0';
246 dmem_din <= inner_dmem_din;
249 inner_per_dout <= uart_dout or per_dout;
252 --inner_irq (6) <= uart_irq;
254 irq_acc <= inner_irq_acc;
256 per_addr <= inner_per_addr;
257 per_din <= inner_per_din;
258 per_wen <= inner_per_wen;
259 per_en <= inner_per_en;