]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/history - .gitmodules
projects / fpga / virtex2 / uart.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
Make RS-232 receiving work. TimerA IRQ connected to the softcore. Sample application...
[fpga/virtex2/uart.git] / .gitmodules
2011-01-09 Vladimir Burian+ OpenMSP430 submodule. blob | commitdiff | raw
MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board