rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/history - Makefile

]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/history - Makefile

projects / fpga / virtex2 / uart.git / history

summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next

[fpga/virtex2/uart.git] / Makefile

2011-02-13	Vladimir Burian	Building procedure changed.	blob \| commitdiff \| raw
2011-01-09	Vladimir Burian	Copied all needed files.	blob \| commitdiff \| raw

MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board