+++ /dev/null
-# TOP - Name of the top-level module
-# DEVICE - Name of the FPGA device (device-package-speed)
-# PRJ - Name of .prj file with names of all source files. See XST manual.
-# BMM - If design contains initialized memories, softcore MCU, etc., this
-# file describes mapping of .elf file to these memories. Only one
-# .bmm file can be used.
-# ELF - File containing initialization data of memories described by
-# previously defined .bmm file. Format can be .elf or .mem.
-# SEARCH_DIRS - Directories to search when searching for netlists (.ngc, ...).
-# See NGDBUILD manual.
-# JTAG_POS - Position of device in JTAG chain. Used when downloading bit stream.
-# INTSTYLE - Style of screen output. (ise | xflow | silent)
-
-
-TOP = openMSP430_uart
-DEVICE = xc2v1000-fg456
-
-PRJ = openMSP430_uart.prj
-
-BMM = memory.bmm
-ELF = software/ta_uart.elf
-
-SEARCH_DIRS = coregen
-
-JTAG_POS = 2
-INTSTYLE = xflow
-
-
-ifneq (${strip ${BMM}},)
- BITFILE = ${TOP}_rp.bit
-else
- BITFILE = ${TOP}.bit
-endif
-
-#===============================================================================
-
-.PHONY: all synth ngdbuild map implement download clean
-
-all: clean implement
-
-implement: ${BITFILE}
-
-#===============================================================================
-
-synth ${TOP}.ngc: ${PRJ}
- echo " \
- run \
- ${addprefix -ifn ,${PRJ}} \
- -ifmt mixed \
- -ofn ${TOP}.ngc \
- -ofmt NGC \
- -top ${TOP} \
- -p ${DEVICE} \
- -opt_mode Speed \
- -opt_level 1" \
- | xst
-
-
-ngdbuild ${TOP}.ngd: ${TOP}.ngc ${BMM} ${TOP}.ucf
- ngdbuild \
- ${addprefix -bm ,${BMM}} \
- -intstyle ${INTSTYLE} \
- -p ${DEVICE} \
- -uc ${TOP}.ucf \
- ${addprefix -sd ,${SEARCH_DIRS}} \
- ${TOP}.ngc \
- ${TOP}.ngd
-
-
-map ${TOP}.ncd: ${TOP}.ngd
- map \
- -p ${DEVICE} \
- -intstyle ${INTSTYLE} \
- ${TOP}.ngd \
- ${TOP}.pcf
- par \
- -w ${TOP}.ncd \
- -intstyle ${INTSTYLE} \
- ${TOP}.ncd \
- ${TOP}.pcf
-
-
-${TOP}.bit: ${TOP}.ncd
- bitgen -w ${TOP}.ncd ${TOP}.bit ${TOP}.pcf
-
-${TOP}_rp.bit: ${TOP}.bit ${ELF}
- data2mem -bm ${basename ${BMM}}_bd.bmm -bd ${ELF} -bt ${TOP}.bit -o b ${TOP}_rp.bit
-
-download: ${BITFILE}
- /bin/echo -e "\
- setMode -bscan \n\
- cleancablelock \n\
- setCable -port auto \n\
- identify \n\
- assignFile -p ${JTAG_POS} -file ${BITFILE} \n\
- program -p ${JTAG_POS} \n\
- exit" | impact -batch
-
-#===============================================================================
-
-clean:
- rm -f _impactbatch.log
- rm -f ${basename ${BMM}}_bd.bmm
- rm -f netlist.lst
- rm -f ${TOP}.bgn
- rm -f ${TOP}.bit
- rm -f ${TOP}.bld
- rm -f ${TOP}.d
- rm -f ${TOP}.drc
- rm -f ${TOP}.lso
- rm -f ${TOP}.map
- rm -f ${TOP}.mrp
- rm -f ${TOP}.ncd
- rm -f ${TOP}.ngc
- rm -f ${TOP}.ngd
- rm -f ${TOP}.ngm
- rm -f ${TOP}.pad
- rm -f ${TOP}_pad.csv
- rm -f ${TOP}_pad.txt
- rm -f ${TOP}.par
- rm -f ${TOP}.pcf
- rm -f ${TOP}_rp.bit
- rm -f ${TOP}_summary.xml
- rm -f ${TOP}.unroutes
- rm -f ${TOP}_usage.xml
- rm -f ${TOP}.xpi
- rm -rf xst
-
-#===============================================================================
-
-%.d: %.prj
- sed -e 's/#.*//' \
- -e 's/[ \t][ \t]*/ /g' \
- -e 's/^ //' -e 's/ $$//' \
- -e 's|\(.*\) \(.*\) \(.*\)|$<: \3|' \
- <$< >$@
-
-%.prj:
- touch $@
-
-include ${PRJ:.prj=.d}
-
--- /dev/null
+# TOP - Name of the top-level module
+# DEVICE - Name of the FPGA device (device-package-speed)
+# PRJ - Name of .prj file with names of all source files. See XST manual.
+# BMM - If design contains initialized memories, softcore MCU, etc., this
+# file describes mapping of .elf file to these memories. Only one
+# .bmm file can be used.
+# ELF - File containing initialization data of memories described by
+# previously defined .bmm file. Format can be .elf or .mem.
+# When the file does not exist, make is called in ELF directory with
+# ELF file name as a target.
+# SEARCH_DIRS - Directories to search when searching for netlists (.ngc, ...).
+# See NGDBUILD manual.
+# JTAG_POS - Position of device in JTAG chain. Used when downloading bit stream.
+# INTSTYLE - Style of screen output. (ise | xflow | silent)
+# SRC - Path to the source directory. All other paths are relative to this.
+
+
+# Targets desctiption:
+# - synthesize : Synthesize all VHDL and Verilog source files, libraries, etc.
+# defined in PRJ files and produces NGC file.
+# - translate : Translate all netlist files (.ngc, ...) into the NGD file,
+# where the design is described in terms of deneral logic elements
+# such as (RAM, flip-flop, XOR, ...).
+# - map : Map the general logic from NGD file to the components in the
+# target FPGA and produces NCD_MAP file.
+# - par : PAR stands for Plase & Route. This procedure takes NCD_MAP file,
+# places all components and makes routes between them (depending
+# on the chosen optimization mode) and produces NCD file.
+# - implement : Transfer placed and routed NCD file into the bit file, which can
+# be then used to configure particular FPGA. When ELF and BMM is
+# specified, this procedure fills in location constraints of all
+# memories in BMM and initialize them with data from ELF.
+# - download : Download bitfile to the target FPGA (by using Impact).
+# - clean : Clean build directory, dependency (*.d) files and call
+# 'make clean' in the directory of ELF file.
+# - all : Do 'clean' and 'implement' targets.
+
+# Dependicies are handled, so in most cases only 'download' target is called.
+
+
+TOP = openMSP430_uart
+DEVICE = xc2v1000-fg456
+
+PRJ = ${TOP}.prj
+UCF = ${TOP}.ucf
+
+BMM = memory.bmm
+ELF = software/ta_uart.elf
+
+SEARCH_DIRS = coregen
+
+JTAG_POS = 2
+INTSTYLE = xflow
+
+SRC = ..
+
+#===============================================================================
+# Abbreviations of frequently used file names.
+
+ifneq (${strip ${ELF}},)
+ BITFILE = ${TOP}_elf.bit
+else
+ BITFILE = ${TOP}.bit
+endif
+
+BMM_BD = ${basename ${BMM}}_bd.bmm
+
+NGC = ${TOP}.ngc
+NGD = ${TOP}.ngd
+PCF = ${TOP}.pcf
+NCD_MAP = ${TOP}_map.ncd
+NCD = ${TOP}.ncd
+
+#===============================================================================
+
+.PHONY: all synthesize translate map par implement download download-only clean
+.PHONY: re-synthesize re-translate re-map re-par
+
+implement: ${BITFILE}
+
+all: clean implement
+
+#===============================================================================
+
+synthesize: ${NGC}
+re-synthesize ${NGC}: ${SRC}/${PRJ}
+ echo " \
+ run \
+ ${addprefix -ifn ${SRC}/,${PRJ}} \
+ -ifmt mixed \
+ -ofn ${TOP}.ngc \
+ -ofmt NGC \
+ -top ${TOP} \
+ -p ${DEVICE} \
+ -opt_mode Speed \
+ -opt_level 1" \
+ | xst
+
+
+translate: ${NGD}
+re-translate ${NGD}: ${NGC} ${SRC}/${BMM} ${SRC}/${UCF}
+ifneq (${strip ${BMM}},)
+ ln -s -f ${SRC}/${BMM} ${BMM}
+endif
+ ngdbuild -intstyle ${INTSTYLE} -p ${DEVICE} -uc ${SRC}/${UCF} \
+ ${addprefix -bm ,${BMM}} \
+ ${addprefix -sd ${SRC}/,${SEARCH_DIRS}} \
+ ${NGC} \
+ ${NGD}
+
+map: ${NCD_MAP} ${PCF}
+re-map ${NCD_MAP} ${PCF}: ${NGD}
+ map -intstyle ${INTSTYLE} -o ${NCD_MAP} ${NGD} ${PCF}
+
+par: ${NCD}
+re-par ${NCD}: ${NCD_MAP} ${PCF}
+ par -intstyle ${INTSTYLE} ${NCD_MAP} ${NCD} ${PCF}
+
+${TOP}.bit ${BMM_BD}: ${NCD}
+ bitgen -w ${NCD} ${TOP}.bit ${PCF}
+
+${TOP}_elf.bit: ${TOP}.bit ${BMM_BD} ${SRC}/${ELF}
+ data2mem -bm ${BMM_BD} -bd ${SRC}/${ELF} -bt ${TOP}.bit -o b ${TOP}_elf.bit
+
+.PHONY: ${SRC}/${ELF}
+${SRC}/${ELF}:
+ make -C ${dir $@} ${nodir $@}
+
+download: ${BITFILE} download-only
+download-only:
+ /bin/echo -e "\
+ setMode -bscan \n\
+ cleancablelock \n\
+ setCable -port auto \n\
+ identify \n\
+ assignFile -p ${JTAG_POS} -file ${BITFILE} \n\
+ program -p ${JTAG_POS} \n\
+ exit" | impact -batch
+
+#===============================================================================
+
+clean:
+ ls | grep -v ^Makefile$$ | xargs rm -rf
+ rm -f ${addprefix ${SRC}/,${PRJ:.prj=.d}}
+ make -C ${SRC}/${dir ${ELF}} clean
+
+#===============================================================================
+
+%.d: %.prj
+ @sed -e 's/#.*//' \
+ -e 's/[ \t][ \t]*/ /g' \
+ -e 's/^ //' -e 's/ $$//' \
+ -e '/"/d' \
+ -e '/^$$/d' \
+ -e 's|\(.*\) \(.*\) \(.*\)|$<: ${dir $<}\3|' \
+ <$< >$@
+
+%.prj:
+ touch $@
+
+include ${addprefix ${SRC}/,${PRJ:.prj=.d}}
+