]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/commit
Toplevel UART signals renamed.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Sat, 12 Feb 2011 20:54:15 +0000 (21:54 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Sun, 13 Feb 2011 12:46:28 +0000 (13:46 +0100)
commitbecb341a3d46f3a6458ce87a4f531f81e03e84b2
tree26c11941dc71355c2af8d036fcc36f186e44d07c
parent5793e4aff64fad0fe712536bf9c7c385dcd82fa8
Toplevel UART signals renamed.

TXD and RXD names in the top-level desing exchanged so it makes more sense.
openMSP430_uart.ucf
openMSP430_uart.vhd