Toplevel UART signals renamed.

[fpga/virtex2/uart.git] / openMSP430_uart.vhd

diff --git a/openMSP430_uart.vhd b/openMSP430_uart.vhd
index 27c4acccb0029cf81c43036a0dcf00cc5755db15..bdd92f6c764508fecc6713f9938c8b9b55959141 100644 (file)
--- a/openMSP430_uart.vhd
+++ b/openMSP430_uart.vhd
@@ -8,8 +8,8 @@ entity openMSP430_uart is
     CLK_24MHz: in std_logic;
     RESET: in std_logic;
 
-    RXD : out std_logic;
-    TXD : in std_logic;
+    RXD : in std_logic;
+    TXD : out std_logic;
     
     ROT_FEED : out std_logic;
     ROT_A : in std_logic;
@@ -242,8 +242,8 @@ begin
     per_irq     => uart_irq,
     per_dout    => uart_dout,
 
-    rxd         => TXD,
-    txd         => RXD
+    rxd         => RXD,
+    txd         => TXD
   );