1 --------------------------------------------------------------------------------
2 -- This file is owned and controlled by Xilinx and must be used --
3 -- solely for design, simulation, implementation and creation of --
4 -- design files limited to Xilinx devices or technologies. Use --
5 -- with non-Xilinx devices or technologies is expressly prohibited --
6 -- and immediately terminates your license. --
8 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
9 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
10 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
11 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
12 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
13 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
14 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
15 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
16 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
17 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
18 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
19 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
20 -- FOR A PARTICULAR PURPOSE. --
22 -- Xilinx products are not intended for use in life support --
23 -- appliances, devices, or systems. Use in such applications are --
24 -- expressly prohibited. --
26 -- (c) Copyright 1995-2007 Xilinx, Inc. --
27 -- All rights reserved. --
28 --------------------------------------------------------------------------------
29 -- The following code must appear in the VHDL architecture header:
31 ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
34 addr: IN std_logic_VECTOR(8 downto 0);
36 din: IN std_logic_VECTOR(7 downto 0);
37 dout: OUT std_logic_VECTOR(7 downto 0);
42 -- Synplicity black box declaration
43 attribute syn_black_box : boolean;
44 attribute syn_black_box of ram_8x512: component is true;
46 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
48 -- The following code must appear in the VHDL architecture
49 -- body. Substitute your own instance name and net names.
51 ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
52 your_instance_name : ram_8x512
60 -- INST_TAG_END ------ End INSTANTIATION Template ------------
62 -- You must compile the wrapper file ram_8x512.vhd when simulating
63 -- the core, ram_8x512. When compiling the wrapper file, be sure to
64 -- reference the XilinxCoreLib VHDL simulation library. For detailed
65 -- instructions, please refer to the "CORE Generator Help".