Pavel Pisa [Sat, 24 May 2014 21:22:24 +0000 (23:22 +0200)]
RoCoN: FPGA access has to be initialized before PXMC initialization.
The actual change is still incorrect, because FPGA
is not programmed before PXMC start. But if LPC external
interface is not setup then whole application blocks.
Martin Meloun [Sun, 11 May 2014 21:43:17 +0000 (23:43 +0200)]
Multiple patches
1) USB sendhex forked due to changes (patch included)
2) Synthesis profiling for HW
3) Added LX master
4) Calbration -> Measuerement
5) Master CPU bus is 50 MHz and wired to Tumbl external bus,
fixes in wiring
6) Cleanups
7) Other crap I forgot in the meantime :-)
Signed-off-by: Martin Meloun <meloumar@cmp.felk.cvut.cz>
Martin Meloun [Wed, 18 Sep 2013 14:18:44 +0000 (16:18 +0200)]
Multiple changes in FPGA, include Tumbl coprocessor
- remove deprecated control bram
- remove testing bcd counter
- fix IRC indexing reacting on index level
- update ucf file
- Tumbl: add sumbodule
- Tumbl: add lx-rocon implementation for Spartan6
- Tumbl: add primitive firmware (requires MicroBlaze binutils and gcc to compile)
- do not use coregen, infer the bram or use primitives
- Master CPU bus: now on 100 MHz instead of 72 MHz
- Master CPU bus: rd / bls is async and filtered
Martin Meloun [Fri, 30 Aug 2013 16:35:10 +0000 (18:35 +0200)]
FPGA: Improvements & Fixes
1) Fix hazardous states when issuing reset (and derps too)
2) Implement calibration registers for reading and writing
on the CPU memory bus
3) bus_id register removed, became calibration register
and implemented properly
4) Implement BCD properly
5) Fix IRC modules (correct indexing)
6) Update testbench to simulate more events
In detail
dff: Fix reset
bcd: Improve implementation
calibration: Added registers for read / write with delay secured
to be longer than for normal transactions (held by extra cycle).
These registers are then used for normal operation. Note that the bus
is synchronous to the CPU / EMC!
irc: Fix reset (hold the asynchronous event by one more cycle to prevent
accounting milions of units based on unstability of the output) and
fixed indexing (does not delay by one cycle)
testbenches: Mostly fixed reset polarity, top module has extra transactions
for the simulation
Martin Meloun [Sun, 25 Aug 2013 20:48:28 +0000 (22:48 +0200)]
Implement interfaces for FPGA
Implemented USB_VENDOR_CALL, used during configuration of the FPGA device.
Implmented FPGA configuration and EMC initialization. At this moment, EMC uses
the longest delays and is not calibrated for performance.
Martin Meloun [Sun, 25 Aug 2013 20:44:51 +0000 (22:44 +0200)]
FPGA: Bugfixes, custom packaging and added testing modules
1) Bugfixes all over the place from initial testing,
especially on the memory bus
2) Use CLKOUT as clock source by default (72 MHz)
3) Add packaging for SelectMAP configuration interface
4) Add some more testing modules (BCD and other ID register)
Martin Meloun [Sun, 18 Aug 2013 11:19:56 +0000 (13:19 +0200)]
Add FPGA sources with Makefile
Requires installed Xilinx ISE and it's build tools in search directory. Includes
sources for testbenches and doesn't include project file for Xilinx ISE.
Signed-off-by: Martin Meloun <meloumar@cmp.felk.cvut.cz>
Pavel Pisa [Fri, 11 Jan 2013 01:14:37 +0000 (02:14 +0100)]
RoCoN: Configure USB to be included in RoCoN application.
This allows to request board reset over USB even
when application runs. When board is reset it goes through
bootblock and can be stop there and new application version
flashed.
USB to uLAN converter functionality is disabled.
It has no use for robotic (controller at lest now)
and ul_drv submodule is not included to the build.
Pavel Pisa [Fri, 11 Jan 2013 00:45:14 +0000 (01:45 +0100)]
RoCoN: define PXMC and application periodic activation.
The system clock interrupt runs at 1kHz (SYS_TIMER_HZ).
The PXMC runs at same frequency. Slow(er) activities
are run at 100 Hz (APPL_SLOW_SFI_USEC is 10000 usec).
Pavel Pisa [Sun, 6 Jan 2013 23:20:33 +0000 (00:20 +0100)]
RoCoN project started.
The aim of this project is to build robotic
motion control system based on LX_CPU1 board
designed by Petr Porazil. Board combines
NXP LPC1788, Xilinx Spartan 6 FPGA and 32 MB
of SDRAM.
Included template based on PiKRON embedded projects
to allow build of sysless and other libraries.
projects / fpga / lx-cpu1 / lx-rocon.git / log