RoCoN: extended to actual 8x IRC/axes design and lxpwr master initialization added.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>

diff --git a/sw/app/rocon/appl_pxmc.c b/sw/app/rocon/appl_pxmc.c
index 4572667cee4dc1792f0ac79040d9988dc1befaac..9a2721e0805b7dc34967b1eac347dadd9b2a83bd 100644 (file)
--- a/sw/app/rocon/appl_pxmc.c
+++ b/sw/app/rocon/appl_pxmc.c
@@ -30,7 +30,7 @@
 #include "appl_defs.h"
 #include "appl_fpga.h"
 
-#define PXML_MAIN_CNT 4
+#define PXML_MAIN_CNT 8
 
 #define PXMC_WITH_PT_ZIC 1
 #define PXMC_PT_ZIC_MASK 0x8000
@@ -321,31 +321,48 @@ pxmc_rocon_pwm_out(pxmc_state_t *mcs)
   return 0;
 }
 
+uint32_t pxmc_rocon_pwm_dummy_reg;
+
+static inline volatile uint32_t *
+pxmc_rocon_pwm_chan2reg(unsigned chan)
+{
+  volatile uint32_t *pwm_reg;
+
+  if (chan >= 16)
+    return &pxmc_rocon_pwm_dummy_reg;
+
+  pwm_reg = fpga_lx_master_transmitter_base;
+  pwm_reg += 1 + (chan >> 8) + chan;
+  return pwm_reg;
+}
+
+
 int
 pxmc_rocon_pwm_dc_out(pxmc_state_t *mcs)
 {
-  volatile uint32_t *pwm_reg;
+  volatile uint32_t *pwm_reg_a, *pwm_reg_b;
   int chan = mcs->pxms_out_info;
   int ene = mcs->pxms_ene;
 
   if (chan > 6)
     return 0;
 
-  pwm_reg = fpga_lx_master_transmitter_base + 1 + chan;
+  pwm_reg_a = pxmc_rocon_pwm_chan2reg(chan + 0);
+  pwm_reg_b = pxmc_rocon_pwm_chan2reg(chan + 1);
 
   if (ene < 0) {
     ene = -ene;
     if (ene > 0x7fff)
       ene = 0x7fff;
     ene = (ene * (2500 + 5)) >> 15;
-    pwm_reg[0] = 0;
-    pwm_reg[1] = ene | 0x4000;
+    *pwm_reg_a = 0;
+    *pwm_reg_b = ene | 0x4000;
   } else {
     if (ene > 0x7fff)
       ene = 0x7fff;
     ene = (ene * (2500 + 5)) >> 15;
-    pwm_reg[1] = 0;
-    pwm_reg[0] = ene | 0x4000;
+    *pwm_reg_b = 0;
+    *pwm_reg_a = ene | 0x4000;
   }
 
   return 0;
@@ -353,12 +370,19 @@ pxmc_rocon_pwm_dc_out(pxmc_state_t *mcs)
 
 /* PWM outputs placed on (PWM1), PWM2, PWM4, PWM6 */
 int
-pxmc_rocon_pwm_init(pxmc_state_t *mcs, int mode)
+pxmc_rocon_pwm_master_init(void)
 {
+  int i;
 
-  /* hal_pin_conf(PWM1_EN_PIN); */
+  *fpga_lx_master_reset = 1;
+  *fpga_lx_master_transmitter_reg = 0;
 
-  /* hal_gpio_set_value(PWM1_EN_PIN,1); */
+  for (i = 0; i < 16 + 3; i ++)
+    fpga_lx_master_transmitter_base[0] = 0;
+
+  fpga_lx_master_transmitter_base[0] = 8;
+
+  *fpga_lx_master_reset = 0;
 
   return 0;
 }
@@ -572,9 +596,141 @@ pxms_cfg:
   pxms_hal: 0x40,
 };
 
+pxmc_state_t mcs4 =
+{
+pxms_flg:
+  PXMS_ENI_m,
+pxms_do_inp:
+  pxmc_inp_rocon_inp,
+pxms_do_con:
+  pxmc_pid_con,
+pxms_do_out:
+  pxmc_rocon_pwm_dc_out,
+  pxms_do_deb: 0,
+  pxms_do_gen: 0,
+pxms_do_ap2hw:
+  pxmc_inp_rocon_ap2hw,
+  pxms_ap: 0, pxms_as: 0,
+  pxms_rp: 55 * 256, pxms_rs: 0, pxms_subdiv: 8,
+  pxms_md: 800 << 8, pxms_ms: 1000, pxms_ma: 10,
+  pxms_inp_info: 4,
+  pxms_out_info: 8,
+  pxms_ene: 0, pxms_erc: 0,
+  pxms_p: 80, pxms_i: 30, pxms_d: 200, pxms_s1: 200, pxms_s2: 0,
+  pxms_me: 0x7e00/*0x7fff*/,
+pxms_cfg:
+  PXMS_CFG_SMTH_m | PXMS_CFG_MD2E_m | PXMS_CFG_HLS_m | PXMS_CFG_I2PT_m * 0 |
+  0x1,
+
+  pxms_ptper: 1,
+  pxms_ptirc: 1000,
+  /*pxms_ptamp: 0x7fff,*/
+
+  pxms_hal: 0x40,
+};
+
+pxmc_state_t mcs5 =
+{
+pxms_flg:
+  PXMS_ENI_m,
+pxms_do_inp:
+  pxmc_inp_rocon_inp,
+pxms_do_con:
+  pxmc_pid_con,
+pxms_do_out:
+  pxmc_rocon_pwm_dc_out,
+  pxms_do_deb: 0,
+  pxms_do_gen: 0,
+pxms_do_ap2hw:
+  pxmc_inp_rocon_ap2hw,
+  pxms_ap: 0, pxms_as: 0,
+  pxms_rp: 55 * 256, pxms_rs: 0, pxms_subdiv: 8,
+  pxms_md: 800 << 8, pxms_ms: 1000, pxms_ma: 10,
+  pxms_inp_info: 5,
+  pxms_out_info: 10,
+  pxms_ene: 0, pxms_erc: 0,
+  pxms_p: 80, pxms_i: 30, pxms_d: 200, pxms_s1: 200, pxms_s2: 0,
+  pxms_me: 0x7e00/*0x7fff*/,
+pxms_cfg:
+  PXMS_CFG_SMTH_m | PXMS_CFG_MD2E_m | PXMS_CFG_HLS_m | PXMS_CFG_I2PT_m * 0 |
+  0x1,
+
+  pxms_ptper: 1,
+  pxms_ptirc: 1000,
+  /*pxms_ptamp: 0x7fff,*/
+
+  pxms_hal: 0x40,
+};
+
+pxmc_state_t mcs6 =
+{
+pxms_flg:
+  PXMS_ENI_m,
+pxms_do_inp:
+  pxmc_inp_rocon_inp,
+pxms_do_con:
+  pxmc_pid_con,
+pxms_do_out:
+  pxmc_rocon_pwm_dc_out,
+  pxms_do_deb: 0,
+  pxms_do_gen: 0,
+pxms_do_ap2hw:
+  pxmc_inp_rocon_ap2hw,
+  pxms_ap: 0, pxms_as: 0,
+  pxms_rp: 55 * 256, pxms_rs: 0, pxms_subdiv: 8,
+  pxms_md: 800 << 8, pxms_ms: 1000, pxms_ma: 10,
+  pxms_inp_info: 6,
+  pxms_out_info: 12,
+  pxms_ene: 0, pxms_erc: 0,
+  pxms_p: 80, pxms_i: 30, pxms_d: 200, pxms_s1: 200, pxms_s2: 0,
+  pxms_me: 0x7e00/*0x7fff*/,
+pxms_cfg:
+  PXMS_CFG_SMTH_m | PXMS_CFG_MD2E_m | PXMS_CFG_HLS_m | PXMS_CFG_I2PT_m * 0 |
+  0x1,
+
+  pxms_ptper: 1,
+  pxms_ptirc: 1000,
+  /*pxms_ptamp: 0x7fff,*/
+
+  pxms_hal: 0x40,
+};
+
+pxmc_state_t mcs7 =
+{
+pxms_flg:
+  PXMS_ENI_m,
+pxms_do_inp:
+  pxmc_inp_rocon_inp,
+pxms_do_con:
+  pxmc_pid_con,
+pxms_do_out:
+  pxmc_rocon_pwm_dc_out,
+  pxms_do_deb: 0,
+  pxms_do_gen: 0,
+pxms_do_ap2hw:
+  pxmc_inp_rocon_ap2hw,
+  pxms_ap: 0, pxms_as: 0,
+  pxms_rp: 55 * 256, pxms_rs: 0, pxms_subdiv: 8,
+  pxms_md: 800 << 8, pxms_ms: 1000, pxms_ma: 10,
+  pxms_inp_info: 7,
+  pxms_out_info: 14,
+  pxms_ene: 0, pxms_erc: 0,
+  pxms_p: 80, pxms_i: 30, pxms_d: 200, pxms_s1: 200, pxms_s2: 0,
+  pxms_me: 0x7e00/*0x7fff*/,
+pxms_cfg:
+  PXMS_CFG_SMTH_m | PXMS_CFG_MD2E_m | PXMS_CFG_HLS_m | PXMS_CFG_I2PT_m * 0 |
+  0x1,
+
+  pxms_ptper: 1,
+  pxms_ptirc: 1000,
+  /*pxms_ptamp: 0x7fff,*/
+
+  pxms_hal: 0x40,
+};
+
 
 pxmc_state_t *pxmc_main_arr[PXML_MAIN_CNT] =
-{&mcs0, &mcs1, &mcs2, &mcs3};
+{&mcs0, &mcs1, &mcs2, &mcs3, &mcs4, &mcs5, &mcs6, &mcs7};
 
 
 pxmc_state_list_t  pxmc_main_list =
@@ -859,7 +1015,7 @@ int pxmc_initialize(void)
   /*pxmc_ctm4pwm3f_wr(mcs, 0, 0, 0);*/
   //pxmc_rocon_pwm3ph_wr(mcs, 0, 0, 0);
 
-  pxmc_rocon_pwm_init(mcs, 0);
+  pxmc_rocon_pwm_master_init();
 
   pxmc_main_list.pxml_cnt = 0;
   pxmc_dbg_hist = NULL;