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drm: xlnx: crtc: Fix max width and height overflow
2018-11-19 Vishal Sagardrm: xlnx: crtc: Fix max width and height overflow
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-19 Vishal Sagardrm: xlnx: dsi: Fix kernel panic when "halt" is run
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarxilinx: v4l: dma: Stop subdevs in reverse order of...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: pl_disp: Enable early callback
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardma: xilinx: Add early callback support to Framebuffer...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardma: xilinx: Fix compilation errors when kernel config...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: Select VIDEOMODE_HELPERS when DRM_XLNX_PL_DISP...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx: vpss-scaler: Correct default values when...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx-gamma: Correct default values when max...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx-demosaic: Correct default values when width...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: mixer: Fix switching to 4K after 1080p
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx: xcsi2rxss: Add VCX support
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardt-bindings: csi2rxss: Enable VCX support
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: scaler: Fix array out of bound access
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx: vpss-scaler: Fix array out of bound access
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx-vpss-scaler: Add check for max width and...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardocumentation: dt: vpss-scaler: Add support for max...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx-vpss-csc: Add check for max width and height
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardocumentation: dt: vpss-csc: Add support for max width...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx-gamma: Add check for max width and height
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardocumentation: dt: gamma: Add support for max width...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx-demosaic: Add check for max width and height
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardocumentation: dt: demosaic: add support for max width...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx: tpg: Add check for max width and height
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardocumentation: dt: vtpg: Add support for max width...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardma: xilinx: Add check for max width and height in...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardocumentation: dt: frmbuf: Add support for max width...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Fix clearing en_st352_c and use_ds2_3ga...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardma: xilinx: Move XILINX_FRMBUF out of XILINX_DMA_ENGINES
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: mixer: Fix linking failure for ARCH arm
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Add support for DS2 payload in 3GA...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Add ST352 payload insertion in Chroma...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardt-bindings: display: xlnx: Add ST352 payload insertion...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Enable support for ancillary data
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardt-bindings: display: xlnx: Add support for ancillary...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Fix timing for 720x486i SD mode
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagararm64: zynqmp: Enable AXI4-Stream Switch flag in default...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx: Driver support for Xilinx AXI4-Stream...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardt: bindings: media: xilinx: Doc for Xilinx AXI4-Stream...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx: sdirxss: Add support for clock framework
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardt: bindings: media: xilinx: sdirxss : Add clock framework...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: vtc: Program Field 1 VTC registers in interlaced...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: vtc: Add support for Field 1 Active size
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Program Field 1 VTC registers in interlaced...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Add support for Field 1 Active size
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Fix the VSync_Start and VSync_End for...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Fix the Vertical Field 1 Size calculation
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Fix the HSIZE calculation
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: sdi: Fix VTC polarity for SD modes
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: vtc: Update license to SPDX
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: pl_disp: Add VTC bridge support
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardt-bindings: display: xlnx: Add VTC bridge support...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: mixer: Add VTC bridge support.
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardt-bindings: display: xlnx: mixer: Adding xlnx vtc...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: vtc: Adding VTC as bridge driver
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardt-bindings: display: xlnx: Add VTC bindings
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagardrm: xlnx: bridge: Add support for VTC as bridge
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-11-07 Vishal Sagarv4l: xilinx: sdirxss: Correct the height of SD 525i...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-03 Vishal Sagarv4l: xilinx: dma: Terminate DMA when media pipeline...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal Sagardma: xilinx: Add fid property for interlaced support...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal Sagardt-bindings: dma: Add fid property for interlaced video
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal Sagardma: xilinx: Flush the framebuffer FIFO on halt
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal Sagarv4l: xilinx: dma: Add interlaced support
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal Sagardma: xilinx: Get DMA alignment from device tree for...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal SagarDocumentation: devicetree: bindings: dma: Add properties...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal Sagardma: xilinx: Add alpha formats support for Framebuffer...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal SagarDocumentation: devicetree: bindings: dma: Add alpha...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-05-02 Vishal Sagardma: xilinx: Add interlaced support to Xilinx Framebuffer...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-05-02 Vishal Sagarv4l: xilinx: sdirxss: Correct the v4l2_field to V4L2_FIELD_A...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-05-02 Vishal Sagararm64: zynqmp: config: Enable soft PL V4L drivers
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-16 Vishal Sagarmedia: xilinx: vip: Correct the fourcc code for BGRX8...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-16 Vishal Sagardma: xilinx: Correct the V4L fourcc for BGRX8 in framebuffer...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-16 Vishal SagarDocumentation: devicetree: bindings: dma: Correct the...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-16 Vishal Sagarv4l: xilinx: Add BGR color format support.
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-16 Vishal Sagardma: xilinx: Add support for BGR8 color format in Framebuffer
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-16 Vishal SagarDocumentation: devicetree: bindings: dma: Add support...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: sdirxss: Add support for YUV420 decoding
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-03-15 Vishal Sagardt: bindings: media: xilinx: Add YUV420 decoding support...
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-03-15 Vishal Sagardrm: drm_fourcc: Correct the DRM YUV444 10bpc
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: csi2rxss: Add rev 3.0 compatible string
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagardt: bindings: media: xilinx: Add rev 3.0 to csi2rxss...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: csi2rxss: Switch to fwnode to fix compilation...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: sdirxss: Update Video lockout Window to...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: sdirxss: Add V4L control for 3G Level...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: sdirxss: Add V4L control for Active streams
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: sdirxss: Add v4l control for transport...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: sdirxss: Add support for subdev get frame...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: sdirxss: Add ST352 decode macros
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: sdirxss: Decode ST352 in irq context
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarv4l: xilinx: Driver support for Xilinx UHDSDI Rx subsystem
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagardt: bindings: media: xilinx: Documentation for Xilinx...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarxcsi2rxss: Add support for Xilinx CSI-2 Receiver Subsystem
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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2018-03-15 Vishal Sagarxcsi2rxss: Add DT documentation for Xilinx MIPI CSI...
Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
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