]> rtime.felk.cvut.cz Git - zynq/linux.git/commit
drm: xlnx: sdi: Add support for Field 1 Active size
authorVishal Sagar <vishal.sagar@xilinx.com>
Wed, 25 Jul 2018 10:25:18 +0000 (15:55 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 7 Nov 2018 10:02:51 +0000 (11:02 +0100)
commit3777acc985f83451b4ea5c4b323bc9544c51198d
tree4319c82dfac3bf44bbfcc254ce0ad4b63b245544
parent0fb71e1c197b0d32bd923b4d3f96d56c733363fd
drm: xlnx: sdi: Add support for Field 1 Active size

Add support for the new Field 1 Active register in the VTC for
interlaced mode. In some interlaced modes, the field 0 and 1 active size
may be different. To support such modes, this new register is added to
the VTC. Writing to this register in progressive mode is optional.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/gpu/drm/xlnx/xlnx_sdi_timing.c