drm: xlnx: sdi: Add support for Field 1 Active size

Add support for the new Field 1 Active register in the VTC for
interlaced mode. In some interlaced modes, the field 0 and 1 active size
may be different. To support such modes, this new register is added to
the VTC. Writing to this register in progressive mode is optional.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/gpu/drm/xlnx/xlnx_sdi_timing.c b/drivers/gpu/drm/xlnx/xlnx_sdi_timing.c
index 1769f3f66dfadc0b848e58a9bf4ddfb4cacdbb4a..b74b2d21c03f7f2f610a35a5d999c96175c03917 100644 (file)
--- a/drivers/gpu/drm/xlnx/xlnx_sdi_timing.c
+++ b/drivers/gpu/drm/xlnx/xlnx_sdi_timing.c
@@ -28,6 +28,7 @@
 #define XSTC_GVBH_F1   0x88
 #define XSTC_GVSYNC_F1 0x8C
 #define XSTC_GVSH_F1   0x90
+#define XSTC_GASIZE_F1 0x94
 #define XSTC_OFFSET    0x10000
 
 /* timing controller register bit */
@@ -331,6 +332,10 @@ void xlnx_stc_sig(void __iomem *base, struct videomode *vm)
        reg = hactive & XSTC_GA_ACTSIZE_MASK;
        reg |= (vactive & XSTC_GA_ACTSIZE_MASK) << 16;
        xlnx_stc_writel(base, XSTC_GASIZE, reg);
+
+       if (vm->flags & DISPLAY_FLAGS_INTERLACED)
+               xlnx_stc_writel(base, XSTC_GASIZE_F1, reg);
+
        reg = hsync_start & XSTC_GH1_SYNCSTART_MASK;
        reg |= (hbackporch_start << XSTC_GH1_BPSTART_SHIFT) &
               XSTC_GH1_BPSTART_MASK;