Preetesh Parekh [Fri, 3 Jun 2016 02:21:46 +0000 (19:21 -0700)]
drm: xilinx: crtc: Add crtc set config helper
The goal is to be able to synchronize resolution changes between the
drm device and emulated fbdev device if both devices are used by an
application e.g. in Qt we use both graphics and video layer whereas
the former is controlled by fbdev and the latter by drm. This patch
propagates resolution changes from the drm device to fbdev. Before
setting the new mode, a copy of the old mode is saved locally and
restored upon last close.
work in progres:
If hot-plug events happen while the application is running, the mode
pre-application start will be restored instead of the mode set by the
last hot-plug event. For example if we switch monitors from 1080p to
4k while the application is running, last close will restore the
fbconsole to 1080p on the 4k monitor. The framebuffer for the fbdev
emulation is allocated when the driver is initialized, thus hotplug
between monitors with different resolutions
(ex, 2560x1440->1920x1080) wouldn’t work correctly as of now.
Michael Gill [Fri, 3 Jun 2016 01:21:20 +0000 (18:21 -0700)]
staging: apf: Fixed DMA-BUF used of buffers spanning partial pages
The DRM infrastructure when using the xilinx driver has a
potential to return a buffer mapped to a memory region spanning a
partial page, such as in the case of a 1920x1080 resolution
buffer. When this happens, the scatterlist returned from the DRM
API describes a region rounded up to a whole page. This patch
trims the returned scatterlist, thus making it usable by a DMA.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 3 Jun 2016 01:21:19 +0000 (18:21 -0700)]
staging: apf: Fix length for non-aligned(4K) DMA-BUF SG
Iterate through DMA-BUF SG list and set length equal to
buffer size.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixes this issue in the driver
--> By updating the number of arguments in the flow handler to one.
--> Use irq_desc_get_chip instead of irq_get_chip
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 20 May 2016 19:40:21 +0000 (12:40 -0700)]
staging: apf: Fixed buffer over run related to page pinning
The data structure used for storing pinned user space page
structures was a constant size. Now it is adjustable
to accommodate large transfers from malloc allocated buffers
Signed-off-by: Michael Gill <gill@xilinx.com>
Tested-by : Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 20 May 2016 19:40:05 +0000 (12:40 -0700)]
staging: apf: Enable MPSoC SG-DMA and removed clock control
This patch enables preliminary scatter-gather support for the
apf DMA driver. This extends only to memory allocated by a call
to sds_alloc, and dma_buf shared buffers. Zynq support is
unchanged. Additionally, control over clocks has been removed
due to clocks being correctly configured during petalinux
boot. There is no impact of this on a user.
Signed-off-by: Michael Gill <gill@xilinx.com>
Tested-by : Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: xilinx: Remove bitbang and register with spi core
This patch removes the bitbang layer registration.
it directly register with spi core using spi_register_master and uses
the call backs provided by spi_master struct.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Arasan controller supports AUTO CMD12, this patch adds
"SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12" quirk to enable auto cmd12
feature.
By using auto cmd12 we can also avoid following error message
"Got data interrupt even though no data operation in progress"
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
P L Sai Krishna [Thu, 26 May 2016 13:54:17 +0000 (19:24 +0530)]
mmc: Modified the SD standard speed to 19MHz.
SD standard speed timing was met only at 19MHz and
not 25 MHz, that's why changing driver to 19MHz.
The reason for this is when a level shifter is used
on the board, timing was met for standard speed only
at 19MHz. since this level shifter is commonly required
for high speed modes, the driver is modified to use
standard speed of 19Mhz. This applies only for ZynqMPSoC.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds phy.h include file from dt-bindings. This is used
for adding phandles to phy driver by high speed pheripherals like
SATA, USB, Display Port, PCIe and SGMII in their device tree nodes.
Hyun Kwon [Tue, 17 May 2016 11:18:59 +0000 (16:48 +0530)]
phy: zynqmp: Add DisplayPort custom functions to serdes driver
The DisplayPort requires programming of preemphasis / voltage swing
value at runtime. These functions will be called from DisplayPort
driver when required.
phy: zynqmp: Add phy driver for xilinx zynqmp phy core
ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed
peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can
rely on any of the four GT lanes for PHY layer. This patch adds driver
for that ZynqMP GT core.
This patch adds the document describing dt bindings for ZynqMP
PHY. ZynqMP SOC has a High Speed Processing System Gigabit
Transceiver which provides PHY capabilties to USB, SATA,
PCIE, Display Port and Ehernet SGMII controllers.
Alexander Graf [Thu, 12 May 2016 11:44:01 +0000 (13:44 +0200)]
ARM64: zynqmp: Align gic ranges for 64k in device tree
The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit 12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.
This patch makes use of that features and sets GICC and GICV to 64kb
aligned and sized regions.
Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
edac: zynqmp: Add EDAC support for ZynqMP OCM Controller
This patch adds EDAC support for ZynqMP OCM Controller, this driver
reports CE and UE errors based on interrupt, and also creates ue/ce
sysfs entires for error injection.
Also updated Kconfig and Makefile.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: ethernet: xilinx: Fix race condition for 10G MAC
In the driver napi is enabled after interrupts
are being registered. This may casue issue
if there is already data in the mac rx fifo.
If there is already data in the mac rx fifo
in the current driver flow it will trigger RX ISR
there we are disabling RX interrupts again it will
get enabled after processing the packets upto quota
in the napi poll.
But with the current driver flow napi will never be called
resulting no more rx packets being processed(As napi is enabled
at the end of the open function).
rtc: zynqmp: Update seconds time programming logic
We program RTC time using SET_TIME_WRITE register and read the RTC
current time using CURRENT_TIME register. When we set the time by
writing into SET_TIME_WRITE Register and immediately try to read the
rtc time from CURRENT_TIME register, the previous old value is
returned instead of the new loaded time. This is because RTC takes
nearly 1 sec to update the new loaded value into the CURRENT_TIME
register. This behaviour is expected in our RTC IP.
This patch updates the driver to read the current time from SET_TIME_WRITE
register instead of CURRENT_TIME when rtc time is requested within an 1sec
period after setting the RTC time. Doing so will ensure the correct time is
given to the user.
Since there is a delay of 1sec in updating the CURRENT_TIME we are loading
set time +1sec while programming the SET_TIME_WRITE register, doing this
will give correct time without any delay when read from CURRENT_TIME.
rtc: zynqmp: Write Calibration value before setting time
It is suggested to program CALIB_WRITE register with the calibration
value before updating the SET_TIME_WRITE register, doing so will
clear the Tick Counter and force the next second to be signaled
exactly in 1 second.
Michal Simek [Thu, 7 Apr 2016 09:28:12 +0000 (11:28 +0200)]
ARM: zynq: Use C pre-processor for includes in dts
Change the dtsi include code to use the C pre-processor #include instead
of the device tree /include/. This brings all ZynqMP device trees inline
with each other.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The goal is to be able to synchronize resolution changes between the
drm device and emulated fbdev device if both devices are used by an
application e.g. in Qt we use both graphics and video layer whereas
the former is controlled by fbdev and the latter by drm. This patch
propagates resolution changes from the drm device to fbdev. Before
setting the new mode, a copy of the old mode is saved locally and
restored upon last close.
work in progres:
If hot-plug events happen while the application is running, the mode
pre-application start will be restored instead of the mode set by the
last hot-plug event. For example if we switch monitors from 1080p to
4k while the application is running, last close will restore the
fbconsole to 1080p on the 4k monitor.
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Tue, 12 Apr 2016 11:32:44 +0000 (04:32 -0700)]
staging: apf: Added support for optional stock DMA driver
Previously we exclusively used our own driver internal to apf
for the DMA. This patch adds the option to instead use
the normal Xilinx DMA driver. This isn't enabled by default.
In addition to the new driver support, this patch introduces
the ability for the user program to poll for the driver
configuration, thus allowing the user program to
use the correct DMA specific code.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add logic such that the "default-input" property becomes unnecessary
for chips that only have one suitable input (ADV7611 by design, and
ADV7612 due to commit 7111cddd "[media] media: adv7604: reduce
support to first (digital) input").
Additionally, Ian's documentation in commit bf9c8227 ("[media] media:
adv7604: ability to read default input port from DT") states that
the "default-input" property should reside directly in the node
for adv7612. Hence, also adjust the parsing to make the implementation
consistent with this.
Signed-off-by: William Towle <william.towle@codethink.co.uk> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Requested-by: Chris Kohn <ckohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Tue, 12 Apr 2016 05:48:10 +0000 (22:48 -0700)]
staging: apf: Introductory MPSoC support
Code has been moved to compile under 64-bit and 32-bit.
MPSoC cache flushing now supported. Additionally, ioctl
arguments have been moved to a data-width stable
form, and correct data widths have been used throughout.
This is the first MPSoC supporting patch
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Tue, 12 Apr 2016 04:24:03 +0000 (21:24 -0700)]
staging: apf: Fixed alignment of ioctl args
Some changes to the user-space code resulted in a shift in the
alignment of several arguments in structures that are used
to communicate to the apf kernel driver via ioctl. This mirrors
those changes in the kernel code.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 8 Apr 2016 21:13:29 +0000 (14:13 -0700)]
staging: apf: Modifications to match user-space xlnk lib changes
Modified apf driver to conform to changes made in xlnk lib user-space
code. Primarily this involves changes in internal DMA naming conventions
and layout of structures used in ioctl calls.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 8 Apr 2016 21:13:22 +0000 (14:13 -0700)]
staging: apf: Made allocated buffers properly configure TLB.
dma_alloc_coherent inherently assumes certain TLB settings, that we were
then manually violating. Instead, user-space accessed DMA buffers
are allocated using kmalloc, which we can make use of more flexibly.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 8 Apr 2016 21:13:13 +0000 (14:13 -0700)]
staging: apf: Fixed an error involving invalidation
If a CPU wrote data to the cache, instructed a DMA to write
to a sub-region an incomplete cache line, then read the line back,
an incorrect data would be read. This stemmed from how the CPU
invalidated the D-Cache after the DMA finished writing. The CPU
would invalidate the entire block, assuming the DMA has written the
entire block, thus losing the data that the CPU wrote that the DMA
did not over-write. This is resolved by manually flushing the value
down, and invalidating before the DMA write is issued, instead of
invalidating after.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 8 Apr 2016 21:13:06 +0000 (14:13 -0700)]
staging: apf: Fixes to error reporting
There were several instances in which apf code could fail silently.
This patch adds descriptive messages to the kernel debug log instead of
just returning an error code. This is done to aid future debugging.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 8 Apr 2016 21:11:52 +0000 (14:11 -0700)]
staging: apf: Making regular use of constant for DMA structure sizes
Originally a constant was defined to specify sizes of structures
that track DMA state. This constant was not used, and instead
a literal integer was used when interacting with these structures as
a bound. This patch makes proper use of the defined constant, and
abandons the literal.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM64: zynqmp: Change usb node label representation
This patch changes usb node label represenation.
Our DTG is not able to recognize that usb node because
the usb node label doesn't have ip address as like other
ip nodes.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drm: xilinx: dp: Program SERDES register when training
SERDES registers should be programmed to predefined values
during link training due to the hardware issue. This patch maps
the SERDES registers directly, but the SERDES is shared between
multiple devices. This patch will be reverted once the SERDES driver,
phy-zynqmp is in place.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Read ecc log info like bankgroup number,bank and blocknumber for CE
and UE from CEADDR1 and UEADDR1 registers respectively. in previous case
we are updating wrong log info.
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The ZynqMP DDRC controller has data poisoning support
to inject CE or UE errors. this patch adds this support
using sysfs attributes.
created the following sysfs entries to support this.
-> /sys/devices/system/edac/mc/mc0/inject_data_poison
-> /sys/devices/system/edac/mc/mc0/inject_data_error
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
P L Sai Krishna [Fri, 18 Mar 2016 17:21:03 +0000 (22:51 +0530)]
spi: zynqmp: gqspi: Added separate dummy entry.
This patch sends dummy as a separate entry.
Break the Address+Cmd+dummy transfer into multiple transfers.
Address+Cmd as one transfer.
Dummy cycles as another transfer.
As per the controller spec, immediate data field of dummy entry
in the GenFifo represent dummy cycles.
Bus width for dummy cycles transfer should be same as
Rx bus width.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
P L Sai Krishna [Fri, 18 Mar 2016 17:21:02 +0000 (22:51 +0530)]
mtd: Added dummy entry in the spi_transfer structure
This patch does following things.
1. Added dummy entry in the spi_transfer structure.
2. Assigned dummy cycles to dummy member in the transfer
structure during read operation.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
With this change the zynq pl353 nand controller is not working
because the ioremap function returning the address that is not
aligned to the given size.
Still debugging why the nand transactions are failing even if the
virtual address is not aligned to given size.
So, reverting the change till the resolution is found for the above
issue.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / zynq / linux.git / log