mmc: Modified the SD standard speed to 19MHz.

SD standard speed timing was met only at 19MHz and
not 25 MHz, that's why changing driver to 19MHz.
The reason for this is when a level shifter is used
on the board, timing was met for standard speed only
at 19MHz. since this level shifter is commonly required
for high speed modes, the driver is modified to use
standard speed of 19Mhz. This applies only for ZynqMPSoC.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 4765d2a518944d84065195a9b605577feca93fe2..eee05fa8178b05726d32010a8edfd0c0dc0aba05 100644 (file)
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -29,6 +29,8 @@
 #define CLK_CTRL_TIMEOUT_SHIFT         16
 #define CLK_CTRL_TIMEOUT_MASK          (0xf << CLK_CTRL_TIMEOUT_SHIFT)
 #define CLK_CTRL_TIMEOUT_MIN_EXP       13
+#define SD_CLK_25_MHZ                          25000000
+#define SD_CLK_19_MHZ                          19000000
 
 /**
  * struct sdhci_arasan_data
@@ -81,6 +83,12 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
        if (clock > MMC_HIGH_52_MAX_DTR && (!IS_ERR(sdhci_arasan->phy)))
                ctrl_phy = true;
 
+       if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN) &&
+               (host->version >= SDHCI_SPEC_300)) {
+               if (clock == SD_CLK_25_MHZ)
+                       clock = SD_CLK_19_MHZ;
+       }
+
        if (ctrl_phy) {
                spin_unlock_irq(&host->lock);
                phy_power_off(sdhci_arasan->phy);
@@ -241,6 +249,10 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
                goto clk_disable_all;
        }
 
+       if (of_device_is_compatible(pdev->dev.of_node, "arasan,sdhci-8.9a")) {
+               host->quirks2 |= SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN;
+       }
+
        sdhci_arasan->phy = ERR_PTR(-ENODEV);
        if (of_device_is_compatible(pdev->dev.of_node,
                                    "arasan,sdhci-5.1")) {

diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 523a0f473f6525100c76513278632b395bdb8b42..3791e1ee3888c1bf26641245092b020de9b7e240 100644 (file)
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -414,6 +414,9 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN             (1<<15)
 /* Tuning Broken for HS200, SDR50 and SDR104 */
 #define SDHCI_QUIRK2_BROKEN_TUNING                     (1<<16)
+/* Broken Clock between 19MHz-25MHz */
+#define SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN          (1<<17)
+
 /*
  * When internal clock is disabled, a delay is needed before modifying the
  * SD clock frequency or enabling back the internal clock.