spi: xilinx: Add devicetree binding for spi-xilinx

Add a binding document for the spi/spi-xilinx
Sync with mainline.

Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.txt b/Documentation/devicetree/bindings/spi/spi-xilinx.txt
index 8f3aadf570b31db693daae2f743d852842ee2f8a..c7b7856bd5281aed0f4a6e5d6bd633386733f763 100644 (file)
--- a/Documentation/devicetree/bindings/spi/spi-xilinx.txt
+++ b/Documentation/devicetree/bindings/spi/spi-xilinx.txt
@@ -2,22 +2,21 @@ Xilinx SPI controller Device Tree Bindings
 -------------------------------------------------
 
 Required properties:
-- compatible           : Should be "xlnx,xps-spi-2.00.a".
-                         "xlnx,xps-spi-2.00.b" (DEPRECATED)
+- compatible           : Should be "xlnx,xps-spi-2.00.a" or "xlnx,xps-spi-2.00.b"
 - reg                  : Physical base address and size of SPI registers map.
 - interrupts           : Property with a value describing the interrupt
                          number.
 - interrupt-parent     : Must be core interrupt controller
 
 Optional properties:
-- num-cs               : Number of chip selects used.
-- xlnx,num-ss-bits     : Number of chip selects used (DEPRECATED).
+- xlnx,num-ss-bits     : Number of chip selects used.
 
 Example:
-       spi@44a00000 {
-               compatible = "xlnx,xps-spi-2.00.a";
-               interrupt-parent = <&microblaze_0_axi_intc>;
-               interrupts = <0 0>;
-               reg = <0x44a00000 0x10000>;
-               num-cs = <0x1>;
-       } ;
+       axi_quad_spi@41e00000 {
+                       compatible = "xlnx,xps-spi-2.00.a";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 31 1>;
+                       reg = <0x41e00000 0x10000>;
+                       xlnx,num-ss-bits = <0x1>;
+       };
+