v4l: xilinx: scd: Request IRQ after completing initialization
IRQs can be triggered as soon as they're requested. To ensure a valid
state in the IRQ handler, make sure to request the IRQ after
initializing all components.
v4l: xilinx: scd: Store channel registers address in iomem field
Store the channel registers address instead of the base offset in the
iomem field of the channel structures. This allows accessing the channel
registers without having to compute the offset each time.
Allocating the pads array dynamically doesn't save much memory, if at
all, due to the extra data needed to track the devm allocation, compared
to embedding an array of two pads in the xscd_device structure. Replace
the dynamic allocation.
v4l: xilinx: scd: Refactor the xscd_device structure
Reorder fields to group them by category (system resources,
configuration V4L2 channels, DMA channels), squash the xscd_shared_data
structure with xscd_device and remove duplicated fields.
v4l: xilinx: scd: Compile all SCD source files in a single module
The files xilinx-scenechange.c, xilinx-scenechange-dma.c and
xilinx-scenechange-channel.c are part of the same driver. Compile them
as a single module.
v4l: xilinx: scd: Merge the main and DMA IRQ handlers
Both the main SCD driver and the DMA support code register an IRQ
handler, for the same IRQ. This is unnecessary, we can just call the DMA
IRQ handling function from the main IRQ handler.
v4l: xilinx: scd: Cleanup the DMA engine at remove() time
The resources allocated by the xscd_dma_init() function are never
released. Add a new xscd_dma_cleanup() function to handle the cleanup
and call it at driver remove() time.
v4l: xilinx: scd: Merge the DMA support in the main SCD driver
There's no need to create a separate platform_driver and platform_device
for the DMA support. Merge the xscd_dma_device structure into the
xscd_device. This allows removing duplicating fields, as well as
unneeded code.
v4l: xilinx: scd: Merge the main and V4L2 IRQ handlers
Both the main SCD driver and the V4L2 support code register an IRQ
handler, for the same IRQ. This is unnecessary, we can just call the
V4L2 IRQ handling function from the main IRQ handler.
v4l: xilinx: scd: Merge the V4L2 support in the main SCD driver
There's no need to create a separate platform_driver and platform_device
for the V4L2 support. Call the xilinx-scenechange-channel initialization
function directly from the main driver. This allows removing duplicating
fields, as well as unneeded code.
Move all driver data structures to the xilinx-scenechange.h header. Turn
the cast macros into static inline function and rename them all to
to_<struct name> for consistency.
v4l: xilinx: vipp: Support entity matching on DT subnodes
When the video IP pipeline is parsed in DT, the composite device stores
all entities found in the graph, along with their corresponding DT node.
Later on the DT nodes pointers are used to locate the corresponding V4L2
subdevs by matching them against subdev->dev->of_node.
This mechanism works fine for devices that register a single subdev. For
devices that register multiple subdevs, subdev->dev->of_node points to
the DT node of the device, while the entities parsed from the pipeline
point to child nodes of the device DT node.
The v4l2_subdev structure has a fwnode field that is set to point to the
fwnode corresponding to the device DT node. Drivers that register
multiple subdevs must set the fwnode field manually to the associated
child node of the device DT node. We can thus fix this issue by locating
V4L2 subdevs for an entity based on the subdev fwnode instead of the
dev->of_node.
v4l: xilinx: sdirxss: Fix the media bus formats to 10bpc type
With commit id 563e888fca45a978e4c29b2f5ec5a8a95af60e68, xyavta now
fails to start stream as the media bus format requested is
MEDIA_BUS_FMT_UYVY10_1x20 but the SDI Rx subdev returned media bus
format is MEDIA_BUS_FMT_UYVY8_1x16.
Fix this by updating the driver for correct media bus formats for YUV
422 and 420 10bpc i.e. MEDIA_BUS_FMT_UYVY10_1X20 and
MEDIA_BUS_FMT_VYYUYY10_4X20.
Vishal Sagar [Fri, 29 Mar 2019 06:23:20 +0000 (23:23 -0700)]
v4l: xilinx: tpg: Dynamically modify TPG output format
The TPG output format was fixed based on the device tree. This patch now
allows the TPG output format to be configured at runtime. This is valid
only for the HLS version of TPG.
Wendy Liang [Fri, 29 Mar 2019 16:45:29 +0000 (09:45 -0700)]
dt-bindings: remoteproc: zynqmp-r5: correct dts example
* Correct ZynqMP r5 remoteproc device node example bindings to
remove the old sram, power domain nodes, and add new reserved memory
nodes.
* Fix the remoteproc device node compatible string to match the driver
* Use the mailbox to match the OpenAMP usecase
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch removes CONFIG_ZYNQMP_RESET_CONTROLLER entry from
xilinx_zynqmp_defconfig file since zynqmp reset driver will
build for ZYNQMP platform by default.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: xilinx: axiethernet: Fix crash in ifconfig down
In axidma(allow un-aligned transfers) designs, axienet_dma_q structure
tx_bufs pointer is not explicitly initialized to NULL so freeing it in
.ndo_stop may result in a kernel crash. To fix it allocate axienet_dma_q
structure memory using kzalloc. This fixes below crash in vcu118 design.
gpio: zynq: Disable the irq if it is not a wakeup source
If gpio is not set to wake disable the interrupt. ATF set all slaves with
enabled interrupts as wakeup sources and if gpio is used in r5 then it
wakes up linux.
net: can: xilinx_can: Fix FSR register handling in the rx path
After commit fc8c67368936 ("net: can: xilinx_can: Add support for
CANFD FD frames") driver is updating the FSR IRI index multiple
times(i.e in xcanfd_rx() and xcan_rx_fifo_get_next_frame()),
It should be updated once per rx packet this patch fixes this issue,
also this patch removes the unnecessary fsr register checks in
xcanfd_rx() API.
Hyun Kwon [Fri, 29 Mar 2019 05:22:00 +0000 (22:22 -0700)]
drm: xlnx: zynqmp_disp: Skip the modeset for same fb
Since the async update creates a separate atomic mode set, there can be
back to back atomic modeset with same fb. If the mode set is applied
twice, it ends up submitting 2 dma transactions, and it results in
jitter. This fixes it by adding the check in plane atomic update,
and using plane mode set in async update.
Rajan Vaja [Fri, 29 Mar 2019 05:46:49 +0000 (22:46 -0700)]
clk: zynqmp: Warn user if clock user are more than allowed
Warn user if clock is used by more than allowed devices.
This check is done by firmware and returns respective
error code. Upon receiving error code for excessive user,
warn user for the same.
This change is done to restrict VPLL use count. It is
assumed that VPLL is used by one user only.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: devices: m25p80: sync driver with mainline v4.19
This patch syncs the driver with mainline 4.19 m25p80.c.
Below is the commit from mainline 9882b53 mtd: m25p80: Use SPI_MEM_OP_NO_DUMMY instead of
SPI_MEM_OP_DUMMY(0, x)
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch move eemi_ops into priv struct zynqmp_reset_data.
Updated all the functions to get the priv struct and use the eemi_ops
structure present inside priv struct.
62f0d7d reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
reset: reset-zynqmp: Sync Reset Id macro with Mainline
Reset Start and End Macro values are updated as part of below
commit Id. bc3843d firmware: xilinx: Add reset API's
Hence updated the driver in using the start and end macro values.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
serial: uartlite: fix null dereference on probe error path
The `pdata->ulite_uart_driver` is assigned last in the probe function. So,
when un-registering the serial device on the error path this causes a
null dereference and a crash.
This fixes that by passing the initialized `ulite_uart_driver` pointer.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Thu, 28 Mar 2019 13:05:56 +0000 (06:05 -0700)]
clk: zynqmp: Fix divider calculation
Linux doesn't know maximum value of divisor that it can support.
zynqmp_clk_divider_round_rate() returns actual divider value
after calculating from parent rate and desired rate, even though
that rate is not supported by single divider of hardware. It is
also possible that such divisor value can be achieved through 2
different dividers. As, Linux tries to set such divisor value(out
of range) in single divider set divider is getting failed.
Fix the same by computing best possible combination of two
divisors which provides more accurate clock rate.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Reviewed-by: Shubhrajyoti Datta <Shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jolly Shah [Fri, 22 Mar 2019 14:21:35 +0000 (07:21 -0700)]
drivers: firmware: Add Pdi load API support
This patch adds load pdi api support to enable pdi/partial loading from
linux. Programmable Device Image (PDI) is combination of headers, images
and bitstream files to be loaded. Partial PDI is partial set of image/
images to be loaded.
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Kalyani Akula [Wed, 27 Mar 2019 07:38:11 +0000 (13:08 +0530)]
zynqmp-secure: Fix for crash seen with secure image loading
This patch resolves the crash/backtrace seen with secure load.
arch_setup_dma_ops is not setting coherent mask due to which
we see a warning (added recently in dma_mapping.h) and backtrace
along with it.
So, instead of using arch_setup_dma_ops we used of_dma_configure.
Kalyani Akula [Wed, 27 Mar 2019 07:38:09 +0000 (13:08 +0530)]
firmware: zynqmp: Modify zynqmp_pm_secure_load to return only dst.
This extra parameter added earlier to know proper error code
from the SMC, but earlier change broken backward compatibility.
So, handling the same in PMU by displaying proper error code
using PmErr.
Wolfram Sang [Thu, 28 Mar 2019 12:35:08 +0000 (18:05 +0530)]
mmc: core: use mrq->sbc when sending CMD23 for RPMB
When sending out CMD23 in the blk preparation, the comment there
rightfully says:
* However, it is not sufficient to just send CMD23,
* and avoid the final CMD12, as on an error condition
* CMD12 (stop) needs to be sent anyway. This, coupled
* with Auto-CMD23 enhancements provided by some
* hosts, means that the complexity of dealing
* with this is best left to the host. If CMD23 is
* supported by card and host, we'll fill sbc in and let
* the host deal with handling it correctly.
Let's do this behaviour for RPMB as well, and not send CMD23
independently. Otherwise IP cores (like Renesas SDHI) may timeout
because of automatic CMD23/CMD12 handling.
spi: spi-xilinx: Added workaround when startup block is enabled
In AXI SPI when the startup block is enabled in the hardware
STARTUP block don't provide clock as soon as SPI provides command,
first command fails. So to overcome this issue added a workaround
to perform a dummy Read Id if startup block is enabled in the
hardware.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Acked-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: phy: dp83867: Add support for 6-wire mode in SGMII configuration
SGMII interface is capable of working as a 4-wire or 6-wire SGMII
interface. Default is 4-wire mode. Read DT "ti,6-wire-mode" property
to program SGMIICTL1[SGMII_TYPE] 6-wire mode.
v4l: xilinx: scd: Enable 10 bit formats support for memory based IP
This patch enables 10bit format support in driver. This will configure
the 8bit or 10bit video format in IP based on media bus format set by
the application.
Harini Katakam [Sat, 23 Mar 2019 07:12:31 +0000 (12:42 +0530)]
arm64: zynqmp: Update Micrel PHY details on zc1275 and zc1285
The FMC card AES-FMC-NETW1-G is the necessary to support ethernet
on zc1275 and zc1285 boards. No previous PHYs/FMCs will be supported
on this HW. So update the phy address to 1 and necessary skew values.
Also remove PL IP related nodes and parameters that DTG generates.
Jarod Wilson [Sat, 23 Mar 2019 10:26:07 +0000 (15:56 +0530)]
net: deprecate eth_change_mtu, remove usage
With centralized MTU checking, there's nothing productive done by
eth_change_mtu that isn't already done in dev_set_mtu, so mark it as
deprecated and remove all usage of it in the kernel. All callers have been
audited for calls to alloc_etherdev* or ether_setup directly, which means
they all have a valid dev->min_mtu and dev->max_mtu. Now eth_change_mtu
prints out a netdev_warn about being deprecated, for the benefit of
out-of-tree drivers that might be utilizing it.
Of note, dvb_net.c actually had dev->mtu = 4096, while using
eth_change_mtu, meaning that if you ever tried changing it's mtu, you
couldn't set it above 1500 anymore. It's now getting dev->max_mtu also set
to 4096 to remedy that.
v2: fix up lantiq_etop, missed breakage due to drive not compiling on x86
CC: netdev@vger.kernel.org Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Philippe Reynes [Sat, 23 Mar 2019 10:26:05 +0000 (15:56 +0530)]
net: ethernet: macb: use phydev from struct net_device
The private structure contain a pointer to phydev, but the structure
net_device already contain such pointer. So we can remove the pointer
phydev in the private structure, and update the driver to use the
one contained in struct net_device.
Rebased on xilinx tree.
Signed-off-by: Philippe Reynes <tremyfr@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Harini Katakam <harini.katakam@xilix.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dmaengine: xilinx_dma: Remove axidma multichannel mode support
The AXI DMA multichannel support is deprecated in the IP and it is no
longer actively supported. For multichannel support, refer to the AXI
multichannel direct memory access IP product guide(PG228). So it is
decided to remove it's complete support from the driver. Just to
highlight that this patch intentionally breaks backward compatibility.
dt-bindings: dmaengine: xilinx_dma: Remove axidma multichannel support
The AXI DMA multichannel support is deprecated in the IP and it is no
longer actively supported. For multichannel support, refer to the AXI
multichannel direct memory access IP product guide(PG228). So it is
decided to remove it's complete support from the driver. Inline with
it remove axidma multichannel optional properties i.e xlnx,mcdma and
dma-channels from the binding description. Just to highlight that this
patch intentionally breaks backward compatibility.
There are changes between xilinx 4.19 kernel m25p80.c and mainline
4.19 kernel m25p80.c. This was happened due to merge. so update the
drver. This update includes below commits from mainline
00a5762 mtd: m25p80: Remove unneeded m25p->command field 4a3e85f mtd: devices: m25p80: Make sure the buffer passed in op is DMA-able 138f5dc mtd: m25p80: add support of SPI 1-2-2 and 1-4-4 protocols b02b17f mtd: m25p80: Call spi_mem_get_name() to let controller set a
custom name 1e07392 mtd: devices: m25p80: Use spi_mem_set_drvdata() instead of
spi_set_drvdata()
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch introduces separate media bus formats for each 10bit pixel
formats. This way v4l2 subdev applications can differentiate between
8bit and 10bit formats.
v4l: xilinx: scd: Fix video format configuration for YUV420
In the current implementation streaming based driver, the video format
value for YUV420 is programmed wrongly. This patch programs it correctly
according to PG322.
net: can: xilinx_can: fix chip_start failure with invalid bus
Currently the xilinx_can xcan_chip_start() function, called from
.ndo_open() and via CAN_MODE_START (bus-off restart), waits for the SR
register to show the wanted operating state, with a 1 sec timeout.
However, that register bit will only be set once the HW has observed 11
consecutive recessive bits (BusIdle) on the bus.
If the bus will not see the 11 bits (e.g. it is stuck dominant), the
function will timeout and return an error.
If this was done as part of a scheduled restart from bus-off, the
interface will stay in bus-off state forever even if the bus recovers
later.
If this was done during interface .ndo_open(), the interface will stay
down.
According to M_CAN and FLEXCAN documentation they also wait for 11
consecutive recessive bits, but their drivers do not seem to wait for
that.
To make the behavior consistent, modify xilinx_can to also not wait for
the synchronization to complete.
The only way for users to know for sure that the bus has been joined
successfully is to see successfully received or transmitted frames. That
does not seem optimal, but it is consistent with other drivers and we
should have a properly working restart-ms with xilinx_can.
Rename axiethernet register description to be inline with product guide
register names. It also corrects TEMAC interrupt controller offsets and
removes obsolete registers and bitmasks. There is no major functional
impact since the modified offsets are only used in ethtool get_regs and
not in any programming sequence.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Wendy Liang [Tue, 19 Mar 2019 12:01:26 +0000 (05:01 -0700)]
remoteproc: zynqmp_r5: allow kick not to pass message
Allow remoteproc kick not to write to IPI buffer. As remotperoc has
sysfs API to allow userspace to kick r5, it is possible to just raise
interrupt but not write data. Otherwise, it will take more time
to kick remoteproc, as it will need to copy the data to the IPI
buffer.
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
SPI subsystem default time out tolerance for a transfer to be complete
is 100ms. This works well on ZynqMP and Zynq platforms because on these
hardwares QSPI and SPI runs at 100MHz. But on versal emulation platform,
QSPI and SPI runs at 25MHz and core runs at 2.16MHz.
so the wait time should be increased to accommodate that clock, when
using DMA or IO. Otherwise we will get transfer time outs. Hence
increase the transfer time out tolerance.
Based on various testings this tolerance is increased from 200 to 1000.
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: rawnand: Apply nand_reset() only to TOSHIBA parts
While writing oob, flash chips like TOSHIBA will clear the whole data
page, if there is no nand_reset(). So limit this reset only to these
parts.
We can still go without checking the jedec_id, but arasan_nand driver
does not support setup_data_interface() hook to initialize the flash
timings during reset. arasan_nand driver is not supporting this hook
because the NAND subsystem is not supporting NVDDR modes. so by adding
this check we can support SDR, NVDDR modes in arasan.
And to support this jedec id check, added new jedec_id variable to
struct onfi_params. This is needed until NAND subsystem supports NVDDR
modes.
Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Fri, 22 Mar 2019 05:20:00 +0000 (10:50 +0530)]
net: macb: Add NULL check for PCLK and HCLK
Both PCLK and HCLK are "required" clocks according to macb devicetree
documentation. There is a chance that devm_clk_get doesn't return a
negative error but just a NULL clock structure instead. In such a case
the driver proceeds as usual and uses pclk value 0 to calculate MDC
divisor which is incorrect. Hence fix the same in clock initialization.
net: can: xilinx_can: Fix incorrect assignment of bittiming_const for canfd
commit 9e5f1b2 ("can: xilinx_can: add support for Xilinx CAN FD core")
had wrong assignment of bittiming_const for axi canfd, It should point to
xcan_bittiming_const_canfd structure instead of xcan_bittiming_const_can.
projects / zynq / linux.git / log