/**
* xscd_chan_configure_params - Program parameters to HW registers
* @chan: Driver specific channel struct pointer
- * @chan_offset: Register offset for a channel
*/
-static void xscd_chan_configure_params(struct xscd_chan *chan,
- u32 chan_offset)
+static void xscd_chan_configure_params(struct xscd_chan *chan)
{
u32 vid_fmt, stride;
- xscd_write(chan->iomem, XSCD_WIDTH_OFFSET + chan_offset,
- chan->format.width);
+ xscd_write(chan->iomem, XSCD_WIDTH_OFFSET, chan->format.width);
/* Stride is required only for memory based IP, not for streaming IP */
if (chan->xscd->memory_based) {
stride = roundup(chan->format.width, XSCD_BYTE_ALIGN);
- xscd_write(chan->iomem, XSCD_STRIDE_OFFSET + chan_offset,
- stride);
+ xscd_write(chan->iomem, XSCD_STRIDE_OFFSET, stride);
}
- xscd_write(chan->iomem, XSCD_HEIGHT_OFFSET + chan_offset,
- chan->format.height);
+ xscd_write(chan->iomem, XSCD_HEIGHT_OFFSET, chan->format.height);
/* Hardware video format */
vid_fmt = xscd_chan_get_vid_fmt(chan->format.code,
chan->xscd->memory_based);
- xscd_write(chan->iomem, XSCD_VID_FMT_OFFSET + chan_offset, vid_fmt);
+ xscd_write(chan->iomem, XSCD_VID_FMT_OFFSET, vid_fmt);
/*
* This is the vertical subsampling factor of the input image. Instead
* of sampling every line to calculate the histogram, IP uses this
* register value to sample only specific lines of the frame.
*/
- xscd_write(chan->iomem, XSCD_SUBSAMPLE_OFFSET + chan_offset,
- XSCD_V_SUBSAMPLING);
+ xscd_write(chan->iomem, XSCD_SUBSAMPLE_OFFSET, XSCD_V_SUBSAMPLING);
}
/* -----------------------------------------------------------------------------
{
struct xscd_chan *chan = to_xscd_chan(subdev);
unsigned long flags;
- u32 chan_offset;
/* TODO: Re-organise shared data in a better way */
chan->dmachan.en = enable;
spin_lock_irqsave(&chan->dmachan.lock, flags);
if (chan->xscd->memory_based) {
- chan_offset = chan->id * XSCD_CHAN_OFFSET;
- xscd_chan_configure_params(chan, chan_offset);
+ xscd_chan_configure_params(chan);
if (enable) {
if (!chan->xscd->active_streams) {
chan->dmachan.valid_interrupt = true;
} else {
/* Streaming based */
if (enable) {
- xscd_chan_configure_params(chan, chan->id);
+ xscd_chan_configure_params(chan);
xscd_dma_reset(&chan->dmachan);
xscd_dma_chan_enable(&chan->dmachan, BIT(chan->id));
xscd_dma_start(&chan->dmachan);
u32 *eventdata;
u32 sad, scd_threshold;
- sad = xscd_read(chan->iomem, XSCD_SAD_OFFSET +
- (chan->id * XSCD_CHAN_OFFSET));
+ sad = xscd_read(chan->iomem, XSCD_SAD_OFFSET);
sad = (sad * XSCD_V_SUBSAMPLING * MULTIPLICATION_FACTOR) /
(chan->format.width * chan->format.height);
eventdata = (u32 *)&chan->event.u.data;
mutex_init(&chan->lock);
chan->xscd = xscd;
chan->id = chan_id;
- chan->iomem = chan->xscd->iomem;
+ chan->iomem = chan->xscd->iomem + chan->id * XSCD_CHAN_OFFSET;
chan->dmachan.id = chan->id;
- chan->dmachan.iomem = chan->xscd->iomem;
+ chan->dmachan.iomem = chan->iomem;
xscd->channels[chan->id] = &chan->dmachan;
*/
void xscd_dma_chan_enable(struct xscd_dma_chan *chan, int chan_en)
{
- xscd_write(chan->iomem, XSCD_CHAN_EN_OFFSET, chan_en);
+ xscd_write(chan->xscd->iomem, XSCD_CHAN_EN_OFFSET, chan_en);
}
/**
void xscd_dma_start_transfer(struct xscd_dma_chan *chan)
{
struct xscd_dma_tx_descriptor *desc;
- u32 chanoffset = chan->id * XSCD_CHAN_OFFSET;
if (!chan->en)
return;
struct xscd_dma_tx_descriptor, node);
/* Start the transfer */
- xscd_write(chan->iomem, XSCD_ADDR_OFFSET + chanoffset,
- desc->sw.luma_plane_addr);
+ xscd_write(chan->iomem, XSCD_ADDR_OFFSET, desc->sw.luma_plane_addr);
list_del(&desc->node);
chan->staged_desc = desc;
struct xscd_device *xscd = chan->xscd;
if (xscd->memory_based)
- xscd_clr(chan->iomem, XSCD_CTRL_OFFSET, XSCD_CTRL_AP_START);
+ xscd_clr(chan->xscd->iomem, XSCD_CTRL_OFFSET,
+ XSCD_CTRL_AP_START);
else
/* Streaming based */
- xscd_clr(chan->iomem, XSCD_CTRL_OFFSET,
+ xscd_clr(chan->xscd->iomem, XSCD_CTRL_OFFSET,
XSCD_CTRL_AP_START | XSCD_CTRL_AUTO_RESTART);
chan->idle = true;
struct xscd_device *xscd = chan->xscd;
if (xscd->memory_based)
- xscd_set(chan->iomem, XSCD_CTRL_OFFSET, XSCD_CTRL_AP_START);
+ xscd_set(chan->xscd->iomem, XSCD_CTRL_OFFSET,
+ XSCD_CTRL_AP_START);
else
/* Streaming based */
- xscd_set(chan->iomem, XSCD_CTRL_OFFSET,
+ xscd_set(chan->xscd->iomem, XSCD_CTRL_OFFSET,
XSCD_CTRL_AP_START | XSCD_CTRL_AUTO_RESTART);
chan->idle = false;
*/
void xscd_dma_reset(struct xscd_dma_chan *chan)
{
- xscd_write(chan->iomem, XSCD_IE_OFFSET, XSCD_IE_AP_DONE);
- xscd_write(chan->iomem, XSCD_GIE_OFFSET, XSCD_GIE_EN);
+ xscd_write(chan->xscd->iomem, XSCD_IE_OFFSET, XSCD_IE_AP_DONE);
+ xscd_write(chan->xscd->iomem, XSCD_GIE_OFFSET, XSCD_GIE_EN);
}
/**