Vidya Sagar [Fri, 6 Jan 2017 14:52:10 +0000 (20:22 +0530)]
pcie: host: tegra: fix bus data memory permissions
this patch removes privileged mode executable permission
for bus mapping data region to avoid any un-intentional
execution happening in kernel space from this region by
using pgprot_device(PAGE_KERNEL) which internally applies
both PTE_PXN and PTE_UXN flags.
Note:- user mode executable permission is already removed
for this region
Remove code to check for valid eld which causes pcm_open to fail if
no monitor is connected. Also remove condition which earlier allowed
pcm_open to succeed if atleast pcm capabilities are known from eld.
All ISO bandwidth required by camera is reserved through the
TEGRA_ISO_CLIENT_TEGRA_CAMERA. VI client is not used by camera
software. This patch removes TEGRA_ISO_CLIENT_TEGRA_VI for t18x
and moves ISO bandwidth restriction on vi hardware to camera client.
Vidya Sagar [Fri, 10 Feb 2017 12:16:09 +0000 (17:46 +0530)]
pcie: host: tegra: fix remove/shutdown hook
PCIe platform device resources are freed if there
are no end point devices enumerated, hence, it is not
required to attempt to do it once again during shutdown
process. This patch takes care of that.
JC Kuo [Tue, 17 Jan 2017 09:26:18 +0000 (17:26 +0800)]
xhci: prevent runtime suspend when process command
When xhci driver queues a command to the controller, runtime suspend
should be avoided, otherwise, xhci driver might never see the command
completion (since controller is suspended).
This commit increases xhci controller's runtime PM usage count at the
time a new command is going to be queued, and decreases usage count
at the time receives the command completion.
Rohit Vaswani [Thu, 2 Feb 2017 02:30:54 +0000 (18:30 -0800)]
defconfig: t186: Provide configs for GPU frequency table calculations
The GPU frequency table needs the configs to provide
values that are used as inputs to calculate the
frequency table in a platform independent way.
L4T needs the minimum frequency to be 140250000 and step
size to be 7 to generate the appropriate tables.
Sumit Gupta [Mon, 23 Jan 2017 17:21:50 +0000 (22:51 +0530)]
arm64: kernel: set Debug Mask bit in disable_dbg
disable_dbg macro is unmasking Debug Exception Mask bit which will
enable debug state instead of disabling. Changing "daifclr" to
"daifset" to mask debug bit for disabling debug state. This prevents
recursive entry at the Exception level that debug exceptions are
targeted to.
Manikanta [Sat, 28 Jan 2017 12:17:52 +0000 (17:47 +0530)]
net: wireless: bcmdhd: protect platform driver probe from IFUP
Issue: Sequence of bcmdhd driver load;
- platform driver probe registers sdio client driver
- sdio client driver registers wlan0 interface
- After creating wlan0 interface, it will free resource
which includes but not limited to few structures,
turning OFF WiFi chip & switching mmc host to power save mode.
- sdio client driver returns back to platform driver probe,
which will set WiFi power state as OFF.
At same time network manager is trying bring up wlan0 interface,
which is causing multiple issues such as;
- Data abort because of freeing si_t structure memory
- mmc time out because setting mmc host in power save
- mmc time out because of mismatch in WiFi power state
Fix: Use mutex lock to protect platform driver probe from IFUP.
Pavan Kunapuli [Tue, 3 Jan 2017 12:01:28 +0000 (17:31 +0530)]
mmc: tegra: Change clock rate before enabling clock
Frequency configuration should be done before enabling clock.
T186 SDMMC4 controller is the exception to this where clock
needs to be enabled for changing frequency. Added support to
take care of this condition.
Terry Wang [Tue, 17 Jan 2017 14:12:07 +0000 (22:12 +0800)]
arm64: tegra: config: enable NVPMODEL_EMC
NVPMODEL_EMC_CAP driver add an EMC bwmgr client and
expose related cap Sysfs to user space, this make the Nvpmodel
to cap EMC BW through Sysfs possible.
The cap value is based on different Nvpmodel usecase.
Sandipan Patra [Tue, 10 Jan 2017 06:41:43 +0000 (12:11 +0530)]
camera: graph: removed extra of_node_put
of_node_put is invoked for more than of_node_get is invoked in function
tegra_vi_graph_build_one and tegra_vi_graph_build_links Because of which
last of_node_put fails saying node should be detached before removing.
Hence additional of_node_put is not needed in tegra_vi_graph_build_one and
tegra_vi_graph_build_links. Respective of_node_put is properly taken care
in of_graph_get_next_endpoint.
Erik Lilliebjerg [Sat, 31 Dec 2016 21:37:41 +0000 (14:37 -0700)]
iio: imu: nvi: Fix false error message
- Due to Invensense parts being register incompatible (even the HW ID),
there were false error messages during the driver process of identifying
the part. This patch suppresses those error messages until the part is
identified and the errors become legitimate.
Riley Andrews [Sat, 6 Jun 2015 01:59:29 +0000 (18:59 -0700)]
cpuset: Add allow_attach hook for cpusets on android.
This patch provides a allow_attach hook for cpusets,
which resolves lots of the following logcat noise.
W SchedPolicy: add_tid_to_cgroup failed to write '2816' (Permission denied); fd=29
W ActivityManager: Failed setting process group of 2816 to 0
W System.err: java.lang.IllegalArgumentException
W System.err: at android.os.Process.setProcessGroup(Native Method)
W System.err: at com.android.server.am.ActivityManagerService.applyOomAdjLocked(ActivityManagerService.java:18763)
W System.err: at com.android.server.am.ActivityManagerService.updateOomAdjLocked(ActivityManagerService.java:19028)
W System.err: at com.android.server.am.ActivityManagerService.updateOomAdjLocked(ActivityManagerService.java:19106)
W System.err: at com.android.server.am.ActiveServices.serviceDoneExecutingLocked(ActiveServices.java:2015)
W System.err: at com.android.server.am.ActiveServices.publishServiceLocked(ActiveServices.java:905)
W System.err: at com.android.server.am.ActivityManagerService.publishService(ActivityManagerService.java:16065)
W System.err: at android.app.ActivityManagerNative.onTransact(ActivityManagerNative.java:1007)
W System.err: at com.android.server.am.ActivityManagerService.onTransact(ActivityManagerService.java:2493)
W System.err: at android.os.Binder.execTransact(Binder.java:453)
This deliberately changes the behavior of the per-cpuset
cpus file to not be effected by hotplug. When a cpu is offlined,
it will be removed from the cpuset/cpus file. When a cpu is onlined,
if the cpuset originally requested that that cpu was part of the cpuset,
that cpu will be restored to the cpuset. The cpus files still
have to be hierachical, but the ranges no longer have to be out of
the currently online cpus, just the physically present cpus.
Bibek Basu [Tue, 3 Jan 2017 06:42:38 +0000 (12:12 +0530)]
arm64: config: tegra18: enable GRHOST TSEC
tsec clock is always high leading to higher vdd_core
idle power.
Reason being, TSEC driver is not enabled which brings
down the clock if not used.
Solution is to enable TSEC Driver for L4T
Ken Chang [Wed, 30 Nov 2016 06:07:14 +0000 (14:07 +0800)]
media: tegra: camera: add control for alignment
The driver needs to know alignment constraints in order to
update bytesperline and sizeimage correctly based on the
hardware requirements. Thus the values can be used to configure
VI to make streaming data written into memory buffers as expected
based on the selected pixel format. Add v4l2 controls to
make the alignment variables configurable for applications:
Ninad Malwade [Fri, 9 Dec 2016 05:24:35 +0000 (13:24 +0800)]
kernel: arm64: Add "model name" for 64bit tasks
Currently we have restriction to display processor model name under
cpuinfo structure for 32 bit tasks only and thus, ubuntu unity center
application or the /proc/cpuinfo does not display processor model name
for 64 bit tasks.
With this we are removing the restriction of displaying model name and
/proc/cpuinfo and ubuntu unity center can display the processor
information to the user for 64 bit tasks.
The parent for afi is actually mselect, not clk_m.
Change-Id: I0ec39e0d2314a62092fe8e55cfa171e3c1067c65 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1270267 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com>
drivers/base/power/domain.c:2851:12: warning: ‘pm_genpd_summary_one’ defined but not used [-Wunused-function]
static int pm_genpd_summary_one(struct seq_file *s,
^
platform: powergate: correct sclg clock names for APE
Change-Id: I7d7059b08711d2fb4a9c1d5d4656f3ef5fb35c61 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1268494 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
clk: tegra: add connection IDs for aclk and sclg_ovr clocks
Also shorten the d_audio_sclg_ovr name to fit within the 16 character conid
limit.
Change-Id: Ib8b376a6b035c192108910d45c59c8f0df3d21d6 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1268493 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Change-Id: I603953cf04d7496377ec018412f9343750a85bb7 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1268492 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Change-Id: I51ed8f2baf6ab55dce608444fb8ee85e0e0c0734 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1269545 Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com>
soc: tegra: pass DT node pointer to SoC specific parts
Some DVFS information in DT is SoC specific, so we need to parse this in the
SoC specific part of the DVFS code.
Change-Id: Id4d6fd805656a608983377aeb8714e28e5a412fa Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1269544 Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com>
Change-Id: I252cf05e07b3a3022cf81b415d0519f4fb2aaeef Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1269543 Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com>
Change-Id: Id0cc69788ff3ecd141b1ae34d1967fdf5a3375e6 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1269541 Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com>
OPPs for the GPU rail are temperature dependent. So add a new debugfs file
to dump the resulting table.
Change-Id: I05a99d041a94dd86f85eb79defc68e0e08c269a7 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1269540 Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com>
This will be used to retrigger DVFS and update the NA PLL settings on
temperature change.
Change-Id: I0204956f1c4251d698b69eba31b810c09a321f9a Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1269539 Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com>
drivers/mtd/devices/qspi_mtd.c: In function ‘qspi_probe’:
drivers/mtd/devices/qspi_mtd.c:1187:23: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 7 has type ‘uint64_t {aka long long unsigned int}’ [-Wformat=]
dev_err(&spi->dev, "%s SSErr %x %x %x %x\n", id->name,
^
In file included from drivers/mtd/devices/qspi_mtd.c:25:0:
drivers/mtd/devices/qspi_mtd.c:1192:23: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 7 has type ‘uint64_t {aka long long unsigned int}’ [-Wformat=]
dev_info(&spi->dev, "%s SSG %x %x %x %x\n", id->name,
^
merge tegra-se-pka1 in kernel-4.4 and
tegra-se-elp in t18x together to kernel-4.4
repo. Both have common code for PKA1 (applicable
for both T214 and T186) and tegra-se-elp has
extra code for RNG1 (applicable for only T186)
Deepak Nibade [Mon, 5 Dec 2016 14:22:35 +0000 (19:52 +0530)]
devfreq: don't set last_scale for same freq
In nvhost_pod_estimate_freq(), we have *freq = 0
in case we decide to keep same frequency
In that case we set *freq as current frequency and
then set last_scale timestamp
This can result in keeping same frequency for
long duration due to less delta from last_scale
To fix this, return immediately in case *freq
is zero and do not set last_scale timestamp
platform: powergate: tegra: control SATA pll sequencer input
Change-Id: I401a8a229cd4c1837d657fcc54d5e096a31baf6b Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1265131
GVS: Gerrit_Virtual_Submit Reviewed-by: Preetham Chandru <pchandru@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
This is used by the powergating driver ensure proper sequencer state when the
SATA domain is powergated.
Change-Id: I881282856282cccef857b513ce60ac9ad6becc51 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1265130 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Wenjia Zhou [Fri, 9 Dec 2016 23:29:23 +0000 (15:29 -0800)]
media:platform:tegra: Move mipical calls to fops
T210 and T186 CSI is different
Rewrite csi2_mipi_cal
Implement csi4_mipi_cal
Add fops->mipical
Modify set_stream to ensure sensor is
enabled first before csi
Remove hardcode T186 specific folder reference
in Makefile to ensure T210 compatible for k4.4
Joseph Lo [Tue, 6 Dec 2016 02:40:06 +0000 (10:40 +0800)]
i2c: tegra-vi: remove redundant I2C init code in probe and resume
We only need to init the I2C when it doesn't support powergate
function. For powergate supported platform, it has been integrated with
power up function.
clk: tegra: move tegra_dvfs_set_dfll_range to cpufreq driver
The DVFS constraints apply to cclk_g, not to dfll clock itself. Therefor
set the CPU rail to DFLL mode in the cpufreq driver as that driver knows
when we source cclk_g from the DFLL. This also prevents the call from
happening before the DVFS layer is initialized.
Change-Id: Idcea614f4cf173f6cf11424301e8299554875052 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1261578 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Change-Id: I92b484ac497306802f066bed9474f5bb0c17d077 Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1261549 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Laxman Dewangan [Thu, 8 Dec 2016 12:43:55 +0000 (18:13 +0530)]
arm: mach-tegra: Get rid of devices.h
The devices.h export all Tegra devices to get it registered
from board files. However, all Tegra platforms has moved to
DT and hence it is not required to register the devices from
DT.
Laxman Dewangan [Thu, 8 Dec 2016 09:29:24 +0000 (14:59 +0530)]
sound: soc: tegra-alt: Move mach/tegra_asoc_pdata.h to include/linux
The include header mach/tegra_asoc_pdata.h is moved to
include/linux/platform_data in order to keep all generic platform
data to this folder and get rid of mach-tegra/include/mach/*.h.
Refer the correct header location for tegra-alt drivers.
The header file tegra-board-id.h is no more used by any source
code and hence removing this header. This header contains the
board IDS which is not required any more after everything moved
to DT.
Joseph Lo [Thu, 1 Dec 2016 02:45:19 +0000 (10:45 +0800)]
soc/tegra: switch to CVB PLL table for Tegra210 CPU DVFS
Drop the static CPU freq/volt table, the table was used for when using
PLL as CPU clock source. This patch replaces it by CVB PLL table, which
will determine the DVFS table based on some calculations of the table,
speedo and voltage scale vaules.
The table is based on DVFS table version p4v64_p4Av07.
-remove macro HDMI_NODE used for chips less than T210
-remove dc_or_node_names global array and make
dc_or_node_name a member of tegra_dc_platform_data.
TDS-1305
Change-Id: I574b17aa43ac190e2d415b7b58a5f352df94bd22 Signed-off-by: Santosh Reddy Galma <galmar@nvidia.com>
Reviewed-on: http://git-master/r/1246842 Reviewed-by: Jani Uusi-Rantala <juusirantala@nvidia.com> Tested-by: Jani Uusi-Rantala <juusirantala@nvidia.com>
Laxman Dewangan [Thu, 8 Dec 2016 10:00:23 +0000 (15:30 +0530)]
arm: mach: include: Move mach/gpufuse.h to include/soc/tegra
The include header mach/mach/gpufuse.h is moved to include/soc/tegra
in order to keep all SOC specific header in include/soc/<chip>
and get rid of mach-tegra/include/mach/*.h.
The header file board_id.h is no more used by any source
code and hence removing this header. This header contains the
board IDS structure which is not required any more after
everything moved to DT.
Enabling UASP gadget protocol config which is
required to communicate with a USB Host.
Enabling below configs for kernel unification.
CONFIG_TARGET_CORE=y
CONFIG_TCM_IBLOCK=y
CONFIG_TCM_FILEIO=y
projects / hercules2020 / nv-tegra / linux-4.4.git / log