platform: powergate: correct sclg clock names for APE

Change-Id: I7d7059b08711d2fb4a9c1d5d4656f3ef5fb35c61
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1268494
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

diff --git a/drivers/platform/tegra/powergate/powergate-t21x.c b/drivers/platform/tegra/powergate/powergate-t21x.c
index e5b41f2f12658d5897c4479729209896d56a4e28..e7fc5f3b86c398c939bbc9821bade56094885885 100644 (file)
--- a/drivers/platform/tegra/powergate/powergate-t21x.c
+++ b/drivers/platform/tegra/powergate/powergate-t21x.c
@@ -430,7 +430,7 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [1] = { .clk_name = "mc_cbpa" },
                        [2] = { .clk_name = "mc_ccpa" },
                        [3] = { .clk_name = "mc_cdpa" },
-                       [4] = { .clk_name = "adsp" },
+                       [4] = { .clk_name = "aclk" },
                        [5] = { .clk_name = "i2s0" },
                        [6] = { .clk_name = "i2s1" },
                        [7] = { .clk_name = "i2s2" },
@@ -439,8 +439,8 @@ static struct powergate_partition_info tegra210_pg_partition_info[] = {
                        [10] = { .clk_name = "spdif_out" },
                        [11] = { .clk_name = "d_audio" },
                        [12] = { .clk_name = "ape_slcg_ovr" },
-                       [13] = { .clk_name = "adsp_slcg_ovr" },
-                       [14] = { .clk_name = "d_audio_slcg_ovr" },
+                       [13] = { .clk_name = "aclk_slcg_ovr" },
+                       [14] = { .clk_name = "daudio_slcg_ovr" },
 
                },
                .reset_id = { TEGRA210_CLK_APE },