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(parent: 9660a2a) | patch
platform: powergate: correct sclg clock names for APE
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Fri, 9 Dec 2016 11:29:41 +0000 (13:29 +0200)
committermobile promotions <svcmobile_promotions@nvidia.com>
Thu, 15 Dec 2016 13:45:48 +0000 (05:45 -0800)
commite93613f7d818dd58041a0b47d2f105b27179d722
treea777ecdb9af143e481d2cbf6cc3f3525460bfd89tree | snapshot
parent9660a2adea7798c48f3dee97ea8abf2976f47337commit | diff
platform: powergate: correct sclg clock names for APE

Change-Id: I7d7059b08711d2fb4a9c1d5d4656f3ef5fb35c61
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/1268494
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
drivers/platform/tegra/powergate/powergate-t21x.c diff | blob | history