]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commitdiff
can_crossbar: fixed STBY bit position in register
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Tue, 24 May 2016 11:08:06 +0000 (13:08 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Tue, 24 May 2016 11:08:06 +0000 (13:08 +0200)
system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v

index 980d4287b781e70cfb7747756deef6dcce2b2422..a50f5932fe6d4e1268098364be6e2bf8061c55d3 100644 (file)
@@ -23,8 +23,8 @@ wire [3:0] can_en;
 
 assign {can4_line, can3_line, can2_line, can1_line} = ctrl_word[7:0];
 assign {ifc4_line, ifc3_line, ifc2_line, ifc1_line} = ctrl_word[15:8];
-assign can_en = ctrl_word[20:16];
-assign can_stby = ctrl_word[21];
+assign can_en = ctrl_word[19:16];
+assign can_stby = ctrl_word[20];
 
 wire [3:0] can_line_rx;
 wire [3:0] line_rx;