]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/commit
can_crossbar: fixed STBY bit position in register
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Tue, 24 May 2016 11:08:06 +0000 (13:08 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Tue, 24 May 2016 11:08:06 +0000 (13:08 +0200)
commite9c112995b419e78c115c959cfeb29b1493687b9
treeb2f20429afc735048f11efe2a01921bd382965d0
parent94d74b77e1e11b198c4daf31bc187886a789dc5d
can_crossbar: fixed STBY bit position in register
system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v