From: Martin Jerabek <jerabma7@fel.cvut.cz>
Date: Tue, 24 May 2016 11:08:06 +0000 (+0200)
Subject: can_crossbar: fixed STBY bit position in register
X-Git-Url: https://rtime.felk.cvut.cz/gitweb/fpga/zynq/canbench-sw.git/commitdiff_plain/e9c112995b419e78c115c959cfeb29b1493687b9

can_crossbar: fixed STBY bit position in register
---

diff --git a/system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v b/system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v
index 980d428..a50f593 100644
--- a/system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v
+++ b/system/ip/can_crossbar_1.0/hdl/can_crossbar_v1_0_S00_AXI.v
@@ -23,8 +23,8 @@ wire [3:0] can_en;
 
 assign {can4_line, can3_line, can2_line, can1_line} = ctrl_word[7:0];
 assign {ifc4_line, ifc3_line, ifc2_line, ifc1_line} = ctrl_word[15:8];
-assign can_en = ctrl_word[20:16];
-assign can_stby = ctrl_word[21];
+assign can_en = ctrl_word[19:16];
+assign can_stby = ctrl_word[20];
 
 wire [3:0] can_line_rx;
 wire [3:0] line_rx;