--- /dev/null
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>user.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>display_16bit_cmd_data_bus</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WIZ_NUM_REG</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">16</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>M00_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="M00_AXI"/>
+ </spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_wready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_rready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI_RST</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI_CLK</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>M00_AXI_RST</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>M00_AXI_CLK</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>m00_axi_aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXI_CLK.ASSOCIATED_BUSIF">M00_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXI_CLK.ASSOCIATED_RESET">m00_axi_aresetn</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:addressSpaces>
+ <spirit:addressSpace>
+ <spirit:name>M00_AXI</spirit:name>
+ <spirit:range spirit:format="long" spirit:resolve="dependent" spirit:dependency="pow(2,(spirit:decode(id('MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH')) - 1) + 1)" spirit:minimum="0" spirit:maximum="4294967296" spirit:rangeType="long">4294967296</spirit:range>
+ <spirit:width spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH')) - 1) + 1">32</spirit:width>
+ </spirit:addressSpace>
+ </spirit:addressSpaces>
+ <spirit:memoryMaps>
+ <spirit:memoryMap>
+ <spirit:name>S00_AXI</spirit:name>
+ <spirit:addressBlock>
+ <spirit:name>S00_AXI_reg</spirit:name>
+ <spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
+ <spirit:range spirit:format="long">4096</spirit:range>
+ <spirit:width spirit:format="long">32</spirit:width>
+ <spirit:usage>register</spirit:usage>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+ <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+ <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:addressBlock>
+ </spirit:memoryMap>
+ </spirit:memoryMaps>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_vhdlsynthesis</spirit:name>
+ <spirit:displayName>VHDL Synthesis</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>display_16bit_cmd_data_bus_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>a45e6952</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
+ <spirit:displayName>VHDL Simulation</spirit:displayName>
+ <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>vhdl</spirit:language>
+ <spirit:modelName>display_16bit_cmd_data_bus_v1_0</spirit:modelName>
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+ <spirit:name>C_M00_AXI_START_DATA_VALUE</spirit:name>
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+ <spirit:displayName>C M00 AXI ADDR WIDTH</spirit:displayName>
+ <spirit:description>Width of M_AXI address bus.
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+ <spirit:description>Width of M_AXI data bus.
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+ <spirit:name>C_M00_AXI_START_DATA_VALUE</spirit:name>
+ <spirit:displayName>C M00 AXI START DATA VALUE</spirit:displayName>
+ <spirit:description>The master will start generating data from the C_M_START_DATA_VALUE value</spirit:description>
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+ <spirit:name>C_M00_AXI_TARGET_SLAVE_BASE_ADDR</spirit:name>
+ <spirit:displayName>C M00 AXI TARGET SLAVE BASE ADDR</spirit:displayName>
+ <spirit:description>The master requires a target slave base address.
+ -- The master will initiate read and write transactions on the slave with base address specified here as a parameter.</spirit:description>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR" spirit:order="8" spirit:bitStringLength="32">0x40000000</spirit:value>
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+ <spirit:displayName>C M00 AXI ADDR WIDTH</spirit:displayName>
+ <spirit:description>Width of M_AXI address bus.
+ -- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.</spirit:description>
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+ <spirit:displayName>C M00 AXI DATA WIDTH</spirit:displayName>
+ <spirit:description>Width of M_AXI data bus.
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+ <spirit:name>C_M00_AXI_TRANSACTIONS_NUM</spirit:name>
+ <spirit:displayName>C M00 AXI TRANSACTIONS NUM</spirit:displayName>
+ <spirit:description>Transaction number is the number of write
+ -- and read transactions the master will perform as a part of this example memory test.</spirit:description>
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+ </spirit:vendorExtensions>
+</spirit:component>
--- /dev/null
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER display_16bit_cmd_data_bus
+ OPTION supported_peripherals = (display_16bit_cmd_data_bus);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = display_16bit_cmd_data_bus;
+END DRIVER
--- /dev/null
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "display_16bit_cmd_data_bus" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}
--- /dev/null
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling display_16bit_cmd_data_bus..."
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
--- /dev/null
+
+
+/***************************** Include Files *******************************/
+#include "display_16bit_cmd_data_bus.h"
+
+/************************** Function Definitions ***************************/
--- /dev/null
+
+#ifndef DISPLAY_16BIT_CMD_DATA_BUS_H
+#define DISPLAY_16BIT_CMD_DATA_BUS_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG0_OFFSET 0
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG1_OFFSET 4
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG2_OFFSET 8
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG3_OFFSET 12
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG4_OFFSET 16
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG5_OFFSET 20
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG6_OFFSET 24
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG7_OFFSET 28
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG8_OFFSET 32
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG9_OFFSET 36
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG10_OFFSET 40
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG11_OFFSET 44
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG12_OFFSET 48
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG13_OFFSET 52
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG14_OFFSET 56
+#define DISPLAY_16BIT_CMD_DATA_BUS_S00_AXI_SLV_REG15_OFFSET 60
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a DISPLAY_16BIT_CMD_DATA_BUS register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param BaseAddress is the base address of the DISPLAY_16BIT_CMD_DATA_BUSdevice.
+ * @param RegOffset is the register offset from the base to write to.
+ * @param Data is the data written to the register.
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void DISPLAY_16BIT_CMD_DATA_BUS_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define DISPLAY_16BIT_CMD_DATA_BUS_mWriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a DISPLAY_16BIT_CMD_DATA_BUS register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param BaseAddress is the base address of the DISPLAY_16BIT_CMD_DATA_BUS device.
+ * @param RegOffset is the register offset from the base to write to.
+ *
+ * @return Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * u32 DISPLAY_16BIT_CMD_DATA_BUS_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define DISPLAY_16BIT_CMD_DATA_BUS_mReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the DISPLAY_16BIT_CMD_DATA_BUS instance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus DISPLAY_16BIT_CMD_DATA_BUS_Reg_SelfTest(void * baseaddr_p);
+
+#endif // DISPLAY_16BIT_CMD_DATA_BUS_H
--- /dev/null
+
+/***************************** Include Files *******************************/
+#include "display_16bit_cmd_data_bus.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the DISPLAY_16BIT_CMD_DATA_BUSinstance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus DISPLAY_16BIT_CMD_DATA_BUS_Reg_SelfTest(void * baseaddr_p)
+{
+ u32 baseaddr;
+ int write_loop_index;
+ int read_loop_index;
+ int Index;
+
+ baseaddr = (u32) baseaddr_p;
+
+ xil_printf("******************************\n\r");
+ xil_printf("* User Peripheral Self Test\n\r");
+ xil_printf("******************************\n\n\r");
+
+ /*
+ * Write to user logic slave module register(s) and read back
+ */
+ xil_printf("User logic slave module test...\n\r");
+
+ for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+ DISPLAY_16BIT_CMD_DATA_BUS_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+ for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+ if ( DISPLAY_16BIT_CMD_DATA_BUS_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+ xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+ return XST_FAILURE;
+ }
+
+ xil_printf(" - slave register write/read passed\n\n\r");
+
+ return XST_SUCCESS;
+}
--- /dev/null
+proc create_ipi_design { offsetfile design_name } {
+ create_bd_design $design_name
+ open_bd_design $design_name
+
+ # Create Clock and Reset Ports
+ set ACLK [ create_bd_port -dir I -type clk ACLK ]
+ set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
+ set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
+ set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
+ set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
+
+ # Create instance: display_16bit_cmd_data_bus_0, and set properties
+ set display_16bit_cmd_data_bus_0 [ create_bd_cell -type ip -vlnv user.org:user:display_16bit_cmd_data_bus:1.0 display_16bit_cmd_data_bus_0]
+
+ # Create instance: master_0, and set properties
+ set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0]
+ set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0
+
+ # Create interface connections
+ connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins display_16bit_cmd_data_bus_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins display_16bit_cmd_data_bus_0/S00_AXI_ACLK]
+ connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins display_16bit_cmd_data_bus_0/S00_AXI_ARESETN]
+
+ # Create External ports
+ set M00_AXI_INIT_AXI_TXN [ create_bd_port -dir I M00_AXI_INIT_AXI_TXN ]
+ set M00_AXI_ERROR [ create_bd_port -dir O M00_AXI_ERROR ]
+ set M00_AXI_TXN_DONE [ create_bd_port -dir O M00_AXI_TXN_DONE ]
+
+ # Create instance: slave_0, and set properties
+ set slave_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm slave_0]
+ set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} CONFIG.C_MODE_SELECT {1} CONFIG.C_S_AXI4_LITE_HIGHADDR {0x4000FFFF} CONFIG.C_S_AXI4_BASEADDR {0x40000000} CONFIG.C_S_AXI4_LITE_MEMORY_MODEL_MODE {1} ] $slave_0
+
+connect_bd_intf_net [get_bd_intf_pins slave_0/S_AXI_LITE] [get_bd_intf_pins display_16bit_cmd_data_bus_0/M00_AXI]
+ # Create port connections
+ connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins slave_0/S_AXI_LITE_ACLK] [get_bd_pins display_16bit_cmd_data_bus_0/M00_AXI_ACLK]
+ connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins slave_0/S_AXI_LITE_ARESETN] [get_bd_pins display_16bit_cmd_data_bus_0/M00_AXI_ARESETN]
+ connect_bd_net -net init_axi_txn_00 [get_bd_ports M00_AXI_INIT_AXI_TXN] [get_bd_pins display_16bit_cmd_data_bus_0/M00_AXI_INIT_AXI_TXN]
+ connect_bd_net -net error_00 [get_bd_ports M00_AXI_ERROR] [get_bd_pins display_16bit_cmd_data_bus_0/M00_AXI_ERROR]
+ connect_bd_net -net txn_done_00 [get_bd_ports M00_AXI_TXN_DONE] [get_bd_pins display_16bit_cmd_data_bus_0/M00_AXI_TXN_DONE]
+
+ # Auto assign address
+ assign_bd_address
+
+ # Copy all address to interface_address.vh file
+ set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
+ upvar 1 $offsetfile offset_file
+ set offset_file "${bd_path}/display_16bit_cmd_data_bus_v1_0_tb_include.vh"
+ set fp [open $offset_file "w"]
+ puts $fp "`ifndef display_16bit_cmd_data_bus_v1_0_tb_include_vh_"
+ puts $fp "`define display_16bit_cmd_data_bus_v1_0_tb_include_vh_\n"
+ puts $fp "//Configuration current bd names"
+ puts $fp "`define BD_INST_NAME ${design_name}_i"
+ puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
+ puts $fp "//Configuration address parameters"
+
+ set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]]
+ set offset_hex [string replace $offset 0 1 "32'h"]
+ puts $fp "`define S00_AXI_SLAVE_ADDRESS ${offset_hex}"
+
+ puts $fp "`endif"
+ close $fp
+}
+
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:display_16bit_cmd_data_bus:1.0]]]]
+set test_bench_file ${ip_path}/example_designs/bfm_design/display_16bit_cmd_data_bus_v1_0_tb.v
+set interface_address_vh_file ""
+
+# Set IP Repository and Update IP Catalogue
+set repo_paths [get_property ip_repo_paths [current_fileset]]
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+ set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+ update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+ set design_name "display_16bit_cmd_data_bus_v1_0_bfm_${i}"
+ if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+ break
+ }
+}
+
+create_ipi_design interface_address_vh_file ${design_name}
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+import_files -fileset sim_1 -norecurse -force $test_bench_file
+remove_files -quiet -fileset sim_1 display_16bit_cmd_data_bus_v1_0_tb_include.vh
+import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
+set_property top display_16bit_cmd_data_bus_v1_0_tb [get_filesets sim_1]
+set_property top_lib {} [get_filesets sim_1]
+set_property top_file {} [get_filesets sim_1]
+launch_xsim -simset sim_1 -mode behavioral
+restart
+run 1000 us
--- /dev/null
+
+`timescale 1 ns / 1 ps
+
+`include "display_16bit_cmd_data_bus_v1_0_tb_include.vh"
+
+// lite_response Type Defines
+`define RESPONSE_OKAY 2'b00
+`define RESPONSE_EXOKAY 2'b01
+`define RESP_BUS_WIDTH 2
+`define BURST_TYPE_INCR 2'b01
+`define BURST_TYPE_WRAP 2'b10
+
+// AMBA AXI4 Lite Range Constants
+`define S00_AXI_MAX_BURST_LENGTH 1
+`define S00_AXI_DATA_BUS_WIDTH 32
+`define S00_AXI_ADDRESS_BUS_WIDTH 32
+`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
+
+module display_16bit_cmd_data_bus_v1_0_tb;
+ reg tb_ACLK;
+ reg tb_ARESETn;
+
+ reg M00_AXI_INIT_AXI_TXN;
+ wire M00_AXI_TXN_DONE;
+ wire M00_AXI_ERROR;
+
+ // Create an instance of the example tb
+ `BD_WRAPPER dut (.ACLK(tb_ACLK),
+ .ARESETN(tb_ARESETn),
+ .M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
+ .M00_AXI_ERROR(M00_AXI_ERROR),
+ .M00_AXI_INIT_AXI_TXN(M00_AXI_INIT_AXI_TXN));
+
+ // Local Variables
+
+ // AMBA S00_AXI AXI4 Lite Local Reg
+ reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
+ reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
+ reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
+ reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
+ reg [3-1:0] S00_AXI_mtestProtection_lite;
+ integer S00_AXI_mtestvectorlite; // Master side testvector
+ integer S00_AXI_mtestdatasizelite;
+ integer result_slave_lite;
+
+
+ // Simple Reset Generator and test
+ initial begin
+ tb_ARESETn = 1'b0;
+ #500;
+ // Release the reset on the posedge of the clk.
+ @(posedge tb_ACLK);
+ tb_ARESETn = 1'b1;
+ @(posedge tb_ACLK);
+ end
+
+ // Simple Clock Generator
+ initial tb_ACLK = 1'b0;
+ always #10 tb_ACLK = !tb_ACLK;
+
+ //------------------------------------------------------------------------
+ // TEST LEVEL API: CHECK_RESPONSE_OKAY
+ //------------------------------------------------------------------------
+ // Description:
+ // CHECK_RESPONSE_OKAY(lite_response)
+ // This task checks if the return lite_response is equal to OKAY
+ //------------------------------------------------------------------------
+ task automatic CHECK_RESPONSE_OKAY;
+ input [`RESP_BUS_WIDTH-1:0] response;
+ begin
+ if (response !== `RESPONSE_OKAY) begin
+ $display("TESTBENCH ERROR! lite_response is not OKAY",
+ "\n expected = 0x%h",`RESPONSE_OKAY,
+ "\n actual = 0x%h",response);
+ $stop;
+ end
+ end
+ endtask
+
+ //------------------------------------------------------------------------
+ // TEST LEVEL API: COMPARE_LITE_DATA
+ //------------------------------------------------------------------------
+ // Description:
+ // COMPARE_LITE_DATA(expected,actual)
+ // This task checks if the actual data is equal to the expected data.
+ // X is used as don't care but it is not permitted for the full vector
+ // to be don't care.
+ //------------------------------------------------------------------------
+ `define S_AXI_DATA_BUS_WIDTH 32
+ task automatic COMPARE_LITE_DATA;
+ input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
+ input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
+ begin
+ if (expected === 'hx || actual === 'hx) begin
+ $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
+ result_slave_lite = 0;
+ $stop;
+ end
+
+ if (actual != expected) begin
+ $display("TESTBENCH ERROR! Data expected is not equal to actual.",
+ "\nexpected = 0x%h",expected,
+ "\nactual = 0x%h",actual);
+ result_slave_lite = 0;
+ $stop;
+ end
+ else
+ begin
+ $display("TESTBENCH Passed! Data expected is equal to actual.",
+ "\n expected = 0x%h",expected,
+ "\n actual = 0x%h",actual);
+ end
+ end
+ endtask
+
+ task automatic S00_AXI_TEST;
+ begin
+ $display("---------------------------------------------------------");
+ $display("EXAMPLE TEST : S00_AXI");
+ $display("Simple register write and read example");
+ $display("---------------------------------------------------------");
+
+ S00_AXI_mtestvectorlite = 0;
+ S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
+ S00_AXI_mtestProtection_lite = 0;
+ S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
+
+ result_slave_lite = 1;
+
+ for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
+ begin
+ dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
+ S00_AXI_mtestProtection_lite,
+ S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
+ S00_AXI_mtestdatasizelite,
+ S00_AXI_lite_response);
+ $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
+ CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
+ dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
+ S00_AXI_mtestProtection_lite,
+ S00_AXI_rd_data_lite,
+ S00_AXI_lite_response);
+ $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
+ CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
+ COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
+ $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
+ S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
+ end
+
+ $display("---------------------------------------------------------");
+ $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
+ if ( result_slave_lite ) begin
+ $display("PTGEN_TEST: PASSED!");
+ end else begin
+ $display("PTGEN_TEST: FAILED!");
+ end
+ $display("---------------------------------------------------------");
+ end
+ endtask
+
+ // Create the test vectors
+ initial begin
+ // When performing debug enable all levels of INFO messages.
+ wait(tb_ARESETn === 0) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+
+ dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
+
+ // Create test data vectors
+ S00_AXI_test_data_lite[0] = 32'h0101FFFF;
+ S00_AXI_test_data_lite[1] = 32'habcd0001;
+ S00_AXI_test_data_lite[2] = 32'hdead0011;
+ S00_AXI_test_data_lite[3] = 32'hbeef0011;
+ end
+
+ // Drive the BFM
+ initial begin
+ // Wait for end of reset
+ wait(tb_ARESETn === 0) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+
+ S00_AXI_TEST();
+
+ end
+
+ // Drive the BFM
+ initial begin
+ // Wait for end of reset
+ wait(tb_ARESETn === 0) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+
+ M00_AXI_INIT_AXI_TXN = 1'b0;
+ #500 M00_AXI_INIT_AXI_TXN = 1'b1;
+
+ $display("EXAMPLE TEST M00_AXI:");
+ wait( M00_AXI_TXN_DONE == 1'b1);
+ $display("M00_AXI: PTGEN_TEST_FINISHED!");
+ if ( M00_AXI_ERROR ) begin
+ $display("PTGEN_TEST: FAILED!");
+ end else begin
+ $display("PTGEN_TEST: PASSED!");
+ end
+
+ end
+
+endmodule
--- /dev/null
+
+proc create_ipi_design { offsetfile design_name } {
+
+ create_bd_design $design_name
+ open_bd_design $design_name
+
+ # Create and configure Clock/Reset
+ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
+ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
+
+ #check if current_board is set, if true - figure out required clocks.
+ set is_board_clock_found 0
+ set is_board_reset_found 0
+ set external_reset_port ""
+ set external_clock_port ""
+
+ if { [current_board_part -quiet] != "" } {
+
+ #check if any reset interface exists in board.
+ set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ]
+ if { $board_reset ne "" } {
+ set is_board_reset_found 1
+ apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design]
+ apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design]
+ set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]]
+ if { $external_rst ne "" } {
+ set external_reset_port [get_property NAME $external_rst]
+ }
+ } else {
+ send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually."
+ }
+
+ # check for differential clock, exclude any special clocks which has TYPE property.
+ set board_clock_busifs ""
+ foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] {
+ set type [get_property PARAM.TYPE $busif]
+ if { $type == "" } {
+ set board_clock_busifs $busif
+ break
+ }
+ }
+ if { $board_clock_busifs ne "" } {
+ apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design]
+ set is_board_clock_found 1
+ } else {
+ # check for single ended clock
+ set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ]
+ if { $board_sclock_busifs ne "" } {
+ apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design]
+ set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]]
+ if { $external_clk ne "" } {
+ set external_clock_port [get_property NAME $external_clk]
+ }
+ set is_board_clock_found 1
+ } else {
+ send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually."
+ }
+ }
+
+ } else {
+ send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually."
+ }
+
+ #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning.
+ if { $is_board_reset_found == 0 } {
+ create_bd_port -dir I -type rst reset_rtl
+ set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
+ connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
+ connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
+ set external_reset_port reset_rtl
+ }
+ if { $is_board_clock_found == 0 } {
+ create_bd_port -dir I -type clk clock_rtl
+ connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
+ set external_clock_port clock_rtl
+ }
+
+ #Avoid IPI DRC, make clock port synchronous to reset
+ if { $external_clock_port ne "" && $external_reset_port ne "" } {
+ set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
+ }
+
+ # Connect other sys_reset pins
+ connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
+
+ # Create instance: display_16bit_cmd_data_bus_0, and set properties
+ set display_16bit_cmd_data_bus_0 [ create_bd_cell -type ip -vlnv user.org:user:display_16bit_cmd_data_bus:1.0 display_16bit_cmd_data_bus_0 ]
+
+ # Create instance: jtag_axi_0, and set properties
+ set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
+ set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
+ connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ # Create instance: axi_peri_interconnect, and set properties
+ set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+ set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
+ connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
+
+ set_property -dict [ list CONFIG.NUM_MI {4} ] $axi_peri_interconnect
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M01_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M01_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M02_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M02_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M03_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M03_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ # Create instance: axi_mem_interconnect, and set properties
+ set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_mem_interconnect ]
+ connect_bd_net [get_bd_pins axi_mem_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_mem_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+ set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_mem_interconnect
+ connect_bd_net [get_bd_pins axi_mem_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_mem_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ set_property -dict [ list CONFIG.NUM_SI {2} ] $axi_mem_interconnect
+ connect_bd_net [get_bd_pins axi_mem_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_mem_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_net [get_bd_pins axi_mem_interconnect/S01_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_mem_interconnect/S01_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins axi_peri_interconnect/M01_AXI]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl axi_bram_ctrl_0 ]
+ connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ # Create instance: axi_bram_0, and set properties
+ set axi_bram_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen axi_bram_0 ]
+ set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} ] $axi_bram_0
+ connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_0/BRAM_PORTA]
+ connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_0/BRAM_PORTB]
+
+ # Create instance: axi_gpio_out, and set properties
+ set axi_gpio_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_out ]
+ set_property -dict [ list CONFIG.C_ALL_OUTPUTS {1} CONFIG.C_GPIO_WIDTH {1} ] $axi_gpio_out
+ connect_bd_net [get_bd_pins axi_gpio_out/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_gpio_out/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_intf_net [get_bd_intf_pins axi_gpio_out/S_AXI] [get_bd_intf_pins axi_peri_interconnect/M02_AXI]
+
+ # Create instance: axi_gpio_in, and set properties
+ set axi_gpio_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_in ]
+ set_property -dict [ list CONFIG.C_ALL_INPUTS {1} CONFIG.C_GPIO_WIDTH {2} ] $axi_gpio_in
+ connect_bd_net [get_bd_pins axi_gpio_in/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_gpio_in/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_intf_net [get_bd_intf_pins axi_gpio_in/S_AXI] [get_bd_intf_pins axi_peri_interconnect/M03_AXI]
+
+ # Create instance: xlconcat_0, and set properties
+ set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_0 ]
+ set_property -dict [ list CONFIG.NUM_PORTS {2} ] $xlconcat_0
+ connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins axi_gpio_in/gpio_io_i]
+
+ # Connect all clock & reset of display_16bit_cmd_data_bus_0 slave interfaces..
+ connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins display_16bit_cmd_data_bus_0/S00_AXI]
+ connect_bd_net [get_bd_pins display_16bit_cmd_data_bus_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins display_16bit_cmd_data_bus_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ # Connect all clock, reset & status pins of display_16bit_cmd_data_bus_0 master interfaces..
+ connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins display_16bit_cmd_data_bus_0/M00_AXI]
+ connect_bd_net [get_bd_pins display_16bit_cmd_data_bus_0/m00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins display_16bit_cmd_data_bus_0/m00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_net [get_bd_pins display_16bit_cmd_data_bus_0/m00_axi_txn_done] [get_bd_pins xlconcat_0/In0]
+ connect_bd_net [get_bd_pins display_16bit_cmd_data_bus_0/m00_axi_error] [get_bd_pins xlconcat_0/In1]
+ connect_bd_net [get_bd_pins display_16bit_cmd_data_bus_0/m00_axi_init_axi_txn] [ get_bd_pins axi_gpio_out/gpio_io_o ]
+
+
+ # Auto assign address
+ assign_bd_address
+
+ # Configure address param & range of display_16bit_cmd_data_bus_0 master interfaces..
+ set_property range 16K [get_bd_addr_segs {jtag_axi_0/Data/SEG_axi_bram_ctrl_0_Mem0}]
+ set_property range 16K [get_bd_addr_segs {display_16bit_cmd_data_bus_0/M00_AXI/SEG_axi_bram_ctrl_0_Mem0}]
+ set_property -dict [list CONFIG.C_M00_AXI_TARGET_SLAVE_BASE_ADDR {0xC0000000} ] [get_bd_cells display_16bit_cmd_data_bus_0]
+
+ # Copy all address to display_16bit_cmd_data_bus_v1_0_include.tcl file
+ set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+ upvar 1 $offsetfile offset_file
+ set offset_file "${bd_path}/display_16bit_cmd_data_bus_v1_0_include.tcl"
+ set fp [open $offset_file "w"]
+ puts $fp "# Configuration address parameters"
+
+ set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_gpio_in_Reg ]]
+ puts $fp "set axi_gpio_in_addr ${offset}"
+
+ set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_gpio_out_Reg ]]
+ puts $fp "set axi_gpio_out_addr ${offset}"
+
+ set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_display_16bit_cmd_data_bus_0_S00_AXI_* ]]
+ puts $fp "set s00_axi_addr ${offset}"
+
+ close $fp
+}
+
+# Set IP Repository and Update IP Catalogue
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:display_16bit_cmd_data_bus:1.0]]]]
+set hw_test_file ${ip_path}/example_designs/debug_hw_design/display_16bit_cmd_data_bus_v1_0_hw_test.tcl
+
+set repo_paths [get_property ip_repo_paths [current_fileset]]
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+ set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+ update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+ set design_name "display_16bit_cmd_data_bus_v1_0_hw_${i}"
+ if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+ break
+ }
+}
+
+set intf_address_include_file ""
+create_ipi_design intf_address_include_file ${design_name}
+save_bd_design
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+puts "-------------------------------------------------------------------------------------------------"
+puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
+puts " please perform following steps to test design in targeted board."
+puts "1. Generate bitstream"
+puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
+puts "3. Download generated bitstream"
+puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
+puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
+puts " : source -notrace ${hw_test_file}"
+puts "-------------------------------------------------------------------------------------------------"
+
--- /dev/null
+# Runtime Tcl commands to interact with - display_16bit_cmd_data_bus_v1_0
+
+# Sourcing design address info tcl
+set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+source ${bd_path}/display_16bit_cmd_data_bus_v1_0_include.tcl
+
+# jtag axi master interface hardware name, change as per your design.
+set jtag_axi_master hw_axi_1
+set ec 0
+
+# hw test script
+# Delete all previous axis transactions
+if { [llength [get_hw_axi_txns -quiet]] } {
+ delete_hw_axi_txn [get_hw_axi_txns -quiet]
+}
+
+
+# Test all lite slaves.
+set wdata_1 abcd1234
+
+# Test: S00_AXI
+# Create a write transaction at s00_axi_addr address
+create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
+# Create a read transaction at s00_axi_addr address
+create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
+# Initiate transactions
+run_hw_axi r_s00_axi_addr
+run_hw_axi w_s00_axi_addr
+run_hw_axi r_s00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
+# Compare read data
+if { $rdata_tmp == $wdata_1 } {
+ puts "Data comparison test pass for - S00_AXI"
+} else {
+ puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
+ inc ec
+}
+
+
+# Master Tests..
+# CIP Master performs write and read transaction followed by data comparison.
+# To initiate the master "init_axi_txn" port needs to be asserted high. The same assertion is done by axi_gpio_out driven by jtag_axi_lite master.
+# Writing 32'b1 to axi_gpio_out reg will initiate the first master. Subsequent masters will take following gpio bits.
+# Master 0 init_axi_txn is controlled by bit_0 of axi_gpio_out while bit_1 initiates Master 1.
+
+# To monitor the result of the data comparison by Master 0, error and done flags are being monitored by axi_gpio_in.
+# Reading bit 0 of gpio_1_reg gives the done status of the master transaction while bit 1 gives the error
+# status of the transaction initiated by the master. bit_0 being '1' means the transaction is complete
+# while bit_1 being 1 means the transaction is completed with error. The status of subsequent masters
+# will take up higher order bits in the same order. Master 1 has bit_2 as done bit, bit_3 as error bit.
+
+# Utility procs
+proc get_done_and_error_bit { rdata totmaster position } {
+ # position can be 0 1 2 3 ...
+ # Always Done is at sequence of bit 0 & error is at bit 1 position.
+ set hexdata [string range $rdata 0 7 ]
+ # In case of 64 bit data width
+ #set hexdata [string range $rdata 8 15 ]
+ binary scan [binary format H* $hexdata] B* bindata
+ set bindata [string range $bindata [expr 32 - $totmaster * 2] 31 ]
+ set DE [string range $bindata [ expr ($totmaster - ($position + 1) ) * 2 ] [expr ($totmaster - ($position + 1) ) * 2 + 1] ]
+ return $DE
+}
+
+proc bin2hex {bin} {
+ set result ""
+ set prepend [string repeat 0 [expr (4-[string length $bin]%4)%4]]
+ foreach g [regexp -all -inline {[01]{4}} $prepend$bin] {
+ foreach {b3 b2 b1 b0} [split $g ""] {
+ append result [format %X [expr {$b3*8+$b2*4+$b1*2+$b0}]]
+ }
+ }
+ return $result
+}
+
+proc get_init_data { position } {
+ # position can be 0, 1, 2, 3, 4...15
+ set initbit 00000000000000000000000000000000
+ set position [ expr 31 - $position ]
+ set newinitbit [string replace $initbit $position $position 1]
+ set hexdata [bin2hex $newinitbit]
+ return $hexdata
+}
+
+# Test: M00_AXI
+set wdata_m00_axi [get_init_data 0]
+create_hw_axi_txn w_m00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $axi_gpio_out_addr -data ${wdata_m00_axi}
+create_hw_axi_txn r_m00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $axi_gpio_in_addr
+# Initiate transactions
+run_hw_axi r_m00_axi_addr
+run_hw_axi w_m00_axi_addr
+run_hw_axi r_m00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_m00_axi_addr]]
+set DE [ get_done_and_error_bit $rdata_tmp 1 0 ]
+# Compare read data
+if { $DE == 01 } {
+ puts "Data comparison test pass for - M00_AXI"
+} else {
+ puts "Data comparison test fail for - M00_AXI, rdata-$rdata_tmp expected-01 actual-$DE"
+ inc ec
+}
+
+# Check error flag
+if { $ec == 0 } {
+ puts "PTGEN_TEST: PASSED!"
+} else {
+ puts "PTGEN_TEST: FAILED!"
+}
+
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity display_16bit_cmd_data_bus_v1_0 is
+ generic (
+ -- Users to add parameters here
+
+ -- User parameters ends
+ -- Do not modify the parameters beyond this line
+
+
+ -- Parameters of Axi Slave Bus Interface S00_AXI
+ C_S00_AXI_DATA_WIDTH : integer := 32;
+ C_S00_AXI_ADDR_WIDTH : integer := 6;
+
+ -- Parameters of Axi Master Bus Interface M00_AXI
+ C_M00_AXI_START_DATA_VALUE : std_logic_vector := x"AA000000";
+ C_M00_AXI_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
+ C_M00_AXI_ADDR_WIDTH : integer := 32;
+ C_M00_AXI_DATA_WIDTH : integer := 32;
+ C_M00_AXI_TRANSACTIONS_NUM : integer := 4
+ );
+ port (
+ -- Users to add ports here
+ lcd_res_n : out std_logic;
+ lcd_cs_n : out std_logic;
+ lcd_wr_n : out std_logic;
+ lcd_rd_n : out std_logic;
+ lcd_dc : out std_logic;
+ lcd_data : inout std_logic_vector(15 downto 0);
+
+ irq_rq_out : out std_logic;
+ -- User ports ends
+ -- Do not modify the ports beyond this line
+
+
+ -- Ports of Axi Slave Bus Interface S00_AXI
+ s00_axi_aclk : in std_logic;
+ s00_axi_aresetn : in std_logic;
+ s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+ s00_axi_awprot : in std_logic_vector(2 downto 0);
+ s00_axi_awvalid : in std_logic;
+ s00_axi_awready : out std_logic;
+ s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+ s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
+ s00_axi_wvalid : in std_logic;
+ s00_axi_wready : out std_logic;
+ s00_axi_bresp : out std_logic_vector(1 downto 0);
+ s00_axi_bvalid : out std_logic;
+ s00_axi_bready : in std_logic;
+ s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
+ s00_axi_arprot : in std_logic_vector(2 downto 0);
+ s00_axi_arvalid : in std_logic;
+ s00_axi_arready : out std_logic;
+ s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
+ s00_axi_rresp : out std_logic_vector(1 downto 0);
+ s00_axi_rvalid : out std_logic;
+ s00_axi_rready : in std_logic;
+
+ -- Ports of Axi Master Bus Interface M00_AXI
+ m00_axi_aclk : in std_logic;
+ m00_axi_aresetn : in std_logic;
+ m00_axi_awaddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
+ m00_axi_awprot : out std_logic_vector(2 downto 0);
+ m00_axi_awvalid : out std_logic;
+ m00_axi_awready : in std_logic;
+ m00_axi_wdata : out std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0);
+ m00_axi_wstrb : out std_logic_vector(C_M00_AXI_DATA_WIDTH/8-1 downto 0);
+ m00_axi_wvalid : out std_logic;
+ m00_axi_wready : in std_logic;
+ m00_axi_bresp : in std_logic_vector(1 downto 0);
+ m00_axi_bvalid : in std_logic;
+ m00_axi_bready : out std_logic;
+ m00_axi_araddr : out std_logic_vector(C_M00_AXI_ADDR_WIDTH-1 downto 0);
+ m00_axi_arprot : out std_logic_vector(2 downto 0);
+ m00_axi_arvalid : out std_logic;
+ m00_axi_arready : in std_logic;
+ m00_axi_rdata : in std_logic_vector(C_M00_AXI_DATA_WIDTH-1 downto 0);
+ m00_axi_rresp : in std_logic_vector(1 downto 0);
+ m00_axi_rvalid : in std_logic;
+ m00_axi_rready : out std_logic
+ );
+end display_16bit_cmd_data_bus_v1_0;
+
+architecture arch_imp of display_16bit_cmd_data_bus_v1_0 is
+
+ -- component declaration
+ component display_16bit_cmd_data_bus_v1_0_S00_AXI is
+ generic (
+ C_S_AXI_DATA_WIDTH : integer := 32;
+ C_S_AXI_ADDR_WIDTH : integer := 6
+ );
+ port (
+ S_AXI_ACLK : in std_logic;
+ S_AXI_ARESETN : in std_logic;
+ S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ S_AXI_AWPROT : in std_logic_vector(2 downto 0);
+ S_AXI_AWVALID : in std_logic;
+ S_AXI_AWREADY : out std_logic;
+ S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+ S_AXI_WVALID : in std_logic;
+ S_AXI_WREADY : out std_logic;
+ S_AXI_BRESP : out std_logic_vector(1 downto 0);
+ S_AXI_BVALID : out std_logic;
+ S_AXI_BREADY : in std_logic;
+ S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ S_AXI_ARPROT : in std_logic_vector(2 downto 0);
+ S_AXI_ARVALID : in std_logic;
+ S_AXI_ARREADY : out std_logic;
+ S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ S_AXI_RRESP : out std_logic_vector(1 downto 0);
+ S_AXI_RVALID : out std_logic;
+ S_AXI_RREADY : in std_logic
+ );
+ end component display_16bit_cmd_data_bus_v1_0_S00_AXI;
+
+ component display_16bit_cmd_data_bus_v1_0_M00_AXI is
+ generic (
+ C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
+ C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
+ C_M_AXI_ADDR_WIDTH : integer := 32;
+ C_M_AXI_DATA_WIDTH : integer := 32;
+ C_M_TRANSACTIONS_NUM : integer := 4
+ );
+ port (
+ INIT_AXI_TXN : in std_logic;
+ ERROR : out std_logic;
+ TXN_DONE : out std_logic;
+ M_AXI_ACLK : in std_logic;
+ M_AXI_ARESETN : in std_logic;
+ M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
+ M_AXI_AWPROT : out std_logic_vector(2 downto 0);
+ M_AXI_AWVALID : out std_logic;
+ M_AXI_AWREADY : in std_logic;
+ M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
+ M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+ M_AXI_WVALID : out std_logic;
+ M_AXI_WREADY : in std_logic;
+ M_AXI_BRESP : in std_logic_vector(1 downto 0);
+ M_AXI_BVALID : in std_logic;
+ M_AXI_BREADY : out std_logic;
+ M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
+ M_AXI_ARPROT : out std_logic_vector(2 downto 0);
+ M_AXI_ARVALID : out std_logic;
+ M_AXI_ARREADY : in std_logic;
+ M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
+ M_AXI_RRESP : in std_logic_vector(1 downto 0);
+ M_AXI_RVALID : in std_logic;
+ M_AXI_RREADY : out std_logic
+ );
+ end component display_16bit_cmd_data_bus_v1_0_M00_AXI;
+
+ signal m00_axi_init_axi_txn : std_logic;
+ signal m00_axi_error : std_logic;
+ signal m00_axi_txn_done : std_logic;
+
+begin
+
+-- Instantiation of Axi Bus Interface S00_AXI
+display_16bit_cmd_data_bus_v1_0_S00_AXI_inst : display_16bit_cmd_data_bus_v1_0_S00_AXI
+ generic map (
+ C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
+ C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
+ )
+ port map (
+ S_AXI_ACLK => s00_axi_aclk,
+ S_AXI_ARESETN => s00_axi_aresetn,
+ S_AXI_AWADDR => s00_axi_awaddr,
+ S_AXI_AWPROT => s00_axi_awprot,
+ S_AXI_AWVALID => s00_axi_awvalid,
+ S_AXI_AWREADY => s00_axi_awready,
+ S_AXI_WDATA => s00_axi_wdata,
+ S_AXI_WSTRB => s00_axi_wstrb,
+ S_AXI_WVALID => s00_axi_wvalid,
+ S_AXI_WREADY => s00_axi_wready,
+ S_AXI_BRESP => s00_axi_bresp,
+ S_AXI_BVALID => s00_axi_bvalid,
+ S_AXI_BREADY => s00_axi_bready,
+ S_AXI_ARADDR => s00_axi_araddr,
+ S_AXI_ARPROT => s00_axi_arprot,
+ S_AXI_ARVALID => s00_axi_arvalid,
+ S_AXI_ARREADY => s00_axi_arready,
+ S_AXI_RDATA => s00_axi_rdata,
+ S_AXI_RRESP => s00_axi_rresp,
+ S_AXI_RVALID => s00_axi_rvalid,
+ S_AXI_RREADY => s00_axi_rready
+ );
+
+-- Instantiation of Axi Bus Interface M00_AXI
+display_16bit_cmd_data_bus_v1_0_M00_AXI_inst : display_16bit_cmd_data_bus_v1_0_M00_AXI
+ generic map (
+ C_M_START_DATA_VALUE => C_M00_AXI_START_DATA_VALUE,
+ C_M_TARGET_SLAVE_BASE_ADDR => C_M00_AXI_TARGET_SLAVE_BASE_ADDR,
+ C_M_AXI_ADDR_WIDTH => C_M00_AXI_ADDR_WIDTH,
+ C_M_AXI_DATA_WIDTH => C_M00_AXI_DATA_WIDTH,
+ C_M_TRANSACTIONS_NUM => C_M00_AXI_TRANSACTIONS_NUM
+ )
+ port map (
+ INIT_AXI_TXN => m00_axi_init_axi_txn,
+ ERROR => m00_axi_error,
+ TXN_DONE => m00_axi_txn_done,
+ M_AXI_ACLK => m00_axi_aclk,
+ M_AXI_ARESETN => m00_axi_aresetn,
+ M_AXI_AWADDR => m00_axi_awaddr,
+ M_AXI_AWPROT => m00_axi_awprot,
+ M_AXI_AWVALID => m00_axi_awvalid,
+ M_AXI_AWREADY => m00_axi_awready,
+ M_AXI_WDATA => m00_axi_wdata,
+ M_AXI_WSTRB => m00_axi_wstrb,
+ M_AXI_WVALID => m00_axi_wvalid,
+ M_AXI_WREADY => m00_axi_wready,
+ M_AXI_BRESP => m00_axi_bresp,
+ M_AXI_BVALID => m00_axi_bvalid,
+ M_AXI_BREADY => m00_axi_bready,
+ M_AXI_ARADDR => m00_axi_araddr,
+ M_AXI_ARPROT => m00_axi_arprot,
+ M_AXI_ARVALID => m00_axi_arvalid,
+ M_AXI_ARREADY => m00_axi_arready,
+ M_AXI_RDATA => m00_axi_rdata,
+ M_AXI_RRESP => m00_axi_rresp,
+ M_AXI_RVALID => m00_axi_rvalid,
+ M_AXI_RREADY => m00_axi_rready
+ );
+
+ -- Add user logic here
+ m00_axi_init_axi_txn <= '0';
+
+ irq_rq_out <= '0';
+
+ lcd_res_n <= '1';
+ lcd_cs_n <= '1';
+ lcd_wr_n <= '1';
+ lcd_rd_n <= '1';
+ lcd_dc <= '0';
+ -- User logic ends
+
+end arch_imp;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity display_16bit_cmd_data_bus_v1_0_M00_AXI is
+ generic (
+ -- Users to add parameters here
+
+ -- User parameters ends
+ -- Do not modify the parameters beyond this line
+
+ -- The master will start generating data from the C_M_START_DATA_VALUE value
+ C_M_START_DATA_VALUE : std_logic_vector := x"AA000000";
+ -- The master requires a target slave base address.
+ -- The master will initiate read and write transactions on the slave with base address specified here as a parameter.
+ C_M_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"40000000";
+ -- Width of M_AXI address bus.
+ -- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.
+ C_M_AXI_ADDR_WIDTH : integer := 32;
+ -- Width of M_AXI data bus.
+ -- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH
+ C_M_AXI_DATA_WIDTH : integer := 32;
+ -- Transaction number is the number of write
+ -- and read transactions the master will perform as a part of this example memory test.
+ C_M_TRANSACTIONS_NUM : integer := 4
+ );
+ port (
+ -- Users to add ports here
+
+ -- User ports ends
+ -- Do not modify the ports beyond this line
+
+ -- Initiate AXI transactions
+ INIT_AXI_TXN : in std_logic;
+ -- Asserts when ERROR is detected
+ ERROR : out std_logic;
+ -- Asserts when AXI transactions is complete
+ TXN_DONE : out std_logic;
+ -- AXI clock signal
+ M_AXI_ACLK : in std_logic;
+ -- AXI active low reset signal
+ M_AXI_ARESETN : in std_logic;
+ -- Master Interface Write Address Channel ports. Write address (issued by master)
+ M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
+ -- Write channel Protection type.
+ -- This signal indicates the privilege and security level of the transaction,
+ -- and whether the transaction is a data access or an instruction access.
+ M_AXI_AWPROT : out std_logic_vector(2 downto 0);
+ -- Write address valid.
+ -- This signal indicates that the master signaling valid write address and control information.
+ M_AXI_AWVALID : out std_logic;
+ -- Write address ready.
+ -- This signal indicates that the slave is ready to accept an address and associated control signals.
+ M_AXI_AWREADY : in std_logic;
+ -- Master Interface Write Data Channel ports. Write data (issued by master)
+ M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
+ -- Write strobes.
+ -- This signal indicates which byte lanes hold valid data.
+ -- There is one write strobe bit for each eight bits of the write data bus.
+ M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
+ -- Write valid. This signal indicates that valid write data and strobes are available.
+ M_AXI_WVALID : out std_logic;
+ -- Write ready. This signal indicates that the slave can accept the write data.
+ M_AXI_WREADY : in std_logic;
+ -- Master Interface Write Response Channel ports.
+ -- This signal indicates the status of the write transaction.
+ M_AXI_BRESP : in std_logic_vector(1 downto 0);
+ -- Write response valid.
+ -- This signal indicates that the channel is signaling a valid write response
+ M_AXI_BVALID : in std_logic;
+ -- Response ready. This signal indicates that the master can accept a write response.
+ M_AXI_BREADY : out std_logic;
+ -- Master Interface Read Address Channel ports. Read address (issued by master)
+ M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
+ -- Protection type.
+ -- This signal indicates the privilege and security level of the transaction,
+ -- and whether the transaction is a data access or an instruction access.
+ M_AXI_ARPROT : out std_logic_vector(2 downto 0);
+ -- Read address valid.
+ -- This signal indicates that the channel is signaling valid read address and control information.
+ M_AXI_ARVALID : out std_logic;
+ -- Read address ready.
+ -- This signal indicates that the slave is ready to accept an address and associated control signals.
+ M_AXI_ARREADY : in std_logic;
+ -- Master Interface Read Data Channel ports. Read data (issued by slave)
+ M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
+ -- Read response. This signal indicates the status of the read transfer.
+ M_AXI_RRESP : in std_logic_vector(1 downto 0);
+ -- Read valid. This signal indicates that the channel is signaling the required read data.
+ M_AXI_RVALID : in std_logic;
+ -- Read ready. This signal indicates that the master can accept the read data and response information.
+ M_AXI_RREADY : out std_logic
+ );
+end display_16bit_cmd_data_bus_v1_0_M00_AXI;
+
+architecture implementation of display_16bit_cmd_data_bus_v1_0_M00_AXI is
+
+ -- function called clogb2 that returns an integer which has the
+ -- value of the ceiling of the log base 2
+ function clogb2 (bit_depth : integer) return integer is
+ variable depth : integer := bit_depth;
+ variable count : integer := 1;
+ begin
+ for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
+ if (bit_depth <= 2) then
+ count := 1;
+ else
+ if(depth <= 1) then
+ count := count;
+ else
+ depth := depth / 2;
+ count := count + 1;
+ end if;
+ end if;
+ end loop;
+ return(count);
+ end;
+
+ -- Example user application signals
+
+ -- TRANS_NUM_BITS is the width of the index counter for
+ -- number of write or read transaction..
+ constant TRANS_NUM_BITS : integer := clogb2(C_M_TRANSACTIONS_NUM-1);
+
+ -- Example State machine to initialize counter, initialize write transactions,
+ -- initialize read transactions and comparison of read data with the
+ -- written data words.
+ type state is ( IDLE, -- This state initiates AXI4Lite transaction
+ -- after the state machine changes state to INIT_WRITE
+ -- when there is 0 to 1 transition on INIT_AXI_TXN
+ INIT_WRITE, -- This state initializes write transaction,
+ -- once writes are done, the state machine
+ -- changes state to INIT_READ
+ INIT_READ, -- This state initializes read transaction
+ -- once reads are done, the state machine
+ -- changes state to INIT_COMPARE
+ INIT_COMPARE);-- This state issues the status of comparison
+ -- of the written data with the read data
+
+ signal mst_exec_state : state ;
+
+ -- AXI4LITE signals
+ --write address valid
+ signal axi_awvalid : std_logic;
+ --write data valid
+ signal axi_wvalid : std_logic;
+ --read address valid
+ signal axi_arvalid : std_logic;
+ --read data acceptance
+ signal axi_rready : std_logic;
+ --write response acceptance
+ signal axi_bready : std_logic;
+ --write address
+ signal axi_awaddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
+ --write data
+ signal axi_wdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
+ --read addresss
+ signal axi_araddr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
+ --Asserts when there is a write response error
+ signal write_resp_error : std_logic;
+ --Asserts when there is a read response error
+ signal read_resp_error : std_logic;
+ --A pulse to initiate a write transaction
+ signal start_single_write : std_logic;
+ --A pulse to initiate a read transaction
+ signal start_single_read : std_logic;
+ --Asserts when a single beat write transaction is issued and remains asserted till the completion of write trasaction.
+ signal write_issued : std_logic;
+ --Asserts when a single beat read transaction is issued and remains asserted till the completion of read trasaction.
+ signal read_issued : std_logic;
+ --flag that marks the completion of write trasactions. The number of write transaction is user selected by the parameter C_M_TRANSACTIONS_NUM.
+ signal writes_done : std_logic;
+ --flag that marks the completion of read trasactions. The number of read transaction is user selected by the parameter C_M_TRANSACTIONS_NUM
+ signal reads_done : std_logic;
+ --The error register is asserted when any of the write response error, read response error or the data mismatch flags are asserted.
+ signal error_reg : std_logic;
+ --index counter to track the number of write transaction issued
+ signal write_index : std_logic_vector(TRANS_NUM_BITS downto 0);
+ --index counter to track the number of read transaction issued
+ signal read_index : std_logic_vector(TRANS_NUM_BITS downto 0);
+ --Expected read data used to compare with the read data.
+ signal expected_rdata : std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
+ --Flag marks the completion of comparison of the read data with the expected read data
+ signal compare_done : std_logic;
+ --This flag is asserted when there is a mismatch of the read data with the expected read data.
+ signal read_mismatch : std_logic;
+ --Flag is asserted when the write index reaches the last write transction number
+ signal last_write : std_logic;
+ --Flag is asserted when the read index reaches the last read transction number
+ signal last_read : std_logic;
+ signal init_txn_ff : std_logic;
+ signal init_txn_ff2 : std_logic;
+ signal init_txn_edge : std_logic;
+ signal init_txn_pulse : std_logic;
+
+
+begin
+ -- I/O Connections assignments
+
+ --Adding the offset address to the base addr of the slave
+ M_AXI_AWADDR <= std_logic_vector (unsigned(C_M_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_awaddr));
+ --AXI 4 write data
+ M_AXI_WDATA <= axi_wdata;
+ M_AXI_AWPROT <= "000";
+ M_AXI_AWVALID <= axi_awvalid;
+ --Write Data(W)
+ M_AXI_WVALID <= axi_wvalid;
+ --Set all byte strobes in this example
+ M_AXI_WSTRB <= "1111";
+ --Write Response (B)
+ M_AXI_BREADY <= axi_bready;
+ --Read Address (AR)
+ M_AXI_ARADDR <= std_logic_vector(unsigned(C_M_TARGET_SLAVE_BASE_ADDR) + unsigned(axi_araddr));
+ M_AXI_ARVALID <= axi_arvalid;
+ M_AXI_ARPROT <= "001";
+ --Read and Read Response (R)
+ M_AXI_RREADY <= axi_rready;
+ --Example design I/O
+ TXN_DONE <= compare_done;
+ init_txn_pulse <= ( not init_txn_ff2) and init_txn_ff;
+
+
+ --Generate a pulse to initiate AXI transaction.
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ -- Initiates AXI transaction delay
+ if (M_AXI_ARESETN = '0' ) then
+ init_txn_ff <= '0';
+ init_txn_ff2 <= '0';
+ else
+ init_txn_ff <= INIT_AXI_TXN;
+ init_txn_ff2 <= init_txn_ff;
+ end if;
+ end if;
+ end process;
+
+
+ ----------------------
+ --Write Address Channel
+ ----------------------
+
+ -- The purpose of the write address channel is to request the address and
+ -- command information for the entire transaction. It is a single beat
+ -- of information.
+
+ -- Note for this example the axi_awvalid/axi_wvalid are asserted at the same
+ -- time, and then each is deasserted independent from each other.
+ -- This is a lower-performance, but simplier control scheme.
+
+ -- AXI VALID signals must be held active until accepted by the partner.
+
+ -- A data transfer is accepted by the slave when a master has
+ -- VALID data and the slave acknoledges it is also READY. While the master
+ -- is allowed to generated multiple, back-to-back requests by not
+ -- deasserting VALID, this design will add rest cycle for
+ -- simplicity.
+
+ -- Since only one outstanding transaction is issued by the user design,
+ -- there will not be a collision between a new request and an accepted
+ -- request on the same clock cycle.
+
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ --Only VALID signals must be deasserted during reset per AXI spec
+ --Consider inverting then registering active-low reset for higher fmax
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ axi_awvalid <= '0';
+ else
+ --Signal a new address/data command is available by user logic
+ if (start_single_write = '1') then
+ axi_awvalid <= '1';
+ elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1') then
+ --Address accepted by interconnect/slave (issue of M_AXI_AWREADY by slave)
+ axi_awvalid <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- start_single_write triggers a new write
+ -- transaction. write_index is a counter to
+ -- keep track with number of write transaction
+ -- issued/initiated
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ write_index <= (others => '0');
+ elsif (start_single_write = '1') then
+ -- Signals a new write address/ write data is
+ -- available by user logic
+ write_index <= std_logic_vector (unsigned(write_index) + 1);
+ end if;
+ end if;
+ end process;
+
+
+ ----------------------
+ --Write Data Channel
+ ----------------------
+
+ --The write data channel is for transfering the actual data.
+ --The data generation is speific to the example design, and
+ --so only the WVALID/WREADY handshake is shown here
+
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
+ axi_wvalid <= '0';
+ else
+ if (start_single_write = '1') then
+ --Signal a new address/data command is available by user logic
+ axi_wvalid <= '1';
+ elsif (M_AXI_WREADY = '1' and axi_wvalid = '1') then
+ --Data accepted by interconnect/slave (issue of M_AXI_WREADY by slave)
+ axi_wvalid <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ ------------------------------
+ --Write Response (B) Channel
+ ------------------------------
+
+ --The write response channel provides feedback that the write has committed
+ --to memory. BREADY will occur after both the data and the write address
+ --has arrived and been accepted by the slave, and can guarantee that no
+ --other accesses launched afterwards will be able to be reordered before it.
+
+ --The BRESP bit [1] is used indicate any errors from the interconnect or
+ --slave for the entire write burst. This example will capture the error.
+
+ --While not necessary per spec, it is advisable to reset READY signals in
+ --case of differing reset latencies between master/slave.
+
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ axi_bready <= '0';
+ else
+ if (M_AXI_BVALID = '1' and axi_bready = '0') then
+ -- accept/acknowledge bresp with axi_bready by the master
+ -- when M_AXI_BVALID is asserted by slave
+ axi_bready <= '1';
+ elsif (axi_bready = '1') then
+ -- deassert after one clock cycle
+ axi_bready <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+ --Flag write errors
+ write_resp_error <= (axi_bready and M_AXI_BVALID and M_AXI_BRESP(1));
+
+
+ ------------------------------
+ --Read Address Channel
+ ------------------------------
+
+ --start_single_read triggers a new read transaction. read_index is a counter to
+ --keep track with number of read transaction issued/initiated
+
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ read_index <= (others => '0');
+ else
+ if (start_single_read = '1') then
+ -- Signals a new read address is
+ -- available by user logic
+ read_index <= std_logic_vector (unsigned(read_index) + 1);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- A new axi_arvalid is asserted when there is a valid read address
+ -- available by the master. start_single_read triggers a new read
+ -- transaction
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ axi_arvalid <= '0';
+ else
+ if (start_single_read = '1') then
+ --Signal a new read address command is available by user logic
+ axi_arvalid <= '1';
+ elsif (M_AXI_ARREADY = '1' and axi_arvalid = '1') then
+ --RAddress accepted by interconnect/slave (issue of M_AXI_ARREADY by slave)
+ axi_arvalid <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ ----------------------------------
+ --Read Data (and Response) Channel
+ ----------------------------------
+
+ --The Read Data channel returns the results of the read request
+ --The master will accept the read data by asserting axi_rready
+ --when there is a valid read data available.
+ --While not necessary per spec, it is advisable to reset READY signals in
+ --case of differing reset latencies between master/slave.
+
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ axi_rready <= '1';
+ else
+ if (M_AXI_RVALID = '1' and axi_rready = '0') then
+ -- accept/acknowledge rdata/rresp with axi_rready by the master
+ -- when M_AXI_RVALID is asserted by slave
+ axi_rready <= '1';
+ elsif (axi_rready = '1') then
+ -- deassert after one clock cycle
+ axi_rready <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ --Flag write errors
+ read_resp_error <= (axi_rready and M_AXI_RVALID and M_AXI_RRESP(1));
+
+
+ ----------------------------------
+ --User Logic
+ ----------------------------------
+
+ --Address/Data Stimulus
+
+ --Address/data pairs for this example. The read and write values should
+ --match.
+ --Modify these as desired for different address patterns.
+
+ -- Write Addresses
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ axi_awaddr <= (others => '0');
+ elsif (M_AXI_AWREADY = '1' and axi_awvalid = '1') then
+ -- Signals a new write address/ write data is
+ -- available by user logic
+ axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) + 4);
+ end if;
+ end if;
+ end process;
+
+ -- Read Addresses
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
+ axi_araddr <= (others => '0');
+ elsif (M_AXI_ARREADY = '1' and axi_arvalid = '1') then
+ -- Signals a new write address/ write data is
+ -- available by user logic
+ axi_araddr <= std_logic_vector (unsigned(axi_araddr) + 4);
+ end if;
+ end if;
+ end process;
+
+ -- Write data
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ axi_wdata <= C_M_START_DATA_VALUE;
+ elsif (M_AXI_WREADY = '1' and axi_wvalid = '1') then
+ -- Signals a new write address/ write data is
+ -- available by user logic
+ axi_wdata <= std_logic_vector (unsigned(C_M_START_DATA_VALUE) + unsigned(write_index));
+ end if;
+ end if;
+ end process;
+
+
+ -- Expected read data
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1' ) then
+ expected_rdata <= C_M_START_DATA_VALUE;
+ elsif (M_AXI_RVALID = '1' and axi_rready = '1') then
+ -- Signals a new write address/ write data is
+ -- available by user logic
+ expected_rdata <= std_logic_vector (unsigned(C_M_START_DATA_VALUE) + unsigned(read_index));
+ end if;
+ end if;
+ end process;
+ --implement master command interface state machine
+ MASTER_EXECUTION_PROC:process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' ) then
+ -- reset condition
+ -- All the signals are ed default values under reset condition
+ mst_exec_state <= IDLE;
+ start_single_write <= '0';
+ write_issued <= '0';
+ start_single_read <= '0';
+ read_issued <= '0';
+ compare_done <= '0';
+ ERROR <= '0';
+ else
+ -- state transition
+ case (mst_exec_state) is
+
+ when IDLE =>
+ -- This state is responsible to initiate
+ -- AXI transaction when init_txn_pulse is asserted
+ if ( init_txn_pulse = '1') then
+ mst_exec_state <= INIT_WRITE;
+ ERROR <= '0';
+ compare_done <= '0';
+ else
+ mst_exec_state <= IDLE;
+ end if;
+
+ when INIT_WRITE =>
+ -- This state is responsible to issue start_single_write pulse to
+ -- initiate a write transaction. Write transactions will be
+ -- issued until last_write signal is asserted.
+ -- write controller
+ if (writes_done = '1') then
+ mst_exec_state <= INIT_READ;
+ else
+ mst_exec_state <= INIT_WRITE;
+
+ if (axi_awvalid = '0' and axi_wvalid = '0' and M_AXI_BVALID = '0' and
+ last_write = '0' and start_single_write = '0' and write_issued = '0') then
+ start_single_write <= '1';
+ write_issued <= '1';
+ elsif (axi_bready = '1') then
+ write_issued <= '0';
+ else
+ start_single_write <= '0'; --Negate to generate a pulse
+ end if;
+ end if;
+
+ when INIT_READ =>
+ -- This state is responsible to issue start_single_read pulse to
+ -- initiate a read transaction. Read transactions will be
+ -- issued until last_read signal is asserted.
+ -- read controller
+ if (reads_done = '1') then
+ mst_exec_state <= INIT_COMPARE;
+ else
+ mst_exec_state <= INIT_READ;
+
+ if (axi_arvalid = '0' and M_AXI_RVALID = '0' and last_read = '0' and
+ start_single_read = '0' and read_issued = '0') then
+ start_single_read <= '1';
+ read_issued <= '1';
+ elsif (axi_rready = '1') then
+ read_issued <= '0';
+ else
+ start_single_read <= '0'; --Negate to generate a pulse
+ end if;
+ end if;
+
+ when INIT_COMPARE =>
+ -- This state is responsible to issue the state of comparison
+ -- of written data with the read data. If no error flags are set,
+ -- compare_done signal will be asseted to indicate success.
+ ERROR <= error_reg;
+ mst_exec_state <= IDLE;
+ compare_done <= '1';
+
+ when others =>
+ mst_exec_state <= IDLE;
+ end case ;
+ end if;
+ end if;
+ end process;
+
+ --Terminal write count
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ -- reset condition
+ last_write <= '0';
+ else
+ --The last write should be associated with a write address ready response
+ if (write_index = STD_LOGIC_VECTOR(TO_UNSIGNED(C_M_TRANSACTIONS_NUM, TRANS_NUM_BITS+1)) and M_AXI_AWREADY = '1') then
+ last_write <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ --/*
+ -- Check for last write completion.
+ --
+ -- This logic is to qualify the last write count with the final write
+ -- response. This demonstrates how to confirm that a write has been
+ -- committed.
+ -- */
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ -- reset condition
+ writes_done <= '0';
+ else
+ if (last_write = '1' and M_AXI_BVALID = '1' and axi_bready = '1') then
+ --The writes_done should be associated with a bready response
+ writes_done <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ --------------
+ --Read example
+ --------------
+
+ --Terminal Read Count
+
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ last_read <= '0';
+ else
+ if (read_index = STD_LOGIC_VECTOR(TO_UNSIGNED(C_M_TRANSACTIONS_NUM, TRANS_NUM_BITS+1)) and (M_AXI_ARREADY = '1') ) then
+ --The last read should be associated with a read address ready response
+ last_read <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ --/*
+ -- Check for last read completion.
+ --
+ -- This logic is to qualify the last read count with the final read
+ -- response/data.
+ -- */
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ reads_done <= '0';
+ else
+ if (last_read = '1' and M_AXI_RVALID = '1' and axi_rready = '1') then
+ --The reads_done should be associated with a read ready response
+ reads_done <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ ------------------------------/
+ --Example design error register
+ ------------------------------/
+
+ --Data Comparison
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ read_mismatch <= '0';
+ else
+ if ((M_AXI_RVALID = '1' and axi_rready = '1') and M_AXI_RDATA /= expected_rdata) then
+ --The read data when available (on axi_rready) is compared with the expected data
+ read_mismatch <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Register and hold any data mismatches, or read/write interface errors
+ process(M_AXI_ACLK)
+ begin
+ if (rising_edge (M_AXI_ACLK)) then
+ if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
+ error_reg <= '0';
+ else
+ if (read_mismatch = '1' or write_resp_error = '1' or read_resp_error = '1') then
+ --Capture any error types
+ error_reg <= '1';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Add user logic here
+
+ -- User logic ends
+
+end implementation;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity display_16bit_cmd_data_bus_v1_0_S00_AXI is
+ generic (
+ -- Users to add parameters here
+
+ -- User parameters ends
+ -- Do not modify the parameters beyond this line
+
+ -- Width of S_AXI data bus
+ C_S_AXI_DATA_WIDTH : integer := 32;
+ -- Width of S_AXI address bus
+ C_S_AXI_ADDR_WIDTH : integer := 6
+ );
+ port (
+ -- Users to add ports here
+
+ -- User ports ends
+ -- Do not modify the ports beyond this line
+
+ -- Global Clock Signal
+ S_AXI_ACLK : in std_logic;
+ -- Global Reset Signal. This Signal is Active LOW
+ S_AXI_ARESETN : in std_logic;
+ -- Write address (issued by master, acceped by Slave)
+ S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ -- Write channel Protection type. This signal indicates the
+ -- privilege and security level of the transaction, and whether
+ -- the transaction is a data access or an instruction access.
+ S_AXI_AWPROT : in std_logic_vector(2 downto 0);
+ -- Write address valid. This signal indicates that the master signaling
+ -- valid write address and control information.
+ S_AXI_AWVALID : in std_logic;
+ -- Write address ready. This signal indicates that the slave is ready
+ -- to accept an address and associated control signals.
+ S_AXI_AWREADY : out std_logic;
+ -- Write data (issued by master, acceped by Slave)
+ S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ -- Write strobes. This signal indicates which byte lanes hold
+ -- valid data. There is one write strobe bit for each eight
+ -- bits of the write data bus.
+ S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
+ -- Write valid. This signal indicates that valid write
+ -- data and strobes are available.
+ S_AXI_WVALID : in std_logic;
+ -- Write ready. This signal indicates that the slave
+ -- can accept the write data.
+ S_AXI_WREADY : out std_logic;
+ -- Write response. This signal indicates the status
+ -- of the write transaction.
+ S_AXI_BRESP : out std_logic_vector(1 downto 0);
+ -- Write response valid. This signal indicates that the channel
+ -- is signaling a valid write response.
+ S_AXI_BVALID : out std_logic;
+ -- Response ready. This signal indicates that the master
+ -- can accept a write response.
+ S_AXI_BREADY : in std_logic;
+ -- Read address (issued by master, acceped by Slave)
+ S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ -- Protection type. This signal indicates the privilege
+ -- and security level of the transaction, and whether the
+ -- transaction is a data access or an instruction access.
+ S_AXI_ARPROT : in std_logic_vector(2 downto 0);
+ -- Read address valid. This signal indicates that the channel
+ -- is signaling valid read address and control information.
+ S_AXI_ARVALID : in std_logic;
+ -- Read address ready. This signal indicates that the slave is
+ -- ready to accept an address and associated control signals.
+ S_AXI_ARREADY : out std_logic;
+ -- Read data (issued by slave)
+ S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ -- Read response. This signal indicates the status of the
+ -- read transfer.
+ S_AXI_RRESP : out std_logic_vector(1 downto 0);
+ -- Read valid. This signal indicates that the channel is
+ -- signaling the required read data.
+ S_AXI_RVALID : out std_logic;
+ -- Read ready. This signal indicates that the master can
+ -- accept the read data and response information.
+ S_AXI_RREADY : in std_logic
+ );
+end display_16bit_cmd_data_bus_v1_0_S00_AXI;
+
+architecture arch_imp of display_16bit_cmd_data_bus_v1_0_S00_AXI is
+
+ -- AXI4LITE signals
+ signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ signal axi_awready : std_logic;
+ signal axi_wready : std_logic;
+ signal axi_bresp : std_logic_vector(1 downto 0);
+ signal axi_bvalid : std_logic;
+ signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
+ signal axi_arready : std_logic;
+ signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal axi_rresp : std_logic_vector(1 downto 0);
+ signal axi_rvalid : std_logic;
+
+ -- Example-specific design signals
+ -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+ -- ADDR_LSB is used for addressing 32/64 bit registers/memories
+ -- ADDR_LSB = 2 for 32 bits (n downto 2)
+ -- ADDR_LSB = 3 for 64 bits (n downto 3)
+ constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
+ constant OPT_MEM_ADDR_BITS : integer := 3;
+ ------------------------------------------------
+ ---- Signals for user logic register space example
+ --------------------------------------------------
+ ---- Number of Slave Registers 16
+ signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal slv_reg_rden : std_logic;
+ signal slv_reg_wren : std_logic;
+ signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
+ signal byte_index : integer;
+
+begin
+ -- I/O Connections assignments
+
+ S_AXI_AWREADY <= axi_awready;
+ S_AXI_WREADY <= axi_wready;
+ S_AXI_BRESP <= axi_bresp;
+ S_AXI_BVALID <= axi_bvalid;
+ S_AXI_ARREADY <= axi_arready;
+ S_AXI_RDATA <= axi_rdata;
+ S_AXI_RRESP <= axi_rresp;
+ S_AXI_RVALID <= axi_rvalid;
+ -- Implement axi_awready generation
+ -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+ -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+ -- de-asserted when reset is low.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_awready <= '0';
+ else
+ if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
+ -- slave is ready to accept write address when
+ -- there is a valid write address and write data
+ -- on the write address and data bus. This design
+ -- expects no outstanding transactions.
+ axi_awready <= '1';
+ else
+ axi_awready <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement axi_awaddr latching
+ -- This process is used to latch the address when both
+ -- S_AXI_AWVALID and S_AXI_WVALID are valid.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_awaddr <= (others => '0');
+ else
+ if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
+ -- Write Address latching
+ axi_awaddr <= S_AXI_AWADDR;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement axi_wready generation
+ -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+ -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
+ -- de-asserted when reset is low.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_wready <= '0';
+ else
+ if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
+ -- slave is ready to accept write data when
+ -- there is a valid write address and write data
+ -- on the write address and data bus. This design
+ -- expects no outstanding transactions.
+ axi_wready <= '1';
+ else
+ axi_wready <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement memory mapped register select and write logic generation
+ -- The write data is accepted and written to memory mapped registers when
+ -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+ -- select byte enables of slave registers while writing.
+ -- These registers are cleared when reset (active low) is applied.
+ -- Slave register write enable is asserted when valid address and data are available
+ -- and the slave is ready to accept the write address and write data.
+ slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
+
+ process (S_AXI_ACLK)
+ variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ slv_reg0 <= (others => '0');
+ slv_reg1 <= (others => '0');
+ slv_reg2 <= (others => '0');
+ slv_reg3 <= (others => '0');
+ slv_reg4 <= (others => '0');
+ slv_reg5 <= (others => '0');
+ slv_reg6 <= (others => '0');
+ slv_reg7 <= (others => '0');
+ slv_reg8 <= (others => '0');
+ slv_reg9 <= (others => '0');
+ slv_reg10 <= (others => '0');
+ slv_reg11 <= (others => '0');
+ slv_reg12 <= (others => '0');
+ slv_reg13 <= (others => '0');
+ slv_reg14 <= (others => '0');
+ slv_reg15 <= (others => '0');
+ else
+ loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+ if (slv_reg_wren = '1') then
+ case loc_addr is
+ when b"0000" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 0
+ slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0001" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 1
+ slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0010" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 2
+ slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0011" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 3
+ slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0100" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 4
+ slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0101" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 5
+ slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0110" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 6
+ slv_reg6(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"0111" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 7
+ slv_reg7(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1000" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 8
+ slv_reg8(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1001" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 9
+ slv_reg9(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1010" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 10
+ slv_reg10(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1011" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 11
+ slv_reg11(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1100" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 12
+ slv_reg12(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1101" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 13
+ slv_reg13(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1110" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 14
+ slv_reg14(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when b"1111" =>
+ for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
+ if ( S_AXI_WSTRB(byte_index) = '1' ) then
+ -- Respective byte enables are asserted as per write strobes
+ -- slave registor 15
+ slv_reg15(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
+ end if;
+ end loop;
+ when others =>
+ slv_reg0 <= slv_reg0;
+ slv_reg1 <= slv_reg1;
+ slv_reg2 <= slv_reg2;
+ slv_reg3 <= slv_reg3;
+ slv_reg4 <= slv_reg4;
+ slv_reg5 <= slv_reg5;
+ slv_reg6 <= slv_reg6;
+ slv_reg7 <= slv_reg7;
+ slv_reg8 <= slv_reg8;
+ slv_reg9 <= slv_reg9;
+ slv_reg10 <= slv_reg10;
+ slv_reg11 <= slv_reg11;
+ slv_reg12 <= slv_reg12;
+ slv_reg13 <= slv_reg13;
+ slv_reg14 <= slv_reg14;
+ slv_reg15 <= slv_reg15;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement write response logic generation
+ -- The write response and response valid signals are asserted by the slave
+ -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
+ -- This marks the acceptance of address and indicates the status of
+ -- write transaction.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_bvalid <= '0';
+ axi_bresp <= "00"; --need to work more on the responses
+ else
+ if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
+ axi_bvalid <= '1';
+ axi_bresp <= "00";
+ elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
+ axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement axi_arready generation
+ -- axi_arready is asserted for one S_AXI_ACLK clock cycle when
+ -- S_AXI_ARVALID is asserted. axi_awready is
+ -- de-asserted when reset (active low) is asserted.
+ -- The read address is also latched when S_AXI_ARVALID is
+ -- asserted. axi_araddr is reset to zero on reset assertion.
+
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_arready <= '0';
+ axi_araddr <= (others => '1');
+ else
+ if (axi_arready = '0' and S_AXI_ARVALID = '1') then
+ -- indicates that the slave has acceped the valid read address
+ axi_arready <= '1';
+ -- Read Address latching
+ axi_araddr <= S_AXI_ARADDR;
+ else
+ axi_arready <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement axi_arvalid generation
+ -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
+ -- S_AXI_ARVALID and axi_arready are asserted. The slave registers
+ -- data are available on the axi_rdata bus at this instance. The
+ -- assertion of axi_rvalid marks the validity of read data on the
+ -- bus and axi_rresp indicates the status of read transaction.axi_rvalid
+ -- is deasserted on reset (active low). axi_rresp and axi_rdata are
+ -- cleared to zero on reset (active low).
+ process (S_AXI_ACLK)
+ begin
+ if rising_edge(S_AXI_ACLK) then
+ if S_AXI_ARESETN = '0' then
+ axi_rvalid <= '0';
+ axi_rresp <= "00";
+ else
+ if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
+ -- Valid read data is available at the read data bus
+ axi_rvalid <= '1';
+ axi_rresp <= "00"; -- 'OKAY' response
+ elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
+ -- Read data is accepted by the master
+ axi_rvalid <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ -- Implement memory mapped register select and read logic generation
+ -- Slave register read enable is asserted when valid address is available
+ -- and the slave is ready to accept the read address.
+ slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
+
+ process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
+ variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
+ begin
+ -- Address decoding for reading registers
+ loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
+ case loc_addr is
+ when b"0000" =>
+ reg_data_out <= slv_reg0;
+ when b"0001" =>
+ reg_data_out <= slv_reg1;
+ when b"0010" =>
+ reg_data_out <= slv_reg2;
+ when b"0011" =>
+ reg_data_out <= slv_reg3;
+ when b"0100" =>
+ reg_data_out <= slv_reg4;
+ when b"0101" =>
+ reg_data_out <= slv_reg5;
+ when b"0110" =>
+ reg_data_out <= slv_reg6;
+ when b"0111" =>
+ reg_data_out <= slv_reg7;
+ when b"1000" =>
+ reg_data_out <= slv_reg8;
+ when b"1001" =>
+ reg_data_out <= slv_reg9;
+ when b"1010" =>
+ reg_data_out <= slv_reg10;
+ when b"1011" =>
+ reg_data_out <= slv_reg11;
+ when b"1100" =>
+ reg_data_out <= slv_reg12;
+ when b"1101" =>
+ reg_data_out <= slv_reg13;
+ when b"1110" =>
+ reg_data_out <= slv_reg14;
+ when b"1111" =>
+ reg_data_out <= slv_reg15;
+ when others =>
+ reg_data_out <= (others => '0');
+ end case;
+ end process;
+
+ -- Output register or memory read data
+ process( S_AXI_ACLK ) is
+ begin
+ if (rising_edge (S_AXI_ACLK)) then
+ if ( S_AXI_ARESETN = '0' ) then
+ axi_rdata <= (others => '0');
+ else
+ if (slv_reg_rden = '1') then
+ -- When there is a valid read address (S_AXI_ARVALID) with
+ -- acceptance of read address by the slave (axi_arready),
+ -- output the read dada
+ -- Read address mux
+ axi_rdata <= reg_data_out; -- register read data
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ -- Add user logic here
+
+ -- User logic ends
+
+end arch_imp;
--- /dev/null
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+ set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+ set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+ set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+ ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+ set C_M00_AXI_START_DATA_VALUE [ipgui::add_param $IPINST -name "C_M00_AXI_START_DATA_VALUE" -parent ${Page_0}]
+ set_property tooltip {The master will start generating data from the C_M_START_DATA_VALUE value} ${C_M00_AXI_START_DATA_VALUE}
+ set C_M00_AXI_TARGET_SLAVE_BASE_ADDR [ipgui::add_param $IPINST -name "C_M00_AXI_TARGET_SLAVE_BASE_ADDR" -parent ${Page_0}]
+ set_property tooltip {The master requires a target slave base address.
+ -- The master will initiate read and write transactions on the slave with base address specified here as a parameter.} ${C_M00_AXI_TARGET_SLAVE_BASE_ADDR}
+ set C_M00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_M00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+ set_property tooltip {Width of M_AXI address bus.
+ -- The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH.} ${C_M00_AXI_ADDR_WIDTH}
+ set C_M00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_M00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+ set_property tooltip {Width of M_AXI data bus.
+ -- The master issues write data and accept read data where the width of the data bus is C_M_AXI_DATA_WIDTH} ${C_M00_AXI_DATA_WIDTH}
+ set C_M00_AXI_TRANSACTIONS_NUM [ipgui::add_param $IPINST -name "C_M00_AXI_TRANSACTIONS_NUM" -parent ${Page_0}]
+ set_property tooltip {Transaction number is the number of write
+ -- and read transactions the master will perform as a part of this example memory test.} ${C_M00_AXI_TRANSACTIONS_NUM}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_S00_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_S00_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+ # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+ # Procedure called to validate C_S00_AXI_BASEADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+ # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+ # Procedure called to validate C_S00_AXI_HIGHADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_START_DATA_VALUE { PARAM_VALUE.C_M00_AXI_START_DATA_VALUE } {
+ # Procedure called to update C_M00_AXI_START_DATA_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_START_DATA_VALUE { PARAM_VALUE.C_M00_AXI_START_DATA_VALUE } {
+ # Procedure called to validate C_M00_AXI_START_DATA_VALUE
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to update C_M00_AXI_TARGET_SLAVE_BASE_ADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to validate C_M00_AXI_TARGET_SLAVE_BASE_ADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_M00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_ADDR_WIDTH { PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_M00_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to update C_M00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_DATA_WIDTH { PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_M00_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM { PARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM } {
+ # Procedure called to update C_M00_AXI_TRANSACTIONS_NUM when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM { PARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM } {
+ # Procedure called to validate C_M00_AXI_TRANSACTIONS_NUM
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_START_DATA_VALUE { MODELPARAM_VALUE.C_M00_AXI_START_DATA_VALUE PARAM_VALUE.C_M00_AXI_START_DATA_VALUE } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_START_DATA_VALUE}] ${MODELPARAM_VALUE.C_M00_AXI_START_DATA_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR { MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}] ${MODELPARAM_VALUE.C_M00_AXI_TARGET_SLAVE_BASE_ADDR}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH PARAM_VALUE.C_M00_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH PARAM_VALUE.C_M00_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM { MODELPARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM PARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM}] ${MODELPARAM_VALUE.C_M00_AXI_TRANSACTIONS_NUM}
+}
+
projects / fpga / zynq / canbench-sw.git / commitdiff