system/ip/display_16bit_cmd_data_bus_1.0/example_designs/bfm_design/display_16bit_cmd_data_bus_v1_0_tb.v

   1
   2 `timescale 1 ns / 1 ps
   3
   4 `include "display_16bit_cmd_data_bus_v1_0_tb_include.vh"
   5
   6 // lite_response Type Defines
   7 `define RESPONSE_OKAY 2'b00
   8 `define RESPONSE_EXOKAY 2'b01
   9 `define RESP_BUS_WIDTH 2
  10 `define BURST_TYPE_INCR  2'b01
  11 `define BURST_TYPE_WRAP  2'b10
  12
  13 // AMBA AXI4 Lite Range Constants
  14 `define S00_AXI_MAX_BURST_LENGTH 1
  15 `define S00_AXI_DATA_BUS_WIDTH 32
  16 `define S00_AXI_ADDRESS_BUS_WIDTH 32
  17 `define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
  18
  19 module display_16bit_cmd_data_bus_v1_0_tb;
  20         reg tb_ACLK;
  21         reg tb_ARESETn;
  22
  23         reg M00_AXI_INIT_AXI_TXN;
  24         wire M00_AXI_TXN_DONE;
  25         wire M00_AXI_ERROR;
  26
  27         // Create an instance of the example tb
  28         `BD_WRAPPER dut (.ACLK(tb_ACLK),
  29                                 .ARESETN(tb_ARESETn),
  30                                 .M00_AXI_TXN_DONE(M00_AXI_TXN_DONE),
  31                                 .M00_AXI_ERROR(M00_AXI_ERROR),
  32                                 .M00_AXI_INIT_AXI_TXN(M00_AXI_INIT_AXI_TXN));
  33
  34         // Local Variables
  35
  36         // AMBA S00_AXI AXI4 Lite Local Reg
  37         reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
  38         reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
  39         reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
  40         reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
  41         reg [3-1:0]   S00_AXI_mtestProtection_lite;
  42         integer S00_AXI_mtestvectorlite; // Master side testvector
  43         integer S00_AXI_mtestdatasizelite;
  44         integer result_slave_lite;
  45
  46
  47         // Simple Reset Generator and test
  48         initial begin
  49                 tb_ARESETn = 1'b0;
  50           #500;
  51                 // Release the reset on the posedge of the clk.
  52                 @(posedge tb_ACLK);
  53           tb_ARESETn = 1'b1;
  54                 @(posedge tb_ACLK);
  55         end
  56
  57         // Simple Clock Generator
  58         initial tb_ACLK = 1'b0;
  59         always #10 tb_ACLK = !tb_ACLK;
  60
  61         //------------------------------------------------------------------------
  62         // TEST LEVEL API: CHECK_RESPONSE_OKAY
  63         //------------------------------------------------------------------------
  64         // Description:
  65         // CHECK_RESPONSE_OKAY(lite_response)
  66         // This task checks if the return lite_response is equal to OKAY
  67         //------------------------------------------------------------------------
  68         task automatic CHECK_RESPONSE_OKAY;
  69                 input [`RESP_BUS_WIDTH-1:0] response;
  70                 begin
  71                   if (response !== `RESPONSE_OKAY) begin
  72                           $display("TESTBENCH ERROR! lite_response is not OKAY",
  73                                          "\n expected = 0x%h",`RESPONSE_OKAY,
  74                                          "\n actual   = 0x%h",response);
  75                     $stop;
  76                   end
  77                 end
  78         endtask
  79
  80         //------------------------------------------------------------------------
  81         // TEST LEVEL API: COMPARE_LITE_DATA
  82         //------------------------------------------------------------------------
  83         // Description:
  84         // COMPARE_LITE_DATA(expected,actual)
  85         // This task checks if the actual data is equal to the expected data.
  86         // X is used as don't care but it is not permitted for the full vector
  87         // to be don't care.
  88         //------------------------------------------------------------------------
  89         `define S_AXI_DATA_BUS_WIDTH 32
  90         task automatic COMPARE_LITE_DATA;
  91                 input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
  92                 input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
  93                 begin
  94                         if (expected === 'hx || actual === 'hx) begin
  95                                 $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
  96                     result_slave_lite = 0;
  97                     $stop;
  98                   end
  99
 100                         if (actual != expected) begin
 101                                 $display("TESTBENCH ERROR! Data expected is not equal to actual.",
 102                                          "\nexpected = 0x%h",expected,
 103                                          "\nactual   = 0x%h",actual);
 104                     result_slave_lite = 0;
 105                     $stop;
 106                   end
 107                         else
 108                         begin
 109                            $display("TESTBENCH Passed! Data expected is equal to actual.",
 110                                     "\n expected = 0x%h",expected,
 111                                     "\n actual   = 0x%h",actual);
 112                         end
 113                 end
 114         endtask
 115
 116         task automatic S00_AXI_TEST;
 117                 begin
 118                         $display("---------------------------------------------------------");
 119                         $display("EXAMPLE TEST : S00_AXI");
 120                         $display("Simple register write and read example");
 121                         $display("---------------------------------------------------------");
 122
 123                         S00_AXI_mtestvectorlite = 0;
 124                         S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
 125                         S00_AXI_mtestProtection_lite = 0;
 126                         S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
 127
 128                          result_slave_lite = 1;
 129
 130                         for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
 131                         begin
 132                           dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
 133                                                      S00_AXI_mtestProtection_lite,
 134                                                      S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
 135                                                      S00_AXI_mtestdatasizelite,
 136                                                      S00_AXI_lite_response);
 137                           $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
 138                           CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
 139                           dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
 140                                                      S00_AXI_mtestProtection_lite,
 141                                                      S00_AXI_rd_data_lite,
 142                                                      S00_AXI_lite_response);
 143                           $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
 144                           CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
 145                           COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
 146                           $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
 147                           S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
 148                         end
 149
 150                         $display("---------------------------------------------------------");
 151                         $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
 152                                 if ( result_slave_lite ) begin
 153                                         $display("PTGEN_TEST: PASSED!");
 154                                 end     else begin
 155                                         $display("PTGEN_TEST: FAILED!");
 156                                 end
 157                         $display("---------------------------------------------------------");
 158                 end
 159         endtask
 160
 161         // Create the test vectors
 162         initial begin
 163                 // When performing debug enable all levels of INFO messages.
 164                 wait(tb_ARESETn === 0) @(posedge tb_ACLK);
 165                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 166                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 167                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 168                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 169
 170                 dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
 171
 172                 // Create test data vectors
 173                 S00_AXI_test_data_lite[0] = 32'h0101FFFF;
 174                 S00_AXI_test_data_lite[1] = 32'habcd0001;
 175                 S00_AXI_test_data_lite[2] = 32'hdead0011;
 176                 S00_AXI_test_data_lite[3] = 32'hbeef0011;
 177         end
 178
 179         // Drive the BFM
 180         initial begin
 181                 // Wait for end of reset
 182                 wait(tb_ARESETn === 0) @(posedge tb_ACLK);
 183                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 184                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 185                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 186                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 187
 188                 S00_AXI_TEST();
 189
 190         end
 191
 192         // Drive the BFM
 193         initial begin
 194                 // Wait for end of reset
 195                 wait(tb_ARESETn === 0) @(posedge tb_ACLK);
 196                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 197                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 198                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 199                 wait(tb_ARESETn === 1) @(posedge tb_ACLK);
 200
 201                 M00_AXI_INIT_AXI_TXN = 1'b0;
 202                 #500 M00_AXI_INIT_AXI_TXN = 1'b1;
 203
 204                 $display("EXAMPLE TEST M00_AXI:");
 205                 wait( M00_AXI_TXN_DONE == 1'b1);
 206                 $display("M00_AXI: PTGEN_TEST_FINISHED!");
 207                 if ( M00_AXI_ERROR ) begin
 208                   $display("PTGEN_TEST: FAILED!");
 209                 end else begin
 210                   $display("PTGEN_TEST: PASSED!");
 211                 end
 212
 213         end
 214
 215 endmodule